2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* Emit a render target cache flush.
60 * This isn't documented anywhere in the PRM. However, it seems to be
61 * necessary prior to changing the surface state base adress. Without
62 * this, we get GPU hangs when using multi-level command buffers which
63 * clear depth, reset state base address, and then go render stuff.
65 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
66 pc
.DCFlushEnable
= true;
67 pc
.RenderTargetCacheFlushEnable
= true;
68 pc
.CommandStreamerStallEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
150 pc
.ConstantCacheInvalidationEnable
= true;
151 pc
.StateCacheInvalidationEnable
= true;
156 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
157 struct anv_state state
,
158 struct anv_bo
*bo
, uint32_t offset
)
160 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
163 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
164 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
165 if (result
!= VK_SUCCESS
)
166 anv_batch_set_error(&cmd_buffer
->batch
, result
);
170 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
171 const struct anv_image_view
*iview
,
172 enum isl_aux_usage aux_usage
,
173 struct anv_state state
)
175 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
177 add_surface_state_reloc(cmd_buffer
, state
, iview
->bo
, iview
->offset
);
179 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
180 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
182 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
183 * used to store other information. This should be ok, however, because
184 * surface buffer addresses are always 4K page alinged.
186 assert((aux_offset
& 0xfff) == 0);
187 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
188 aux_offset
+= *aux_addr_dw
& 0xfff;
191 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
192 &cmd_buffer
->pool
->alloc
,
193 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
194 iview
->bo
, aux_offset
);
195 if (result
!= VK_SUCCESS
)
196 anv_batch_set_error(&cmd_buffer
->batch
, result
);
201 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
203 if (isl_format_has_int_channel(format
)) {
204 for (unsigned i
= 0; i
< 4; i
++) {
205 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
209 for (unsigned i
= 0; i
< 4; i
++) {
210 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
219 color_attachment_compute_aux_usage(struct anv_device
*device
,
220 struct anv_attachment_state
*att_state
,
221 struct anv_image_view
*iview
,
222 VkRect2D render_area
,
223 union isl_color_value
*fast_clear_color
)
225 if (iview
->image
->aux_surface
.isl
.size
== 0) {
226 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
227 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
228 att_state
->fast_clear
= false;
230 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
231 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
232 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
233 att_state
->fast_clear
= false;
237 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
239 att_state
->clear_color_is_zero_one
=
240 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
242 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
243 /* Start off assuming fast clears are possible */
244 att_state
->fast_clear
= true;
246 /* Potentially, we could do partial fast-clears but doing so has crazy
247 * alignment restrictions. It's easier to just restrict to full size
248 * fast clears for now.
250 if (render_area
.offset
.x
!= 0 ||
251 render_area
.offset
.y
!= 0 ||
252 render_area
.extent
.width
!= iview
->extent
.width
||
253 render_area
.extent
.height
!= iview
->extent
.height
)
254 att_state
->fast_clear
= false;
257 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
258 * technically can, but it comes with crazy restrictions that we
259 * don't want to deal with now.
261 if (iview
->isl
.base_level
> 0 ||
262 iview
->isl
.base_array_layer
> 0 ||
263 iview
->isl
.array_len
> 1)
264 att_state
->fast_clear
= false;
267 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
268 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
269 att_state
->fast_clear
= false;
271 if (att_state
->fast_clear
) {
272 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
273 sizeof(fast_clear_color
->u32
));
276 att_state
->fast_clear
= false;
280 * TODO: Consider using a heuristic to determine if temporarily enabling
281 * CCS_E for this image view would be beneficial.
283 * While fast-clear resolves and partial resolves are fairly cheap in the
284 * case where you render to most of the pixels, full resolves are not
285 * because they potentially involve reading and writing the entire
286 * framebuffer. If we can't texture with CCS_E, we should leave it off and
287 * limit ourselves to fast clears.
289 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
290 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
292 } else if (att_state
->fast_clear
) {
293 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
295 !isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
)) {
296 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
298 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
299 * setting is only allowed if Surface Format supported for Fast
300 * Clear. In addition, if the surface is bound to the sampling
301 * engine, Surface Format must be supported for Render Target
302 * Compression for surfaces bound to the sampling engine."
304 * In other words, we can't sample from a fast-cleared image if it
305 * doesn't also support color compression.
307 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
308 } else if (GEN_GEN
== 8) {
309 /* Broadwell can sample from fast-cleared images */
310 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
312 /* Ivy Bridge and Haswell cannot */
313 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
316 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
317 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
322 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
324 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
327 /* We only allocate input attachment states for color surfaces. Compression
328 * is not yet enabled for depth textures and stencil doesn't allow
329 * compression so we can just use the texture surface state from the view.
331 return vk_format_is_color(att
->format
);
334 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
335 * the initial layout is undefined, the HiZ buffer and depth buffer will
336 * represent the same data at the end of this operation.
339 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
340 const struct anv_image
*image
,
341 VkImageLayout initial_layout
,
342 VkImageLayout final_layout
)
346 /* A transition is a no-op if HiZ is not enabled, or if the initial and
347 * final layouts are equal.
349 * The undefined layout indicates that the user doesn't care about the data
350 * that's currently in the buffer. Therefore, a data-preserving resolve
351 * operation is not needed.
353 * The pre-initialized layout is equivalent to the undefined layout for
354 * optimally-tiled images. Anv only exposes support for optimally-tiled
357 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
||
358 initial_layout
== final_layout
||
359 initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
360 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)
363 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
364 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
366 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
367 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
370 enum blorp_hiz_op hiz_op
;
371 if (hiz_enabled
&& !enable_hiz
) {
372 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
373 } else if (!hiz_enabled
&& enable_hiz
) {
374 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
376 assert(hiz_enabled
== enable_hiz
);
377 /* If the same buffer will be used, no resolves are necessary. */
378 hiz_op
= BLORP_HIZ_OP_NONE
;
381 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
382 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
387 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
390 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
391 struct anv_render_pass
*pass
,
392 const VkRenderPassBeginInfo
*begin
)
394 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
395 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
397 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
399 if (pass
->attachment_count
== 0) {
400 state
->attachments
= NULL
;
404 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
405 pass
->attachment_count
*
406 sizeof(state
->attachments
[0]),
407 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
408 if (state
->attachments
== NULL
) {
409 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
410 return anv_batch_set_error(&cmd_buffer
->batch
,
411 VK_ERROR_OUT_OF_HOST_MEMORY
);
414 bool need_null_state
= false;
415 unsigned num_states
= 0;
416 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
417 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
420 /* We need a null state for any depth-stencil-only subpasses.
421 * Importantly, this includes depth/stencil clears so we create one
422 * whenever we have depth or stencil
424 need_null_state
= true;
427 if (need_input_attachment_state(&pass
->attachments
[i
]))
430 num_states
+= need_null_state
;
432 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
433 state
->render_pass_states
=
434 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
435 num_states
* ss_stride
, isl_dev
->ss
.align
);
437 struct anv_state next_state
= state
->render_pass_states
;
438 next_state
.alloc_size
= isl_dev
->ss
.size
;
440 if (need_null_state
) {
441 state
->null_surface_state
= next_state
;
442 next_state
.offset
+= ss_stride
;
443 next_state
.map
+= ss_stride
;
446 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
447 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
448 state
->attachments
[i
].color_rt_state
= next_state
;
449 next_state
.offset
+= ss_stride
;
450 next_state
.map
+= ss_stride
;
453 if (need_input_attachment_state(&pass
->attachments
[i
])) {
454 state
->attachments
[i
].input_att_state
= next_state
;
455 next_state
.offset
+= ss_stride
;
456 next_state
.map
+= ss_stride
;
459 assert(next_state
.offset
== state
->render_pass_states
.offset
+
460 state
->render_pass_states
.alloc_size
);
463 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
464 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
466 if (need_null_state
) {
467 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
468 .SurfaceType
= SURFTYPE_NULL
,
469 .SurfaceArray
= framebuffer
->layers
> 0,
470 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
474 .TiledSurface
= true,
476 .Width
= framebuffer
->width
- 1,
477 .Height
= framebuffer
->height
- 1,
478 .Depth
= framebuffer
->layers
- 1,
479 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
481 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
485 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
486 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
487 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
488 VkImageAspectFlags clear_aspects
= 0;
490 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
491 /* color attachment */
492 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
493 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
496 /* depthstencil attachment */
497 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
498 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
499 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
501 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
502 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
503 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
507 state
->attachments
[i
].current_layout
= att
->initial_layout
;
508 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
510 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
512 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
513 anv_assert(iview
->vk_format
== att
->format
);
515 union isl_color_value clear_color
= { .u32
= { 0, } };
516 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
517 color_attachment_compute_aux_usage(cmd_buffer
->device
,
518 &state
->attachments
[i
],
519 iview
, begin
->renderArea
,
522 struct isl_view view
= iview
->isl
;
523 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
524 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
525 isl_surf_fill_state(isl_dev
,
526 state
->attachments
[i
].color_rt_state
.map
,
527 .surf
= &iview
->image
->color_surface
.isl
,
529 .aux_surf
= &iview
->image
->aux_surface
.isl
,
530 .aux_usage
= state
->attachments
[i
].aux_usage
,
531 .clear_color
= clear_color
,
532 .mocs
= cmd_buffer
->device
->default_mocs
);
534 add_image_view_relocs(cmd_buffer
, iview
,
535 state
->attachments
[i
].aux_usage
,
536 state
->attachments
[i
].color_rt_state
);
538 /* This field will be initialized after the first subpass
541 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
543 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
546 if (need_input_attachment_state(&pass
->attachments
[i
])) {
547 struct isl_view view
= iview
->isl
;
548 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
549 isl_surf_fill_state(isl_dev
,
550 state
->attachments
[i
].input_att_state
.map
,
551 .surf
= &iview
->image
->color_surface
.isl
,
553 .aux_surf
= &iview
->image
->aux_surface
.isl
,
554 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
555 .clear_color
= clear_color
,
556 .mocs
= cmd_buffer
->device
->default_mocs
);
558 add_image_view_relocs(cmd_buffer
, iview
,
559 state
->attachments
[i
].input_aux_usage
,
560 state
->attachments
[i
].input_att_state
);
564 anv_state_flush(cmd_buffer
->device
, state
->render_pass_states
);
571 genX(BeginCommandBuffer
)(
572 VkCommandBuffer commandBuffer
,
573 const VkCommandBufferBeginInfo
* pBeginInfo
)
575 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
577 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
578 * command buffer's state. Otherwise, we must *reset* its state. In both
581 * From the Vulkan 1.0 spec:
583 * If a command buffer is in the executable state and the command buffer
584 * was allocated from a command pool with the
585 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
586 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
587 * as if vkResetCommandBuffer had been called with
588 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
589 * the command buffer in the recording state.
591 anv_cmd_buffer_reset(cmd_buffer
);
593 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
595 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
596 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
598 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
600 VkResult result
= VK_SUCCESS
;
601 if (cmd_buffer
->usage_flags
&
602 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
603 cmd_buffer
->state
.pass
=
604 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
605 cmd_buffer
->state
.subpass
=
606 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
607 cmd_buffer
->state
.framebuffer
= NULL
;
609 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
610 cmd_buffer
->state
.pass
, NULL
);
612 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
619 genX(EndCommandBuffer
)(
620 VkCommandBuffer commandBuffer
)
622 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
624 if (anv_batch_has_error(&cmd_buffer
->batch
))
625 return cmd_buffer
->batch
.status
;
627 /* We want every command buffer to start with the PMA fix in a known state,
628 * so we disable it at the end of the command buffer.
630 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
632 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
634 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
640 genX(CmdExecuteCommands
)(
641 VkCommandBuffer commandBuffer
,
642 uint32_t commandBufferCount
,
643 const VkCommandBuffer
* pCmdBuffers
)
645 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
647 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
649 /* The secondary command buffers will assume that the PMA fix is disabled
650 * when they begin executing. Make sure this is true.
652 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
654 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
655 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
657 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
659 if (secondary
->usage_flags
&
660 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
661 /* If we're continuing a render pass from the primary, we need to
662 * copy the surface states for the current subpass into the storage
663 * we allocated for them in BeginCommandBuffer.
665 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
666 struct anv_state src_state
= primary
->state
.render_pass_states
;
667 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
668 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
670 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
671 ss_bo
, src_state
.offset
,
672 src_state
.alloc_size
);
675 anv_cmd_buffer_add_secondary(primary
, secondary
);
678 /* Each of the secondary command buffers will use its own state base
679 * address. We need to re-emit state base address for the primary after
680 * all of the secondaries are done.
682 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
685 genX(cmd_buffer_emit_state_base_address
)(primary
);
688 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
689 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
690 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
693 * Program the hardware to use the specified L3 configuration.
696 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
697 const struct gen_l3_config
*cfg
)
700 if (cfg
== cmd_buffer
->state
.current_l3_config
)
703 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
704 fprintf(stderr
, "L3 config transition: ");
705 gen_dump_l3_config(cfg
, stderr
);
708 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
710 /* According to the hardware docs, the L3 partitioning can only be changed
711 * while the pipeline is completely drained and the caches are flushed,
712 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
714 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
715 pc
.DCFlushEnable
= true;
716 pc
.PostSyncOperation
= NoWrite
;
717 pc
.CommandStreamerStallEnable
= true;
720 /* ...followed by a second pipelined PIPE_CONTROL that initiates
721 * invalidation of the relevant caches. Note that because RO invalidation
722 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
723 * command is processed by the CS) we cannot combine it with the previous
724 * stalling flush as the hardware documentation suggests, because that
725 * would cause the CS to stall on previous rendering *after* RO
726 * invalidation and wouldn't prevent the RO caches from being polluted by
727 * concurrent rendering before the stall completes. This intentionally
728 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
729 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
730 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
731 * already guarantee that there is no concurrent GPGPU kernel execution
732 * (see SKL HSD 2132585).
734 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
735 pc
.TextureCacheInvalidationEnable
= true;
736 pc
.ConstantCacheInvalidationEnable
= true;
737 pc
.InstructionCacheInvalidateEnable
= true;
738 pc
.StateCacheInvalidationEnable
= true;
739 pc
.PostSyncOperation
= NoWrite
;
742 /* Now send a third stalling flush to make sure that invalidation is
743 * complete when the L3 configuration registers are modified.
745 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
746 pc
.DCFlushEnable
= true;
747 pc
.PostSyncOperation
= NoWrite
;
748 pc
.CommandStreamerStallEnable
= true;
753 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
756 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
757 .SLMEnable
= has_slm
,
758 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
759 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
760 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
761 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
763 /* Set up the L3 partitioning. */
764 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
768 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
769 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
771 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
773 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
776 assert(!cfg
->n
[GEN_L3P_ALL
]);
778 /* When enabled SLM only uses a portion of the L3 on half of the banks,
779 * the matching space on the remaining banks has to be allocated to a
780 * client (URB for all validated configurations) set to the
781 * lower-bandwidth 2-bank address hashing mode.
783 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
784 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
785 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
787 /* Minimum number of ways that can be allocated to the URB. */
788 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
789 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
791 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
792 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
793 .ConvertDC_UC
= !has_dc
,
794 .ConvertIS_UC
= !has_is
,
795 .ConvertC_UC
= !has_c
,
796 .ConvertT_UC
= !has_t
);
798 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
799 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
800 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
802 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
803 .SLMEnable
= has_slm
,
804 .URBLowBandwidth
= urb_low_bw
,
805 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
807 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
809 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
810 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
812 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
813 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
815 .CAllocation
= cfg
->n
[GEN_L3P_C
],
817 .TAllocation
= cfg
->n
[GEN_L3P_T
],
820 /* Set up the L3 partitioning. */
821 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
822 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
823 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
826 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
827 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
828 * them disabled to avoid crashing the system hard.
830 uint32_t scratch1
, chicken3
;
831 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
832 .L3AtomicDisable
= !has_dc
);
833 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
834 .L3AtomicDisableMask
= true,
835 .L3AtomicDisable
= !has_dc
);
836 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
837 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
843 cmd_buffer
->state
.current_l3_config
= cfg
;
847 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
849 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
851 /* Flushes are pipelined while invalidations are handled immediately.
852 * Therefore, if we're flushing anything then we need to schedule a stall
853 * before any invalidations can happen.
855 if (bits
& ANV_PIPE_FLUSH_BITS
)
856 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
858 /* If we're going to do an invalidate and we have a pending CS stall that
859 * has yet to be resolved, we do the CS stall now.
861 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
862 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
863 bits
|= ANV_PIPE_CS_STALL_BIT
;
864 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
867 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
868 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
869 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
870 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
871 pipe
.RenderTargetCacheFlushEnable
=
872 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
874 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
875 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
876 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
879 * According to the Broadwell documentation, any PIPE_CONTROL with the
880 * "Command Streamer Stall" bit set must also have another bit set,
881 * with five different options:
883 * - Render Target Cache Flush
884 * - Depth Cache Flush
885 * - Stall at Pixel Scoreboard
886 * - Post-Sync Operation
890 * I chose "Stall at Pixel Scoreboard" since that's what we use in
891 * mesa and it seems to work fine. The choice is fairly arbitrary.
893 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
894 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
895 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
896 pipe
.StallAtPixelScoreboard
= true;
899 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
902 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
903 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
904 pipe
.StateCacheInvalidationEnable
=
905 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
906 pipe
.ConstantCacheInvalidationEnable
=
907 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
908 pipe
.VFCacheInvalidationEnable
=
909 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
910 pipe
.TextureCacheInvalidationEnable
=
911 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
912 pipe
.InstructionCacheInvalidateEnable
=
913 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
916 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
919 cmd_buffer
->state
.pending_pipe_bits
= bits
;
922 void genX(CmdPipelineBarrier
)(
923 VkCommandBuffer commandBuffer
,
924 VkPipelineStageFlags srcStageMask
,
925 VkPipelineStageFlags destStageMask
,
927 uint32_t memoryBarrierCount
,
928 const VkMemoryBarrier
* pMemoryBarriers
,
929 uint32_t bufferMemoryBarrierCount
,
930 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
931 uint32_t imageMemoryBarrierCount
,
932 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
934 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
937 /* XXX: Right now, we're really dumb and just flush whatever categories
938 * the app asks for. One of these days we may make this a bit better
939 * but right now that's all the hardware allows for in most areas.
941 VkAccessFlags src_flags
= 0;
942 VkAccessFlags dst_flags
= 0;
944 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
945 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
946 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
949 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
950 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
951 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
954 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
955 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
956 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
957 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
958 if (pImageMemoryBarriers
[i
].subresourceRange
.aspectMask
&
959 VK_IMAGE_ASPECT_DEPTH_BIT
) {
960 transition_depth_buffer(cmd_buffer
, image
,
961 pImageMemoryBarriers
[i
].oldLayout
,
962 pImageMemoryBarriers
[i
].newLayout
);
966 enum anv_pipe_bits pipe_bits
= 0;
968 for_each_bit(b
, src_flags
) {
969 switch ((VkAccessFlagBits
)(1 << b
)) {
970 case VK_ACCESS_SHADER_WRITE_BIT
:
971 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
973 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
974 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
976 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
977 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
979 case VK_ACCESS_TRANSFER_WRITE_BIT
:
980 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
981 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
984 break; /* Nothing to do */
988 for_each_bit(b
, dst_flags
) {
989 switch ((VkAccessFlagBits
)(1 << b
)) {
990 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
991 case VK_ACCESS_INDEX_READ_BIT
:
992 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
993 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
995 case VK_ACCESS_UNIFORM_READ_BIT
:
996 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
997 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
999 case VK_ACCESS_SHADER_READ_BIT
:
1000 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1001 case VK_ACCESS_TRANSFER_READ_BIT
:
1002 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1005 break; /* Nothing to do */
1009 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
1013 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1015 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1017 /* In order to avoid thrash, we assume that vertex and fragment stages
1018 * always exist. In the rare case where one is missing *and* the other
1019 * uses push concstants, this may be suboptimal. However, avoiding stalls
1020 * seems more important.
1022 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1024 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1028 const unsigned push_constant_kb
= 32;
1029 #elif GEN_IS_HASWELL
1030 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1032 const unsigned push_constant_kb
= 16;
1035 const unsigned num_stages
=
1036 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1037 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1039 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1040 * units of 2KB. Incidentally, these are the same platforms that have
1041 * 32KB worth of push constant space.
1043 if (push_constant_kb
== 32)
1044 size_per_stage
&= ~1u;
1046 uint32_t kb_used
= 0;
1047 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1048 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1049 anv_batch_emit(&cmd_buffer
->batch
,
1050 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1051 alloc
._3DCommandSubOpcode
= 18 + i
;
1052 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1053 alloc
.ConstantBufferSize
= push_size
;
1055 kb_used
+= push_size
;
1058 anv_batch_emit(&cmd_buffer
->batch
,
1059 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1060 alloc
.ConstantBufferOffset
= kb_used
;
1061 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1064 cmd_buffer
->state
.push_constant_stages
= stages
;
1066 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1068 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1069 * the next 3DPRIMITIVE command after programming the
1070 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1072 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1073 * pipeline setup, we need to dirty push constants.
1075 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1079 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1080 gl_shader_stage stage
,
1081 struct anv_state
*bt_state
)
1083 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1084 struct anv_pipeline
*pipeline
;
1085 uint32_t bias
, state_offset
;
1088 case MESA_SHADER_COMPUTE
:
1089 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1093 pipeline
= cmd_buffer
->state
.pipeline
;
1098 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1099 *bt_state
= (struct anv_state
) { 0, };
1103 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1104 if (bias
+ map
->surface_count
== 0) {
1105 *bt_state
= (struct anv_state
) { 0, };
1109 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1110 bias
+ map
->surface_count
,
1112 uint32_t *bt_map
= bt_state
->map
;
1114 if (bt_state
->map
== NULL
)
1115 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1117 if (stage
== MESA_SHADER_COMPUTE
&&
1118 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1119 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1120 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1122 struct anv_state surface_state
;
1124 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1126 const enum isl_format format
=
1127 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1128 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1129 format
, bo_offset
, 12, 1);
1131 bt_map
[0] = surface_state
.offset
+ state_offset
;
1132 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1135 if (map
->surface_count
== 0)
1138 if (map
->image_count
> 0) {
1140 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1141 if (result
!= VK_SUCCESS
)
1144 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1148 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1149 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1151 struct anv_state surface_state
;
1153 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1154 /* Color attachment binding */
1155 assert(stage
== MESA_SHADER_FRAGMENT
);
1156 assert(binding
->binding
== 0);
1157 if (binding
->index
< subpass
->color_count
) {
1158 const unsigned att
= subpass
->color_attachments
[binding
->index
].attachment
;
1159 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1161 surface_state
= cmd_buffer
->state
.null_surface_state
;
1164 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1168 struct anv_descriptor_set
*set
=
1169 cmd_buffer
->state
.descriptors
[binding
->set
];
1170 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1171 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1173 switch (desc
->type
) {
1174 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1175 /* Nothing for us to do here */
1178 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1179 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1180 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1181 desc
->image_view
->no_aux_sampler_surface_state
:
1182 desc
->image_view
->sampler_surface_state
;
1183 assert(surface_state
.alloc_size
);
1184 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1185 desc
->aux_usage
, surface_state
);
1187 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1188 assert(stage
== MESA_SHADER_FRAGMENT
);
1189 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1190 /* For depth and stencil input attachments, we treat it like any
1191 * old texture that a user may have bound.
1193 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1194 desc
->image_view
->no_aux_sampler_surface_state
:
1195 desc
->image_view
->sampler_surface_state
;
1196 assert(surface_state
.alloc_size
);
1197 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1198 desc
->aux_usage
, surface_state
);
1200 /* For color input attachments, we create the surface state at
1201 * vkBeginRenderPass time so that we can include aux and clear
1202 * color information.
1204 assert(binding
->input_attachment_index
< subpass
->input_count
);
1205 const unsigned subpass_att
= binding
->input_attachment_index
;
1206 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1207 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1211 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1212 surface_state
= (binding
->write_only
)
1213 ? desc
->image_view
->writeonly_storage_surface_state
1214 : desc
->image_view
->storage_surface_state
;
1215 assert(surface_state
.alloc_size
);
1216 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1217 desc
->image_view
->image
->aux_usage
,
1220 struct brw_image_param
*image_param
=
1221 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1223 *image_param
= desc
->image_view
->storage_image_param
;
1224 image_param
->surface_idx
= bias
+ s
;
1228 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1229 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1230 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1231 surface_state
= desc
->buffer_view
->surface_state
;
1232 assert(surface_state
.alloc_size
);
1233 add_surface_state_reloc(cmd_buffer
, surface_state
,
1234 desc
->buffer_view
->bo
,
1235 desc
->buffer_view
->offset
);
1238 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1239 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1240 uint32_t dynamic_offset_idx
=
1241 pipeline
->layout
->set
[binding
->set
].dynamic_offset_start
+
1242 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1245 /* Compute the offset within the buffer */
1246 uint64_t offset
= desc
->offset
+
1247 cmd_buffer
->state
.dynamic_offsets
[dynamic_offset_idx
];
1248 /* Clamp to the buffer size */
1249 offset
= MIN2(offset
, desc
->buffer
->size
);
1250 /* Clamp the range to the buffer size */
1251 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1254 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1255 enum isl_format format
=
1256 anv_isl_format_for_descriptor_type(desc
->type
);
1258 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1259 format
, offset
, range
, 1);
1260 add_surface_state_reloc(cmd_buffer
, surface_state
,
1262 desc
->buffer
->offset
+ offset
);
1266 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1267 surface_state
= (binding
->write_only
)
1268 ? desc
->buffer_view
->writeonly_storage_surface_state
1269 : desc
->buffer_view
->storage_surface_state
;
1270 assert(surface_state
.alloc_size
);
1271 add_surface_state_reloc(cmd_buffer
, surface_state
,
1272 desc
->buffer_view
->bo
,
1273 desc
->buffer_view
->offset
);
1275 struct brw_image_param
*image_param
=
1276 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1278 *image_param
= desc
->buffer_view
->storage_image_param
;
1279 image_param
->surface_idx
= bias
+ s
;
1283 assert(!"Invalid descriptor type");
1287 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1289 assert(image
== map
->image_count
);
1292 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1298 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1299 gl_shader_stage stage
,
1300 struct anv_state
*state
)
1302 struct anv_pipeline
*pipeline
;
1304 if (stage
== MESA_SHADER_COMPUTE
)
1305 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1307 pipeline
= cmd_buffer
->state
.pipeline
;
1309 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1310 *state
= (struct anv_state
) { 0, };
1314 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1315 if (map
->sampler_count
== 0) {
1316 *state
= (struct anv_state
) { 0, };
1320 uint32_t size
= map
->sampler_count
* 16;
1321 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1323 if (state
->map
== NULL
)
1324 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1326 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1327 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1328 struct anv_descriptor_set
*set
=
1329 cmd_buffer
->state
.descriptors
[binding
->set
];
1330 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1331 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1333 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1334 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1337 struct anv_sampler
*sampler
= desc
->sampler
;
1339 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1340 * happens to be zero.
1342 if (sampler
== NULL
)
1345 memcpy(state
->map
+ (s
* 16),
1346 sampler
->state
, sizeof(sampler
->state
));
1349 anv_state_flush(cmd_buffer
->device
, *state
);
1355 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1357 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1358 cmd_buffer
->state
.pipeline
->active_stages
;
1360 VkResult result
= VK_SUCCESS
;
1361 anv_foreach_stage(s
, dirty
) {
1362 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1363 if (result
!= VK_SUCCESS
)
1365 result
= emit_binding_table(cmd_buffer
, s
,
1366 &cmd_buffer
->state
.binding_tables
[s
]);
1367 if (result
!= VK_SUCCESS
)
1371 if (result
!= VK_SUCCESS
) {
1372 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1374 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1375 assert(result
== VK_SUCCESS
);
1377 /* Re-emit state base addresses so we get the new surface state base
1378 * address before we start emitting binding tables etc.
1380 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1382 /* Re-emit all active binding tables */
1383 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1384 anv_foreach_stage(s
, dirty
) {
1385 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1386 if (result
!= VK_SUCCESS
)
1388 result
= emit_binding_table(cmd_buffer
, s
,
1389 &cmd_buffer
->state
.binding_tables
[s
]);
1390 if (result
!= VK_SUCCESS
)
1395 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1401 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1404 static const uint32_t sampler_state_opcodes
[] = {
1405 [MESA_SHADER_VERTEX
] = 43,
1406 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1407 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1408 [MESA_SHADER_GEOMETRY
] = 46,
1409 [MESA_SHADER_FRAGMENT
] = 47,
1410 [MESA_SHADER_COMPUTE
] = 0,
1413 static const uint32_t binding_table_opcodes
[] = {
1414 [MESA_SHADER_VERTEX
] = 38,
1415 [MESA_SHADER_TESS_CTRL
] = 39,
1416 [MESA_SHADER_TESS_EVAL
] = 40,
1417 [MESA_SHADER_GEOMETRY
] = 41,
1418 [MESA_SHADER_FRAGMENT
] = 42,
1419 [MESA_SHADER_COMPUTE
] = 0,
1422 anv_foreach_stage(s
, stages
) {
1423 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1424 anv_batch_emit(&cmd_buffer
->batch
,
1425 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1426 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1427 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1431 /* Always emit binding table pointers if we're asked to, since on SKL
1432 * this is what flushes push constants. */
1433 anv_batch_emit(&cmd_buffer
->batch
,
1434 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1435 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1436 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1442 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1444 static const uint32_t push_constant_opcodes
[] = {
1445 [MESA_SHADER_VERTEX
] = 21,
1446 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1447 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1448 [MESA_SHADER_GEOMETRY
] = 22,
1449 [MESA_SHADER_FRAGMENT
] = 23,
1450 [MESA_SHADER_COMPUTE
] = 0,
1453 VkShaderStageFlags flushed
= 0;
1455 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1456 if (stage
== MESA_SHADER_COMPUTE
)
1459 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1461 if (state
.offset
== 0) {
1462 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1463 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1465 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1466 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1467 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1469 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1470 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1472 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1473 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1479 flushed
|= mesa_to_vk_shader_stage(stage
);
1482 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1488 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1490 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1493 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1495 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1497 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1499 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1502 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1503 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1505 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1506 GENX(3DSTATE_VERTEX_BUFFERS
));
1508 for_each_bit(vb
, vb_emit
) {
1509 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1510 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1512 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1513 .VertexBufferIndex
= vb
,
1516 .MemoryObjectControlState
= GENX(MOCS
),
1518 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1519 .InstanceDataStepRate
= 1,
1520 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1523 .AddressModifyEnable
= true,
1524 .BufferPitch
= pipeline
->binding_stride
[vb
],
1525 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1528 .BufferSize
= buffer
->size
- offset
1530 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1534 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1539 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1541 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1542 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1544 /* The exact descriptor layout is pulled from the pipeline, so we need
1545 * to re-emit binding tables on every pipeline change.
1547 cmd_buffer
->state
.descriptors_dirty
|=
1548 cmd_buffer
->state
.pipeline
->active_stages
;
1550 /* If the pipeline changed, we may need to re-allocate push constant
1553 cmd_buffer_alloc_push_constants(cmd_buffer
);
1557 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1558 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1559 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1561 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1562 * stall needs to be sent just prior to any 3DSTATE_VS,
1563 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1564 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1565 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1566 * PIPE_CONTROL needs to be sent before any combination of VS
1567 * associated 3DSTATE."
1569 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1570 pc
.DepthStallEnable
= true;
1571 pc
.PostSyncOperation
= WriteImmediateData
;
1573 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1578 /* Render targets live in the same binding table as fragment descriptors */
1579 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1580 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1582 /* We emit the binding tables and sampler tables first, then emit push
1583 * constants and then finally emit binding table and sampler table
1584 * pointers. It has to happen in this order, since emitting the binding
1585 * tables may change the push constants (in case of storage images). After
1586 * emitting push constants, on SKL+ we have to emit the corresponding
1587 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1590 if (cmd_buffer
->state
.descriptors_dirty
)
1591 dirty
= flush_descriptor_sets(cmd_buffer
);
1593 if (cmd_buffer
->state
.push_constants_dirty
) {
1595 /* On Sky Lake and later, the binding table pointers commands are
1596 * what actually flush the changes to push constant state so we need
1597 * to dirty them so they get re-emitted below.
1599 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1601 cmd_buffer_flush_push_constants(cmd_buffer
);
1606 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1608 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1609 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1611 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1612 ANV_CMD_DIRTY_PIPELINE
)) {
1613 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1614 pipeline
->depth_clamp_enable
);
1617 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1618 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1620 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1622 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1626 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
1627 struct anv_bo
*bo
, uint32_t offset
,
1628 uint32_t size
, uint32_t index
)
1630 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1631 GENX(3DSTATE_VERTEX_BUFFERS
));
1633 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1634 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1635 .VertexBufferIndex
= index
,
1636 .AddressModifyEnable
= true,
1639 .MemoryObjectControlState
= GENX(MOCS
),
1640 .BufferStartingAddress
= { bo
, offset
},
1643 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1644 .BufferStartingAddress
= { bo
, offset
},
1645 .EndAddress
= { bo
, offset
+ size
},
1651 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1652 struct anv_bo
*bo
, uint32_t offset
)
1654 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
1658 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1659 uint32_t base_vertex
, uint32_t base_instance
)
1661 struct anv_state id_state
=
1662 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1664 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1665 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1667 anv_state_flush(cmd_buffer
->device
, id_state
);
1669 emit_base_vertex_instance_bo(cmd_buffer
,
1670 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1674 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
1676 struct anv_state state
=
1677 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
1679 ((uint32_t *)state
.map
)[0] = draw_index
;
1681 anv_state_flush(cmd_buffer
->device
, state
);
1683 emit_vertex_bo(cmd_buffer
,
1684 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
1685 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
1689 VkCommandBuffer commandBuffer
,
1690 uint32_t vertexCount
,
1691 uint32_t instanceCount
,
1692 uint32_t firstVertex
,
1693 uint32_t firstInstance
)
1695 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1696 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1697 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1699 if (anv_batch_has_error(&cmd_buffer
->batch
))
1702 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1704 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1705 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1706 if (vs_prog_data
->uses_drawid
)
1707 emit_draw_index(cmd_buffer
, 0);
1709 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1710 prim
.VertexAccessType
= SEQUENTIAL
;
1711 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1712 prim
.VertexCountPerInstance
= vertexCount
;
1713 prim
.StartVertexLocation
= firstVertex
;
1714 prim
.InstanceCount
= instanceCount
;
1715 prim
.StartInstanceLocation
= firstInstance
;
1716 prim
.BaseVertexLocation
= 0;
1720 void genX(CmdDrawIndexed
)(
1721 VkCommandBuffer commandBuffer
,
1722 uint32_t indexCount
,
1723 uint32_t instanceCount
,
1724 uint32_t firstIndex
,
1725 int32_t vertexOffset
,
1726 uint32_t firstInstance
)
1728 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1729 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1730 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1732 if (anv_batch_has_error(&cmd_buffer
->batch
))
1735 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1737 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1738 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1739 if (vs_prog_data
->uses_drawid
)
1740 emit_draw_index(cmd_buffer
, 0);
1742 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1743 prim
.VertexAccessType
= RANDOM
;
1744 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1745 prim
.VertexCountPerInstance
= indexCount
;
1746 prim
.StartVertexLocation
= firstIndex
;
1747 prim
.InstanceCount
= instanceCount
;
1748 prim
.StartInstanceLocation
= firstInstance
;
1749 prim
.BaseVertexLocation
= vertexOffset
;
1753 /* Auto-Draw / Indirect Registers */
1754 #define GEN7_3DPRIM_END_OFFSET 0x2420
1755 #define GEN7_3DPRIM_START_VERTEX 0x2430
1756 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1757 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1758 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1759 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1761 void genX(CmdDrawIndirect
)(
1762 VkCommandBuffer commandBuffer
,
1764 VkDeviceSize offset
,
1768 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1769 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1770 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1771 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1772 struct anv_bo
*bo
= buffer
->bo
;
1773 uint32_t bo_offset
= buffer
->offset
+ offset
;
1775 if (anv_batch_has_error(&cmd_buffer
->batch
))
1778 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1780 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1781 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1782 if (vs_prog_data
->uses_drawid
)
1783 emit_draw_index(cmd_buffer
, 0);
1785 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1786 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1787 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1788 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1789 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1791 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1792 prim
.IndirectParameterEnable
= true;
1793 prim
.VertexAccessType
= SEQUENTIAL
;
1794 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1798 void genX(CmdDrawIndexedIndirect
)(
1799 VkCommandBuffer commandBuffer
,
1801 VkDeviceSize offset
,
1805 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1806 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1807 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1808 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1809 struct anv_bo
*bo
= buffer
->bo
;
1810 uint32_t bo_offset
= buffer
->offset
+ offset
;
1812 if (anv_batch_has_error(&cmd_buffer
->batch
))
1815 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1817 /* TODO: We need to stomp base vertex to 0 somehow */
1818 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1819 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1820 if (vs_prog_data
->uses_drawid
)
1821 emit_draw_index(cmd_buffer
, 0);
1823 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1824 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1825 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1826 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1827 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1829 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1830 prim
.IndirectParameterEnable
= true;
1831 prim
.VertexAccessType
= RANDOM
;
1832 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1837 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1839 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1840 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1843 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1844 if (result
!= VK_SUCCESS
) {
1845 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1846 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1847 assert(result
== VK_SUCCESS
);
1849 /* Re-emit state base addresses so we get the new surface state base
1850 * address before we start emitting binding tables etc.
1852 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1854 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1855 assert(result
== VK_SUCCESS
);
1858 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1859 assert(result
== VK_SUCCESS
);
1861 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1862 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1863 .BindingTablePointer
= surfaces
.offset
,
1864 .SamplerStatePointer
= samplers
.offset
,
1866 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1868 struct anv_state state
=
1869 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1870 pipeline
->interface_descriptor_data
,
1871 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1874 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1875 anv_batch_emit(&cmd_buffer
->batch
,
1876 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1877 mid
.InterfaceDescriptorTotalLength
= size
;
1878 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1885 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1887 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1888 MAYBE_UNUSED VkResult result
;
1890 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1892 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1894 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1896 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1897 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1899 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1900 * the only bits that are changed are scoreboard related: Scoreboard
1901 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1902 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1905 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1906 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1908 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1911 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1912 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1913 /* FIXME: figure out descriptors for gen7 */
1914 result
= flush_compute_descriptor_set(cmd_buffer
);
1915 assert(result
== VK_SUCCESS
);
1916 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1919 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1920 struct anv_state push_state
=
1921 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1923 if (push_state
.alloc_size
) {
1924 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1925 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1926 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1931 cmd_buffer
->state
.compute_dirty
= 0;
1933 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1939 verify_cmd_parser(const struct anv_device
*device
,
1940 int required_version
,
1941 const char *function
)
1943 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1944 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1945 "cmd parser version %d is required for %s",
1946 required_version
, function
);
1954 void genX(CmdDispatch
)(
1955 VkCommandBuffer commandBuffer
,
1960 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1961 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1962 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1964 if (anv_batch_has_error(&cmd_buffer
->batch
))
1967 if (prog_data
->uses_num_work_groups
) {
1968 struct anv_state state
=
1969 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1970 uint32_t *sizes
= state
.map
;
1974 anv_state_flush(cmd_buffer
->device
, state
);
1975 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1976 cmd_buffer
->state
.num_workgroups_bo
=
1977 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1980 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1982 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1983 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1984 ggw
.ThreadDepthCounterMaximum
= 0;
1985 ggw
.ThreadHeightCounterMaximum
= 0;
1986 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1987 ggw
.ThreadGroupIDXDimension
= x
;
1988 ggw
.ThreadGroupIDYDimension
= y
;
1989 ggw
.ThreadGroupIDZDimension
= z
;
1990 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1991 ggw
.BottomExecutionMask
= 0xffffffff;
1994 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1997 #define GPGPU_DISPATCHDIMX 0x2500
1998 #define GPGPU_DISPATCHDIMY 0x2504
1999 #define GPGPU_DISPATCHDIMZ 0x2508
2001 #define MI_PREDICATE_SRC0 0x2400
2002 #define MI_PREDICATE_SRC1 0x2408
2004 void genX(CmdDispatchIndirect
)(
2005 VkCommandBuffer commandBuffer
,
2007 VkDeviceSize offset
)
2009 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2010 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2011 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
2012 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
2013 struct anv_bo
*bo
= buffer
->bo
;
2014 uint32_t bo_offset
= buffer
->offset
+ offset
;
2015 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2018 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2019 * indirect dispatch registers to be written.
2021 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2022 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2026 if (prog_data
->uses_num_work_groups
) {
2027 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
2028 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2031 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2033 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2034 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2035 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2038 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2039 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2040 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2041 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2043 /* Load compute_dispatch_indirect_x_size into SRC0 */
2044 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2046 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2047 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2048 mip
.LoadOperation
= LOAD_LOAD
;
2049 mip
.CombineOperation
= COMBINE_SET
;
2050 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2053 /* Load compute_dispatch_indirect_y_size into SRC0 */
2054 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2056 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2057 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2058 mip
.LoadOperation
= LOAD_LOAD
;
2059 mip
.CombineOperation
= COMBINE_OR
;
2060 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2063 /* Load compute_dispatch_indirect_z_size into SRC0 */
2064 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2066 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2067 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2068 mip
.LoadOperation
= LOAD_LOAD
;
2069 mip
.CombineOperation
= COMBINE_OR
;
2070 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2073 /* predicate = !predicate; */
2074 #define COMPARE_FALSE 1
2075 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2076 mip
.LoadOperation
= LOAD_LOADINV
;
2077 mip
.CombineOperation
= COMBINE_OR
;
2078 mip
.CompareOperation
= COMPARE_FALSE
;
2082 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2083 ggw
.IndirectParameterEnable
= true;
2084 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2085 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2086 ggw
.ThreadDepthCounterMaximum
= 0;
2087 ggw
.ThreadHeightCounterMaximum
= 0;
2088 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2089 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2090 ggw
.BottomExecutionMask
= 0xffffffff;
2093 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2097 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
2100 #if GEN_GEN >= 8 && GEN_GEN < 10
2101 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2103 * Software must clear the COLOR_CALC_STATE Valid field in
2104 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2105 * with Pipeline Select set to GPGPU.
2107 * The internal hardware docs recommend the same workaround for Gen9
2110 if (pipeline
== GPGPU
)
2111 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2113 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2114 * PIPELINE_SELECT [DevBWR+]":
2118 * Software must ensure all the write caches are flushed through a
2119 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2120 * command to invalidate read only caches prior to programming
2121 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2123 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2124 pc
.RenderTargetCacheFlushEnable
= true;
2125 pc
.DepthCacheFlushEnable
= true;
2126 pc
.DCFlushEnable
= true;
2127 pc
.PostSyncOperation
= NoWrite
;
2128 pc
.CommandStreamerStallEnable
= true;
2131 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2132 pc
.TextureCacheInvalidationEnable
= true;
2133 pc
.ConstantCacheInvalidationEnable
= true;
2134 pc
.StateCacheInvalidationEnable
= true;
2135 pc
.InstructionCacheInvalidateEnable
= true;
2136 pc
.PostSyncOperation
= NoWrite
;
2142 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2144 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
2145 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
2147 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2151 ps
.PipelineSelection
= _3D
;
2154 cmd_buffer
->state
.current_pipeline
= _3D
;
2159 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2161 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
2162 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
2164 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2168 ps
.PipelineSelection
= GPGPU
;
2171 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2176 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2181 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2183 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2184 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2185 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2186 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2187 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2188 * Depth Flush Bit set, followed by another pipelined depth stall
2189 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2190 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2191 * via a preceding MI_FLUSH)."
2193 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2194 pipe
.DepthStallEnable
= true;
2196 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2197 pipe
.DepthCacheFlushEnable
= true;
2199 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2200 pipe
.DepthStallEnable
= true;
2205 depth_stencil_surface_type(enum isl_surf_dim dim
)
2208 case ISL_SURF_DIM_1D
:
2210 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2212 * Programming Notes:
2213 * The Surface Type of the depth buffer must be the same as the
2214 * Surface Type of the render target(s) (defined in
2215 * SURFACE_STATE), unless either the depth buffer or render
2216 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2217 * surface type not allowed for depth surface and stencil surface.
2220 * If depth/stencil is enabled with 1D render target,
2221 * depth/stencil surface type needs to be set to 2D surface type
2222 * and height set to 1. Depth will use (legacy) TileY and stencil
2223 * will use TileW. For this case only, the Surface Type of the
2224 * depth buffer can be 2D while the Surface Type of the render
2225 * target(s) are 1D, representing an exception to a programming
2232 case ISL_SURF_DIM_2D
:
2234 case ISL_SURF_DIM_3D
:
2236 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2237 * they have the exact same layout as 2D arrays on gen9+, so we can
2245 unreachable("Invalid surface dimension");
2250 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2252 struct anv_device
*device
= cmd_buffer
->device
;
2253 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2254 const struct anv_image_view
*iview
=
2255 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2256 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2257 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2258 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2259 const bool has_hiz
= image
!= NULL
&&
2260 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2261 const bool has_stencil
=
2262 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2264 cmd_buffer
->state
.hiz_enabled
= has_hiz
;
2266 /* FIXME: Width and Height are wrong */
2268 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2270 /* Emit 3DSTATE_DEPTH_BUFFER */
2272 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2274 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2275 db
.DepthWriteEnable
= true;
2276 db
.StencilWriteEnable
= has_stencil
;
2277 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2279 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2280 &image
->depth_surface
.isl
);
2282 db
.SurfaceBaseAddress
= (struct anv_address
) {
2284 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2286 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2288 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2289 db
.Height
= image
->extent
.height
- 1;
2290 db
.Width
= image
->extent
.width
- 1;
2291 db
.LOD
= iview
->isl
.base_level
;
2292 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2294 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2296 db
.RenderTargetViewExtent
= iview
->isl
.array_len
- 1;
2300 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2304 /* Even when no depth buffer is present, the hardware requires that
2305 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2307 * If a null depth buffer is bound, the driver must instead bind depth as:
2308 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2309 * 3DSTATE_DEPTH.Width = 1
2310 * 3DSTATE_DEPTH.Height = 1
2311 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2312 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2313 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2314 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2315 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2317 * The PRM is wrong, though. The width and height must be programmed to
2318 * actual framebuffer's width and height, even when neither depth buffer
2319 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2320 * be combined with a stencil buffer so we use D32_FLOAT instead.
2322 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2325 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2327 db
.SurfaceType
= SURFTYPE_2D
;
2329 db
.SurfaceFormat
= D32_FLOAT
;
2330 db
.Width
= MAX2(fb
->width
, 1) - 1;
2331 db
.Height
= MAX2(fb
->height
, 1) - 1;
2332 db
.StencilWriteEnable
= has_stencil
;
2337 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2338 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2339 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2340 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2342 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2345 /* From the SKL PRM Vol2a:
2347 * The interpretation of this field is dependent on Surface Type
2349 * - SURFTYPE_1D: distance in pixels between array slices
2350 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2351 * - SURFTYPE_3D: distance in rows between R - slices
2353 * Unfortunately, the docs aren't 100% accurate here. They fail to
2354 * mention that the 1-D rule only applies to linear 1-D images.
2355 * Since depth and HiZ buffers are always tiled, they are treated as
2356 * 2-D images. Prior to Sky Lake, this field is always in rows.
2359 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2363 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2366 /* Emit 3DSTATE_STENCIL_BUFFER */
2368 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2369 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2370 sb
.StencilBufferEnable
= true;
2372 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2374 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2377 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2379 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2381 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2385 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2388 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2390 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2391 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2392 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2394 * Testing also shows that some variant of this restriction may exist HSW+.
2395 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2396 * both have DepthClearValueValid set. An analysis of such state programming
2397 * on SKL showed that the GPU doesn't register the latter packet's clear
2400 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2402 cp
.DepthClearValueValid
= true;
2403 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2410 * @brief Perform any layout transitions required at the beginning and/or end
2411 * of the current subpass for depth buffers.
2413 * TODO: Consider preprocessing the attachment reference array at render pass
2414 * create time to determine if no layout transition is needed at the
2415 * beginning and/or end of each subpass.
2417 * @param cmd_buffer The command buffer the transition is happening within.
2418 * @param subpass_end If true, marks that the transition is happening at the
2419 * end of the subpass.
2422 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
2423 const bool subpass_end
)
2425 /* We need a non-NULL command buffer. */
2428 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
2429 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
2431 /* This function must be called within a subpass. */
2434 /* If there are attachment references, the array shouldn't be NULL.
2436 if (subpass
->attachment_count
> 0)
2437 assert(subpass
->attachments
);
2439 /* Iterate over the array of attachment references. */
2440 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
2441 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
2443 /* If the attachment is unused, we can't perform a layout transition. */
2444 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
2447 /* This attachment index shouldn't go out of bounds. */
2448 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
2450 const struct anv_render_pass_attachment
* const att_desc
=
2451 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
2452 struct anv_attachment_state
* const att_state
=
2453 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
2455 /* The attachment should not be used in a subpass after its last. */
2456 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
2458 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
2459 att_desc
->last_subpass_idx
) {
2460 /* We're calling this function on a buffer twice in one subpass and
2461 * this is not the last use of the buffer. The layout should not have
2462 * changed from the first call and no transition is necessary.
2464 assert(att_ref
->layout
== att_state
->current_layout
);
2468 /* Get the appropriate target layout for this attachment. */
2469 const VkImageLayout target_layout
= subpass_end
?
2470 att_desc
->final_layout
: att_ref
->layout
;
2472 /* The attachment index must be less than the number of attachments
2473 * within the framebuffer.
2475 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
2477 const struct anv_image
* const image
=
2478 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
]->image
;
2480 /* Perform the layout transition. */
2481 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2482 transition_depth_buffer(cmd_buffer
, image
,
2483 att_state
->current_layout
, target_layout
);
2484 att_state
->aux_usage
=
2485 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
2486 image
->aspects
, target_layout
);
2489 att_state
->current_layout
= target_layout
;
2494 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2495 struct anv_subpass
*subpass
)
2497 cmd_buffer
->state
.subpass
= subpass
;
2499 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2501 /* Perform transitions to the subpass layout before any writes have
2504 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
2506 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2508 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2511 void genX(CmdBeginRenderPass
)(
2512 VkCommandBuffer commandBuffer
,
2513 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2514 VkSubpassContents contents
)
2516 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2517 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2518 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2520 cmd_buffer
->state
.framebuffer
= framebuffer
;
2521 cmd_buffer
->state
.pass
= pass
;
2522 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2524 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2526 /* If we failed to setup the attachments we should not try to go further */
2527 if (result
!= VK_SUCCESS
) {
2528 assert(anv_batch_has_error(&cmd_buffer
->batch
));
2532 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2534 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2537 void genX(CmdNextSubpass
)(
2538 VkCommandBuffer commandBuffer
,
2539 VkSubpassContents contents
)
2541 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2543 if (anv_batch_has_error(&cmd_buffer
->batch
))
2546 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2548 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2550 /* Perform transitions to the final layout after all writes have occurred.
2552 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2554 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2557 void genX(CmdEndRenderPass
)(
2558 VkCommandBuffer commandBuffer
)
2560 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2562 if (anv_batch_has_error(&cmd_buffer
->batch
))
2565 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2567 /* Perform transitions to the final layout after all writes have occurred.
2569 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2571 cmd_buffer
->state
.hiz_enabled
= false;
2574 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2577 /* Remove references to render pass specific state. This enables us to
2578 * detect whether or not we're in a renderpass.
2580 cmd_buffer
->state
.framebuffer
= NULL
;
2581 cmd_buffer
->state
.pass
= NULL
;
2582 cmd_buffer
->state
.subpass
= NULL
;