2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
31 #include "common/gen_l3_config.h"
32 #include "genxml/gen_macros.h"
33 #include "genxml/genX_pack.h"
36 emit_lrm(struct anv_batch
*batch
,
37 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
39 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
40 lrm
.RegisterAddress
= reg
;
41 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
46 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
48 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
49 lri
.RegisterOffset
= reg
;
54 #if GEN_IS_HASWELL || GEN_GEN >= 8
56 emit_lrr(struct anv_batch
*batch
, uint32_t dst
, uint32_t src
)
58 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
59 lrr
.SourceRegisterAddress
= src
;
60 lrr
.DestinationRegisterAddress
= dst
;
66 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
68 struct anv_device
*device
= cmd_buffer
->device
;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
83 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
84 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
85 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
86 sba
.GeneralStateBaseAddressModifyEnable
= true;
88 sba
.SurfaceStateBaseAddress
=
89 anv_cmd_buffer_surface_base_address(cmd_buffer
);
90 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
91 sba
.SurfaceStateBaseAddressModifyEnable
= true;
93 sba
.DynamicStateBaseAddress
=
94 (struct anv_address
) { &device
->dynamic_state_pool
.block_pool
.bo
, 0 };
95 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
96 sba
.DynamicStateBaseAddressModifyEnable
= true;
98 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
99 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
100 sba
.IndirectObjectBaseAddressModifyEnable
= true;
102 sba
.InstructionBaseAddress
=
103 (struct anv_address
) { &device
->instruction_state_pool
.block_pool
.bo
, 0 };
104 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
105 sba
.InstructionBaseAddressModifyEnable
= true;
108 /* Broadwell requires that we specify a buffer size for a bunch of
109 * these fields. However, since we will be growing the BO's live, we
110 * just set them all to the maximum.
112 sba
.GeneralStateBufferSize
= 0xfffff;
113 sba
.GeneralStateBufferSizeModifyEnable
= true;
114 sba
.DynamicStateBufferSize
= 0xfffff;
115 sba
.DynamicStateBufferSizeModifyEnable
= true;
116 sba
.IndirectObjectBufferSize
= 0xfffff;
117 sba
.IndirectObjectBufferSizeModifyEnable
= true;
118 sba
.InstructionBufferSize
= 0xfffff;
119 sba
.InstructionBuffersizeModifyEnable
= true;
123 /* After re-setting the surface state base address, we have to do some
124 * cache flusing so that the sampler engine will pick up the new
125 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
126 * Shared Function > 3D Sampler > State > State Caching (page 96):
128 * Coherency with system memory in the state cache, like the texture
129 * cache is handled partially by software. It is expected that the
130 * command stream or shader will issue Cache Flush operation or
131 * Cache_Flush sampler message to ensure that the L1 cache remains
132 * coherent with system memory.
136 * Whenever the value of the Dynamic_State_Base_Addr,
137 * Surface_State_Base_Addr are altered, the L1 state cache must be
138 * invalidated to ensure the new surface or sampler state is fetched
139 * from system memory.
141 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
142 * which, according the PIPE_CONTROL instruction documentation in the
145 * Setting this bit is independent of any other bit in this packet.
146 * This bit controls the invalidation of the L1 and L2 state caches
147 * at the top of the pipe i.e. at the parsing time.
149 * Unfortunately, experimentation seems to indicate that state cache
150 * invalidation through a PIPE_CONTROL does nothing whatsoever in
151 * regards to surface state and binding tables. In stead, it seems that
152 * invalidating the texture cache is what is actually needed.
154 * XXX: As far as we have been able to determine through
155 * experimentation, shows that flush the texture cache appears to be
156 * sufficient. The theory here is that all of the sampling/rendering
157 * units cache the binding table in the texture cache. However, we have
158 * yet to be able to actually confirm this.
160 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
161 pc
.TextureCacheInvalidationEnable
= true;
162 pc
.ConstantCacheInvalidationEnable
= true;
163 pc
.StateCacheInvalidationEnable
= true;
168 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
169 struct anv_state state
, struct anv_address addr
)
171 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
174 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
175 state
.offset
+ isl_dev
->ss
.addr_offset
,
176 addr
.bo
, addr
.offset
);
177 if (result
!= VK_SUCCESS
)
178 anv_batch_set_error(&cmd_buffer
->batch
, result
);
182 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
183 struct anv_surface_state state
)
185 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
187 assert(!anv_address_is_null(state
.address
));
188 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
190 if (!anv_address_is_null(state
.aux_address
)) {
192 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
193 &cmd_buffer
->pool
->alloc
,
194 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
195 state
.aux_address
.bo
, state
.aux_address
.offset
);
196 if (result
!= VK_SUCCESS
)
197 anv_batch_set_error(&cmd_buffer
->batch
, result
);
200 if (!anv_address_is_null(state
.clear_address
)) {
202 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
203 &cmd_buffer
->pool
->alloc
,
205 isl_dev
->ss
.clear_color_state_offset
,
206 state
.clear_address
.bo
, state
.clear_address
.offset
);
207 if (result
!= VK_SUCCESS
)
208 anv_batch_set_error(&cmd_buffer
->batch
, result
);
213 color_attachment_compute_aux_usage(struct anv_device
* device
,
214 struct anv_cmd_state
* cmd_state
,
215 uint32_t att
, VkRect2D render_area
,
216 union isl_color_value
*fast_clear_color
)
218 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
219 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
221 assert(iview
->n_planes
== 1);
223 if (iview
->planes
[0].isl
.base_array_layer
>=
224 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
225 iview
->planes
[0].isl
.base_level
)) {
226 /* There is no aux buffer which corresponds to the level and layer(s)
229 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
230 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
231 att_state
->fast_clear
= false;
235 att_state
->aux_usage
=
236 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
237 VK_IMAGE_ASPECT_COLOR_BIT
,
238 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
240 /* If we don't have aux, then we should have returned early in the layer
241 * check above. If we got here, we must have something.
243 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
245 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
246 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
247 att_state
->input_aux_usage
= att_state
->aux_usage
;
249 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
251 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
252 * setting is only allowed if Surface Format supported for Fast
253 * Clear. In addition, if the surface is bound to the sampling
254 * engine, Surface Format must be supported for Render Target
255 * Compression for surfaces bound to the sampling engine."
257 * In other words, we can only sample from a fast-cleared image if it
258 * also supports color compression.
260 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
261 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
263 /* While fast-clear resolves and partial resolves are fairly cheap in the
264 * case where you render to most of the pixels, full resolves are not
265 * because they potentially involve reading and writing the entire
266 * framebuffer. If we can't texture with CCS_E, we should leave it off and
267 * limit ourselves to fast clears.
269 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
270 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
271 anv_perf_warn(device
->instance
, iview
->image
,
272 "Not temporarily enabling CCS_E.");
275 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
279 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
280 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
282 union isl_color_value clear_color
= {};
283 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
285 att_state
->clear_color_is_zero_one
=
286 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
287 att_state
->clear_color_is_zero
=
288 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
290 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
291 /* Start by getting the fast clear type. We use the first subpass
292 * layout here because we don't want to fast-clear if the first subpass
293 * to use the attachment can't handle fast-clears.
295 enum anv_fast_clear_type fast_clear_type
=
296 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
297 VK_IMAGE_ASPECT_COLOR_BIT
,
298 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
299 switch (fast_clear_type
) {
300 case ANV_FAST_CLEAR_NONE
:
301 att_state
->fast_clear
= false;
303 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
304 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
306 case ANV_FAST_CLEAR_ANY
:
307 att_state
->fast_clear
= true;
311 /* Potentially, we could do partial fast-clears but doing so has crazy
312 * alignment restrictions. It's easier to just restrict to full size
313 * fast clears for now.
315 if (render_area
.offset
.x
!= 0 ||
316 render_area
.offset
.y
!= 0 ||
317 render_area
.extent
.width
!= iview
->extent
.width
||
318 render_area
.extent
.height
!= iview
->extent
.height
)
319 att_state
->fast_clear
= false;
321 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
322 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
323 att_state
->fast_clear
= false;
325 /* We only allow fast clears to the first slice of an image (level 0,
326 * layer 0) and only for the entire slice. This guarantees us that, at
327 * any given time, there is only one clear color on any given image at
328 * any given time. At the time of our testing (Jan 17, 2018), there
329 * were no known applications which would benefit from fast-clearing
330 * more than just the first slice.
332 if (att_state
->fast_clear
&&
333 (iview
->planes
[0].isl
.base_level
> 0 ||
334 iview
->planes
[0].isl
.base_array_layer
> 0)) {
335 anv_perf_warn(device
->instance
, iview
->image
,
336 "Rendering with multi-lod or multi-layer framebuffer "
337 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
338 "baseArrayLayer > 0. Not fast clearing.");
339 att_state
->fast_clear
= false;
340 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
341 anv_perf_warn(device
->instance
, iview
->image
,
342 "Rendering to a multi-layer framebuffer with "
343 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
346 if (att_state
->fast_clear
)
347 *fast_clear_color
= clear_color
;
349 att_state
->fast_clear
= false;
354 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
355 struct anv_cmd_state
*cmd_state
,
356 uint32_t att
, VkRect2D render_area
)
358 struct anv_render_pass_attachment
*pass_att
=
359 &cmd_state
->pass
->attachments
[att
];
360 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
361 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
363 /* These will be initialized after the first subpass transition. */
364 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
365 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
368 /* We don't do any HiZ or depth fast-clears on gen7 yet */
369 att_state
->fast_clear
= false;
373 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
374 /* If we're just clearing stencil, we can always HiZ clear */
375 att_state
->fast_clear
= true;
379 /* Default to false for now */
380 att_state
->fast_clear
= false;
382 /* We must have depth in order to have HiZ */
383 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
386 const enum isl_aux_usage first_subpass_aux_usage
=
387 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
388 VK_IMAGE_ASPECT_DEPTH_BIT
,
389 pass_att
->first_subpass_layout
);
390 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
393 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
394 iview
->planes
[0].isl
.format
,
395 iview
->image
->samples
,
396 render_area
.offset
.x
,
397 render_area
.offset
.y
,
398 render_area
.offset
.x
+
399 render_area
.extent
.width
,
400 render_area
.offset
.y
+
401 render_area
.extent
.height
))
404 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
407 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
408 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
409 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
410 * only supports returning 0.0f. Gens prior to gen8 do not support this
416 /* If we got here, then we can fast clear */
417 att_state
->fast_clear
= true;
421 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
423 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
426 /* We only allocate input attachment states for color surfaces. Compression
427 * is not yet enabled for depth textures and stencil doesn't allow
428 * compression so we can just use the texture surface state from the view.
430 return vk_format_is_color(att
->format
);
433 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
434 * the initial layout is undefined, the HiZ buffer and depth buffer will
435 * represent the same data at the end of this operation.
438 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
439 const struct anv_image
*image
,
440 VkImageLayout initial_layout
,
441 VkImageLayout final_layout
)
443 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
444 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
445 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
446 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
447 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
448 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
450 enum isl_aux_op hiz_op
;
451 if (hiz_enabled
&& !enable_hiz
) {
452 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
453 } else if (!hiz_enabled
&& enable_hiz
) {
454 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
456 assert(hiz_enabled
== enable_hiz
);
457 /* If the same buffer will be used, no resolves are necessary. */
458 hiz_op
= ISL_AUX_OP_NONE
;
461 if (hiz_op
!= ISL_AUX_OP_NONE
)
462 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
466 #define MI_PREDICATE_SRC0 0x2400
467 #define MI_PREDICATE_SRC1 0x2408
470 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
471 const struct anv_image
*image
,
472 VkImageAspectFlagBits aspect
,
474 uint32_t base_layer
, uint32_t layer_count
,
477 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
479 /* We only have compression tracking for CCS_E */
480 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
483 for (uint32_t a
= 0; a
< layer_count
; a
++) {
484 uint32_t layer
= base_layer
+ a
;
485 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
486 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
489 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
495 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
496 const struct anv_image
*image
,
497 VkImageAspectFlagBits aspect
,
498 enum anv_fast_clear_type fast_clear
)
500 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
501 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
503 sdi
.ImmediateData
= fast_clear
;
506 /* Whenever we have fast-clear, we consider that slice to be compressed.
507 * This makes building predicates much easier.
509 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
510 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
513 #if GEN_IS_HASWELL || GEN_GEN >= 8
514 static inline uint32_t
515 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
517 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
519 .Operand1
= operand1
,
520 .Operand2
= operand2
,
524 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
530 #define CS_GPR(n) (0x2600 + (n) * 8)
532 /* This is only really practical on haswell and above because it requires
533 * MI math in order to get it correct.
535 #if GEN_GEN >= 8 || GEN_IS_HASWELL
537 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
538 const struct anv_image
*image
,
539 VkImageAspectFlagBits aspect
,
540 uint32_t level
, uint32_t array_layer
,
541 enum isl_aux_op resolve_op
,
542 enum anv_fast_clear_type fast_clear_supported
)
544 struct anv_address fast_clear_type_addr
=
545 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
547 /* Name some registers */
548 const int image_fc_reg
= MI_ALU_REG0
;
549 const int fc_imm_reg
= MI_ALU_REG1
;
550 const int pred_reg
= MI_ALU_REG2
;
554 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
555 /* In this case, we're doing a full resolve which means we want the
556 * resolve to happen if any compression (including fast-clears) is
559 * In order to simplify the logic a bit, we make the assumption that,
560 * if the first slice has been fast-cleared, it is also marked as
561 * compressed. See also set_image_fast_clear_state.
563 struct anv_address compression_state_addr
=
564 anv_image_get_compression_state_addr(cmd_buffer
->device
, image
,
565 aspect
, level
, array_layer
);
566 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
567 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
568 lrm
.MemoryAddress
= compression_state_addr
;
570 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
571 sdi
.Address
= compression_state_addr
;
572 sdi
.ImmediateData
= 0;
575 if (level
== 0 && array_layer
== 0) {
576 /* If the predicate is true, we want to write 0 to the fast clear type
577 * and, if it's false, leave it alone. We can do this by writing
579 * clear_type = clear_type & ~predicate;
581 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
582 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
583 lrm
.MemoryAddress
= fast_clear_type_addr
;
585 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_REG
), lrr
) {
586 lrr
.DestinationRegisterAddress
= CS_GPR(pred_reg
);
587 lrr
.SourceRegisterAddress
= MI_PREDICATE_SRC0
;
590 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
591 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
592 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
593 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
594 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
596 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
597 srm
.MemoryAddress
= fast_clear_type_addr
;
598 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
601 } else if (level
== 0 && array_layer
== 0) {
602 /* In this case, we are doing a partial resolve to get rid of fast-clear
603 * colors. We don't care about the compression state but we do care
604 * about how much fast clear is allowed by the final layout.
606 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
607 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
609 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
610 lrm
.RegisterAddress
= CS_GPR(image_fc_reg
);
611 lrm
.MemoryAddress
= fast_clear_type_addr
;
613 emit_lri(&cmd_buffer
->batch
, CS_GPR(image_fc_reg
) + 4, 0);
615 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
), fast_clear_supported
);
616 emit_lri(&cmd_buffer
->batch
, CS_GPR(fc_imm_reg
) + 4, 0);
618 /* We need to compute (fast_clear_supported < image->fast_clear).
619 * We do this by subtracting and storing the carry bit.
621 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
622 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, fc_imm_reg
);
623 dw
[2] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, image_fc_reg
);
624 dw
[3] = mi_alu(MI_ALU_SUB
, 0, 0);
625 dw
[4] = mi_alu(MI_ALU_STORE
, pred_reg
, MI_ALU_CF
);
627 /* Store the predicate */
628 emit_lrr(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
, CS_GPR(pred_reg
));
630 /* If the predicate is true, we want to write 0 to the fast clear type
631 * and, if it's false, leave it alone. We can do this by writing
633 * clear_type = clear_type & ~predicate;
635 dw
= anv_batch_emitn(&cmd_buffer
->batch
, 5, GENX(MI_MATH
));
636 dw
[1] = mi_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, image_fc_reg
);
637 dw
[2] = mi_alu(MI_ALU_LOADINV
, MI_ALU_SRCB
, pred_reg
);
638 dw
[3] = mi_alu(MI_ALU_AND
, 0, 0);
639 dw
[4] = mi_alu(MI_ALU_STORE
, image_fc_reg
, MI_ALU_ACCU
);
641 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
642 srm
.RegisterAddress
= CS_GPR(image_fc_reg
);
643 srm
.MemoryAddress
= fast_clear_type_addr
;
646 /* In this case, we're trying to do a partial resolve on a slice that
647 * doesn't have clear color. There's nothing to do.
649 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
653 /* We use the first half of src0 for the actual predicate. Set the second
654 * half of src0 and all of src1 to 0 as the predicate operation will be
655 * doing an implicit src0 != src1.
657 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
658 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
659 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
661 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
662 mip
.LoadOperation
= LOAD_LOADINV
;
663 mip
.CombineOperation
= COMBINE_SET
;
664 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
667 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
671 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
672 const struct anv_image
*image
,
673 VkImageAspectFlagBits aspect
,
674 uint32_t level
, uint32_t array_layer
,
675 enum isl_aux_op resolve_op
,
676 enum anv_fast_clear_type fast_clear_supported
)
678 struct anv_address fast_clear_type_addr
=
679 anv_image_get_fast_clear_type_addr(cmd_buffer
->device
, image
, aspect
);
681 /* This only works for partial resolves and only when the clear color is
682 * all or nothing. On the upside, this emits less command streamer code
683 * and works on Ivybridge and Bay Trail.
685 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
686 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
688 /* We don't support fast clears on anything other than the first slice. */
689 if (level
> 0 || array_layer
> 0)
692 /* On gen8, we don't have a concept of default clear colors because we
693 * can't sample from CCS surfaces. It's enough to just load the fast clear
694 * state into the predicate register.
696 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
697 lrm
.RegisterAddress
= MI_PREDICATE_SRC0
;
698 lrm
.MemoryAddress
= fast_clear_type_addr
;
700 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
701 sdi
.Address
= fast_clear_type_addr
;
702 sdi
.ImmediateData
= 0;
705 /* We use the first half of src0 for the actual predicate. Set the second
706 * half of src0 and all of src1 to 0 as the predicate operation will be
707 * doing an implicit src0 != src1.
709 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC0
+ 4, 0);
710 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
, 0);
711 emit_lri(&cmd_buffer
->batch
, MI_PREDICATE_SRC1
+ 4, 0);
713 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
714 mip
.LoadOperation
= LOAD_LOADINV
;
715 mip
.CombineOperation
= COMBINE_SET
;
716 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
719 #endif /* GEN_GEN <= 8 */
722 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
723 const struct anv_image
*image
,
724 VkImageAspectFlagBits aspect
,
725 uint32_t level
, uint32_t array_layer
,
726 enum isl_aux_op resolve_op
,
727 enum anv_fast_clear_type fast_clear_supported
)
729 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
732 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
733 aspect
, level
, array_layer
,
734 resolve_op
, fast_clear_supported
);
735 #else /* GEN_GEN <= 8 */
736 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
737 aspect
, level
, array_layer
,
738 resolve_op
, fast_clear_supported
);
741 /* CCS_D only supports full resolves and BLORP will assert on us if we try
742 * to do a partial resolve on a CCS_D surface.
744 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
745 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
746 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
748 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
749 array_layer
, 1, resolve_op
, NULL
, true);
753 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
754 const struct anv_image
*image
,
755 VkImageAspectFlagBits aspect
,
756 uint32_t array_layer
,
757 enum isl_aux_op resolve_op
,
758 enum anv_fast_clear_type fast_clear_supported
)
760 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
761 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
763 #if GEN_GEN >= 8 || GEN_IS_HASWELL
764 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
765 aspect
, 0, array_layer
,
766 resolve_op
, fast_clear_supported
);
768 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
769 array_layer
, 1, resolve_op
, NULL
, true);
771 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
776 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
777 const struct anv_image
*image
,
778 VkImageAspectFlagBits aspect
,
779 enum isl_aux_usage aux_usage
,
782 uint32_t layer_count
)
784 /* The aspect must be exactly one of the image aspects. */
785 assert(_mesa_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
787 /* The only compression types with more than just fast-clears are MCS,
788 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
789 * track the current fast-clear and compression state. This leaves us
790 * with just MCS and CCS_E.
792 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
793 aux_usage
!= ISL_AUX_USAGE_MCS
)
796 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
797 level
, base_layer
, layer_count
, true);
801 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
802 const struct anv_image
*image
,
803 VkImageAspectFlagBits aspect
)
805 assert(cmd_buffer
&& image
);
806 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
808 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
809 ANV_FAST_CLEAR_NONE
);
811 /* The fast clear value dword(s) will be copied into a surface state object.
812 * Ensure that the restrictions of the fields in the dword(s) are followed.
814 * CCS buffers on SKL+ can have any value set for the clear colors.
816 if (image
->samples
== 1 && GEN_GEN
>= 9)
819 /* Other combinations of auxiliary buffers and platforms require specific
820 * values in the clear value dword(s).
822 struct anv_address addr
=
823 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
826 for (unsigned i
= 0; i
< 4; i
++) {
827 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
829 sdi
.Address
.offset
+= i
* 4;
830 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
831 assert(image
->samples
> 1);
832 sdi
.ImmediateData
= 0;
836 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
838 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
839 /* Pre-SKL, the dword containing the clear values also contains
840 * other fields, so we need to initialize those fields to match the
841 * values that would be in a color attachment.
843 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
844 ISL_CHANNEL_SELECT_GREEN
<< 22 |
845 ISL_CHANNEL_SELECT_BLUE
<< 19 |
846 ISL_CHANNEL_SELECT_ALPHA
<< 16;
847 } else if (GEN_GEN
== 7) {
848 /* On IVB, the dword containing the clear values also contains
849 * other fields that must be zero or can be zero.
851 sdi
.ImmediateData
= 0;
857 /* Copy the fast-clear value dword(s) between a surface state object and an
858 * image's fast clear state buffer.
861 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
862 struct anv_state surface_state
,
863 const struct anv_image
*image
,
864 VkImageAspectFlagBits aspect
,
865 bool copy_from_surface_state
)
867 assert(cmd_buffer
&& image
);
868 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
870 struct anv_bo
*ss_bo
=
871 &cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
;
872 uint32_t ss_clear_offset
= surface_state
.offset
+
873 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
;
874 const struct anv_address entry_addr
=
875 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
876 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
878 if (copy_from_surface_state
) {
879 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, entry_addr
.bo
, entry_addr
.offset
,
880 ss_bo
, ss_clear_offset
, copy_size
);
882 genX(cmd_buffer_mi_memcpy
)(cmd_buffer
, ss_bo
, ss_clear_offset
,
883 entry_addr
.bo
, entry_addr
.offset
, copy_size
);
885 /* Updating a surface state object may require that the state cache be
886 * invalidated. From the SKL PRM, Shared Functions -> State -> State
889 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
890 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
891 * modified [...], the L1 state cache must be invalidated to ensure
892 * the new surface or sampler state is fetched from system memory.
894 * In testing, SKL doesn't actually seem to need this, but HSW does.
896 cmd_buffer
->state
.pending_pipe_bits
|=
897 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
902 * @brief Transitions a color buffer from one layout to another.
904 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
907 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
908 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
909 * this represents the maximum layers to transition at each
910 * specified miplevel.
913 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
914 const struct anv_image
*image
,
915 VkImageAspectFlagBits aspect
,
916 const uint32_t base_level
, uint32_t level_count
,
917 uint32_t base_layer
, uint32_t layer_count
,
918 VkImageLayout initial_layout
,
919 VkImageLayout final_layout
)
921 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
922 /* Validate the inputs. */
924 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
925 /* These values aren't supported for simplicity's sake. */
926 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
927 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
928 /* Ensure the subresource range is valid. */
929 uint64_t last_level_num
= base_level
+ level_count
;
930 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
931 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
932 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
933 assert(last_level_num
<= image
->levels
);
934 /* The spec disallows these final layouts. */
935 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
936 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
938 /* No work is necessary if the layout stays the same or if this subresource
939 * range lacks auxiliary data.
941 if (initial_layout
== final_layout
)
944 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
946 if (image
->planes
[plane
].shadow_surface
.isl
.size
> 0 &&
947 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
948 /* This surface is a linear compressed image with a tiled shadow surface
949 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
950 * we need to ensure the shadow copy is up-to-date.
952 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
953 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
954 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
955 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
957 anv_image_copy_to_shadow(cmd_buffer
, image
,
958 base_level
, level_count
,
959 base_layer
, layer_count
);
962 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
965 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
967 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
968 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
969 /* A subresource in the undefined layout may have been aliased and
970 * populated with any arrangement of bits. Therefore, we must initialize
971 * the related aux buffer and clear buffer entry with desirable values.
972 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
973 * images with VK_IMAGE_TILING_OPTIMAL.
975 * Initialize the relevant clear buffer entries.
977 if (base_level
== 0 && base_layer
== 0)
978 init_fast_clear_color(cmd_buffer
, image
, aspect
);
980 /* Initialize the aux buffers to enable correct rendering. In order to
981 * ensure that things such as storage images work correctly, aux buffers
982 * need to be initialized to valid data.
984 * Having an aux buffer with invalid data is a problem for two reasons:
986 * 1) Having an invalid value in the buffer can confuse the hardware.
987 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
988 * invalid and leads to the hardware doing strange things. It
989 * doesn't hang as far as we can tell but rendering corruption can
992 * 2) If this transition is into the GENERAL layout and we then use the
993 * image as a storage image, then we must have the aux buffer in the
994 * pass-through state so that, if we then go to texture from the
995 * image, we get the results of our storage image writes and not the
996 * fast clear color or other random data.
998 * For CCS both of the problems above are real demonstrable issues. In
999 * that case, the only thing we can do is to perform an ambiguate to
1000 * transition the aux surface into the pass-through state.
1002 * For MCS, (2) is never an issue because we don't support multisampled
1003 * storage images. In theory, issue (1) is a problem with MCS but we've
1004 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1005 * theory, be interpreted as something but we don't know that all bit
1006 * patterns are actually valid. For 2x and 8x, you could easily end up
1007 * with the MCS referring to an invalid plane because not all bits of
1008 * the MCS value are actually used. Even though we've never seen issues
1009 * in the wild, it's best to play it safe and initialize the MCS. We
1010 * can use a fast-clear for MCS because we only ever touch from render
1011 * and texture (no image load store).
1013 if (image
->samples
== 1) {
1014 for (uint32_t l
= 0; l
< level_count
; l
++) {
1015 const uint32_t level
= base_level
+ l
;
1017 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1018 if (base_layer
>= aux_layers
)
1019 break; /* We will only get fewer layers as level increases */
1020 uint32_t level_layer_count
=
1021 MIN2(layer_count
, aux_layers
- base_layer
);
1023 anv_image_ccs_op(cmd_buffer
, image
, aspect
, level
,
1024 base_layer
, level_layer_count
,
1025 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1027 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1028 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1029 level
, base_layer
, level_layer_count
,
1034 if (image
->samples
== 4 || image
->samples
== 16) {
1035 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1036 "Doing a potentially unnecessary fast-clear to "
1037 "define an MCS buffer.");
1040 assert(base_level
== 0 && level_count
== 1);
1041 anv_image_mcs_op(cmd_buffer
, image
, aspect
,
1042 base_layer
, layer_count
,
1043 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1048 const enum isl_aux_usage initial_aux_usage
=
1049 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1050 const enum isl_aux_usage final_aux_usage
=
1051 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1053 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1054 * We can handle transitions between CCS_D/E to and from NONE. What we
1055 * don't yet handle is switching between CCS_E and CCS_D within a given
1056 * image. Doing so in a performant way requires more detailed aux state
1057 * tracking such as what is done in i965. For now, just assume that we
1058 * only have one type of compression.
1060 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1061 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1062 initial_aux_usage
== final_aux_usage
);
1064 /* If initial aux usage is NONE, there is nothing to resolve */
1065 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1068 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1070 /* If the initial layout supports more fast clear than the final layout
1071 * then we need at least a partial resolve.
1073 const enum anv_fast_clear_type initial_fast_clear
=
1074 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1075 const enum anv_fast_clear_type final_fast_clear
=
1076 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1077 if (final_fast_clear
< initial_fast_clear
)
1078 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1080 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1081 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1082 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1084 if (resolve_op
== ISL_AUX_OP_NONE
)
1087 /* Perform a resolve to synchronize data between the main and aux buffer.
1088 * Before we begin, we must satisfy the cache flushing requirement specified
1089 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1091 * Any transition from any value in {Clear, Render, Resolve} to a
1092 * different value in {Clear, Render, Resolve} requires end of pipe
1095 * We perform a flush of the write cache before and after the clear and
1096 * resolve operations to meet this requirement.
1098 * Unlike other drawing, fast clear operations are not properly
1099 * synchronized. The first PIPE_CONTROL here likely ensures that the
1100 * contents of the previous render or clear hit the render target before we
1101 * resolve and the second likely ensures that the resolve is complete before
1102 * we do any more rendering or clearing.
1104 cmd_buffer
->state
.pending_pipe_bits
|=
1105 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1107 for (uint32_t l
= 0; l
< level_count
; l
++) {
1108 uint32_t level
= base_level
+ l
;
1110 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1111 if (base_layer
>= aux_layers
)
1112 break; /* We will only get fewer layers as level increases */
1113 uint32_t level_layer_count
=
1114 MIN2(layer_count
, aux_layers
- base_layer
);
1116 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1117 uint32_t array_layer
= base_layer
+ a
;
1118 if (image
->samples
== 1) {
1119 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
, aspect
,
1120 level
, array_layer
, resolve_op
,
1123 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
, aspect
,
1124 array_layer
, resolve_op
,
1130 cmd_buffer
->state
.pending_pipe_bits
|=
1131 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1135 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1138 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1139 struct anv_render_pass
*pass
,
1140 const VkRenderPassBeginInfo
*begin
)
1142 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1143 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1145 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1147 if (pass
->attachment_count
> 0) {
1148 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1149 pass
->attachment_count
*
1150 sizeof(state
->attachments
[0]),
1151 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1152 if (state
->attachments
== NULL
) {
1153 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1154 return anv_batch_set_error(&cmd_buffer
->batch
,
1155 VK_ERROR_OUT_OF_HOST_MEMORY
);
1158 state
->attachments
= NULL
;
1161 /* Reserve one for the NULL state. */
1162 unsigned num_states
= 1;
1163 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1164 if (vk_format_is_color(pass
->attachments
[i
].format
))
1167 if (need_input_attachment_state(&pass
->attachments
[i
]))
1171 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1172 state
->render_pass_states
=
1173 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1174 num_states
* ss_stride
, isl_dev
->ss
.align
);
1176 struct anv_state next_state
= state
->render_pass_states
;
1177 next_state
.alloc_size
= isl_dev
->ss
.size
;
1179 state
->null_surface_state
= next_state
;
1180 next_state
.offset
+= ss_stride
;
1181 next_state
.map
+= ss_stride
;
1183 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1184 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1185 state
->attachments
[i
].color
.state
= next_state
;
1186 next_state
.offset
+= ss_stride
;
1187 next_state
.map
+= ss_stride
;
1190 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1191 state
->attachments
[i
].input
.state
= next_state
;
1192 next_state
.offset
+= ss_stride
;
1193 next_state
.map
+= ss_stride
;
1196 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1197 state
->render_pass_states
.alloc_size
);
1200 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1201 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1203 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1204 isl_extent3d(framebuffer
->width
,
1205 framebuffer
->height
,
1206 framebuffer
->layers
));
1208 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1209 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1210 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1211 VkImageAspectFlags clear_aspects
= 0;
1212 VkImageAspectFlags load_aspects
= 0;
1214 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1215 /* color attachment */
1216 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1217 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1218 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1219 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1222 /* depthstencil attachment */
1223 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1224 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1225 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1226 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1227 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1230 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1231 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1232 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1233 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1234 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1239 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1240 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1241 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1243 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1245 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1246 anv_assert(iview
->vk_format
== att
->format
);
1248 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1249 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1251 union isl_color_value clear_color
= { .u32
= { 0, } };
1252 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1253 anv_assert(iview
->n_planes
== 1);
1254 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1255 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1256 state
, i
, begin
->renderArea
,
1259 anv_image_fill_surface_state(cmd_buffer
->device
,
1261 VK_IMAGE_ASPECT_COLOR_BIT
,
1262 &iview
->planes
[0].isl
,
1263 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1264 state
->attachments
[i
].aux_usage
,
1267 &state
->attachments
[i
].color
,
1270 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1272 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1277 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1278 anv_image_fill_surface_state(cmd_buffer
->device
,
1280 VK_IMAGE_ASPECT_COLOR_BIT
,
1281 &iview
->planes
[0].isl
,
1282 ISL_SURF_USAGE_TEXTURE_BIT
,
1283 state
->attachments
[i
].input_aux_usage
,
1286 &state
->attachments
[i
].input
,
1289 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1298 genX(BeginCommandBuffer
)(
1299 VkCommandBuffer commandBuffer
,
1300 const VkCommandBufferBeginInfo
* pBeginInfo
)
1302 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1304 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1305 * command buffer's state. Otherwise, we must *reset* its state. In both
1306 * cases we reset it.
1308 * From the Vulkan 1.0 spec:
1310 * If a command buffer is in the executable state and the command buffer
1311 * was allocated from a command pool with the
1312 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1313 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1314 * as if vkResetCommandBuffer had been called with
1315 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1316 * the command buffer in the recording state.
1318 anv_cmd_buffer_reset(cmd_buffer
);
1320 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1322 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1323 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1325 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1327 /* We sometimes store vertex data in the dynamic state buffer for blorp
1328 * operations and our dynamic state stream may re-use data from previous
1329 * command buffers. In order to prevent stale cache data, we flush the VF
1330 * cache. We could do this on every blorp call but that's not really
1331 * needed as all of the data will get written by the CPU prior to the GPU
1332 * executing anything. The chances are fairly high that they will use
1333 * blorp at least once per primary command buffer so it shouldn't be
1336 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1337 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1339 /* We send an "Indirect State Pointers Disable" packet at
1340 * EndCommandBuffer, so all push contant packets are ignored during a
1341 * context restore. Documentation says after that command, we need to
1342 * emit push constants again before any rendering operation. So we
1343 * flag them dirty here to make sure they get emitted.
1345 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1347 VkResult result
= VK_SUCCESS
;
1348 if (cmd_buffer
->usage_flags
&
1349 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1350 assert(pBeginInfo
->pInheritanceInfo
);
1351 cmd_buffer
->state
.pass
=
1352 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1353 cmd_buffer
->state
.subpass
=
1354 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1356 /* This is optional in the inheritance info. */
1357 cmd_buffer
->state
.framebuffer
=
1358 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1360 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1361 cmd_buffer
->state
.pass
, NULL
);
1363 /* Record that HiZ is enabled if we can. */
1364 if (cmd_buffer
->state
.framebuffer
) {
1365 const struct anv_image_view
* const iview
=
1366 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1369 VkImageLayout layout
=
1370 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.layout
;
1372 enum isl_aux_usage aux_usage
=
1373 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1374 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1376 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1380 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1386 /* From the PRM, Volume 2a:
1388 * "Indirect State Pointers Disable
1390 * At the completion of the post-sync operation associated with this pipe
1391 * control packet, the indirect state pointers in the hardware are
1392 * considered invalid; the indirect pointers are not saved in the context.
1393 * If any new indirect state commands are executed in the command stream
1394 * while the pipe control is pending, the new indirect state commands are
1397 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1398 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1399 * commands are only considered as Indirect State Pointers. Once ISP is
1400 * issued in a context, SW must initialize by programming push constant
1401 * commands for all the shaders (at least to zero length) before attempting
1402 * any rendering operation for the same context."
1404 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1405 * even though they point to a BO that has been already unreferenced at
1406 * the end of the previous batch buffer. This has been fine so far since
1407 * we are protected by these scratch page (every address not covered by
1408 * a BO should be pointing to the scratch page). But on CNL, it is
1409 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1412 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1413 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1414 * context restore, so the mentioned hang doesn't happen. However,
1415 * software must program push constant commands for all stages prior to
1416 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1418 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1419 * constants have been loaded into the EUs prior to disable the push constants
1420 * so that it doesn't hang a previous 3DPRIMITIVE.
1423 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1425 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1426 pc
.StallAtPixelScoreboard
= true;
1427 pc
.CommandStreamerStallEnable
= true;
1429 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1430 pc
.IndirectStatePointersDisable
= true;
1431 pc
.CommandStreamerStallEnable
= true;
1436 genX(EndCommandBuffer
)(
1437 VkCommandBuffer commandBuffer
)
1439 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1441 if (anv_batch_has_error(&cmd_buffer
->batch
))
1442 return cmd_buffer
->batch
.status
;
1444 /* We want every command buffer to start with the PMA fix in a known state,
1445 * so we disable it at the end of the command buffer.
1447 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1449 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1451 emit_isp_disable(cmd_buffer
);
1453 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1459 genX(CmdExecuteCommands
)(
1460 VkCommandBuffer commandBuffer
,
1461 uint32_t commandBufferCount
,
1462 const VkCommandBuffer
* pCmdBuffers
)
1464 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1466 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1468 if (anv_batch_has_error(&primary
->batch
))
1471 /* The secondary command buffers will assume that the PMA fix is disabled
1472 * when they begin executing. Make sure this is true.
1474 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1476 /* The secondary command buffer doesn't know which textures etc. have been
1477 * flushed prior to their execution. Apply those flushes now.
1479 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1481 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1482 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1484 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1485 assert(!anv_batch_has_error(&secondary
->batch
));
1487 if (secondary
->usage_flags
&
1488 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1489 /* If we're continuing a render pass from the primary, we need to
1490 * copy the surface states for the current subpass into the storage
1491 * we allocated for them in BeginCommandBuffer.
1493 struct anv_bo
*ss_bo
=
1494 &primary
->device
->surface_state_pool
.block_pool
.bo
;
1495 struct anv_state src_state
= primary
->state
.render_pass_states
;
1496 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1497 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1499 genX(cmd_buffer_so_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
1500 ss_bo
, src_state
.offset
,
1501 src_state
.alloc_size
);
1504 anv_cmd_buffer_add_secondary(primary
, secondary
);
1507 /* The secondary may have selected a different pipeline (3D or compute) and
1508 * may have changed the current L3$ configuration. Reset our tracking
1509 * variables to invalid values to ensure that we re-emit these in the case
1510 * where we do any draws or compute dispatches from the primary after the
1511 * secondary has returned.
1513 primary
->state
.current_pipeline
= UINT32_MAX
;
1514 primary
->state
.current_l3_config
= NULL
;
1516 /* Each of the secondary command buffers will use its own state base
1517 * address. We need to re-emit state base address for the primary after
1518 * all of the secondaries are done.
1520 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1523 genX(cmd_buffer_emit_state_base_address
)(primary
);
1526 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1527 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1528 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1531 * Program the hardware to use the specified L3 configuration.
1534 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1535 const struct gen_l3_config
*cfg
)
1538 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1541 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1542 intel_logd("L3 config transition: ");
1543 gen_dump_l3_config(cfg
, stderr
);
1546 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1548 /* According to the hardware docs, the L3 partitioning can only be changed
1549 * while the pipeline is completely drained and the caches are flushed,
1550 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1552 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1553 pc
.DCFlushEnable
= true;
1554 pc
.PostSyncOperation
= NoWrite
;
1555 pc
.CommandStreamerStallEnable
= true;
1558 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1559 * invalidation of the relevant caches. Note that because RO invalidation
1560 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1561 * command is processed by the CS) we cannot combine it with the previous
1562 * stalling flush as the hardware documentation suggests, because that
1563 * would cause the CS to stall on previous rendering *after* RO
1564 * invalidation and wouldn't prevent the RO caches from being polluted by
1565 * concurrent rendering before the stall completes. This intentionally
1566 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1567 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1568 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1569 * already guarantee that there is no concurrent GPGPU kernel execution
1570 * (see SKL HSD 2132585).
1572 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1573 pc
.TextureCacheInvalidationEnable
= true;
1574 pc
.ConstantCacheInvalidationEnable
= true;
1575 pc
.InstructionCacheInvalidateEnable
= true;
1576 pc
.StateCacheInvalidationEnable
= true;
1577 pc
.PostSyncOperation
= NoWrite
;
1580 /* Now send a third stalling flush to make sure that invalidation is
1581 * complete when the L3 configuration registers are modified.
1583 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1584 pc
.DCFlushEnable
= true;
1585 pc
.PostSyncOperation
= NoWrite
;
1586 pc
.CommandStreamerStallEnable
= true;
1591 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1594 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1595 .SLMEnable
= has_slm
,
1596 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1597 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1598 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1599 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1601 /* Set up the L3 partitioning. */
1602 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1606 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1607 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1608 cfg
->n
[GEN_L3P_ALL
];
1609 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1610 cfg
->n
[GEN_L3P_ALL
];
1611 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1612 cfg
->n
[GEN_L3P_ALL
];
1614 assert(!cfg
->n
[GEN_L3P_ALL
]);
1616 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1617 * the matching space on the remaining banks has to be allocated to a
1618 * client (URB for all validated configurations) set to the
1619 * lower-bandwidth 2-bank address hashing mode.
1621 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1622 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1623 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1625 /* Minimum number of ways that can be allocated to the URB. */
1626 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1627 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1629 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1630 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1631 .ConvertDC_UC
= !has_dc
,
1632 .ConvertIS_UC
= !has_is
,
1633 .ConvertC_UC
= !has_c
,
1634 .ConvertT_UC
= !has_t
);
1636 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1637 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1638 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1640 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1641 .SLMEnable
= has_slm
,
1642 .URBLowBandwidth
= urb_low_bw
,
1643 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1645 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1647 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1648 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1650 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1651 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1652 .ISLowBandwidth
= 0,
1653 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1655 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1656 .TLowBandwidth
= 0);
1658 /* Set up the L3 partitioning. */
1659 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1660 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1661 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1664 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1665 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1666 * them disabled to avoid crashing the system hard.
1668 uint32_t scratch1
, chicken3
;
1669 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1670 .L3AtomicDisable
= !has_dc
);
1671 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1672 .L3AtomicDisableMask
= true,
1673 .L3AtomicDisable
= !has_dc
);
1674 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1675 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1681 cmd_buffer
->state
.current_l3_config
= cfg
;
1685 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1687 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1689 /* Flushes are pipelined while invalidations are handled immediately.
1690 * Therefore, if we're flushing anything then we need to schedule a stall
1691 * before any invalidations can happen.
1693 if (bits
& ANV_PIPE_FLUSH_BITS
)
1694 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1696 /* If we're going to do an invalidate and we have a pending CS stall that
1697 * has yet to be resolved, we do the CS stall now.
1699 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1700 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1701 bits
|= ANV_PIPE_CS_STALL_BIT
;
1702 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1705 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1706 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1707 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1708 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1709 pipe
.RenderTargetCacheFlushEnable
=
1710 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1712 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1713 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1714 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1717 * According to the Broadwell documentation, any PIPE_CONTROL with the
1718 * "Command Streamer Stall" bit set must also have another bit set,
1719 * with five different options:
1721 * - Render Target Cache Flush
1722 * - Depth Cache Flush
1723 * - Stall at Pixel Scoreboard
1724 * - Post-Sync Operation
1728 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1729 * mesa and it seems to work fine. The choice is fairly arbitrary.
1731 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1732 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1733 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1734 pipe
.StallAtPixelScoreboard
= true;
1737 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1740 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1741 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1742 pipe
.StateCacheInvalidationEnable
=
1743 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1744 pipe
.ConstantCacheInvalidationEnable
=
1745 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1746 pipe
.VFCacheInvalidationEnable
=
1747 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1748 pipe
.TextureCacheInvalidationEnable
=
1749 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1750 pipe
.InstructionCacheInvalidateEnable
=
1751 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1754 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1757 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1760 void genX(CmdPipelineBarrier
)(
1761 VkCommandBuffer commandBuffer
,
1762 VkPipelineStageFlags srcStageMask
,
1763 VkPipelineStageFlags destStageMask
,
1765 uint32_t memoryBarrierCount
,
1766 const VkMemoryBarrier
* pMemoryBarriers
,
1767 uint32_t bufferMemoryBarrierCount
,
1768 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1769 uint32_t imageMemoryBarrierCount
,
1770 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1772 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1774 /* XXX: Right now, we're really dumb and just flush whatever categories
1775 * the app asks for. One of these days we may make this a bit better
1776 * but right now that's all the hardware allows for in most areas.
1778 VkAccessFlags src_flags
= 0;
1779 VkAccessFlags dst_flags
= 0;
1781 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1782 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1783 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1786 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1787 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1788 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1791 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1792 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1793 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1794 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1795 const VkImageSubresourceRange
*range
=
1796 &pImageMemoryBarriers
[i
].subresourceRange
;
1798 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1799 transition_depth_buffer(cmd_buffer
, image
,
1800 pImageMemoryBarriers
[i
].oldLayout
,
1801 pImageMemoryBarriers
[i
].newLayout
);
1802 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1803 VkImageAspectFlags color_aspects
=
1804 anv_image_expand_aspects(image
, range
->aspectMask
);
1805 uint32_t aspect_bit
;
1807 uint32_t base_layer
, layer_count
;
1808 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1810 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1812 base_layer
= range
->baseArrayLayer
;
1813 layer_count
= anv_get_layerCount(image
, range
);
1816 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1817 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1818 range
->baseMipLevel
,
1819 anv_get_levelCount(image
, range
),
1820 base_layer
, layer_count
,
1821 pImageMemoryBarriers
[i
].oldLayout
,
1822 pImageMemoryBarriers
[i
].newLayout
);
1827 cmd_buffer
->state
.pending_pipe_bits
|=
1828 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1829 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1833 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1835 VkShaderStageFlags stages
=
1836 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1838 /* In order to avoid thrash, we assume that vertex and fragment stages
1839 * always exist. In the rare case where one is missing *and* the other
1840 * uses push concstants, this may be suboptimal. However, avoiding stalls
1841 * seems more important.
1843 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1845 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1849 const unsigned push_constant_kb
= 32;
1850 #elif GEN_IS_HASWELL
1851 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1853 const unsigned push_constant_kb
= 16;
1856 const unsigned num_stages
=
1857 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1858 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1860 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1861 * units of 2KB. Incidentally, these are the same platforms that have
1862 * 32KB worth of push constant space.
1864 if (push_constant_kb
== 32)
1865 size_per_stage
&= ~1u;
1867 uint32_t kb_used
= 0;
1868 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1869 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1870 anv_batch_emit(&cmd_buffer
->batch
,
1871 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1872 alloc
._3DCommandSubOpcode
= 18 + i
;
1873 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1874 alloc
.ConstantBufferSize
= push_size
;
1876 kb_used
+= push_size
;
1879 anv_batch_emit(&cmd_buffer
->batch
,
1880 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1881 alloc
.ConstantBufferOffset
= kb_used
;
1882 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1885 cmd_buffer
->state
.push_constant_stages
= stages
;
1887 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1889 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1890 * the next 3DPRIMITIVE command after programming the
1891 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1893 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1894 * pipeline setup, we need to dirty push constants.
1896 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1899 static const struct anv_descriptor
*
1900 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1901 const struct anv_pipeline_binding
*binding
)
1903 assert(binding
->set
< MAX_SETS
);
1904 const struct anv_descriptor_set
*set
=
1905 pipe_state
->descriptors
[binding
->set
];
1906 const uint32_t offset
=
1907 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1908 return &set
->descriptors
[offset
+ binding
->index
];
1912 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1913 const struct anv_pipeline_binding
*binding
)
1915 assert(binding
->set
< MAX_SETS
);
1916 const struct anv_descriptor_set
*set
=
1917 pipe_state
->descriptors
[binding
->set
];
1919 uint32_t dynamic_offset_idx
=
1920 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1921 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1924 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1928 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1929 gl_shader_stage stage
,
1930 struct anv_state
*bt_state
)
1932 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1933 struct anv_cmd_pipeline_state
*pipe_state
;
1934 struct anv_pipeline
*pipeline
;
1935 uint32_t bias
, state_offset
;
1938 case MESA_SHADER_COMPUTE
:
1939 pipe_state
= &cmd_buffer
->state
.compute
.base
;
1943 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
1947 pipeline
= pipe_state
->pipeline
;
1949 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1950 *bt_state
= (struct anv_state
) { 0, };
1954 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1955 if (bias
+ map
->surface_count
== 0) {
1956 *bt_state
= (struct anv_state
) { 0, };
1960 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1961 bias
+ map
->surface_count
,
1963 uint32_t *bt_map
= bt_state
->map
;
1965 if (bt_state
->map
== NULL
)
1966 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1968 if (stage
== MESA_SHADER_COMPUTE
&&
1969 get_cs_prog_data(pipeline
)->uses_num_work_groups
) {
1970 struct anv_state surface_state
;
1972 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1974 const enum isl_format format
=
1975 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1976 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1978 cmd_buffer
->state
.compute
.num_workgroups
,
1981 bt_map
[0] = surface_state
.offset
+ state_offset
;
1982 add_surface_reloc(cmd_buffer
, surface_state
,
1983 cmd_buffer
->state
.compute
.num_workgroups
);
1986 if (map
->surface_count
== 0)
1989 if (map
->image_count
> 0) {
1991 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1992 if (result
!= VK_SUCCESS
)
1995 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1999 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2000 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2002 struct anv_state surface_state
;
2004 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2005 /* Color attachment binding */
2006 assert(stage
== MESA_SHADER_FRAGMENT
);
2007 assert(binding
->binding
== 0);
2008 if (binding
->index
< subpass
->color_count
) {
2009 const unsigned att
=
2010 subpass
->color_attachments
[binding
->index
].attachment
;
2012 /* From the Vulkan 1.0.46 spec:
2014 * "If any color or depth/stencil attachments are
2015 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2018 if (att
== VK_ATTACHMENT_UNUSED
) {
2019 surface_state
= cmd_buffer
->state
.null_surface_state
;
2021 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2024 surface_state
= cmd_buffer
->state
.null_surface_state
;
2027 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2031 const struct anv_descriptor
*desc
=
2032 anv_descriptor_for_binding(pipe_state
, binding
);
2034 switch (desc
->type
) {
2035 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2036 /* Nothing for us to do here */
2039 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2040 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2041 struct anv_surface_state sstate
=
2042 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2043 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2044 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2045 surface_state
= sstate
.state
;
2046 assert(surface_state
.alloc_size
);
2047 add_surface_state_relocs(cmd_buffer
, sstate
);
2050 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2051 assert(stage
== MESA_SHADER_FRAGMENT
);
2052 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2053 /* For depth and stencil input attachments, we treat it like any
2054 * old texture that a user may have bound.
2056 struct anv_surface_state sstate
=
2057 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2058 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2059 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2060 surface_state
= sstate
.state
;
2061 assert(surface_state
.alloc_size
);
2062 add_surface_state_relocs(cmd_buffer
, sstate
);
2064 /* For color input attachments, we create the surface state at
2065 * vkBeginRenderPass time so that we can include aux and clear
2066 * color information.
2068 assert(binding
->input_attachment_index
< subpass
->input_count
);
2069 const unsigned subpass_att
= binding
->input_attachment_index
;
2070 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2071 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2075 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2076 struct anv_surface_state sstate
= (binding
->write_only
)
2077 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2078 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2079 surface_state
= sstate
.state
;
2080 assert(surface_state
.alloc_size
);
2081 add_surface_state_relocs(cmd_buffer
, sstate
);
2083 struct brw_image_param
*image_param
=
2084 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2086 *image_param
= desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2087 image_param
->surface_idx
= bias
+ s
;
2091 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2092 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2093 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2094 surface_state
= desc
->buffer_view
->surface_state
;
2095 assert(surface_state
.alloc_size
);
2096 add_surface_reloc(cmd_buffer
, surface_state
,
2097 desc
->buffer_view
->address
);
2100 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2101 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2102 /* Compute the offset within the buffer */
2103 uint32_t dynamic_offset
=
2104 dynamic_offset_for_binding(pipe_state
, binding
);
2105 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2106 /* Clamp to the buffer size */
2107 offset
= MIN2(offset
, desc
->buffer
->size
);
2108 /* Clamp the range to the buffer size */
2109 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2111 struct anv_address address
=
2112 anv_address_add(desc
->buffer
->address
, offset
);
2115 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2116 enum isl_format format
=
2117 anv_isl_format_for_descriptor_type(desc
->type
);
2119 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2120 format
, address
, range
, 1);
2121 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2125 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2126 surface_state
= (binding
->write_only
)
2127 ? desc
->buffer_view
->writeonly_storage_surface_state
2128 : desc
->buffer_view
->storage_surface_state
;
2129 assert(surface_state
.alloc_size
);
2130 add_surface_reloc(cmd_buffer
, surface_state
,
2131 desc
->buffer_view
->address
);
2133 struct brw_image_param
*image_param
=
2134 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2136 *image_param
= desc
->buffer_view
->storage_image_param
;
2137 image_param
->surface_idx
= bias
+ s
;
2141 assert(!"Invalid descriptor type");
2145 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
2147 assert(image
== map
->image_count
);
2150 anv_state_flush(cmd_buffer
->device
, *bt_state
);
2153 /* The PIPE_CONTROL command description says:
2155 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2156 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2157 * Target Cache Flush by enabling this bit. When render target flush
2158 * is set due to new association of BTI, PS Scoreboard Stall bit must
2159 * be set in this packet."
2161 * FINISHME: Currently we shuffle around the surface states in the binding
2162 * table based on if they are getting used or not. So, we've to do below
2163 * pipe control flush for every binding table upload. Make changes so
2164 * that we do it only when we modify render target surface states.
2166 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2167 pc
.RenderTargetCacheFlushEnable
= true;
2168 pc
.StallAtPixelScoreboard
= true;
2176 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2177 gl_shader_stage stage
,
2178 struct anv_state
*state
)
2180 struct anv_cmd_pipeline_state
*pipe_state
=
2181 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2182 &cmd_buffer
->state
.gfx
.base
;
2183 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2185 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2186 *state
= (struct anv_state
) { 0, };
2190 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2191 if (map
->sampler_count
== 0) {
2192 *state
= (struct anv_state
) { 0, };
2196 uint32_t size
= map
->sampler_count
* 16;
2197 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2199 if (state
->map
== NULL
)
2200 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2202 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2203 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2204 const struct anv_descriptor
*desc
=
2205 anv_descriptor_for_binding(pipe_state
, binding
);
2207 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2208 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2211 struct anv_sampler
*sampler
= desc
->sampler
;
2213 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2214 * happens to be zero.
2216 if (sampler
== NULL
)
2219 memcpy(state
->map
+ (s
* 16),
2220 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2223 anv_state_flush(cmd_buffer
->device
, *state
);
2229 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2231 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2233 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2234 pipeline
->active_stages
;
2236 VkResult result
= VK_SUCCESS
;
2237 anv_foreach_stage(s
, dirty
) {
2238 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2239 if (result
!= VK_SUCCESS
)
2241 result
= emit_binding_table(cmd_buffer
, s
,
2242 &cmd_buffer
->state
.binding_tables
[s
]);
2243 if (result
!= VK_SUCCESS
)
2247 if (result
!= VK_SUCCESS
) {
2248 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2250 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2251 if (result
!= VK_SUCCESS
)
2254 /* Re-emit state base addresses so we get the new surface state base
2255 * address before we start emitting binding tables etc.
2257 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2259 /* Re-emit all active binding tables */
2260 dirty
|= pipeline
->active_stages
;
2261 anv_foreach_stage(s
, dirty
) {
2262 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2263 if (result
!= VK_SUCCESS
) {
2264 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2267 result
= emit_binding_table(cmd_buffer
, s
,
2268 &cmd_buffer
->state
.binding_tables
[s
]);
2269 if (result
!= VK_SUCCESS
) {
2270 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2276 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2282 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2285 static const uint32_t sampler_state_opcodes
[] = {
2286 [MESA_SHADER_VERTEX
] = 43,
2287 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2288 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2289 [MESA_SHADER_GEOMETRY
] = 46,
2290 [MESA_SHADER_FRAGMENT
] = 47,
2291 [MESA_SHADER_COMPUTE
] = 0,
2294 static const uint32_t binding_table_opcodes
[] = {
2295 [MESA_SHADER_VERTEX
] = 38,
2296 [MESA_SHADER_TESS_CTRL
] = 39,
2297 [MESA_SHADER_TESS_EVAL
] = 40,
2298 [MESA_SHADER_GEOMETRY
] = 41,
2299 [MESA_SHADER_FRAGMENT
] = 42,
2300 [MESA_SHADER_COMPUTE
] = 0,
2303 anv_foreach_stage(s
, stages
) {
2304 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2305 assert(binding_table_opcodes
[s
] > 0);
2307 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2308 anv_batch_emit(&cmd_buffer
->batch
,
2309 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2310 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2311 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2315 /* Always emit binding table pointers if we're asked to, since on SKL
2316 * this is what flushes push constants. */
2317 anv_batch_emit(&cmd_buffer
->batch
,
2318 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2319 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2320 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2326 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2327 VkShaderStageFlags dirty_stages
)
2329 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2330 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2332 static const uint32_t push_constant_opcodes
[] = {
2333 [MESA_SHADER_VERTEX
] = 21,
2334 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2335 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2336 [MESA_SHADER_GEOMETRY
] = 22,
2337 [MESA_SHADER_FRAGMENT
] = 23,
2338 [MESA_SHADER_COMPUTE
] = 0,
2341 VkShaderStageFlags flushed
= 0;
2343 anv_foreach_stage(stage
, dirty_stages
) {
2344 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2345 assert(push_constant_opcodes
[stage
] > 0);
2347 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2348 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2350 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2351 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2352 const struct brw_stage_prog_data
*prog_data
=
2353 pipeline
->shaders
[stage
]->prog_data
;
2354 const struct anv_pipeline_bind_map
*bind_map
=
2355 &pipeline
->shaders
[stage
]->bind_map
;
2357 /* The Skylake PRM contains the following restriction:
2359 * "The driver must ensure The following case does not occur
2360 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2361 * buffer 3 read length equal to zero committed followed by a
2362 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2365 * To avoid this, we program the buffers in the highest slots.
2366 * This way, slot 0 is only used if slot 3 is also used.
2370 for (int i
= 3; i
>= 0; i
--) {
2371 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2372 if (range
->length
== 0)
2375 const unsigned surface
=
2376 prog_data
->binding_table
.ubo_start
+ range
->block
;
2378 assert(surface
<= bind_map
->surface_count
);
2379 const struct anv_pipeline_binding
*binding
=
2380 &bind_map
->surface_to_descriptor
[surface
];
2382 const struct anv_descriptor
*desc
=
2383 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2385 struct anv_address read_addr
;
2387 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2388 read_len
= MIN2(range
->length
,
2389 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2390 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2393 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2395 uint32_t dynamic_offset
=
2396 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2397 uint32_t buf_offset
=
2398 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2399 uint32_t buf_range
=
2400 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2402 read_len
= MIN2(range
->length
,
2403 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2404 read_addr
= anv_address_add(desc
->buffer
->address
,
2405 buf_offset
+ range
->start
* 32);
2409 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2410 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2415 struct anv_state state
=
2416 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2418 if (state
.alloc_size
> 0) {
2419 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2420 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2421 .offset
= state
.offset
,
2423 c
.ConstantBody
.ReadLength
[n
] =
2424 DIV_ROUND_UP(state
.alloc_size
, 32);
2427 /* For Ivy Bridge, the push constants packets have a different
2428 * rule that would require us to iterate in the other direction
2429 * and possibly mess around with dynamic state base address.
2430 * Don't bother; just emit regular push constants at n = 0.
2432 struct anv_state state
=
2433 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2435 if (state
.alloc_size
> 0) {
2436 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2437 c
.ConstantBody
.ReadLength
[0] =
2438 DIV_ROUND_UP(state
.alloc_size
, 32);
2444 flushed
|= mesa_to_vk_shader_stage(stage
);
2447 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2451 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2453 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2456 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2458 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2460 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2462 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2465 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2466 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2468 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2469 GENX(3DSTATE_VERTEX_BUFFERS
));
2471 for_each_bit(vb
, vb_emit
) {
2472 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2473 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2475 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2476 .VertexBufferIndex
= vb
,
2479 .MemoryObjectControlState
= GENX(MOCS
),
2481 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
2482 /* Our implementation of VK_KHR_multiview uses instancing to draw
2483 * the different views. If the client asks for instancing, we
2484 * need to use the Instance Data Step Rate to ensure that we
2485 * repeat the client's per-instance data once for each view.
2487 .InstanceDataStepRate
= anv_subpass_view_count(pipeline
->subpass
),
2488 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2491 .AddressModifyEnable
= true,
2492 .BufferPitch
= pipeline
->binding_stride
[vb
],
2493 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2496 .BufferSize
= buffer
->size
- offset
2498 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2502 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2507 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2509 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2510 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2512 /* The exact descriptor layout is pulled from the pipeline, so we need
2513 * to re-emit binding tables on every pipeline change.
2515 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2517 /* If the pipeline changed, we may need to re-allocate push constant
2520 cmd_buffer_alloc_push_constants(cmd_buffer
);
2524 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2525 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2526 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2528 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2529 * stall needs to be sent just prior to any 3DSTATE_VS,
2530 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2531 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2532 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2533 * PIPE_CONTROL needs to be sent before any combination of VS
2534 * associated 3DSTATE."
2536 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2537 pc
.DepthStallEnable
= true;
2538 pc
.PostSyncOperation
= WriteImmediateData
;
2540 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2545 /* Render targets live in the same binding table as fragment descriptors */
2546 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2547 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2549 /* We emit the binding tables and sampler tables first, then emit push
2550 * constants and then finally emit binding table and sampler table
2551 * pointers. It has to happen in this order, since emitting the binding
2552 * tables may change the push constants (in case of storage images). After
2553 * emitting push constants, on SKL+ we have to emit the corresponding
2554 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2557 if (cmd_buffer
->state
.descriptors_dirty
)
2558 dirty
= flush_descriptor_sets(cmd_buffer
);
2560 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2561 /* Because we're pushing UBOs, we have to push whenever either
2562 * descriptors or push constants is dirty.
2564 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2565 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2566 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2570 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2572 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2573 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2575 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2576 ANV_CMD_DIRTY_PIPELINE
)) {
2577 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2578 pipeline
->depth_clamp_enable
);
2581 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
2582 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2584 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2586 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2590 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2591 struct anv_address addr
,
2592 uint32_t size
, uint32_t index
)
2594 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2595 GENX(3DSTATE_VERTEX_BUFFERS
));
2597 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2598 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2599 .VertexBufferIndex
= index
,
2600 .AddressModifyEnable
= true,
2603 .MemoryObjectControlState
= GENX(MOCS
),
2604 .BufferStartingAddress
= addr
,
2607 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
2608 .BufferStartingAddress
= addr
,
2609 .EndAddress
= anv_address_add(addr
, size
),
2615 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2616 struct anv_address addr
)
2618 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2622 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2623 uint32_t base_vertex
, uint32_t base_instance
)
2625 struct anv_state id_state
=
2626 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2628 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2629 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2631 anv_state_flush(cmd_buffer
->device
, id_state
);
2633 struct anv_address addr
= {
2634 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2635 .offset
= id_state
.offset
,
2638 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2642 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2644 struct anv_state state
=
2645 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2647 ((uint32_t *)state
.map
)[0] = draw_index
;
2649 anv_state_flush(cmd_buffer
->device
, state
);
2651 struct anv_address addr
= {
2652 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2653 .offset
= state
.offset
,
2656 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2660 VkCommandBuffer commandBuffer
,
2661 uint32_t vertexCount
,
2662 uint32_t instanceCount
,
2663 uint32_t firstVertex
,
2664 uint32_t firstInstance
)
2666 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2667 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2668 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2670 if (anv_batch_has_error(&cmd_buffer
->batch
))
2673 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2675 if (vs_prog_data
->uses_firstvertex
||
2676 vs_prog_data
->uses_baseinstance
)
2677 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2678 if (vs_prog_data
->uses_drawid
)
2679 emit_draw_index(cmd_buffer
, 0);
2681 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2682 * different views. We need to multiply instanceCount by the view count.
2684 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2686 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2687 prim
.VertexAccessType
= SEQUENTIAL
;
2688 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2689 prim
.VertexCountPerInstance
= vertexCount
;
2690 prim
.StartVertexLocation
= firstVertex
;
2691 prim
.InstanceCount
= instanceCount
;
2692 prim
.StartInstanceLocation
= firstInstance
;
2693 prim
.BaseVertexLocation
= 0;
2697 void genX(CmdDrawIndexed
)(
2698 VkCommandBuffer commandBuffer
,
2699 uint32_t indexCount
,
2700 uint32_t instanceCount
,
2701 uint32_t firstIndex
,
2702 int32_t vertexOffset
,
2703 uint32_t firstInstance
)
2705 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2706 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2707 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2709 if (anv_batch_has_error(&cmd_buffer
->batch
))
2712 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2714 if (vs_prog_data
->uses_firstvertex
||
2715 vs_prog_data
->uses_baseinstance
)
2716 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2717 if (vs_prog_data
->uses_drawid
)
2718 emit_draw_index(cmd_buffer
, 0);
2720 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2721 * different views. We need to multiply instanceCount by the view count.
2723 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2725 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2726 prim
.VertexAccessType
= RANDOM
;
2727 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2728 prim
.VertexCountPerInstance
= indexCount
;
2729 prim
.StartVertexLocation
= firstIndex
;
2730 prim
.InstanceCount
= instanceCount
;
2731 prim
.StartInstanceLocation
= firstInstance
;
2732 prim
.BaseVertexLocation
= vertexOffset
;
2736 /* Auto-Draw / Indirect Registers */
2737 #define GEN7_3DPRIM_END_OFFSET 0x2420
2738 #define GEN7_3DPRIM_START_VERTEX 0x2430
2739 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2740 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2741 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2742 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2744 /* MI_MATH only exists on Haswell+ */
2745 #if GEN_IS_HASWELL || GEN_GEN >= 8
2747 /* Emit dwords to multiply GPR0 by N */
2749 build_alu_multiply_gpr0(uint32_t *dw
, unsigned *dw_count
, uint32_t N
)
2751 VK_OUTARRAY_MAKE(out
, dw
, dw_count
);
2753 #define append_alu(opcode, operand1, operand2) \
2754 vk_outarray_append(&out, alu_dw) *alu_dw = mi_alu(opcode, operand1, operand2)
2757 unsigned top_bit
= 31 - __builtin_clz(N
);
2758 for (int i
= top_bit
- 1; i
>= 0; i
--) {
2759 /* We get our initial data in GPR0 and we write the final data out to
2760 * GPR0 but we use GPR1 as our scratch register.
2762 unsigned src_reg
= i
== top_bit
- 1 ? MI_ALU_REG0
: MI_ALU_REG1
;
2763 unsigned dst_reg
= i
== 0 ? MI_ALU_REG0
: MI_ALU_REG1
;
2765 /* Shift the current value left by 1 */
2766 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, src_reg
);
2767 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, src_reg
);
2768 append_alu(MI_ALU_ADD
, 0, 0);
2771 /* Store ACCU to R1 and add R0 to R1 */
2772 append_alu(MI_ALU_STORE
, MI_ALU_REG1
, MI_ALU_ACCU
);
2773 append_alu(MI_ALU_LOAD
, MI_ALU_SRCA
, MI_ALU_REG0
);
2774 append_alu(MI_ALU_LOAD
, MI_ALU_SRCB
, MI_ALU_REG1
);
2775 append_alu(MI_ALU_ADD
, 0, 0);
2778 append_alu(MI_ALU_STORE
, dst_reg
, MI_ALU_ACCU
);
2785 emit_mul_gpr0(struct anv_batch
*batch
, uint32_t N
)
2787 uint32_t num_dwords
;
2788 build_alu_multiply_gpr0(NULL
, &num_dwords
, N
);
2790 uint32_t *dw
= anv_batch_emitn(batch
, 1 + num_dwords
, GENX(MI_MATH
));
2791 build_alu_multiply_gpr0(dw
+ 1, &num_dwords
, N
);
2794 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2797 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2798 struct anv_address addr
,
2801 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2803 emit_lrm(batch
, GEN7_3DPRIM_VERTEX_COUNT
, addr
.bo
, addr
.offset
);
2805 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2806 if (view_count
> 1) {
2807 #if GEN_IS_HASWELL || GEN_GEN >= 8
2808 emit_lrm(batch
, CS_GPR(0), addr
.bo
, addr
.offset
+ 4);
2809 emit_mul_gpr0(batch
, view_count
);
2810 emit_lrr(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, CS_GPR(0));
2812 anv_finishme("Multiview + indirect draw requires MI_MATH; "
2813 "MI_MATH is not supported on Ivy Bridge");
2814 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, addr
.bo
, addr
.offset
+ 4);
2817 emit_lrm(batch
, GEN7_3DPRIM_INSTANCE_COUNT
, addr
.bo
, addr
.offset
+ 4);
2820 emit_lrm(batch
, GEN7_3DPRIM_START_VERTEX
, addr
.bo
, addr
.offset
+ 8);
2823 emit_lrm(batch
, GEN7_3DPRIM_BASE_VERTEX
, addr
.bo
, addr
.offset
+ 12);
2824 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, addr
.bo
, addr
.offset
+ 16);
2826 emit_lrm(batch
, GEN7_3DPRIM_START_INSTANCE
, addr
.bo
, addr
.offset
+ 12);
2827 emit_lri(batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
2831 void genX(CmdDrawIndirect
)(
2832 VkCommandBuffer commandBuffer
,
2834 VkDeviceSize offset
,
2838 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2839 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2840 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2841 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2843 if (anv_batch_has_error(&cmd_buffer
->batch
))
2846 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2848 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2849 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2851 if (vs_prog_data
->uses_firstvertex
||
2852 vs_prog_data
->uses_baseinstance
)
2853 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
2854 if (vs_prog_data
->uses_drawid
)
2855 emit_draw_index(cmd_buffer
, i
);
2857 load_indirect_parameters(cmd_buffer
, draw
, false);
2859 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2860 prim
.IndirectParameterEnable
= true;
2861 prim
.VertexAccessType
= SEQUENTIAL
;
2862 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2869 void genX(CmdDrawIndexedIndirect
)(
2870 VkCommandBuffer commandBuffer
,
2872 VkDeviceSize offset
,
2876 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2877 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
2878 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2879 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2881 if (anv_batch_has_error(&cmd_buffer
->batch
))
2884 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2886 for (uint32_t i
= 0; i
< drawCount
; i
++) {
2887 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
2889 /* TODO: We need to stomp base vertex to 0 somehow */
2890 if (vs_prog_data
->uses_firstvertex
||
2891 vs_prog_data
->uses_baseinstance
)
2892 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
2893 if (vs_prog_data
->uses_drawid
)
2894 emit_draw_index(cmd_buffer
, i
);
2896 load_indirect_parameters(cmd_buffer
, draw
, true);
2898 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2899 prim
.IndirectParameterEnable
= true;
2900 prim
.VertexAccessType
= RANDOM
;
2901 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2909 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
2911 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2912 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
2915 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2916 if (result
!= VK_SUCCESS
) {
2917 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2919 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2920 if (result
!= VK_SUCCESS
)
2923 /* Re-emit state base addresses so we get the new surface state base
2924 * address before we start emitting binding tables etc.
2926 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2928 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
2929 if (result
!= VK_SUCCESS
) {
2930 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2935 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
2936 if (result
!= VK_SUCCESS
) {
2937 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2941 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
2942 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
2943 .BindingTablePointer
= surfaces
.offset
,
2944 .SamplerStatePointer
= samplers
.offset
,
2946 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
2948 struct anv_state state
=
2949 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
2950 pipeline
->interface_descriptor_data
,
2951 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
2954 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
2955 anv_batch_emit(&cmd_buffer
->batch
,
2956 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
2957 mid
.InterfaceDescriptorTotalLength
= size
;
2958 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
2965 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2967 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
2968 MAYBE_UNUSED VkResult result
;
2970 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
2972 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2974 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
2976 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
2977 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
2979 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
2980 * the only bits that are changed are scoreboard related: Scoreboard
2981 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
2982 * these scoreboard related states, a MEDIA_STATE_FLUSH is
2985 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2986 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2988 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2991 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
2992 cmd_buffer
->state
.compute
.pipeline_dirty
) {
2993 /* FIXME: figure out descriptors for gen7 */
2994 result
= flush_compute_descriptor_set(cmd_buffer
);
2995 if (result
!= VK_SUCCESS
)
2998 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3001 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3002 struct anv_state push_state
=
3003 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3005 if (push_state
.alloc_size
) {
3006 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3007 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3008 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3013 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3015 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3021 verify_cmd_parser(const struct anv_device
*device
,
3022 int required_version
,
3023 const char *function
)
3025 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3026 return vk_errorf(device
->instance
, device
->instance
,
3027 VK_ERROR_FEATURE_NOT_PRESENT
,
3028 "cmd parser version %d is required for %s",
3029 required_version
, function
);
3038 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3039 uint32_t baseGroupX
,
3040 uint32_t baseGroupY
,
3041 uint32_t baseGroupZ
)
3043 if (anv_batch_has_error(&cmd_buffer
->batch
))
3047 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3048 base_work_group_id
);
3049 if (result
!= VK_SUCCESS
) {
3050 cmd_buffer
->batch
.status
= result
;
3054 struct anv_push_constants
*push
=
3055 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3056 if (push
->base_work_group_id
[0] != baseGroupX
||
3057 push
->base_work_group_id
[1] != baseGroupY
||
3058 push
->base_work_group_id
[2] != baseGroupZ
) {
3059 push
->base_work_group_id
[0] = baseGroupX
;
3060 push
->base_work_group_id
[1] = baseGroupY
;
3061 push
->base_work_group_id
[2] = baseGroupZ
;
3063 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3067 void genX(CmdDispatch
)(
3068 VkCommandBuffer commandBuffer
,
3073 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3076 void genX(CmdDispatchBase
)(
3077 VkCommandBuffer commandBuffer
,
3078 uint32_t baseGroupX
,
3079 uint32_t baseGroupY
,
3080 uint32_t baseGroupZ
,
3081 uint32_t groupCountX
,
3082 uint32_t groupCountY
,
3083 uint32_t groupCountZ
)
3085 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3086 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3087 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3089 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3090 baseGroupY
, baseGroupZ
);
3092 if (anv_batch_has_error(&cmd_buffer
->batch
))
3095 if (prog_data
->uses_num_work_groups
) {
3096 struct anv_state state
=
3097 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3098 uint32_t *sizes
= state
.map
;
3099 sizes
[0] = groupCountX
;
3100 sizes
[1] = groupCountY
;
3101 sizes
[2] = groupCountZ
;
3102 anv_state_flush(cmd_buffer
->device
, state
);
3103 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3104 .bo
= &cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3105 .offset
= state
.offset
,
3109 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3111 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3112 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3113 ggw
.ThreadDepthCounterMaximum
= 0;
3114 ggw
.ThreadHeightCounterMaximum
= 0;
3115 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3116 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3117 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3118 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3119 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3120 ggw
.BottomExecutionMask
= 0xffffffff;
3123 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3126 #define GPGPU_DISPATCHDIMX 0x2500
3127 #define GPGPU_DISPATCHDIMY 0x2504
3128 #define GPGPU_DISPATCHDIMZ 0x2508
3130 void genX(CmdDispatchIndirect
)(
3131 VkCommandBuffer commandBuffer
,
3133 VkDeviceSize offset
)
3135 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3136 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3137 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3138 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3139 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3140 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3142 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3145 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3146 * indirect dispatch registers to be written.
3148 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3149 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3153 if (prog_data
->uses_num_work_groups
)
3154 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3156 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3158 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, addr
.bo
, addr
.offset
);
3159 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, addr
.bo
, addr
.offset
+ 4);
3160 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, addr
.bo
, addr
.offset
+ 8);
3163 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
3164 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
3165 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
3166 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
3168 /* Load compute_dispatch_indirect_x_size into SRC0 */
3169 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 0);
3171 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3172 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3173 mip
.LoadOperation
= LOAD_LOAD
;
3174 mip
.CombineOperation
= COMBINE_SET
;
3175 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3178 /* Load compute_dispatch_indirect_y_size into SRC0 */
3179 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 4);
3181 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3182 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3183 mip
.LoadOperation
= LOAD_LOAD
;
3184 mip
.CombineOperation
= COMBINE_OR
;
3185 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3188 /* Load compute_dispatch_indirect_z_size into SRC0 */
3189 emit_lrm(batch
, MI_PREDICATE_SRC0
, addr
.bo
, addr
.offset
+ 8);
3191 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3192 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3193 mip
.LoadOperation
= LOAD_LOAD
;
3194 mip
.CombineOperation
= COMBINE_OR
;
3195 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3198 /* predicate = !predicate; */
3199 #define COMPARE_FALSE 1
3200 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3201 mip
.LoadOperation
= LOAD_LOADINV
;
3202 mip
.CombineOperation
= COMBINE_OR
;
3203 mip
.CompareOperation
= COMPARE_FALSE
;
3207 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3208 ggw
.IndirectParameterEnable
= true;
3209 ggw
.PredicateEnable
= GEN_GEN
<= 7;
3210 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3211 ggw
.ThreadDepthCounterMaximum
= 0;
3212 ggw
.ThreadHeightCounterMaximum
= 0;
3213 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3214 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3215 ggw
.BottomExecutionMask
= 0xffffffff;
3218 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3222 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3225 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3227 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3230 #if GEN_GEN >= 8 && GEN_GEN < 10
3231 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3233 * Software must clear the COLOR_CALC_STATE Valid field in
3234 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3235 * with Pipeline Select set to GPGPU.
3237 * The internal hardware docs recommend the same workaround for Gen9
3240 if (pipeline
== GPGPU
)
3241 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3244 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3245 * PIPELINE_SELECT [DevBWR+]":
3249 * Software must ensure all the write caches are flushed through a
3250 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3251 * command to invalidate read only caches prior to programming
3252 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3254 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3255 pc
.RenderTargetCacheFlushEnable
= true;
3256 pc
.DepthCacheFlushEnable
= true;
3257 pc
.DCFlushEnable
= true;
3258 pc
.PostSyncOperation
= NoWrite
;
3259 pc
.CommandStreamerStallEnable
= true;
3262 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3263 pc
.TextureCacheInvalidationEnable
= true;
3264 pc
.ConstantCacheInvalidationEnable
= true;
3265 pc
.StateCacheInvalidationEnable
= true;
3266 pc
.InstructionCacheInvalidateEnable
= true;
3267 pc
.PostSyncOperation
= NoWrite
;
3270 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3274 ps
.PipelineSelection
= pipeline
;
3278 if (devinfo
->is_geminilake
) {
3281 * "This chicken bit works around a hardware issue with barrier logic
3282 * encountered when switching between GPGPU and 3D pipelines. To
3283 * workaround the issue, this mode bit should be set after a pipeline
3287 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3289 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3290 : GLK_BARRIER_MODE_3D_HULL
,
3291 .GLKBarrierModeMask
= 1);
3292 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3296 cmd_buffer
->state
.current_pipeline
= pipeline
;
3300 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3302 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3306 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3308 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3312 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3317 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3319 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3320 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3321 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3322 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3323 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3324 * Depth Flush Bit set, followed by another pipelined depth stall
3325 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3326 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3327 * via a preceding MI_FLUSH)."
3329 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3330 pipe
.DepthStallEnable
= true;
3332 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3333 pipe
.DepthCacheFlushEnable
= true;
3335 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3336 pipe
.DepthStallEnable
= true;
3341 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3343 struct anv_device
*device
= cmd_buffer
->device
;
3344 const struct anv_image_view
*iview
=
3345 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3346 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3348 /* FIXME: Width and Height are wrong */
3350 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3352 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3353 device
->isl_dev
.ds
.size
/ 4);
3357 struct isl_depth_stencil_hiz_emit_info info
= {
3358 .mocs
= device
->default_mocs
,
3362 info
.view
= &iview
->planes
[0].isl
;
3364 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3365 uint32_t depth_plane
=
3366 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3367 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3369 info
.depth_surf
= &surface
->isl
;
3371 info
.depth_address
=
3372 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3373 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3374 image
->planes
[depth_plane
].address
.bo
,
3375 image
->planes
[depth_plane
].address
.offset
+
3379 cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
3380 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3381 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3382 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3385 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3386 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3387 image
->planes
[depth_plane
].address
.bo
,
3388 image
->planes
[depth_plane
].address
.offset
+
3389 image
->planes
[depth_plane
].aux_surface
.offset
);
3391 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3395 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3396 uint32_t stencil_plane
=
3397 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3398 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3400 info
.stencil_surf
= &surface
->isl
;
3402 info
.stencil_address
=
3403 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3404 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3405 image
->planes
[stencil_plane
].address
.bo
,
3406 image
->planes
[stencil_plane
].address
.offset
+
3410 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3412 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3416 * This ANDs the view mask of the current subpass with the pending clear
3417 * views in the attachment to get the mask of views active in the subpass
3418 * that still need to be cleared.
3420 static inline uint32_t
3421 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3422 const struct anv_attachment_state
*att_state
)
3424 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3428 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3429 const struct anv_attachment_state
*att_state
)
3431 if (!cmd_state
->subpass
->view_mask
)
3434 uint32_t pending_clear_mask
=
3435 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3437 return pending_clear_mask
& 1;
3441 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3444 const uint32_t last_subpass_idx
=
3445 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3446 const struct anv_subpass
*last_subpass
=
3447 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3448 return last_subpass
== cmd_state
->subpass
;
3452 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3453 uint32_t subpass_id
)
3455 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3456 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3457 cmd_state
->subpass
= subpass
;
3459 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3461 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3462 * different views. If the client asks for instancing, we need to use the
3463 * Instance Data Step Rate to ensure that we repeat the client's
3464 * per-instance data once for each view. Since this bit is in
3465 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
3469 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
3471 /* It is possible to start a render pass with an old pipeline. Because the
3472 * render pass and subpass index are both baked into the pipeline, this is
3473 * highly unlikely. In order to do so, it requires that you have a render
3474 * pass with a single subpass and that you use that render pass twice
3475 * back-to-back and use the same pipeline at the start of the second render
3476 * pass as at the end of the first. In order to avoid unpredictable issues
3477 * with this edge case, we just dirty the pipeline at the start of every
3480 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
3482 /* Accumulate any subpass flushes that need to happen before the subpass */
3483 cmd_buffer
->state
.pending_pipe_bits
|=
3484 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
3486 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
3487 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3489 bool is_multiview
= subpass
->view_mask
!= 0;
3491 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3492 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3493 if (a
== VK_ATTACHMENT_UNUSED
)
3496 assert(a
< cmd_state
->pass
->attachment_count
);
3497 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3499 struct anv_image_view
*iview
= fb
->attachments
[a
];
3500 const struct anv_image
*image
= iview
->image
;
3502 /* A resolve is necessary before use as an input attachment if the clear
3503 * color or auxiliary buffer usage isn't supported by the sampler.
3505 const bool input_needs_resolve
=
3506 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
3507 att_state
->input_aux_usage
!= att_state
->aux_usage
;
3509 VkImageLayout target_layout
;
3510 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
3511 !input_needs_resolve
) {
3512 /* Layout transitions before the final only help to enable sampling
3513 * as an input attachment. If the input attachment supports sampling
3514 * using the auxiliary surface, we can skip such transitions by
3515 * making the target layout one that is CCS-aware.
3517 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
3519 target_layout
= subpass
->attachments
[i
].layout
;
3522 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3523 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3525 uint32_t base_layer
, layer_count
;
3526 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3528 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3529 iview
->planes
[0].isl
.base_level
);
3531 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3532 layer_count
= fb
->layers
;
3535 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3536 iview
->planes
[0].isl
.base_level
, 1,
3537 base_layer
, layer_count
,
3538 att_state
->current_layout
, target_layout
);
3539 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3540 transition_depth_buffer(cmd_buffer
, image
,
3541 att_state
->current_layout
, target_layout
);
3542 att_state
->aux_usage
=
3543 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
3544 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
3546 att_state
->current_layout
= target_layout
;
3548 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3549 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3551 /* Multi-planar images are not supported as attachments */
3552 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3553 assert(image
->n_planes
== 1);
3555 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
3556 uint32_t clear_layer_count
= fb
->layers
;
3558 if (att_state
->fast_clear
&&
3559 do_first_layer_clear(cmd_state
, att_state
)) {
3560 /* We only support fast-clears on the first layer */
3561 assert(iview
->planes
[0].isl
.base_level
== 0);
3562 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3564 union isl_color_value clear_color
= {};
3565 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
3566 if (iview
->image
->samples
== 1) {
3567 anv_image_ccs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3568 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3572 anv_image_mcs_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3573 0, 1, ISL_AUX_OP_FAST_CLEAR
,
3578 clear_layer_count
--;
3580 att_state
->pending_clear_views
&= ~1;
3582 if (att_state
->clear_color_is_zero
) {
3583 /* This image has the auxiliary buffer enabled. We can mark the
3584 * subresource as not needing a resolve because the clear color
3585 * will match what's in every RENDER_SURFACE_STATE object when
3586 * it's being used for sampling.
3588 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3589 VK_IMAGE_ASPECT_COLOR_BIT
,
3590 ANV_FAST_CLEAR_DEFAULT_VALUE
);
3592 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
3593 VK_IMAGE_ASPECT_COLOR_BIT
,
3594 ANV_FAST_CLEAR_ANY
);
3598 /* From the VkFramebufferCreateInfo spec:
3600 * "If the render pass uses multiview, then layers must be one and each
3601 * attachment requires a number of layers that is greater than the
3602 * maximum bit index set in the view mask in the subpasses in which it
3605 * So if multiview is active we ignore the number of layers in the
3606 * framebuffer and instead we honor the view mask from the subpass.
3609 assert(image
->n_planes
== 1);
3610 uint32_t pending_clear_mask
=
3611 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3614 for_each_bit(layer_idx
, pending_clear_mask
) {
3616 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3618 anv_image_clear_color(cmd_buffer
, image
,
3619 VK_IMAGE_ASPECT_COLOR_BIT
,
3620 att_state
->aux_usage
,
3621 iview
->planes
[0].isl
.format
,
3622 iview
->planes
[0].isl
.swizzle
,
3623 iview
->planes
[0].isl
.base_level
,
3626 vk_to_isl_color(att_state
->clear_value
.color
));
3629 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3630 } else if (clear_layer_count
> 0) {
3631 assert(image
->n_planes
== 1);
3632 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3633 att_state
->aux_usage
,
3634 iview
->planes
[0].isl
.format
,
3635 iview
->planes
[0].isl
.swizzle
,
3636 iview
->planes
[0].isl
.base_level
,
3637 base_clear_layer
, clear_layer_count
,
3639 vk_to_isl_color(att_state
->clear_value
.color
));
3641 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
3642 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3643 if (att_state
->fast_clear
&& !is_multiview
) {
3644 /* We currently only support HiZ for single-layer images */
3645 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3646 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
3647 assert(iview
->planes
[0].isl
.base_level
== 0);
3648 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
3649 assert(fb
->layers
== 1);
3652 anv_image_hiz_clear(cmd_buffer
, image
,
3653 att_state
->pending_clear_aspects
,
3654 iview
->planes
[0].isl
.base_level
,
3655 iview
->planes
[0].isl
.base_array_layer
,
3656 fb
->layers
, render_area
,
3657 att_state
->clear_value
.depthStencil
.stencil
);
3658 } else if (is_multiview
) {
3659 uint32_t pending_clear_mask
=
3660 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3663 for_each_bit(layer_idx
, pending_clear_mask
) {
3665 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
3667 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3668 att_state
->pending_clear_aspects
,
3669 att_state
->aux_usage
,
3670 iview
->planes
[0].isl
.base_level
,
3673 att_state
->clear_value
.depthStencil
.depth
,
3674 att_state
->clear_value
.depthStencil
.stencil
);
3677 att_state
->pending_clear_views
&= ~pending_clear_mask
;
3679 anv_image_clear_depth_stencil(cmd_buffer
, image
,
3680 att_state
->pending_clear_aspects
,
3681 att_state
->aux_usage
,
3682 iview
->planes
[0].isl
.base_level
,
3683 iview
->planes
[0].isl
.base_array_layer
,
3684 fb
->layers
, render_area
,
3685 att_state
->clear_value
.depthStencil
.depth
,
3686 att_state
->clear_value
.depthStencil
.stencil
);
3689 assert(att_state
->pending_clear_aspects
== 0);
3693 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
3694 image
->planes
[0].aux_surface
.isl
.size
> 0 &&
3695 iview
->planes
[0].isl
.base_level
== 0 &&
3696 iview
->planes
[0].isl
.base_array_layer
== 0) {
3697 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
3698 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
3699 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3700 false /* copy to ss */);
3703 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
3704 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
3705 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
3706 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3707 false /* copy to ss */);
3711 if (subpass
->attachments
[i
].usage
==
3712 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
3713 /* We assume that if we're starting a subpass, we're going to do some
3714 * rendering so we may end up with compressed data.
3716 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
3717 VK_IMAGE_ASPECT_COLOR_BIT
,
3718 att_state
->aux_usage
,
3719 iview
->planes
[0].isl
.base_level
,
3720 iview
->planes
[0].isl
.base_array_layer
,
3722 } else if (subpass
->attachments
[i
].usage
==
3723 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
3724 /* We may be writing depth or stencil so we need to mark the surface.
3725 * Unfortunately, there's no way to know at this point whether the
3726 * depth or stencil tests used will actually write to the surface.
3728 * Even though stencil may be plane 1, it always shares a base_level
3731 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
3732 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3733 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3734 VK_IMAGE_ASPECT_DEPTH_BIT
,
3735 att_state
->aux_usage
,
3736 ds_view
->base_level
,
3737 ds_view
->base_array_layer
,
3740 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
3741 /* Even though stencil may be plane 1, it always shares a
3742 * base_level with depth.
3744 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
3745 VK_IMAGE_ASPECT_STENCIL_BIT
,
3747 ds_view
->base_level
,
3748 ds_view
->base_array_layer
,
3753 /* If multiview is enabled, then we are only done clearing when we no
3754 * longer have pending layers to clear, or when we have processed the
3755 * last subpass that uses this attachment.
3757 if (!is_multiview
||
3758 att_state
->pending_clear_views
== 0 ||
3759 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
3760 att_state
->pending_clear_aspects
= 0;
3763 att_state
->pending_load_aspects
= 0;
3766 cmd_buffer_emit_depth_stencil(cmd_buffer
);
3770 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
3772 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3773 struct anv_subpass
*subpass
= cmd_state
->subpass
;
3774 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
3776 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
3778 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
3779 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
3780 const uint32_t a
= subpass
->attachments
[i
].attachment
;
3781 if (a
== VK_ATTACHMENT_UNUSED
)
3784 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
3787 assert(a
< cmd_state
->pass
->attachment_count
);
3788 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
3789 struct anv_image_view
*iview
= fb
->attachments
[a
];
3790 const struct anv_image
*image
= iview
->image
;
3792 /* Transition the image into the final layout for this render pass */
3793 VkImageLayout target_layout
=
3794 cmd_state
->pass
->attachments
[a
].final_layout
;
3796 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
3797 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
3799 uint32_t base_layer
, layer_count
;
3800 if (image
->type
== VK_IMAGE_TYPE_3D
) {
3802 layer_count
= anv_minify(iview
->image
->extent
.depth
,
3803 iview
->planes
[0].isl
.base_level
);
3805 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
3806 layer_count
= fb
->layers
;
3809 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
3810 iview
->planes
[0].isl
.base_level
, 1,
3811 base_layer
, layer_count
,
3812 att_state
->current_layout
, target_layout
);
3813 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
3814 transition_depth_buffer(cmd_buffer
, image
,
3815 att_state
->current_layout
, target_layout
);
3819 /* Accumulate any subpass flushes that need to happen after the subpass.
3820 * Yes, they do get accumulated twice in the NextSubpass case but since
3821 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
3822 * ORing the bits in twice so it's harmless.
3824 cmd_buffer
->state
.pending_pipe_bits
|=
3825 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
3828 void genX(CmdBeginRenderPass
)(
3829 VkCommandBuffer commandBuffer
,
3830 const VkRenderPassBeginInfo
* pRenderPassBegin
,
3831 VkSubpassContents contents
)
3833 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3834 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
3835 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
3837 cmd_buffer
->state
.framebuffer
= framebuffer
;
3838 cmd_buffer
->state
.pass
= pass
;
3839 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
3841 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
3843 /* If we failed to setup the attachments we should not try to go further */
3844 if (result
!= VK_SUCCESS
) {
3845 assert(anv_batch_has_error(&cmd_buffer
->batch
));
3849 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3851 cmd_buffer_begin_subpass(cmd_buffer
, 0);
3854 void genX(CmdNextSubpass
)(
3855 VkCommandBuffer commandBuffer
,
3856 VkSubpassContents contents
)
3858 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3860 if (anv_batch_has_error(&cmd_buffer
->batch
))
3863 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3865 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
3866 cmd_buffer_end_subpass(cmd_buffer
);
3867 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
3870 void genX(CmdEndRenderPass
)(
3871 VkCommandBuffer commandBuffer
)
3873 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3875 if (anv_batch_has_error(&cmd_buffer
->batch
))
3878 cmd_buffer_end_subpass(cmd_buffer
);
3880 cmd_buffer
->state
.hiz_enabled
= false;
3883 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
3886 /* Remove references to render pass specific state. This enables us to
3887 * detect whether or not we're in a renderpass.
3889 cmd_buffer
->state
.framebuffer
= NULL
;
3890 cmd_buffer
->state
.pass
= NULL
;
3891 cmd_buffer
->state
.subpass
= NULL
;