2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
38 * - GPR 14 for secondary command buffer returns
39 * - GPR 15 for conditional rendering
41 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
42 #define __gen_get_batch_dwords anv_batch_emit_dwords
43 #define __gen_address_offset anv_address_add
44 #include "common/gen_mi_builder.h"
46 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
50 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
52 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
53 lri
.RegisterOffset
= reg
;
59 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
61 struct anv_device
*device
= cmd_buffer
->device
;
62 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
63 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
65 /* If we are emitting a new state base address we probably need to re-emit
68 cmd_buffer
->state
.descriptors_dirty
|= ~0;
70 /* Emit a render target cache flush.
72 * This isn't documented anywhere in the PRM. However, it seems to be
73 * necessary prior to changing the surface state base adress. Without
74 * this, we get GPU hangs when using multi-level command buffers which
75 * clear depth, reset state base address, and then go render stuff.
77 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
78 pc
.DCFlushEnable
= true;
79 pc
.RenderTargetCacheFlushEnable
= true;
80 pc
.CommandStreamerStallEnable
= true;
82 pc
.TileCacheFlushEnable
= true;
85 /* GEN:BUG:1606662791:
87 * Software must program PIPE_CONTROL command with "HDC Pipeline
88 * Flush" prior to programming of the below two non-pipeline state :
89 * * STATE_BASE_ADDRESS
90 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
92 if (devinfo
->revision
== 0 /* A0 */)
93 pc
.HDCPipelineFlushEnable
= true;
98 /* GEN:BUG:1607854226:
100 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
101 * mode by putting the pipeline temporarily in 3D mode.
103 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
104 genX(flush_pipeline_select_3d
)(cmd_buffer
);
107 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
108 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
109 sba
.GeneralStateMOCS
= mocs
;
110 sba
.GeneralStateBaseAddressModifyEnable
= true;
112 sba
.StatelessDataPortAccessMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddress
=
115 anv_cmd_buffer_surface_base_address(cmd_buffer
);
116 sba
.SurfaceStateMOCS
= mocs
;
117 sba
.SurfaceStateBaseAddressModifyEnable
= true;
119 sba
.DynamicStateBaseAddress
=
120 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
121 sba
.DynamicStateMOCS
= mocs
;
122 sba
.DynamicStateBaseAddressModifyEnable
= true;
124 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
125 sba
.IndirectObjectMOCS
= mocs
;
126 sba
.IndirectObjectBaseAddressModifyEnable
= true;
128 sba
.InstructionBaseAddress
=
129 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
130 sba
.InstructionMOCS
= mocs
;
131 sba
.InstructionBaseAddressModifyEnable
= true;
134 /* Broadwell requires that we specify a buffer size for a bunch of
135 * these fields. However, since we will be growing the BO's live, we
136 * just set them all to the maximum.
138 sba
.GeneralStateBufferSize
= 0xfffff;
139 sba
.IndirectObjectBufferSize
= 0xfffff;
140 if (device
->physical
->use_softpin
) {
141 /* With softpin, we use fixed addresses so we actually know how big
142 * our base addresses are.
144 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
145 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
147 sba
.DynamicStateBufferSize
= 0xfffff;
148 sba
.InstructionBufferSize
= 0xfffff;
150 sba
.GeneralStateBufferSizeModifyEnable
= true;
151 sba
.IndirectObjectBufferSizeModifyEnable
= true;
152 sba
.DynamicStateBufferSizeModifyEnable
= true;
153 sba
.InstructionBuffersizeModifyEnable
= true;
155 /* On gen7, we have upper bounds instead. According to the docs,
156 * setting an upper bound of zero means that no bounds checking is
157 * performed so, in theory, we should be able to leave them zero.
158 * However, border color is broken and the GPU bounds-checks anyway.
159 * To avoid this and other potential problems, we may as well set it
162 sba
.GeneralStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
165 sba
.DynamicStateAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
168 sba
.InstructionAccessUpperBound
=
169 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
170 sba
.InstructionAccessUpperBoundModifyEnable
= true;
173 if (cmd_buffer
->device
->physical
->use_softpin
) {
174 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
175 .bo
= device
->surface_state_pool
.block_pool
.bo
,
178 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
180 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
181 sba
.BindlessSurfaceStateSize
= 0;
183 sba
.BindlessSurfaceStateMOCS
= mocs
;
184 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
188 sba
.BindlessSamplerStateMOCS
= mocs
;
189 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
190 sba
.BindlessSamplerStateBufferSize
= 0;
195 /* GEN:BUG:1607854226:
197 * Put the pipeline back into its current mode.
199 if (gen12_wa_pipeline
!= UINT32_MAX
)
200 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
203 /* After re-setting the surface state base address, we have to do some
204 * cache flusing so that the sampler engine will pick up the new
205 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
206 * Shared Function > 3D Sampler > State > State Caching (page 96):
208 * Coherency with system memory in the state cache, like the texture
209 * cache is handled partially by software. It is expected that the
210 * command stream or shader will issue Cache Flush operation or
211 * Cache_Flush sampler message to ensure that the L1 cache remains
212 * coherent with system memory.
216 * Whenever the value of the Dynamic_State_Base_Addr,
217 * Surface_State_Base_Addr are altered, the L1 state cache must be
218 * invalidated to ensure the new surface or sampler state is fetched
219 * from system memory.
221 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
222 * which, according the PIPE_CONTROL instruction documentation in the
225 * Setting this bit is independent of any other bit in this packet.
226 * This bit controls the invalidation of the L1 and L2 state caches
227 * at the top of the pipe i.e. at the parsing time.
229 * Unfortunately, experimentation seems to indicate that state cache
230 * invalidation through a PIPE_CONTROL does nothing whatsoever in
231 * regards to surface state and binding tables. In stead, it seems that
232 * invalidating the texture cache is what is actually needed.
234 * XXX: As far as we have been able to determine through
235 * experimentation, shows that flush the texture cache appears to be
236 * sufficient. The theory here is that all of the sampling/rendering
237 * units cache the binding table in the texture cache. However, we have
238 * yet to be able to actually confirm this.
240 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
241 pc
.TextureCacheInvalidationEnable
= true;
242 pc
.ConstantCacheInvalidationEnable
= true;
243 pc
.StateCacheInvalidationEnable
= true;
248 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
249 struct anv_state state
, struct anv_address addr
)
251 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
254 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
255 state
.offset
+ isl_dev
->ss
.addr_offset
,
256 addr
.bo
, addr
.offset
, NULL
);
257 if (result
!= VK_SUCCESS
)
258 anv_batch_set_error(&cmd_buffer
->batch
, result
);
262 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
263 struct anv_surface_state state
)
265 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
267 assert(!anv_address_is_null(state
.address
));
268 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
270 if (!anv_address_is_null(state
.aux_address
)) {
272 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
273 &cmd_buffer
->pool
->alloc
,
274 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
275 state
.aux_address
.bo
,
276 state
.aux_address
.offset
,
278 if (result
!= VK_SUCCESS
)
279 anv_batch_set_error(&cmd_buffer
->batch
, result
);
282 if (!anv_address_is_null(state
.clear_address
)) {
284 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
285 &cmd_buffer
->pool
->alloc
,
287 isl_dev
->ss
.clear_color_state_offset
,
288 state
.clear_address
.bo
,
289 state
.clear_address
.offset
,
291 if (result
!= VK_SUCCESS
)
292 anv_batch_set_error(&cmd_buffer
->batch
, result
);
297 isl_color_value_requires_conversion(union isl_color_value color
,
298 const struct isl_surf
*surf
,
299 const struct isl_view
*view
)
301 if (surf
->format
== view
->format
&& isl_swizzle_is_identity(view
->swizzle
))
304 uint32_t surf_pack
[4] = { 0, 0, 0, 0 };
305 isl_color_value_pack(&color
, surf
->format
, surf_pack
);
307 uint32_t view_pack
[4] = { 0, 0, 0, 0 };
308 union isl_color_value swiz_color
=
309 isl_color_value_swizzle_inv(color
, view
->swizzle
);
310 isl_color_value_pack(&swiz_color
, view
->format
, view_pack
);
312 return memcmp(surf_pack
, view_pack
, sizeof(surf_pack
)) != 0;
316 anv_can_fast_clear_color_view(struct anv_device
* device
,
317 struct anv_image_view
*iview
,
318 VkImageLayout layout
,
319 union isl_color_value clear_color
,
321 VkRect2D render_area
)
323 if (iview
->planes
[0].isl
.base_array_layer
>=
324 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
325 iview
->planes
[0].isl
.base_level
))
328 /* Start by getting the fast clear type. We use the first subpass
329 * layout here because we don't want to fast-clear if the first subpass
330 * to use the attachment can't handle fast-clears.
332 enum anv_fast_clear_type fast_clear_type
=
333 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
334 VK_IMAGE_ASPECT_COLOR_BIT
,
336 switch (fast_clear_type
) {
337 case ANV_FAST_CLEAR_NONE
:
339 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
340 if (!isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
))
343 case ANV_FAST_CLEAR_ANY
:
347 /* Potentially, we could do partial fast-clears but doing so has crazy
348 * alignment restrictions. It's easier to just restrict to full size
349 * fast clears for now.
351 if (render_area
.offset
.x
!= 0 ||
352 render_area
.offset
.y
!= 0 ||
353 render_area
.extent
.width
!= iview
->extent
.width
||
354 render_area
.extent
.height
!= iview
->extent
.height
)
357 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
359 !isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
))
362 /* If the clear color is one that would require non-trivial format
363 * conversion on resolve, we don't bother with the fast clear. This
364 * shouldn't be common as most clear colors are 0/1 and the most common
365 * format re-interpretation is for sRGB.
367 if (isl_color_value_requires_conversion(clear_color
,
368 &iview
->image
->planes
[0].surface
.isl
,
369 &iview
->planes
[0].isl
)) {
370 anv_perf_warn(device
, iview
,
371 "Cannot fast-clear to colors which would require "
372 "format conversion on resolve");
376 /* We only allow fast clears to the first slice of an image (level 0,
377 * layer 0) and only for the entire slice. This guarantees us that, at
378 * any given time, there is only one clear color on any given image at
379 * any given time. At the time of our testing (Jan 17, 2018), there
380 * were no known applications which would benefit from fast-clearing
381 * more than just the first slice.
383 if (iview
->planes
[0].isl
.base_level
> 0 ||
384 iview
->planes
[0].isl
.base_array_layer
> 0) {
385 anv_perf_warn(device
, iview
->image
,
386 "Rendering with multi-lod or multi-layer framebuffer "
387 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
388 "baseArrayLayer > 0. Not fast clearing.");
392 if (num_layers
> 1) {
393 anv_perf_warn(device
, iview
->image
,
394 "Rendering to a multi-layer framebuffer with "
395 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
402 anv_can_hiz_clear_ds_view(struct anv_device
*device
,
403 struct anv_image_view
*iview
,
404 VkImageLayout layout
,
405 VkImageAspectFlags clear_aspects
,
406 float depth_clear_value
,
407 VkRect2D render_area
)
409 /* We don't do any HiZ or depth fast-clears on gen7 yet */
413 /* If we're just clearing stencil, we can always HiZ clear */
414 if (!(clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
417 /* We must have depth in order to have HiZ */
418 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
421 const enum isl_aux_usage clear_aux_usage
=
422 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
423 VK_IMAGE_ASPECT_DEPTH_BIT
,
424 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
426 if (!blorp_can_hiz_clear_depth(&device
->info
,
427 &iview
->image
->planes
[0].surface
.isl
,
429 iview
->planes
[0].isl
.base_level
,
430 iview
->planes
[0].isl
.base_array_layer
,
431 render_area
.offset
.x
,
432 render_area
.offset
.y
,
433 render_area
.offset
.x
+
434 render_area
.extent
.width
,
435 render_area
.offset
.y
+
436 render_area
.extent
.height
))
439 if (depth_clear_value
!= ANV_HZ_FC_VAL
)
442 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a fast-cleared
443 * portion of a HiZ buffer. Testing has revealed that Gen8 only supports
444 * returning 0.0f. Gens prior to gen8 do not support this feature at all.
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
))
449 /* If we got here, then we can fast clear */
453 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
457 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
458 const struct anv_image
*image
,
459 VkImageAspectFlagBits aspect
,
460 uint32_t base_level
, uint32_t level_count
,
461 uint32_t base_layer
, uint32_t layer_count
)
463 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
465 uint64_t base_address
=
466 anv_address_physical(image
->planes
[plane
].address
);
468 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
469 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
471 /* We're about to live-update the AUX-TT. We really don't want anyone else
472 * trying to read it while we're doing this. We could probably get away
473 * with not having this stall in some cases if we were really careful but
474 * it's better to play it safe. Full stall the GPU.
476 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
477 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
479 struct gen_mi_builder b
;
480 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
482 for (uint32_t a
= 0; a
< layer_count
; a
++) {
483 const uint32_t layer
= base_layer
+ a
;
485 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
486 for (uint32_t l
= 0; l
< level_count
; l
++) {
487 const uint32_t level
= base_level
+ l
;
489 uint32_t logical_array_layer
, logical_z_offset_px
;
490 if (image
->type
== VK_IMAGE_TYPE_3D
) {
491 logical_array_layer
= 0;
493 /* If the given miplevel does not have this layer, then any higher
494 * miplevels won't either because miplevels only get smaller the
497 assert(layer
< image
->extent
.depth
);
498 if (layer
>= anv_minify(image
->extent
.depth
, level
))
500 logical_z_offset_px
= layer
;
502 assert(layer
< image
->array_size
);
503 logical_array_layer
= layer
;
504 logical_z_offset_px
= 0;
507 uint32_t slice_start_offset_B
, slice_end_offset_B
;
508 isl_surf_get_image_range_B_tile(isl_surf
, level
,
511 &slice_start_offset_B
,
512 &slice_end_offset_B
);
514 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
515 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
518 /* Aux operates 64K at a time */
519 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
520 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
522 for (uint64_t offset
= start_offset_B
;
523 offset
< end_offset_B
; offset
+= 64 * 1024) {
524 uint64_t address
= base_address
+ offset
;
526 uint64_t aux_entry_addr64
, *aux_entry_map
;
527 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
528 address
, &aux_entry_addr64
);
530 assert(cmd_buffer
->device
->physical
->use_softpin
);
531 struct anv_address aux_entry_address
= {
533 .offset
= aux_entry_addr64
,
536 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
537 uint64_t new_aux_entry
=
538 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
540 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
541 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
543 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
544 gen_mi_imm(new_aux_entry
));
548 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
550 #endif /* GEN_GEN == 12 */
552 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
553 * the initial layout is undefined, the HiZ buffer and depth buffer will
554 * represent the same data at the end of this operation.
557 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
558 const struct anv_image
*image
,
559 uint32_t base_layer
, uint32_t layer_count
,
560 VkImageLayout initial_layout
,
561 VkImageLayout final_layout
)
563 uint32_t depth_plane
=
564 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
565 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
569 if ((initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
570 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) &&
571 cmd_buffer
->device
->physical
->has_implicit_ccs
&&
572 cmd_buffer
->device
->info
.has_aux_map
) {
573 anv_image_init_aux_tt(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
578 const enum isl_aux_state initial_state
=
579 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
580 VK_IMAGE_ASPECT_DEPTH_BIT
,
582 const enum isl_aux_state final_state
=
583 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
584 VK_IMAGE_ASPECT_DEPTH_BIT
,
587 const bool initial_depth_valid
=
588 isl_aux_state_has_valid_primary(initial_state
);
589 const bool initial_hiz_valid
=
590 isl_aux_state_has_valid_aux(initial_state
);
591 const bool final_needs_depth
=
592 isl_aux_state_has_valid_primary(final_state
);
593 const bool final_needs_hiz
=
594 isl_aux_state_has_valid_aux(final_state
);
596 /* Getting into the pass-through state for Depth is tricky and involves
597 * both a resolve and an ambiguate. We don't handle that state right now
598 * as anv_layout_to_aux_state never returns it.
600 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
602 if (final_needs_depth
&& !initial_depth_valid
) {
603 assert(initial_hiz_valid
);
604 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
605 0, base_layer
, layer_count
, ISL_AUX_OP_FULL_RESOLVE
);
606 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
607 assert(initial_depth_valid
);
608 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
609 0, base_layer
, layer_count
, ISL_AUX_OP_AMBIGUATE
);
614 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
616 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
617 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
618 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
621 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
622 * the initial layout is undefined, the HiZ buffer and depth buffer will
623 * represent the same data at the end of this operation.
626 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
627 const struct anv_image
*image
,
628 uint32_t base_level
, uint32_t level_count
,
629 uint32_t base_layer
, uint32_t layer_count
,
630 VkImageLayout initial_layout
,
631 VkImageLayout final_layout
)
634 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
635 VK_IMAGE_ASPECT_STENCIL_BIT
);
637 /* On gen7, we have to store a texturable version of the stencil buffer in
638 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
639 * forth at strategic points. Stencil writes are only allowed in following
642 * - VK_IMAGE_LAYOUT_GENERAL
643 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
644 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
645 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
646 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
648 * For general, we have no nice opportunity to transition so we do the copy
649 * to the shadow unconditionally at the end of the subpass. For transfer
650 * destinations, we can update it as part of the transfer op. For the other
651 * layouts, we delay the copy until a transition into some other layout.
653 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
654 vk_image_layout_stencil_write_optimal(initial_layout
) &&
655 !vk_image_layout_stencil_write_optimal(final_layout
)) {
656 anv_image_copy_to_shadow(cmd_buffer
, image
,
657 VK_IMAGE_ASPECT_STENCIL_BIT
,
658 base_level
, level_count
,
659 base_layer
, layer_count
);
661 #endif /* GEN_GEN == 7 */
664 #define MI_PREDICATE_SRC0 0x2400
665 #define MI_PREDICATE_SRC1 0x2408
666 #define MI_PREDICATE_RESULT 0x2418
669 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
670 const struct anv_image
*image
,
671 VkImageAspectFlagBits aspect
,
673 uint32_t base_layer
, uint32_t layer_count
,
676 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
678 /* We only have compression tracking for CCS_E */
679 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
682 for (uint32_t a
= 0; a
< layer_count
; a
++) {
683 uint32_t layer
= base_layer
+ a
;
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
685 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
688 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
694 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 enum anv_fast_clear_type fast_clear
)
699 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
700 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
702 sdi
.ImmediateData
= fast_clear
;
705 /* Whenever we have fast-clear, we consider that slice to be compressed.
706 * This makes building predicates much easier.
708 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
709 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
712 /* This is only really practical on haswell and above because it requires
713 * MI math in order to get it correct.
715 #if GEN_GEN >= 8 || GEN_IS_HASWELL
717 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
718 const struct anv_image
*image
,
719 VkImageAspectFlagBits aspect
,
720 uint32_t level
, uint32_t array_layer
,
721 enum isl_aux_op resolve_op
,
722 enum anv_fast_clear_type fast_clear_supported
)
724 struct gen_mi_builder b
;
725 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
727 const struct gen_mi_value fast_clear_type
=
728 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
731 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
732 /* In this case, we're doing a full resolve which means we want the
733 * resolve to happen if any compression (including fast-clears) is
736 * In order to simplify the logic a bit, we make the assumption that,
737 * if the first slice has been fast-cleared, it is also marked as
738 * compressed. See also set_image_fast_clear_state.
740 const struct gen_mi_value compression_state
=
741 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
743 level
, array_layer
));
744 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
746 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
748 if (level
== 0 && array_layer
== 0) {
749 /* If the predicate is true, we want to write 0 to the fast clear type
750 * and, if it's false, leave it alone. We can do this by writing
752 * clear_type = clear_type & ~predicate;
754 struct gen_mi_value new_fast_clear_type
=
755 gen_mi_iand(&b
, fast_clear_type
,
756 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
757 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
759 } else if (level
== 0 && array_layer
== 0) {
760 /* In this case, we are doing a partial resolve to get rid of fast-clear
761 * colors. We don't care about the compression state but we do care
762 * about how much fast clear is allowed by the final layout.
764 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
765 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
767 /* We need to compute (fast_clear_supported < image->fast_clear) */
768 struct gen_mi_value pred
=
769 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
770 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
771 gen_mi_value_ref(&b
, pred
));
773 /* If the predicate is true, we want to write 0 to the fast clear type
774 * and, if it's false, leave it alone. We can do this by writing
776 * clear_type = clear_type & ~predicate;
778 struct gen_mi_value new_fast_clear_type
=
779 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
780 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
782 /* In this case, we're trying to do a partial resolve on a slice that
783 * doesn't have clear color. There's nothing to do.
785 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
789 /* Set src1 to 0 and use a != condition */
790 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
792 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
793 mip
.LoadOperation
= LOAD_LOADINV
;
794 mip
.CombineOperation
= COMBINE_SET
;
795 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
798 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
802 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
803 const struct anv_image
*image
,
804 VkImageAspectFlagBits aspect
,
805 uint32_t level
, uint32_t array_layer
,
806 enum isl_aux_op resolve_op
,
807 enum anv_fast_clear_type fast_clear_supported
)
809 struct gen_mi_builder b
;
810 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
812 struct gen_mi_value fast_clear_type_mem
=
813 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
816 /* This only works for partial resolves and only when the clear color is
817 * all or nothing. On the upside, this emits less command streamer code
818 * and works on Ivybridge and Bay Trail.
820 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
821 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
823 /* We don't support fast clears on anything other than the first slice. */
824 if (level
> 0 || array_layer
> 0)
827 /* On gen8, we don't have a concept of default clear colors because we
828 * can't sample from CCS surfaces. It's enough to just load the fast clear
829 * state into the predicate register.
831 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
832 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
833 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
835 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
836 mip
.LoadOperation
= LOAD_LOADINV
;
837 mip
.CombineOperation
= COMBINE_SET
;
838 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
841 #endif /* GEN_GEN <= 8 */
844 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
845 const struct anv_image
*image
,
846 enum isl_format format
,
847 struct isl_swizzle swizzle
,
848 VkImageAspectFlagBits aspect
,
849 uint32_t level
, uint32_t array_layer
,
850 enum isl_aux_op resolve_op
,
851 enum anv_fast_clear_type fast_clear_supported
)
853 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
856 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
857 aspect
, level
, array_layer
,
858 resolve_op
, fast_clear_supported
);
859 #else /* GEN_GEN <= 8 */
860 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
861 aspect
, level
, array_layer
,
862 resolve_op
, fast_clear_supported
);
865 /* CCS_D only supports full resolves and BLORP will assert on us if we try
866 * to do a partial resolve on a CCS_D surface.
868 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
869 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
870 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
872 anv_image_ccs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
873 level
, array_layer
, 1, resolve_op
, NULL
, true);
877 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
878 const struct anv_image
*image
,
879 enum isl_format format
,
880 struct isl_swizzle swizzle
,
881 VkImageAspectFlagBits aspect
,
882 uint32_t array_layer
,
883 enum isl_aux_op resolve_op
,
884 enum anv_fast_clear_type fast_clear_supported
)
886 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
887 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
889 #if GEN_GEN >= 8 || GEN_IS_HASWELL
890 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
891 aspect
, 0, array_layer
,
892 resolve_op
, fast_clear_supported
);
894 anv_image_mcs_op(cmd_buffer
, image
, format
, swizzle
, aspect
,
895 array_layer
, 1, resolve_op
, NULL
, true);
897 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
902 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
903 const struct anv_image
*image
,
904 VkImageAspectFlagBits aspect
,
905 enum isl_aux_usage aux_usage
,
908 uint32_t layer_count
)
910 /* The aspect must be exactly one of the image aspects. */
911 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
913 /* The only compression types with more than just fast-clears are MCS,
914 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
915 * track the current fast-clear and compression state. This leaves us
916 * with just MCS and CCS_E.
918 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
919 aux_usage
!= ISL_AUX_USAGE_MCS
)
922 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
923 level
, base_layer
, layer_count
, true);
927 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
928 const struct anv_image
*image
,
929 VkImageAspectFlagBits aspect
)
931 assert(cmd_buffer
&& image
);
932 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
934 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
935 ANV_FAST_CLEAR_NONE
);
937 /* Initialize the struct fields that are accessed for fast-clears so that
938 * the HW restrictions on the field values are satisfied.
940 struct anv_address addr
=
941 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
944 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
945 const unsigned num_dwords
= GEN_GEN
>= 10 ?
946 isl_dev
->ss
.clear_color_state_size
/ 4 :
947 isl_dev
->ss
.clear_value_size
/ 4;
948 for (unsigned i
= 0; i
< num_dwords
; i
++) {
949 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
951 sdi
.Address
.offset
+= i
* 4;
952 sdi
.ImmediateData
= 0;
956 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
958 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
959 /* Pre-SKL, the dword containing the clear values also contains
960 * other fields, so we need to initialize those fields to match the
961 * values that would be in a color attachment.
963 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
964 ISL_CHANNEL_SELECT_GREEN
<< 22 |
965 ISL_CHANNEL_SELECT_BLUE
<< 19 |
966 ISL_CHANNEL_SELECT_ALPHA
<< 16;
967 } else if (GEN_GEN
== 7) {
968 /* On IVB, the dword containing the clear values also contains
969 * other fields that must be zero or can be zero.
971 sdi
.ImmediateData
= 0;
977 /* Copy the fast-clear value dword(s) between a surface state object and an
978 * image's fast clear state buffer.
981 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
982 struct anv_state surface_state
,
983 const struct anv_image
*image
,
984 VkImageAspectFlagBits aspect
,
985 bool copy_from_surface_state
)
987 assert(cmd_buffer
&& image
);
988 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
990 struct anv_address ss_clear_addr
= {
991 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
992 .offset
= surface_state
.offset
+
993 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
995 const struct anv_address entry_addr
=
996 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
997 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
1000 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
1001 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
1002 * in-flight when they are issued even if the memory touched is not
1003 * currently active for rendering. The weird bit is that it is not the
1004 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
1005 * rendering hangs such that the next stalling command after the
1006 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
1008 * It is unclear exactly why this hang occurs. Both MI commands come with
1009 * warnings about the 3D pipeline but that doesn't seem to fully explain
1010 * it. My (Jason's) best theory is that it has something to do with the
1011 * fact that we're using a GPU state register as our temporary and that
1012 * something with reading/writing it is causing problems.
1014 * In order to work around this issue, we emit a PIPE_CONTROL with the
1015 * command streamer stall bit set.
1017 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1018 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1021 struct gen_mi_builder b
;
1022 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1024 if (copy_from_surface_state
) {
1025 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
1027 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
1029 /* Updating a surface state object may require that the state cache be
1030 * invalidated. From the SKL PRM, Shared Functions -> State -> State
1033 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
1034 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
1035 * modified [...], the L1 state cache must be invalidated to ensure
1036 * the new surface or sampler state is fetched from system memory.
1038 * In testing, SKL doesn't actually seem to need this, but HSW does.
1040 cmd_buffer
->state
.pending_pipe_bits
|=
1041 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1046 * @brief Transitions a color buffer from one layout to another.
1048 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1051 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1052 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1053 * this represents the maximum layers to transition at each
1054 * specified miplevel.
1057 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1058 const struct anv_image
*image
,
1059 VkImageAspectFlagBits aspect
,
1060 const uint32_t base_level
, uint32_t level_count
,
1061 uint32_t base_layer
, uint32_t layer_count
,
1062 VkImageLayout initial_layout
,
1063 VkImageLayout final_layout
)
1065 struct anv_device
*device
= cmd_buffer
->device
;
1066 const struct gen_device_info
*devinfo
= &device
->info
;
1067 /* Validate the inputs. */
1069 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1070 /* These values aren't supported for simplicity's sake. */
1071 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1072 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1073 /* Ensure the subresource range is valid. */
1074 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1075 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1076 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1077 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1078 assert(last_level_num
<= image
->levels
);
1079 /* The spec disallows these final layouts. */
1080 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1081 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1083 /* No work is necessary if the layout stays the same or if this subresource
1084 * range lacks auxiliary data.
1086 if (initial_layout
== final_layout
)
1089 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1091 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1092 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1093 /* This surface is a linear compressed image with a tiled shadow surface
1094 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1095 * we need to ensure the shadow copy is up-to-date.
1097 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1098 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1099 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1100 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1102 anv_image_copy_to_shadow(cmd_buffer
, image
,
1103 VK_IMAGE_ASPECT_COLOR_BIT
,
1104 base_level
, level_count
,
1105 base_layer
, layer_count
);
1108 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1111 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1113 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1114 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1116 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1117 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1118 base_level
, level_count
,
1119 base_layer
, layer_count
);
1122 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1125 /* A subresource in the undefined layout may have been aliased and
1126 * populated with any arrangement of bits. Therefore, we must initialize
1127 * the related aux buffer and clear buffer entry with desirable values.
1128 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1129 * images with VK_IMAGE_TILING_OPTIMAL.
1131 * Initialize the relevant clear buffer entries.
1133 if (base_level
== 0 && base_layer
== 0)
1134 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1136 /* Initialize the aux buffers to enable correct rendering. In order to
1137 * ensure that things such as storage images work correctly, aux buffers
1138 * need to be initialized to valid data.
1140 * Having an aux buffer with invalid data is a problem for two reasons:
1142 * 1) Having an invalid value in the buffer can confuse the hardware.
1143 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1144 * invalid and leads to the hardware doing strange things. It
1145 * doesn't hang as far as we can tell but rendering corruption can
1148 * 2) If this transition is into the GENERAL layout and we then use the
1149 * image as a storage image, then we must have the aux buffer in the
1150 * pass-through state so that, if we then go to texture from the
1151 * image, we get the results of our storage image writes and not the
1152 * fast clear color or other random data.
1154 * For CCS both of the problems above are real demonstrable issues. In
1155 * that case, the only thing we can do is to perform an ambiguate to
1156 * transition the aux surface into the pass-through state.
1158 * For MCS, (2) is never an issue because we don't support multisampled
1159 * storage images. In theory, issue (1) is a problem with MCS but we've
1160 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1161 * theory, be interpreted as something but we don't know that all bit
1162 * patterns are actually valid. For 2x and 8x, you could easily end up
1163 * with the MCS referring to an invalid plane because not all bits of
1164 * the MCS value are actually used. Even though we've never seen issues
1165 * in the wild, it's best to play it safe and initialize the MCS. We
1166 * can use a fast-clear for MCS because we only ever touch from render
1167 * and texture (no image load store).
1169 if (image
->samples
== 1) {
1170 for (uint32_t l
= 0; l
< level_count
; l
++) {
1171 const uint32_t level
= base_level
+ l
;
1173 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1174 if (base_layer
>= aux_layers
)
1175 break; /* We will only get fewer layers as level increases */
1176 uint32_t level_layer_count
=
1177 MIN2(layer_count
, aux_layers
- base_layer
);
1179 anv_image_ccs_op(cmd_buffer
, image
,
1180 image
->planes
[plane
].surface
.isl
.format
,
1181 ISL_SWIZZLE_IDENTITY
,
1182 aspect
, level
, base_layer
, level_layer_count
,
1183 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1185 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1186 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1187 level
, base_layer
, level_layer_count
,
1192 if (image
->samples
== 4 || image
->samples
== 16) {
1193 anv_perf_warn(cmd_buffer
->device
, image
,
1194 "Doing a potentially unnecessary fast-clear to "
1195 "define an MCS buffer.");
1198 assert(base_level
== 0 && level_count
== 1);
1199 anv_image_mcs_op(cmd_buffer
, image
,
1200 image
->planes
[plane
].surface
.isl
.format
,
1201 ISL_SWIZZLE_IDENTITY
,
1202 aspect
, base_layer
, layer_count
,
1203 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1208 const enum isl_aux_usage initial_aux_usage
=
1209 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1210 const enum isl_aux_usage final_aux_usage
=
1211 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1213 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1214 * We can handle transitions between CCS_D/E to and from NONE. What we
1215 * don't yet handle is switching between CCS_E and CCS_D within a given
1216 * image. Doing so in a performant way requires more detailed aux state
1217 * tracking such as what is done in i965. For now, just assume that we
1218 * only have one type of compression.
1220 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1221 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1222 initial_aux_usage
== final_aux_usage
);
1224 /* If initial aux usage is NONE, there is nothing to resolve */
1225 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1228 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1230 /* If the initial layout supports more fast clear than the final layout
1231 * then we need at least a partial resolve.
1233 const enum anv_fast_clear_type initial_fast_clear
=
1234 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1235 const enum anv_fast_clear_type final_fast_clear
=
1236 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1237 if (final_fast_clear
< initial_fast_clear
)
1238 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1240 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1241 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1242 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1244 if (resolve_op
== ISL_AUX_OP_NONE
)
1247 /* Perform a resolve to synchronize data between the main and aux buffer.
1248 * Before we begin, we must satisfy the cache flushing requirement specified
1249 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1251 * Any transition from any value in {Clear, Render, Resolve} to a
1252 * different value in {Clear, Render, Resolve} requires end of pipe
1255 * We perform a flush of the write cache before and after the clear and
1256 * resolve operations to meet this requirement.
1258 * Unlike other drawing, fast clear operations are not properly
1259 * synchronized. The first PIPE_CONTROL here likely ensures that the
1260 * contents of the previous render or clear hit the render target before we
1261 * resolve and the second likely ensures that the resolve is complete before
1262 * we do any more rendering or clearing.
1264 cmd_buffer
->state
.pending_pipe_bits
|=
1265 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1267 for (uint32_t l
= 0; l
< level_count
; l
++) {
1268 uint32_t level
= base_level
+ l
;
1270 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1271 if (base_layer
>= aux_layers
)
1272 break; /* We will only get fewer layers as level increases */
1273 uint32_t level_layer_count
=
1274 MIN2(layer_count
, aux_layers
- base_layer
);
1276 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1277 uint32_t array_layer
= base_layer
+ a
;
1278 if (image
->samples
== 1) {
1279 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1280 image
->planes
[plane
].surface
.isl
.format
,
1281 ISL_SWIZZLE_IDENTITY
,
1282 aspect
, level
, array_layer
, resolve_op
,
1285 /* We only support fast-clear on the first layer so partial
1286 * resolves should not be used on other layers as they will use
1287 * the clear color stored in memory that is only valid for layer0.
1289 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1293 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1294 image
->planes
[plane
].surface
.isl
.format
,
1295 ISL_SWIZZLE_IDENTITY
,
1296 aspect
, array_layer
, resolve_op
,
1302 cmd_buffer
->state
.pending_pipe_bits
|=
1303 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1307 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1308 const struct anv_render_pass
*pass
,
1309 const struct anv_framebuffer
*framebuffer
,
1310 const VkRenderPassBeginInfo
*begin
)
1312 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1314 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1316 if (pass
->attachment_count
> 0) {
1317 state
->attachments
= vk_zalloc(&cmd_buffer
->pool
->alloc
,
1318 pass
->attachment_count
*
1319 sizeof(state
->attachments
[0]),
1320 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1321 if (state
->attachments
== NULL
) {
1322 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1323 return anv_batch_set_error(&cmd_buffer
->batch
,
1324 VK_ERROR_OUT_OF_HOST_MEMORY
);
1327 state
->attachments
= NULL
;
1330 const VkRenderPassAttachmentBeginInfoKHR
*attach_begin
=
1331 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1332 if (begin
&& !attach_begin
)
1333 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1335 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1336 if (attach_begin
&& attach_begin
->attachmentCount
!= 0) {
1337 assert(attach_begin
->attachmentCount
== pass
->attachment_count
);
1338 ANV_FROM_HANDLE(anv_image_view
, iview
, attach_begin
->pAttachments
[i
]);
1339 state
->attachments
[i
].image_view
= iview
;
1340 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1341 state
->attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1343 state
->attachments
[i
].image_view
= NULL
;
1348 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1349 const struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[i
];
1350 struct anv_attachment_state
*att_state
= &state
->attachments
[i
];
1351 VkImageAspectFlags att_aspects
= vk_format_aspects(pass_att
->format
);
1352 VkImageAspectFlags clear_aspects
= 0;
1353 VkImageAspectFlags load_aspects
= 0;
1355 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1356 /* color attachment */
1357 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1358 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1359 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1360 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1363 /* depthstencil attachment */
1364 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1365 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1366 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1367 } else if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1368 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1371 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1372 if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1373 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1374 } else if (pass_att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1375 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1380 att_state
->current_layout
= pass_att
->initial_layout
;
1381 att_state
->current_stencil_layout
= pass_att
->stencil_initial_layout
;
1382 att_state
->pending_clear_aspects
= clear_aspects
;
1383 att_state
->pending_load_aspects
= load_aspects
;
1385 att_state
->clear_value
= begin
->pClearValues
[i
];
1387 struct anv_image_view
*iview
= state
->attachments
[i
].image_view
;
1388 anv_assert(iview
->vk_format
== pass_att
->format
);
1390 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1391 att_state
->pending_clear_views
= (1 << num_layers
) - 1;
1393 /* This will be initialized after the first subpass transition. */
1394 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
1396 att_state
->fast_clear
= false;
1397 if (clear_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1398 assert(clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1399 att_state
->fast_clear
=
1400 anv_can_fast_clear_color_view(cmd_buffer
->device
, iview
,
1401 pass_att
->first_subpass_layout
,
1402 vk_to_isl_color(att_state
->clear_value
.color
),
1403 framebuffer
->layers
,
1405 } else if (clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
1406 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
1407 att_state
->fast_clear
=
1408 anv_can_hiz_clear_ds_view(cmd_buffer
->device
, iview
,
1409 pass_att
->first_subpass_layout
,
1411 att_state
->clear_value
.depthStencil
.depth
,
1421 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1424 genX(cmd_buffer_alloc_att_surf_states
)(struct anv_cmd_buffer
*cmd_buffer
,
1425 const struct anv_render_pass
*pass
,
1426 const struct anv_subpass
*subpass
)
1428 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1429 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1431 /* Reserve one for the NULL state. */
1432 unsigned num_states
= 1;
1433 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1434 uint32_t att
= subpass
->attachments
[i
].attachment
;
1435 if (att
== VK_ATTACHMENT_UNUSED
)
1438 assert(att
< pass
->attachment_count
);
1439 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1442 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1443 assert(util_bitcount(att_usage
) == 1);
1445 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
||
1446 att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1450 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1451 state
->attachment_states
=
1452 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1453 num_states
* ss_stride
, isl_dev
->ss
.align
);
1454 if (state
->attachment_states
.map
== NULL
) {
1455 return anv_batch_set_error(&cmd_buffer
->batch
,
1456 VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1459 struct anv_state next_state
= state
->attachment_states
;
1460 next_state
.alloc_size
= isl_dev
->ss
.size
;
1462 state
->null_surface_state
= next_state
;
1463 next_state
.offset
+= ss_stride
;
1464 next_state
.map
+= ss_stride
;
1466 for (uint32_t i
= 0; i
< subpass
->attachment_count
; i
++) {
1467 uint32_t att
= subpass
->attachments
[i
].attachment
;
1468 if (att
== VK_ATTACHMENT_UNUSED
)
1471 assert(att
< pass
->attachment_count
);
1472 if (!vk_format_is_color(pass
->attachments
[att
].format
))
1475 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
1476 assert(util_bitcount(att_usage
) == 1);
1478 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
)
1479 state
->attachments
[att
].color
.state
= next_state
;
1480 else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)
1481 state
->attachments
[att
].input
.state
= next_state
;
1485 state
->attachments
[att
].color
.state
= next_state
;
1486 next_state
.offset
+= ss_stride
;
1487 next_state
.map
+= ss_stride
;
1490 assert(next_state
.offset
== state
->attachment_states
.offset
+
1491 state
->attachment_states
.alloc_size
);
1497 genX(BeginCommandBuffer
)(
1498 VkCommandBuffer commandBuffer
,
1499 const VkCommandBufferBeginInfo
* pBeginInfo
)
1501 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1503 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1504 * command buffer's state. Otherwise, we must *reset* its state. In both
1505 * cases we reset it.
1507 * From the Vulkan 1.0 spec:
1509 * If a command buffer is in the executable state and the command buffer
1510 * was allocated from a command pool with the
1511 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1512 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1513 * as if vkResetCommandBuffer had been called with
1514 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1515 * the command buffer in the recording state.
1517 anv_cmd_buffer_reset(cmd_buffer
);
1519 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1521 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1522 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1524 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1526 /* We sometimes store vertex data in the dynamic state buffer for blorp
1527 * operations and our dynamic state stream may re-use data from previous
1528 * command buffers. In order to prevent stale cache data, we flush the VF
1529 * cache. We could do this on every blorp call but that's not really
1530 * needed as all of the data will get written by the CPU prior to the GPU
1531 * executing anything. The chances are fairly high that they will use
1532 * blorp at least once per primary command buffer so it shouldn't be
1535 * There is also a workaround on gen8 which requires us to invalidate the
1536 * VF cache occasionally. It's easier if we can assume we start with a
1537 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1539 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1541 /* Re-emit the aux table register in every command buffer. This way we're
1542 * ensured that we have the table even if this command buffer doesn't
1543 * initialize any images.
1545 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1547 /* We send an "Indirect State Pointers Disable" packet at
1548 * EndCommandBuffer, so all push contant packets are ignored during a
1549 * context restore. Documentation says after that command, we need to
1550 * emit push constants again before any rendering operation. So we
1551 * flag them dirty here to make sure they get emitted.
1553 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1555 VkResult result
= VK_SUCCESS
;
1556 if (cmd_buffer
->usage_flags
&
1557 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1558 assert(pBeginInfo
->pInheritanceInfo
);
1559 ANV_FROM_HANDLE(anv_render_pass
, pass
,
1560 pBeginInfo
->pInheritanceInfo
->renderPass
);
1561 struct anv_subpass
*subpass
=
1562 &pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1563 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
,
1564 pBeginInfo
->pInheritanceInfo
->framebuffer
);
1566 cmd_buffer
->state
.pass
= pass
;
1567 cmd_buffer
->state
.subpass
= subpass
;
1569 /* This is optional in the inheritance info. */
1570 cmd_buffer
->state
.framebuffer
= framebuffer
;
1572 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
1574 if (result
!= VK_SUCCESS
)
1577 result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
, pass
,
1579 if (result
!= VK_SUCCESS
)
1582 /* Record that HiZ is enabled if we can. */
1583 if (cmd_buffer
->state
.framebuffer
) {
1584 const struct anv_image_view
* const iview
=
1585 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1588 VkImageLayout layout
=
1589 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1591 enum isl_aux_usage aux_usage
=
1592 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1593 VK_IMAGE_ASPECT_DEPTH_BIT
,
1594 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1597 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(aux_usage
);
1601 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1604 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1605 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1606 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1607 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1609 /* If secondary buffer supports conditional rendering
1610 * we should emit commands as if conditional rendering is enabled.
1612 cmd_buffer
->state
.conditional_render_enabled
=
1613 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1620 /* From the PRM, Volume 2a:
1622 * "Indirect State Pointers Disable
1624 * At the completion of the post-sync operation associated with this pipe
1625 * control packet, the indirect state pointers in the hardware are
1626 * considered invalid; the indirect pointers are not saved in the context.
1627 * If any new indirect state commands are executed in the command stream
1628 * while the pipe control is pending, the new indirect state commands are
1631 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1632 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1633 * commands are only considered as Indirect State Pointers. Once ISP is
1634 * issued in a context, SW must initialize by programming push constant
1635 * commands for all the shaders (at least to zero length) before attempting
1636 * any rendering operation for the same context."
1638 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1639 * even though they point to a BO that has been already unreferenced at
1640 * the end of the previous batch buffer. This has been fine so far since
1641 * we are protected by these scratch page (every address not covered by
1642 * a BO should be pointing to the scratch page). But on CNL, it is
1643 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1646 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1647 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1648 * context restore, so the mentioned hang doesn't happen. However,
1649 * software must program push constant commands for all stages prior to
1650 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1652 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1653 * constants have been loaded into the EUs prior to disable the push constants
1654 * so that it doesn't hang a previous 3DPRIMITIVE.
1657 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1659 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1660 pc
.StallAtPixelScoreboard
= true;
1661 pc
.CommandStreamerStallEnable
= true;
1663 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1664 pc
.IndirectStatePointersDisable
= true;
1665 pc
.CommandStreamerStallEnable
= true;
1670 genX(EndCommandBuffer
)(
1671 VkCommandBuffer commandBuffer
)
1673 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1675 if (anv_batch_has_error(&cmd_buffer
->batch
))
1676 return cmd_buffer
->batch
.status
;
1678 /* We want every command buffer to start with the PMA fix in a known state,
1679 * so we disable it at the end of the command buffer.
1681 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1683 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1685 emit_isp_disable(cmd_buffer
);
1687 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1693 genX(CmdExecuteCommands
)(
1694 VkCommandBuffer commandBuffer
,
1695 uint32_t commandBufferCount
,
1696 const VkCommandBuffer
* pCmdBuffers
)
1698 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1700 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1702 if (anv_batch_has_error(&primary
->batch
))
1705 /* The secondary command buffers will assume that the PMA fix is disabled
1706 * when they begin executing. Make sure this is true.
1708 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1710 /* The secondary command buffer doesn't know which textures etc. have been
1711 * flushed prior to their execution. Apply those flushes now.
1713 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1715 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1716 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1718 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1719 assert(!anv_batch_has_error(&secondary
->batch
));
1721 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1722 if (secondary
->state
.conditional_render_enabled
) {
1723 if (!primary
->state
.conditional_render_enabled
) {
1724 /* Secondary buffer is constructed as if it will be executed
1725 * with conditional rendering, we should satisfy this dependency
1726 * regardless of conditional rendering being enabled in primary.
1728 struct gen_mi_builder b
;
1729 gen_mi_builder_init(&b
, &primary
->batch
);
1730 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1731 gen_mi_imm(UINT64_MAX
));
1736 if (secondary
->usage_flags
&
1737 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1738 /* If we're continuing a render pass from the primary, we need to
1739 * copy the surface states for the current subpass into the storage
1740 * we allocated for them in BeginCommandBuffer.
1742 struct anv_bo
*ss_bo
=
1743 primary
->device
->surface_state_pool
.block_pool
.bo
;
1744 struct anv_state src_state
= primary
->state
.attachment_states
;
1745 struct anv_state dst_state
= secondary
->state
.attachment_states
;
1746 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1748 genX(cmd_buffer_so_memcpy
)(primary
,
1749 (struct anv_address
) {
1751 .offset
= dst_state
.offset
,
1753 (struct anv_address
) {
1755 .offset
= src_state
.offset
,
1757 src_state
.alloc_size
);
1760 anv_cmd_buffer_add_secondary(primary
, secondary
);
1762 assert(secondary
->perf_query_pool
== NULL
|| primary
->perf_query_pool
== NULL
||
1763 secondary
->perf_query_pool
== primary
->perf_query_pool
);
1764 if (secondary
->perf_query_pool
)
1765 primary
->perf_query_pool
= secondary
->perf_query_pool
;
1768 /* The secondary isn't counted in our VF cache tracking so we need to
1769 * invalidate the whole thing.
1771 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1772 primary
->state
.pending_pipe_bits
|=
1773 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1776 /* The secondary may have selected a different pipeline (3D or compute) and
1777 * may have changed the current L3$ configuration. Reset our tracking
1778 * variables to invalid values to ensure that we re-emit these in the case
1779 * where we do any draws or compute dispatches from the primary after the
1780 * secondary has returned.
1782 primary
->state
.current_pipeline
= UINT32_MAX
;
1783 primary
->state
.current_l3_config
= NULL
;
1784 primary
->state
.current_hash_scale
= 0;
1786 /* Each of the secondary command buffers will use its own state base
1787 * address. We need to re-emit state base address for the primary after
1788 * all of the secondaries are done.
1790 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1793 genX(cmd_buffer_emit_state_base_address
)(primary
);
1796 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1797 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1798 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1801 * Program the hardware to use the specified L3 configuration.
1804 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1805 const struct gen_l3_config
*cfg
)
1808 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1811 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1812 intel_logd("L3 config transition: ");
1813 gen_dump_l3_config(cfg
, stderr
);
1816 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1818 /* According to the hardware docs, the L3 partitioning can only be changed
1819 * while the pipeline is completely drained and the caches are flushed,
1820 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1822 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1823 pc
.DCFlushEnable
= true;
1824 pc
.PostSyncOperation
= NoWrite
;
1825 pc
.CommandStreamerStallEnable
= true;
1828 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1829 * invalidation of the relevant caches. Note that because RO invalidation
1830 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1831 * command is processed by the CS) we cannot combine it with the previous
1832 * stalling flush as the hardware documentation suggests, because that
1833 * would cause the CS to stall on previous rendering *after* RO
1834 * invalidation and wouldn't prevent the RO caches from being polluted by
1835 * concurrent rendering before the stall completes. This intentionally
1836 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1837 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1838 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1839 * already guarantee that there is no concurrent GPGPU kernel execution
1840 * (see SKL HSD 2132585).
1842 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1843 pc
.TextureCacheInvalidationEnable
= true;
1844 pc
.ConstantCacheInvalidationEnable
= true;
1845 pc
.InstructionCacheInvalidateEnable
= true;
1846 pc
.StateCacheInvalidationEnable
= true;
1847 pc
.PostSyncOperation
= NoWrite
;
1850 /* Now send a third stalling flush to make sure that invalidation is
1851 * complete when the L3 configuration registers are modified.
1853 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1854 pc
.DCFlushEnable
= true;
1855 pc
.PostSyncOperation
= NoWrite
;
1856 pc
.CommandStreamerStallEnable
= true;
1861 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1864 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1865 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1867 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1868 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1872 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1874 .SLMEnable
= has_slm
,
1877 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1878 * in L3CNTLREG register. The default setting of the bit is not the
1879 * desirable behavior.
1881 .ErrorDetectionBehaviorControl
= true,
1882 .UseFullWays
= true,
1884 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1885 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1886 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1887 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1889 /* Set up the L3 partitioning. */
1890 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1894 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1895 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1896 cfg
->n
[GEN_L3P_ALL
];
1897 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1898 cfg
->n
[GEN_L3P_ALL
];
1899 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1900 cfg
->n
[GEN_L3P_ALL
];
1902 assert(!cfg
->n
[GEN_L3P_ALL
]);
1904 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1905 * the matching space on the remaining banks has to be allocated to a
1906 * client (URB for all validated configurations) set to the
1907 * lower-bandwidth 2-bank address hashing mode.
1909 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1910 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1911 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1913 /* Minimum number of ways that can be allocated to the URB. */
1914 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1915 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1917 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1918 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1919 .ConvertDC_UC
= !has_dc
,
1920 .ConvertIS_UC
= !has_is
,
1921 .ConvertC_UC
= !has_c
,
1922 .ConvertT_UC
= !has_t
);
1924 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1925 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1926 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1928 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1929 .SLMEnable
= has_slm
,
1930 .URBLowBandwidth
= urb_low_bw
,
1931 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1933 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1935 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1936 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1938 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1939 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1940 .ISLowBandwidth
= 0,
1941 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1943 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1944 .TLowBandwidth
= 0);
1946 /* Set up the L3 partitioning. */
1947 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1948 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1949 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1952 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1953 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1954 * them disabled to avoid crashing the system hard.
1956 uint32_t scratch1
, chicken3
;
1957 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1958 .L3AtomicDisable
= !has_dc
);
1959 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1960 .L3AtomicDisableMask
= true,
1961 .L3AtomicDisable
= !has_dc
);
1962 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1963 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1969 cmd_buffer
->state
.current_l3_config
= cfg
;
1973 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1975 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1976 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1978 if (cmd_buffer
->device
->physical
->always_flush_cache
)
1979 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1982 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
1984 * Write synchronization is a special case of end-of-pipe
1985 * synchronization that requires that the render cache and/or depth
1986 * related caches are flushed to memory, where the data will become
1987 * globally visible. This type of synchronization is required prior to
1988 * SW (CPU) actually reading the result data from memory, or initiating
1989 * an operation that will use as a read surface (such as a texture
1990 * surface) a previous render target and/or depth/stencil buffer
1993 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
1995 * Exercising the write cache flush bits (Render Target Cache Flush
1996 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
1997 * ensures the write caches are flushed and doesn't guarantee the data
1998 * is globally visible.
2000 * SW can track the completion of the end-of-pipe-synchronization by
2001 * using "Notify Enable" and "PostSync Operation - Write Immediate
2002 * Data" in the PIPE_CONTROL command.
2004 * In other words, flushes are pipelined while invalidations are handled
2005 * immediately. Therefore, if we're flushing anything then we need to
2006 * schedule an end-of-pipe sync before any invalidations can happen.
2008 if (bits
& ANV_PIPE_FLUSH_BITS
)
2009 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2012 /* HSD 1209978178: docs say that before programming the aux table:
2014 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2015 * add extra flushes in the case it knows that the engine is already
2018 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
))
2019 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2021 /* If we're going to do an invalidate and we have a pending end-of-pipe
2022 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2024 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2025 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2026 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2027 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2030 if (GEN_GEN
>= 12 &&
2031 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2032 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2033 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2036 * Unified Cache (Tile Cache Disabled):
2038 * When the Color and Depth (Z) streams are enabled to be cached in
2039 * the DC space of L2, Software must use "Render Target Cache Flush
2040 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2041 * Flush" for getting the color and depth (Z) write data to be
2042 * globally observable. In this mode of operation it is not required
2043 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2045 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2048 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2049 * invalidates the instruction cache
2051 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2052 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2054 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2055 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2056 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2057 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2058 * both) then we can reset our vertex cache tracking.
2060 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2061 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2062 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2063 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2066 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2068 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2069 * programmed prior to programming a PIPECONTROL command with "LRI
2070 * Post Sync Operation" in GPGPU mode of operation (i.e when
2071 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2073 * The same text exists a few rows below for Post Sync Op.
2075 * On Gen12 this is GEN:BUG:1607156449.
2077 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2078 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2079 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2080 bits
|= ANV_PIPE_CS_STALL_BIT
;
2081 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2084 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2085 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2086 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2088 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2090 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2091 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2092 pipe
.RenderTargetCacheFlushEnable
=
2093 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2095 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2096 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2099 pipe
.DepthStallEnable
=
2100 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2102 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2105 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2106 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2108 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2110 * "The most common action to perform upon reaching a
2111 * synchronization point is to write a value out to memory. An
2112 * immediate value (included with the synchronization command) may
2116 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2118 * "In case the data flushed out by the render engine is to be
2119 * read back in to the render engine in coherent manner, then the
2120 * render engine has to wait for the fence completion before
2121 * accessing the flushed data. This can be achieved by following
2122 * means on various products: PIPE_CONTROL command with CS Stall
2123 * and the required write caches flushed with Post-Sync-Operation
2124 * as Write Immediate Data.
2127 * - Workload-1 (3D/GPGPU/MEDIA)
2128 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2129 * Immediate Data, Required Write Cache Flush bits set)
2130 * - Workload-2 (Can use the data produce or output by
2133 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2134 pipe
.CommandStreamerStallEnable
= true;
2135 pipe
.PostSyncOperation
= WriteImmediateData
;
2136 pipe
.Address
= (struct anv_address
) {
2137 .bo
= cmd_buffer
->device
->workaround_bo
,
2143 * According to the Broadwell documentation, any PIPE_CONTROL with the
2144 * "Command Streamer Stall" bit set must also have another bit set,
2145 * with five different options:
2147 * - Render Target Cache Flush
2148 * - Depth Cache Flush
2149 * - Stall at Pixel Scoreboard
2150 * - Post-Sync Operation
2154 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2155 * mesa and it seems to work fine. The choice is fairly arbitrary.
2157 if (pipe
.CommandStreamerStallEnable
&&
2158 !pipe
.RenderTargetCacheFlushEnable
&&
2159 !pipe
.DepthCacheFlushEnable
&&
2160 !pipe
.StallAtPixelScoreboard
&&
2161 !pipe
.PostSyncOperation
&&
2162 !pipe
.DepthStallEnable
&&
2163 !pipe
.DCFlushEnable
)
2164 pipe
.StallAtPixelScoreboard
= true;
2167 /* If a render target flush was emitted, then we can toggle off the bit
2168 * saying that render target writes are ongoing.
2170 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2171 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2173 if (GEN_IS_HASWELL
) {
2174 /* Haswell needs addition work-arounds:
2176 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2179 * PIPE_CONTROL command with the CS Stall and the required write
2180 * caches flushed with Post-SyncOperation as Write Immediate Data
2181 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2186 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2187 * Immediate Data, Required Write Cache Flush bits set)
2188 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2189 * - Workload-2 (Can use the data produce or output by
2192 * Unfortunately, both the PRMs and the internal docs are a bit
2193 * out-of-date in this regard. What the windows driver does (and
2194 * this appears to actually work) is to emit a register read from the
2195 * memory address written by the pipe control above.
2197 * What register we load into doesn't matter. We choose an indirect
2198 * rendering register because we know it always exists and it's one
2199 * of the first registers the command parser allows us to write. If
2200 * you don't have command parser support in your kernel (pre-4.2),
2201 * this will get turned into MI_NOOP and you won't get the
2202 * workaround. Unfortunately, there's just not much we can do in
2203 * that case. This register is perfectly safe to write since we
2204 * always re-load all of the indirect draw registers right before
2205 * 3DPRIMITIVE when needed anyway.
2207 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2208 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2209 lrm
.MemoryAddress
= (struct anv_address
) {
2210 .bo
= cmd_buffer
->device
->workaround_bo
,
2216 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2217 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2220 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2221 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2223 * "If the VF Cache Invalidation Enable is set to a 1 in a
2224 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2225 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2226 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2229 * This appears to hang Broadwell, so we restrict it to just gen9.
2231 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2232 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2234 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2235 pipe
.StateCacheInvalidationEnable
=
2236 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2237 pipe
.ConstantCacheInvalidationEnable
=
2238 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2239 pipe
.VFCacheInvalidationEnable
=
2240 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2241 pipe
.TextureCacheInvalidationEnable
=
2242 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2243 pipe
.InstructionCacheInvalidateEnable
=
2244 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2246 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2248 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2249 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2250 * “Write Timestamp”.
2252 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2253 pipe
.PostSyncOperation
= WriteImmediateData
;
2255 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2260 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2261 cmd_buffer
->device
->info
.has_aux_map
) {
2262 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2263 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2269 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2272 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2275 void genX(CmdPipelineBarrier
)(
2276 VkCommandBuffer commandBuffer
,
2277 VkPipelineStageFlags srcStageMask
,
2278 VkPipelineStageFlags destStageMask
,
2280 uint32_t memoryBarrierCount
,
2281 const VkMemoryBarrier
* pMemoryBarriers
,
2282 uint32_t bufferMemoryBarrierCount
,
2283 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2284 uint32_t imageMemoryBarrierCount
,
2285 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2287 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2289 /* XXX: Right now, we're really dumb and just flush whatever categories
2290 * the app asks for. One of these days we may make this a bit better
2291 * but right now that's all the hardware allows for in most areas.
2293 VkAccessFlags src_flags
= 0;
2294 VkAccessFlags dst_flags
= 0;
2296 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2297 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2298 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2301 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2302 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2303 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2306 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2307 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2308 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2309 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2310 const VkImageSubresourceRange
*range
=
2311 &pImageMemoryBarriers
[i
].subresourceRange
;
2313 uint32_t base_layer
, layer_count
;
2314 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2316 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2318 base_layer
= range
->baseArrayLayer
;
2319 layer_count
= anv_get_layerCount(image
, range
);
2322 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2323 transition_depth_buffer(cmd_buffer
, image
,
2324 base_layer
, layer_count
,
2325 pImageMemoryBarriers
[i
].oldLayout
,
2326 pImageMemoryBarriers
[i
].newLayout
);
2329 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2330 transition_stencil_buffer(cmd_buffer
, image
,
2331 range
->baseMipLevel
,
2332 anv_get_levelCount(image
, range
),
2333 base_layer
, layer_count
,
2334 pImageMemoryBarriers
[i
].oldLayout
,
2335 pImageMemoryBarriers
[i
].newLayout
);
2338 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2339 VkImageAspectFlags color_aspects
=
2340 anv_image_expand_aspects(image
, range
->aspectMask
);
2341 uint32_t aspect_bit
;
2342 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2343 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2344 range
->baseMipLevel
,
2345 anv_get_levelCount(image
, range
),
2346 base_layer
, layer_count
,
2347 pImageMemoryBarriers
[i
].oldLayout
,
2348 pImageMemoryBarriers
[i
].newLayout
);
2353 cmd_buffer
->state
.pending_pipe_bits
|=
2354 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2355 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2359 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2361 VkShaderStageFlags stages
=
2362 cmd_buffer
->state
.gfx
.pipeline
->active_stages
;
2364 /* In order to avoid thrash, we assume that vertex and fragment stages
2365 * always exist. In the rare case where one is missing *and* the other
2366 * uses push concstants, this may be suboptimal. However, avoiding stalls
2367 * seems more important.
2369 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2371 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2375 const unsigned push_constant_kb
= 32;
2376 #elif GEN_IS_HASWELL
2377 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2379 const unsigned push_constant_kb
= 16;
2382 const unsigned num_stages
=
2383 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2384 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2386 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2387 * units of 2KB. Incidentally, these are the same platforms that have
2388 * 32KB worth of push constant space.
2390 if (push_constant_kb
== 32)
2391 size_per_stage
&= ~1u;
2393 uint32_t kb_used
= 0;
2394 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2395 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2396 anv_batch_emit(&cmd_buffer
->batch
,
2397 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2398 alloc
._3DCommandSubOpcode
= 18 + i
;
2399 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2400 alloc
.ConstantBufferSize
= push_size
;
2402 kb_used
+= push_size
;
2405 anv_batch_emit(&cmd_buffer
->batch
,
2406 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2407 alloc
.ConstantBufferOffset
= kb_used
;
2408 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2411 cmd_buffer
->state
.push_constant_stages
= stages
;
2413 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2415 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2416 * the next 3DPRIMITIVE command after programming the
2417 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2419 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2420 * pipeline setup, we need to dirty push constants.
2422 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2425 static struct anv_address
2426 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2427 struct anv_descriptor_set
*set
)
2430 /* This is a normal descriptor set */
2431 return (struct anv_address
) {
2432 .bo
= set
->pool
->bo
,
2433 .offset
= set
->desc_mem
.offset
,
2436 /* This is a push descriptor set. We have to flag it as used on the GPU
2437 * so that the next time we push descriptors, we grab a new memory.
2439 struct anv_push_descriptor_set
*push_set
=
2440 (struct anv_push_descriptor_set
*)set
;
2441 push_set
->set_used_on_gpu
= true;
2443 return (struct anv_address
) {
2444 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2445 .offset
= set
->desc_mem
.offset
,
2451 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2452 struct anv_cmd_pipeline_state
*pipe_state
,
2453 struct anv_shader_bin
*shader
,
2454 struct anv_state
*bt_state
)
2456 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2457 uint32_t state_offset
;
2459 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2460 if (map
->surface_count
== 0) {
2461 *bt_state
= (struct anv_state
) { 0, };
2465 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2468 uint32_t *bt_map
= bt_state
->map
;
2470 if (bt_state
->map
== NULL
)
2471 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2473 /* We only need to emit relocs if we're not using softpin. If we are using
2474 * softpin then we always keep all user-allocated memory objects resident.
2476 const bool need_client_mem_relocs
=
2477 !cmd_buffer
->device
->physical
->use_softpin
;
2479 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2480 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2482 struct anv_state surface_state
;
2484 switch (binding
->set
) {
2485 case ANV_DESCRIPTOR_SET_NULL
:
2489 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2490 /* Color attachment binding */
2491 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2492 if (binding
->index
< subpass
->color_count
) {
2493 const unsigned att
=
2494 subpass
->color_attachments
[binding
->index
].attachment
;
2496 /* From the Vulkan 1.0.46 spec:
2498 * "If any color or depth/stencil attachments are
2499 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2502 if (att
== VK_ATTACHMENT_UNUSED
) {
2503 surface_state
= cmd_buffer
->state
.null_surface_state
;
2505 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2508 surface_state
= cmd_buffer
->state
.null_surface_state
;
2511 assert(surface_state
.map
);
2512 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2515 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2516 struct anv_state surface_state
=
2517 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2519 struct anv_address constant_data
= {
2520 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2521 .offset
= shader
->constant_data
.offset
,
2523 unsigned constant_data_size
= shader
->constant_data_size
;
2525 const enum isl_format format
=
2526 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2527 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2528 surface_state
, format
,
2529 constant_data
, constant_data_size
, 1);
2531 assert(surface_state
.map
);
2532 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2533 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2537 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2538 /* This is always the first binding for compute shaders */
2539 assert(shader
->stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2541 struct anv_state surface_state
=
2542 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2544 const enum isl_format format
=
2545 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2546 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2548 cmd_buffer
->state
.compute
.num_workgroups
,
2551 assert(surface_state
.map
);
2552 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2553 if (need_client_mem_relocs
) {
2554 add_surface_reloc(cmd_buffer
, surface_state
,
2555 cmd_buffer
->state
.compute
.num_workgroups
);
2560 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2561 /* This is a descriptor set buffer so the set index is actually
2562 * given by binding->binding. (Yes, that's confusing.)
2564 struct anv_descriptor_set
*set
=
2565 pipe_state
->descriptors
[binding
->index
];
2566 assert(set
->desc_mem
.alloc_size
);
2567 assert(set
->desc_surface_state
.alloc_size
);
2568 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2569 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2570 anv_descriptor_set_address(cmd_buffer
, set
));
2575 assert(binding
->set
< MAX_SETS
);
2576 const struct anv_descriptor
*desc
=
2577 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2579 switch (desc
->type
) {
2580 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2581 /* Nothing for us to do here */
2584 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2585 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2586 if (desc
->image_view
) {
2587 struct anv_surface_state sstate
=
2588 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2589 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2590 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2591 surface_state
= sstate
.state
;
2592 assert(surface_state
.alloc_size
);
2593 if (need_client_mem_relocs
)
2594 add_surface_state_relocs(cmd_buffer
, sstate
);
2596 surface_state
= cmd_buffer
->device
->null_surface_state
;
2600 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2601 assert(shader
->stage
== MESA_SHADER_FRAGMENT
);
2602 assert(desc
->image_view
!= NULL
);
2603 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2604 /* For depth and stencil input attachments, we treat it like any
2605 * old texture that a user may have bound.
2607 assert(desc
->image_view
->n_planes
== 1);
2608 struct anv_surface_state sstate
=
2609 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2610 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2611 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2612 surface_state
= sstate
.state
;
2613 assert(surface_state
.alloc_size
);
2614 if (need_client_mem_relocs
)
2615 add_surface_state_relocs(cmd_buffer
, sstate
);
2617 /* For color input attachments, we create the surface state at
2618 * vkBeginRenderPass time so that we can include aux and clear
2619 * color information.
2621 assert(binding
->input_attachment_index
< subpass
->input_count
);
2622 const unsigned subpass_att
= binding
->input_attachment_index
;
2623 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2624 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2628 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2629 if (desc
->image_view
) {
2630 struct anv_surface_state sstate
= (binding
->write_only
)
2631 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2632 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2633 surface_state
= sstate
.state
;
2634 assert(surface_state
.alloc_size
);
2635 if (need_client_mem_relocs
)
2636 add_surface_state_relocs(cmd_buffer
, sstate
);
2638 surface_state
= cmd_buffer
->device
->null_surface_state
;
2643 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2644 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2645 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2646 if (desc
->buffer_view
) {
2647 surface_state
= desc
->buffer_view
->surface_state
;
2648 assert(surface_state
.alloc_size
);
2649 if (need_client_mem_relocs
) {
2650 add_surface_reloc(cmd_buffer
, surface_state
,
2651 desc
->buffer_view
->address
);
2654 surface_state
= cmd_buffer
->device
->null_surface_state
;
2658 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2659 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2661 /* Compute the offset within the buffer */
2662 struct anv_push_constants
*push
=
2663 &cmd_buffer
->state
.push_constants
[shader
->stage
];
2665 uint32_t dynamic_offset
=
2666 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2667 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2668 /* Clamp to the buffer size */
2669 offset
= MIN2(offset
, desc
->buffer
->size
);
2670 /* Clamp the range to the buffer size */
2671 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2673 /* Align the range for consistency */
2674 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
)
2675 range
= align_u32(range
, ANV_UBO_ALIGNMENT
);
2677 struct anv_address address
=
2678 anv_address_add(desc
->buffer
->address
, offset
);
2681 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2682 enum isl_format format
=
2683 anv_isl_format_for_descriptor_type(desc
->type
);
2685 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2686 format
, address
, range
, 1);
2687 if (need_client_mem_relocs
)
2688 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2690 surface_state
= cmd_buffer
->device
->null_surface_state
;
2695 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2696 if (desc
->buffer_view
) {
2697 surface_state
= (binding
->write_only
)
2698 ? desc
->buffer_view
->writeonly_storage_surface_state
2699 : desc
->buffer_view
->storage_surface_state
;
2700 assert(surface_state
.alloc_size
);
2701 if (need_client_mem_relocs
) {
2702 add_surface_reloc(cmd_buffer
, surface_state
,
2703 desc
->buffer_view
->address
);
2706 surface_state
= cmd_buffer
->device
->null_surface_state
;
2711 assert(!"Invalid descriptor type");
2714 assert(surface_state
.map
);
2715 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2725 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2726 struct anv_cmd_pipeline_state
*pipe_state
,
2727 struct anv_shader_bin
*shader
,
2728 struct anv_state
*state
)
2730 struct anv_pipeline_bind_map
*map
= &shader
->bind_map
;
2731 if (map
->sampler_count
== 0) {
2732 *state
= (struct anv_state
) { 0, };
2736 uint32_t size
= map
->sampler_count
* 16;
2737 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2739 if (state
->map
== NULL
)
2740 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2742 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2743 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2744 const struct anv_descriptor
*desc
=
2745 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2747 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2748 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2751 struct anv_sampler
*sampler
= desc
->sampler
;
2753 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2754 * happens to be zero.
2756 if (sampler
== NULL
)
2759 memcpy(state
->map
+ (s
* 16),
2760 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2767 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2768 struct anv_cmd_pipeline_state
*pipe_state
,
2769 struct anv_shader_bin
**shaders
,
2770 uint32_t num_shaders
)
2772 const VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
;
2773 VkShaderStageFlags flushed
= 0;
2775 VkResult result
= VK_SUCCESS
;
2776 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2780 gl_shader_stage stage
= shaders
[i
]->stage
;
2781 VkShaderStageFlags vk_stage
= mesa_to_vk_shader_stage(stage
);
2782 if ((vk_stage
& dirty
) == 0)
2785 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2786 &cmd_buffer
->state
.samplers
[stage
]);
2787 if (result
!= VK_SUCCESS
)
2789 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2790 &cmd_buffer
->state
.binding_tables
[stage
]);
2791 if (result
!= VK_SUCCESS
)
2794 flushed
|= vk_stage
;
2797 if (result
!= VK_SUCCESS
) {
2798 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2800 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2801 if (result
!= VK_SUCCESS
)
2804 /* Re-emit state base addresses so we get the new surface state base
2805 * address before we start emitting binding tables etc.
2807 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2809 /* Re-emit all active binding tables */
2812 for (uint32_t i
= 0; i
< num_shaders
; i
++) {
2816 gl_shader_stage stage
= shaders
[i
]->stage
;
2818 result
= emit_samplers(cmd_buffer
, pipe_state
, shaders
[i
],
2819 &cmd_buffer
->state
.samplers
[stage
]);
2820 if (result
!= VK_SUCCESS
) {
2821 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2824 result
= emit_binding_table(cmd_buffer
, pipe_state
, shaders
[i
],
2825 &cmd_buffer
->state
.binding_tables
[stage
]);
2826 if (result
!= VK_SUCCESS
) {
2827 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2831 flushed
|= mesa_to_vk_shader_stage(stage
);
2835 cmd_buffer
->state
.descriptors_dirty
&= ~flushed
;
2841 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2844 static const uint32_t sampler_state_opcodes
[] = {
2845 [MESA_SHADER_VERTEX
] = 43,
2846 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2847 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2848 [MESA_SHADER_GEOMETRY
] = 46,
2849 [MESA_SHADER_FRAGMENT
] = 47,
2850 [MESA_SHADER_COMPUTE
] = 0,
2853 static const uint32_t binding_table_opcodes
[] = {
2854 [MESA_SHADER_VERTEX
] = 38,
2855 [MESA_SHADER_TESS_CTRL
] = 39,
2856 [MESA_SHADER_TESS_EVAL
] = 40,
2857 [MESA_SHADER_GEOMETRY
] = 41,
2858 [MESA_SHADER_FRAGMENT
] = 42,
2859 [MESA_SHADER_COMPUTE
] = 0,
2862 anv_foreach_stage(s
, stages
) {
2863 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2864 assert(binding_table_opcodes
[s
] > 0);
2866 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2867 anv_batch_emit(&cmd_buffer
->batch
,
2868 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2869 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2870 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2874 /* Always emit binding table pointers if we're asked to, since on SKL
2875 * this is what flushes push constants. */
2876 anv_batch_emit(&cmd_buffer
->batch
,
2877 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2878 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2879 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2884 static struct anv_address
2885 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2886 gl_shader_stage stage
,
2887 const struct anv_push_range
*range
)
2889 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2890 switch (range
->set
) {
2891 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2892 /* This is a descriptor set buffer so the set index is
2893 * actually given by binding->binding. (Yes, that's
2896 struct anv_descriptor_set
*set
=
2897 gfx_state
->base
.descriptors
[range
->index
];
2898 return anv_descriptor_set_address(cmd_buffer
, set
);
2901 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2902 struct anv_state state
=
2903 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2904 return (struct anv_address
) {
2905 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2906 .offset
= state
.offset
,
2911 assert(range
->set
< MAX_SETS
);
2912 struct anv_descriptor_set
*set
=
2913 gfx_state
->base
.descriptors
[range
->set
];
2914 const struct anv_descriptor
*desc
=
2915 &set
->descriptors
[range
->index
];
2917 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2918 if (desc
->buffer_view
)
2919 return desc
->buffer_view
->address
;
2921 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2923 struct anv_push_constants
*push
=
2924 &cmd_buffer
->state
.push_constants
[stage
];
2925 uint32_t dynamic_offset
=
2926 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2927 return anv_address_add(desc
->buffer
->address
,
2928 desc
->offset
+ dynamic_offset
);
2932 /* For NULL UBOs, we just return an address in the workaround BO. We do
2933 * writes to it for workarounds but always at the bottom. The higher
2934 * bytes should be all zeros.
2936 assert(range
->length
* 32 <= 2048);
2937 return (struct anv_address
) {
2938 .bo
= cmd_buffer
->device
->workaround_bo
,
2946 /** Returns the size in bytes of the bound buffer
2948 * The range is relative to the start of the buffer, not the start of the
2949 * range. The returned range may be smaller than
2951 * (range->start + range->length) * 32;
2954 get_push_range_bound_size(struct anv_cmd_buffer
*cmd_buffer
,
2955 gl_shader_stage stage
,
2956 const struct anv_push_range
*range
)
2958 assert(stage
!= MESA_SHADER_COMPUTE
);
2959 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2960 switch (range
->set
) {
2961 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2962 struct anv_descriptor_set
*set
=
2963 gfx_state
->base
.descriptors
[range
->index
];
2964 assert(range
->start
* 32 < set
->desc_mem
.alloc_size
);
2965 assert((range
->start
+ range
->length
) * 32 <= set
->desc_mem
.alloc_size
);
2966 return set
->desc_mem
.alloc_size
;
2969 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
:
2970 return (range
->start
+ range
->length
) * 32;
2973 assert(range
->set
< MAX_SETS
);
2974 struct anv_descriptor_set
*set
=
2975 gfx_state
->base
.descriptors
[range
->set
];
2976 const struct anv_descriptor
*desc
=
2977 &set
->descriptors
[range
->index
];
2979 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2980 if (!desc
->buffer_view
)
2983 if (range
->start
* 32 > desc
->buffer_view
->range
)
2986 return desc
->buffer_view
->range
;
2991 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2992 /* Compute the offset within the buffer */
2993 struct anv_push_constants
*push
=
2994 &cmd_buffer
->state
.push_constants
[stage
];
2995 uint32_t dynamic_offset
=
2996 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2997 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2998 /* Clamp to the buffer size */
2999 offset
= MIN2(offset
, desc
->buffer
->size
);
3000 /* Clamp the range to the buffer size */
3001 uint32_t bound_range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
3003 /* Align the range for consistency */
3004 bound_range
= align_u32(bound_range
, ANV_UBO_ALIGNMENT
);
3013 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
3014 gl_shader_stage stage
,
3015 struct anv_address
*buffers
,
3016 unsigned buffer_count
)
3018 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3019 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3021 static const uint32_t push_constant_opcodes
[] = {
3022 [MESA_SHADER_VERTEX
] = 21,
3023 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3024 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3025 [MESA_SHADER_GEOMETRY
] = 22,
3026 [MESA_SHADER_FRAGMENT
] = 23,
3027 [MESA_SHADER_COMPUTE
] = 0,
3030 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3031 assert(push_constant_opcodes
[stage
] > 0);
3033 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
3034 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
3036 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3037 const struct anv_pipeline_bind_map
*bind_map
=
3038 &pipeline
->shaders
[stage
]->bind_map
;
3041 /* This field exists since Gen8. However, the Broadwell PRM says:
3043 * "Constant Buffer Object Control State must be always programmed
3046 * This restriction does not exist on any newer platforms.
3048 * We only have one MOCS field for the whole packet, not one per
3049 * buffer. We could go out of our way here to walk over all of the
3050 * buffers and see if any of them are used externally and use the
3051 * external MOCS. However, the notion that someone would use the
3052 * same bit of memory for both scanout and a UBO is nuts. Let's not
3053 * bother and assume it's all internal.
3055 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3058 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3059 /* The Skylake PRM contains the following restriction:
3061 * "The driver must ensure The following case does not occur
3062 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
3063 * buffer 3 read length equal to zero committed followed by a
3064 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
3067 * To avoid this, we program the buffers in the highest slots.
3068 * This way, slot 0 is only used if slot 3 is also used.
3070 assert(buffer_count
<= 4);
3071 const unsigned shift
= 4 - buffer_count
;
3072 for (unsigned i
= 0; i
< buffer_count
; i
++) {
3073 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3075 /* At this point we only have non-empty ranges */
3076 assert(range
->length
> 0);
3078 /* For Ivy Bridge, make sure we only set the first range (actual
3081 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
3083 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
3084 c
.ConstantBody
.Buffer
[i
+ shift
] =
3085 anv_address_add(buffers
[i
], range
->start
* 32);
3088 /* For Ivy Bridge, push constants are relative to dynamic state
3089 * base address and we only ever push actual push constants.
3091 if (bind_map
->push_ranges
[0].length
> 0) {
3092 assert(buffer_count
== 1);
3093 assert(bind_map
->push_ranges
[0].set
==
3094 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3095 assert(buffers
[0].bo
==
3096 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
);
3097 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3098 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3099 c
.ConstantBody
.Buffer
[0].offset
= buffers
[0].offset
;
3101 assert(bind_map
->push_ranges
[1].length
== 0);
3102 assert(bind_map
->push_ranges
[2].length
== 0);
3103 assert(bind_map
->push_ranges
[3].length
== 0);
3111 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3112 uint32_t shader_mask
,
3113 struct anv_address
*buffers
,
3114 uint32_t buffer_count
)
3116 if (buffer_count
== 0) {
3117 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3118 c
.ShaderUpdateEnable
= shader_mask
;
3119 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3124 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3125 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3127 static const uint32_t push_constant_opcodes
[] = {
3128 [MESA_SHADER_VERTEX
] = 21,
3129 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3130 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3131 [MESA_SHADER_GEOMETRY
] = 22,
3132 [MESA_SHADER_FRAGMENT
] = 23,
3133 [MESA_SHADER_COMPUTE
] = 0,
3136 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3137 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3138 assert(push_constant_opcodes
[stage
] > 0);
3140 const struct anv_pipeline_bind_map
*bind_map
=
3141 &pipeline
->shaders
[stage
]->bind_map
;
3144 const uint32_t buffer_mask
= (1 << buffer_count
) - 1;
3145 const uint32_t num_dwords
= 2 + 2 * buffer_count
;
3147 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3148 GENX(3DSTATE_CONSTANT_ALL
),
3149 .ShaderUpdateEnable
= shader_mask
,
3150 .PointerBufferMask
= buffer_mask
,
3151 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3153 for (int i
= 0; i
< buffer_count
; i
++) {
3154 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3155 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3156 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3157 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3158 .PointerToConstantBuffer
=
3159 anv_address_add(buffers
[i
], range
->start
* 32),
3160 .ConstantBufferReadLength
= range
->length
,
3167 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3168 VkShaderStageFlags dirty_stages
)
3170 VkShaderStageFlags flushed
= 0;
3171 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3172 const struct anv_graphics_pipeline
*pipeline
= gfx_state
->pipeline
;
3175 uint32_t nobuffer_stages
= 0;
3178 anv_foreach_stage(stage
, dirty_stages
) {
3179 unsigned buffer_count
= 0;
3180 flushed
|= mesa_to_vk_shader_stage(stage
);
3181 UNUSED
uint32_t max_push_range
= 0;
3183 struct anv_address buffers
[4] = {};
3184 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3185 const struct anv_pipeline_bind_map
*bind_map
=
3186 &pipeline
->shaders
[stage
]->bind_map
;
3187 struct anv_push_constants
*push
=
3188 &cmd_buffer
->state
.push_constants
[stage
];
3190 if (cmd_buffer
->device
->robust_buffer_access
) {
3191 push
->push_reg_mask
= 0;
3192 /* Start of the current range in the shader, relative to the start
3193 * of push constants in the shader.
3195 unsigned range_start_reg
= 0;
3196 for (unsigned i
= 0; i
< 4; i
++) {
3197 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3198 if (range
->length
== 0)
3201 unsigned bound_size
=
3202 get_push_range_bound_size(cmd_buffer
, stage
, range
);
3203 if (bound_size
>= range
->start
* 32) {
3204 unsigned bound_regs
=
3205 MIN2(DIV_ROUND_UP(bound_size
, 32) - range
->start
,
3207 assert(range_start_reg
+ bound_regs
<= 64);
3208 push
->push_reg_mask
|= BITFIELD64_RANGE(range_start_reg
,
3212 cmd_buffer
->state
.push_constants_dirty
|=
3213 mesa_to_vk_shader_stage(stage
);
3215 range_start_reg
+= range
->length
;
3219 /* We have to gather buffer addresses as a second step because the
3220 * loop above puts data into the push constant area and the call to
3221 * get_push_range_address is what locks our push constants and copies
3222 * them into the actual GPU buffer. If we did the two loops at the
3223 * same time, we'd risk only having some of the sizes in the push
3224 * constant buffer when we did the copy.
3226 for (unsigned i
= 0; i
< 4; i
++) {
3227 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3228 if (range
->length
== 0)
3231 buffers
[i
] = get_push_range_address(cmd_buffer
, stage
, range
);
3232 max_push_range
= MAX2(max_push_range
, range
->length
);
3236 /* We have at most 4 buffers but they should be tightly packed */
3237 for (unsigned i
= buffer_count
; i
< 4; i
++)
3238 assert(bind_map
->push_ranges
[i
].length
== 0);
3242 /* If this stage doesn't have any push constants, emit it later in a
3243 * single CONSTANT_ALL packet.
3245 if (buffer_count
== 0) {
3246 nobuffer_stages
|= 1 << stage
;
3250 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3251 * contains only 5 bits, so we can only use it for buffers smaller than
3254 if (max_push_range
< 32) {
3255 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3256 buffers
, buffer_count
);
3261 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffers
, buffer_count
);
3265 if (nobuffer_stages
)
3266 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, NULL
, 0);
3269 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3273 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3275 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3278 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3280 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
3282 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3284 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3286 /* Apply any pending pipeline flushes we may have. We want to apply them
3287 * now because, if any of those flushes are for things like push constants,
3288 * the GPU will read the state at weird times.
3290 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3292 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3293 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3294 vb_emit
|= pipeline
->vb_used
;
3297 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3298 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3300 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3301 GENX(3DSTATE_VERTEX_BUFFERS
));
3303 for_each_bit(vb
, vb_emit
) {
3304 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3305 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3307 struct GENX(VERTEX_BUFFER_STATE
) state
;
3309 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3310 .VertexBufferIndex
= vb
,
3312 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3314 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3315 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3318 .AddressModifyEnable
= true,
3319 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3320 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3321 .NullVertexBuffer
= offset
>= buffer
->size
,
3324 .BufferSize
= buffer
->size
- offset
3326 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3330 state
= (struct GENX(VERTEX_BUFFER_STATE
)) {
3331 .VertexBufferIndex
= vb
,
3332 .NullVertexBuffer
= true,
3336 #if GEN_GEN >= 8 && GEN_GEN <= 9
3337 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3338 state
.BufferStartingAddress
,
3342 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3347 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3350 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3351 /* We don't need any per-buffer dirty tracking because you're not
3352 * allowed to bind different XFB buffers while XFB is enabled.
3354 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3355 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3356 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3358 sob
.SOBufferIndex
= idx
;
3360 sob
._3DCommandOpcode
= 0;
3361 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3364 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3365 sob
.SOBufferEnable
= true;
3366 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3367 sob
.StreamOffsetWriteEnable
= false;
3368 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3370 /* Size is in DWords - 1 */
3371 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3376 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3378 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3382 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3383 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
3385 /* If the pipeline changed, we may need to re-allocate push constant
3388 cmd_buffer_alloc_push_constants(cmd_buffer
);
3392 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3393 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3394 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3396 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3397 * stall needs to be sent just prior to any 3DSTATE_VS,
3398 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3399 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3400 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3401 * PIPE_CONTROL needs to be sent before any combination of VS
3402 * associated 3DSTATE."
3404 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3405 pc
.DepthStallEnable
= true;
3406 pc
.PostSyncOperation
= WriteImmediateData
;
3408 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
3413 /* Render targets live in the same binding table as fragment descriptors */
3414 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3415 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3417 /* We emit the binding tables and sampler tables first, then emit push
3418 * constants and then finally emit binding table and sampler table
3419 * pointers. It has to happen in this order, since emitting the binding
3420 * tables may change the push constants (in case of storage images). After
3421 * emitting push constants, on SKL+ we have to emit the corresponding
3422 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3425 if (cmd_buffer
->state
.descriptors_dirty
) {
3426 dirty
= flush_descriptor_sets(cmd_buffer
,
3427 &cmd_buffer
->state
.gfx
.base
,
3429 ARRAY_SIZE(pipeline
->shaders
));
3432 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3433 /* Because we're pushing UBOs, we have to push whenever either
3434 * descriptors or push constants is dirty.
3436 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3437 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3438 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3442 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3444 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3445 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3447 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3448 ANV_CMD_DIRTY_PIPELINE
)) {
3449 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3450 pipeline
->depth_clamp_enable
);
3453 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3454 ANV_CMD_DIRTY_RENDER_TARGETS
))
3455 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3457 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3461 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3462 struct anv_address addr
,
3463 uint32_t size
, uint32_t index
)
3465 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3466 GENX(3DSTATE_VERTEX_BUFFERS
));
3468 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3469 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3470 .VertexBufferIndex
= index
,
3471 .AddressModifyEnable
= true,
3473 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3474 .NullVertexBuffer
= size
== 0,
3476 .BufferStartingAddress
= addr
,
3479 .BufferStartingAddress
= addr
,
3480 .EndAddress
= anv_address_add(addr
, size
),
3484 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3489 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3490 struct anv_address addr
)
3492 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3496 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3497 uint32_t base_vertex
, uint32_t base_instance
)
3499 if (base_vertex
== 0 && base_instance
== 0) {
3500 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3502 struct anv_state id_state
=
3503 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3505 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3506 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3508 struct anv_address addr
= {
3509 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3510 .offset
= id_state
.offset
,
3513 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3518 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3520 struct anv_state state
=
3521 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3523 ((uint32_t *)state
.map
)[0] = draw_index
;
3525 struct anv_address addr
= {
3526 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3527 .offset
= state
.offset
,
3530 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3534 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3535 uint32_t access_type
)
3537 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3538 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3540 uint64_t vb_used
= pipeline
->vb_used
;
3541 if (vs_prog_data
->uses_firstvertex
||
3542 vs_prog_data
->uses_baseinstance
)
3543 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3544 if (vs_prog_data
->uses_drawid
)
3545 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3547 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3548 access_type
== RANDOM
,
3553 VkCommandBuffer commandBuffer
,
3554 uint32_t vertexCount
,
3555 uint32_t instanceCount
,
3556 uint32_t firstVertex
,
3557 uint32_t firstInstance
)
3559 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3560 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3561 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3563 if (anv_batch_has_error(&cmd_buffer
->batch
))
3566 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3568 if (cmd_buffer
->state
.conditional_render_enabled
)
3569 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3571 if (vs_prog_data
->uses_firstvertex
||
3572 vs_prog_data
->uses_baseinstance
)
3573 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3574 if (vs_prog_data
->uses_drawid
)
3575 emit_draw_index(cmd_buffer
, 0);
3577 /* Emitting draw index or vertex index BOs may result in needing
3578 * additional VF cache flushes.
3580 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3582 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3583 * different views. We need to multiply instanceCount by the view count.
3585 if (!pipeline
->use_primitive_replication
)
3586 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3588 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3589 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3590 prim
.VertexAccessType
= SEQUENTIAL
;
3591 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3592 prim
.VertexCountPerInstance
= vertexCount
;
3593 prim
.StartVertexLocation
= firstVertex
;
3594 prim
.InstanceCount
= instanceCount
;
3595 prim
.StartInstanceLocation
= firstInstance
;
3596 prim
.BaseVertexLocation
= 0;
3599 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3602 void genX(CmdDrawIndexed
)(
3603 VkCommandBuffer commandBuffer
,
3604 uint32_t indexCount
,
3605 uint32_t instanceCount
,
3606 uint32_t firstIndex
,
3607 int32_t vertexOffset
,
3608 uint32_t firstInstance
)
3610 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3611 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3612 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3614 if (anv_batch_has_error(&cmd_buffer
->batch
))
3617 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3619 if (cmd_buffer
->state
.conditional_render_enabled
)
3620 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3622 if (vs_prog_data
->uses_firstvertex
||
3623 vs_prog_data
->uses_baseinstance
)
3624 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3625 if (vs_prog_data
->uses_drawid
)
3626 emit_draw_index(cmd_buffer
, 0);
3628 /* Emitting draw index or vertex index BOs may result in needing
3629 * additional VF cache flushes.
3631 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3633 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3634 * different views. We need to multiply instanceCount by the view count.
3636 if (!pipeline
->use_primitive_replication
)
3637 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3639 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3640 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3641 prim
.VertexAccessType
= RANDOM
;
3642 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3643 prim
.VertexCountPerInstance
= indexCount
;
3644 prim
.StartVertexLocation
= firstIndex
;
3645 prim
.InstanceCount
= instanceCount
;
3646 prim
.StartInstanceLocation
= firstInstance
;
3647 prim
.BaseVertexLocation
= vertexOffset
;
3650 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3653 /* Auto-Draw / Indirect Registers */
3654 #define GEN7_3DPRIM_END_OFFSET 0x2420
3655 #define GEN7_3DPRIM_START_VERTEX 0x2430
3656 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3657 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3658 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3659 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3661 void genX(CmdDrawIndirectByteCountEXT
)(
3662 VkCommandBuffer commandBuffer
,
3663 uint32_t instanceCount
,
3664 uint32_t firstInstance
,
3665 VkBuffer counterBuffer
,
3666 VkDeviceSize counterBufferOffset
,
3667 uint32_t counterOffset
,
3668 uint32_t vertexStride
)
3670 #if GEN_IS_HASWELL || GEN_GEN >= 8
3671 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3672 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3673 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3674 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3676 /* firstVertex is always zero for this draw function */
3677 const uint32_t firstVertex
= 0;
3679 if (anv_batch_has_error(&cmd_buffer
->batch
))
3682 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3684 if (vs_prog_data
->uses_firstvertex
||
3685 vs_prog_data
->uses_baseinstance
)
3686 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3687 if (vs_prog_data
->uses_drawid
)
3688 emit_draw_index(cmd_buffer
, 0);
3690 /* Emitting draw index or vertex index BOs may result in needing
3691 * additional VF cache flushes.
3693 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3695 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3696 * different views. We need to multiply instanceCount by the view count.
3698 if (!pipeline
->use_primitive_replication
)
3699 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3701 struct gen_mi_builder b
;
3702 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3703 struct gen_mi_value count
=
3704 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3705 counterBufferOffset
));
3707 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3708 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3709 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3711 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3712 gen_mi_imm(firstVertex
));
3713 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3714 gen_mi_imm(instanceCount
));
3715 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3716 gen_mi_imm(firstInstance
));
3717 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3719 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3720 prim
.IndirectParameterEnable
= true;
3721 prim
.VertexAccessType
= SEQUENTIAL
;
3722 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3725 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3726 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3730 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3731 struct anv_address addr
,
3734 struct gen_mi_builder b
;
3735 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3737 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3738 gen_mi_mem32(anv_address_add(addr
, 0)));
3740 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3741 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3742 if (view_count
> 1) {
3743 #if GEN_IS_HASWELL || GEN_GEN >= 8
3744 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3746 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3747 "MI_MATH is not supported on Ivy Bridge");
3750 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3752 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3753 gen_mi_mem32(anv_address_add(addr
, 8)));
3756 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3757 gen_mi_mem32(anv_address_add(addr
, 12)));
3758 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3759 gen_mi_mem32(anv_address_add(addr
, 16)));
3761 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3762 gen_mi_mem32(anv_address_add(addr
, 12)));
3763 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3767 void genX(CmdDrawIndirect
)(
3768 VkCommandBuffer commandBuffer
,
3770 VkDeviceSize offset
,
3774 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3775 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3776 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3777 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3779 if (anv_batch_has_error(&cmd_buffer
->batch
))
3782 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3784 if (cmd_buffer
->state
.conditional_render_enabled
)
3785 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3787 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3788 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3790 if (vs_prog_data
->uses_firstvertex
||
3791 vs_prog_data
->uses_baseinstance
)
3792 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3793 if (vs_prog_data
->uses_drawid
)
3794 emit_draw_index(cmd_buffer
, i
);
3796 /* Emitting draw index or vertex index BOs may result in needing
3797 * additional VF cache flushes.
3799 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3801 load_indirect_parameters(cmd_buffer
, draw
, false);
3803 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3804 prim
.IndirectParameterEnable
= true;
3805 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3806 prim
.VertexAccessType
= SEQUENTIAL
;
3807 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3810 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3816 void genX(CmdDrawIndexedIndirect
)(
3817 VkCommandBuffer commandBuffer
,
3819 VkDeviceSize offset
,
3823 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3824 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3825 struct anv_graphics_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.pipeline
;
3826 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3828 if (anv_batch_has_error(&cmd_buffer
->batch
))
3831 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3833 if (cmd_buffer
->state
.conditional_render_enabled
)
3834 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3836 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3837 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3839 /* TODO: We need to stomp base vertex to 0 somehow */
3840 if (vs_prog_data
->uses_firstvertex
||
3841 vs_prog_data
->uses_baseinstance
)
3842 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3843 if (vs_prog_data
->uses_drawid
)
3844 emit_draw_index(cmd_buffer
, i
);
3846 /* Emitting draw index or vertex index BOs may result in needing
3847 * additional VF cache flushes.
3849 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3851 load_indirect_parameters(cmd_buffer
, draw
, true);
3853 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3854 prim
.IndirectParameterEnable
= true;
3855 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3856 prim
.VertexAccessType
= RANDOM
;
3857 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3860 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3866 static struct gen_mi_value
3867 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3868 struct gen_mi_builder
*b
,
3869 struct anv_address count_address
,
3870 const bool conditional_render_enabled
)
3872 struct gen_mi_value ret
= gen_mi_imm(0);
3874 if (conditional_render_enabled
) {
3875 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3876 ret
= gen_mi_new_gpr(b
);
3877 gen_mi_store(b
, gen_mi_value_ref(b
, ret
), gen_mi_mem32(count_address
));
3880 /* Upload the current draw count from the draw parameters buffer to
3881 * MI_PREDICATE_SRC0.
3883 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3884 gen_mi_mem32(count_address
));
3886 gen_mi_store(b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3893 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3894 struct gen_mi_builder
*b
,
3895 uint32_t draw_index
)
3897 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3898 gen_mi_store(b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3900 if (draw_index
== 0) {
3901 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3902 mip
.LoadOperation
= LOAD_LOADINV
;
3903 mip
.CombineOperation
= COMBINE_SET
;
3904 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3907 /* While draw_index < draw_count the predicate's result will be
3908 * (draw_index == draw_count) ^ TRUE = TRUE
3909 * When draw_index == draw_count the result is
3910 * (TRUE) ^ TRUE = FALSE
3911 * After this all results will be:
3912 * (FALSE) ^ FALSE = FALSE
3914 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3915 mip
.LoadOperation
= LOAD_LOAD
;
3916 mip
.CombineOperation
= COMBINE_XOR
;
3917 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3922 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3924 emit_draw_count_predicate_with_conditional_render(
3925 struct anv_cmd_buffer
*cmd_buffer
,
3926 struct gen_mi_builder
*b
,
3927 uint32_t draw_index
,
3928 struct gen_mi_value max
)
3930 struct gen_mi_value pred
= gen_mi_ult(b
, gen_mi_imm(draw_index
), max
);
3931 pred
= gen_mi_iand(b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3934 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3936 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3937 * so we emit MI_PREDICATE to set it.
3940 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3941 gen_mi_store(b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3943 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3944 mip
.LoadOperation
= LOAD_LOADINV
;
3945 mip
.CombineOperation
= COMBINE_SET
;
3946 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3952 void genX(CmdDrawIndirectCount
)(
3953 VkCommandBuffer commandBuffer
,
3955 VkDeviceSize offset
,
3956 VkBuffer _countBuffer
,
3957 VkDeviceSize countBufferOffset
,
3958 uint32_t maxDrawCount
,
3961 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3962 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3963 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3964 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3965 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
3966 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3968 if (anv_batch_has_error(&cmd_buffer
->batch
))
3971 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3973 struct gen_mi_builder b
;
3974 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3975 struct anv_address count_address
=
3976 anv_address_add(count_buffer
->address
, countBufferOffset
);
3977 struct gen_mi_value max
=
3978 prepare_for_draw_count_predicate(cmd_buffer
, &b
, count_address
,
3979 cmd_state
->conditional_render_enabled
);
3981 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3982 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3984 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3985 if (cmd_state
->conditional_render_enabled
) {
3986 emit_draw_count_predicate_with_conditional_render(
3987 cmd_buffer
, &b
, i
, gen_mi_value_ref(&b
, max
));
3989 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
3992 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
3995 if (vs_prog_data
->uses_firstvertex
||
3996 vs_prog_data
->uses_baseinstance
)
3997 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3998 if (vs_prog_data
->uses_drawid
)
3999 emit_draw_index(cmd_buffer
, i
);
4001 /* Emitting draw index or vertex index BOs may result in needing
4002 * additional VF cache flushes.
4004 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4006 load_indirect_parameters(cmd_buffer
, draw
, false);
4008 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4009 prim
.IndirectParameterEnable
= true;
4010 prim
.PredicateEnable
= true;
4011 prim
.VertexAccessType
= SEQUENTIAL
;
4012 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4015 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
4020 gen_mi_value_unref(&b
, max
);
4023 void genX(CmdDrawIndexedIndirectCount
)(
4024 VkCommandBuffer commandBuffer
,
4026 VkDeviceSize offset
,
4027 VkBuffer _countBuffer
,
4028 VkDeviceSize countBufferOffset
,
4029 uint32_t maxDrawCount
,
4032 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4033 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4034 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
4035 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4036 struct anv_graphics_pipeline
*pipeline
= cmd_state
->gfx
.pipeline
;
4037 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
4039 if (anv_batch_has_error(&cmd_buffer
->batch
))
4042 genX(cmd_buffer_flush_state
)(cmd_buffer
);
4044 struct gen_mi_builder b
;
4045 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4046 struct anv_address count_address
=
4047 anv_address_add(count_buffer
->address
, countBufferOffset
);
4048 struct gen_mi_value max
=
4049 prepare_for_draw_count_predicate(cmd_buffer
, &b
, count_address
,
4050 cmd_state
->conditional_render_enabled
);
4052 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
4053 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
4055 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4056 if (cmd_state
->conditional_render_enabled
) {
4057 emit_draw_count_predicate_with_conditional_render(
4058 cmd_buffer
, &b
, i
, gen_mi_value_ref(&b
, max
));
4060 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4063 emit_draw_count_predicate(cmd_buffer
, &b
, i
);
4066 /* TODO: We need to stomp base vertex to 0 somehow */
4067 if (vs_prog_data
->uses_firstvertex
||
4068 vs_prog_data
->uses_baseinstance
)
4069 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
4070 if (vs_prog_data
->uses_drawid
)
4071 emit_draw_index(cmd_buffer
, i
);
4073 /* Emitting draw index or vertex index BOs may result in needing
4074 * additional VF cache flushes.
4076 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4078 load_indirect_parameters(cmd_buffer
, draw
, true);
4080 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
4081 prim
.IndirectParameterEnable
= true;
4082 prim
.PredicateEnable
= true;
4083 prim
.VertexAccessType
= RANDOM
;
4084 prim
.PrimitiveTopologyType
= pipeline
->topology
;
4087 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
4092 gen_mi_value_unref(&b
, max
);
4095 void genX(CmdBeginTransformFeedbackEXT
)(
4096 VkCommandBuffer commandBuffer
,
4097 uint32_t firstCounterBuffer
,
4098 uint32_t counterBufferCount
,
4099 const VkBuffer
* pCounterBuffers
,
4100 const VkDeviceSize
* pCounterBufferOffsets
)
4102 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4104 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4105 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4106 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4108 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4110 * "Ssoftware must ensure that no HW stream output operations can be in
4111 * process or otherwise pending at the point that the MI_LOAD/STORE
4112 * commands are processed. This will likely require a pipeline flush."
4114 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4115 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4117 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
4118 /* If we have a counter buffer, this is a resume so we need to load the
4119 * value into the streamout offset register. Otherwise, this is a begin
4120 * and we need to reset it to zero.
4122 if (pCounterBuffers
&&
4123 idx
>= firstCounterBuffer
&&
4124 idx
- firstCounterBuffer
< counterBufferCount
&&
4125 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
4126 uint32_t cb_idx
= idx
- firstCounterBuffer
;
4127 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4128 uint64_t offset
= pCounterBufferOffsets
?
4129 pCounterBufferOffsets
[cb_idx
] : 0;
4131 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
4132 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4133 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4137 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
4138 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4144 cmd_buffer
->state
.xfb_enabled
= true;
4145 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4148 void genX(CmdEndTransformFeedbackEXT
)(
4149 VkCommandBuffer commandBuffer
,
4150 uint32_t firstCounterBuffer
,
4151 uint32_t counterBufferCount
,
4152 const VkBuffer
* pCounterBuffers
,
4153 const VkDeviceSize
* pCounterBufferOffsets
)
4155 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4157 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
4158 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4159 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4161 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4163 * "Ssoftware must ensure that no HW stream output operations can be in
4164 * process or otherwise pending at the point that the MI_LOAD/STORE
4165 * commands are processed. This will likely require a pipeline flush."
4167 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4168 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4170 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4171 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4173 /* If we have a counter buffer, this is a resume so we need to load the
4174 * value into the streamout offset register. Otherwise, this is a begin
4175 * and we need to reset it to zero.
4177 if (pCounterBuffers
&&
4178 cb_idx
< counterBufferCount
&&
4179 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4180 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4181 uint64_t offset
= pCounterBufferOffsets
?
4182 pCounterBufferOffsets
[cb_idx
] : 0;
4184 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4185 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4187 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4192 cmd_buffer
->state
.xfb_enabled
= false;
4193 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4197 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4199 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4201 assert(pipeline
->cs
);
4203 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->base
.l3_config
);
4205 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4207 /* Apply any pending pipeline flushes we may have. We want to apply them
4208 * now because, if any of those flushes are for things like push constants,
4209 * the GPU will read the state at weird times.
4211 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4213 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4214 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4216 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4217 * the only bits that are changed are scoreboard related: Scoreboard
4218 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4219 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4222 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4223 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4225 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->base
.batch
);
4227 /* The workgroup size of the pipeline affects our push constant layout
4228 * so flag push constants as dirty if we change the pipeline.
4230 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4233 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4234 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4235 flush_descriptor_sets(cmd_buffer
,
4236 &cmd_buffer
->state
.compute
.base
,
4239 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4240 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4241 .BindingTablePointer
=
4242 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4243 .SamplerStatePointer
=
4244 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4246 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4248 struct anv_state state
=
4249 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4250 pipeline
->interface_descriptor_data
,
4251 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4254 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4255 anv_batch_emit(&cmd_buffer
->batch
,
4256 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4257 mid
.InterfaceDescriptorTotalLength
= size
;
4258 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4262 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4263 struct anv_state push_state
=
4264 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4266 if (push_state
.alloc_size
) {
4267 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4268 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4269 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4273 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4276 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4278 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4284 verify_cmd_parser(const struct anv_device
*device
,
4285 int required_version
,
4286 const char *function
)
4288 if (device
->physical
->cmd_parser_version
< required_version
) {
4289 return vk_errorf(device
, device
->physical
,
4290 VK_ERROR_FEATURE_NOT_PRESENT
,
4291 "cmd parser version %d is required for %s",
4292 required_version
, function
);
4301 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4302 uint32_t baseGroupX
,
4303 uint32_t baseGroupY
,
4304 uint32_t baseGroupZ
)
4306 if (anv_batch_has_error(&cmd_buffer
->batch
))
4309 struct anv_push_constants
*push
=
4310 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4311 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4312 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4313 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4314 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4315 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4316 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4318 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4322 void genX(CmdDispatch
)(
4323 VkCommandBuffer commandBuffer
,
4328 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4331 void genX(CmdDispatchBase
)(
4332 VkCommandBuffer commandBuffer
,
4333 uint32_t baseGroupX
,
4334 uint32_t baseGroupY
,
4335 uint32_t baseGroupZ
,
4336 uint32_t groupCountX
,
4337 uint32_t groupCountY
,
4338 uint32_t groupCountZ
)
4340 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4341 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4342 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4344 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4345 baseGroupY
, baseGroupZ
);
4347 if (anv_batch_has_error(&cmd_buffer
->batch
))
4350 if (prog_data
->uses_num_work_groups
) {
4351 struct anv_state state
=
4352 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4353 uint32_t *sizes
= state
.map
;
4354 sizes
[0] = groupCountX
;
4355 sizes
[1] = groupCountY
;
4356 sizes
[2] = groupCountZ
;
4357 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4358 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4359 .offset
= state
.offset
,
4362 /* The num_workgroups buffer goes in the binding table */
4363 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4366 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4368 if (cmd_buffer
->state
.conditional_render_enabled
)
4369 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4371 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4372 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
4373 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4374 ggw
.ThreadDepthCounterMaximum
= 0;
4375 ggw
.ThreadHeightCounterMaximum
= 0;
4376 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4377 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4378 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4379 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4380 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4381 ggw
.BottomExecutionMask
= 0xffffffff;
4384 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4387 #define GPGPU_DISPATCHDIMX 0x2500
4388 #define GPGPU_DISPATCHDIMY 0x2504
4389 #define GPGPU_DISPATCHDIMZ 0x2508
4391 void genX(CmdDispatchIndirect
)(
4392 VkCommandBuffer commandBuffer
,
4394 VkDeviceSize offset
)
4396 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4397 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4398 struct anv_compute_pipeline
*pipeline
= cmd_buffer
->state
.compute
.pipeline
;
4399 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4400 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4401 struct anv_batch
*batch
= &cmd_buffer
->batch
;
4403 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4406 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4407 * indirect dispatch registers to be written.
4409 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4410 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4414 if (prog_data
->uses_num_work_groups
) {
4415 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4417 /* The num_workgroups buffer goes in the binding table */
4418 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4421 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4423 struct gen_mi_builder b
;
4424 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4426 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4427 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4428 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4430 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4431 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4432 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4435 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4436 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4437 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4438 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4439 mip
.LoadOperation
= LOAD_LOAD
;
4440 mip
.CombineOperation
= COMBINE_SET
;
4441 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4444 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4445 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4446 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4447 mip
.LoadOperation
= LOAD_LOAD
;
4448 mip
.CombineOperation
= COMBINE_OR
;
4449 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4452 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4453 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4454 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4455 mip
.LoadOperation
= LOAD_LOAD
;
4456 mip
.CombineOperation
= COMBINE_OR
;
4457 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4460 /* predicate = !predicate; */
4461 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4462 mip
.LoadOperation
= LOAD_LOADINV
;
4463 mip
.CombineOperation
= COMBINE_OR
;
4464 mip
.CompareOperation
= COMPARE_FALSE
;
4468 if (cmd_buffer
->state
.conditional_render_enabled
) {
4469 /* predicate &= !(conditional_rendering_predicate == 0); */
4470 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4471 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4472 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4473 mip
.LoadOperation
= LOAD_LOADINV
;
4474 mip
.CombineOperation
= COMBINE_AND
;
4475 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4480 #else /* GEN_GEN > 7 */
4481 if (cmd_buffer
->state
.conditional_render_enabled
)
4482 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4485 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4486 ggw
.IndirectParameterEnable
= true;
4487 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4488 cmd_buffer
->state
.conditional_render_enabled
;
4489 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4490 ggw
.ThreadDepthCounterMaximum
= 0;
4491 ggw
.ThreadHeightCounterMaximum
= 0;
4492 ggw
.ThreadWidthCounterMaximum
= anv_cs_threads(pipeline
) - 1;
4493 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4494 ggw
.BottomExecutionMask
= 0xffffffff;
4497 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4501 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4504 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4506 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4509 #if GEN_GEN >= 8 && GEN_GEN < 10
4510 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4512 * Software must clear the COLOR_CALC_STATE Valid field in
4513 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4514 * with Pipeline Select set to GPGPU.
4516 * The internal hardware docs recommend the same workaround for Gen9
4519 if (pipeline
== GPGPU
)
4520 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4524 if (pipeline
== _3D
) {
4525 /* There is a mid-object preemption workaround which requires you to
4526 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4527 * even without preemption, we have issues with geometry flickering when
4528 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4531 const uint32_t subslices
=
4532 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4533 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4534 vfe
.MaximumNumberofThreads
=
4535 devinfo
->max_cs_threads
* subslices
- 1;
4536 vfe
.NumberofURBEntries
= 2;
4537 vfe
.URBEntryAllocationSize
= 2;
4540 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4541 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4542 * pipeline in case we get back-to-back dispatch calls with the same
4543 * pipeline and a PIPELINE_SELECT in between.
4545 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4549 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4550 * PIPELINE_SELECT [DevBWR+]":
4554 * Software must ensure all the write caches are flushed through a
4555 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4556 * command to invalidate read only caches prior to programming
4557 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4559 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4560 pc
.RenderTargetCacheFlushEnable
= true;
4561 pc
.DepthCacheFlushEnable
= true;
4562 pc
.DCFlushEnable
= true;
4563 pc
.PostSyncOperation
= NoWrite
;
4564 pc
.CommandStreamerStallEnable
= true;
4566 pc
.TileCacheFlushEnable
= true;
4568 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4569 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4571 pc
.DepthStallEnable
= true;
4575 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4576 pc
.TextureCacheInvalidationEnable
= true;
4577 pc
.ConstantCacheInvalidationEnable
= true;
4578 pc
.StateCacheInvalidationEnable
= true;
4579 pc
.InstructionCacheInvalidateEnable
= true;
4580 pc
.PostSyncOperation
= NoWrite
;
4582 pc
.TileCacheFlushEnable
= true;
4586 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4590 ps
.PipelineSelection
= pipeline
;
4594 if (devinfo
->is_geminilake
) {
4597 * "This chicken bit works around a hardware issue with barrier logic
4598 * encountered when switching between GPGPU and 3D pipelines. To
4599 * workaround the issue, this mode bit should be set after a pipeline
4603 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4605 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4606 : GLK_BARRIER_MODE_3D_HULL
,
4607 .GLKBarrierModeMask
= 1);
4608 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4612 cmd_buffer
->state
.current_pipeline
= pipeline
;
4616 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4618 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4622 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4624 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4628 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4633 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4635 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4636 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4637 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4638 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4639 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4640 * Depth Flush Bit set, followed by another pipelined depth stall
4641 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4642 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4643 * via a preceding MI_FLUSH)."
4645 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4646 pipe
.DepthStallEnable
= true;
4648 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4649 pipe
.DepthCacheFlushEnable
= true;
4651 pipe
.TileCacheFlushEnable
= true;
4654 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4655 pipe
.DepthStallEnable
= true;
4659 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4661 * "The VF cache needs to be invalidated before binding and then using
4662 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4663 * (at a 64B granularity) since the last invalidation. A VF cache
4664 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4665 * bit in PIPE_CONTROL."
4667 * This is implemented by carefully tracking all vertex and index buffer
4668 * bindings and flushing if the cache ever ends up with a range in the cache
4669 * that would exceed 4 GiB. This is implemented in three parts:
4671 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4672 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4673 * tracking code of the new binding. If this new binding would cause
4674 * the cache to have a too-large range on the next draw call, a pipeline
4675 * stall and VF cache invalidate are added to pending_pipeline_bits.
4677 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4678 * empty whenever we emit a VF invalidate.
4680 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4681 * after every 3DPRIMITIVE and copies the bound range into the dirty
4682 * range for each used buffer. This has to be a separate step because
4683 * we don't always re-bind all buffers and so 1. can't know which
4684 * buffers are actually bound.
4687 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4689 struct anv_address vb_address
,
4692 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4693 !cmd_buffer
->device
->physical
->use_softpin
)
4696 struct anv_vb_cache_range
*bound
, *dirty
;
4697 if (vb_index
== -1) {
4698 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4699 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4701 assert(vb_index
>= 0);
4702 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4703 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4704 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4705 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4714 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4715 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4716 bound
->end
= bound
->start
+ vb_size
;
4717 assert(bound
->end
> bound
->start
); /* No overflow */
4719 /* Align everything to a cache line */
4720 bound
->start
&= ~(64ull - 1ull);
4721 bound
->end
= align_u64(bound
->end
, 64);
4723 /* Compute the dirty range */
4724 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4725 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4727 /* If our range is larger than 32 bits, we have to flush */
4728 assert(bound
->end
- bound
->start
<= (1ull << 32));
4729 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4730 cmd_buffer
->state
.pending_pipe_bits
|=
4731 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4736 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4737 uint32_t access_type
,
4740 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4741 !cmd_buffer
->device
->physical
->use_softpin
)
4744 if (access_type
== RANDOM
) {
4745 /* We have an index buffer */
4746 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4747 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4749 if (bound
->end
> bound
->start
) {
4750 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4751 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4755 uint64_t mask
= vb_used
;
4757 int i
= u_bit_scan64(&mask
);
4759 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4760 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4762 struct anv_vb_cache_range
*bound
, *dirty
;
4763 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4764 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4766 if (bound
->end
> bound
->start
) {
4767 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4768 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4774 * Update the pixel hashing modes that determine the balancing of PS threads
4775 * across subslices and slices.
4777 * \param width Width bound of the rendering area (already scaled down if \p
4778 * scale is greater than 1).
4779 * \param height Height bound of the rendering area (already scaled down if \p
4780 * scale is greater than 1).
4781 * \param scale The number of framebuffer samples that could potentially be
4782 * affected by an individual channel of the PS thread. This is
4783 * typically one for single-sampled rendering, but for operations
4784 * like CCS resolves and fast clears a single PS invocation may
4785 * update a huge number of pixels, in which case a finer
4786 * balancing is desirable in order to maximally utilize the
4787 * bandwidth available. UINT_MAX can be used as shorthand for
4788 * "finest hashing mode available".
4791 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4792 unsigned width
, unsigned height
,
4796 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4797 const unsigned slice_hashing
[] = {
4798 /* Because all Gen9 platforms with more than one slice require
4799 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4800 * block is guaranteed to suffer from substantial imbalance, with one
4801 * subslice receiving twice as much work as the other two in the
4804 * The performance impact of that would be particularly severe when
4805 * three-way hashing is also in use for slice balancing (which is the
4806 * case for all Gen9 GT4 platforms), because one of the slices
4807 * receives one every three 16x16 blocks in either direction, which
4808 * is roughly the periodicity of the underlying subslice imbalance
4809 * pattern ("roughly" because in reality the hardware's
4810 * implementation of three-way hashing doesn't do exact modulo 3
4811 * arithmetic, which somewhat decreases the magnitude of this effect
4812 * in practice). This leads to a systematic subslice imbalance
4813 * within that slice regardless of the size of the primitive. The
4814 * 32x32 hashing mode guarantees that the subslice imbalance within a
4815 * single slice hashing block is minimal, largely eliminating this
4819 /* Finest slice hashing mode available. */
4822 const unsigned subslice_hashing
[] = {
4823 /* 16x16 would provide a slight cache locality benefit especially
4824 * visible in the sampler L1 cache efficiency of low-bandwidth
4825 * non-LLC platforms, but it comes at the cost of greater subslice
4826 * imbalance for primitives of dimensions approximately intermediate
4827 * between 16x4 and 16x16.
4830 /* Finest subslice hashing mode available. */
4833 /* Dimensions of the smallest hashing block of a given hashing mode. If
4834 * the rendering area is smaller than this there can't possibly be any
4835 * benefit from switching to this mode, so we optimize out the
4838 const unsigned min_size
[][2] = {
4842 const unsigned idx
= scale
> 1;
4844 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4845 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4848 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4849 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4850 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4851 .SubsliceHashing
= subslice_hashing
[idx
],
4852 .SubsliceHashingMask
= -1);
4854 cmd_buffer
->state
.pending_pipe_bits
|=
4855 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4856 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4858 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4860 cmd_buffer
->state
.current_hash_scale
= scale
;
4866 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4868 struct anv_device
*device
= cmd_buffer
->device
;
4869 const struct anv_image_view
*iview
=
4870 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4871 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4873 /* FIXME: Width and Height are wrong */
4875 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4877 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4878 device
->isl_dev
.ds
.size
/ 4);
4882 struct isl_depth_stencil_hiz_emit_info info
= { };
4885 info
.view
= &iview
->planes
[0].isl
;
4887 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4888 uint32_t depth_plane
=
4889 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4890 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4892 info
.depth_surf
= &surface
->isl
;
4894 info
.depth_address
=
4895 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4896 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4897 image
->planes
[depth_plane
].address
.bo
,
4898 image
->planes
[depth_plane
].address
.offset
+
4901 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4904 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4905 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4906 if (info
.hiz_usage
!= ISL_AUX_USAGE_NONE
) {
4907 assert(isl_aux_usage_has_hiz(info
.hiz_usage
));
4908 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4911 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4912 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4913 image
->planes
[depth_plane
].address
.bo
,
4914 image
->planes
[depth_plane
].address
.offset
+
4915 image
->planes
[depth_plane
].aux_surface
.offset
);
4917 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4921 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4922 uint32_t stencil_plane
=
4923 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4924 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4926 info
.stencil_surf
= &surface
->isl
;
4928 info
.stencil_address
=
4929 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4930 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4931 image
->planes
[stencil_plane
].address
.bo
,
4932 image
->planes
[stencil_plane
].address
.offset
+
4935 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4938 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4940 if (GEN_GEN
>= 12) {
4941 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4942 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4944 /* GEN:BUG:1408224581
4946 * Workaround: Gen12LP Astep only An additional pipe control with
4947 * post-sync = store dword operation would be required.( w/a is to
4948 * have an additional pipe control after the stencil state whenever
4949 * the surface state bits of this state is changing).
4951 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4952 pc
.PostSyncOperation
= WriteImmediateData
;
4954 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4957 cmd_buffer
->state
.hiz_enabled
= isl_aux_usage_has_hiz(info
.hiz_usage
);
4961 * This ANDs the view mask of the current subpass with the pending clear
4962 * views in the attachment to get the mask of views active in the subpass
4963 * that still need to be cleared.
4965 static inline uint32_t
4966 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4967 const struct anv_attachment_state
*att_state
)
4969 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4973 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4974 const struct anv_attachment_state
*att_state
)
4976 if (!cmd_state
->subpass
->view_mask
)
4979 uint32_t pending_clear_mask
=
4980 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4982 return pending_clear_mask
& 1;
4986 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4989 const uint32_t last_subpass_idx
=
4990 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4991 const struct anv_subpass
*last_subpass
=
4992 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4993 return last_subpass
== cmd_state
->subpass
;
4997 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4998 uint32_t subpass_id
)
5000 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5001 struct anv_render_pass
*pass
= cmd_state
->pass
;
5002 struct anv_subpass
*subpass
= &pass
->subpasses
[subpass_id
];
5003 cmd_state
->subpass
= subpass
;
5005 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
5007 /* Our implementation of VK_KHR_multiview uses instancing to draw the
5008 * different views. If the client asks for instancing, we need to use the
5009 * Instance Data Step Rate to ensure that we repeat the client's
5010 * per-instance data once for each view. Since this bit is in
5011 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
5015 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
5017 /* It is possible to start a render pass with an old pipeline. Because the
5018 * render pass and subpass index are both baked into the pipeline, this is
5019 * highly unlikely. In order to do so, it requires that you have a render
5020 * pass with a single subpass and that you use that render pass twice
5021 * back-to-back and use the same pipeline at the start of the second render
5022 * pass as at the end of the first. In order to avoid unpredictable issues
5023 * with this edge case, we just dirty the pipeline at the start of every
5026 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
5028 /* Accumulate any subpass flushes that need to happen before the subpass */
5029 cmd_buffer
->state
.pending_pipe_bits
|=
5030 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
5032 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5033 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5035 bool is_multiview
= subpass
->view_mask
!= 0;
5037 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5038 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5039 if (a
== VK_ATTACHMENT_UNUSED
)
5042 assert(a
< cmd_state
->pass
->attachment_count
);
5043 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5045 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5046 const struct anv_image
*image
= iview
->image
;
5048 VkImageLayout target_layout
= subpass
->attachments
[i
].layout
;
5049 VkImageLayout target_stencil_layout
=
5050 subpass
->attachments
[i
].stencil_layout
;
5052 uint32_t base_layer
, layer_count
;
5053 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5055 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5056 iview
->planes
[0].isl
.base_level
);
5058 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5059 layer_count
= fb
->layers
;
5062 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5063 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5064 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5065 iview
->planes
[0].isl
.base_level
, 1,
5066 base_layer
, layer_count
,
5067 att_state
->current_layout
, target_layout
);
5068 att_state
->aux_usage
=
5069 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5070 VK_IMAGE_ASPECT_COLOR_BIT
,
5071 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
5075 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5076 transition_depth_buffer(cmd_buffer
, image
,
5077 base_layer
, layer_count
,
5078 att_state
->current_layout
, target_layout
);
5079 att_state
->aux_usage
=
5080 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
5081 VK_IMAGE_ASPECT_DEPTH_BIT
,
5082 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
5086 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5087 transition_stencil_buffer(cmd_buffer
, image
,
5088 iview
->planes
[0].isl
.base_level
, 1,
5089 base_layer
, layer_count
,
5090 att_state
->current_stencil_layout
,
5091 target_stencil_layout
);
5093 att_state
->current_layout
= target_layout
;
5094 att_state
->current_stencil_layout
= target_stencil_layout
;
5096 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
5097 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5099 /* Multi-planar images are not supported as attachments */
5100 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5101 assert(image
->n_planes
== 1);
5103 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
5104 uint32_t clear_layer_count
= fb
->layers
;
5106 if (att_state
->fast_clear
&&
5107 do_first_layer_clear(cmd_state
, att_state
)) {
5108 /* We only support fast-clears on the first layer */
5109 assert(iview
->planes
[0].isl
.base_level
== 0);
5110 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5112 union isl_color_value clear_color
= {};
5113 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5114 if (iview
->image
->samples
== 1) {
5115 anv_image_ccs_op(cmd_buffer
, image
,
5116 iview
->planes
[0].isl
.format
,
5117 iview
->planes
[0].isl
.swizzle
,
5118 VK_IMAGE_ASPECT_COLOR_BIT
,
5119 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5123 anv_image_mcs_op(cmd_buffer
, image
,
5124 iview
->planes
[0].isl
.format
,
5125 iview
->planes
[0].isl
.swizzle
,
5126 VK_IMAGE_ASPECT_COLOR_BIT
,
5127 0, 1, ISL_AUX_OP_FAST_CLEAR
,
5132 clear_layer_count
--;
5134 att_state
->pending_clear_views
&= ~1;
5136 if (isl_color_value_is_zero(clear_color
,
5137 iview
->planes
[0].isl
.format
)) {
5138 /* This image has the auxiliary buffer enabled. We can mark the
5139 * subresource as not needing a resolve because the clear color
5140 * will match what's in every RENDER_SURFACE_STATE object when
5141 * it's being used for sampling.
5143 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5144 VK_IMAGE_ASPECT_COLOR_BIT
,
5145 ANV_FAST_CLEAR_DEFAULT_VALUE
);
5147 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
5148 VK_IMAGE_ASPECT_COLOR_BIT
,
5149 ANV_FAST_CLEAR_ANY
);
5153 /* From the VkFramebufferCreateInfo spec:
5155 * "If the render pass uses multiview, then layers must be one and each
5156 * attachment requires a number of layers that is greater than the
5157 * maximum bit index set in the view mask in the subpasses in which it
5160 * So if multiview is active we ignore the number of layers in the
5161 * framebuffer and instead we honor the view mask from the subpass.
5164 assert(image
->n_planes
== 1);
5165 uint32_t pending_clear_mask
=
5166 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5169 for_each_bit(layer_idx
, pending_clear_mask
) {
5171 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5173 anv_image_clear_color(cmd_buffer
, image
,
5174 VK_IMAGE_ASPECT_COLOR_BIT
,
5175 att_state
->aux_usage
,
5176 iview
->planes
[0].isl
.format
,
5177 iview
->planes
[0].isl
.swizzle
,
5178 iview
->planes
[0].isl
.base_level
,
5181 vk_to_isl_color(att_state
->clear_value
.color
));
5184 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5185 } else if (clear_layer_count
> 0) {
5186 assert(image
->n_planes
== 1);
5187 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5188 att_state
->aux_usage
,
5189 iview
->planes
[0].isl
.format
,
5190 iview
->planes
[0].isl
.swizzle
,
5191 iview
->planes
[0].isl
.base_level
,
5192 base_clear_layer
, clear_layer_count
,
5194 vk_to_isl_color(att_state
->clear_value
.color
));
5196 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5197 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5198 if (att_state
->fast_clear
&& !is_multiview
) {
5199 /* We currently only support HiZ for single-LOD images */
5200 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5201 assert(isl_aux_usage_has_hiz(iview
->image
->planes
[0].aux_usage
));
5202 assert(iview
->planes
[0].isl
.base_level
== 0);
5205 anv_image_hiz_clear(cmd_buffer
, image
,
5206 att_state
->pending_clear_aspects
,
5207 iview
->planes
[0].isl
.base_level
,
5208 iview
->planes
[0].isl
.base_array_layer
,
5209 fb
->layers
, render_area
,
5210 att_state
->clear_value
.depthStencil
.stencil
);
5211 } else if (is_multiview
) {
5212 uint32_t pending_clear_mask
=
5213 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5216 for_each_bit(layer_idx
, pending_clear_mask
) {
5218 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5220 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5221 att_state
->pending_clear_aspects
,
5222 att_state
->aux_usage
,
5223 iview
->planes
[0].isl
.base_level
,
5226 att_state
->clear_value
.depthStencil
.depth
,
5227 att_state
->clear_value
.depthStencil
.stencil
);
5230 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5232 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5233 att_state
->pending_clear_aspects
,
5234 att_state
->aux_usage
,
5235 iview
->planes
[0].isl
.base_level
,
5236 iview
->planes
[0].isl
.base_array_layer
,
5237 fb
->layers
, render_area
,
5238 att_state
->clear_value
.depthStencil
.depth
,
5239 att_state
->clear_value
.depthStencil
.stencil
);
5242 assert(att_state
->pending_clear_aspects
== 0);
5245 /* If multiview is enabled, then we are only done clearing when we no
5246 * longer have pending layers to clear, or when we have processed the
5247 * last subpass that uses this attachment.
5249 if (!is_multiview
||
5250 att_state
->pending_clear_views
== 0 ||
5251 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5252 att_state
->pending_clear_aspects
= 0;
5255 att_state
->pending_load_aspects
= 0;
5258 /* We've transitioned all our images possibly fast clearing them. Now we
5259 * can fill out the surface states that we will use as render targets
5260 * during actual subpass rendering.
5262 VkResult result
= genX(cmd_buffer_alloc_att_surf_states
)(cmd_buffer
,
5264 if (result
!= VK_SUCCESS
)
5267 isl_null_fill_state(&cmd_buffer
->device
->isl_dev
,
5268 cmd_state
->null_surface_state
.map
,
5269 isl_extent3d(fb
->width
, fb
->height
, fb
->layers
));
5271 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5272 const uint32_t att
= subpass
->attachments
[i
].attachment
;
5273 if (att
== VK_ATTACHMENT_UNUSED
)
5276 assert(att
< cmd_state
->pass
->attachment_count
);
5277 struct anv_render_pass_attachment
*pass_att
= &pass
->attachments
[att
];
5278 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
5279 struct anv_image_view
*iview
= att_state
->image_view
;
5281 if (!vk_format_is_color(pass_att
->format
))
5284 const VkImageUsageFlagBits att_usage
= subpass
->attachments
[i
].usage
;
5285 assert(util_bitcount(att_usage
) == 1);
5287 struct anv_surface_state
*surface_state
;
5288 isl_surf_usage_flags_t isl_surf_usage
;
5289 enum isl_aux_usage isl_aux_usage
;
5290 if (att_usage
== VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5291 surface_state
= &att_state
->color
;
5292 isl_surf_usage
= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
5293 isl_aux_usage
= att_state
->aux_usage
;
5294 } else if (att_usage
== VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
) {
5295 surface_state
= &att_state
->input
;
5296 isl_surf_usage
= ISL_SURF_USAGE_TEXTURE_BIT
;
5298 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
5299 VK_IMAGE_ASPECT_COLOR_BIT
,
5300 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
,
5301 att_state
->current_layout
);
5306 /* We had better have a surface state when we get here */
5307 assert(surface_state
->state
.map
);
5309 union isl_color_value clear_color
= { .u32
= { 0, } };
5310 if (pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
&&
5311 att_state
->fast_clear
)
5312 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
5314 anv_image_fill_surface_state(cmd_buffer
->device
,
5316 VK_IMAGE_ASPECT_COLOR_BIT
,
5317 &iview
->planes
[0].isl
,
5325 add_surface_state_relocs(cmd_buffer
, *surface_state
);
5328 pass_att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
&&
5329 iview
->image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5330 iview
->planes
[0].isl
.base_level
== 0 &&
5331 iview
->planes
[0].isl
.base_array_layer
== 0) {
5332 genX(copy_fast_clear_dwords
)(cmd_buffer
, surface_state
->state
,
5334 VK_IMAGE_ASPECT_COLOR_BIT
,
5335 false /* copy to ss */);
5340 /* The PIPE_CONTROL command description says:
5342 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5343 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5344 * Target Cache Flush by enabling this bit. When render target flush
5345 * is set due to new association of BTI, PS Scoreboard Stall bit must
5346 * be set in this packet."
5348 cmd_buffer
->state
.pending_pipe_bits
|=
5349 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5350 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5354 /* GEN:BUG:14010455700
5356 * ISL will change some CHICKEN registers depending on the depth surface
5357 * format, along with emitting the depth and stencil packets. In that case,
5358 * we want to do a depth flush and stall, so the pipeline is not using these
5359 * settings while we change the registers.
5361 cmd_buffer
->state
.pending_pipe_bits
|=
5362 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5363 ANV_PIPE_DEPTH_STALL_BIT
|
5364 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5365 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5368 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5371 static enum blorp_filter
5372 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5375 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5376 return BLORP_FILTER_SAMPLE_0
;
5377 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5378 return BLORP_FILTER_AVERAGE
;
5379 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5380 return BLORP_FILTER_MIN_SAMPLE
;
5381 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5382 return BLORP_FILTER_MAX_SAMPLE
;
5384 return BLORP_FILTER_NONE
;
5389 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5391 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5392 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5393 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5394 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5396 /* We are done with the previous subpass and all rendering directly to that
5397 * subpass is now complete. Zero out all the surface states so we don't
5398 * accidentally use them between now and the next subpass.
5400 for (uint32_t i
= 0; i
< cmd_state
->pass
->attachment_count
; ++i
) {
5401 memset(&cmd_state
->attachments
[i
].color
, 0,
5402 sizeof(cmd_state
->attachments
[i
].color
));
5403 memset(&cmd_state
->attachments
[i
].input
, 0,
5404 sizeof(cmd_state
->attachments
[i
].input
));
5406 cmd_state
->null_surface_state
= ANV_STATE_NULL
;
5407 cmd_state
->attachment_states
= ANV_STATE_NULL
;
5409 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5410 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5411 if (a
== VK_ATTACHMENT_UNUSED
)
5414 assert(a
< cmd_state
->pass
->attachment_count
);
5415 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5416 struct anv_image_view
*iview
= att_state
->image_view
;
5418 assert(util_bitcount(subpass
->attachments
[i
].usage
) == 1);
5419 if (subpass
->attachments
[i
].usage
==
5420 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5421 /* We assume that if we're ending a subpass, we did do some rendering
5422 * so we may end up with compressed data.
5424 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5425 VK_IMAGE_ASPECT_COLOR_BIT
,
5426 att_state
->aux_usage
,
5427 iview
->planes
[0].isl
.base_level
,
5428 iview
->planes
[0].isl
.base_array_layer
,
5430 } else if (subpass
->attachments
[i
].usage
==
5431 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5432 /* We may be writing depth or stencil so we need to mark the surface.
5433 * Unfortunately, there's no way to know at this point whether the
5434 * depth or stencil tests used will actually write to the surface.
5436 * Even though stencil may be plane 1, it always shares a base_level
5439 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5440 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5441 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5442 VK_IMAGE_ASPECT_DEPTH_BIT
,
5443 att_state
->aux_usage
,
5444 ds_view
->base_level
,
5445 ds_view
->base_array_layer
,
5448 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5449 /* Even though stencil may be plane 1, it always shares a
5450 * base_level with depth.
5452 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5453 VK_IMAGE_ASPECT_STENCIL_BIT
,
5455 ds_view
->base_level
,
5456 ds_view
->base_array_layer
,
5462 if (subpass
->has_color_resolve
) {
5463 /* We are about to do some MSAA resolves. We need to flush so that the
5464 * result of writes to the MSAA color attachments show up in the sampler
5465 * when we blit to the single-sampled resolve target.
5467 cmd_buffer
->state
.pending_pipe_bits
|=
5468 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5469 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5471 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5472 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5473 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5475 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5478 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5479 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5481 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5482 /* From the Vulkan 1.0 spec:
5484 * If the first use of an attachment in a render pass is as a
5485 * resolve attachment, then the loadOp is effectively ignored
5486 * as the resolve is guaranteed to overwrite all pixels in the
5489 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5492 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5493 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5495 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5497 enum isl_aux_usage src_aux_usage
=
5498 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5499 enum isl_aux_usage dst_aux_usage
=
5500 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5502 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5503 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5505 anv_image_msaa_resolve(cmd_buffer
,
5506 src_iview
->image
, src_aux_usage
,
5507 src_iview
->planes
[0].isl
.base_level
,
5508 src_iview
->planes
[0].isl
.base_array_layer
,
5509 dst_iview
->image
, dst_aux_usage
,
5510 dst_iview
->planes
[0].isl
.base_level
,
5511 dst_iview
->planes
[0].isl
.base_array_layer
,
5512 VK_IMAGE_ASPECT_COLOR_BIT
,
5513 render_area
.offset
.x
, render_area
.offset
.y
,
5514 render_area
.offset
.x
, render_area
.offset
.y
,
5515 render_area
.extent
.width
,
5516 render_area
.extent
.height
,
5517 fb
->layers
, BLORP_FILTER_NONE
);
5521 if (subpass
->ds_resolve_attachment
) {
5522 /* We are about to do some MSAA resolves. We need to flush so that the
5523 * result of writes to the MSAA depth attachments show up in the sampler
5524 * when we blit to the single-sampled resolve target.
5526 cmd_buffer
->state
.pending_pipe_bits
|=
5527 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5528 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5530 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5531 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5533 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5534 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5536 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5537 /* From the Vulkan 1.0 spec:
5539 * If the first use of an attachment in a render pass is as a
5540 * resolve attachment, then the loadOp is effectively ignored
5541 * as the resolve is guaranteed to overwrite all pixels in the
5544 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5547 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5548 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5550 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5552 struct anv_attachment_state
*src_state
=
5553 &cmd_state
->attachments
[src_att
];
5554 struct anv_attachment_state
*dst_state
=
5555 &cmd_state
->attachments
[dst_att
];
5557 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5558 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5560 /* MSAA resolves sample from the source attachment. Transition the
5561 * depth attachment first to get rid of any HiZ that we may not be
5564 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5565 src_iview
->planes
[0].isl
.base_array_layer
,
5567 src_state
->current_layout
,
5568 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5569 src_state
->aux_usage
=
5570 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5571 VK_IMAGE_ASPECT_DEPTH_BIT
,
5572 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5573 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5574 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5576 /* MSAA resolves write to the resolve attachment as if it were any
5577 * other transfer op. Transition the resolve attachment accordingly.
5579 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5581 /* If our render area is the entire size of the image, we're going to
5582 * blow it all away so we can claim the initial layout is UNDEFINED
5583 * and we'll get a HiZ ambiguate instead of a resolve.
5585 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5586 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5587 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5588 render_area
.extent
.height
== dst_iview
->extent
.height
)
5589 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5591 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5592 dst_iview
->planes
[0].isl
.base_array_layer
,
5595 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5596 dst_state
->aux_usage
=
5597 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5598 VK_IMAGE_ASPECT_DEPTH_BIT
,
5599 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5600 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5601 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5603 enum blorp_filter filter
=
5604 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5606 anv_image_msaa_resolve(cmd_buffer
,
5607 src_iview
->image
, src_state
->aux_usage
,
5608 src_iview
->planes
[0].isl
.base_level
,
5609 src_iview
->planes
[0].isl
.base_array_layer
,
5610 dst_iview
->image
, dst_state
->aux_usage
,
5611 dst_iview
->planes
[0].isl
.base_level
,
5612 dst_iview
->planes
[0].isl
.base_array_layer
,
5613 VK_IMAGE_ASPECT_DEPTH_BIT
,
5614 render_area
.offset
.x
, render_area
.offset
.y
,
5615 render_area
.offset
.x
, render_area
.offset
.y
,
5616 render_area
.extent
.width
,
5617 render_area
.extent
.height
,
5618 fb
->layers
, filter
);
5621 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5622 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5624 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5625 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5627 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5628 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5630 enum blorp_filter filter
=
5631 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5633 anv_image_msaa_resolve(cmd_buffer
,
5634 src_iview
->image
, src_aux_usage
,
5635 src_iview
->planes
[0].isl
.base_level
,
5636 src_iview
->planes
[0].isl
.base_array_layer
,
5637 dst_iview
->image
, dst_aux_usage
,
5638 dst_iview
->planes
[0].isl
.base_level
,
5639 dst_iview
->planes
[0].isl
.base_array_layer
,
5640 VK_IMAGE_ASPECT_STENCIL_BIT
,
5641 render_area
.offset
.x
, render_area
.offset
.y
,
5642 render_area
.offset
.x
, render_area
.offset
.y
,
5643 render_area
.extent
.width
,
5644 render_area
.extent
.height
,
5645 fb
->layers
, filter
);
5650 /* On gen7, we have to store a texturable version of the stencil buffer in
5651 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5652 * forth at strategic points. Stencil writes are only allowed in following
5655 * - VK_IMAGE_LAYOUT_GENERAL
5656 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5657 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5658 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5659 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5661 * For general, we have no nice opportunity to transition so we do the copy
5662 * to the shadow unconditionally at the end of the subpass. For transfer
5663 * destinations, we can update it as part of the transfer op. For the other
5664 * layouts, we delay the copy until a transition into some other layout.
5666 if (subpass
->depth_stencil_attachment
) {
5667 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5668 assert(a
!= VK_ATTACHMENT_UNUSED
);
5670 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5671 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5672 const struct anv_image
*image
= iview
->image
;
5674 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5675 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5676 VK_IMAGE_ASPECT_STENCIL_BIT
);
5678 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5679 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5680 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5681 anv_image_copy_to_shadow(cmd_buffer
, image
,
5682 VK_IMAGE_ASPECT_STENCIL_BIT
,
5683 iview
->planes
[plane
].isl
.base_level
, 1,
5684 iview
->planes
[plane
].isl
.base_array_layer
,
5689 #endif /* GEN_GEN == 7 */
5691 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5692 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5693 if (a
== VK_ATTACHMENT_UNUSED
)
5696 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5699 assert(a
< cmd_state
->pass
->attachment_count
);
5700 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5701 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5702 const struct anv_image
*image
= iview
->image
;
5704 /* Transition the image into the final layout for this render pass */
5705 VkImageLayout target_layout
=
5706 cmd_state
->pass
->attachments
[a
].final_layout
;
5707 VkImageLayout target_stencil_layout
=
5708 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5710 uint32_t base_layer
, layer_count
;
5711 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5713 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5714 iview
->planes
[0].isl
.base_level
);
5716 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5717 layer_count
= fb
->layers
;
5720 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5721 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5722 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5723 iview
->planes
[0].isl
.base_level
, 1,
5724 base_layer
, layer_count
,
5725 att_state
->current_layout
, target_layout
);
5728 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5729 transition_depth_buffer(cmd_buffer
, image
,
5730 base_layer
, layer_count
,
5731 att_state
->current_layout
, target_layout
);
5734 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5735 transition_stencil_buffer(cmd_buffer
, image
,
5736 iview
->planes
[0].isl
.base_level
, 1,
5737 base_layer
, layer_count
,
5738 att_state
->current_stencil_layout
,
5739 target_stencil_layout
);
5743 /* Accumulate any subpass flushes that need to happen after the subpass.
5744 * Yes, they do get accumulated twice in the NextSubpass case but since
5745 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5746 * ORing the bits in twice so it's harmless.
5748 cmd_buffer
->state
.pending_pipe_bits
|=
5749 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5752 void genX(CmdBeginRenderPass
)(
5753 VkCommandBuffer commandBuffer
,
5754 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5755 VkSubpassContents contents
)
5757 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5758 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5759 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5762 cmd_buffer
->state
.framebuffer
= framebuffer
;
5763 cmd_buffer
->state
.pass
= pass
;
5764 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5766 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
,
5769 if (result
!= VK_SUCCESS
) {
5770 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5774 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5776 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5779 void genX(CmdBeginRenderPass2
)(
5780 VkCommandBuffer commandBuffer
,
5781 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5782 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5784 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5785 pSubpassBeginInfo
->contents
);
5788 void genX(CmdNextSubpass
)(
5789 VkCommandBuffer commandBuffer
,
5790 VkSubpassContents contents
)
5792 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5794 if (anv_batch_has_error(&cmd_buffer
->batch
))
5797 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5799 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5800 cmd_buffer_end_subpass(cmd_buffer
);
5801 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5804 void genX(CmdNextSubpass2
)(
5805 VkCommandBuffer commandBuffer
,
5806 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5807 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5809 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5812 void genX(CmdEndRenderPass
)(
5813 VkCommandBuffer commandBuffer
)
5815 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5817 if (anv_batch_has_error(&cmd_buffer
->batch
))
5820 cmd_buffer_end_subpass(cmd_buffer
);
5822 cmd_buffer
->state
.hiz_enabled
= false;
5825 anv_dump_add_attachments(cmd_buffer
);
5828 /* Remove references to render pass specific state. This enables us to
5829 * detect whether or not we're in a renderpass.
5831 cmd_buffer
->state
.framebuffer
= NULL
;
5832 cmd_buffer
->state
.pass
= NULL
;
5833 cmd_buffer
->state
.subpass
= NULL
;
5836 void genX(CmdEndRenderPass2
)(
5837 VkCommandBuffer commandBuffer
,
5838 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5840 genX(CmdEndRenderPass
)(commandBuffer
);
5844 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5846 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5847 struct gen_mi_builder b
;
5848 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5850 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5851 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5852 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5854 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5855 mip
.LoadOperation
= LOAD_LOADINV
;
5856 mip
.CombineOperation
= COMBINE_SET
;
5857 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5862 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5863 void genX(CmdBeginConditionalRenderingEXT
)(
5864 VkCommandBuffer commandBuffer
,
5865 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5867 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5868 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5869 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5870 struct anv_address value_address
=
5871 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5873 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5874 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5876 cmd_state
->conditional_render_enabled
= true;
5878 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5880 struct gen_mi_builder b
;
5881 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5883 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5885 * If the value of the predicate in buffer memory changes
5886 * while conditional rendering is active, the rendering commands
5887 * may be discarded in an implementation-dependent way.
5888 * Some implementations may latch the value of the predicate
5889 * upon beginning conditional rendering while others
5890 * may read it before every rendering command.
5892 * So it's perfectly fine to read a value from the buffer once.
5894 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5896 /* Precompute predicate result, it is necessary to support secondary
5897 * command buffers since it is unknown if conditional rendering is
5898 * inverted when populating them.
5900 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5901 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5902 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5905 void genX(CmdEndConditionalRenderingEXT
)(
5906 VkCommandBuffer commandBuffer
)
5908 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5909 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5911 cmd_state
->conditional_render_enabled
= false;
5915 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5916 * command streamer for later execution.
5918 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5919 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5920 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5921 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5922 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5923 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5924 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5925 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5926 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5927 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5928 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5929 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5930 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5931 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5932 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5934 void genX(CmdSetEvent
)(
5935 VkCommandBuffer commandBuffer
,
5937 VkPipelineStageFlags stageMask
)
5939 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5940 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5942 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5943 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5945 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5946 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5947 pc
.StallAtPixelScoreboard
= true;
5948 pc
.CommandStreamerStallEnable
= true;
5951 pc
.DestinationAddressType
= DAT_PPGTT
,
5952 pc
.PostSyncOperation
= WriteImmediateData
,
5953 pc
.Address
= (struct anv_address
) {
5954 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5957 pc
.ImmediateData
= VK_EVENT_SET
;
5961 void genX(CmdResetEvent
)(
5962 VkCommandBuffer commandBuffer
,
5964 VkPipelineStageFlags stageMask
)
5966 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5967 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5969 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5970 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5972 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5973 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5974 pc
.StallAtPixelScoreboard
= true;
5975 pc
.CommandStreamerStallEnable
= true;
5978 pc
.DestinationAddressType
= DAT_PPGTT
;
5979 pc
.PostSyncOperation
= WriteImmediateData
;
5980 pc
.Address
= (struct anv_address
) {
5981 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5984 pc
.ImmediateData
= VK_EVENT_RESET
;
5988 void genX(CmdWaitEvents
)(
5989 VkCommandBuffer commandBuffer
,
5990 uint32_t eventCount
,
5991 const VkEvent
* pEvents
,
5992 VkPipelineStageFlags srcStageMask
,
5993 VkPipelineStageFlags destStageMask
,
5994 uint32_t memoryBarrierCount
,
5995 const VkMemoryBarrier
* pMemoryBarriers
,
5996 uint32_t bufferMemoryBarrierCount
,
5997 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5998 uint32_t imageMemoryBarrierCount
,
5999 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
6002 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6004 for (uint32_t i
= 0; i
< eventCount
; i
++) {
6005 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
6007 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
6008 sem
.WaitMode
= PollingMode
,
6009 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
6010 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
6011 sem
.SemaphoreAddress
= (struct anv_address
) {
6012 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
6018 anv_finishme("Implement events on gen7");
6021 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
6022 false, /* byRegion */
6023 memoryBarrierCount
, pMemoryBarriers
,
6024 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
6025 imageMemoryBarrierCount
, pImageMemoryBarriers
);
6028 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
6029 VkCommandBuffer commandBuffer
,
6030 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
6032 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
6034 switch (pOverrideInfo
->type
) {
6035 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
6039 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
6040 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6041 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6042 ._3DRenderingInstructionDisableMask
= true,
6043 .MediaInstructionDisableMask
= true);
6044 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
6046 anv_pack_struct(&dw
, GENX(INSTPM
),
6047 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
6048 .MediaInstructionDisable
= pOverrideInfo
->enable
,
6049 ._3DRenderingInstructionDisableMask
= true,
6050 .MediaInstructionDisableMask
= true);
6051 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
6056 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
6057 if (pOverrideInfo
->enable
) {
6058 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
6059 cmd_buffer
->state
.pending_pipe_bits
|=
6060 ANV_PIPE_FLUSH_BITS
|
6061 ANV_PIPE_INVALIDATE_BITS
;
6062 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
6067 unreachable("Invalid override");
6073 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
6074 VkCommandBuffer commandBuffer
,
6075 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
6077 /* TODO: Waiting on the register to write, might depend on generation. */