2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
44 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
46 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
47 lri
.RegisterOffset
= reg
;
53 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
55 struct anv_device
*device
= cmd_buffer
->device
;
56 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
58 /* If we are emitting a new state base address we probably need to re-emit
61 cmd_buffer
->state
.descriptors_dirty
|= ~0;
63 /* Emit a render target cache flush.
65 * This isn't documented anywhere in the PRM. However, it seems to be
66 * necessary prior to changing the surface state base adress. Without
67 * this, we get GPU hangs when using multi-level command buffers which
68 * clear depth, reset state base address, and then go render stuff.
70 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
71 pc
.DCFlushEnable
= true;
72 pc
.RenderTargetCacheFlushEnable
= true;
73 pc
.CommandStreamerStallEnable
= true;
75 pc
.TileCacheFlushEnable
= true;
79 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
80 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
81 sba
.GeneralStateMOCS
= mocs
;
82 sba
.GeneralStateBaseAddressModifyEnable
= true;
84 sba
.StatelessDataPortAccessMOCS
= mocs
;
86 sba
.SurfaceStateBaseAddress
=
87 anv_cmd_buffer_surface_base_address(cmd_buffer
);
88 sba
.SurfaceStateMOCS
= mocs
;
89 sba
.SurfaceStateBaseAddressModifyEnable
= true;
91 sba
.DynamicStateBaseAddress
=
92 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
93 sba
.DynamicStateMOCS
= mocs
;
94 sba
.DynamicStateBaseAddressModifyEnable
= true;
96 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
97 sba
.IndirectObjectMOCS
= mocs
;
98 sba
.IndirectObjectBaseAddressModifyEnable
= true;
100 sba
.InstructionBaseAddress
=
101 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
102 sba
.InstructionMOCS
= mocs
;
103 sba
.InstructionBaseAddressModifyEnable
= true;
106 /* Broadwell requires that we specify a buffer size for a bunch of
107 * these fields. However, since we will be growing the BO's live, we
108 * just set them all to the maximum.
110 sba
.GeneralStateBufferSize
= 0xfffff;
111 sba
.GeneralStateBufferSizeModifyEnable
= true;
112 sba
.DynamicStateBufferSize
= 0xfffff;
113 sba
.DynamicStateBufferSizeModifyEnable
= true;
114 sba
.IndirectObjectBufferSize
= 0xfffff;
115 sba
.IndirectObjectBufferSizeModifyEnable
= true;
116 sba
.InstructionBufferSize
= 0xfffff;
117 sba
.InstructionBuffersizeModifyEnable
= true;
119 /* On gen7, we have upper bounds instead. According to the docs,
120 * setting an upper bound of zero means that no bounds checking is
121 * performed so, in theory, we should be able to leave them zero.
122 * However, border color is broken and the GPU bounds-checks anyway.
123 * To avoid this and other potential problems, we may as well set it
126 sba
.GeneralStateAccessUpperBound
=
127 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
128 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
129 sba
.DynamicStateAccessUpperBound
=
130 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
131 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
132 sba
.InstructionAccessUpperBound
=
133 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
134 sba
.InstructionAccessUpperBoundModifyEnable
= true;
137 if (cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
) {
138 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
139 .bo
= device
->surface_state_pool
.block_pool
.bo
,
142 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
144 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
145 sba
.BindlessSurfaceStateSize
= 0;
147 sba
.BindlessSurfaceStateMOCS
= mocs
;
148 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
151 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
152 sba
.BindlessSamplerStateMOCS
= mocs
;
153 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
154 sba
.BindlessSamplerStateBufferSize
= 0;
158 /* After re-setting the surface state base address, we have to do some
159 * cache flusing so that the sampler engine will pick up the new
160 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
161 * Shared Function > 3D Sampler > State > State Caching (page 96):
163 * Coherency with system memory in the state cache, like the texture
164 * cache is handled partially by software. It is expected that the
165 * command stream or shader will issue Cache Flush operation or
166 * Cache_Flush sampler message to ensure that the L1 cache remains
167 * coherent with system memory.
171 * Whenever the value of the Dynamic_State_Base_Addr,
172 * Surface_State_Base_Addr are altered, the L1 state cache must be
173 * invalidated to ensure the new surface or sampler state is fetched
174 * from system memory.
176 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
177 * which, according the PIPE_CONTROL instruction documentation in the
180 * Setting this bit is independent of any other bit in this packet.
181 * This bit controls the invalidation of the L1 and L2 state caches
182 * at the top of the pipe i.e. at the parsing time.
184 * Unfortunately, experimentation seems to indicate that state cache
185 * invalidation through a PIPE_CONTROL does nothing whatsoever in
186 * regards to surface state and binding tables. In stead, it seems that
187 * invalidating the texture cache is what is actually needed.
189 * XXX: As far as we have been able to determine through
190 * experimentation, shows that flush the texture cache appears to be
191 * sufficient. The theory here is that all of the sampling/rendering
192 * units cache the binding table in the texture cache. However, we have
193 * yet to be able to actually confirm this.
195 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
196 pc
.TextureCacheInvalidationEnable
= true;
197 pc
.ConstantCacheInvalidationEnable
= true;
198 pc
.StateCacheInvalidationEnable
= true;
203 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
204 struct anv_state state
, struct anv_address addr
)
206 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
209 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
210 state
.offset
+ isl_dev
->ss
.addr_offset
,
211 addr
.bo
, addr
.offset
, NULL
);
212 if (result
!= VK_SUCCESS
)
213 anv_batch_set_error(&cmd_buffer
->batch
, result
);
217 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
218 struct anv_surface_state state
)
220 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
222 assert(!anv_address_is_null(state
.address
));
223 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
225 if (!anv_address_is_null(state
.aux_address
)) {
227 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
228 &cmd_buffer
->pool
->alloc
,
229 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
230 state
.aux_address
.bo
,
231 state
.aux_address
.offset
,
233 if (result
!= VK_SUCCESS
)
234 anv_batch_set_error(&cmd_buffer
->batch
, result
);
237 if (!anv_address_is_null(state
.clear_address
)) {
239 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
240 &cmd_buffer
->pool
->alloc
,
242 isl_dev
->ss
.clear_color_state_offset
,
243 state
.clear_address
.bo
,
244 state
.clear_address
.offset
,
246 if (result
!= VK_SUCCESS
)
247 anv_batch_set_error(&cmd_buffer
->batch
, result
);
252 color_attachment_compute_aux_usage(struct anv_device
* device
,
253 struct anv_cmd_state
* cmd_state
,
254 uint32_t att
, VkRect2D render_area
,
255 union isl_color_value
*fast_clear_color
)
257 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
258 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
260 assert(iview
->n_planes
== 1);
262 if (iview
->planes
[0].isl
.base_array_layer
>=
263 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
264 iview
->planes
[0].isl
.base_level
)) {
265 /* There is no aux buffer which corresponds to the level and layer(s)
268 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
269 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
270 att_state
->fast_clear
= false;
274 att_state
->aux_usage
=
275 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
276 VK_IMAGE_ASPECT_COLOR_BIT
,
277 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
279 /* If we don't have aux, then we should have returned early in the layer
280 * check above. If we got here, we must have something.
282 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
284 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
285 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
286 att_state
->input_aux_usage
= att_state
->aux_usage
;
288 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
290 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
291 * setting is only allowed if Surface Format supported for Fast
292 * Clear. In addition, if the surface is bound to the sampling
293 * engine, Surface Format must be supported for Render Target
294 * Compression for surfaces bound to the sampling engine."
296 * In other words, we can only sample from a fast-cleared image if it
297 * also supports color compression.
299 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
300 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
301 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
303 /* While fast-clear resolves and partial resolves are fairly cheap in the
304 * case where you render to most of the pixels, full resolves are not
305 * because they potentially involve reading and writing the entire
306 * framebuffer. If we can't texture with CCS_E, we should leave it off and
307 * limit ourselves to fast clears.
309 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
310 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
311 anv_perf_warn(device
->instance
, iview
->image
,
312 "Not temporarily enabling CCS_E.");
315 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
319 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
320 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
322 union isl_color_value clear_color
= {};
323 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
325 att_state
->clear_color_is_zero_one
=
326 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
327 att_state
->clear_color_is_zero
=
328 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
330 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
331 /* Start by getting the fast clear type. We use the first subpass
332 * layout here because we don't want to fast-clear if the first subpass
333 * to use the attachment can't handle fast-clears.
335 enum anv_fast_clear_type fast_clear_type
=
336 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
337 VK_IMAGE_ASPECT_COLOR_BIT
,
338 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
339 switch (fast_clear_type
) {
340 case ANV_FAST_CLEAR_NONE
:
341 att_state
->fast_clear
= false;
343 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
344 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
346 case ANV_FAST_CLEAR_ANY
:
347 att_state
->fast_clear
= true;
351 /* Potentially, we could do partial fast-clears but doing so has crazy
352 * alignment restrictions. It's easier to just restrict to full size
353 * fast clears for now.
355 if (render_area
.offset
.x
!= 0 ||
356 render_area
.offset
.y
!= 0 ||
357 render_area
.extent
.width
!= iview
->extent
.width
||
358 render_area
.extent
.height
!= iview
->extent
.height
)
359 att_state
->fast_clear
= false;
361 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
362 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
363 att_state
->fast_clear
= false;
365 /* We only allow fast clears to the first slice of an image (level 0,
366 * layer 0) and only for the entire slice. This guarantees us that, at
367 * any given time, there is only one clear color on any given image at
368 * any given time. At the time of our testing (Jan 17, 2018), there
369 * were no known applications which would benefit from fast-clearing
370 * more than just the first slice.
372 if (att_state
->fast_clear
&&
373 (iview
->planes
[0].isl
.base_level
> 0 ||
374 iview
->planes
[0].isl
.base_array_layer
> 0)) {
375 anv_perf_warn(device
->instance
, iview
->image
,
376 "Rendering with multi-lod or multi-layer framebuffer "
377 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
378 "baseArrayLayer > 0. Not fast clearing.");
379 att_state
->fast_clear
= false;
380 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
381 anv_perf_warn(device
->instance
, iview
->image
,
382 "Rendering to a multi-layer framebuffer with "
383 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
386 if (att_state
->fast_clear
)
387 *fast_clear_color
= clear_color
;
389 att_state
->fast_clear
= false;
394 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
395 struct anv_cmd_state
*cmd_state
,
396 uint32_t att
, VkRect2D render_area
)
398 struct anv_render_pass_attachment
*pass_att
=
399 &cmd_state
->pass
->attachments
[att
];
400 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
401 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
403 /* These will be initialized after the first subpass transition. */
404 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
405 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
408 /* We don't do any HiZ or depth fast-clears on gen7 yet */
409 att_state
->fast_clear
= false;
413 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
414 /* If we're just clearing stencil, we can always HiZ clear */
415 att_state
->fast_clear
= true;
419 /* Default to false for now */
420 att_state
->fast_clear
= false;
422 /* We must have depth in order to have HiZ */
423 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
426 const enum isl_aux_usage first_subpass_aux_usage
=
427 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
428 VK_IMAGE_ASPECT_DEPTH_BIT
,
429 pass_att
->first_subpass_layout
);
430 if (!blorp_can_hiz_clear_depth(&device
->info
,
431 &iview
->image
->planes
[0].surface
.isl
,
432 first_subpass_aux_usage
,
433 iview
->planes
[0].isl
.base_level
,
434 iview
->planes
[0].isl
.base_array_layer
,
435 render_area
.offset
.x
,
436 render_area
.offset
.y
,
437 render_area
.offset
.x
+
438 render_area
.extent
.width
,
439 render_area
.offset
.y
+
440 render_area
.extent
.height
))
443 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
446 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
447 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
448 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
449 * only supports returning 0.0f. Gens prior to gen8 do not support this
455 /* If we got here, then we can fast clear */
456 att_state
->fast_clear
= true;
460 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
462 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
465 /* We only allocate input attachment states for color surfaces. Compression
466 * is not yet enabled for depth textures and stencil doesn't allow
467 * compression so we can just use the texture surface state from the view.
469 return vk_format_is_color(att
->format
);
472 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
473 * the initial layout is undefined, the HiZ buffer and depth buffer will
474 * represent the same data at the end of this operation.
477 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
478 const struct anv_image
*image
,
479 VkImageLayout initial_layout
,
480 VkImageLayout final_layout
)
482 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
483 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
484 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
485 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
486 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
487 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
489 enum isl_aux_op hiz_op
;
490 if (hiz_enabled
&& !enable_hiz
) {
491 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
492 } else if (!hiz_enabled
&& enable_hiz
) {
493 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
495 assert(hiz_enabled
== enable_hiz
);
496 /* If the same buffer will be used, no resolves are necessary. */
497 hiz_op
= ISL_AUX_OP_NONE
;
500 if (hiz_op
!= ISL_AUX_OP_NONE
)
501 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
506 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
508 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
509 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
510 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
513 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
514 * the initial layout is undefined, the HiZ buffer and depth buffer will
515 * represent the same data at the end of this operation.
518 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
519 const struct anv_image
*image
,
520 uint32_t base_level
, uint32_t level_count
,
521 uint32_t base_layer
, uint32_t layer_count
,
522 VkImageLayout initial_layout
,
523 VkImageLayout final_layout
)
526 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
527 VK_IMAGE_ASPECT_STENCIL_BIT
);
529 /* On gen7, we have to store a texturable version of the stencil buffer in
530 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
531 * forth at strategic points. Stencil writes are only allowed in following
534 * - VK_IMAGE_LAYOUT_GENERAL
535 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
536 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
537 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
538 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
540 * For general, we have no nice opportunity to transition so we do the copy
541 * to the shadow unconditionally at the end of the subpass. For transfer
542 * destinations, we can update it as part of the transfer op. For the other
543 * layouts, we delay the copy until a transition into some other layout.
545 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
546 vk_image_layout_stencil_write_optimal(initial_layout
) &&
547 !vk_image_layout_stencil_write_optimal(final_layout
)) {
548 anv_image_copy_to_shadow(cmd_buffer
, image
,
549 VK_IMAGE_ASPECT_STENCIL_BIT
,
550 base_level
, level_count
,
551 base_layer
, layer_count
);
553 #endif /* GEN_GEN == 7 */
556 #define MI_PREDICATE_SRC0 0x2400
557 #define MI_PREDICATE_SRC1 0x2408
558 #define MI_PREDICATE_RESULT 0x2418
561 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
562 const struct anv_image
*image
,
563 VkImageAspectFlagBits aspect
,
565 uint32_t base_layer
, uint32_t layer_count
,
568 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
570 /* We only have compression tracking for CCS_E */
571 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
574 for (uint32_t a
= 0; a
< layer_count
; a
++) {
575 uint32_t layer
= base_layer
+ a
;
576 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
577 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
580 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
586 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
587 const struct anv_image
*image
,
588 VkImageAspectFlagBits aspect
,
589 enum anv_fast_clear_type fast_clear
)
591 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
592 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
594 sdi
.ImmediateData
= fast_clear
;
597 /* Whenever we have fast-clear, we consider that slice to be compressed.
598 * This makes building predicates much easier.
600 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
601 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
604 /* This is only really practical on haswell and above because it requires
605 * MI math in order to get it correct.
607 #if GEN_GEN >= 8 || GEN_IS_HASWELL
609 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
610 const struct anv_image
*image
,
611 VkImageAspectFlagBits aspect
,
612 uint32_t level
, uint32_t array_layer
,
613 enum isl_aux_op resolve_op
,
614 enum anv_fast_clear_type fast_clear_supported
)
616 struct gen_mi_builder b
;
617 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
619 const struct gen_mi_value fast_clear_type
=
620 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
623 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
624 /* In this case, we're doing a full resolve which means we want the
625 * resolve to happen if any compression (including fast-clears) is
628 * In order to simplify the logic a bit, we make the assumption that,
629 * if the first slice has been fast-cleared, it is also marked as
630 * compressed. See also set_image_fast_clear_state.
632 const struct gen_mi_value compression_state
=
633 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
635 level
, array_layer
));
636 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
638 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
640 if (level
== 0 && array_layer
== 0) {
641 /* If the predicate is true, we want to write 0 to the fast clear type
642 * and, if it's false, leave it alone. We can do this by writing
644 * clear_type = clear_type & ~predicate;
646 struct gen_mi_value new_fast_clear_type
=
647 gen_mi_iand(&b
, fast_clear_type
,
648 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
649 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
651 } else if (level
== 0 && array_layer
== 0) {
652 /* In this case, we are doing a partial resolve to get rid of fast-clear
653 * colors. We don't care about the compression state but we do care
654 * about how much fast clear is allowed by the final layout.
656 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
657 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
659 /* We need to compute (fast_clear_supported < image->fast_clear) */
660 struct gen_mi_value pred
=
661 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
662 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
663 gen_mi_value_ref(&b
, pred
));
665 /* If the predicate is true, we want to write 0 to the fast clear type
666 * and, if it's false, leave it alone. We can do this by writing
668 * clear_type = clear_type & ~predicate;
670 struct gen_mi_value new_fast_clear_type
=
671 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
672 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
674 /* In this case, we're trying to do a partial resolve on a slice that
675 * doesn't have clear color. There's nothing to do.
677 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
681 /* Set src1 to 0 and use a != condition */
682 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
684 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
685 mip
.LoadOperation
= LOAD_LOADINV
;
686 mip
.CombineOperation
= COMBINE_SET
;
687 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
690 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
694 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
695 const struct anv_image
*image
,
696 VkImageAspectFlagBits aspect
,
697 uint32_t level
, uint32_t array_layer
,
698 enum isl_aux_op resolve_op
,
699 enum anv_fast_clear_type fast_clear_supported
)
701 struct gen_mi_builder b
;
702 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
704 struct gen_mi_value fast_clear_type_mem
=
705 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
708 /* This only works for partial resolves and only when the clear color is
709 * all or nothing. On the upside, this emits less command streamer code
710 * and works on Ivybridge and Bay Trail.
712 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
713 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
715 /* We don't support fast clears on anything other than the first slice. */
716 if (level
> 0 || array_layer
> 0)
719 /* On gen8, we don't have a concept of default clear colors because we
720 * can't sample from CCS surfaces. It's enough to just load the fast clear
721 * state into the predicate register.
723 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
724 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
725 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
727 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
728 mip
.LoadOperation
= LOAD_LOADINV
;
729 mip
.CombineOperation
= COMBINE_SET
;
730 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
733 #endif /* GEN_GEN <= 8 */
736 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
737 const struct anv_image
*image
,
738 enum isl_format format
,
739 VkImageAspectFlagBits aspect
,
740 uint32_t level
, uint32_t array_layer
,
741 enum isl_aux_op resolve_op
,
742 enum anv_fast_clear_type fast_clear_supported
)
744 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
747 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
748 aspect
, level
, array_layer
,
749 resolve_op
, fast_clear_supported
);
750 #else /* GEN_GEN <= 8 */
751 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
752 aspect
, level
, array_layer
,
753 resolve_op
, fast_clear_supported
);
756 /* CCS_D only supports full resolves and BLORP will assert on us if we try
757 * to do a partial resolve on a CCS_D surface.
759 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
760 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
761 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
763 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
764 array_layer
, 1, resolve_op
, NULL
, true);
768 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
769 const struct anv_image
*image
,
770 enum isl_format format
,
771 VkImageAspectFlagBits aspect
,
772 uint32_t array_layer
,
773 enum isl_aux_op resolve_op
,
774 enum anv_fast_clear_type fast_clear_supported
)
776 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
777 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 #if GEN_GEN >= 8 || GEN_IS_HASWELL
780 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
781 aspect
, 0, array_layer
,
782 resolve_op
, fast_clear_supported
);
784 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
785 array_layer
, 1, resolve_op
, NULL
, true);
787 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
792 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
793 const struct anv_image
*image
,
794 VkImageAspectFlagBits aspect
,
795 enum isl_aux_usage aux_usage
,
798 uint32_t layer_count
)
800 /* The aspect must be exactly one of the image aspects. */
801 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
803 /* The only compression types with more than just fast-clears are MCS,
804 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
805 * track the current fast-clear and compression state. This leaves us
806 * with just MCS and CCS_E.
808 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
809 aux_usage
!= ISL_AUX_USAGE_MCS
)
812 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
813 level
, base_layer
, layer_count
, true);
817 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
818 const struct anv_image
*image
,
819 VkImageAspectFlagBits aspect
)
821 assert(cmd_buffer
&& image
);
822 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
824 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
825 ANV_FAST_CLEAR_NONE
);
827 /* Initialize the struct fields that are accessed for fast-clears so that
828 * the HW restrictions on the field values are satisfied.
830 struct anv_address addr
=
831 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
834 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
835 const unsigned num_dwords
= GEN_GEN
>= 10 ?
836 isl_dev
->ss
.clear_color_state_size
/ 4 :
837 isl_dev
->ss
.clear_value_size
/ 4;
838 for (unsigned i
= 0; i
< num_dwords
; i
++) {
839 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
841 sdi
.Address
.offset
+= i
* 4;
842 sdi
.ImmediateData
= 0;
846 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
848 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
849 /* Pre-SKL, the dword containing the clear values also contains
850 * other fields, so we need to initialize those fields to match the
851 * values that would be in a color attachment.
853 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
854 ISL_CHANNEL_SELECT_GREEN
<< 22 |
855 ISL_CHANNEL_SELECT_BLUE
<< 19 |
856 ISL_CHANNEL_SELECT_ALPHA
<< 16;
857 } else if (GEN_GEN
== 7) {
858 /* On IVB, the dword containing the clear values also contains
859 * other fields that must be zero or can be zero.
861 sdi
.ImmediateData
= 0;
867 /* Copy the fast-clear value dword(s) between a surface state object and an
868 * image's fast clear state buffer.
871 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
872 struct anv_state surface_state
,
873 const struct anv_image
*image
,
874 VkImageAspectFlagBits aspect
,
875 bool copy_from_surface_state
)
877 assert(cmd_buffer
&& image
);
878 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
880 struct anv_address ss_clear_addr
= {
881 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
882 .offset
= surface_state
.offset
+
883 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
885 const struct anv_address entry_addr
=
886 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
887 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
890 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
891 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
892 * in-flight when they are issued even if the memory touched is not
893 * currently active for rendering. The weird bit is that it is not the
894 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
895 * rendering hangs such that the next stalling command after the
896 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
898 * It is unclear exactly why this hang occurs. Both MI commands come with
899 * warnings about the 3D pipeline but that doesn't seem to fully explain
900 * it. My (Jason's) best theory is that it has something to do with the
901 * fact that we're using a GPU state register as our temporary and that
902 * something with reading/writing it is causing problems.
904 * In order to work around this issue, we emit a PIPE_CONTROL with the
905 * command streamer stall bit set.
907 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
908 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
911 struct gen_mi_builder b
;
912 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
914 if (copy_from_surface_state
) {
915 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
917 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
919 /* Updating a surface state object may require that the state cache be
920 * invalidated. From the SKL PRM, Shared Functions -> State -> State
923 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
924 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
925 * modified [...], the L1 state cache must be invalidated to ensure
926 * the new surface or sampler state is fetched from system memory.
928 * In testing, SKL doesn't actually seem to need this, but HSW does.
930 cmd_buffer
->state
.pending_pipe_bits
|=
931 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
936 * @brief Transitions a color buffer from one layout to another.
938 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
941 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
942 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
943 * this represents the maximum layers to transition at each
944 * specified miplevel.
947 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
948 const struct anv_image
*image
,
949 VkImageAspectFlagBits aspect
,
950 const uint32_t base_level
, uint32_t level_count
,
951 uint32_t base_layer
, uint32_t layer_count
,
952 VkImageLayout initial_layout
,
953 VkImageLayout final_layout
)
955 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
956 /* Validate the inputs. */
958 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
959 /* These values aren't supported for simplicity's sake. */
960 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
961 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
962 /* Ensure the subresource range is valid. */
963 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
964 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
965 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
966 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
967 assert(last_level_num
<= image
->levels
);
968 /* The spec disallows these final layouts. */
969 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
970 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
972 /* No work is necessary if the layout stays the same or if this subresource
973 * range lacks auxiliary data.
975 if (initial_layout
== final_layout
)
978 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
980 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
981 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
982 /* This surface is a linear compressed image with a tiled shadow surface
983 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
984 * we need to ensure the shadow copy is up-to-date.
986 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
987 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
988 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
989 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
991 anv_image_copy_to_shadow(cmd_buffer
, image
,
992 VK_IMAGE_ASPECT_COLOR_BIT
,
993 base_level
, level_count
,
994 base_layer
, layer_count
);
997 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1000 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
1002 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1003 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1004 /* A subresource in the undefined layout may have been aliased and
1005 * populated with any arrangement of bits. Therefore, we must initialize
1006 * the related aux buffer and clear buffer entry with desirable values.
1007 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1008 * images with VK_IMAGE_TILING_OPTIMAL.
1010 * Initialize the relevant clear buffer entries.
1012 if (base_level
== 0 && base_layer
== 0)
1013 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1015 /* Initialize the aux buffers to enable correct rendering. In order to
1016 * ensure that things such as storage images work correctly, aux buffers
1017 * need to be initialized to valid data.
1019 * Having an aux buffer with invalid data is a problem for two reasons:
1021 * 1) Having an invalid value in the buffer can confuse the hardware.
1022 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1023 * invalid and leads to the hardware doing strange things. It
1024 * doesn't hang as far as we can tell but rendering corruption can
1027 * 2) If this transition is into the GENERAL layout and we then use the
1028 * image as a storage image, then we must have the aux buffer in the
1029 * pass-through state so that, if we then go to texture from the
1030 * image, we get the results of our storage image writes and not the
1031 * fast clear color or other random data.
1033 * For CCS both of the problems above are real demonstrable issues. In
1034 * that case, the only thing we can do is to perform an ambiguate to
1035 * transition the aux surface into the pass-through state.
1037 * For MCS, (2) is never an issue because we don't support multisampled
1038 * storage images. In theory, issue (1) is a problem with MCS but we've
1039 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1040 * theory, be interpreted as something but we don't know that all bit
1041 * patterns are actually valid. For 2x and 8x, you could easily end up
1042 * with the MCS referring to an invalid plane because not all bits of
1043 * the MCS value are actually used. Even though we've never seen issues
1044 * in the wild, it's best to play it safe and initialize the MCS. We
1045 * can use a fast-clear for MCS because we only ever touch from render
1046 * and texture (no image load store).
1048 if (image
->samples
== 1) {
1049 for (uint32_t l
= 0; l
< level_count
; l
++) {
1050 const uint32_t level
= base_level
+ l
;
1052 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1053 if (base_layer
>= aux_layers
)
1054 break; /* We will only get fewer layers as level increases */
1055 uint32_t level_layer_count
=
1056 MIN2(layer_count
, aux_layers
- base_layer
);
1058 anv_image_ccs_op(cmd_buffer
, image
,
1059 image
->planes
[plane
].surface
.isl
.format
,
1060 aspect
, level
, base_layer
, level_layer_count
,
1061 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1063 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1064 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1065 level
, base_layer
, level_layer_count
,
1070 if (image
->samples
== 4 || image
->samples
== 16) {
1071 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1072 "Doing a potentially unnecessary fast-clear to "
1073 "define an MCS buffer.");
1076 assert(base_level
== 0 && level_count
== 1);
1077 anv_image_mcs_op(cmd_buffer
, image
,
1078 image
->planes
[plane
].surface
.isl
.format
,
1079 aspect
, base_layer
, layer_count
,
1080 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1085 const enum isl_aux_usage initial_aux_usage
=
1086 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1087 const enum isl_aux_usage final_aux_usage
=
1088 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1090 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1091 * We can handle transitions between CCS_D/E to and from NONE. What we
1092 * don't yet handle is switching between CCS_E and CCS_D within a given
1093 * image. Doing so in a performant way requires more detailed aux state
1094 * tracking such as what is done in i965. For now, just assume that we
1095 * only have one type of compression.
1097 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1098 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1099 initial_aux_usage
== final_aux_usage
);
1101 /* If initial aux usage is NONE, there is nothing to resolve */
1102 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1105 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1107 /* If the initial layout supports more fast clear than the final layout
1108 * then we need at least a partial resolve.
1110 const enum anv_fast_clear_type initial_fast_clear
=
1111 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1112 const enum anv_fast_clear_type final_fast_clear
=
1113 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1114 if (final_fast_clear
< initial_fast_clear
)
1115 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1117 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1118 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1119 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1121 if (resolve_op
== ISL_AUX_OP_NONE
)
1124 /* Perform a resolve to synchronize data between the main and aux buffer.
1125 * Before we begin, we must satisfy the cache flushing requirement specified
1126 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1128 * Any transition from any value in {Clear, Render, Resolve} to a
1129 * different value in {Clear, Render, Resolve} requires end of pipe
1132 * We perform a flush of the write cache before and after the clear and
1133 * resolve operations to meet this requirement.
1135 * Unlike other drawing, fast clear operations are not properly
1136 * synchronized. The first PIPE_CONTROL here likely ensures that the
1137 * contents of the previous render or clear hit the render target before we
1138 * resolve and the second likely ensures that the resolve is complete before
1139 * we do any more rendering or clearing.
1141 cmd_buffer
->state
.pending_pipe_bits
|=
1142 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1144 for (uint32_t l
= 0; l
< level_count
; l
++) {
1145 uint32_t level
= base_level
+ l
;
1147 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1148 if (base_layer
>= aux_layers
)
1149 break; /* We will only get fewer layers as level increases */
1150 uint32_t level_layer_count
=
1151 MIN2(layer_count
, aux_layers
- base_layer
);
1153 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1154 uint32_t array_layer
= base_layer
+ a
;
1155 if (image
->samples
== 1) {
1156 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1157 image
->planes
[plane
].surface
.isl
.format
,
1158 aspect
, level
, array_layer
, resolve_op
,
1161 /* We only support fast-clear on the first layer so partial
1162 * resolves should not be used on other layers as they will use
1163 * the clear color stored in memory that is only valid for layer0.
1165 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1169 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1170 image
->planes
[plane
].surface
.isl
.format
,
1171 aspect
, array_layer
, resolve_op
,
1177 cmd_buffer
->state
.pending_pipe_bits
|=
1178 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1182 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1185 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1186 struct anv_render_pass
*pass
,
1187 const VkRenderPassBeginInfo
*begin
)
1189 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1190 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1191 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1193 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1195 if (pass
->attachment_count
> 0) {
1196 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1197 pass
->attachment_count
*
1198 sizeof(state
->attachments
[0]),
1199 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1200 if (state
->attachments
== NULL
) {
1201 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1202 return anv_batch_set_error(&cmd_buffer
->batch
,
1203 VK_ERROR_OUT_OF_HOST_MEMORY
);
1206 state
->attachments
= NULL
;
1209 /* Reserve one for the NULL state. */
1210 unsigned num_states
= 1;
1211 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1212 if (vk_format_is_color(pass
->attachments
[i
].format
))
1215 if (need_input_attachment_state(&pass
->attachments
[i
]))
1219 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1220 state
->render_pass_states
=
1221 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1222 num_states
* ss_stride
, isl_dev
->ss
.align
);
1224 struct anv_state next_state
= state
->render_pass_states
;
1225 next_state
.alloc_size
= isl_dev
->ss
.size
;
1227 state
->null_surface_state
= next_state
;
1228 next_state
.offset
+= ss_stride
;
1229 next_state
.map
+= ss_stride
;
1231 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1232 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1234 if (begin
&& !begin_attachment
)
1235 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1237 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1238 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1239 state
->attachments
[i
].color
.state
= next_state
;
1240 next_state
.offset
+= ss_stride
;
1241 next_state
.map
+= ss_stride
;
1244 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1245 state
->attachments
[i
].input
.state
= next_state
;
1246 next_state
.offset
+= ss_stride
;
1247 next_state
.map
+= ss_stride
;
1250 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1251 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1252 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1253 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1254 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1255 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1258 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1259 state
->render_pass_states
.alloc_size
);
1262 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1263 isl_extent3d(framebuffer
->width
,
1264 framebuffer
->height
,
1265 framebuffer
->layers
));
1267 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1268 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1269 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1270 VkImageAspectFlags clear_aspects
= 0;
1271 VkImageAspectFlags load_aspects
= 0;
1273 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1274 /* color attachment */
1275 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1276 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1277 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1278 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1281 /* depthstencil attachment */
1282 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1283 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1284 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1285 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1286 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1289 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1290 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1291 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1292 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1293 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1298 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1299 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1300 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1301 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1303 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1305 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1306 anv_assert(iview
->vk_format
== att
->format
);
1308 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1309 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1311 union isl_color_value clear_color
= { .u32
= { 0, } };
1312 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1313 anv_assert(iview
->n_planes
== 1);
1314 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1315 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1316 state
, i
, begin
->renderArea
,
1319 anv_image_fill_surface_state(cmd_buffer
->device
,
1321 VK_IMAGE_ASPECT_COLOR_BIT
,
1322 &iview
->planes
[0].isl
,
1323 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1324 state
->attachments
[i
].aux_usage
,
1327 &state
->attachments
[i
].color
,
1330 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1332 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1337 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1338 anv_image_fill_surface_state(cmd_buffer
->device
,
1340 VK_IMAGE_ASPECT_COLOR_BIT
,
1341 &iview
->planes
[0].isl
,
1342 ISL_SURF_USAGE_TEXTURE_BIT
,
1343 state
->attachments
[i
].input_aux_usage
,
1346 &state
->attachments
[i
].input
,
1349 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1358 genX(BeginCommandBuffer
)(
1359 VkCommandBuffer commandBuffer
,
1360 const VkCommandBufferBeginInfo
* pBeginInfo
)
1362 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1364 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1365 * command buffer's state. Otherwise, we must *reset* its state. In both
1366 * cases we reset it.
1368 * From the Vulkan 1.0 spec:
1370 * If a command buffer is in the executable state and the command buffer
1371 * was allocated from a command pool with the
1372 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1373 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1374 * as if vkResetCommandBuffer had been called with
1375 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1376 * the command buffer in the recording state.
1378 anv_cmd_buffer_reset(cmd_buffer
);
1380 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1382 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1383 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1385 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1387 /* We sometimes store vertex data in the dynamic state buffer for blorp
1388 * operations and our dynamic state stream may re-use data from previous
1389 * command buffers. In order to prevent stale cache data, we flush the VF
1390 * cache. We could do this on every blorp call but that's not really
1391 * needed as all of the data will get written by the CPU prior to the GPU
1392 * executing anything. The chances are fairly high that they will use
1393 * blorp at least once per primary command buffer so it shouldn't be
1396 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1397 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1399 /* We send an "Indirect State Pointers Disable" packet at
1400 * EndCommandBuffer, so all push contant packets are ignored during a
1401 * context restore. Documentation says after that command, we need to
1402 * emit push constants again before any rendering operation. So we
1403 * flag them dirty here to make sure they get emitted.
1405 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1407 VkResult result
= VK_SUCCESS
;
1408 if (cmd_buffer
->usage_flags
&
1409 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1410 assert(pBeginInfo
->pInheritanceInfo
);
1411 cmd_buffer
->state
.pass
=
1412 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1413 cmd_buffer
->state
.subpass
=
1414 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1416 /* This is optional in the inheritance info. */
1417 cmd_buffer
->state
.framebuffer
=
1418 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1420 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1421 cmd_buffer
->state
.pass
, NULL
);
1423 /* Record that HiZ is enabled if we can. */
1424 if (cmd_buffer
->state
.framebuffer
) {
1425 const struct anv_image_view
* const iview
=
1426 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1429 VkImageLayout layout
=
1430 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1432 enum isl_aux_usage aux_usage
=
1433 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1434 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1436 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1440 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1443 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1444 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1445 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1446 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1448 /* If secondary buffer supports conditional rendering
1449 * we should emit commands as if conditional rendering is enabled.
1451 cmd_buffer
->state
.conditional_render_enabled
=
1452 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1459 /* From the PRM, Volume 2a:
1461 * "Indirect State Pointers Disable
1463 * At the completion of the post-sync operation associated with this pipe
1464 * control packet, the indirect state pointers in the hardware are
1465 * considered invalid; the indirect pointers are not saved in the context.
1466 * If any new indirect state commands are executed in the command stream
1467 * while the pipe control is pending, the new indirect state commands are
1470 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1471 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1472 * commands are only considered as Indirect State Pointers. Once ISP is
1473 * issued in a context, SW must initialize by programming push constant
1474 * commands for all the shaders (at least to zero length) before attempting
1475 * any rendering operation for the same context."
1477 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1478 * even though they point to a BO that has been already unreferenced at
1479 * the end of the previous batch buffer. This has been fine so far since
1480 * we are protected by these scratch page (every address not covered by
1481 * a BO should be pointing to the scratch page). But on CNL, it is
1482 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1485 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1486 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1487 * context restore, so the mentioned hang doesn't happen. However,
1488 * software must program push constant commands for all stages prior to
1489 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1491 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1492 * constants have been loaded into the EUs prior to disable the push constants
1493 * so that it doesn't hang a previous 3DPRIMITIVE.
1496 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1498 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1499 pc
.StallAtPixelScoreboard
= true;
1500 pc
.CommandStreamerStallEnable
= true;
1502 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1503 pc
.IndirectStatePointersDisable
= true;
1504 pc
.CommandStreamerStallEnable
= true;
1509 genX(EndCommandBuffer
)(
1510 VkCommandBuffer commandBuffer
)
1512 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1514 if (anv_batch_has_error(&cmd_buffer
->batch
))
1515 return cmd_buffer
->batch
.status
;
1517 /* We want every command buffer to start with the PMA fix in a known state,
1518 * so we disable it at the end of the command buffer.
1520 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1522 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1524 emit_isp_disable(cmd_buffer
);
1526 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1532 genX(CmdExecuteCommands
)(
1533 VkCommandBuffer commandBuffer
,
1534 uint32_t commandBufferCount
,
1535 const VkCommandBuffer
* pCmdBuffers
)
1537 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1539 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1541 if (anv_batch_has_error(&primary
->batch
))
1544 /* The secondary command buffers will assume that the PMA fix is disabled
1545 * when they begin executing. Make sure this is true.
1547 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1549 /* The secondary command buffer doesn't know which textures etc. have been
1550 * flushed prior to their execution. Apply those flushes now.
1552 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1554 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1555 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1557 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1558 assert(!anv_batch_has_error(&secondary
->batch
));
1560 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1561 if (secondary
->state
.conditional_render_enabled
) {
1562 if (!primary
->state
.conditional_render_enabled
) {
1563 /* Secondary buffer is constructed as if it will be executed
1564 * with conditional rendering, we should satisfy this dependency
1565 * regardless of conditional rendering being enabled in primary.
1567 struct gen_mi_builder b
;
1568 gen_mi_builder_init(&b
, &primary
->batch
);
1569 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1570 gen_mi_imm(UINT64_MAX
));
1575 if (secondary
->usage_flags
&
1576 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1577 /* If we're continuing a render pass from the primary, we need to
1578 * copy the surface states for the current subpass into the storage
1579 * we allocated for them in BeginCommandBuffer.
1581 struct anv_bo
*ss_bo
=
1582 primary
->device
->surface_state_pool
.block_pool
.bo
;
1583 struct anv_state src_state
= primary
->state
.render_pass_states
;
1584 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1585 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1587 genX(cmd_buffer_so_memcpy
)(primary
,
1588 (struct anv_address
) {
1590 .offset
= dst_state
.offset
,
1592 (struct anv_address
) {
1594 .offset
= src_state
.offset
,
1596 src_state
.alloc_size
);
1599 anv_cmd_buffer_add_secondary(primary
, secondary
);
1602 /* The secondary may have selected a different pipeline (3D or compute) and
1603 * may have changed the current L3$ configuration. Reset our tracking
1604 * variables to invalid values to ensure that we re-emit these in the case
1605 * where we do any draws or compute dispatches from the primary after the
1606 * secondary has returned.
1608 primary
->state
.current_pipeline
= UINT32_MAX
;
1609 primary
->state
.current_l3_config
= NULL
;
1610 primary
->state
.current_hash_scale
= 0;
1612 /* Each of the secondary command buffers will use its own state base
1613 * address. We need to re-emit state base address for the primary after
1614 * all of the secondaries are done.
1616 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1619 genX(cmd_buffer_emit_state_base_address
)(primary
);
1622 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1623 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1624 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1627 * Program the hardware to use the specified L3 configuration.
1630 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1631 const struct gen_l3_config
*cfg
)
1634 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1637 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1638 intel_logd("L3 config transition: ");
1639 gen_dump_l3_config(cfg
, stderr
);
1642 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1644 /* According to the hardware docs, the L3 partitioning can only be changed
1645 * while the pipeline is completely drained and the caches are flushed,
1646 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1648 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1649 pc
.DCFlushEnable
= true;
1650 pc
.PostSyncOperation
= NoWrite
;
1651 pc
.CommandStreamerStallEnable
= true;
1654 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1655 * invalidation of the relevant caches. Note that because RO invalidation
1656 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1657 * command is processed by the CS) we cannot combine it with the previous
1658 * stalling flush as the hardware documentation suggests, because that
1659 * would cause the CS to stall on previous rendering *after* RO
1660 * invalidation and wouldn't prevent the RO caches from being polluted by
1661 * concurrent rendering before the stall completes. This intentionally
1662 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1663 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1664 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1665 * already guarantee that there is no concurrent GPGPU kernel execution
1666 * (see SKL HSD 2132585).
1668 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1669 pc
.TextureCacheInvalidationEnable
= true;
1670 pc
.ConstantCacheInvalidationEnable
= true;
1671 pc
.InstructionCacheInvalidateEnable
= true;
1672 pc
.StateCacheInvalidationEnable
= true;
1673 pc
.PostSyncOperation
= NoWrite
;
1676 /* Now send a third stalling flush to make sure that invalidation is
1677 * complete when the L3 configuration registers are modified.
1679 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1680 pc
.DCFlushEnable
= true;
1681 pc
.PostSyncOperation
= NoWrite
;
1682 pc
.CommandStreamerStallEnable
= true;
1687 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1690 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1691 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1693 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1694 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1698 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1700 .SLMEnable
= has_slm
,
1703 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1704 * in L3CNTLREG register. The default setting of the bit is not the
1705 * desirable behavior.
1707 .ErrorDetectionBehaviorControl
= true,
1708 .UseFullWays
= true,
1710 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1711 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1712 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1713 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1715 /* Set up the L3 partitioning. */
1716 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1720 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1721 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1722 cfg
->n
[GEN_L3P_ALL
];
1723 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1724 cfg
->n
[GEN_L3P_ALL
];
1725 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1726 cfg
->n
[GEN_L3P_ALL
];
1728 assert(!cfg
->n
[GEN_L3P_ALL
]);
1730 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1731 * the matching space on the remaining banks has to be allocated to a
1732 * client (URB for all validated configurations) set to the
1733 * lower-bandwidth 2-bank address hashing mode.
1735 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1736 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1737 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1739 /* Minimum number of ways that can be allocated to the URB. */
1740 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1741 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1743 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1744 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1745 .ConvertDC_UC
= !has_dc
,
1746 .ConvertIS_UC
= !has_is
,
1747 .ConvertC_UC
= !has_c
,
1748 .ConvertT_UC
= !has_t
);
1750 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1751 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1752 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1754 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1755 .SLMEnable
= has_slm
,
1756 .URBLowBandwidth
= urb_low_bw
,
1757 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1759 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1761 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1762 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1764 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1765 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1766 .ISLowBandwidth
= 0,
1767 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1769 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1770 .TLowBandwidth
= 0);
1772 /* Set up the L3 partitioning. */
1773 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1774 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1775 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1778 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1779 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1780 * them disabled to avoid crashing the system hard.
1782 uint32_t scratch1
, chicken3
;
1783 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1784 .L3AtomicDisable
= !has_dc
);
1785 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1786 .L3AtomicDisableMask
= true,
1787 .L3AtomicDisable
= !has_dc
);
1788 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1789 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1795 cmd_buffer
->state
.current_l3_config
= cfg
;
1799 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1801 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1803 if (cmd_buffer
->device
->instance
->physicalDevice
.always_flush_cache
)
1804 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
1806 /* Flushes are pipelined while invalidations are handled immediately.
1807 * Therefore, if we're flushing anything then we need to schedule a stall
1808 * before any invalidations can happen.
1810 if (bits
& ANV_PIPE_FLUSH_BITS
)
1811 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1813 /* If we're going to do an invalidate and we have a pending CS stall that
1814 * has yet to be resolved, we do the CS stall now.
1816 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1817 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1818 bits
|= ANV_PIPE_CS_STALL_BIT
;
1819 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1822 if (GEN_GEN
>= 12 &&
1823 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
1824 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
1825 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
1828 * Unified Cache (Tile Cache Disabled):
1830 * When the Color and Depth (Z) streams are enabled to be cached in
1831 * the DC space of L2, Software must use "Render Target Cache Flush
1832 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
1833 * Flush" for getting the color and depth (Z) write data to be
1834 * globally observable. In this mode of operation it is not required
1835 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
1837 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1840 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1841 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1843 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
1845 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1846 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1847 pipe
.RenderTargetCacheFlushEnable
=
1848 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1850 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1851 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1852 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1855 * According to the Broadwell documentation, any PIPE_CONTROL with the
1856 * "Command Streamer Stall" bit set must also have another bit set,
1857 * with five different options:
1859 * - Render Target Cache Flush
1860 * - Depth Cache Flush
1861 * - Stall at Pixel Scoreboard
1862 * - Post-Sync Operation
1866 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1867 * mesa and it seems to work fine. The choice is fairly arbitrary.
1869 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1870 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1871 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1872 pipe
.StallAtPixelScoreboard
= true;
1875 /* If a render target flush was emitted, then we can toggle off the bit
1876 * saying that render target writes are ongoing.
1878 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1879 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1881 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1884 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1885 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1887 * "If the VF Cache Invalidation Enable is set to a 1 in a
1888 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1889 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1890 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1893 * This appears to hang Broadwell, so we restrict it to just gen9.
1895 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1896 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1898 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1899 pipe
.StateCacheInvalidationEnable
=
1900 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1901 pipe
.ConstantCacheInvalidationEnable
=
1902 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1903 pipe
.VFCacheInvalidationEnable
=
1904 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1905 pipe
.TextureCacheInvalidationEnable
=
1906 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1907 pipe
.InstructionCacheInvalidateEnable
=
1908 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1910 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1912 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1913 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1914 * “Write Timestamp”.
1916 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1917 pipe
.PostSyncOperation
= WriteImmediateData
;
1919 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
1923 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1926 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1929 void genX(CmdPipelineBarrier
)(
1930 VkCommandBuffer commandBuffer
,
1931 VkPipelineStageFlags srcStageMask
,
1932 VkPipelineStageFlags destStageMask
,
1934 uint32_t memoryBarrierCount
,
1935 const VkMemoryBarrier
* pMemoryBarriers
,
1936 uint32_t bufferMemoryBarrierCount
,
1937 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1938 uint32_t imageMemoryBarrierCount
,
1939 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1941 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1943 /* XXX: Right now, we're really dumb and just flush whatever categories
1944 * the app asks for. One of these days we may make this a bit better
1945 * but right now that's all the hardware allows for in most areas.
1947 VkAccessFlags src_flags
= 0;
1948 VkAccessFlags dst_flags
= 0;
1950 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1951 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1952 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1955 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1956 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1957 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1960 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1961 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1962 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1963 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1964 const VkImageSubresourceRange
*range
=
1965 &pImageMemoryBarriers
[i
].subresourceRange
;
1967 uint32_t base_layer
, layer_count
;
1968 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1970 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1972 base_layer
= range
->baseArrayLayer
;
1973 layer_count
= anv_get_layerCount(image
, range
);
1976 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1977 transition_depth_buffer(cmd_buffer
, image
,
1978 pImageMemoryBarriers
[i
].oldLayout
,
1979 pImageMemoryBarriers
[i
].newLayout
);
1982 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1983 transition_stencil_buffer(cmd_buffer
, image
,
1984 range
->baseMipLevel
,
1985 anv_get_levelCount(image
, range
),
1986 base_layer
, layer_count
,
1987 pImageMemoryBarriers
[i
].oldLayout
,
1988 pImageMemoryBarriers
[i
].newLayout
);
1991 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1992 VkImageAspectFlags color_aspects
=
1993 anv_image_expand_aspects(image
, range
->aspectMask
);
1994 uint32_t aspect_bit
;
1995 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1996 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1997 range
->baseMipLevel
,
1998 anv_get_levelCount(image
, range
),
1999 base_layer
, layer_count
,
2000 pImageMemoryBarriers
[i
].oldLayout
,
2001 pImageMemoryBarriers
[i
].newLayout
);
2006 cmd_buffer
->state
.pending_pipe_bits
|=
2007 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2008 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2012 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2014 VkShaderStageFlags stages
=
2015 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2017 /* In order to avoid thrash, we assume that vertex and fragment stages
2018 * always exist. In the rare case where one is missing *and* the other
2019 * uses push concstants, this may be suboptimal. However, avoiding stalls
2020 * seems more important.
2022 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2024 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2028 const unsigned push_constant_kb
= 32;
2029 #elif GEN_IS_HASWELL
2030 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2032 const unsigned push_constant_kb
= 16;
2035 const unsigned num_stages
=
2036 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2037 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2039 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2040 * units of 2KB. Incidentally, these are the same platforms that have
2041 * 32KB worth of push constant space.
2043 if (push_constant_kb
== 32)
2044 size_per_stage
&= ~1u;
2046 uint32_t kb_used
= 0;
2047 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2048 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2049 anv_batch_emit(&cmd_buffer
->batch
,
2050 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2051 alloc
._3DCommandSubOpcode
= 18 + i
;
2052 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2053 alloc
.ConstantBufferSize
= push_size
;
2055 kb_used
+= push_size
;
2058 anv_batch_emit(&cmd_buffer
->batch
,
2059 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2060 alloc
.ConstantBufferOffset
= kb_used
;
2061 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2064 cmd_buffer
->state
.push_constant_stages
= stages
;
2066 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2068 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2069 * the next 3DPRIMITIVE command after programming the
2070 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2072 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2073 * pipeline setup, we need to dirty push constants.
2075 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2078 static struct anv_address
2079 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2080 struct anv_descriptor_set
*set
)
2083 /* This is a normal descriptor set */
2084 return (struct anv_address
) {
2085 .bo
= set
->pool
->bo
,
2086 .offset
= set
->desc_mem
.offset
,
2089 /* This is a push descriptor set. We have to flag it as used on the GPU
2090 * so that the next time we push descriptors, we grab a new memory.
2092 struct anv_push_descriptor_set
*push_set
=
2093 (struct anv_push_descriptor_set
*)set
;
2094 push_set
->set_used_on_gpu
= true;
2096 return (struct anv_address
) {
2097 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2098 .offset
= set
->desc_mem
.offset
,
2104 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2105 gl_shader_stage stage
,
2106 struct anv_state
*bt_state
)
2108 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2109 struct anv_cmd_pipeline_state
*pipe_state
;
2110 struct anv_pipeline
*pipeline
;
2111 uint32_t state_offset
;
2114 case MESA_SHADER_COMPUTE
:
2115 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2118 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2121 pipeline
= pipe_state
->pipeline
;
2123 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2124 *bt_state
= (struct anv_state
) { 0, };
2128 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2129 if (map
->surface_count
== 0) {
2130 *bt_state
= (struct anv_state
) { 0, };
2134 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2137 uint32_t *bt_map
= bt_state
->map
;
2139 if (bt_state
->map
== NULL
)
2140 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2142 /* We only need to emit relocs if we're not using softpin. If we are using
2143 * softpin then we always keep all user-allocated memory objects resident.
2145 const bool need_client_mem_relocs
=
2146 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2148 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2149 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2151 struct anv_state surface_state
;
2153 switch (binding
->set
) {
2154 case ANV_DESCRIPTOR_SET_NULL
:
2158 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2159 /* Color attachment binding */
2160 assert(stage
== MESA_SHADER_FRAGMENT
);
2161 if (binding
->index
< subpass
->color_count
) {
2162 const unsigned att
=
2163 subpass
->color_attachments
[binding
->index
].attachment
;
2165 /* From the Vulkan 1.0.46 spec:
2167 * "If any color or depth/stencil attachments are
2168 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2171 if (att
== VK_ATTACHMENT_UNUSED
) {
2172 surface_state
= cmd_buffer
->state
.null_surface_state
;
2174 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2177 surface_state
= cmd_buffer
->state
.null_surface_state
;
2180 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2183 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2184 struct anv_state surface_state
=
2185 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2187 struct anv_address constant_data
= {
2188 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2189 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2191 unsigned constant_data_size
=
2192 pipeline
->shaders
[stage
]->constant_data_size
;
2194 const enum isl_format format
=
2195 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2196 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2197 surface_state
, format
,
2198 constant_data
, constant_data_size
, 1);
2200 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2201 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2205 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2206 /* This is always the first binding for compute shaders */
2207 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2209 struct anv_state surface_state
=
2210 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2212 const enum isl_format format
=
2213 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2214 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2216 cmd_buffer
->state
.compute
.num_workgroups
,
2218 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2219 if (need_client_mem_relocs
) {
2220 add_surface_reloc(cmd_buffer
, surface_state
,
2221 cmd_buffer
->state
.compute
.num_workgroups
);
2226 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2227 /* This is a descriptor set buffer so the set index is actually
2228 * given by binding->binding. (Yes, that's confusing.)
2230 struct anv_descriptor_set
*set
=
2231 pipe_state
->descriptors
[binding
->index
];
2232 assert(set
->desc_mem
.alloc_size
);
2233 assert(set
->desc_surface_state
.alloc_size
);
2234 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2235 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2236 anv_descriptor_set_address(cmd_buffer
, set
));
2241 assert(binding
->set
< MAX_SETS
);
2242 const struct anv_descriptor
*desc
=
2243 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2245 switch (desc
->type
) {
2246 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2247 /* Nothing for us to do here */
2250 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2251 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2252 struct anv_surface_state sstate
=
2253 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2254 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2255 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2256 surface_state
= sstate
.state
;
2257 assert(surface_state
.alloc_size
);
2258 if (need_client_mem_relocs
)
2259 add_surface_state_relocs(cmd_buffer
, sstate
);
2262 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2263 assert(stage
== MESA_SHADER_FRAGMENT
);
2264 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2265 /* For depth and stencil input attachments, we treat it like any
2266 * old texture that a user may have bound.
2268 assert(desc
->image_view
->n_planes
== 1);
2269 struct anv_surface_state sstate
=
2270 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2271 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2272 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2273 surface_state
= sstate
.state
;
2274 assert(surface_state
.alloc_size
);
2275 if (need_client_mem_relocs
)
2276 add_surface_state_relocs(cmd_buffer
, sstate
);
2278 /* For color input attachments, we create the surface state at
2279 * vkBeginRenderPass time so that we can include aux and clear
2280 * color information.
2282 assert(binding
->input_attachment_index
< subpass
->input_count
);
2283 const unsigned subpass_att
= binding
->input_attachment_index
;
2284 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2285 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2289 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2290 struct anv_surface_state sstate
= (binding
->write_only
)
2291 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2292 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2293 surface_state
= sstate
.state
;
2294 assert(surface_state
.alloc_size
);
2295 if (need_client_mem_relocs
)
2296 add_surface_state_relocs(cmd_buffer
, sstate
);
2300 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2301 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2302 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2303 surface_state
= desc
->buffer_view
->surface_state
;
2304 assert(surface_state
.alloc_size
);
2305 if (need_client_mem_relocs
) {
2306 add_surface_reloc(cmd_buffer
, surface_state
,
2307 desc
->buffer_view
->address
);
2311 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2312 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2313 /* Compute the offset within the buffer */
2314 struct anv_push_constants
*push
=
2315 &cmd_buffer
->state
.push_constants
[stage
];
2317 uint32_t dynamic_offset
=
2318 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2319 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2320 /* Clamp to the buffer size */
2321 offset
= MIN2(offset
, desc
->buffer
->size
);
2322 /* Clamp the range to the buffer size */
2323 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2325 struct anv_address address
=
2326 anv_address_add(desc
->buffer
->address
, offset
);
2329 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2330 enum isl_format format
=
2331 anv_isl_format_for_descriptor_type(desc
->type
);
2333 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2334 format
, address
, range
, 1);
2335 if (need_client_mem_relocs
)
2336 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2340 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2341 surface_state
= (binding
->write_only
)
2342 ? desc
->buffer_view
->writeonly_storage_surface_state
2343 : desc
->buffer_view
->storage_surface_state
;
2344 assert(surface_state
.alloc_size
);
2345 if (need_client_mem_relocs
) {
2346 add_surface_reloc(cmd_buffer
, surface_state
,
2347 desc
->buffer_view
->address
);
2352 assert(!"Invalid descriptor type");
2355 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2365 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2366 gl_shader_stage stage
,
2367 struct anv_state
*state
)
2369 struct anv_cmd_pipeline_state
*pipe_state
=
2370 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2371 &cmd_buffer
->state
.gfx
.base
;
2372 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2374 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2375 *state
= (struct anv_state
) { 0, };
2379 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2380 if (map
->sampler_count
== 0) {
2381 *state
= (struct anv_state
) { 0, };
2385 uint32_t size
= map
->sampler_count
* 16;
2386 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2388 if (state
->map
== NULL
)
2389 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2391 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2392 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2393 const struct anv_descriptor
*desc
=
2394 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2396 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2397 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2400 struct anv_sampler
*sampler
= desc
->sampler
;
2402 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2403 * happens to be zero.
2405 if (sampler
== NULL
)
2408 memcpy(state
->map
+ (s
* 16),
2409 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2416 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2418 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2420 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2421 pipeline
->active_stages
;
2423 VkResult result
= VK_SUCCESS
;
2424 anv_foreach_stage(s
, dirty
) {
2425 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2426 if (result
!= VK_SUCCESS
)
2428 result
= emit_binding_table(cmd_buffer
, s
,
2429 &cmd_buffer
->state
.binding_tables
[s
]);
2430 if (result
!= VK_SUCCESS
)
2434 if (result
!= VK_SUCCESS
) {
2435 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2437 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2438 if (result
!= VK_SUCCESS
)
2441 /* Re-emit state base addresses so we get the new surface state base
2442 * address before we start emitting binding tables etc.
2444 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2446 /* Re-emit all active binding tables */
2447 dirty
|= pipeline
->active_stages
;
2448 anv_foreach_stage(s
, dirty
) {
2449 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2450 if (result
!= VK_SUCCESS
) {
2451 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2454 result
= emit_binding_table(cmd_buffer
, s
,
2455 &cmd_buffer
->state
.binding_tables
[s
]);
2456 if (result
!= VK_SUCCESS
) {
2457 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2463 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2469 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2472 static const uint32_t sampler_state_opcodes
[] = {
2473 [MESA_SHADER_VERTEX
] = 43,
2474 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2475 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2476 [MESA_SHADER_GEOMETRY
] = 46,
2477 [MESA_SHADER_FRAGMENT
] = 47,
2478 [MESA_SHADER_COMPUTE
] = 0,
2481 static const uint32_t binding_table_opcodes
[] = {
2482 [MESA_SHADER_VERTEX
] = 38,
2483 [MESA_SHADER_TESS_CTRL
] = 39,
2484 [MESA_SHADER_TESS_EVAL
] = 40,
2485 [MESA_SHADER_GEOMETRY
] = 41,
2486 [MESA_SHADER_FRAGMENT
] = 42,
2487 [MESA_SHADER_COMPUTE
] = 0,
2490 anv_foreach_stage(s
, stages
) {
2491 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2492 assert(binding_table_opcodes
[s
] > 0);
2494 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2495 anv_batch_emit(&cmd_buffer
->batch
,
2496 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2497 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2498 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2502 /* Always emit binding table pointers if we're asked to, since on SKL
2503 * this is what flushes push constants. */
2504 anv_batch_emit(&cmd_buffer
->batch
,
2505 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2506 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2507 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2512 static struct anv_address
2513 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2514 gl_shader_stage stage
,
2515 const struct anv_push_range
*range
)
2517 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2518 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2519 switch (range
->set
) {
2520 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2521 /* This is a descriptor set buffer so the set index is
2522 * actually given by binding->binding. (Yes, that's
2525 struct anv_descriptor_set
*set
=
2526 gfx_state
->base
.descriptors
[range
->index
];
2527 return anv_descriptor_set_address(cmd_buffer
, set
);
2531 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2532 struct anv_state state
=
2533 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2534 return (struct anv_address
) {
2535 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2536 .offset
= state
.offset
,
2542 assert(range
->set
< MAX_SETS
);
2543 struct anv_descriptor_set
*set
=
2544 gfx_state
->base
.descriptors
[range
->set
];
2545 const struct anv_descriptor
*desc
=
2546 &set
->descriptors
[range
->index
];
2548 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2549 return desc
->buffer_view
->address
;
2551 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2552 struct anv_push_constants
*push
=
2553 &cmd_buffer
->state
.push_constants
[stage
];
2554 uint32_t dynamic_offset
=
2555 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2556 return anv_address_add(desc
->buffer
->address
,
2557 desc
->offset
+ dynamic_offset
);
2562 /* For Ivy Bridge, push constants are relative to dynamic state
2563 * base address and we only ever push actual push constants.
2565 assert(range
->length
> 0);
2566 assert(range
->set
== ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
2567 struct anv_state state
=
2568 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2569 return (struct anv_address
) {
2570 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2571 .offset
= state
.offset
,
2577 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2578 VkShaderStageFlags dirty_stages
)
2580 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2581 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2583 static const uint32_t push_constant_opcodes
[] = {
2584 [MESA_SHADER_VERTEX
] = 21,
2585 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2586 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2587 [MESA_SHADER_GEOMETRY
] = 22,
2588 [MESA_SHADER_FRAGMENT
] = 23,
2589 [MESA_SHADER_COMPUTE
] = 0,
2592 VkShaderStageFlags flushed
= 0;
2594 anv_foreach_stage(stage
, dirty_stages
) {
2595 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2596 assert(push_constant_opcodes
[stage
] > 0);
2598 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2599 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2601 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2602 const struct anv_pipeline_bind_map
*bind_map
=
2603 &pipeline
->shaders
[stage
]->bind_map
;
2605 unsigned buffer_count
= 0;
2606 for (unsigned i
= 0; i
< 4; i
++) {
2607 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2608 if (range
->length
> 0)
2612 /* The Skylake PRM contains the following restriction:
2614 * "The driver must ensure The following case does not occur
2615 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2616 * buffer 3 read length equal to zero committed followed by a
2617 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2620 * To avoid this, we program the buffers in the highest slots.
2621 * This way, slot 0 is only used if slot 3 is also used.
2623 assert(buffer_count
<= 4);
2624 const unsigned shift
= 4 - buffer_count
;
2625 for (unsigned i
= 0; i
< buffer_count
; i
++) {
2626 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2628 /* At this point we only have non-empty ranges */
2629 assert(range
->length
> 0);
2631 /* For Ivy Bridge, make sure we only set the first range (actual
2634 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
2636 const struct anv_address addr
=
2637 get_push_range_address(cmd_buffer
, stage
, range
);
2639 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
2640 c
.ConstantBody
.Buffer
[i
+ shift
] =
2641 anv_address_add(addr
, range
->start
* 32);
2646 flushed
|= mesa_to_vk_shader_stage(stage
);
2649 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2654 genX(cmd_buffer_aux_map_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2656 void *aux_map_ctx
= cmd_buffer
->device
->aux_map_ctx
;
2659 uint32_t aux_map_state_num
= gen_aux_map_get_state_num(aux_map_ctx
);
2660 if (cmd_buffer
->state
.last_aux_map_state
!= aux_map_state_num
) {
2661 /* If the aux-map state number increased, then we need to rewrite the
2662 * register. Rewriting the register is used to both set the aux-map
2663 * translation table address, and also to invalidate any previously
2664 * cached translations.
2666 uint64_t base_addr
= gen_aux_map_get_base(aux_map_ctx
);
2667 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2668 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
);
2669 lri
.DataDWord
= base_addr
& 0xffffffff;
2671 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2672 lri
.RegisterOffset
= GENX(GFX_AUX_TABLE_BASE_ADDR_num
) + 4;
2673 lri
.DataDWord
= base_addr
>> 32;
2675 cmd_buffer
->state
.last_aux_map_state
= aux_map_state_num
;
2681 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2683 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2686 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2687 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2688 vb_emit
|= pipeline
->vb_used
;
2690 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2692 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2694 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
2696 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2699 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
2703 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2704 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2706 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2707 GENX(3DSTATE_VERTEX_BUFFERS
));
2709 for_each_bit(vb
, vb_emit
) {
2710 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2711 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2713 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2714 .VertexBufferIndex
= vb
,
2716 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2718 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2719 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2722 .AddressModifyEnable
= true,
2723 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2724 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2727 .BufferSize
= buffer
->size
- offset
2729 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2733 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2738 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2741 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2742 /* We don't need any per-buffer dirty tracking because you're not
2743 * allowed to bind different XFB buffers while XFB is enabled.
2745 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2746 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2747 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2749 sob
.SOBufferIndex
= idx
;
2751 sob
._3DCommandOpcode
= 0;
2752 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
2755 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2756 sob
.SOBufferEnable
= true;
2757 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
2758 sob
.StreamOffsetWriteEnable
= false;
2759 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2761 /* Size is in DWords - 1 */
2762 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2767 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2769 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2773 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2774 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2776 /* If the pipeline changed, we may need to re-allocate push constant
2779 cmd_buffer_alloc_push_constants(cmd_buffer
);
2783 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2784 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2785 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2787 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2788 * stall needs to be sent just prior to any 3DSTATE_VS,
2789 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2790 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2791 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2792 * PIPE_CONTROL needs to be sent before any combination of VS
2793 * associated 3DSTATE."
2795 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2796 pc
.DepthStallEnable
= true;
2797 pc
.PostSyncOperation
= WriteImmediateData
;
2799 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2804 /* Render targets live in the same binding table as fragment descriptors */
2805 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2806 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2808 /* We emit the binding tables and sampler tables first, then emit push
2809 * constants and then finally emit binding table and sampler table
2810 * pointers. It has to happen in this order, since emitting the binding
2811 * tables may change the push constants (in case of storage images). After
2812 * emitting push constants, on SKL+ we have to emit the corresponding
2813 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2816 if (cmd_buffer
->state
.descriptors_dirty
)
2817 dirty
= flush_descriptor_sets(cmd_buffer
);
2819 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2820 /* Because we're pushing UBOs, we have to push whenever either
2821 * descriptors or push constants is dirty.
2823 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2824 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2825 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2829 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2831 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2832 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2834 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2835 ANV_CMD_DIRTY_PIPELINE
)) {
2836 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2837 pipeline
->depth_clamp_enable
);
2840 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2841 ANV_CMD_DIRTY_RENDER_TARGETS
))
2842 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2844 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2846 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2850 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2851 struct anv_address addr
,
2852 uint32_t size
, uint32_t index
)
2854 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2855 GENX(3DSTATE_VERTEX_BUFFERS
));
2857 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2858 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2859 .VertexBufferIndex
= index
,
2860 .AddressModifyEnable
= true,
2862 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
2863 .NullVertexBuffer
= size
== 0,
2865 .BufferStartingAddress
= addr
,
2868 .BufferStartingAddress
= addr
,
2869 .EndAddress
= anv_address_add(addr
, size
),
2875 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2876 struct anv_address addr
)
2878 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
2882 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2883 uint32_t base_vertex
, uint32_t base_instance
)
2885 if (base_vertex
== 0 && base_instance
== 0) {
2886 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
2888 struct anv_state id_state
=
2889 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2891 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2892 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2894 struct anv_address addr
= {
2895 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2896 .offset
= id_state
.offset
,
2899 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2904 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2906 struct anv_state state
=
2907 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2909 ((uint32_t *)state
.map
)[0] = draw_index
;
2911 struct anv_address addr
= {
2912 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2913 .offset
= state
.offset
,
2916 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2920 VkCommandBuffer commandBuffer
,
2921 uint32_t vertexCount
,
2922 uint32_t instanceCount
,
2923 uint32_t firstVertex
,
2924 uint32_t firstInstance
)
2926 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2927 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2928 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2930 if (anv_batch_has_error(&cmd_buffer
->batch
))
2933 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2935 if (cmd_buffer
->state
.conditional_render_enabled
)
2936 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2938 if (vs_prog_data
->uses_firstvertex
||
2939 vs_prog_data
->uses_baseinstance
)
2940 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2941 if (vs_prog_data
->uses_drawid
)
2942 emit_draw_index(cmd_buffer
, 0);
2944 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2945 * different views. We need to multiply instanceCount by the view count.
2947 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2949 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2950 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2951 prim
.VertexAccessType
= SEQUENTIAL
;
2952 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2953 prim
.VertexCountPerInstance
= vertexCount
;
2954 prim
.StartVertexLocation
= firstVertex
;
2955 prim
.InstanceCount
= instanceCount
;
2956 prim
.StartInstanceLocation
= firstInstance
;
2957 prim
.BaseVertexLocation
= 0;
2961 void genX(CmdDrawIndexed
)(
2962 VkCommandBuffer commandBuffer
,
2963 uint32_t indexCount
,
2964 uint32_t instanceCount
,
2965 uint32_t firstIndex
,
2966 int32_t vertexOffset
,
2967 uint32_t firstInstance
)
2969 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2970 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2971 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2973 if (anv_batch_has_error(&cmd_buffer
->batch
))
2976 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2978 if (cmd_buffer
->state
.conditional_render_enabled
)
2979 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2981 if (vs_prog_data
->uses_firstvertex
||
2982 vs_prog_data
->uses_baseinstance
)
2983 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2984 if (vs_prog_data
->uses_drawid
)
2985 emit_draw_index(cmd_buffer
, 0);
2987 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2988 * different views. We need to multiply instanceCount by the view count.
2990 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2992 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2993 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2994 prim
.VertexAccessType
= RANDOM
;
2995 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2996 prim
.VertexCountPerInstance
= indexCount
;
2997 prim
.StartVertexLocation
= firstIndex
;
2998 prim
.InstanceCount
= instanceCount
;
2999 prim
.StartInstanceLocation
= firstInstance
;
3000 prim
.BaseVertexLocation
= vertexOffset
;
3004 /* Auto-Draw / Indirect Registers */
3005 #define GEN7_3DPRIM_END_OFFSET 0x2420
3006 #define GEN7_3DPRIM_START_VERTEX 0x2430
3007 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3008 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3009 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3010 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3012 void genX(CmdDrawIndirectByteCountEXT
)(
3013 VkCommandBuffer commandBuffer
,
3014 uint32_t instanceCount
,
3015 uint32_t firstInstance
,
3016 VkBuffer counterBuffer
,
3017 VkDeviceSize counterBufferOffset
,
3018 uint32_t counterOffset
,
3019 uint32_t vertexStride
)
3021 #if GEN_IS_HASWELL || GEN_GEN >= 8
3022 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3023 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3024 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3025 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3027 /* firstVertex is always zero for this draw function */
3028 const uint32_t firstVertex
= 0;
3030 if (anv_batch_has_error(&cmd_buffer
->batch
))
3033 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3035 if (vs_prog_data
->uses_firstvertex
||
3036 vs_prog_data
->uses_baseinstance
)
3037 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3038 if (vs_prog_data
->uses_drawid
)
3039 emit_draw_index(cmd_buffer
, 0);
3041 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3042 * different views. We need to multiply instanceCount by the view count.
3044 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3046 struct gen_mi_builder b
;
3047 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3048 struct gen_mi_value count
=
3049 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3050 counterBufferOffset
));
3052 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3053 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3054 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3056 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3057 gen_mi_imm(firstVertex
));
3058 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3059 gen_mi_imm(instanceCount
));
3060 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3061 gen_mi_imm(firstInstance
));
3062 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3064 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3065 prim
.IndirectParameterEnable
= true;
3066 prim
.VertexAccessType
= SEQUENTIAL
;
3067 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3069 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3073 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3074 struct anv_address addr
,
3077 struct gen_mi_builder b
;
3078 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3080 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3081 gen_mi_mem32(anv_address_add(addr
, 0)));
3083 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3084 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3085 if (view_count
> 1) {
3086 #if GEN_IS_HASWELL || GEN_GEN >= 8
3087 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3089 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3090 "MI_MATH is not supported on Ivy Bridge");
3093 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3095 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3096 gen_mi_mem32(anv_address_add(addr
, 8)));
3099 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3100 gen_mi_mem32(anv_address_add(addr
, 12)));
3101 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3102 gen_mi_mem32(anv_address_add(addr
, 16)));
3104 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3105 gen_mi_mem32(anv_address_add(addr
, 12)));
3106 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3110 void genX(CmdDrawIndirect
)(
3111 VkCommandBuffer commandBuffer
,
3113 VkDeviceSize offset
,
3117 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3118 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3119 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3120 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3122 if (anv_batch_has_error(&cmd_buffer
->batch
))
3125 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3127 if (cmd_buffer
->state
.conditional_render_enabled
)
3128 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3130 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3131 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3133 if (vs_prog_data
->uses_firstvertex
||
3134 vs_prog_data
->uses_baseinstance
)
3135 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3136 if (vs_prog_data
->uses_drawid
)
3137 emit_draw_index(cmd_buffer
, i
);
3139 load_indirect_parameters(cmd_buffer
, draw
, false);
3141 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3142 prim
.IndirectParameterEnable
= true;
3143 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3144 prim
.VertexAccessType
= SEQUENTIAL
;
3145 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3152 void genX(CmdDrawIndexedIndirect
)(
3153 VkCommandBuffer commandBuffer
,
3155 VkDeviceSize offset
,
3159 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3160 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3161 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3162 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3164 if (anv_batch_has_error(&cmd_buffer
->batch
))
3167 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3169 if (cmd_buffer
->state
.conditional_render_enabled
)
3170 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3172 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3173 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3175 /* TODO: We need to stomp base vertex to 0 somehow */
3176 if (vs_prog_data
->uses_firstvertex
||
3177 vs_prog_data
->uses_baseinstance
)
3178 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3179 if (vs_prog_data
->uses_drawid
)
3180 emit_draw_index(cmd_buffer
, i
);
3182 load_indirect_parameters(cmd_buffer
, draw
, true);
3184 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3185 prim
.IndirectParameterEnable
= true;
3186 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3187 prim
.VertexAccessType
= RANDOM
;
3188 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3195 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3198 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3199 struct anv_address count_address
,
3200 const bool conditional_render_enabled
)
3202 struct gen_mi_builder b
;
3203 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3205 if (conditional_render_enabled
) {
3206 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3207 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3208 gen_mi_mem32(count_address
));
3211 /* Upload the current draw count from the draw parameters buffer to
3212 * MI_PREDICATE_SRC0.
3214 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3215 gen_mi_mem32(count_address
));
3217 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3222 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3223 uint32_t draw_index
)
3225 struct gen_mi_builder b
;
3226 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3228 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3229 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3231 if (draw_index
== 0) {
3232 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3233 mip
.LoadOperation
= LOAD_LOADINV
;
3234 mip
.CombineOperation
= COMBINE_SET
;
3235 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3238 /* While draw_index < draw_count the predicate's result will be
3239 * (draw_index == draw_count) ^ TRUE = TRUE
3240 * When draw_index == draw_count the result is
3241 * (TRUE) ^ TRUE = FALSE
3242 * After this all results will be:
3243 * (FALSE) ^ FALSE = FALSE
3245 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3246 mip
.LoadOperation
= LOAD_LOAD
;
3247 mip
.CombineOperation
= COMBINE_XOR
;
3248 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3253 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3255 emit_draw_count_predicate_with_conditional_render(
3256 struct anv_cmd_buffer
*cmd_buffer
,
3257 uint32_t draw_index
)
3259 struct gen_mi_builder b
;
3260 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3262 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3263 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3264 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3267 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3269 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3270 * so we emit MI_PREDICATE to set it.
3273 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3274 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3276 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3277 mip
.LoadOperation
= LOAD_LOADINV
;
3278 mip
.CombineOperation
= COMBINE_SET
;
3279 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3285 void genX(CmdDrawIndirectCountKHR
)(
3286 VkCommandBuffer commandBuffer
,
3288 VkDeviceSize offset
,
3289 VkBuffer _countBuffer
,
3290 VkDeviceSize countBufferOffset
,
3291 uint32_t maxDrawCount
,
3294 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3295 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3296 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3297 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3298 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3299 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3301 if (anv_batch_has_error(&cmd_buffer
->batch
))
3304 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3306 struct anv_address count_address
=
3307 anv_address_add(count_buffer
->address
, countBufferOffset
);
3309 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3310 cmd_state
->conditional_render_enabled
);
3312 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3313 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3315 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3316 if (cmd_state
->conditional_render_enabled
) {
3317 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3319 emit_draw_count_predicate(cmd_buffer
, i
);
3322 emit_draw_count_predicate(cmd_buffer
, i
);
3325 if (vs_prog_data
->uses_firstvertex
||
3326 vs_prog_data
->uses_baseinstance
)
3327 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3328 if (vs_prog_data
->uses_drawid
)
3329 emit_draw_index(cmd_buffer
, i
);
3331 load_indirect_parameters(cmd_buffer
, draw
, false);
3333 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3334 prim
.IndirectParameterEnable
= true;
3335 prim
.PredicateEnable
= true;
3336 prim
.VertexAccessType
= SEQUENTIAL
;
3337 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3344 void genX(CmdDrawIndexedIndirectCountKHR
)(
3345 VkCommandBuffer commandBuffer
,
3347 VkDeviceSize offset
,
3348 VkBuffer _countBuffer
,
3349 VkDeviceSize countBufferOffset
,
3350 uint32_t maxDrawCount
,
3353 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3354 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3355 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3356 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3357 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3358 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3360 if (anv_batch_has_error(&cmd_buffer
->batch
))
3363 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3365 struct anv_address count_address
=
3366 anv_address_add(count_buffer
->address
, countBufferOffset
);
3368 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3369 cmd_state
->conditional_render_enabled
);
3371 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3372 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3374 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3375 if (cmd_state
->conditional_render_enabled
) {
3376 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3378 emit_draw_count_predicate(cmd_buffer
, i
);
3381 emit_draw_count_predicate(cmd_buffer
, i
);
3384 /* TODO: We need to stomp base vertex to 0 somehow */
3385 if (vs_prog_data
->uses_firstvertex
||
3386 vs_prog_data
->uses_baseinstance
)
3387 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3388 if (vs_prog_data
->uses_drawid
)
3389 emit_draw_index(cmd_buffer
, i
);
3391 load_indirect_parameters(cmd_buffer
, draw
, true);
3393 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3394 prim
.IndirectParameterEnable
= true;
3395 prim
.PredicateEnable
= true;
3396 prim
.VertexAccessType
= RANDOM
;
3397 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3404 void genX(CmdBeginTransformFeedbackEXT
)(
3405 VkCommandBuffer commandBuffer
,
3406 uint32_t firstCounterBuffer
,
3407 uint32_t counterBufferCount
,
3408 const VkBuffer
* pCounterBuffers
,
3409 const VkDeviceSize
* pCounterBufferOffsets
)
3411 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3413 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3414 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3415 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3417 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3419 * "Ssoftware must ensure that no HW stream output operations can be in
3420 * process or otherwise pending at the point that the MI_LOAD/STORE
3421 * commands are processed. This will likely require a pipeline flush."
3423 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3424 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3426 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3427 /* If we have a counter buffer, this is a resume so we need to load the
3428 * value into the streamout offset register. Otherwise, this is a begin
3429 * and we need to reset it to zero.
3431 if (pCounterBuffers
&&
3432 idx
>= firstCounterBuffer
&&
3433 idx
- firstCounterBuffer
< counterBufferCount
&&
3434 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3435 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3436 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3437 uint64_t offset
= pCounterBufferOffsets
?
3438 pCounterBufferOffsets
[cb_idx
] : 0;
3440 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3441 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3442 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3446 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3447 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3453 cmd_buffer
->state
.xfb_enabled
= true;
3454 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3457 void genX(CmdEndTransformFeedbackEXT
)(
3458 VkCommandBuffer commandBuffer
,
3459 uint32_t firstCounterBuffer
,
3460 uint32_t counterBufferCount
,
3461 const VkBuffer
* pCounterBuffers
,
3462 const VkDeviceSize
* pCounterBufferOffsets
)
3464 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3466 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3467 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3468 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3470 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3472 * "Ssoftware must ensure that no HW stream output operations can be in
3473 * process or otherwise pending at the point that the MI_LOAD/STORE
3474 * commands are processed. This will likely require a pipeline flush."
3476 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3477 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3479 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3480 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3482 /* If we have a counter buffer, this is a resume so we need to load the
3483 * value into the streamout offset register. Otherwise, this is a begin
3484 * and we need to reset it to zero.
3486 if (pCounterBuffers
&&
3487 cb_idx
< counterBufferCount
&&
3488 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3489 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3490 uint64_t offset
= pCounterBufferOffsets
?
3491 pCounterBufferOffsets
[cb_idx
] : 0;
3493 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3494 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3496 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3501 cmd_buffer
->state
.xfb_enabled
= false;
3502 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3506 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3508 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3509 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3512 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3513 if (result
!= VK_SUCCESS
) {
3514 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3516 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3517 if (result
!= VK_SUCCESS
)
3520 /* Re-emit state base addresses so we get the new surface state base
3521 * address before we start emitting binding tables etc.
3523 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3525 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3526 if (result
!= VK_SUCCESS
) {
3527 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3532 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3533 if (result
!= VK_SUCCESS
) {
3534 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3538 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3539 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3540 .BindingTablePointer
= surfaces
.offset
,
3541 .SamplerStatePointer
= samplers
.offset
,
3543 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3545 struct anv_state state
=
3546 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3547 pipeline
->interface_descriptor_data
,
3548 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3551 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3552 anv_batch_emit(&cmd_buffer
->batch
,
3553 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3554 mid
.InterfaceDescriptorTotalLength
= size
;
3555 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3562 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3564 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3567 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3569 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3571 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3574 genX(cmd_buffer_aux_map_state
)(cmd_buffer
);
3577 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3578 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3580 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3581 * the only bits that are changed are scoreboard related: Scoreboard
3582 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3583 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3586 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3587 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3589 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3591 /* The workgroup size of the pipeline affects our push constant layout
3592 * so flag push constants as dirty if we change the pipeline.
3594 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3597 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3598 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3599 /* FIXME: figure out descriptors for gen7 */
3600 result
= flush_compute_descriptor_set(cmd_buffer
);
3601 if (result
!= VK_SUCCESS
)
3604 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3607 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3608 struct anv_state push_state
=
3609 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3611 if (push_state
.alloc_size
) {
3612 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3613 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3614 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3618 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3621 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3623 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3629 verify_cmd_parser(const struct anv_device
*device
,
3630 int required_version
,
3631 const char *function
)
3633 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3634 return vk_errorf(device
->instance
, device
->instance
,
3635 VK_ERROR_FEATURE_NOT_PRESENT
,
3636 "cmd parser version %d is required for %s",
3637 required_version
, function
);
3646 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3647 uint32_t baseGroupX
,
3648 uint32_t baseGroupY
,
3649 uint32_t baseGroupZ
)
3651 if (anv_batch_has_error(&cmd_buffer
->batch
))
3654 struct anv_push_constants
*push
=
3655 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3656 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
3657 push
->cs
.base_work_group_id
[1] != baseGroupY
||
3658 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
3659 push
->cs
.base_work_group_id
[0] = baseGroupX
;
3660 push
->cs
.base_work_group_id
[1] = baseGroupY
;
3661 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
3663 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3667 void genX(CmdDispatch
)(
3668 VkCommandBuffer commandBuffer
,
3673 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3676 void genX(CmdDispatchBase
)(
3677 VkCommandBuffer commandBuffer
,
3678 uint32_t baseGroupX
,
3679 uint32_t baseGroupY
,
3680 uint32_t baseGroupZ
,
3681 uint32_t groupCountX
,
3682 uint32_t groupCountY
,
3683 uint32_t groupCountZ
)
3685 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3686 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3687 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3689 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3690 baseGroupY
, baseGroupZ
);
3692 if (anv_batch_has_error(&cmd_buffer
->batch
))
3695 if (prog_data
->uses_num_work_groups
) {
3696 struct anv_state state
=
3697 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3698 uint32_t *sizes
= state
.map
;
3699 sizes
[0] = groupCountX
;
3700 sizes
[1] = groupCountY
;
3701 sizes
[2] = groupCountZ
;
3702 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3703 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3704 .offset
= state
.offset
,
3708 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3710 if (cmd_buffer
->state
.conditional_render_enabled
)
3711 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3713 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3714 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3715 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3716 ggw
.ThreadDepthCounterMaximum
= 0;
3717 ggw
.ThreadHeightCounterMaximum
= 0;
3718 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3719 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3720 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3721 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3722 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3723 ggw
.BottomExecutionMask
= 0xffffffff;
3726 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3729 #define GPGPU_DISPATCHDIMX 0x2500
3730 #define GPGPU_DISPATCHDIMY 0x2504
3731 #define GPGPU_DISPATCHDIMZ 0x2508
3733 void genX(CmdDispatchIndirect
)(
3734 VkCommandBuffer commandBuffer
,
3736 VkDeviceSize offset
)
3738 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3739 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3740 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3741 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3742 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3743 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3745 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3748 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3749 * indirect dispatch registers to be written.
3751 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3752 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3756 if (prog_data
->uses_num_work_groups
)
3757 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3759 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3761 struct gen_mi_builder b
;
3762 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3764 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3765 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3766 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3768 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3769 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3770 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3773 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3774 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3775 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3776 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3777 mip
.LoadOperation
= LOAD_LOAD
;
3778 mip
.CombineOperation
= COMBINE_SET
;
3779 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3782 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3783 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3784 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3785 mip
.LoadOperation
= LOAD_LOAD
;
3786 mip
.CombineOperation
= COMBINE_OR
;
3787 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3790 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3791 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3792 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3793 mip
.LoadOperation
= LOAD_LOAD
;
3794 mip
.CombineOperation
= COMBINE_OR
;
3795 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3798 /* predicate = !predicate; */
3799 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3800 mip
.LoadOperation
= LOAD_LOADINV
;
3801 mip
.CombineOperation
= COMBINE_OR
;
3802 mip
.CompareOperation
= COMPARE_FALSE
;
3806 if (cmd_buffer
->state
.conditional_render_enabled
) {
3807 /* predicate &= !(conditional_rendering_predicate == 0); */
3808 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3809 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3810 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3811 mip
.LoadOperation
= LOAD_LOADINV
;
3812 mip
.CombineOperation
= COMBINE_AND
;
3813 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3818 #else /* GEN_GEN > 7 */
3819 if (cmd_buffer
->state
.conditional_render_enabled
)
3820 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3823 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3824 ggw
.IndirectParameterEnable
= true;
3825 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3826 cmd_buffer
->state
.conditional_render_enabled
;
3827 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3828 ggw
.ThreadDepthCounterMaximum
= 0;
3829 ggw
.ThreadHeightCounterMaximum
= 0;
3830 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3831 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3832 ggw
.BottomExecutionMask
= 0xffffffff;
3835 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3839 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3842 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3844 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3847 #if GEN_GEN >= 8 && GEN_GEN < 10
3848 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3850 * Software must clear the COLOR_CALC_STATE Valid field in
3851 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3852 * with Pipeline Select set to GPGPU.
3854 * The internal hardware docs recommend the same workaround for Gen9
3857 if (pipeline
== GPGPU
)
3858 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3862 if (pipeline
== _3D
) {
3863 /* There is a mid-object preemption workaround which requires you to
3864 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
3865 * even without preemption, we have issues with geometry flickering when
3866 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
3869 const uint32_t subslices
=
3870 MAX2(cmd_buffer
->device
->instance
->physicalDevice
.subslice_total
, 1);
3871 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
3872 vfe
.MaximumNumberofThreads
=
3873 devinfo
->max_cs_threads
* subslices
- 1;
3874 vfe
.NumberofURBEntries
= 2;
3875 vfe
.URBEntryAllocationSize
= 2;
3880 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3881 * PIPELINE_SELECT [DevBWR+]":
3885 * Software must ensure all the write caches are flushed through a
3886 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3887 * command to invalidate read only caches prior to programming
3888 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3890 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3891 pc
.RenderTargetCacheFlushEnable
= true;
3892 pc
.DepthCacheFlushEnable
= true;
3893 pc
.DCFlushEnable
= true;
3894 pc
.PostSyncOperation
= NoWrite
;
3895 pc
.CommandStreamerStallEnable
= true;
3897 pc
.TileCacheFlushEnable
= true;
3901 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3902 pc
.TextureCacheInvalidationEnable
= true;
3903 pc
.ConstantCacheInvalidationEnable
= true;
3904 pc
.StateCacheInvalidationEnable
= true;
3905 pc
.InstructionCacheInvalidateEnable
= true;
3906 pc
.PostSyncOperation
= NoWrite
;
3908 pc
.TileCacheFlushEnable
= true;
3912 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3916 ps
.PipelineSelection
= pipeline
;
3920 if (devinfo
->is_geminilake
) {
3923 * "This chicken bit works around a hardware issue with barrier logic
3924 * encountered when switching between GPGPU and 3D pipelines. To
3925 * workaround the issue, this mode bit should be set after a pipeline
3929 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3931 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3932 : GLK_BARRIER_MODE_3D_HULL
,
3933 .GLKBarrierModeMask
= 1);
3934 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3938 cmd_buffer
->state
.current_pipeline
= pipeline
;
3942 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3944 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3948 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3950 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3954 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3959 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3961 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3962 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3963 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3964 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3965 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3966 * Depth Flush Bit set, followed by another pipelined depth stall
3967 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3968 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3969 * via a preceding MI_FLUSH)."
3971 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3972 pipe
.DepthStallEnable
= true;
3974 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3975 pipe
.DepthCacheFlushEnable
= true;
3977 pipe
.TileCacheFlushEnable
= true;
3980 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3981 pipe
.DepthStallEnable
= true;
3986 * Update the pixel hashing modes that determine the balancing of PS threads
3987 * across subslices and slices.
3989 * \param width Width bound of the rendering area (already scaled down if \p
3990 * scale is greater than 1).
3991 * \param height Height bound of the rendering area (already scaled down if \p
3992 * scale is greater than 1).
3993 * \param scale The number of framebuffer samples that could potentially be
3994 * affected by an individual channel of the PS thread. This is
3995 * typically one for single-sampled rendering, but for operations
3996 * like CCS resolves and fast clears a single PS invocation may
3997 * update a huge number of pixels, in which case a finer
3998 * balancing is desirable in order to maximally utilize the
3999 * bandwidth available. UINT_MAX can be used as shorthand for
4000 * "finest hashing mode available".
4003 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4004 unsigned width
, unsigned height
,
4008 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4009 const unsigned slice_hashing
[] = {
4010 /* Because all Gen9 platforms with more than one slice require
4011 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4012 * block is guaranteed to suffer from substantial imbalance, with one
4013 * subslice receiving twice as much work as the other two in the
4016 * The performance impact of that would be particularly severe when
4017 * three-way hashing is also in use for slice balancing (which is the
4018 * case for all Gen9 GT4 platforms), because one of the slices
4019 * receives one every three 16x16 blocks in either direction, which
4020 * is roughly the periodicity of the underlying subslice imbalance
4021 * pattern ("roughly" because in reality the hardware's
4022 * implementation of three-way hashing doesn't do exact modulo 3
4023 * arithmetic, which somewhat decreases the magnitude of this effect
4024 * in practice). This leads to a systematic subslice imbalance
4025 * within that slice regardless of the size of the primitive. The
4026 * 32x32 hashing mode guarantees that the subslice imbalance within a
4027 * single slice hashing block is minimal, largely eliminating this
4031 /* Finest slice hashing mode available. */
4034 const unsigned subslice_hashing
[] = {
4035 /* 16x16 would provide a slight cache locality benefit especially
4036 * visible in the sampler L1 cache efficiency of low-bandwidth
4037 * non-LLC platforms, but it comes at the cost of greater subslice
4038 * imbalance for primitives of dimensions approximately intermediate
4039 * between 16x4 and 16x16.
4042 /* Finest subslice hashing mode available. */
4045 /* Dimensions of the smallest hashing block of a given hashing mode. If
4046 * the rendering area is smaller than this there can't possibly be any
4047 * benefit from switching to this mode, so we optimize out the
4050 const unsigned min_size
[][2] = {
4054 const unsigned idx
= scale
> 1;
4056 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4057 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4060 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4061 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4062 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4063 .SubsliceHashing
= subslice_hashing
[idx
],
4064 .SubsliceHashingMask
= -1);
4066 cmd_buffer
->state
.pending_pipe_bits
|=
4067 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4068 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4070 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4072 cmd_buffer
->state
.current_hash_scale
= scale
;
4078 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4080 struct anv_device
*device
= cmd_buffer
->device
;
4081 const struct anv_image_view
*iview
=
4082 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4083 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4085 /* FIXME: Width and Height are wrong */
4087 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4089 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4090 device
->isl_dev
.ds
.size
/ 4);
4094 struct isl_depth_stencil_hiz_emit_info info
= { };
4097 info
.view
= &iview
->planes
[0].isl
;
4099 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4100 uint32_t depth_plane
=
4101 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4102 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4104 info
.depth_surf
= &surface
->isl
;
4106 info
.depth_address
=
4107 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4108 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4109 image
->planes
[depth_plane
].address
.bo
,
4110 image
->planes
[depth_plane
].address
.offset
+
4113 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4116 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4117 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4118 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4119 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4122 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4123 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4124 image
->planes
[depth_plane
].address
.bo
,
4125 image
->planes
[depth_plane
].address
.offset
+
4126 image
->planes
[depth_plane
].aux_surface
.offset
);
4128 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4132 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4133 uint32_t stencil_plane
=
4134 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4135 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4137 info
.stencil_surf
= &surface
->isl
;
4139 info
.stencil_address
=
4140 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4141 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4142 image
->planes
[stencil_plane
].address
.bo
,
4143 image
->planes
[stencil_plane
].address
.offset
+
4146 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4149 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4151 if (GEN_GEN
>= 12) {
4152 /* GEN:BUG:1408224581
4154 * Workaround: Gen12LP Astep only An additional pipe control with
4155 * post-sync = store dword operation would be required.( w/a is to
4156 * have an additional pipe control after the stencil state whenever
4157 * the surface state bits of this state is changing).
4159 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4160 pc
.PostSyncOperation
= WriteImmediateData
;
4162 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4165 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4169 * This ANDs the view mask of the current subpass with the pending clear
4170 * views in the attachment to get the mask of views active in the subpass
4171 * that still need to be cleared.
4173 static inline uint32_t
4174 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4175 const struct anv_attachment_state
*att_state
)
4177 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4181 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4182 const struct anv_attachment_state
*att_state
)
4184 if (!cmd_state
->subpass
->view_mask
)
4187 uint32_t pending_clear_mask
=
4188 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4190 return pending_clear_mask
& 1;
4194 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4197 const uint32_t last_subpass_idx
=
4198 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4199 const struct anv_subpass
*last_subpass
=
4200 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4201 return last_subpass
== cmd_state
->subpass
;
4205 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4206 uint32_t subpass_id
)
4208 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4209 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4210 cmd_state
->subpass
= subpass
;
4212 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4214 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4215 * different views. If the client asks for instancing, we need to use the
4216 * Instance Data Step Rate to ensure that we repeat the client's
4217 * per-instance data once for each view. Since this bit is in
4218 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4222 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4224 /* It is possible to start a render pass with an old pipeline. Because the
4225 * render pass and subpass index are both baked into the pipeline, this is
4226 * highly unlikely. In order to do so, it requires that you have a render
4227 * pass with a single subpass and that you use that render pass twice
4228 * back-to-back and use the same pipeline at the start of the second render
4229 * pass as at the end of the first. In order to avoid unpredictable issues
4230 * with this edge case, we just dirty the pipeline at the start of every
4233 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4235 /* Accumulate any subpass flushes that need to happen before the subpass */
4236 cmd_buffer
->state
.pending_pipe_bits
|=
4237 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4239 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4240 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4242 bool is_multiview
= subpass
->view_mask
!= 0;
4244 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4245 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4246 if (a
== VK_ATTACHMENT_UNUSED
)
4249 assert(a
< cmd_state
->pass
->attachment_count
);
4250 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4252 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4253 const struct anv_image
*image
= iview
->image
;
4255 /* A resolve is necessary before use as an input attachment if the clear
4256 * color or auxiliary buffer usage isn't supported by the sampler.
4258 const bool input_needs_resolve
=
4259 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4260 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4262 VkImageLayout target_layout
, target_stencil_layout
;
4263 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4264 !input_needs_resolve
) {
4265 /* Layout transitions before the final only help to enable sampling
4266 * as an input attachment. If the input attachment supports sampling
4267 * using the auxiliary surface, we can skip such transitions by
4268 * making the target layout one that is CCS-aware.
4270 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4272 target_layout
= subpass
->attachments
[i
].layout
;
4273 target_stencil_layout
= subpass
->attachments
[i
].stencil_layout
;
4276 uint32_t base_layer
, layer_count
;
4277 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4279 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4280 iview
->planes
[0].isl
.base_level
);
4282 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4283 layer_count
= fb
->layers
;
4286 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4287 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4288 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4289 iview
->planes
[0].isl
.base_level
, 1,
4290 base_layer
, layer_count
,
4291 att_state
->current_layout
, target_layout
);
4294 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4295 transition_depth_buffer(cmd_buffer
, image
,
4296 att_state
->current_layout
, target_layout
);
4297 att_state
->aux_usage
=
4298 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4299 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4302 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4303 transition_stencil_buffer(cmd_buffer
, image
,
4304 iview
->planes
[0].isl
.base_level
, 1,
4305 base_layer
, layer_count
,
4306 att_state
->current_stencil_layout
,
4307 target_stencil_layout
);
4309 att_state
->current_layout
= target_layout
;
4310 att_state
->current_stencil_layout
= target_stencil_layout
;
4312 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4313 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4315 /* Multi-planar images are not supported as attachments */
4316 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4317 assert(image
->n_planes
== 1);
4319 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4320 uint32_t clear_layer_count
= fb
->layers
;
4322 if (att_state
->fast_clear
&&
4323 do_first_layer_clear(cmd_state
, att_state
)) {
4324 /* We only support fast-clears on the first layer */
4325 assert(iview
->planes
[0].isl
.base_level
== 0);
4326 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4328 union isl_color_value clear_color
= {};
4329 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4330 if (iview
->image
->samples
== 1) {
4331 anv_image_ccs_op(cmd_buffer
, image
,
4332 iview
->planes
[0].isl
.format
,
4333 VK_IMAGE_ASPECT_COLOR_BIT
,
4334 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4338 anv_image_mcs_op(cmd_buffer
, image
,
4339 iview
->planes
[0].isl
.format
,
4340 VK_IMAGE_ASPECT_COLOR_BIT
,
4341 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4346 clear_layer_count
--;
4348 att_state
->pending_clear_views
&= ~1;
4350 if (att_state
->clear_color_is_zero
) {
4351 /* This image has the auxiliary buffer enabled. We can mark the
4352 * subresource as not needing a resolve because the clear color
4353 * will match what's in every RENDER_SURFACE_STATE object when
4354 * it's being used for sampling.
4356 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4357 VK_IMAGE_ASPECT_COLOR_BIT
,
4358 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4360 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4361 VK_IMAGE_ASPECT_COLOR_BIT
,
4362 ANV_FAST_CLEAR_ANY
);
4366 /* From the VkFramebufferCreateInfo spec:
4368 * "If the render pass uses multiview, then layers must be one and each
4369 * attachment requires a number of layers that is greater than the
4370 * maximum bit index set in the view mask in the subpasses in which it
4373 * So if multiview is active we ignore the number of layers in the
4374 * framebuffer and instead we honor the view mask from the subpass.
4377 assert(image
->n_planes
== 1);
4378 uint32_t pending_clear_mask
=
4379 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4382 for_each_bit(layer_idx
, pending_clear_mask
) {
4384 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4386 anv_image_clear_color(cmd_buffer
, image
,
4387 VK_IMAGE_ASPECT_COLOR_BIT
,
4388 att_state
->aux_usage
,
4389 iview
->planes
[0].isl
.format
,
4390 iview
->planes
[0].isl
.swizzle
,
4391 iview
->planes
[0].isl
.base_level
,
4394 vk_to_isl_color(att_state
->clear_value
.color
));
4397 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4398 } else if (clear_layer_count
> 0) {
4399 assert(image
->n_planes
== 1);
4400 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4401 att_state
->aux_usage
,
4402 iview
->planes
[0].isl
.format
,
4403 iview
->planes
[0].isl
.swizzle
,
4404 iview
->planes
[0].isl
.base_level
,
4405 base_clear_layer
, clear_layer_count
,
4407 vk_to_isl_color(att_state
->clear_value
.color
));
4409 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4410 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4411 if (att_state
->fast_clear
&& !is_multiview
) {
4412 /* We currently only support HiZ for single-layer images */
4413 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4414 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4415 assert(iview
->planes
[0].isl
.base_level
== 0);
4416 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4417 assert(fb
->layers
== 1);
4420 anv_image_hiz_clear(cmd_buffer
, image
,
4421 att_state
->pending_clear_aspects
,
4422 iview
->planes
[0].isl
.base_level
,
4423 iview
->planes
[0].isl
.base_array_layer
,
4424 fb
->layers
, render_area
,
4425 att_state
->clear_value
.depthStencil
.stencil
);
4426 } else if (is_multiview
) {
4427 uint32_t pending_clear_mask
=
4428 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4431 for_each_bit(layer_idx
, pending_clear_mask
) {
4433 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4435 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4436 att_state
->pending_clear_aspects
,
4437 att_state
->aux_usage
,
4438 iview
->planes
[0].isl
.base_level
,
4441 att_state
->clear_value
.depthStencil
.depth
,
4442 att_state
->clear_value
.depthStencil
.stencil
);
4445 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4447 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4448 att_state
->pending_clear_aspects
,
4449 att_state
->aux_usage
,
4450 iview
->planes
[0].isl
.base_level
,
4451 iview
->planes
[0].isl
.base_array_layer
,
4452 fb
->layers
, render_area
,
4453 att_state
->clear_value
.depthStencil
.depth
,
4454 att_state
->clear_value
.depthStencil
.stencil
);
4457 assert(att_state
->pending_clear_aspects
== 0);
4461 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4462 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4463 iview
->planes
[0].isl
.base_level
== 0 &&
4464 iview
->planes
[0].isl
.base_array_layer
== 0) {
4465 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4466 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4467 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4468 false /* copy to ss */);
4471 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4472 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4473 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4474 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4475 false /* copy to ss */);
4479 if (subpass
->attachments
[i
].usage
==
4480 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4481 /* We assume that if we're starting a subpass, we're going to do some
4482 * rendering so we may end up with compressed data.
4484 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4485 VK_IMAGE_ASPECT_COLOR_BIT
,
4486 att_state
->aux_usage
,
4487 iview
->planes
[0].isl
.base_level
,
4488 iview
->planes
[0].isl
.base_array_layer
,
4490 } else if (subpass
->attachments
[i
].usage
==
4491 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4492 /* We may be writing depth or stencil so we need to mark the surface.
4493 * Unfortunately, there's no way to know at this point whether the
4494 * depth or stencil tests used will actually write to the surface.
4496 * Even though stencil may be plane 1, it always shares a base_level
4499 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4500 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4501 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4502 VK_IMAGE_ASPECT_DEPTH_BIT
,
4503 att_state
->aux_usage
,
4504 ds_view
->base_level
,
4505 ds_view
->base_array_layer
,
4508 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4509 /* Even though stencil may be plane 1, it always shares a
4510 * base_level with depth.
4512 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4513 VK_IMAGE_ASPECT_STENCIL_BIT
,
4515 ds_view
->base_level
,
4516 ds_view
->base_array_layer
,
4521 /* If multiview is enabled, then we are only done clearing when we no
4522 * longer have pending layers to clear, or when we have processed the
4523 * last subpass that uses this attachment.
4525 if (!is_multiview
||
4526 att_state
->pending_clear_views
== 0 ||
4527 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4528 att_state
->pending_clear_aspects
= 0;
4531 att_state
->pending_load_aspects
= 0;
4534 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4537 /* The PIPE_CONTROL command description says:
4539 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
4540 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
4541 * Target Cache Flush by enabling this bit. When render target flush
4542 * is set due to new association of BTI, PS Scoreboard Stall bit must
4543 * be set in this packet."
4545 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4546 pc
.RenderTargetCacheFlushEnable
= true;
4547 pc
.StallAtPixelScoreboard
= true;
4549 pc
.TileCacheFlushEnable
= true;
4555 static enum blorp_filter
4556 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4559 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4560 return BLORP_FILTER_SAMPLE_0
;
4561 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4562 return BLORP_FILTER_AVERAGE
;
4563 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4564 return BLORP_FILTER_MIN_SAMPLE
;
4565 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4566 return BLORP_FILTER_MAX_SAMPLE
;
4568 return BLORP_FILTER_NONE
;
4573 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4575 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4576 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4577 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4578 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4580 if (subpass
->has_color_resolve
) {
4581 /* We are about to do some MSAA resolves. We need to flush so that the
4582 * result of writes to the MSAA color attachments show up in the sampler
4583 * when we blit to the single-sampled resolve target.
4585 cmd_buffer
->state
.pending_pipe_bits
|=
4586 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4587 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4589 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4590 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4591 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4593 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4596 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4597 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4599 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4600 /* From the Vulkan 1.0 spec:
4602 * If the first use of an attachment in a render pass is as a
4603 * resolve attachment, then the loadOp is effectively ignored
4604 * as the resolve is guaranteed to overwrite all pixels in the
4607 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4610 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4611 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4613 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4615 enum isl_aux_usage src_aux_usage
=
4616 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4617 enum isl_aux_usage dst_aux_usage
=
4618 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4620 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4621 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4623 anv_image_msaa_resolve(cmd_buffer
,
4624 src_iview
->image
, src_aux_usage
,
4625 src_iview
->planes
[0].isl
.base_level
,
4626 src_iview
->planes
[0].isl
.base_array_layer
,
4627 dst_iview
->image
, dst_aux_usage
,
4628 dst_iview
->planes
[0].isl
.base_level
,
4629 dst_iview
->planes
[0].isl
.base_array_layer
,
4630 VK_IMAGE_ASPECT_COLOR_BIT
,
4631 render_area
.offset
.x
, render_area
.offset
.y
,
4632 render_area
.offset
.x
, render_area
.offset
.y
,
4633 render_area
.extent
.width
,
4634 render_area
.extent
.height
,
4635 fb
->layers
, BLORP_FILTER_NONE
);
4639 if (subpass
->ds_resolve_attachment
) {
4640 /* We are about to do some MSAA resolves. We need to flush so that the
4641 * result of writes to the MSAA depth attachments show up in the sampler
4642 * when we blit to the single-sampled resolve target.
4644 cmd_buffer
->state
.pending_pipe_bits
|=
4645 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4646 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4648 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4649 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4651 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4652 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4654 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4655 /* From the Vulkan 1.0 spec:
4657 * If the first use of an attachment in a render pass is as a
4658 * resolve attachment, then the loadOp is effectively ignored
4659 * as the resolve is guaranteed to overwrite all pixels in the
4662 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4665 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
4666 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
4668 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4670 struct anv_attachment_state
*src_state
=
4671 &cmd_state
->attachments
[src_att
];
4672 struct anv_attachment_state
*dst_state
=
4673 &cmd_state
->attachments
[dst_att
];
4675 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4676 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4678 /* MSAA resolves sample from the source attachment. Transition the
4679 * depth attachment first to get rid of any HiZ that we may not be
4682 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4683 src_state
->current_layout
,
4684 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4685 src_state
->aux_usage
=
4686 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4687 VK_IMAGE_ASPECT_DEPTH_BIT
,
4688 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4689 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4691 /* MSAA resolves write to the resolve attachment as if it were any
4692 * other transfer op. Transition the resolve attachment accordingly.
4694 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4696 /* If our render area is the entire size of the image, we're going to
4697 * blow it all away so we can claim the initial layout is UNDEFINED
4698 * and we'll get a HiZ ambiguate instead of a resolve.
4700 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4701 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4702 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4703 render_area
.extent
.height
== dst_iview
->extent
.height
)
4704 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4706 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4708 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4709 dst_state
->aux_usage
=
4710 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4711 VK_IMAGE_ASPECT_DEPTH_BIT
,
4712 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4713 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4715 enum blorp_filter filter
=
4716 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4718 anv_image_msaa_resolve(cmd_buffer
,
4719 src_iview
->image
, src_state
->aux_usage
,
4720 src_iview
->planes
[0].isl
.base_level
,
4721 src_iview
->planes
[0].isl
.base_array_layer
,
4722 dst_iview
->image
, dst_state
->aux_usage
,
4723 dst_iview
->planes
[0].isl
.base_level
,
4724 dst_iview
->planes
[0].isl
.base_array_layer
,
4725 VK_IMAGE_ASPECT_DEPTH_BIT
,
4726 render_area
.offset
.x
, render_area
.offset
.y
,
4727 render_area
.offset
.x
, render_area
.offset
.y
,
4728 render_area
.extent
.width
,
4729 render_area
.extent
.height
,
4730 fb
->layers
, filter
);
4733 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4734 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4736 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4737 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4739 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4740 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4742 enum blorp_filter filter
=
4743 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4745 anv_image_msaa_resolve(cmd_buffer
,
4746 src_iview
->image
, src_aux_usage
,
4747 src_iview
->planes
[0].isl
.base_level
,
4748 src_iview
->planes
[0].isl
.base_array_layer
,
4749 dst_iview
->image
, dst_aux_usage
,
4750 dst_iview
->planes
[0].isl
.base_level
,
4751 dst_iview
->planes
[0].isl
.base_array_layer
,
4752 VK_IMAGE_ASPECT_STENCIL_BIT
,
4753 render_area
.offset
.x
, render_area
.offset
.y
,
4754 render_area
.offset
.x
, render_area
.offset
.y
,
4755 render_area
.extent
.width
,
4756 render_area
.extent
.height
,
4757 fb
->layers
, filter
);
4762 /* On gen7, we have to store a texturable version of the stencil buffer in
4763 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
4764 * forth at strategic points. Stencil writes are only allowed in following
4767 * - VK_IMAGE_LAYOUT_GENERAL
4768 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
4769 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
4770 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
4771 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
4773 * For general, we have no nice opportunity to transition so we do the copy
4774 * to the shadow unconditionally at the end of the subpass. For transfer
4775 * destinations, we can update it as part of the transfer op. For the other
4776 * layouts, we delay the copy until a transition into some other layout.
4778 if (subpass
->depth_stencil_attachment
) {
4779 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
4780 assert(a
!= VK_ATTACHMENT_UNUSED
);
4782 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4783 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
4784 const struct anv_image
*image
= iview
->image
;
4786 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4787 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
4788 VK_IMAGE_ASPECT_STENCIL_BIT
);
4790 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
4791 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
4792 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
4793 anv_image_copy_to_shadow(cmd_buffer
, image
,
4794 VK_IMAGE_ASPECT_STENCIL_BIT
,
4795 iview
->planes
[plane
].isl
.base_level
, 1,
4796 iview
->planes
[plane
].isl
.base_array_layer
,
4801 #endif /* GEN_GEN == 7 */
4803 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4804 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4805 if (a
== VK_ATTACHMENT_UNUSED
)
4808 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4811 assert(a
< cmd_state
->pass
->attachment_count
);
4812 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4813 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4814 const struct anv_image
*image
= iview
->image
;
4816 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4817 image
->vk_format
!= iview
->vk_format
) {
4818 enum anv_fast_clear_type fast_clear_type
=
4819 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4820 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4821 att_state
->current_layout
);
4823 /* If any clear color was used, flush it down the aux surfaces. If we
4824 * don't do it now using the view's format we might use the clear
4825 * color incorrectly in the following resolves (for example with an
4826 * SRGB view & a UNORM image).
4828 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4829 anv_perf_warn(cmd_buffer
->device
->instance
, iview
,
4830 "Doing a partial resolve to get rid of clear color at the "
4831 "end of a renderpass due to an image/view format mismatch");
4833 uint32_t base_layer
, layer_count
;
4834 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4836 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4837 iview
->planes
[0].isl
.base_level
);
4839 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4840 layer_count
= fb
->layers
;
4843 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4844 uint32_t array_layer
= base_layer
+ a
;
4845 if (image
->samples
== 1) {
4846 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4847 iview
->planes
[0].isl
.format
,
4848 VK_IMAGE_ASPECT_COLOR_BIT
,
4849 iview
->planes
[0].isl
.base_level
,
4851 ISL_AUX_OP_PARTIAL_RESOLVE
,
4852 ANV_FAST_CLEAR_NONE
);
4854 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4855 iview
->planes
[0].isl
.format
,
4856 VK_IMAGE_ASPECT_COLOR_BIT
,
4858 ISL_AUX_OP_PARTIAL_RESOLVE
,
4859 ANV_FAST_CLEAR_NONE
);
4865 /* Transition the image into the final layout for this render pass */
4866 VkImageLayout target_layout
=
4867 cmd_state
->pass
->attachments
[a
].final_layout
;
4868 VkImageLayout target_stencil_layout
=
4869 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
4871 uint32_t base_layer
, layer_count
;
4872 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4874 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4875 iview
->planes
[0].isl
.base_level
);
4877 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4878 layer_count
= fb
->layers
;
4881 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4882 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4883 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4884 iview
->planes
[0].isl
.base_level
, 1,
4885 base_layer
, layer_count
,
4886 att_state
->current_layout
, target_layout
);
4889 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4890 transition_depth_buffer(cmd_buffer
, image
,
4891 att_state
->current_layout
, target_layout
);
4894 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4895 transition_stencil_buffer(cmd_buffer
, image
,
4896 iview
->planes
[0].isl
.base_level
, 1,
4897 base_layer
, layer_count
,
4898 att_state
->current_stencil_layout
,
4899 target_stencil_layout
);
4903 /* Accumulate any subpass flushes that need to happen after the subpass.
4904 * Yes, they do get accumulated twice in the NextSubpass case but since
4905 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4906 * ORing the bits in twice so it's harmless.
4908 cmd_buffer
->state
.pending_pipe_bits
|=
4909 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4912 void genX(CmdBeginRenderPass
)(
4913 VkCommandBuffer commandBuffer
,
4914 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4915 VkSubpassContents contents
)
4917 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4918 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4919 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4921 cmd_buffer
->state
.framebuffer
= framebuffer
;
4922 cmd_buffer
->state
.pass
= pass
;
4923 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4925 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4927 /* If we failed to setup the attachments we should not try to go further */
4928 if (result
!= VK_SUCCESS
) {
4929 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4933 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4935 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4938 void genX(CmdBeginRenderPass2KHR
)(
4939 VkCommandBuffer commandBuffer
,
4940 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4941 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4943 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4944 pSubpassBeginInfo
->contents
);
4947 void genX(CmdNextSubpass
)(
4948 VkCommandBuffer commandBuffer
,
4949 VkSubpassContents contents
)
4951 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4953 if (anv_batch_has_error(&cmd_buffer
->batch
))
4956 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4958 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4959 cmd_buffer_end_subpass(cmd_buffer
);
4960 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4963 void genX(CmdNextSubpass2KHR
)(
4964 VkCommandBuffer commandBuffer
,
4965 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4966 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4968 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4971 void genX(CmdEndRenderPass
)(
4972 VkCommandBuffer commandBuffer
)
4974 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4976 if (anv_batch_has_error(&cmd_buffer
->batch
))
4979 cmd_buffer_end_subpass(cmd_buffer
);
4981 cmd_buffer
->state
.hiz_enabled
= false;
4984 anv_dump_add_attachments(cmd_buffer
);
4987 /* Remove references to render pass specific state. This enables us to
4988 * detect whether or not we're in a renderpass.
4990 cmd_buffer
->state
.framebuffer
= NULL
;
4991 cmd_buffer
->state
.pass
= NULL
;
4992 cmd_buffer
->state
.subpass
= NULL
;
4995 void genX(CmdEndRenderPass2KHR
)(
4996 VkCommandBuffer commandBuffer
,
4997 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4999 genX(CmdEndRenderPass
)(commandBuffer
);
5003 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5005 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5006 struct gen_mi_builder b
;
5007 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5009 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5010 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5011 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5013 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5014 mip
.LoadOperation
= LOAD_LOADINV
;
5015 mip
.CombineOperation
= COMBINE_SET
;
5016 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5021 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5022 void genX(CmdBeginConditionalRenderingEXT
)(
5023 VkCommandBuffer commandBuffer
,
5024 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5026 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5027 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5028 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5029 struct anv_address value_address
=
5030 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5032 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5033 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5035 cmd_state
->conditional_render_enabled
= true;
5037 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5039 struct gen_mi_builder b
;
5040 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5042 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5044 * If the value of the predicate in buffer memory changes
5045 * while conditional rendering is active, the rendering commands
5046 * may be discarded in an implementation-dependent way.
5047 * Some implementations may latch the value of the predicate
5048 * upon beginning conditional rendering while others
5049 * may read it before every rendering command.
5051 * So it's perfectly fine to read a value from the buffer once.
5053 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5055 /* Precompute predicate result, it is necessary to support secondary
5056 * command buffers since it is unknown if conditional rendering is
5057 * inverted when populating them.
5059 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5060 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5061 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5064 void genX(CmdEndConditionalRenderingEXT
)(
5065 VkCommandBuffer commandBuffer
)
5067 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5068 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5070 cmd_state
->conditional_render_enabled
= false;
5074 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5075 * command streamer for later execution.
5077 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5078 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5079 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5080 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5081 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5082 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5083 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5084 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5085 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5086 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5087 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5088 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5089 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5090 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5091 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5093 void genX(CmdSetEvent
)(
5094 VkCommandBuffer commandBuffer
,
5096 VkPipelineStageFlags stageMask
)
5098 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5099 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5101 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5102 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5103 pc
.StallAtPixelScoreboard
= true;
5104 pc
.CommandStreamerStallEnable
= true;
5107 pc
.DestinationAddressType
= DAT_PPGTT
,
5108 pc
.PostSyncOperation
= WriteImmediateData
,
5109 pc
.Address
= (struct anv_address
) {
5110 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5113 pc
.ImmediateData
= VK_EVENT_SET
;
5117 void genX(CmdResetEvent
)(
5118 VkCommandBuffer commandBuffer
,
5120 VkPipelineStageFlags stageMask
)
5122 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5123 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5125 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5126 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5127 pc
.StallAtPixelScoreboard
= true;
5128 pc
.CommandStreamerStallEnable
= true;
5131 pc
.DestinationAddressType
= DAT_PPGTT
;
5132 pc
.PostSyncOperation
= WriteImmediateData
;
5133 pc
.Address
= (struct anv_address
) {
5134 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5137 pc
.ImmediateData
= VK_EVENT_RESET
;
5141 void genX(CmdWaitEvents
)(
5142 VkCommandBuffer commandBuffer
,
5143 uint32_t eventCount
,
5144 const VkEvent
* pEvents
,
5145 VkPipelineStageFlags srcStageMask
,
5146 VkPipelineStageFlags destStageMask
,
5147 uint32_t memoryBarrierCount
,
5148 const VkMemoryBarrier
* pMemoryBarriers
,
5149 uint32_t bufferMemoryBarrierCount
,
5150 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5151 uint32_t imageMemoryBarrierCount
,
5152 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5155 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5157 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5158 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5160 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5161 sem
.WaitMode
= PollingMode
,
5162 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5163 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5164 sem
.SemaphoreAddress
= (struct anv_address
) {
5165 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5171 anv_finishme("Implement events on gen7");
5174 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5175 false, /* byRegion */
5176 memoryBarrierCount
, pMemoryBarriers
,
5177 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5178 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5181 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5182 VkCommandBuffer commandBuffer
,
5183 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5185 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5187 switch (pOverrideInfo
->type
) {
5188 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5192 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5193 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5194 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5195 ._3DRenderingInstructionDisableMask
= true,
5196 .MediaInstructionDisableMask
= true);
5197 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5199 anv_pack_struct(&dw
, GENX(INSTPM
),
5200 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5201 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5202 ._3DRenderingInstructionDisableMask
= true,
5203 .MediaInstructionDisableMask
= true);
5204 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5209 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5210 if (pOverrideInfo
->enable
) {
5211 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5212 cmd_buffer
->state
.pending_pipe_bits
|=
5213 ANV_PIPE_FLUSH_BITS
|
5214 ANV_PIPE_INVALIDATE_BITS
;
5215 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5220 unreachable("Invalid override");
5226 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5227 VkCommandBuffer commandBuffer
,
5228 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5230 /* TODO: Waiting on the register to write, might depend on generation. */