2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_l3_config.h"
33 #include "genxml/gen_macros.h"
34 #include "genxml/genX_pack.h"
36 /* We reserve GPR 14 and 15 for conditional rendering */
37 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
38 #define __gen_get_batch_dwords anv_batch_emit_dwords
39 #define __gen_address_offset anv_address_add
40 #include "common/gen_mi_builder.h"
43 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
45 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
46 lri
.RegisterOffset
= reg
;
52 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
54 struct anv_device
*device
= cmd_buffer
->device
;
56 /* If we are emitting a new state base address we probably need to re-emit
59 cmd_buffer
->state
.descriptors_dirty
|= ~0;
61 /* Emit a render target cache flush.
63 * This isn't documented anywhere in the PRM. However, it seems to be
64 * necessary prior to changing the surface state base adress. Without
65 * this, we get GPU hangs when using multi-level command buffers which
66 * clear depth, reset state base address, and then go render stuff.
68 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
69 pc
.DCFlushEnable
= true;
70 pc
.RenderTargetCacheFlushEnable
= true;
71 pc
.CommandStreamerStallEnable
= true;
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
75 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
76 sba
.GeneralStateMOCS
= GENX(MOCS
);
77 sba
.GeneralStateBaseAddressModifyEnable
= true;
79 sba
.SurfaceStateBaseAddress
=
80 anv_cmd_buffer_surface_base_address(cmd_buffer
);
81 sba
.SurfaceStateMOCS
= GENX(MOCS
);
82 sba
.SurfaceStateBaseAddressModifyEnable
= true;
84 sba
.DynamicStateBaseAddress
=
85 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
86 sba
.DynamicStateMOCS
= GENX(MOCS
);
87 sba
.DynamicStateBaseAddressModifyEnable
= true;
89 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
90 sba
.IndirectObjectMOCS
= GENX(MOCS
);
91 sba
.IndirectObjectBaseAddressModifyEnable
= true;
93 sba
.InstructionBaseAddress
=
94 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
95 sba
.InstructionMOCS
= GENX(MOCS
);
96 sba
.InstructionBaseAddressModifyEnable
= true;
99 /* Broadwell requires that we specify a buffer size for a bunch of
100 * these fields. However, since we will be growing the BO's live, we
101 * just set them all to the maximum.
103 sba
.GeneralStateBufferSize
= 0xfffff;
104 sba
.GeneralStateBufferSizeModifyEnable
= true;
105 sba
.DynamicStateBufferSize
= 0xfffff;
106 sba
.DynamicStateBufferSizeModifyEnable
= true;
107 sba
.IndirectObjectBufferSize
= 0xfffff;
108 sba
.IndirectObjectBufferSizeModifyEnable
= true;
109 sba
.InstructionBufferSize
= 0xfffff;
110 sba
.InstructionBuffersizeModifyEnable
= true;
113 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
114 sba
.BindlessSurfaceStateMOCS
= GENX(MOCS
);
115 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
116 sba
.BindlessSurfaceStateSize
= 0;
119 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
120 sba
.BindlessSamplerStateMOCS
= GENX(MOCS
);
121 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
122 sba
.BindlessSamplerStateBufferSize
= 0;
126 /* After re-setting the surface state base address, we have to do some
127 * cache flusing so that the sampler engine will pick up the new
128 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
129 * Shared Function > 3D Sampler > State > State Caching (page 96):
131 * Coherency with system memory in the state cache, like the texture
132 * cache is handled partially by software. It is expected that the
133 * command stream or shader will issue Cache Flush operation or
134 * Cache_Flush sampler message to ensure that the L1 cache remains
135 * coherent with system memory.
139 * Whenever the value of the Dynamic_State_Base_Addr,
140 * Surface_State_Base_Addr are altered, the L1 state cache must be
141 * invalidated to ensure the new surface or sampler state is fetched
142 * from system memory.
144 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
145 * which, according the PIPE_CONTROL instruction documentation in the
148 * Setting this bit is independent of any other bit in this packet.
149 * This bit controls the invalidation of the L1 and L2 state caches
150 * at the top of the pipe i.e. at the parsing time.
152 * Unfortunately, experimentation seems to indicate that state cache
153 * invalidation through a PIPE_CONTROL does nothing whatsoever in
154 * regards to surface state and binding tables. In stead, it seems that
155 * invalidating the texture cache is what is actually needed.
157 * XXX: As far as we have been able to determine through
158 * experimentation, shows that flush the texture cache appears to be
159 * sufficient. The theory here is that all of the sampling/rendering
160 * units cache the binding table in the texture cache. However, we have
161 * yet to be able to actually confirm this.
163 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
164 pc
.TextureCacheInvalidationEnable
= true;
165 pc
.ConstantCacheInvalidationEnable
= true;
166 pc
.StateCacheInvalidationEnable
= true;
171 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
172 struct anv_state state
, struct anv_address addr
)
174 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
177 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
178 state
.offset
+ isl_dev
->ss
.addr_offset
,
179 addr
.bo
, addr
.offset
);
180 if (result
!= VK_SUCCESS
)
181 anv_batch_set_error(&cmd_buffer
->batch
, result
);
185 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
186 struct anv_surface_state state
)
188 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
190 assert(!anv_address_is_null(state
.address
));
191 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
193 if (!anv_address_is_null(state
.aux_address
)) {
195 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
196 &cmd_buffer
->pool
->alloc
,
197 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
198 state
.aux_address
.bo
, state
.aux_address
.offset
);
199 if (result
!= VK_SUCCESS
)
200 anv_batch_set_error(&cmd_buffer
->batch
, result
);
203 if (!anv_address_is_null(state
.clear_address
)) {
205 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
206 &cmd_buffer
->pool
->alloc
,
208 isl_dev
->ss
.clear_color_state_offset
,
209 state
.clear_address
.bo
, state
.clear_address
.offset
);
210 if (result
!= VK_SUCCESS
)
211 anv_batch_set_error(&cmd_buffer
->batch
, result
);
216 color_attachment_compute_aux_usage(struct anv_device
* device
,
217 struct anv_cmd_state
* cmd_state
,
218 uint32_t att
, VkRect2D render_area
,
219 union isl_color_value
*fast_clear_color
)
221 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
222 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
224 assert(iview
->n_planes
== 1);
226 if (iview
->planes
[0].isl
.base_array_layer
>=
227 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
228 iview
->planes
[0].isl
.base_level
)) {
229 /* There is no aux buffer which corresponds to the level and layer(s)
232 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
233 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
234 att_state
->fast_clear
= false;
238 att_state
->aux_usage
=
239 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
240 VK_IMAGE_ASPECT_COLOR_BIT
,
241 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
243 /* If we don't have aux, then we should have returned early in the layer
244 * check above. If we got here, we must have something.
246 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
248 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
249 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
250 att_state
->input_aux_usage
= att_state
->aux_usage
;
252 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
254 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
255 * setting is only allowed if Surface Format supported for Fast
256 * Clear. In addition, if the surface is bound to the sampling
257 * engine, Surface Format must be supported for Render Target
258 * Compression for surfaces bound to the sampling engine."
260 * In other words, we can only sample from a fast-cleared image if it
261 * also supports color compression.
263 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
)) {
264 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
266 /* While fast-clear resolves and partial resolves are fairly cheap in the
267 * case where you render to most of the pixels, full resolves are not
268 * because they potentially involve reading and writing the entire
269 * framebuffer. If we can't texture with CCS_E, we should leave it off and
270 * limit ourselves to fast clears.
272 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
273 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
274 anv_perf_warn(device
->instance
, iview
->image
,
275 "Not temporarily enabling CCS_E.");
278 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
282 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
283 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
285 union isl_color_value clear_color
= {};
286 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
288 att_state
->clear_color_is_zero_one
=
289 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
290 att_state
->clear_color_is_zero
=
291 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
293 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
294 /* Start by getting the fast clear type. We use the first subpass
295 * layout here because we don't want to fast-clear if the first subpass
296 * to use the attachment can't handle fast-clears.
298 enum anv_fast_clear_type fast_clear_type
=
299 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
300 VK_IMAGE_ASPECT_COLOR_BIT
,
301 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
302 switch (fast_clear_type
) {
303 case ANV_FAST_CLEAR_NONE
:
304 att_state
->fast_clear
= false;
306 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
307 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
309 case ANV_FAST_CLEAR_ANY
:
310 att_state
->fast_clear
= true;
314 /* Potentially, we could do partial fast-clears but doing so has crazy
315 * alignment restrictions. It's easier to just restrict to full size
316 * fast clears for now.
318 if (render_area
.offset
.x
!= 0 ||
319 render_area
.offset
.y
!= 0 ||
320 render_area
.extent
.width
!= iview
->extent
.width
||
321 render_area
.extent
.height
!= iview
->extent
.height
)
322 att_state
->fast_clear
= false;
324 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
325 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
326 att_state
->fast_clear
= false;
328 /* We only allow fast clears to the first slice of an image (level 0,
329 * layer 0) and only for the entire slice. This guarantees us that, at
330 * any given time, there is only one clear color on any given image at
331 * any given time. At the time of our testing (Jan 17, 2018), there
332 * were no known applications which would benefit from fast-clearing
333 * more than just the first slice.
335 if (att_state
->fast_clear
&&
336 (iview
->planes
[0].isl
.base_level
> 0 ||
337 iview
->planes
[0].isl
.base_array_layer
> 0)) {
338 anv_perf_warn(device
->instance
, iview
->image
,
339 "Rendering with multi-lod or multi-layer framebuffer "
340 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
341 "baseArrayLayer > 0. Not fast clearing.");
342 att_state
->fast_clear
= false;
343 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
344 anv_perf_warn(device
->instance
, iview
->image
,
345 "Rendering to a multi-layer framebuffer with "
346 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
349 if (att_state
->fast_clear
)
350 *fast_clear_color
= clear_color
;
352 att_state
->fast_clear
= false;
357 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
358 struct anv_cmd_state
*cmd_state
,
359 uint32_t att
, VkRect2D render_area
)
361 struct anv_render_pass_attachment
*pass_att
=
362 &cmd_state
->pass
->attachments
[att
];
363 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
364 struct anv_image_view
*iview
= cmd_state
->framebuffer
->attachments
[att
];
366 /* These will be initialized after the first subpass transition. */
367 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
368 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
371 /* We don't do any HiZ or depth fast-clears on gen7 yet */
372 att_state
->fast_clear
= false;
376 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
377 /* If we're just clearing stencil, we can always HiZ clear */
378 att_state
->fast_clear
= true;
382 /* Default to false for now */
383 att_state
->fast_clear
= false;
385 /* We must have depth in order to have HiZ */
386 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
389 const enum isl_aux_usage first_subpass_aux_usage
=
390 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
391 VK_IMAGE_ASPECT_DEPTH_BIT
,
392 pass_att
->first_subpass_layout
);
393 if (first_subpass_aux_usage
!= ISL_AUX_USAGE_HIZ
)
396 if (!blorp_can_hiz_clear_depth(GEN_GEN
,
397 iview
->planes
[0].isl
.format
,
398 iview
->image
->samples
,
399 render_area
.offset
.x
,
400 render_area
.offset
.y
,
401 render_area
.offset
.x
+
402 render_area
.extent
.width
,
403 render_area
.offset
.y
+
404 render_area
.extent
.height
))
407 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
410 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
411 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
412 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
413 * only supports returning 0.0f. Gens prior to gen8 do not support this
419 /* If we got here, then we can fast clear */
420 att_state
->fast_clear
= true;
424 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
426 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
429 /* We only allocate input attachment states for color surfaces. Compression
430 * is not yet enabled for depth textures and stencil doesn't allow
431 * compression so we can just use the texture surface state from the view.
433 return vk_format_is_color(att
->format
);
436 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
437 * the initial layout is undefined, the HiZ buffer and depth buffer will
438 * represent the same data at the end of this operation.
441 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
442 const struct anv_image
*image
,
443 VkImageLayout initial_layout
,
444 VkImageLayout final_layout
)
446 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
447 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
448 VK_IMAGE_ASPECT_DEPTH_BIT
, initial_layout
);
449 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
450 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
451 VK_IMAGE_ASPECT_DEPTH_BIT
, final_layout
);
453 enum isl_aux_op hiz_op
;
454 if (hiz_enabled
&& !enable_hiz
) {
455 hiz_op
= ISL_AUX_OP_FULL_RESOLVE
;
456 } else if (!hiz_enabled
&& enable_hiz
) {
457 hiz_op
= ISL_AUX_OP_AMBIGUATE
;
459 assert(hiz_enabled
== enable_hiz
);
460 /* If the same buffer will be used, no resolves are necessary. */
461 hiz_op
= ISL_AUX_OP_NONE
;
464 if (hiz_op
!= ISL_AUX_OP_NONE
)
465 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
469 #define MI_PREDICATE_SRC0 0x2400
470 #define MI_PREDICATE_SRC1 0x2408
471 #define MI_PREDICATE_RESULT 0x2418
474 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
475 const struct anv_image
*image
,
476 VkImageAspectFlagBits aspect
,
478 uint32_t base_layer
, uint32_t layer_count
,
481 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
483 /* We only have compression tracking for CCS_E */
484 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
487 for (uint32_t a
= 0; a
< layer_count
; a
++) {
488 uint32_t layer
= base_layer
+ a
;
489 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
490 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
493 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
499 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
500 const struct anv_image
*image
,
501 VkImageAspectFlagBits aspect
,
502 enum anv_fast_clear_type fast_clear
)
504 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
505 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
507 sdi
.ImmediateData
= fast_clear
;
510 /* Whenever we have fast-clear, we consider that slice to be compressed.
511 * This makes building predicates much easier.
513 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
514 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
517 #if GEN_IS_HASWELL || GEN_GEN >= 8
518 static inline uint32_t
519 mi_alu(uint32_t opcode
, uint32_t operand1
, uint32_t operand2
)
521 struct GENX(MI_MATH_ALU_INSTRUCTION
) instr
= {
523 .Operand1
= operand1
,
524 .Operand2
= operand2
,
528 GENX(MI_MATH_ALU_INSTRUCTION_pack
)(NULL
, &dw
, &instr
);
534 /* This is only really practical on haswell and above because it requires
535 * MI math in order to get it correct.
537 #if GEN_GEN >= 8 || GEN_IS_HASWELL
539 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
540 const struct anv_image
*image
,
541 VkImageAspectFlagBits aspect
,
542 uint32_t level
, uint32_t array_layer
,
543 enum isl_aux_op resolve_op
,
544 enum anv_fast_clear_type fast_clear_supported
)
546 struct gen_mi_builder b
;
547 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
549 const struct gen_mi_value fast_clear_type
=
550 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
553 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
554 /* In this case, we're doing a full resolve which means we want the
555 * resolve to happen if any compression (including fast-clears) is
558 * In order to simplify the logic a bit, we make the assumption that,
559 * if the first slice has been fast-cleared, it is also marked as
560 * compressed. See also set_image_fast_clear_state.
562 const struct gen_mi_value compression_state
=
563 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
565 level
, array_layer
));
566 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
568 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
570 if (level
== 0 && array_layer
== 0) {
571 /* If the predicate is true, we want to write 0 to the fast clear type
572 * and, if it's false, leave it alone. We can do this by writing
574 * clear_type = clear_type & ~predicate;
576 struct gen_mi_value new_fast_clear_type
=
577 gen_mi_iand(&b
, fast_clear_type
,
578 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
579 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
581 } else if (level
== 0 && array_layer
== 0) {
582 /* In this case, we are doing a partial resolve to get rid of fast-clear
583 * colors. We don't care about the compression state but we do care
584 * about how much fast clear is allowed by the final layout.
586 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
587 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
589 /* We need to compute (fast_clear_supported < image->fast_clear) */
590 struct gen_mi_value pred
=
591 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
592 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
593 gen_mi_value_ref(&b
, pred
));
595 /* If the predicate is true, we want to write 0 to the fast clear type
596 * and, if it's false, leave it alone. We can do this by writing
598 * clear_type = clear_type & ~predicate;
600 struct gen_mi_value new_fast_clear_type
=
601 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
602 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
604 /* In this case, we're trying to do a partial resolve on a slice that
605 * doesn't have clear color. There's nothing to do.
607 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
611 /* Set src1 to 0 and use a != condition */
612 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
614 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
615 mip
.LoadOperation
= LOAD_LOADINV
;
616 mip
.CombineOperation
= COMBINE_SET
;
617 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
620 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
624 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
625 const struct anv_image
*image
,
626 VkImageAspectFlagBits aspect
,
627 uint32_t level
, uint32_t array_layer
,
628 enum isl_aux_op resolve_op
,
629 enum anv_fast_clear_type fast_clear_supported
)
631 struct gen_mi_builder b
;
632 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
634 struct gen_mi_value fast_clear_type_mem
=
635 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
638 /* This only works for partial resolves and only when the clear color is
639 * all or nothing. On the upside, this emits less command streamer code
640 * and works on Ivybridge and Bay Trail.
642 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
643 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
645 /* We don't support fast clears on anything other than the first slice. */
646 if (level
> 0 || array_layer
> 0)
649 /* On gen8, we don't have a concept of default clear colors because we
650 * can't sample from CCS surfaces. It's enough to just load the fast clear
651 * state into the predicate register.
653 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
654 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
655 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
658 mip
.LoadOperation
= LOAD_LOADINV
;
659 mip
.CombineOperation
= COMBINE_SET
;
660 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
663 #endif /* GEN_GEN <= 8 */
666 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
667 const struct anv_image
*image
,
668 enum isl_format format
,
669 VkImageAspectFlagBits aspect
,
670 uint32_t level
, uint32_t array_layer
,
671 enum isl_aux_op resolve_op
,
672 enum anv_fast_clear_type fast_clear_supported
)
674 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
677 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
678 aspect
, level
, array_layer
,
679 resolve_op
, fast_clear_supported
);
680 #else /* GEN_GEN <= 8 */
681 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
682 aspect
, level
, array_layer
,
683 resolve_op
, fast_clear_supported
);
686 /* CCS_D only supports full resolves and BLORP will assert on us if we try
687 * to do a partial resolve on a CCS_D surface.
689 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
690 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
691 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
693 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
694 array_layer
, 1, resolve_op
, NULL
, true);
698 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
699 const struct anv_image
*image
,
700 enum isl_format format
,
701 VkImageAspectFlagBits aspect
,
702 uint32_t array_layer
,
703 enum isl_aux_op resolve_op
,
704 enum anv_fast_clear_type fast_clear_supported
)
706 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
707 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
709 #if GEN_GEN >= 8 || GEN_IS_HASWELL
710 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
711 aspect
, 0, array_layer
,
712 resolve_op
, fast_clear_supported
);
714 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
715 array_layer
, 1, resolve_op
, NULL
, true);
717 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
722 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
723 const struct anv_image
*image
,
724 VkImageAspectFlagBits aspect
,
725 enum isl_aux_usage aux_usage
,
728 uint32_t layer_count
)
730 /* The aspect must be exactly one of the image aspects. */
731 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
733 /* The only compression types with more than just fast-clears are MCS,
734 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
735 * track the current fast-clear and compression state. This leaves us
736 * with just MCS and CCS_E.
738 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
739 aux_usage
!= ISL_AUX_USAGE_MCS
)
742 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
743 level
, base_layer
, layer_count
, true);
747 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
748 const struct anv_image
*image
,
749 VkImageAspectFlagBits aspect
)
751 assert(cmd_buffer
&& image
);
752 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
754 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
755 ANV_FAST_CLEAR_NONE
);
757 /* The fast clear value dword(s) will be copied into a surface state object.
758 * Ensure that the restrictions of the fields in the dword(s) are followed.
760 * CCS buffers on SKL+ can have any value set for the clear colors.
762 if (image
->samples
== 1 && GEN_GEN
>= 9)
765 /* Other combinations of auxiliary buffers and platforms require specific
766 * values in the clear value dword(s).
768 struct anv_address addr
=
769 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
772 for (unsigned i
= 0; i
< 4; i
++) {
773 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
775 sdi
.Address
.offset
+= i
* 4;
776 /* MCS buffers on SKL+ can only have 1/0 clear colors. */
777 assert(image
->samples
> 1);
778 sdi
.ImmediateData
= 0;
782 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
784 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
785 /* Pre-SKL, the dword containing the clear values also contains
786 * other fields, so we need to initialize those fields to match the
787 * values that would be in a color attachment.
789 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
790 ISL_CHANNEL_SELECT_GREEN
<< 22 |
791 ISL_CHANNEL_SELECT_BLUE
<< 19 |
792 ISL_CHANNEL_SELECT_ALPHA
<< 16;
793 } else if (GEN_GEN
== 7) {
794 /* On IVB, the dword containing the clear values also contains
795 * other fields that must be zero or can be zero.
797 sdi
.ImmediateData
= 0;
803 /* Copy the fast-clear value dword(s) between a surface state object and an
804 * image's fast clear state buffer.
807 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
808 struct anv_state surface_state
,
809 const struct anv_image
*image
,
810 VkImageAspectFlagBits aspect
,
811 bool copy_from_surface_state
)
813 assert(cmd_buffer
&& image
);
814 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
816 struct anv_address ss_clear_addr
= {
817 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
818 .offset
= surface_state
.offset
+
819 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
821 const struct anv_address entry_addr
=
822 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
823 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
826 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
827 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
828 * in-flight when they are issued even if the memory touched is not
829 * currently active for rendering. The weird bit is that it is not the
830 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
831 * rendering hangs such that the next stalling command after the
832 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
834 * It is unclear exactly why this hang occurs. Both MI commands come with
835 * warnings about the 3D pipeline but that doesn't seem to fully explain
836 * it. My (Jason's) best theory is that it has something to do with the
837 * fact that we're using a GPU state register as our temporary and that
838 * something with reading/writing it is causing problems.
840 * In order to work around this issue, we emit a PIPE_CONTROL with the
841 * command streamer stall bit set.
843 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
844 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
847 struct gen_mi_builder b
;
848 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
850 if (copy_from_surface_state
) {
851 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
853 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
855 /* Updating a surface state object may require that the state cache be
856 * invalidated. From the SKL PRM, Shared Functions -> State -> State
859 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
860 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
861 * modified [...], the L1 state cache must be invalidated to ensure
862 * the new surface or sampler state is fetched from system memory.
864 * In testing, SKL doesn't actually seem to need this, but HSW does.
866 cmd_buffer
->state
.pending_pipe_bits
|=
867 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
872 * @brief Transitions a color buffer from one layout to another.
874 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
877 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
878 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
879 * this represents the maximum layers to transition at each
880 * specified miplevel.
883 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
884 const struct anv_image
*image
,
885 VkImageAspectFlagBits aspect
,
886 const uint32_t base_level
, uint32_t level_count
,
887 uint32_t base_layer
, uint32_t layer_count
,
888 VkImageLayout initial_layout
,
889 VkImageLayout final_layout
)
891 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
892 /* Validate the inputs. */
894 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
895 /* These values aren't supported for simplicity's sake. */
896 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
897 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
898 /* Ensure the subresource range is valid. */
899 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
900 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
901 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
902 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
903 assert(last_level_num
<= image
->levels
);
904 /* The spec disallows these final layouts. */
905 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
906 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
908 /* No work is necessary if the layout stays the same or if this subresource
909 * range lacks auxiliary data.
911 if (initial_layout
== final_layout
)
914 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
916 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
917 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
918 /* This surface is a linear compressed image with a tiled shadow surface
919 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
920 * we need to ensure the shadow copy is up-to-date.
922 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
923 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
924 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
925 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
927 anv_image_copy_to_shadow(cmd_buffer
, image
,
928 base_level
, level_count
,
929 base_layer
, layer_count
);
932 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
935 assert(image
->tiling
== VK_IMAGE_TILING_OPTIMAL
);
937 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
938 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
939 /* A subresource in the undefined layout may have been aliased and
940 * populated with any arrangement of bits. Therefore, we must initialize
941 * the related aux buffer and clear buffer entry with desirable values.
942 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
943 * images with VK_IMAGE_TILING_OPTIMAL.
945 * Initialize the relevant clear buffer entries.
947 if (base_level
== 0 && base_layer
== 0)
948 init_fast_clear_color(cmd_buffer
, image
, aspect
);
950 /* Initialize the aux buffers to enable correct rendering. In order to
951 * ensure that things such as storage images work correctly, aux buffers
952 * need to be initialized to valid data.
954 * Having an aux buffer with invalid data is a problem for two reasons:
956 * 1) Having an invalid value in the buffer can confuse the hardware.
957 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
958 * invalid and leads to the hardware doing strange things. It
959 * doesn't hang as far as we can tell but rendering corruption can
962 * 2) If this transition is into the GENERAL layout and we then use the
963 * image as a storage image, then we must have the aux buffer in the
964 * pass-through state so that, if we then go to texture from the
965 * image, we get the results of our storage image writes and not the
966 * fast clear color or other random data.
968 * For CCS both of the problems above are real demonstrable issues. In
969 * that case, the only thing we can do is to perform an ambiguate to
970 * transition the aux surface into the pass-through state.
972 * For MCS, (2) is never an issue because we don't support multisampled
973 * storage images. In theory, issue (1) is a problem with MCS but we've
974 * never seen it in the wild. For 4x and 16x, all bit patters could, in
975 * theory, be interpreted as something but we don't know that all bit
976 * patterns are actually valid. For 2x and 8x, you could easily end up
977 * with the MCS referring to an invalid plane because not all bits of
978 * the MCS value are actually used. Even though we've never seen issues
979 * in the wild, it's best to play it safe and initialize the MCS. We
980 * can use a fast-clear for MCS because we only ever touch from render
981 * and texture (no image load store).
983 if (image
->samples
== 1) {
984 for (uint32_t l
= 0; l
< level_count
; l
++) {
985 const uint32_t level
= base_level
+ l
;
987 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
988 if (base_layer
>= aux_layers
)
989 break; /* We will only get fewer layers as level increases */
990 uint32_t level_layer_count
=
991 MIN2(layer_count
, aux_layers
- base_layer
);
993 anv_image_ccs_op(cmd_buffer
, image
,
994 image
->planes
[plane
].surface
.isl
.format
,
995 aspect
, level
, base_layer
, level_layer_count
,
996 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
998 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
999 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1000 level
, base_layer
, level_layer_count
,
1005 if (image
->samples
== 4 || image
->samples
== 16) {
1006 anv_perf_warn(cmd_buffer
->device
->instance
, image
,
1007 "Doing a potentially unnecessary fast-clear to "
1008 "define an MCS buffer.");
1011 assert(base_level
== 0 && level_count
== 1);
1012 anv_image_mcs_op(cmd_buffer
, image
,
1013 image
->planes
[plane
].surface
.isl
.format
,
1014 aspect
, base_layer
, layer_count
,
1015 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1020 const enum isl_aux_usage initial_aux_usage
=
1021 anv_layout_to_aux_usage(devinfo
, image
, aspect
, initial_layout
);
1022 const enum isl_aux_usage final_aux_usage
=
1023 anv_layout_to_aux_usage(devinfo
, image
, aspect
, final_layout
);
1025 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1026 * We can handle transitions between CCS_D/E to and from NONE. What we
1027 * don't yet handle is switching between CCS_E and CCS_D within a given
1028 * image. Doing so in a performant way requires more detailed aux state
1029 * tracking such as what is done in i965. For now, just assume that we
1030 * only have one type of compression.
1032 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1033 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1034 initial_aux_usage
== final_aux_usage
);
1036 /* If initial aux usage is NONE, there is nothing to resolve */
1037 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1040 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1042 /* If the initial layout supports more fast clear than the final layout
1043 * then we need at least a partial resolve.
1045 const enum anv_fast_clear_type initial_fast_clear
=
1046 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1047 const enum anv_fast_clear_type final_fast_clear
=
1048 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1049 if (final_fast_clear
< initial_fast_clear
)
1050 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1052 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1053 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1054 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1056 if (resolve_op
== ISL_AUX_OP_NONE
)
1059 /* Perform a resolve to synchronize data between the main and aux buffer.
1060 * Before we begin, we must satisfy the cache flushing requirement specified
1061 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1063 * Any transition from any value in {Clear, Render, Resolve} to a
1064 * different value in {Clear, Render, Resolve} requires end of pipe
1067 * We perform a flush of the write cache before and after the clear and
1068 * resolve operations to meet this requirement.
1070 * Unlike other drawing, fast clear operations are not properly
1071 * synchronized. The first PIPE_CONTROL here likely ensures that the
1072 * contents of the previous render or clear hit the render target before we
1073 * resolve and the second likely ensures that the resolve is complete before
1074 * we do any more rendering or clearing.
1076 cmd_buffer
->state
.pending_pipe_bits
|=
1077 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1079 for (uint32_t l
= 0; l
< level_count
; l
++) {
1080 uint32_t level
= base_level
+ l
;
1082 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1083 if (base_layer
>= aux_layers
)
1084 break; /* We will only get fewer layers as level increases */
1085 uint32_t level_layer_count
=
1086 MIN2(layer_count
, aux_layers
- base_layer
);
1088 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1089 uint32_t array_layer
= base_layer
+ a
;
1090 if (image
->samples
== 1) {
1091 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1092 image
->planes
[plane
].surface
.isl
.format
,
1093 aspect
, level
, array_layer
, resolve_op
,
1096 /* We only support fast-clear on the first layer so partial
1097 * resolves should not be used on other layers as they will use
1098 * the clear color stored in memory that is only valid for layer0.
1100 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1104 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1105 image
->planes
[plane
].surface
.isl
.format
,
1106 aspect
, array_layer
, resolve_op
,
1112 cmd_buffer
->state
.pending_pipe_bits
|=
1113 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_CS_STALL_BIT
;
1117 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1120 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1121 struct anv_render_pass
*pass
,
1122 const VkRenderPassBeginInfo
*begin
)
1124 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1125 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1127 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1129 if (pass
->attachment_count
> 0) {
1130 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1131 pass
->attachment_count
*
1132 sizeof(state
->attachments
[0]),
1133 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1134 if (state
->attachments
== NULL
) {
1135 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1136 return anv_batch_set_error(&cmd_buffer
->batch
,
1137 VK_ERROR_OUT_OF_HOST_MEMORY
);
1140 state
->attachments
= NULL
;
1143 /* Reserve one for the NULL state. */
1144 unsigned num_states
= 1;
1145 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1146 if (vk_format_is_color(pass
->attachments
[i
].format
))
1149 if (need_input_attachment_state(&pass
->attachments
[i
]))
1153 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1154 state
->render_pass_states
=
1155 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1156 num_states
* ss_stride
, isl_dev
->ss
.align
);
1158 struct anv_state next_state
= state
->render_pass_states
;
1159 next_state
.alloc_size
= isl_dev
->ss
.size
;
1161 state
->null_surface_state
= next_state
;
1162 next_state
.offset
+= ss_stride
;
1163 next_state
.map
+= ss_stride
;
1165 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1166 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1167 state
->attachments
[i
].color
.state
= next_state
;
1168 next_state
.offset
+= ss_stride
;
1169 next_state
.map
+= ss_stride
;
1172 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1173 state
->attachments
[i
].input
.state
= next_state
;
1174 next_state
.offset
+= ss_stride
;
1175 next_state
.map
+= ss_stride
;
1178 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1179 state
->render_pass_states
.alloc_size
);
1182 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
1183 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1185 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1186 isl_extent3d(framebuffer
->width
,
1187 framebuffer
->height
,
1188 framebuffer
->layers
));
1190 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1191 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1192 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1193 VkImageAspectFlags clear_aspects
= 0;
1194 VkImageAspectFlags load_aspects
= 0;
1196 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1197 /* color attachment */
1198 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1199 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1200 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1201 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1204 /* depthstencil attachment */
1205 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1206 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1207 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1208 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1209 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1212 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1213 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1214 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1215 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1216 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1221 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1222 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1223 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1225 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1227 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
1228 anv_assert(iview
->vk_format
== att
->format
);
1230 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1231 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1233 union isl_color_value clear_color
= { .u32
= { 0, } };
1234 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1235 anv_assert(iview
->n_planes
== 1);
1236 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1237 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1238 state
, i
, begin
->renderArea
,
1241 anv_image_fill_surface_state(cmd_buffer
->device
,
1243 VK_IMAGE_ASPECT_COLOR_BIT
,
1244 &iview
->planes
[0].isl
,
1245 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1246 state
->attachments
[i
].aux_usage
,
1249 &state
->attachments
[i
].color
,
1252 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1254 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1259 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1260 anv_image_fill_surface_state(cmd_buffer
->device
,
1262 VK_IMAGE_ASPECT_COLOR_BIT
,
1263 &iview
->planes
[0].isl
,
1264 ISL_SURF_USAGE_TEXTURE_BIT
,
1265 state
->attachments
[i
].input_aux_usage
,
1268 &state
->attachments
[i
].input
,
1271 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1280 genX(BeginCommandBuffer
)(
1281 VkCommandBuffer commandBuffer
,
1282 const VkCommandBufferBeginInfo
* pBeginInfo
)
1284 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1286 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1287 * command buffer's state. Otherwise, we must *reset* its state. In both
1288 * cases we reset it.
1290 * From the Vulkan 1.0 spec:
1292 * If a command buffer is in the executable state and the command buffer
1293 * was allocated from a command pool with the
1294 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1295 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1296 * as if vkResetCommandBuffer had been called with
1297 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1298 * the command buffer in the recording state.
1300 anv_cmd_buffer_reset(cmd_buffer
);
1302 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1304 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1305 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1307 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1309 /* We sometimes store vertex data in the dynamic state buffer for blorp
1310 * operations and our dynamic state stream may re-use data from previous
1311 * command buffers. In order to prevent stale cache data, we flush the VF
1312 * cache. We could do this on every blorp call but that's not really
1313 * needed as all of the data will get written by the CPU prior to the GPU
1314 * executing anything. The chances are fairly high that they will use
1315 * blorp at least once per primary command buffer so it shouldn't be
1318 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
)
1319 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1321 /* We send an "Indirect State Pointers Disable" packet at
1322 * EndCommandBuffer, so all push contant packets are ignored during a
1323 * context restore. Documentation says after that command, we need to
1324 * emit push constants again before any rendering operation. So we
1325 * flag them dirty here to make sure they get emitted.
1327 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1329 VkResult result
= VK_SUCCESS
;
1330 if (cmd_buffer
->usage_flags
&
1331 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1332 assert(pBeginInfo
->pInheritanceInfo
);
1333 cmd_buffer
->state
.pass
=
1334 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1335 cmd_buffer
->state
.subpass
=
1336 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1338 /* This is optional in the inheritance info. */
1339 cmd_buffer
->state
.framebuffer
=
1340 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1342 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1343 cmd_buffer
->state
.pass
, NULL
);
1345 /* Record that HiZ is enabled if we can. */
1346 if (cmd_buffer
->state
.framebuffer
) {
1347 const struct anv_image_view
* const iview
=
1348 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1351 VkImageLayout layout
=
1352 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1354 enum isl_aux_usage aux_usage
=
1355 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1356 VK_IMAGE_ASPECT_DEPTH_BIT
, layout
);
1358 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1362 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1365 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1366 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1367 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1368 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1370 /* If secondary buffer supports conditional rendering
1371 * we should emit commands as if conditional rendering is enabled.
1373 cmd_buffer
->state
.conditional_render_enabled
=
1374 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1381 /* From the PRM, Volume 2a:
1383 * "Indirect State Pointers Disable
1385 * At the completion of the post-sync operation associated with this pipe
1386 * control packet, the indirect state pointers in the hardware are
1387 * considered invalid; the indirect pointers are not saved in the context.
1388 * If any new indirect state commands are executed in the command stream
1389 * while the pipe control is pending, the new indirect state commands are
1392 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1393 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1394 * commands are only considered as Indirect State Pointers. Once ISP is
1395 * issued in a context, SW must initialize by programming push constant
1396 * commands for all the shaders (at least to zero length) before attempting
1397 * any rendering operation for the same context."
1399 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1400 * even though they point to a BO that has been already unreferenced at
1401 * the end of the previous batch buffer. This has been fine so far since
1402 * we are protected by these scratch page (every address not covered by
1403 * a BO should be pointing to the scratch page). But on CNL, it is
1404 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1407 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1408 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1409 * context restore, so the mentioned hang doesn't happen. However,
1410 * software must program push constant commands for all stages prior to
1411 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1413 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1414 * constants have been loaded into the EUs prior to disable the push constants
1415 * so that it doesn't hang a previous 3DPRIMITIVE.
1418 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1420 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1421 pc
.StallAtPixelScoreboard
= true;
1422 pc
.CommandStreamerStallEnable
= true;
1424 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1425 pc
.IndirectStatePointersDisable
= true;
1426 pc
.CommandStreamerStallEnable
= true;
1431 genX(EndCommandBuffer
)(
1432 VkCommandBuffer commandBuffer
)
1434 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1436 if (anv_batch_has_error(&cmd_buffer
->batch
))
1437 return cmd_buffer
->batch
.status
;
1439 /* We want every command buffer to start with the PMA fix in a known state,
1440 * so we disable it at the end of the command buffer.
1442 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1444 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1446 emit_isp_disable(cmd_buffer
);
1448 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1454 genX(CmdExecuteCommands
)(
1455 VkCommandBuffer commandBuffer
,
1456 uint32_t commandBufferCount
,
1457 const VkCommandBuffer
* pCmdBuffers
)
1459 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1461 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1463 if (anv_batch_has_error(&primary
->batch
))
1466 /* The secondary command buffers will assume that the PMA fix is disabled
1467 * when they begin executing. Make sure this is true.
1469 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1471 /* The secondary command buffer doesn't know which textures etc. have been
1472 * flushed prior to their execution. Apply those flushes now.
1474 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1476 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1477 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1479 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1480 assert(!anv_batch_has_error(&secondary
->batch
));
1482 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1483 if (secondary
->state
.conditional_render_enabled
) {
1484 if (!primary
->state
.conditional_render_enabled
) {
1485 /* Secondary buffer is constructed as if it will be executed
1486 * with conditional rendering, we should satisfy this dependency
1487 * regardless of conditional rendering being enabled in primary.
1489 struct gen_mi_builder b
;
1490 gen_mi_builder_init(&b
, &primary
->batch
);
1491 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1492 gen_mi_imm(UINT64_MAX
));
1497 if (secondary
->usage_flags
&
1498 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1499 /* If we're continuing a render pass from the primary, we need to
1500 * copy the surface states for the current subpass into the storage
1501 * we allocated for them in BeginCommandBuffer.
1503 struct anv_bo
*ss_bo
=
1504 primary
->device
->surface_state_pool
.block_pool
.bo
;
1505 struct anv_state src_state
= primary
->state
.render_pass_states
;
1506 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1507 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1509 genX(cmd_buffer_so_memcpy
)(primary
,
1510 (struct anv_address
) {
1512 .offset
= dst_state
.offset
,
1514 (struct anv_address
) {
1516 .offset
= src_state
.offset
,
1518 src_state
.alloc_size
);
1521 anv_cmd_buffer_add_secondary(primary
, secondary
);
1524 /* The secondary may have selected a different pipeline (3D or compute) and
1525 * may have changed the current L3$ configuration. Reset our tracking
1526 * variables to invalid values to ensure that we re-emit these in the case
1527 * where we do any draws or compute dispatches from the primary after the
1528 * secondary has returned.
1530 primary
->state
.current_pipeline
= UINT32_MAX
;
1531 primary
->state
.current_l3_config
= NULL
;
1533 /* Each of the secondary command buffers will use its own state base
1534 * address. We need to re-emit state base address for the primary after
1535 * all of the secondaries are done.
1537 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1540 genX(cmd_buffer_emit_state_base_address
)(primary
);
1543 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1544 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1545 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1548 * Program the hardware to use the specified L3 configuration.
1551 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1552 const struct gen_l3_config
*cfg
)
1555 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1558 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1559 intel_logd("L3 config transition: ");
1560 gen_dump_l3_config(cfg
, stderr
);
1563 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1565 /* According to the hardware docs, the L3 partitioning can only be changed
1566 * while the pipeline is completely drained and the caches are flushed,
1567 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1569 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1570 pc
.DCFlushEnable
= true;
1571 pc
.PostSyncOperation
= NoWrite
;
1572 pc
.CommandStreamerStallEnable
= true;
1575 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1576 * invalidation of the relevant caches. Note that because RO invalidation
1577 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1578 * command is processed by the CS) we cannot combine it with the previous
1579 * stalling flush as the hardware documentation suggests, because that
1580 * would cause the CS to stall on previous rendering *after* RO
1581 * invalidation and wouldn't prevent the RO caches from being polluted by
1582 * concurrent rendering before the stall completes. This intentionally
1583 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1584 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1585 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1586 * already guarantee that there is no concurrent GPGPU kernel execution
1587 * (see SKL HSD 2132585).
1589 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1590 pc
.TextureCacheInvalidationEnable
= true;
1591 pc
.ConstantCacheInvalidationEnable
= true;
1592 pc
.InstructionCacheInvalidateEnable
= true;
1593 pc
.StateCacheInvalidationEnable
= true;
1594 pc
.PostSyncOperation
= NoWrite
;
1597 /* Now send a third stalling flush to make sure that invalidation is
1598 * complete when the L3 configuration registers are modified.
1600 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1601 pc
.DCFlushEnable
= true;
1602 pc
.PostSyncOperation
= NoWrite
;
1603 pc
.CommandStreamerStallEnable
= true;
1608 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1611 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
1612 .SLMEnable
= has_slm
,
1614 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1615 * in L3CNTLREG register. The default setting of the bit is not the
1616 * desirable behavior.
1618 .ErrorDetectionBehaviorControl
= true,
1619 .UseFullWays
= true,
1621 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1622 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1623 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1624 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1626 /* Set up the L3 partitioning. */
1627 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
1631 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1632 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1633 cfg
->n
[GEN_L3P_ALL
];
1634 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1635 cfg
->n
[GEN_L3P_ALL
];
1636 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1637 cfg
->n
[GEN_L3P_ALL
];
1639 assert(!cfg
->n
[GEN_L3P_ALL
]);
1641 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1642 * the matching space on the remaining banks has to be allocated to a
1643 * client (URB for all validated configurations) set to the
1644 * lower-bandwidth 2-bank address hashing mode.
1646 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1647 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1648 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1650 /* Minimum number of ways that can be allocated to the URB. */
1651 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1652 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1654 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1655 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1656 .ConvertDC_UC
= !has_dc
,
1657 .ConvertIS_UC
= !has_is
,
1658 .ConvertC_UC
= !has_c
,
1659 .ConvertT_UC
= !has_t
);
1661 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1662 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1663 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1665 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1666 .SLMEnable
= has_slm
,
1667 .URBLowBandwidth
= urb_low_bw
,
1668 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1670 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1672 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1673 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1675 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1676 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1677 .ISLowBandwidth
= 0,
1678 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1680 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1681 .TLowBandwidth
= 0);
1683 /* Set up the L3 partitioning. */
1684 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1685 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1686 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1689 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
1690 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1691 * them disabled to avoid crashing the system hard.
1693 uint32_t scratch1
, chicken3
;
1694 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1695 .L3AtomicDisable
= !has_dc
);
1696 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1697 .L3AtomicDisableMask
= true,
1698 .L3AtomicDisable
= !has_dc
);
1699 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1700 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1706 cmd_buffer
->state
.current_l3_config
= cfg
;
1710 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1712 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1714 /* Flushes are pipelined while invalidations are handled immediately.
1715 * Therefore, if we're flushing anything then we need to schedule a stall
1716 * before any invalidations can happen.
1718 if (bits
& ANV_PIPE_FLUSH_BITS
)
1719 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
1721 /* If we're going to do an invalidate and we have a pending CS stall that
1722 * has yet to be resolved, we do the CS stall now.
1724 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
1725 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
1726 bits
|= ANV_PIPE_CS_STALL_BIT
;
1727 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
1730 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
1731 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1732 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
1733 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
1734 pipe
.RenderTargetCacheFlushEnable
=
1735 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
1737 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
1738 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
1739 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
1742 * According to the Broadwell documentation, any PIPE_CONTROL with the
1743 * "Command Streamer Stall" bit set must also have another bit set,
1744 * with five different options:
1746 * - Render Target Cache Flush
1747 * - Depth Cache Flush
1748 * - Stall at Pixel Scoreboard
1749 * - Post-Sync Operation
1753 * I chose "Stall at Pixel Scoreboard" since that's what we use in
1754 * mesa and it seems to work fine. The choice is fairly arbitrary.
1756 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
1757 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
1758 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
1759 pipe
.StallAtPixelScoreboard
= true;
1762 /* If a render target flush was emitted, then we can toggle off the bit
1763 * saying that render target writes are ongoing.
1765 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
1766 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
1768 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
1771 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
1772 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1774 * "If the VF Cache Invalidation Enable is set to a 1 in a
1775 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
1776 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
1777 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
1780 * This appears to hang Broadwell, so we restrict it to just gen9.
1782 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
1783 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
1785 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
1786 pipe
.StateCacheInvalidationEnable
=
1787 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1788 pipe
.ConstantCacheInvalidationEnable
=
1789 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1790 pipe
.VFCacheInvalidationEnable
=
1791 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1792 pipe
.TextureCacheInvalidationEnable
=
1793 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1794 pipe
.InstructionCacheInvalidateEnable
=
1795 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
1797 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
1799 * "When VF Cache Invalidate is set “Post Sync Operation” must be
1800 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
1801 * “Write Timestamp”.
1803 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
1804 pipe
.PostSyncOperation
= WriteImmediateData
;
1806 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1810 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
1813 cmd_buffer
->state
.pending_pipe_bits
= bits
;
1816 void genX(CmdPipelineBarrier
)(
1817 VkCommandBuffer commandBuffer
,
1818 VkPipelineStageFlags srcStageMask
,
1819 VkPipelineStageFlags destStageMask
,
1821 uint32_t memoryBarrierCount
,
1822 const VkMemoryBarrier
* pMemoryBarriers
,
1823 uint32_t bufferMemoryBarrierCount
,
1824 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
1825 uint32_t imageMemoryBarrierCount
,
1826 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
1828 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1830 /* XXX: Right now, we're really dumb and just flush whatever categories
1831 * the app asks for. One of these days we may make this a bit better
1832 * but right now that's all the hardware allows for in most areas.
1834 VkAccessFlags src_flags
= 0;
1835 VkAccessFlags dst_flags
= 0;
1837 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
1838 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
1839 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
1842 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
1843 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
1844 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
1847 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
1848 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
1849 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
1850 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
1851 const VkImageSubresourceRange
*range
=
1852 &pImageMemoryBarriers
[i
].subresourceRange
;
1854 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1855 transition_depth_buffer(cmd_buffer
, image
,
1856 pImageMemoryBarriers
[i
].oldLayout
,
1857 pImageMemoryBarriers
[i
].newLayout
);
1858 } else if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1859 VkImageAspectFlags color_aspects
=
1860 anv_image_expand_aspects(image
, range
->aspectMask
);
1861 uint32_t aspect_bit
;
1863 uint32_t base_layer
, layer_count
;
1864 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1866 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
1868 base_layer
= range
->baseArrayLayer
;
1869 layer_count
= anv_get_layerCount(image
, range
);
1872 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
1873 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
1874 range
->baseMipLevel
,
1875 anv_get_levelCount(image
, range
),
1876 base_layer
, layer_count
,
1877 pImageMemoryBarriers
[i
].oldLayout
,
1878 pImageMemoryBarriers
[i
].newLayout
);
1883 cmd_buffer
->state
.pending_pipe_bits
|=
1884 anv_pipe_flush_bits_for_access_flags(src_flags
) |
1885 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
1889 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1891 VkShaderStageFlags stages
=
1892 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
1894 /* In order to avoid thrash, we assume that vertex and fragment stages
1895 * always exist. In the rare case where one is missing *and* the other
1896 * uses push concstants, this may be suboptimal. However, avoiding stalls
1897 * seems more important.
1899 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1901 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1905 const unsigned push_constant_kb
= 32;
1906 #elif GEN_IS_HASWELL
1907 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1909 const unsigned push_constant_kb
= 16;
1912 const unsigned num_stages
=
1913 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1914 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1916 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1917 * units of 2KB. Incidentally, these are the same platforms that have
1918 * 32KB worth of push constant space.
1920 if (push_constant_kb
== 32)
1921 size_per_stage
&= ~1u;
1923 uint32_t kb_used
= 0;
1924 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1925 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1926 anv_batch_emit(&cmd_buffer
->batch
,
1927 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1928 alloc
._3DCommandSubOpcode
= 18 + i
;
1929 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1930 alloc
.ConstantBufferSize
= push_size
;
1932 kb_used
+= push_size
;
1935 anv_batch_emit(&cmd_buffer
->batch
,
1936 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1937 alloc
.ConstantBufferOffset
= kb_used
;
1938 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1941 cmd_buffer
->state
.push_constant_stages
= stages
;
1943 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1945 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1946 * the next 3DPRIMITIVE command after programming the
1947 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1949 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1950 * pipeline setup, we need to dirty push constants.
1952 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1955 static const struct anv_descriptor
*
1956 anv_descriptor_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1957 const struct anv_pipeline_binding
*binding
)
1959 assert(binding
->set
< MAX_SETS
);
1960 const struct anv_descriptor_set
*set
=
1961 pipe_state
->descriptors
[binding
->set
];
1962 const uint32_t offset
=
1963 set
->layout
->binding
[binding
->binding
].descriptor_index
;
1964 return &set
->descriptors
[offset
+ binding
->index
];
1968 dynamic_offset_for_binding(const struct anv_cmd_pipeline_state
*pipe_state
,
1969 const struct anv_pipeline_binding
*binding
)
1971 assert(binding
->set
< MAX_SETS
);
1972 const struct anv_descriptor_set
*set
=
1973 pipe_state
->descriptors
[binding
->set
];
1975 uint32_t dynamic_offset_idx
=
1976 pipe_state
->layout
->set
[binding
->set
].dynamic_offset_start
+
1977 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1980 return pipe_state
->dynamic_offsets
[dynamic_offset_idx
];
1983 static struct anv_address
1984 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
1985 struct anv_descriptor_set
*set
)
1988 /* This is a normal descriptor set */
1989 return (struct anv_address
) {
1990 .bo
= &set
->pool
->bo
,
1991 .offset
= set
->desc_mem
.offset
,
1994 /* This is a push descriptor set. We have to flag it as used on the GPU
1995 * so that the next time we push descriptors, we grab a new memory.
1997 struct anv_push_descriptor_set
*push_set
=
1998 (struct anv_push_descriptor_set
*)set
;
1999 push_set
->set_used_on_gpu
= true;
2001 return (struct anv_address
) {
2002 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2003 .offset
= set
->desc_mem
.offset
,
2009 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2010 gl_shader_stage stage
,
2011 struct anv_state
*bt_state
)
2013 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
2014 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2015 struct anv_cmd_pipeline_state
*pipe_state
;
2016 struct anv_pipeline
*pipeline
;
2017 uint32_t state_offset
;
2020 case MESA_SHADER_COMPUTE
:
2021 pipe_state
= &cmd_buffer
->state
.compute
.base
;
2024 pipe_state
= &cmd_buffer
->state
.gfx
.base
;
2027 pipeline
= pipe_state
->pipeline
;
2029 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2030 *bt_state
= (struct anv_state
) { 0, };
2034 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2035 if (map
->surface_count
== 0) {
2036 *bt_state
= (struct anv_state
) { 0, };
2040 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2043 uint32_t *bt_map
= bt_state
->map
;
2045 if (bt_state
->map
== NULL
)
2046 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2048 /* We only need to emit relocs if we're not using softpin. If we are using
2049 * softpin then we always keep all user-allocated memory objects resident.
2051 const bool need_client_mem_relocs
=
2052 !cmd_buffer
->device
->instance
->physicalDevice
.use_softpin
;
2054 /* We only use push constant space for images before gen9 */
2055 if (map
->image_param_count
> 0) {
2057 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
2058 if (result
!= VK_SUCCESS
)
2061 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
2065 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2066 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2068 struct anv_state surface_state
;
2070 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
2071 /* Color attachment binding */
2072 assert(stage
== MESA_SHADER_FRAGMENT
);
2073 assert(binding
->binding
== 0);
2074 if (binding
->index
< subpass
->color_count
) {
2075 const unsigned att
=
2076 subpass
->color_attachments
[binding
->index
].attachment
;
2078 /* From the Vulkan 1.0.46 spec:
2080 * "If any color or depth/stencil attachments are
2081 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2084 if (att
== VK_ATTACHMENT_UNUSED
) {
2085 surface_state
= cmd_buffer
->state
.null_surface_state
;
2087 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2090 surface_state
= cmd_buffer
->state
.null_surface_state
;
2093 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2095 } else if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2096 struct anv_state surface_state
=
2097 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2099 struct anv_address constant_data
= {
2100 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2101 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2103 unsigned constant_data_size
=
2104 pipeline
->shaders
[stage
]->constant_data_size
;
2106 const enum isl_format format
=
2107 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2108 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2109 surface_state
, format
,
2110 constant_data
, constant_data_size
, 1);
2112 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2113 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2115 } else if (binding
->set
== ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
) {
2116 /* This is always the first binding for compute shaders */
2117 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2118 if (!get_cs_prog_data(pipeline
)->uses_num_work_groups
)
2121 struct anv_state surface_state
=
2122 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2124 const enum isl_format format
=
2125 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2126 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2128 cmd_buffer
->state
.compute
.num_workgroups
,
2130 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2131 if (need_client_mem_relocs
) {
2132 add_surface_reloc(cmd_buffer
, surface_state
,
2133 cmd_buffer
->state
.compute
.num_workgroups
);
2136 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2137 /* This is a descriptor set buffer so the set index is actually
2138 * given by binding->binding. (Yes, that's confusing.)
2140 struct anv_descriptor_set
*set
=
2141 pipe_state
->descriptors
[binding
->binding
];
2142 assert(set
->desc_mem
.alloc_size
);
2143 assert(set
->desc_surface_state
.alloc_size
);
2144 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2145 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2146 anv_descriptor_set_address(cmd_buffer
, set
));
2150 const struct anv_descriptor
*desc
=
2151 anv_descriptor_for_binding(pipe_state
, binding
);
2153 switch (desc
->type
) {
2154 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2155 /* Nothing for us to do here */
2158 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2159 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2160 struct anv_surface_state sstate
=
2161 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2162 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2163 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2164 surface_state
= sstate
.state
;
2165 assert(surface_state
.alloc_size
);
2166 if (need_client_mem_relocs
)
2167 add_surface_state_relocs(cmd_buffer
, sstate
);
2170 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2171 assert(stage
== MESA_SHADER_FRAGMENT
);
2172 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2173 /* For depth and stencil input attachments, we treat it like any
2174 * old texture that a user may have bound.
2176 struct anv_surface_state sstate
=
2177 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2178 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2179 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2180 surface_state
= sstate
.state
;
2181 assert(surface_state
.alloc_size
);
2182 if (need_client_mem_relocs
)
2183 add_surface_state_relocs(cmd_buffer
, sstate
);
2185 /* For color input attachments, we create the surface state at
2186 * vkBeginRenderPass time so that we can include aux and clear
2187 * color information.
2189 assert(binding
->input_attachment_index
< subpass
->input_count
);
2190 const unsigned subpass_att
= binding
->input_attachment_index
;
2191 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2192 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2196 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2197 struct anv_surface_state sstate
= (binding
->write_only
)
2198 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2199 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2200 surface_state
= sstate
.state
;
2201 assert(surface_state
.alloc_size
);
2202 if (need_client_mem_relocs
)
2203 add_surface_state_relocs(cmd_buffer
, sstate
);
2204 if (devinfo
->gen
< 9) {
2205 /* We only need the image params on gen8 and earlier. No image
2206 * workarounds that require tiling information are required on
2209 assert(image
< MAX_GEN8_IMAGES
);
2210 struct brw_image_param
*image_param
=
2211 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2214 desc
->image_view
->planes
[binding
->plane
].storage_image_param
;
2219 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2220 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2221 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2222 surface_state
= desc
->buffer_view
->surface_state
;
2223 assert(surface_state
.alloc_size
);
2224 if (need_client_mem_relocs
) {
2225 add_surface_reloc(cmd_buffer
, surface_state
,
2226 desc
->buffer_view
->address
);
2230 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2231 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2232 /* Compute the offset within the buffer */
2233 uint32_t dynamic_offset
=
2234 dynamic_offset_for_binding(pipe_state
, binding
);
2235 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2236 /* Clamp to the buffer size */
2237 offset
= MIN2(offset
, desc
->buffer
->size
);
2238 /* Clamp the range to the buffer size */
2239 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2241 struct anv_address address
=
2242 anv_address_add(desc
->buffer
->address
, offset
);
2245 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2246 enum isl_format format
=
2247 anv_isl_format_for_descriptor_type(desc
->type
);
2249 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2250 format
, address
, range
, 1);
2251 if (need_client_mem_relocs
)
2252 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2256 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2257 surface_state
= (binding
->write_only
)
2258 ? desc
->buffer_view
->writeonly_storage_surface_state
2259 : desc
->buffer_view
->storage_surface_state
;
2260 assert(surface_state
.alloc_size
);
2261 if (need_client_mem_relocs
) {
2262 add_surface_reloc(cmd_buffer
, surface_state
,
2263 desc
->buffer_view
->address
);
2265 if (devinfo
->gen
< 9) {
2266 assert(image
< MAX_GEN8_IMAGES
);
2267 struct brw_image_param
*image_param
=
2268 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
2270 *image_param
= desc
->buffer_view
->storage_image_param
;
2275 assert(!"Invalid descriptor type");
2279 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2281 assert(image
== map
->image_param_count
);
2284 /* The PIPE_CONTROL command description says:
2286 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
2287 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
2288 * Target Cache Flush by enabling this bit. When render target flush
2289 * is set due to new association of BTI, PS Scoreboard Stall bit must
2290 * be set in this packet."
2292 * FINISHME: Currently we shuffle around the surface states in the binding
2293 * table based on if they are getting used or not. So, we've to do below
2294 * pipe control flush for every binding table upload. Make changes so
2295 * that we do it only when we modify render target surface states.
2297 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2298 pc
.RenderTargetCacheFlushEnable
= true;
2299 pc
.StallAtPixelScoreboard
= true;
2307 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2308 gl_shader_stage stage
,
2309 struct anv_state
*state
)
2311 struct anv_cmd_pipeline_state
*pipe_state
=
2312 stage
== MESA_SHADER_COMPUTE
? &cmd_buffer
->state
.compute
.base
:
2313 &cmd_buffer
->state
.gfx
.base
;
2314 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2316 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2317 *state
= (struct anv_state
) { 0, };
2321 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2322 if (map
->sampler_count
== 0) {
2323 *state
= (struct anv_state
) { 0, };
2327 uint32_t size
= map
->sampler_count
* 16;
2328 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2330 if (state
->map
== NULL
)
2331 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2333 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2334 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2335 const struct anv_descriptor
*desc
=
2336 anv_descriptor_for_binding(pipe_state
, binding
);
2338 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2339 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2342 struct anv_sampler
*sampler
= desc
->sampler
;
2344 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2345 * happens to be zero.
2347 if (sampler
== NULL
)
2350 memcpy(state
->map
+ (s
* 16),
2351 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2358 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
2360 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2362 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2363 pipeline
->active_stages
;
2365 VkResult result
= VK_SUCCESS
;
2366 anv_foreach_stage(s
, dirty
) {
2367 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2368 if (result
!= VK_SUCCESS
)
2370 result
= emit_binding_table(cmd_buffer
, s
,
2371 &cmd_buffer
->state
.binding_tables
[s
]);
2372 if (result
!= VK_SUCCESS
)
2376 if (result
!= VK_SUCCESS
) {
2377 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2379 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2380 if (result
!= VK_SUCCESS
)
2383 /* Re-emit state base addresses so we get the new surface state base
2384 * address before we start emitting binding tables etc.
2386 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2388 /* Re-emit all active binding tables */
2389 dirty
|= pipeline
->active_stages
;
2390 anv_foreach_stage(s
, dirty
) {
2391 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2392 if (result
!= VK_SUCCESS
) {
2393 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2396 result
= emit_binding_table(cmd_buffer
, s
,
2397 &cmd_buffer
->state
.binding_tables
[s
]);
2398 if (result
!= VK_SUCCESS
) {
2399 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2405 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2411 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2414 static const uint32_t sampler_state_opcodes
[] = {
2415 [MESA_SHADER_VERTEX
] = 43,
2416 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2417 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2418 [MESA_SHADER_GEOMETRY
] = 46,
2419 [MESA_SHADER_FRAGMENT
] = 47,
2420 [MESA_SHADER_COMPUTE
] = 0,
2423 static const uint32_t binding_table_opcodes
[] = {
2424 [MESA_SHADER_VERTEX
] = 38,
2425 [MESA_SHADER_TESS_CTRL
] = 39,
2426 [MESA_SHADER_TESS_EVAL
] = 40,
2427 [MESA_SHADER_GEOMETRY
] = 41,
2428 [MESA_SHADER_FRAGMENT
] = 42,
2429 [MESA_SHADER_COMPUTE
] = 0,
2432 anv_foreach_stage(s
, stages
) {
2433 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2434 assert(binding_table_opcodes
[s
] > 0);
2436 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2437 anv_batch_emit(&cmd_buffer
->batch
,
2438 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2439 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2440 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2444 /* Always emit binding table pointers if we're asked to, since on SKL
2445 * this is what flushes push constants. */
2446 anv_batch_emit(&cmd_buffer
->batch
,
2447 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2448 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2449 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2455 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
2456 VkShaderStageFlags dirty_stages
)
2458 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2459 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2461 static const uint32_t push_constant_opcodes
[] = {
2462 [MESA_SHADER_VERTEX
] = 21,
2463 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2464 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2465 [MESA_SHADER_GEOMETRY
] = 22,
2466 [MESA_SHADER_FRAGMENT
] = 23,
2467 [MESA_SHADER_COMPUTE
] = 0,
2470 VkShaderStageFlags flushed
= 0;
2472 anv_foreach_stage(stage
, dirty_stages
) {
2473 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2474 assert(push_constant_opcodes
[stage
] > 0);
2476 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2477 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2479 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2480 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2481 const struct brw_stage_prog_data
*prog_data
=
2482 pipeline
->shaders
[stage
]->prog_data
;
2483 const struct anv_pipeline_bind_map
*bind_map
=
2484 &pipeline
->shaders
[stage
]->bind_map
;
2486 /* The Skylake PRM contains the following restriction:
2488 * "The driver must ensure The following case does not occur
2489 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2490 * buffer 3 read length equal to zero committed followed by a
2491 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2494 * To avoid this, we program the buffers in the highest slots.
2495 * This way, slot 0 is only used if slot 3 is also used.
2499 for (int i
= 3; i
>= 0; i
--) {
2500 const struct brw_ubo_range
*range
= &prog_data
->ubo_ranges
[i
];
2501 if (range
->length
== 0)
2504 const unsigned surface
=
2505 prog_data
->binding_table
.ubo_start
+ range
->block
;
2507 assert(surface
<= bind_map
->surface_count
);
2508 const struct anv_pipeline_binding
*binding
=
2509 &bind_map
->surface_to_descriptor
[surface
];
2511 struct anv_address read_addr
;
2513 if (binding
->set
== ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
) {
2514 struct anv_address constant_data
= {
2515 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2516 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2518 unsigned constant_data_size
=
2519 pipeline
->shaders
[stage
]->constant_data_size
;
2521 read_len
= MIN2(range
->length
,
2522 DIV_ROUND_UP(constant_data_size
, 32) - range
->start
);
2523 read_addr
= anv_address_add(constant_data
,
2525 } else if (binding
->set
== ANV_DESCRIPTOR_SET_DESCRIPTORS
) {
2526 /* This is a descriptor set buffer so the set index is
2527 * actually given by binding->binding. (Yes, that's
2530 struct anv_descriptor_set
*set
=
2531 gfx_state
->base
.descriptors
[binding
->binding
];
2532 struct anv_address desc_buffer_addr
=
2533 anv_descriptor_set_address(cmd_buffer
, set
);
2534 const unsigned desc_buffer_size
= set
->desc_mem
.alloc_size
;
2536 read_len
= MIN2(range
->length
,
2537 DIV_ROUND_UP(desc_buffer_size
, 32) - range
->start
);
2538 read_addr
= anv_address_add(desc_buffer_addr
,
2541 const struct anv_descriptor
*desc
=
2542 anv_descriptor_for_binding(&gfx_state
->base
, binding
);
2544 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2545 read_len
= MIN2(range
->length
,
2546 DIV_ROUND_UP(desc
->buffer_view
->range
, 32) - range
->start
);
2547 read_addr
= anv_address_add(desc
->buffer_view
->address
,
2550 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2552 uint32_t dynamic_offset
=
2553 dynamic_offset_for_binding(&gfx_state
->base
, binding
);
2554 uint32_t buf_offset
=
2555 MIN2(desc
->offset
+ dynamic_offset
, desc
->buffer
->size
);
2556 uint32_t buf_range
=
2557 MIN2(desc
->range
, desc
->buffer
->size
- buf_offset
);
2559 read_len
= MIN2(range
->length
,
2560 DIV_ROUND_UP(buf_range
, 32) - range
->start
);
2561 read_addr
= anv_address_add(desc
->buffer
->address
,
2562 buf_offset
+ range
->start
* 32);
2567 c
.ConstantBody
.Buffer
[n
] = read_addr
;
2568 c
.ConstantBody
.ReadLength
[n
] = read_len
;
2573 struct anv_state state
=
2574 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2576 if (state
.alloc_size
> 0) {
2577 c
.ConstantBody
.Buffer
[n
] = (struct anv_address
) {
2578 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2579 .offset
= state
.offset
,
2581 c
.ConstantBody
.ReadLength
[n
] =
2582 DIV_ROUND_UP(state
.alloc_size
, 32);
2585 /* For Ivy Bridge, the push constants packets have a different
2586 * rule that would require us to iterate in the other direction
2587 * and possibly mess around with dynamic state base address.
2588 * Don't bother; just emit regular push constants at n = 0.
2590 struct anv_state state
=
2591 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2593 if (state
.alloc_size
> 0) {
2594 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
,
2595 c
.ConstantBody
.ReadLength
[0] =
2596 DIV_ROUND_UP(state
.alloc_size
, 32);
2602 flushed
|= mesa_to_vk_shader_stage(stage
);
2605 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
2609 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
2611 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2614 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
2615 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
2616 vb_emit
|= pipeline
->vb_used
;
2618 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
2620 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
2622 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2625 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
2626 const uint32_t num_dwords
= 1 + num_buffers
* 4;
2628 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
2629 GENX(3DSTATE_VERTEX_BUFFERS
));
2631 for_each_bit(vb
, vb_emit
) {
2632 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
2633 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
2635 struct GENX(VERTEX_BUFFER_STATE
) state
= {
2636 .VertexBufferIndex
= vb
,
2638 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
2640 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
2641 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
2644 .AddressModifyEnable
= true,
2645 .BufferPitch
= pipeline
->vb
[vb
].stride
,
2646 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
2649 .BufferSize
= buffer
->size
- offset
2651 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
2655 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
2660 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
2663 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
2664 /* We don't need any per-buffer dirty tracking because you're not
2665 * allowed to bind different XFB buffers while XFB is enabled.
2667 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
2668 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
2669 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
2670 sob
.SOBufferIndex
= idx
;
2672 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
2673 sob
.SOBufferEnable
= true;
2674 sob
.MOCS
= cmd_buffer
->device
->default_mocs
,
2675 sob
.StreamOffsetWriteEnable
= false;
2676 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
2678 /* Size is in DWords - 1 */
2679 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
2684 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
2686 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
2690 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
2691 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
2693 /* The exact descriptor layout is pulled from the pipeline, so we need
2694 * to re-emit binding tables on every pipeline change.
2696 cmd_buffer
->state
.descriptors_dirty
|= pipeline
->active_stages
;
2698 /* If the pipeline changed, we may need to re-allocate push constant
2701 cmd_buffer_alloc_push_constants(cmd_buffer
);
2705 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
2706 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
2707 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
2709 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
2710 * stall needs to be sent just prior to any 3DSTATE_VS,
2711 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
2712 * 3DSTATE_BINDING_TABLE_POINTER_VS,
2713 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
2714 * PIPE_CONTROL needs to be sent before any combination of VS
2715 * associated 3DSTATE."
2717 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2718 pc
.DepthStallEnable
= true;
2719 pc
.PostSyncOperation
= WriteImmediateData
;
2721 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
2726 /* Render targets live in the same binding table as fragment descriptors */
2727 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
2728 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
2730 /* We emit the binding tables and sampler tables first, then emit push
2731 * constants and then finally emit binding table and sampler table
2732 * pointers. It has to happen in this order, since emitting the binding
2733 * tables may change the push constants (in case of storage images). After
2734 * emitting push constants, on SKL+ we have to emit the corresponding
2735 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
2738 if (cmd_buffer
->state
.descriptors_dirty
)
2739 dirty
= flush_descriptor_sets(cmd_buffer
);
2741 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
2742 /* Because we're pushing UBOs, we have to push whenever either
2743 * descriptors or push constants is dirty.
2745 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
2746 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
2747 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
2751 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
2753 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
2754 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
2756 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
2757 ANV_CMD_DIRTY_PIPELINE
)) {
2758 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
2759 pipeline
->depth_clamp_enable
);
2762 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
2763 ANV_CMD_DIRTY_RENDER_TARGETS
))
2764 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
2766 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
2768 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
2772 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
2773 struct anv_address addr
,
2774 uint32_t size
, uint32_t index
)
2776 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
2777 GENX(3DSTATE_VERTEX_BUFFERS
));
2779 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
2780 &(struct GENX(VERTEX_BUFFER_STATE
)) {
2781 .VertexBufferIndex
= index
,
2782 .AddressModifyEnable
= true,
2784 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
),
2786 .BufferStartingAddress
= addr
,
2789 .BufferStartingAddress
= addr
,
2790 .EndAddress
= anv_address_add(addr
, size
),
2796 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
2797 struct anv_address addr
)
2799 emit_vertex_bo(cmd_buffer
, addr
, 8, ANV_SVGS_VB_INDEX
);
2803 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
2804 uint32_t base_vertex
, uint32_t base_instance
)
2806 struct anv_state id_state
=
2807 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
2809 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
2810 ((uint32_t *)id_state
.map
)[1] = base_instance
;
2812 struct anv_address addr
= {
2813 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2814 .offset
= id_state
.offset
,
2817 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
2821 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
2823 struct anv_state state
=
2824 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
2826 ((uint32_t *)state
.map
)[0] = draw_index
;
2828 struct anv_address addr
= {
2829 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2830 .offset
= state
.offset
,
2833 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
2837 VkCommandBuffer commandBuffer
,
2838 uint32_t vertexCount
,
2839 uint32_t instanceCount
,
2840 uint32_t firstVertex
,
2841 uint32_t firstInstance
)
2843 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2844 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2845 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2847 if (anv_batch_has_error(&cmd_buffer
->batch
))
2850 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2852 if (cmd_buffer
->state
.conditional_render_enabled
)
2853 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2855 if (vs_prog_data
->uses_firstvertex
||
2856 vs_prog_data
->uses_baseinstance
)
2857 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2858 if (vs_prog_data
->uses_drawid
)
2859 emit_draw_index(cmd_buffer
, 0);
2861 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2862 * different views. We need to multiply instanceCount by the view count.
2864 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2866 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2867 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2868 prim
.VertexAccessType
= SEQUENTIAL
;
2869 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2870 prim
.VertexCountPerInstance
= vertexCount
;
2871 prim
.StartVertexLocation
= firstVertex
;
2872 prim
.InstanceCount
= instanceCount
;
2873 prim
.StartInstanceLocation
= firstInstance
;
2874 prim
.BaseVertexLocation
= 0;
2878 void genX(CmdDrawIndexed
)(
2879 VkCommandBuffer commandBuffer
,
2880 uint32_t indexCount
,
2881 uint32_t instanceCount
,
2882 uint32_t firstIndex
,
2883 int32_t vertexOffset
,
2884 uint32_t firstInstance
)
2886 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2887 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2888 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2890 if (anv_batch_has_error(&cmd_buffer
->batch
))
2893 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2895 if (cmd_buffer
->state
.conditional_render_enabled
)
2896 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
2898 if (vs_prog_data
->uses_firstvertex
||
2899 vs_prog_data
->uses_baseinstance
)
2900 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
2901 if (vs_prog_data
->uses_drawid
)
2902 emit_draw_index(cmd_buffer
, 0);
2904 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2905 * different views. We need to multiply instanceCount by the view count.
2907 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2909 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2910 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
2911 prim
.VertexAccessType
= RANDOM
;
2912 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2913 prim
.VertexCountPerInstance
= indexCount
;
2914 prim
.StartVertexLocation
= firstIndex
;
2915 prim
.InstanceCount
= instanceCount
;
2916 prim
.StartInstanceLocation
= firstInstance
;
2917 prim
.BaseVertexLocation
= vertexOffset
;
2921 /* Auto-Draw / Indirect Registers */
2922 #define GEN7_3DPRIM_END_OFFSET 0x2420
2923 #define GEN7_3DPRIM_START_VERTEX 0x2430
2924 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
2925 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
2926 #define GEN7_3DPRIM_START_INSTANCE 0x243C
2927 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
2929 void genX(CmdDrawIndirectByteCountEXT
)(
2930 VkCommandBuffer commandBuffer
,
2931 uint32_t instanceCount
,
2932 uint32_t firstInstance
,
2933 VkBuffer counterBuffer
,
2934 VkDeviceSize counterBufferOffset
,
2935 uint32_t counterOffset
,
2936 uint32_t vertexStride
)
2938 #if GEN_IS_HASWELL || GEN_GEN >= 8
2939 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2940 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
2941 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
2942 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
2944 /* firstVertex is always zero for this draw function */
2945 const uint32_t firstVertex
= 0;
2947 if (anv_batch_has_error(&cmd_buffer
->batch
))
2950 genX(cmd_buffer_flush_state
)(cmd_buffer
);
2952 if (vs_prog_data
->uses_firstvertex
||
2953 vs_prog_data
->uses_baseinstance
)
2954 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
2955 if (vs_prog_data
->uses_drawid
)
2956 emit_draw_index(cmd_buffer
, 0);
2958 /* Our implementation of VK_KHR_multiview uses instancing to draw the
2959 * different views. We need to multiply instanceCount by the view count.
2961 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
2963 struct gen_mi_builder b
;
2964 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2965 struct gen_mi_value count
=
2966 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
2967 counterBufferOffset
));
2969 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
2970 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
2971 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
2973 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
2974 gen_mi_imm(firstVertex
));
2975 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
2976 gen_mi_imm(instanceCount
));
2977 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
2978 gen_mi_imm(firstInstance
));
2979 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
2981 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
2982 prim
.IndirectParameterEnable
= true;
2983 prim
.VertexAccessType
= SEQUENTIAL
;
2984 prim
.PrimitiveTopologyType
= pipeline
->topology
;
2986 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
2990 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
2991 struct anv_address addr
,
2994 struct gen_mi_builder b
;
2995 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
2997 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
2998 gen_mi_mem32(anv_address_add(addr
, 0)));
3000 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3001 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3002 if (view_count
> 1) {
3003 #if GEN_IS_HASWELL || GEN_GEN >= 8
3004 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3006 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3007 "MI_MATH is not supported on Ivy Bridge");
3010 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3012 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3013 gen_mi_mem32(anv_address_add(addr
, 8)));
3016 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3017 gen_mi_mem32(anv_address_add(addr
, 12)));
3018 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3019 gen_mi_mem32(anv_address_add(addr
, 16)));
3021 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3022 gen_mi_mem32(anv_address_add(addr
, 12)));
3023 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3027 void genX(CmdDrawIndirect
)(
3028 VkCommandBuffer commandBuffer
,
3030 VkDeviceSize offset
,
3034 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3035 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3036 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3037 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3039 if (anv_batch_has_error(&cmd_buffer
->batch
))
3042 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3044 if (cmd_buffer
->state
.conditional_render_enabled
)
3045 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3047 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3048 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3050 if (vs_prog_data
->uses_firstvertex
||
3051 vs_prog_data
->uses_baseinstance
)
3052 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3053 if (vs_prog_data
->uses_drawid
)
3054 emit_draw_index(cmd_buffer
, i
);
3056 load_indirect_parameters(cmd_buffer
, draw
, false);
3058 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3059 prim
.IndirectParameterEnable
= true;
3060 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3061 prim
.VertexAccessType
= SEQUENTIAL
;
3062 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3069 void genX(CmdDrawIndexedIndirect
)(
3070 VkCommandBuffer commandBuffer
,
3072 VkDeviceSize offset
,
3076 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3077 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3078 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3079 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3081 if (anv_batch_has_error(&cmd_buffer
->batch
))
3084 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3086 if (cmd_buffer
->state
.conditional_render_enabled
)
3087 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3089 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3090 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3092 /* TODO: We need to stomp base vertex to 0 somehow */
3093 if (vs_prog_data
->uses_firstvertex
||
3094 vs_prog_data
->uses_baseinstance
)
3095 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3096 if (vs_prog_data
->uses_drawid
)
3097 emit_draw_index(cmd_buffer
, i
);
3099 load_indirect_parameters(cmd_buffer
, draw
, true);
3101 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3102 prim
.IndirectParameterEnable
= true;
3103 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3104 prim
.VertexAccessType
= RANDOM
;
3105 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3112 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3115 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3116 struct anv_address count_address
,
3117 const bool conditional_render_enabled
)
3119 struct gen_mi_builder b
;
3120 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3122 if (conditional_render_enabled
) {
3123 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3124 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3125 gen_mi_mem32(count_address
));
3128 /* Upload the current draw count from the draw parameters buffer to
3129 * MI_PREDICATE_SRC0.
3131 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3132 gen_mi_mem32(count_address
));
3134 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3139 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3140 uint32_t draw_index
)
3142 struct gen_mi_builder b
;
3143 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3145 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3146 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3148 if (draw_index
== 0) {
3149 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3150 mip
.LoadOperation
= LOAD_LOADINV
;
3151 mip
.CombineOperation
= COMBINE_SET
;
3152 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3155 /* While draw_index < draw_count the predicate's result will be
3156 * (draw_index == draw_count) ^ TRUE = TRUE
3157 * When draw_index == draw_count the result is
3158 * (TRUE) ^ TRUE = FALSE
3159 * After this all results will be:
3160 * (FALSE) ^ FALSE = FALSE
3162 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3163 mip
.LoadOperation
= LOAD_LOAD
;
3164 mip
.CombineOperation
= COMBINE_XOR
;
3165 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3170 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3172 emit_draw_count_predicate_with_conditional_render(
3173 struct anv_cmd_buffer
*cmd_buffer
,
3174 uint32_t draw_index
)
3176 struct gen_mi_builder b
;
3177 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3179 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3180 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3181 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3184 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3186 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3187 * so we emit MI_PREDICATE to set it.
3190 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3191 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3193 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3194 mip
.LoadOperation
= LOAD_LOADINV
;
3195 mip
.CombineOperation
= COMBINE_SET
;
3196 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3202 void genX(CmdDrawIndirectCountKHR
)(
3203 VkCommandBuffer commandBuffer
,
3205 VkDeviceSize offset
,
3206 VkBuffer _countBuffer
,
3207 VkDeviceSize countBufferOffset
,
3208 uint32_t maxDrawCount
,
3211 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3212 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3213 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3214 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3215 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3216 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3218 if (anv_batch_has_error(&cmd_buffer
->batch
))
3221 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3223 struct anv_address count_address
=
3224 anv_address_add(count_buffer
->address
, countBufferOffset
);
3226 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3227 cmd_state
->conditional_render_enabled
);
3229 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3230 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3232 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3233 if (cmd_state
->conditional_render_enabled
) {
3234 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3236 emit_draw_count_predicate(cmd_buffer
, i
);
3239 emit_draw_count_predicate(cmd_buffer
, i
);
3242 if (vs_prog_data
->uses_firstvertex
||
3243 vs_prog_data
->uses_baseinstance
)
3244 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3245 if (vs_prog_data
->uses_drawid
)
3246 emit_draw_index(cmd_buffer
, i
);
3248 load_indirect_parameters(cmd_buffer
, draw
, false);
3250 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3251 prim
.IndirectParameterEnable
= true;
3252 prim
.PredicateEnable
= true;
3253 prim
.VertexAccessType
= SEQUENTIAL
;
3254 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3261 void genX(CmdDrawIndexedIndirectCountKHR
)(
3262 VkCommandBuffer commandBuffer
,
3264 VkDeviceSize offset
,
3265 VkBuffer _countBuffer
,
3266 VkDeviceSize countBufferOffset
,
3267 uint32_t maxDrawCount
,
3270 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3271 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3272 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3273 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3274 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3275 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3277 if (anv_batch_has_error(&cmd_buffer
->batch
))
3280 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3282 struct anv_address count_address
=
3283 anv_address_add(count_buffer
->address
, countBufferOffset
);
3285 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3286 cmd_state
->conditional_render_enabled
);
3288 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3289 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3291 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3292 if (cmd_state
->conditional_render_enabled
) {
3293 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3295 emit_draw_count_predicate(cmd_buffer
, i
);
3298 emit_draw_count_predicate(cmd_buffer
, i
);
3301 /* TODO: We need to stomp base vertex to 0 somehow */
3302 if (vs_prog_data
->uses_firstvertex
||
3303 vs_prog_data
->uses_baseinstance
)
3304 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3305 if (vs_prog_data
->uses_drawid
)
3306 emit_draw_index(cmd_buffer
, i
);
3308 load_indirect_parameters(cmd_buffer
, draw
, true);
3310 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3311 prim
.IndirectParameterEnable
= true;
3312 prim
.PredicateEnable
= true;
3313 prim
.VertexAccessType
= RANDOM
;
3314 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3321 void genX(CmdBeginTransformFeedbackEXT
)(
3322 VkCommandBuffer commandBuffer
,
3323 uint32_t firstCounterBuffer
,
3324 uint32_t counterBufferCount
,
3325 const VkBuffer
* pCounterBuffers
,
3326 const VkDeviceSize
* pCounterBufferOffsets
)
3328 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3330 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3331 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3332 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3334 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3336 * "Ssoftware must ensure that no HW stream output operations can be in
3337 * process or otherwise pending at the point that the MI_LOAD/STORE
3338 * commands are processed. This will likely require a pipeline flush."
3340 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3341 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3343 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3344 /* If we have a counter buffer, this is a resume so we need to load the
3345 * value into the streamout offset register. Otherwise, this is a begin
3346 * and we need to reset it to zero.
3348 if (pCounterBuffers
&&
3349 idx
>= firstCounterBuffer
&&
3350 idx
- firstCounterBuffer
< counterBufferCount
&&
3351 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3352 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3353 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3354 uint64_t offset
= pCounterBufferOffsets
?
3355 pCounterBufferOffsets
[cb_idx
] : 0;
3357 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3358 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3359 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3363 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3364 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3370 cmd_buffer
->state
.xfb_enabled
= true;
3371 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3374 void genX(CmdEndTransformFeedbackEXT
)(
3375 VkCommandBuffer commandBuffer
,
3376 uint32_t firstCounterBuffer
,
3377 uint32_t counterBufferCount
,
3378 const VkBuffer
* pCounterBuffers
,
3379 const VkDeviceSize
* pCounterBufferOffsets
)
3381 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3383 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3384 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3385 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3387 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3389 * "Ssoftware must ensure that no HW stream output operations can be in
3390 * process or otherwise pending at the point that the MI_LOAD/STORE
3391 * commands are processed. This will likely require a pipeline flush."
3393 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3394 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3396 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
3397 unsigned idx
= firstCounterBuffer
+ cb_idx
;
3399 /* If we have a counter buffer, this is a resume so we need to load the
3400 * value into the streamout offset register. Otherwise, this is a begin
3401 * and we need to reset it to zero.
3403 if (pCounterBuffers
&&
3404 cb_idx
< counterBufferCount
&&
3405 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
3406 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3407 uint64_t offset
= pCounterBufferOffsets
?
3408 pCounterBufferOffsets
[cb_idx
] : 0;
3410 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
3411 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3413 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3418 cmd_buffer
->state
.xfb_enabled
= false;
3419 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3423 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
3425 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3426 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
3429 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3430 if (result
!= VK_SUCCESS
) {
3431 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3433 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
3434 if (result
!= VK_SUCCESS
)
3437 /* Re-emit state base addresses so we get the new surface state base
3438 * address before we start emitting binding tables etc.
3440 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
3442 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
3443 if (result
!= VK_SUCCESS
) {
3444 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3449 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
3450 if (result
!= VK_SUCCESS
) {
3451 anv_batch_set_error(&cmd_buffer
->batch
, result
);
3455 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
3456 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
3457 .BindingTablePointer
= surfaces
.offset
,
3458 .SamplerStatePointer
= samplers
.offset
,
3460 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
3462 struct anv_state state
=
3463 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
3464 pipeline
->interface_descriptor_data
,
3465 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
3468 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
3469 anv_batch_emit(&cmd_buffer
->batch
,
3470 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
3471 mid
.InterfaceDescriptorTotalLength
= size
;
3472 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
3479 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3481 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3482 MAYBE_UNUSED VkResult result
;
3484 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
3486 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
3488 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
3490 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
3491 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
3493 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
3494 * the only bits that are changed are scoreboard related: Scoreboard
3495 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
3496 * these scoreboard related states, a MEDIA_STATE_FLUSH is
3499 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3500 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3502 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3505 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
3506 cmd_buffer
->state
.compute
.pipeline_dirty
) {
3507 /* FIXME: figure out descriptors for gen7 */
3508 result
= flush_compute_descriptor_set(cmd_buffer
);
3509 if (result
!= VK_SUCCESS
)
3512 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3515 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
3516 struct anv_state push_state
=
3517 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
3519 if (push_state
.alloc_size
) {
3520 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
3521 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
3522 curbe
.CURBEDataStartAddress
= push_state
.offset
;
3526 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
3529 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
3531 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3537 verify_cmd_parser(const struct anv_device
*device
,
3538 int required_version
,
3539 const char *function
)
3541 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
3542 return vk_errorf(device
->instance
, device
->instance
,
3543 VK_ERROR_FEATURE_NOT_PRESENT
,
3544 "cmd parser version %d is required for %s",
3545 required_version
, function
);
3554 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
3555 uint32_t baseGroupX
,
3556 uint32_t baseGroupY
,
3557 uint32_t baseGroupZ
)
3559 if (anv_batch_has_error(&cmd_buffer
->batch
))
3563 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, MESA_SHADER_COMPUTE
,
3564 base_work_group_id
);
3565 if (result
!= VK_SUCCESS
) {
3566 cmd_buffer
->batch
.status
= result
;
3570 struct anv_push_constants
*push
=
3571 cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
3572 if (push
->base_work_group_id
[0] != baseGroupX
||
3573 push
->base_work_group_id
[1] != baseGroupY
||
3574 push
->base_work_group_id
[2] != baseGroupZ
) {
3575 push
->base_work_group_id
[0] = baseGroupX
;
3576 push
->base_work_group_id
[1] = baseGroupY
;
3577 push
->base_work_group_id
[2] = baseGroupZ
;
3579 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
3583 void genX(CmdDispatch
)(
3584 VkCommandBuffer commandBuffer
,
3589 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
3592 void genX(CmdDispatchBase
)(
3593 VkCommandBuffer commandBuffer
,
3594 uint32_t baseGroupX
,
3595 uint32_t baseGroupY
,
3596 uint32_t baseGroupZ
,
3597 uint32_t groupCountX
,
3598 uint32_t groupCountY
,
3599 uint32_t groupCountZ
)
3601 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3602 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3603 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3605 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
3606 baseGroupY
, baseGroupZ
);
3608 if (anv_batch_has_error(&cmd_buffer
->batch
))
3611 if (prog_data
->uses_num_work_groups
) {
3612 struct anv_state state
=
3613 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
3614 uint32_t *sizes
= state
.map
;
3615 sizes
[0] = groupCountX
;
3616 sizes
[1] = groupCountY
;
3617 sizes
[2] = groupCountZ
;
3618 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
3619 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3620 .offset
= state
.offset
,
3624 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3626 if (cmd_buffer
->state
.conditional_render_enabled
)
3627 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3629 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
3630 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3631 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3632 ggw
.ThreadDepthCounterMaximum
= 0;
3633 ggw
.ThreadHeightCounterMaximum
= 0;
3634 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3635 ggw
.ThreadGroupIDXDimension
= groupCountX
;
3636 ggw
.ThreadGroupIDYDimension
= groupCountY
;
3637 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
3638 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3639 ggw
.BottomExecutionMask
= 0xffffffff;
3642 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3645 #define GPGPU_DISPATCHDIMX 0x2500
3646 #define GPGPU_DISPATCHDIMY 0x2504
3647 #define GPGPU_DISPATCHDIMZ 0x2508
3649 void genX(CmdDispatchIndirect
)(
3650 VkCommandBuffer commandBuffer
,
3652 VkDeviceSize offset
)
3654 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3655 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3656 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
3657 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
3658 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
3659 struct anv_batch
*batch
= &cmd_buffer
->batch
;
3661 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
3664 /* Linux 4.4 added command parser version 5 which allows the GPGPU
3665 * indirect dispatch registers to be written.
3667 if (verify_cmd_parser(cmd_buffer
->device
, 5,
3668 "vkCmdDispatchIndirect") != VK_SUCCESS
)
3672 if (prog_data
->uses_num_work_groups
)
3673 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
3675 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
3677 struct gen_mi_builder b
;
3678 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3680 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
3681 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
3682 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
3684 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
3685 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
3686 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
3689 /* predicate = (compute_dispatch_indirect_x_size == 0); */
3690 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
3691 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3692 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3693 mip
.LoadOperation
= LOAD_LOAD
;
3694 mip
.CombineOperation
= COMBINE_SET
;
3695 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3698 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
3699 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
3700 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3701 mip
.LoadOperation
= LOAD_LOAD
;
3702 mip
.CombineOperation
= COMBINE_OR
;
3703 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3706 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
3707 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
3708 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3709 mip
.LoadOperation
= LOAD_LOAD
;
3710 mip
.CombineOperation
= COMBINE_OR
;
3711 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3714 /* predicate = !predicate; */
3715 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3716 mip
.LoadOperation
= LOAD_LOADINV
;
3717 mip
.CombineOperation
= COMBINE_OR
;
3718 mip
.CompareOperation
= COMPARE_FALSE
;
3722 if (cmd_buffer
->state
.conditional_render_enabled
) {
3723 /* predicate &= !(conditional_rendering_predicate == 0); */
3724 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
3725 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
3726 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
3727 mip
.LoadOperation
= LOAD_LOADINV
;
3728 mip
.CombineOperation
= COMBINE_AND
;
3729 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3734 #else /* GEN_GEN > 7 */
3735 if (cmd_buffer
->state
.conditional_render_enabled
)
3736 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3739 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
3740 ggw
.IndirectParameterEnable
= true;
3741 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
3742 cmd_buffer
->state
.conditional_render_enabled
;
3743 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
3744 ggw
.ThreadDepthCounterMaximum
= 0;
3745 ggw
.ThreadHeightCounterMaximum
= 0;
3746 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
3747 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
3748 ggw
.BottomExecutionMask
= 0xffffffff;
3751 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
3755 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
3758 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
3760 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
3763 #if GEN_GEN >= 8 && GEN_GEN < 10
3764 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
3766 * Software must clear the COLOR_CALC_STATE Valid field in
3767 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
3768 * with Pipeline Select set to GPGPU.
3770 * The internal hardware docs recommend the same workaround for Gen9
3773 if (pipeline
== GPGPU
)
3774 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
3777 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
3778 * PIPELINE_SELECT [DevBWR+]":
3782 * Software must ensure all the write caches are flushed through a
3783 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
3784 * command to invalidate read only caches prior to programming
3785 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
3787 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3788 pc
.RenderTargetCacheFlushEnable
= true;
3789 pc
.DepthCacheFlushEnable
= true;
3790 pc
.DCFlushEnable
= true;
3791 pc
.PostSyncOperation
= NoWrite
;
3792 pc
.CommandStreamerStallEnable
= true;
3795 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3796 pc
.TextureCacheInvalidationEnable
= true;
3797 pc
.ConstantCacheInvalidationEnable
= true;
3798 pc
.StateCacheInvalidationEnable
= true;
3799 pc
.InstructionCacheInvalidateEnable
= true;
3800 pc
.PostSyncOperation
= NoWrite
;
3803 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
3807 ps
.PipelineSelection
= pipeline
;
3811 if (devinfo
->is_geminilake
) {
3814 * "This chicken bit works around a hardware issue with barrier logic
3815 * encountered when switching between GPGPU and 3D pipelines. To
3816 * workaround the issue, this mode bit should be set after a pipeline
3820 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
3822 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
3823 : GLK_BARRIER_MODE_3D_HULL
,
3824 .GLKBarrierModeMask
= 1);
3825 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
3829 cmd_buffer
->state
.current_pipeline
= pipeline
;
3833 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
3835 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
3839 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
3841 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
3845 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
3850 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
3852 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
3853 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
3854 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
3855 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
3856 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
3857 * Depth Flush Bit set, followed by another pipelined depth stall
3858 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
3859 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
3860 * via a preceding MI_FLUSH)."
3862 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3863 pipe
.DepthStallEnable
= true;
3865 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3866 pipe
.DepthCacheFlushEnable
= true;
3868 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
3869 pipe
.DepthStallEnable
= true;
3874 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
3876 struct anv_device
*device
= cmd_buffer
->device
;
3877 const struct anv_image_view
*iview
=
3878 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
3879 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
3881 /* FIXME: Width and Height are wrong */
3883 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
3885 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
3886 device
->isl_dev
.ds
.size
/ 4);
3890 struct isl_depth_stencil_hiz_emit_info info
= { };
3893 info
.view
= &iview
->planes
[0].isl
;
3895 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
3896 uint32_t depth_plane
=
3897 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
3898 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
3900 info
.depth_surf
= &surface
->isl
;
3902 info
.depth_address
=
3903 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3904 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
3905 image
->planes
[depth_plane
].address
.bo
,
3906 image
->planes
[depth_plane
].address
.offset
+
3909 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
3912 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
3913 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
3914 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
3915 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
3918 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3919 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
3920 image
->planes
[depth_plane
].address
.bo
,
3921 image
->planes
[depth_plane
].address
.offset
+
3922 image
->planes
[depth_plane
].aux_surface
.offset
);
3924 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
3928 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3929 uint32_t stencil_plane
=
3930 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
3931 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
3933 info
.stencil_surf
= &surface
->isl
;
3935 info
.stencil_address
=
3936 anv_batch_emit_reloc(&cmd_buffer
->batch
,
3937 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
3938 image
->planes
[stencil_plane
].address
.bo
,
3939 image
->planes
[stencil_plane
].address
.offset
+
3942 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
3945 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
3947 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
3951 * This ANDs the view mask of the current subpass with the pending clear
3952 * views in the attachment to get the mask of views active in the subpass
3953 * that still need to be cleared.
3955 static inline uint32_t
3956 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
3957 const struct anv_attachment_state
*att_state
)
3959 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
3963 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
3964 const struct anv_attachment_state
*att_state
)
3966 if (!cmd_state
->subpass
->view_mask
)
3969 uint32_t pending_clear_mask
=
3970 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
3972 return pending_clear_mask
& 1;
3976 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
3979 const uint32_t last_subpass_idx
=
3980 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
3981 const struct anv_subpass
*last_subpass
=
3982 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
3983 return last_subpass
== cmd_state
->subpass
;
3987 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
3988 uint32_t subpass_id
)
3990 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3991 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
3992 cmd_state
->subpass
= subpass
;
3994 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
3996 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3997 * different views. If the client asks for instancing, we need to use the
3998 * Instance Data Step Rate to ensure that we repeat the client's
3999 * per-instance data once for each view. Since this bit is in
4000 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4004 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4006 /* It is possible to start a render pass with an old pipeline. Because the
4007 * render pass and subpass index are both baked into the pipeline, this is
4008 * highly unlikely. In order to do so, it requires that you have a render
4009 * pass with a single subpass and that you use that render pass twice
4010 * back-to-back and use the same pipeline at the start of the second render
4011 * pass as at the end of the first. In order to avoid unpredictable issues
4012 * with this edge case, we just dirty the pipeline at the start of every
4015 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4017 /* Accumulate any subpass flushes that need to happen before the subpass */
4018 cmd_buffer
->state
.pending_pipe_bits
|=
4019 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4021 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4022 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4024 bool is_multiview
= subpass
->view_mask
!= 0;
4026 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4027 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4028 if (a
== VK_ATTACHMENT_UNUSED
)
4031 assert(a
< cmd_state
->pass
->attachment_count
);
4032 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4034 struct anv_image_view
*iview
= fb
->attachments
[a
];
4035 const struct anv_image
*image
= iview
->image
;
4037 /* A resolve is necessary before use as an input attachment if the clear
4038 * color or auxiliary buffer usage isn't supported by the sampler.
4040 const bool input_needs_resolve
=
4041 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4042 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4044 VkImageLayout target_layout
;
4045 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4046 !input_needs_resolve
) {
4047 /* Layout transitions before the final only help to enable sampling
4048 * as an input attachment. If the input attachment supports sampling
4049 * using the auxiliary surface, we can skip such transitions by
4050 * making the target layout one that is CCS-aware.
4052 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4054 target_layout
= subpass
->attachments
[i
].layout
;
4057 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4058 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4060 uint32_t base_layer
, layer_count
;
4061 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4063 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4064 iview
->planes
[0].isl
.base_level
);
4066 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4067 layer_count
= fb
->layers
;
4070 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4071 iview
->planes
[0].isl
.base_level
, 1,
4072 base_layer
, layer_count
,
4073 att_state
->current_layout
, target_layout
);
4074 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4075 transition_depth_buffer(cmd_buffer
, image
,
4076 att_state
->current_layout
, target_layout
);
4077 att_state
->aux_usage
=
4078 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4079 VK_IMAGE_ASPECT_DEPTH_BIT
, target_layout
);
4081 att_state
->current_layout
= target_layout
;
4083 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4084 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4086 /* Multi-planar images are not supported as attachments */
4087 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4088 assert(image
->n_planes
== 1);
4090 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4091 uint32_t clear_layer_count
= fb
->layers
;
4093 if (att_state
->fast_clear
&&
4094 do_first_layer_clear(cmd_state
, att_state
)) {
4095 /* We only support fast-clears on the first layer */
4096 assert(iview
->planes
[0].isl
.base_level
== 0);
4097 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4099 union isl_color_value clear_color
= {};
4100 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4101 if (iview
->image
->samples
== 1) {
4102 anv_image_ccs_op(cmd_buffer
, image
,
4103 iview
->planes
[0].isl
.format
,
4104 VK_IMAGE_ASPECT_COLOR_BIT
,
4105 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4109 anv_image_mcs_op(cmd_buffer
, image
,
4110 iview
->planes
[0].isl
.format
,
4111 VK_IMAGE_ASPECT_COLOR_BIT
,
4112 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4117 clear_layer_count
--;
4119 att_state
->pending_clear_views
&= ~1;
4121 if (att_state
->clear_color_is_zero
) {
4122 /* This image has the auxiliary buffer enabled. We can mark the
4123 * subresource as not needing a resolve because the clear color
4124 * will match what's in every RENDER_SURFACE_STATE object when
4125 * it's being used for sampling.
4127 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4128 VK_IMAGE_ASPECT_COLOR_BIT
,
4129 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4131 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4132 VK_IMAGE_ASPECT_COLOR_BIT
,
4133 ANV_FAST_CLEAR_ANY
);
4137 /* From the VkFramebufferCreateInfo spec:
4139 * "If the render pass uses multiview, then layers must be one and each
4140 * attachment requires a number of layers that is greater than the
4141 * maximum bit index set in the view mask in the subpasses in which it
4144 * So if multiview is active we ignore the number of layers in the
4145 * framebuffer and instead we honor the view mask from the subpass.
4148 assert(image
->n_planes
== 1);
4149 uint32_t pending_clear_mask
=
4150 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4153 for_each_bit(layer_idx
, pending_clear_mask
) {
4155 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4157 anv_image_clear_color(cmd_buffer
, image
,
4158 VK_IMAGE_ASPECT_COLOR_BIT
,
4159 att_state
->aux_usage
,
4160 iview
->planes
[0].isl
.format
,
4161 iview
->planes
[0].isl
.swizzle
,
4162 iview
->planes
[0].isl
.base_level
,
4165 vk_to_isl_color(att_state
->clear_value
.color
));
4168 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4169 } else if (clear_layer_count
> 0) {
4170 assert(image
->n_planes
== 1);
4171 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4172 att_state
->aux_usage
,
4173 iview
->planes
[0].isl
.format
,
4174 iview
->planes
[0].isl
.swizzle
,
4175 iview
->planes
[0].isl
.base_level
,
4176 base_clear_layer
, clear_layer_count
,
4178 vk_to_isl_color(att_state
->clear_value
.color
));
4180 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
4181 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4182 if (att_state
->fast_clear
&& !is_multiview
) {
4183 /* We currently only support HiZ for single-layer images */
4184 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4185 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
4186 assert(iview
->planes
[0].isl
.base_level
== 0);
4187 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4188 assert(fb
->layers
== 1);
4191 anv_image_hiz_clear(cmd_buffer
, image
,
4192 att_state
->pending_clear_aspects
,
4193 iview
->planes
[0].isl
.base_level
,
4194 iview
->planes
[0].isl
.base_array_layer
,
4195 fb
->layers
, render_area
,
4196 att_state
->clear_value
.depthStencil
.stencil
);
4197 } else if (is_multiview
) {
4198 uint32_t pending_clear_mask
=
4199 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4202 for_each_bit(layer_idx
, pending_clear_mask
) {
4204 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
4206 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4207 att_state
->pending_clear_aspects
,
4208 att_state
->aux_usage
,
4209 iview
->planes
[0].isl
.base_level
,
4212 att_state
->clear_value
.depthStencil
.depth
,
4213 att_state
->clear_value
.depthStencil
.stencil
);
4216 att_state
->pending_clear_views
&= ~pending_clear_mask
;
4218 anv_image_clear_depth_stencil(cmd_buffer
, image
,
4219 att_state
->pending_clear_aspects
,
4220 att_state
->aux_usage
,
4221 iview
->planes
[0].isl
.base_level
,
4222 iview
->planes
[0].isl
.base_array_layer
,
4223 fb
->layers
, render_area
,
4224 att_state
->clear_value
.depthStencil
.depth
,
4225 att_state
->clear_value
.depthStencil
.stencil
);
4228 assert(att_state
->pending_clear_aspects
== 0);
4232 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4233 image
->planes
[0].aux_surface
.isl
.size_B
> 0 &&
4234 iview
->planes
[0].isl
.base_level
== 0 &&
4235 iview
->planes
[0].isl
.base_array_layer
== 0) {
4236 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
4237 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
4238 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4239 false /* copy to ss */);
4242 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
4243 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
4244 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
4245 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4246 false /* copy to ss */);
4250 if (subpass
->attachments
[i
].usage
==
4251 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
4252 /* We assume that if we're starting a subpass, we're going to do some
4253 * rendering so we may end up with compressed data.
4255 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
4256 VK_IMAGE_ASPECT_COLOR_BIT
,
4257 att_state
->aux_usage
,
4258 iview
->planes
[0].isl
.base_level
,
4259 iview
->planes
[0].isl
.base_array_layer
,
4261 } else if (subpass
->attachments
[i
].usage
==
4262 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
4263 /* We may be writing depth or stencil so we need to mark the surface.
4264 * Unfortunately, there's no way to know at this point whether the
4265 * depth or stencil tests used will actually write to the surface.
4267 * Even though stencil may be plane 1, it always shares a base_level
4270 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
4271 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4272 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4273 VK_IMAGE_ASPECT_DEPTH_BIT
,
4274 att_state
->aux_usage
,
4275 ds_view
->base_level
,
4276 ds_view
->base_array_layer
,
4279 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4280 /* Even though stencil may be plane 1, it always shares a
4281 * base_level with depth.
4283 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
4284 VK_IMAGE_ASPECT_STENCIL_BIT
,
4286 ds_view
->base_level
,
4287 ds_view
->base_array_layer
,
4292 /* If multiview is enabled, then we are only done clearing when we no
4293 * longer have pending layers to clear, or when we have processed the
4294 * last subpass that uses this attachment.
4296 if (!is_multiview
||
4297 att_state
->pending_clear_views
== 0 ||
4298 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
4299 att_state
->pending_clear_aspects
= 0;
4302 att_state
->pending_load_aspects
= 0;
4305 cmd_buffer_emit_depth_stencil(cmd_buffer
);
4308 static enum blorp_filter
4309 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
4312 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
4313 return BLORP_FILTER_SAMPLE_0
;
4314 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
4315 return BLORP_FILTER_AVERAGE
;
4316 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
4317 return BLORP_FILTER_MIN_SAMPLE
;
4318 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
4319 return BLORP_FILTER_MAX_SAMPLE
;
4321 return BLORP_FILTER_NONE
;
4326 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
4328 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4329 struct anv_subpass
*subpass
= cmd_state
->subpass
;
4330 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
4331 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4333 if (subpass
->has_color_resolve
) {
4334 /* We are about to do some MSAA resolves. We need to flush so that the
4335 * result of writes to the MSAA color attachments show up in the sampler
4336 * when we blit to the single-sampled resolve target.
4338 cmd_buffer
->state
.pending_pipe_bits
|=
4339 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4340 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
4342 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
4343 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
4344 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
4346 if (dst_att
== VK_ATTACHMENT_UNUSED
)
4349 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4350 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4352 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4353 /* From the Vulkan 1.0 spec:
4355 * If the first use of an attachment in a render pass is as a
4356 * resolve attachment, then the loadOp is effectively ignored
4357 * as the resolve is guaranteed to overwrite all pixels in the
4360 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4363 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4364 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4366 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4368 enum isl_aux_usage src_aux_usage
=
4369 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
4370 enum isl_aux_usage dst_aux_usage
=
4371 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
4373 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
4374 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
4376 anv_image_msaa_resolve(cmd_buffer
,
4377 src_iview
->image
, src_aux_usage
,
4378 src_iview
->planes
[0].isl
.base_level
,
4379 src_iview
->planes
[0].isl
.base_array_layer
,
4380 dst_iview
->image
, dst_aux_usage
,
4381 dst_iview
->planes
[0].isl
.base_level
,
4382 dst_iview
->planes
[0].isl
.base_array_layer
,
4383 VK_IMAGE_ASPECT_COLOR_BIT
,
4384 render_area
.offset
.x
, render_area
.offset
.y
,
4385 render_area
.offset
.x
, render_area
.offset
.y
,
4386 render_area
.extent
.width
,
4387 render_area
.extent
.height
,
4388 fb
->layers
, BLORP_FILTER_NONE
);
4392 if (subpass
->ds_resolve_attachment
) {
4393 /* We are about to do some MSAA resolves. We need to flush so that the
4394 * result of writes to the MSAA depth attachments show up in the sampler
4395 * when we blit to the single-sampled resolve target.
4397 cmd_buffer
->state
.pending_pipe_bits
|=
4398 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
4399 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
4401 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
4402 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
4404 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
4405 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
4407 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
4408 /* From the Vulkan 1.0 spec:
4410 * If the first use of an attachment in a render pass is as a
4411 * resolve attachment, then the loadOp is effectively ignored
4412 * as the resolve is guaranteed to overwrite all pixels in the
4415 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
4418 struct anv_image_view
*src_iview
= fb
->attachments
[src_att
];
4419 struct anv_image_view
*dst_iview
= fb
->attachments
[dst_att
];
4421 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4423 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
4424 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4426 struct anv_attachment_state
*src_state
=
4427 &cmd_state
->attachments
[src_att
];
4428 struct anv_attachment_state
*dst_state
=
4429 &cmd_state
->attachments
[dst_att
];
4431 /* MSAA resolves sample from the source attachment. Transition the
4432 * depth attachment first to get rid of any HiZ that we may not be
4435 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
4436 src_state
->current_layout
,
4437 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4438 src_state
->aux_usage
=
4439 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
4440 VK_IMAGE_ASPECT_DEPTH_BIT
,
4441 VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
);
4442 src_state
->current_layout
= VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
;
4444 /* MSAA resolves write to the resolve attachment as if it were any
4445 * other transfer op. Transition the resolve attachment accordingly.
4447 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
4449 /* If our render area is the entire size of the image, we're going to
4450 * blow it all away so we can claim the initial layout is UNDEFINED
4451 * and we'll get a HiZ ambiguate instead of a resolve.
4453 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
4454 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
4455 render_area
.extent
.width
== dst_iview
->extent
.width
&&
4456 render_area
.extent
.height
== dst_iview
->extent
.height
)
4457 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
4459 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
4461 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4462 dst_state
->aux_usage
=
4463 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
4464 VK_IMAGE_ASPECT_DEPTH_BIT
,
4465 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
4466 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
4468 enum blorp_filter filter
=
4469 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
4471 anv_image_msaa_resolve(cmd_buffer
,
4472 src_iview
->image
, src_state
->aux_usage
,
4473 src_iview
->planes
[0].isl
.base_level
,
4474 src_iview
->planes
[0].isl
.base_array_layer
,
4475 dst_iview
->image
, dst_state
->aux_usage
,
4476 dst_iview
->planes
[0].isl
.base_level
,
4477 dst_iview
->planes
[0].isl
.base_array_layer
,
4478 VK_IMAGE_ASPECT_DEPTH_BIT
,
4479 render_area
.offset
.x
, render_area
.offset
.y
,
4480 render_area
.offset
.x
, render_area
.offset
.y
,
4481 render_area
.extent
.width
,
4482 render_area
.extent
.height
,
4483 fb
->layers
, filter
);
4486 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
4487 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
4489 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
4490 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
4492 enum blorp_filter filter
=
4493 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
4495 anv_image_msaa_resolve(cmd_buffer
,
4496 src_iview
->image
, src_aux_usage
,
4497 src_iview
->planes
[0].isl
.base_level
,
4498 src_iview
->planes
[0].isl
.base_array_layer
,
4499 dst_iview
->image
, dst_aux_usage
,
4500 dst_iview
->planes
[0].isl
.base_level
,
4501 dst_iview
->planes
[0].isl
.base_array_layer
,
4502 VK_IMAGE_ASPECT_STENCIL_BIT
,
4503 render_area
.offset
.x
, render_area
.offset
.y
,
4504 render_area
.offset
.x
, render_area
.offset
.y
,
4505 render_area
.extent
.width
,
4506 render_area
.extent
.height
,
4507 fb
->layers
, filter
);
4511 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4512 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4513 if (a
== VK_ATTACHMENT_UNUSED
)
4516 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
4519 assert(a
< cmd_state
->pass
->attachment_count
);
4520 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4521 struct anv_image_view
*iview
= fb
->attachments
[a
];
4522 const struct anv_image
*image
= iview
->image
;
4524 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
4525 image
->vk_format
!= iview
->vk_format
) {
4526 enum anv_fast_clear_type fast_clear_type
=
4527 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
4528 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4529 att_state
->current_layout
);
4531 /* If any clear color was used, flush it down the aux surfaces. If we
4532 * don't do it now using the view's format we might use the clear
4533 * color incorrectly in the following resolves (for example with an
4534 * SRGB view & a UNORM image).
4536 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
4537 anv_perf_warn(cmd_buffer
->device
->instance
, fb
,
4538 "Doing a partial resolve to get rid of clear color at the "
4539 "end of a renderpass due to an image/view format mismatch");
4541 uint32_t base_layer
, layer_count
;
4542 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4544 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4545 iview
->planes
[0].isl
.base_level
);
4547 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4548 layer_count
= fb
->layers
;
4551 for (uint32_t a
= 0; a
< layer_count
; a
++) {
4552 uint32_t array_layer
= base_layer
+ a
;
4553 if (image
->samples
== 1) {
4554 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
4555 iview
->planes
[0].isl
.format
,
4556 VK_IMAGE_ASPECT_COLOR_BIT
,
4557 iview
->planes
[0].isl
.base_level
,
4559 ISL_AUX_OP_PARTIAL_RESOLVE
,
4560 ANV_FAST_CLEAR_NONE
);
4562 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
4563 iview
->planes
[0].isl
.format
,
4564 VK_IMAGE_ASPECT_COLOR_BIT
,
4566 ISL_AUX_OP_PARTIAL_RESOLVE
,
4567 ANV_FAST_CLEAR_NONE
);
4573 /* Transition the image into the final layout for this render pass */
4574 VkImageLayout target_layout
=
4575 cmd_state
->pass
->attachments
[a
].final_layout
;
4577 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4578 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4580 uint32_t base_layer
, layer_count
;
4581 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4583 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4584 iview
->planes
[0].isl
.base_level
);
4586 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4587 layer_count
= fb
->layers
;
4590 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4591 iview
->planes
[0].isl
.base_level
, 1,
4592 base_layer
, layer_count
,
4593 att_state
->current_layout
, target_layout
);
4594 } else if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4595 transition_depth_buffer(cmd_buffer
, image
,
4596 att_state
->current_layout
, target_layout
);
4600 /* Accumulate any subpass flushes that need to happen after the subpass.
4601 * Yes, they do get accumulated twice in the NextSubpass case but since
4602 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
4603 * ORing the bits in twice so it's harmless.
4605 cmd_buffer
->state
.pending_pipe_bits
|=
4606 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
4609 void genX(CmdBeginRenderPass
)(
4610 VkCommandBuffer commandBuffer
,
4611 const VkRenderPassBeginInfo
* pRenderPassBegin
,
4612 VkSubpassContents contents
)
4614 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4615 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
4616 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
4618 cmd_buffer
->state
.framebuffer
= framebuffer
;
4619 cmd_buffer
->state
.pass
= pass
;
4620 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
4622 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
4624 /* If we failed to setup the attachments we should not try to go further */
4625 if (result
!= VK_SUCCESS
) {
4626 assert(anv_batch_has_error(&cmd_buffer
->batch
));
4630 genX(flush_pipeline_select_3d
)(cmd_buffer
);
4632 cmd_buffer_begin_subpass(cmd_buffer
, 0);
4635 void genX(CmdBeginRenderPass2KHR
)(
4636 VkCommandBuffer commandBuffer
,
4637 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
4638 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
4640 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
4641 pSubpassBeginInfo
->contents
);
4644 void genX(CmdNextSubpass
)(
4645 VkCommandBuffer commandBuffer
,
4646 VkSubpassContents contents
)
4648 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4650 if (anv_batch_has_error(&cmd_buffer
->batch
))
4653 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4655 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
4656 cmd_buffer_end_subpass(cmd_buffer
);
4657 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
4660 void genX(CmdNextSubpass2KHR
)(
4661 VkCommandBuffer commandBuffer
,
4662 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
4663 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4665 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
4668 void genX(CmdEndRenderPass
)(
4669 VkCommandBuffer commandBuffer
)
4671 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4673 if (anv_batch_has_error(&cmd_buffer
->batch
))
4676 cmd_buffer_end_subpass(cmd_buffer
);
4678 cmd_buffer
->state
.hiz_enabled
= false;
4681 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
4684 /* Remove references to render pass specific state. This enables us to
4685 * detect whether or not we're in a renderpass.
4687 cmd_buffer
->state
.framebuffer
= NULL
;
4688 cmd_buffer
->state
.pass
= NULL
;
4689 cmd_buffer
->state
.subpass
= NULL
;
4692 void genX(CmdEndRenderPass2KHR
)(
4693 VkCommandBuffer commandBuffer
,
4694 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
4696 genX(CmdEndRenderPass
)(commandBuffer
);
4700 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
4702 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4703 struct gen_mi_builder b
;
4704 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4706 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
4707 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4708 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4710 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
4711 mip
.LoadOperation
= LOAD_LOADINV
;
4712 mip
.CombineOperation
= COMBINE_SET
;
4713 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4718 #if GEN_GEN >= 8 || GEN_IS_HASWELL
4719 void genX(CmdBeginConditionalRenderingEXT
)(
4720 VkCommandBuffer commandBuffer
,
4721 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
4723 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4724 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
4725 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4726 struct anv_address value_address
=
4727 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
4729 const bool isInverted
= pConditionalRenderingBegin
->flags
&
4730 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
4732 cmd_state
->conditional_render_enabled
= true;
4734 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4736 struct gen_mi_builder b
;
4737 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4739 /* Section 19.4 of the Vulkan 1.1.85 spec says:
4741 * If the value of the predicate in buffer memory changes
4742 * while conditional rendering is active, the rendering commands
4743 * may be discarded in an implementation-dependent way.
4744 * Some implementations may latch the value of the predicate
4745 * upon beginning conditional rendering while others
4746 * may read it before every rendering command.
4748 * So it's perfectly fine to read a value from the buffer once.
4750 struct gen_mi_value value
= gen_mi_mem32(value_address
);
4752 /* Precompute predicate result, it is necessary to support secondary
4753 * command buffers since it is unknown if conditional rendering is
4754 * inverted when populating them.
4756 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
4757 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
4758 gen_mi_ult(&b
, gen_mi_imm(0), value
));
4761 void genX(CmdEndConditionalRenderingEXT
)(
4762 VkCommandBuffer commandBuffer
)
4764 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4765 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4767 cmd_state
->conditional_render_enabled
= false;