2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* Emit a render target cache flush.
60 * This isn't documented anywhere in the PRM. However, it seems to be
61 * necessary prior to changing the surface state base adress. Without
62 * this, we get GPU hangs when using multi-level command buffers which
63 * clear depth, reset state base address, and then go render stuff.
65 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
66 pc
.DCFlushEnable
= true;
67 pc
.RenderTargetCacheFlushEnable
= true;
68 pc
.CommandStreamerStallEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
150 pc
.ConstantCacheInvalidationEnable
= true;
151 pc
.StateCacheInvalidationEnable
= true;
156 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
157 struct anv_state state
,
158 struct anv_bo
*bo
, uint32_t offset
)
160 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
163 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
164 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
165 if (result
!= VK_SUCCESS
)
166 anv_batch_set_error(&cmd_buffer
->batch
, result
);
170 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
171 const struct anv_image_view
*iview
,
172 enum isl_aux_usage aux_usage
,
173 struct anv_state state
)
175 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
177 add_surface_state_reloc(cmd_buffer
, state
, iview
->bo
, iview
->offset
);
179 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
180 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
182 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
183 * used to store other information. This should be ok, however, because
184 * surface buffer addresses are always 4K page alinged.
186 assert((aux_offset
& 0xfff) == 0);
187 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
188 aux_offset
+= *aux_addr_dw
& 0xfff;
191 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
192 &cmd_buffer
->pool
->alloc
,
193 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
194 iview
->bo
, aux_offset
);
195 if (result
!= VK_SUCCESS
)
196 anv_batch_set_error(&cmd_buffer
->batch
, result
);
201 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
203 if (isl_format_has_int_channel(format
)) {
204 for (unsigned i
= 0; i
< 4; i
++) {
205 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
209 for (unsigned i
= 0; i
< 4; i
++) {
210 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
219 color_attachment_compute_aux_usage(struct anv_device
*device
,
220 struct anv_attachment_state
*att_state
,
221 struct anv_image_view
*iview
,
222 VkRect2D render_area
,
223 union isl_color_value
*fast_clear_color
)
225 if (iview
->image
->aux_surface
.isl
.size
== 0) {
226 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
227 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
228 att_state
->fast_clear
= false;
230 } else if (iview
->image
->aux_usage
== ISL_AUX_USAGE_MCS
) {
231 att_state
->aux_usage
= ISL_AUX_USAGE_MCS
;
232 att_state
->input_aux_usage
= ISL_AUX_USAGE_MCS
;
233 att_state
->fast_clear
= false;
237 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
239 att_state
->clear_color_is_zero_one
=
240 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
242 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
243 /* Start off assuming fast clears are possible */
244 att_state
->fast_clear
= true;
246 /* Potentially, we could do partial fast-clears but doing so has crazy
247 * alignment restrictions. It's easier to just restrict to full size
248 * fast clears for now.
250 if (render_area
.offset
.x
!= 0 ||
251 render_area
.offset
.y
!= 0 ||
252 render_area
.extent
.width
!= iview
->extent
.width
||
253 render_area
.extent
.height
!= iview
->extent
.height
)
254 att_state
->fast_clear
= false;
257 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
258 * technically can, but it comes with crazy restrictions that we
259 * don't want to deal with now.
261 if (iview
->isl
.base_level
> 0 ||
262 iview
->isl
.base_array_layer
> 0 ||
263 iview
->isl
.array_len
> 1)
264 att_state
->fast_clear
= false;
267 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
268 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
269 att_state
->fast_clear
= false;
271 if (att_state
->fast_clear
) {
272 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
273 sizeof(fast_clear_color
->u32
));
276 att_state
->fast_clear
= false;
280 * TODO: Consider using a heuristic to determine if temporarily enabling
281 * CCS_E for this image view would be beneficial.
283 * While fast-clear resolves and partial resolves are fairly cheap in the
284 * case where you render to most of the pixels, full resolves are not
285 * because they potentially involve reading and writing the entire
286 * framebuffer. If we can't texture with CCS_E, we should leave it off and
287 * limit ourselves to fast clears.
289 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
290 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
291 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
292 } else if (att_state
->fast_clear
) {
293 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
295 !isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
)) {
296 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
298 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
299 * setting is only allowed if Surface Format supported for Fast
300 * Clear. In addition, if the surface is bound to the sampling
301 * engine, Surface Format must be supported for Render Target
302 * Compression for surfaces bound to the sampling engine."
304 * In other words, we can't sample from a fast-cleared image if it
305 * doesn't also support color compression.
307 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
308 } else if (GEN_GEN
>= 8) {
309 /* Broadwell/Skylake can sample from fast-cleared images */
310 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
312 /* Ivy Bridge and Haswell cannot */
313 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
316 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
317 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
322 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
324 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
327 /* We only allocate input attachment states for color surfaces. Compression
328 * is not yet enabled for depth textures and stencil doesn't allow
329 * compression so we can just use the texture surface state from the view.
331 return vk_format_is_color(att
->format
);
334 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
335 * the initial layout is undefined, the HiZ buffer and depth buffer will
336 * represent the same data at the end of this operation.
339 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
340 const struct anv_image
*image
,
341 VkImageLayout initial_layout
,
342 VkImageLayout final_layout
)
346 /* A transition is a no-op if HiZ is not enabled, or if the initial and
347 * final layouts are equal.
349 * The undefined layout indicates that the user doesn't care about the data
350 * that's currently in the buffer. Therefore, a data-preserving resolve
351 * operation is not needed.
353 * The pre-initialized layout is equivalent to the undefined layout for
354 * optimally-tiled images. Anv only exposes support for optimally-tiled
357 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
||
358 initial_layout
== final_layout
||
359 initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
360 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)
363 const bool hiz_enabled
= ISL_AUX_USAGE_HIZ
==
364 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
366 const bool enable_hiz
= ISL_AUX_USAGE_HIZ
==
367 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
, image
->aspects
,
370 enum blorp_hiz_op hiz_op
;
371 if (hiz_enabled
&& !enable_hiz
) {
372 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
373 } else if (!hiz_enabled
&& enable_hiz
) {
374 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
376 assert(hiz_enabled
== enable_hiz
);
377 /* If the same buffer will be used, no resolves are necessary. */
378 hiz_op
= BLORP_HIZ_OP_NONE
;
381 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
382 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
387 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
390 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
391 struct anv_render_pass
*pass
,
392 const VkRenderPassBeginInfo
*begin
)
394 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
395 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
397 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
399 if (pass
->attachment_count
== 0) {
400 state
->attachments
= NULL
;
404 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
405 pass
->attachment_count
*
406 sizeof(state
->attachments
[0]),
407 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
408 if (state
->attachments
== NULL
) {
409 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
410 return anv_batch_set_error(&cmd_buffer
->batch
,
411 VK_ERROR_OUT_OF_HOST_MEMORY
);
414 bool need_null_state
= false;
415 unsigned num_states
= 0;
416 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
417 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
420 /* We need a null state for any depth-stencil-only subpasses.
421 * Importantly, this includes depth/stencil clears so we create one
422 * whenever we have depth or stencil
424 need_null_state
= true;
427 if (need_input_attachment_state(&pass
->attachments
[i
]))
430 num_states
+= need_null_state
;
432 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
433 state
->render_pass_states
=
434 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
435 num_states
* ss_stride
, isl_dev
->ss
.align
);
437 struct anv_state next_state
= state
->render_pass_states
;
438 next_state
.alloc_size
= isl_dev
->ss
.size
;
440 if (need_null_state
) {
441 state
->null_surface_state
= next_state
;
442 next_state
.offset
+= ss_stride
;
443 next_state
.map
+= ss_stride
;
446 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
447 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
448 state
->attachments
[i
].color_rt_state
= next_state
;
449 next_state
.offset
+= ss_stride
;
450 next_state
.map
+= ss_stride
;
453 if (need_input_attachment_state(&pass
->attachments
[i
])) {
454 state
->attachments
[i
].input_att_state
= next_state
;
455 next_state
.offset
+= ss_stride
;
456 next_state
.map
+= ss_stride
;
459 assert(next_state
.offset
== state
->render_pass_states
.offset
+
460 state
->render_pass_states
.alloc_size
);
463 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
464 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
466 if (need_null_state
) {
467 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
468 .SurfaceType
= SURFTYPE_NULL
,
469 .SurfaceArray
= framebuffer
->layers
> 0,
470 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
474 .TiledSurface
= true,
476 .Width
= framebuffer
->width
- 1,
477 .Height
= framebuffer
->height
- 1,
478 .Depth
= framebuffer
->layers
- 1,
479 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
481 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
485 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
486 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
487 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
488 VkImageAspectFlags clear_aspects
= 0;
490 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
491 /* color attachment */
492 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
493 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
496 /* depthstencil attachment */
497 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
498 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
499 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
501 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
502 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
503 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
507 state
->attachments
[i
].current_layout
= att
->initial_layout
;
508 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
510 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
512 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
513 anv_assert(iview
->vk_format
== att
->format
);
515 union isl_color_value clear_color
= { .u32
= { 0, } };
516 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
517 color_attachment_compute_aux_usage(cmd_buffer
->device
,
518 &state
->attachments
[i
],
519 iview
, begin
->renderArea
,
522 struct isl_view view
= iview
->isl
;
523 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
524 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
525 isl_surf_fill_state(isl_dev
,
526 state
->attachments
[i
].color_rt_state
.map
,
527 .surf
= &iview
->image
->color_surface
.isl
,
529 .aux_surf
= &iview
->image
->aux_surface
.isl
,
530 .aux_usage
= state
->attachments
[i
].aux_usage
,
531 .clear_color
= clear_color
,
532 .mocs
= cmd_buffer
->device
->default_mocs
);
534 add_image_view_relocs(cmd_buffer
, iview
,
535 state
->attachments
[i
].aux_usage
,
536 state
->attachments
[i
].color_rt_state
);
538 /* This field will be initialized after the first subpass
541 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
543 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
546 if (need_input_attachment_state(&pass
->attachments
[i
])) {
547 struct isl_view view
= iview
->isl
;
548 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
549 isl_surf_fill_state(isl_dev
,
550 state
->attachments
[i
].input_att_state
.map
,
551 .surf
= &iview
->image
->color_surface
.isl
,
553 .aux_surf
= &iview
->image
->aux_surface
.isl
,
554 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
555 .clear_color
= clear_color
,
556 .mocs
= cmd_buffer
->device
->default_mocs
);
558 add_image_view_relocs(cmd_buffer
, iview
,
559 state
->attachments
[i
].input_aux_usage
,
560 state
->attachments
[i
].input_att_state
);
564 anv_state_flush(cmd_buffer
->device
, state
->render_pass_states
);
571 genX(BeginCommandBuffer
)(
572 VkCommandBuffer commandBuffer
,
573 const VkCommandBufferBeginInfo
* pBeginInfo
)
575 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
577 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
578 * command buffer's state. Otherwise, we must *reset* its state. In both
581 * From the Vulkan 1.0 spec:
583 * If a command buffer is in the executable state and the command buffer
584 * was allocated from a command pool with the
585 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
586 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
587 * as if vkResetCommandBuffer had been called with
588 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
589 * the command buffer in the recording state.
591 anv_cmd_buffer_reset(cmd_buffer
);
593 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
595 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
596 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
598 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
600 VkResult result
= VK_SUCCESS
;
601 if (cmd_buffer
->usage_flags
&
602 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
603 cmd_buffer
->state
.pass
=
604 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
605 cmd_buffer
->state
.subpass
=
606 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
607 cmd_buffer
->state
.framebuffer
= NULL
;
609 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
610 cmd_buffer
->state
.pass
, NULL
);
612 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
619 genX(EndCommandBuffer
)(
620 VkCommandBuffer commandBuffer
)
622 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
624 if (anv_batch_has_error(&cmd_buffer
->batch
))
625 return cmd_buffer
->batch
.status
;
627 /* We want every command buffer to start with the PMA fix in a known state,
628 * so we disable it at the end of the command buffer.
630 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
632 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
634 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
640 genX(CmdExecuteCommands
)(
641 VkCommandBuffer commandBuffer
,
642 uint32_t commandBufferCount
,
643 const VkCommandBuffer
* pCmdBuffers
)
645 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
647 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
649 if (anv_batch_has_error(&primary
->batch
))
652 /* The secondary command buffers will assume that the PMA fix is disabled
653 * when they begin executing. Make sure this is true.
655 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
657 /* The secondary command buffer doesn't know which textures etc. have been
658 * flushed prior to their execution. Apply those flushes now.
660 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
662 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
663 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
665 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
666 assert(!anv_batch_has_error(&secondary
->batch
));
668 if (secondary
->usage_flags
&
669 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
670 /* If we're continuing a render pass from the primary, we need to
671 * copy the surface states for the current subpass into the storage
672 * we allocated for them in BeginCommandBuffer.
674 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
675 struct anv_state src_state
= primary
->state
.render_pass_states
;
676 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
677 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
679 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
680 ss_bo
, src_state
.offset
,
681 src_state
.alloc_size
);
684 anv_cmd_buffer_add_secondary(primary
, secondary
);
687 /* Each of the secondary command buffers will use its own state base
688 * address. We need to re-emit state base address for the primary after
689 * all of the secondaries are done.
691 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
694 genX(cmd_buffer_emit_state_base_address
)(primary
);
697 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
698 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
699 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
702 * Program the hardware to use the specified L3 configuration.
705 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
706 const struct gen_l3_config
*cfg
)
709 if (cfg
== cmd_buffer
->state
.current_l3_config
)
712 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
713 fprintf(stderr
, "L3 config transition: ");
714 gen_dump_l3_config(cfg
, stderr
);
717 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
719 /* According to the hardware docs, the L3 partitioning can only be changed
720 * while the pipeline is completely drained and the caches are flushed,
721 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
723 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
724 pc
.DCFlushEnable
= true;
725 pc
.PostSyncOperation
= NoWrite
;
726 pc
.CommandStreamerStallEnable
= true;
729 /* ...followed by a second pipelined PIPE_CONTROL that initiates
730 * invalidation of the relevant caches. Note that because RO invalidation
731 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
732 * command is processed by the CS) we cannot combine it with the previous
733 * stalling flush as the hardware documentation suggests, because that
734 * would cause the CS to stall on previous rendering *after* RO
735 * invalidation and wouldn't prevent the RO caches from being polluted by
736 * concurrent rendering before the stall completes. This intentionally
737 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
738 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
739 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
740 * already guarantee that there is no concurrent GPGPU kernel execution
741 * (see SKL HSD 2132585).
743 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
744 pc
.TextureCacheInvalidationEnable
= true;
745 pc
.ConstantCacheInvalidationEnable
= true;
746 pc
.InstructionCacheInvalidateEnable
= true;
747 pc
.StateCacheInvalidationEnable
= true;
748 pc
.PostSyncOperation
= NoWrite
;
751 /* Now send a third stalling flush to make sure that invalidation is
752 * complete when the L3 configuration registers are modified.
754 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
755 pc
.DCFlushEnable
= true;
756 pc
.PostSyncOperation
= NoWrite
;
757 pc
.CommandStreamerStallEnable
= true;
762 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
765 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
766 .SLMEnable
= has_slm
,
767 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
768 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
769 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
770 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
772 /* Set up the L3 partitioning. */
773 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
777 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
778 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
780 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
782 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
785 assert(!cfg
->n
[GEN_L3P_ALL
]);
787 /* When enabled SLM only uses a portion of the L3 on half of the banks,
788 * the matching space on the remaining banks has to be allocated to a
789 * client (URB for all validated configurations) set to the
790 * lower-bandwidth 2-bank address hashing mode.
792 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
793 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
794 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
796 /* Minimum number of ways that can be allocated to the URB. */
797 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
798 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
800 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
801 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
802 .ConvertDC_UC
= !has_dc
,
803 .ConvertIS_UC
= !has_is
,
804 .ConvertC_UC
= !has_c
,
805 .ConvertT_UC
= !has_t
);
807 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
808 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
809 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
811 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
812 .SLMEnable
= has_slm
,
813 .URBLowBandwidth
= urb_low_bw
,
814 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
816 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
818 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
819 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
821 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
822 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
824 .CAllocation
= cfg
->n
[GEN_L3P_C
],
826 .TAllocation
= cfg
->n
[GEN_L3P_T
],
829 /* Set up the L3 partitioning. */
830 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
831 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
832 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
835 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
836 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
837 * them disabled to avoid crashing the system hard.
839 uint32_t scratch1
, chicken3
;
840 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
841 .L3AtomicDisable
= !has_dc
);
842 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
843 .L3AtomicDisableMask
= true,
844 .L3AtomicDisable
= !has_dc
);
845 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
846 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
852 cmd_buffer
->state
.current_l3_config
= cfg
;
856 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
858 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
860 /* Flushes are pipelined while invalidations are handled immediately.
861 * Therefore, if we're flushing anything then we need to schedule a stall
862 * before any invalidations can happen.
864 if (bits
& ANV_PIPE_FLUSH_BITS
)
865 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
867 /* If we're going to do an invalidate and we have a pending CS stall that
868 * has yet to be resolved, we do the CS stall now.
870 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
871 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
872 bits
|= ANV_PIPE_CS_STALL_BIT
;
873 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
876 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
877 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
878 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
879 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
880 pipe
.RenderTargetCacheFlushEnable
=
881 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
883 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
884 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
885 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
888 * According to the Broadwell documentation, any PIPE_CONTROL with the
889 * "Command Streamer Stall" bit set must also have another bit set,
890 * with five different options:
892 * - Render Target Cache Flush
893 * - Depth Cache Flush
894 * - Stall at Pixel Scoreboard
895 * - Post-Sync Operation
899 * I chose "Stall at Pixel Scoreboard" since that's what we use in
900 * mesa and it seems to work fine. The choice is fairly arbitrary.
902 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
903 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
904 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
905 pipe
.StallAtPixelScoreboard
= true;
908 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
911 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
912 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
913 pipe
.StateCacheInvalidationEnable
=
914 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
915 pipe
.ConstantCacheInvalidationEnable
=
916 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
917 pipe
.VFCacheInvalidationEnable
=
918 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
919 pipe
.TextureCacheInvalidationEnable
=
920 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
921 pipe
.InstructionCacheInvalidateEnable
=
922 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
925 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
928 cmd_buffer
->state
.pending_pipe_bits
= bits
;
931 void genX(CmdPipelineBarrier
)(
932 VkCommandBuffer commandBuffer
,
933 VkPipelineStageFlags srcStageMask
,
934 VkPipelineStageFlags destStageMask
,
936 uint32_t memoryBarrierCount
,
937 const VkMemoryBarrier
* pMemoryBarriers
,
938 uint32_t bufferMemoryBarrierCount
,
939 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
940 uint32_t imageMemoryBarrierCount
,
941 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
943 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
945 /* XXX: Right now, we're really dumb and just flush whatever categories
946 * the app asks for. One of these days we may make this a bit better
947 * but right now that's all the hardware allows for in most areas.
949 VkAccessFlags src_flags
= 0;
950 VkAccessFlags dst_flags
= 0;
952 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
953 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
954 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
957 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
958 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
959 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
962 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
963 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
964 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
965 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
966 if (pImageMemoryBarriers
[i
].subresourceRange
.aspectMask
&
967 VK_IMAGE_ASPECT_DEPTH_BIT
) {
968 transition_depth_buffer(cmd_buffer
, image
,
969 pImageMemoryBarriers
[i
].oldLayout
,
970 pImageMemoryBarriers
[i
].newLayout
);
974 cmd_buffer
->state
.pending_pipe_bits
|=
975 anv_pipe_flush_bits_for_access_flags(src_flags
) |
976 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
980 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
982 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
984 /* In order to avoid thrash, we assume that vertex and fragment stages
985 * always exist. In the rare case where one is missing *and* the other
986 * uses push concstants, this may be suboptimal. However, avoiding stalls
987 * seems more important.
989 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
991 if (stages
== cmd_buffer
->state
.push_constant_stages
)
995 const unsigned push_constant_kb
= 32;
997 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
999 const unsigned push_constant_kb
= 16;
1002 const unsigned num_stages
=
1003 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1004 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1006 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1007 * units of 2KB. Incidentally, these are the same platforms that have
1008 * 32KB worth of push constant space.
1010 if (push_constant_kb
== 32)
1011 size_per_stage
&= ~1u;
1013 uint32_t kb_used
= 0;
1014 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1015 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1016 anv_batch_emit(&cmd_buffer
->batch
,
1017 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1018 alloc
._3DCommandSubOpcode
= 18 + i
;
1019 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1020 alloc
.ConstantBufferSize
= push_size
;
1022 kb_used
+= push_size
;
1025 anv_batch_emit(&cmd_buffer
->batch
,
1026 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1027 alloc
.ConstantBufferOffset
= kb_used
;
1028 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1031 cmd_buffer
->state
.push_constant_stages
= stages
;
1033 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1035 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1036 * the next 3DPRIMITIVE command after programming the
1037 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1039 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1040 * pipeline setup, we need to dirty push constants.
1042 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1046 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1047 gl_shader_stage stage
,
1048 struct anv_state
*bt_state
)
1050 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1051 struct anv_pipeline
*pipeline
;
1052 uint32_t bias
, state_offset
;
1055 case MESA_SHADER_COMPUTE
:
1056 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1060 pipeline
= cmd_buffer
->state
.pipeline
;
1065 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1066 *bt_state
= (struct anv_state
) { 0, };
1070 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1071 if (bias
+ map
->surface_count
== 0) {
1072 *bt_state
= (struct anv_state
) { 0, };
1076 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1077 bias
+ map
->surface_count
,
1079 uint32_t *bt_map
= bt_state
->map
;
1081 if (bt_state
->map
== NULL
)
1082 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1084 if (stage
== MESA_SHADER_COMPUTE
&&
1085 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1086 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1087 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1089 struct anv_state surface_state
;
1091 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1093 const enum isl_format format
=
1094 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1095 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1096 format
, bo_offset
, 12, 1);
1098 bt_map
[0] = surface_state
.offset
+ state_offset
;
1099 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1102 if (map
->surface_count
== 0)
1105 if (map
->image_count
> 0) {
1107 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1108 if (result
!= VK_SUCCESS
)
1111 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1115 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1116 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1118 struct anv_state surface_state
;
1120 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1121 /* Color attachment binding */
1122 assert(stage
== MESA_SHADER_FRAGMENT
);
1123 assert(binding
->binding
== 0);
1124 if (binding
->index
< subpass
->color_count
) {
1125 const unsigned att
= subpass
->color_attachments
[binding
->index
].attachment
;
1126 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1128 surface_state
= cmd_buffer
->state
.null_surface_state
;
1131 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1135 struct anv_descriptor_set
*set
=
1136 cmd_buffer
->state
.descriptors
[binding
->set
];
1137 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1138 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1140 switch (desc
->type
) {
1141 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1142 /* Nothing for us to do here */
1145 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1146 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1147 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1148 desc
->image_view
->no_aux_sampler_surface_state
:
1149 desc
->image_view
->sampler_surface_state
;
1150 assert(surface_state
.alloc_size
);
1151 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1152 desc
->aux_usage
, surface_state
);
1154 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1155 assert(stage
== MESA_SHADER_FRAGMENT
);
1156 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1157 /* For depth and stencil input attachments, we treat it like any
1158 * old texture that a user may have bound.
1160 surface_state
= desc
->aux_usage
== ISL_AUX_USAGE_NONE
?
1161 desc
->image_view
->no_aux_sampler_surface_state
:
1162 desc
->image_view
->sampler_surface_state
;
1163 assert(surface_state
.alloc_size
);
1164 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1165 desc
->aux_usage
, surface_state
);
1167 /* For color input attachments, we create the surface state at
1168 * vkBeginRenderPass time so that we can include aux and clear
1169 * color information.
1171 assert(binding
->input_attachment_index
< subpass
->input_count
);
1172 const unsigned subpass_att
= binding
->input_attachment_index
;
1173 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
1174 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1178 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1179 surface_state
= (binding
->write_only
)
1180 ? desc
->image_view
->writeonly_storage_surface_state
1181 : desc
->image_view
->storage_surface_state
;
1182 assert(surface_state
.alloc_size
);
1183 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1184 desc
->image_view
->image
->aux_usage
,
1187 struct brw_image_param
*image_param
=
1188 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1190 *image_param
= desc
->image_view
->storage_image_param
;
1191 image_param
->surface_idx
= bias
+ s
;
1195 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1196 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1197 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1198 surface_state
= desc
->buffer_view
->surface_state
;
1199 assert(surface_state
.alloc_size
);
1200 add_surface_state_reloc(cmd_buffer
, surface_state
,
1201 desc
->buffer_view
->bo
,
1202 desc
->buffer_view
->offset
);
1205 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1206 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
1207 uint32_t dynamic_offset_idx
=
1208 pipeline
->layout
->set
[binding
->set
].dynamic_offset_start
+
1209 set
->layout
->binding
[binding
->binding
].dynamic_offset_index
+
1212 /* Compute the offset within the buffer */
1213 uint64_t offset
= desc
->offset
+
1214 cmd_buffer
->state
.dynamic_offsets
[dynamic_offset_idx
];
1215 /* Clamp to the buffer size */
1216 offset
= MIN2(offset
, desc
->buffer
->size
);
1217 /* Clamp the range to the buffer size */
1218 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
1221 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
1222 enum isl_format format
=
1223 anv_isl_format_for_descriptor_type(desc
->type
);
1225 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1226 format
, offset
, range
, 1);
1227 add_surface_state_reloc(cmd_buffer
, surface_state
,
1229 desc
->buffer
->offset
+ offset
);
1233 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1234 surface_state
= (binding
->write_only
)
1235 ? desc
->buffer_view
->writeonly_storage_surface_state
1236 : desc
->buffer_view
->storage_surface_state
;
1237 assert(surface_state
.alloc_size
);
1238 add_surface_state_reloc(cmd_buffer
, surface_state
,
1239 desc
->buffer_view
->bo
,
1240 desc
->buffer_view
->offset
);
1242 struct brw_image_param
*image_param
=
1243 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1245 *image_param
= desc
->buffer_view
->storage_image_param
;
1246 image_param
->surface_idx
= bias
+ s
;
1250 assert(!"Invalid descriptor type");
1254 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1256 assert(image
== map
->image_count
);
1259 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1265 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1266 gl_shader_stage stage
,
1267 struct anv_state
*state
)
1269 struct anv_pipeline
*pipeline
;
1271 if (stage
== MESA_SHADER_COMPUTE
)
1272 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1274 pipeline
= cmd_buffer
->state
.pipeline
;
1276 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1277 *state
= (struct anv_state
) { 0, };
1281 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1282 if (map
->sampler_count
== 0) {
1283 *state
= (struct anv_state
) { 0, };
1287 uint32_t size
= map
->sampler_count
* 16;
1288 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1290 if (state
->map
== NULL
)
1291 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1293 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1294 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1295 struct anv_descriptor_set
*set
=
1296 cmd_buffer
->state
.descriptors
[binding
->set
];
1297 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1298 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1300 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1301 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1304 struct anv_sampler
*sampler
= desc
->sampler
;
1306 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1307 * happens to be zero.
1309 if (sampler
== NULL
)
1312 memcpy(state
->map
+ (s
* 16),
1313 sampler
->state
, sizeof(sampler
->state
));
1316 anv_state_flush(cmd_buffer
->device
, *state
);
1322 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1324 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1325 cmd_buffer
->state
.pipeline
->active_stages
;
1327 VkResult result
= VK_SUCCESS
;
1328 anv_foreach_stage(s
, dirty
) {
1329 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1330 if (result
!= VK_SUCCESS
)
1332 result
= emit_binding_table(cmd_buffer
, s
,
1333 &cmd_buffer
->state
.binding_tables
[s
]);
1334 if (result
!= VK_SUCCESS
)
1338 if (result
!= VK_SUCCESS
) {
1339 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1341 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1342 if (result
!= VK_SUCCESS
)
1345 /* Re-emit state base addresses so we get the new surface state base
1346 * address before we start emitting binding tables etc.
1348 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1350 /* Re-emit all active binding tables */
1351 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1352 anv_foreach_stage(s
, dirty
) {
1353 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1354 if (result
!= VK_SUCCESS
) {
1355 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1358 result
= emit_binding_table(cmd_buffer
, s
,
1359 &cmd_buffer
->state
.binding_tables
[s
]);
1360 if (result
!= VK_SUCCESS
) {
1361 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1367 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1373 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1376 static const uint32_t sampler_state_opcodes
[] = {
1377 [MESA_SHADER_VERTEX
] = 43,
1378 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1379 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1380 [MESA_SHADER_GEOMETRY
] = 46,
1381 [MESA_SHADER_FRAGMENT
] = 47,
1382 [MESA_SHADER_COMPUTE
] = 0,
1385 static const uint32_t binding_table_opcodes
[] = {
1386 [MESA_SHADER_VERTEX
] = 38,
1387 [MESA_SHADER_TESS_CTRL
] = 39,
1388 [MESA_SHADER_TESS_EVAL
] = 40,
1389 [MESA_SHADER_GEOMETRY
] = 41,
1390 [MESA_SHADER_FRAGMENT
] = 42,
1391 [MESA_SHADER_COMPUTE
] = 0,
1394 anv_foreach_stage(s
, stages
) {
1395 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1396 anv_batch_emit(&cmd_buffer
->batch
,
1397 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1398 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1399 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1403 /* Always emit binding table pointers if we're asked to, since on SKL
1404 * this is what flushes push constants. */
1405 anv_batch_emit(&cmd_buffer
->batch
,
1406 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1407 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1408 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1414 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1416 static const uint32_t push_constant_opcodes
[] = {
1417 [MESA_SHADER_VERTEX
] = 21,
1418 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1419 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1420 [MESA_SHADER_GEOMETRY
] = 22,
1421 [MESA_SHADER_FRAGMENT
] = 23,
1422 [MESA_SHADER_COMPUTE
] = 0,
1425 VkShaderStageFlags flushed
= 0;
1427 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1428 if (stage
== MESA_SHADER_COMPUTE
)
1431 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1433 if (state
.offset
== 0) {
1434 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1435 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1437 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1438 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1439 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1441 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1442 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1444 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1445 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1451 flushed
|= mesa_to_vk_shader_stage(stage
);
1454 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1460 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1462 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1465 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1467 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1469 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1471 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1474 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1475 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1477 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1478 GENX(3DSTATE_VERTEX_BUFFERS
));
1480 for_each_bit(vb
, vb_emit
) {
1481 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1482 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1484 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1485 .VertexBufferIndex
= vb
,
1488 .MemoryObjectControlState
= GENX(MOCS
),
1490 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1491 .InstanceDataStepRate
= 1,
1492 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1495 .AddressModifyEnable
= true,
1496 .BufferPitch
= pipeline
->binding_stride
[vb
],
1497 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1500 .BufferSize
= buffer
->size
- offset
1502 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1506 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1511 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1513 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1514 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1516 /* The exact descriptor layout is pulled from the pipeline, so we need
1517 * to re-emit binding tables on every pipeline change.
1519 cmd_buffer
->state
.descriptors_dirty
|=
1520 cmd_buffer
->state
.pipeline
->active_stages
;
1522 /* If the pipeline changed, we may need to re-allocate push constant
1525 cmd_buffer_alloc_push_constants(cmd_buffer
);
1529 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1530 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1531 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1533 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1534 * stall needs to be sent just prior to any 3DSTATE_VS,
1535 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1536 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1537 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1538 * PIPE_CONTROL needs to be sent before any combination of VS
1539 * associated 3DSTATE."
1541 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1542 pc
.DepthStallEnable
= true;
1543 pc
.PostSyncOperation
= WriteImmediateData
;
1545 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1550 /* Render targets live in the same binding table as fragment descriptors */
1551 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1552 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1554 /* We emit the binding tables and sampler tables first, then emit push
1555 * constants and then finally emit binding table and sampler table
1556 * pointers. It has to happen in this order, since emitting the binding
1557 * tables may change the push constants (in case of storage images). After
1558 * emitting push constants, on SKL+ we have to emit the corresponding
1559 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1562 if (cmd_buffer
->state
.descriptors_dirty
)
1563 dirty
= flush_descriptor_sets(cmd_buffer
);
1565 if (cmd_buffer
->state
.push_constants_dirty
) {
1567 /* On Sky Lake and later, the binding table pointers commands are
1568 * what actually flush the changes to push constant state so we need
1569 * to dirty them so they get re-emitted below.
1571 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1573 cmd_buffer_flush_push_constants(cmd_buffer
);
1578 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1580 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1581 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1583 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1584 ANV_CMD_DIRTY_PIPELINE
)) {
1585 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1586 pipeline
->depth_clamp_enable
);
1589 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1590 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1592 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1594 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1598 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
1599 struct anv_bo
*bo
, uint32_t offset
,
1600 uint32_t size
, uint32_t index
)
1602 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1603 GENX(3DSTATE_VERTEX_BUFFERS
));
1605 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1606 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1607 .VertexBufferIndex
= index
,
1608 .AddressModifyEnable
= true,
1611 .MemoryObjectControlState
= GENX(MOCS
),
1612 .BufferStartingAddress
= { bo
, offset
},
1615 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1616 .BufferStartingAddress
= { bo
, offset
},
1617 .EndAddress
= { bo
, offset
+ size
},
1623 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1624 struct anv_bo
*bo
, uint32_t offset
)
1626 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
1630 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1631 uint32_t base_vertex
, uint32_t base_instance
)
1633 struct anv_state id_state
=
1634 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1636 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1637 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1639 anv_state_flush(cmd_buffer
->device
, id_state
);
1641 emit_base_vertex_instance_bo(cmd_buffer
,
1642 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1646 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
1648 struct anv_state state
=
1649 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
1651 ((uint32_t *)state
.map
)[0] = draw_index
;
1653 anv_state_flush(cmd_buffer
->device
, state
);
1655 emit_vertex_bo(cmd_buffer
,
1656 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
1657 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
1661 VkCommandBuffer commandBuffer
,
1662 uint32_t vertexCount
,
1663 uint32_t instanceCount
,
1664 uint32_t firstVertex
,
1665 uint32_t firstInstance
)
1667 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1668 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1669 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1671 if (anv_batch_has_error(&cmd_buffer
->batch
))
1674 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1676 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1677 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1678 if (vs_prog_data
->uses_drawid
)
1679 emit_draw_index(cmd_buffer
, 0);
1681 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1682 prim
.VertexAccessType
= SEQUENTIAL
;
1683 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1684 prim
.VertexCountPerInstance
= vertexCount
;
1685 prim
.StartVertexLocation
= firstVertex
;
1686 prim
.InstanceCount
= instanceCount
;
1687 prim
.StartInstanceLocation
= firstInstance
;
1688 prim
.BaseVertexLocation
= 0;
1692 void genX(CmdDrawIndexed
)(
1693 VkCommandBuffer commandBuffer
,
1694 uint32_t indexCount
,
1695 uint32_t instanceCount
,
1696 uint32_t firstIndex
,
1697 int32_t vertexOffset
,
1698 uint32_t firstInstance
)
1700 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1701 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1702 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1704 if (anv_batch_has_error(&cmd_buffer
->batch
))
1707 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1709 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1710 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1711 if (vs_prog_data
->uses_drawid
)
1712 emit_draw_index(cmd_buffer
, 0);
1714 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1715 prim
.VertexAccessType
= RANDOM
;
1716 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1717 prim
.VertexCountPerInstance
= indexCount
;
1718 prim
.StartVertexLocation
= firstIndex
;
1719 prim
.InstanceCount
= instanceCount
;
1720 prim
.StartInstanceLocation
= firstInstance
;
1721 prim
.BaseVertexLocation
= vertexOffset
;
1725 /* Auto-Draw / Indirect Registers */
1726 #define GEN7_3DPRIM_END_OFFSET 0x2420
1727 #define GEN7_3DPRIM_START_VERTEX 0x2430
1728 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1729 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1730 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1731 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1733 void genX(CmdDrawIndirect
)(
1734 VkCommandBuffer commandBuffer
,
1736 VkDeviceSize offset
,
1740 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1741 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1742 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1743 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1744 struct anv_bo
*bo
= buffer
->bo
;
1745 uint32_t bo_offset
= buffer
->offset
+ offset
;
1747 if (anv_batch_has_error(&cmd_buffer
->batch
))
1750 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1752 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1753 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1754 if (vs_prog_data
->uses_drawid
)
1755 emit_draw_index(cmd_buffer
, 0);
1757 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1758 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1759 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1760 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1761 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1763 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1764 prim
.IndirectParameterEnable
= true;
1765 prim
.VertexAccessType
= SEQUENTIAL
;
1766 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1770 void genX(CmdDrawIndexedIndirect
)(
1771 VkCommandBuffer commandBuffer
,
1773 VkDeviceSize offset
,
1777 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1778 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1779 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1780 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1781 struct anv_bo
*bo
= buffer
->bo
;
1782 uint32_t bo_offset
= buffer
->offset
+ offset
;
1784 if (anv_batch_has_error(&cmd_buffer
->batch
))
1787 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1789 /* TODO: We need to stomp base vertex to 0 somehow */
1790 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1791 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1792 if (vs_prog_data
->uses_drawid
)
1793 emit_draw_index(cmd_buffer
, 0);
1795 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1796 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1797 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1798 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1799 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1801 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1802 prim
.IndirectParameterEnable
= true;
1803 prim
.VertexAccessType
= RANDOM
;
1804 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1809 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1811 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1812 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1815 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1816 if (result
!= VK_SUCCESS
) {
1817 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1819 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1820 if (result
!= VK_SUCCESS
)
1823 /* Re-emit state base addresses so we get the new surface state base
1824 * address before we start emitting binding tables etc.
1826 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1828 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1829 if (result
!= VK_SUCCESS
) {
1830 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1835 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1836 if (result
!= VK_SUCCESS
) {
1837 anv_batch_set_error(&cmd_buffer
->batch
, result
);
1841 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1842 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1843 .BindingTablePointer
= surfaces
.offset
,
1844 .SamplerStatePointer
= samplers
.offset
,
1846 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1848 struct anv_state state
=
1849 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1850 pipeline
->interface_descriptor_data
,
1851 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1854 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1855 anv_batch_emit(&cmd_buffer
->batch
,
1856 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1857 mid
.InterfaceDescriptorTotalLength
= size
;
1858 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1865 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1867 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1868 MAYBE_UNUSED VkResult result
;
1870 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1872 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1874 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1876 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1877 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1879 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1880 * the only bits that are changed are scoreboard related: Scoreboard
1881 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1882 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1885 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1886 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1888 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1891 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1892 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1893 /* FIXME: figure out descriptors for gen7 */
1894 result
= flush_compute_descriptor_set(cmd_buffer
);
1895 if (result
!= VK_SUCCESS
)
1898 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1901 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1902 struct anv_state push_state
=
1903 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1905 if (push_state
.alloc_size
) {
1906 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1907 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1908 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1913 cmd_buffer
->state
.compute_dirty
= 0;
1915 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1921 verify_cmd_parser(const struct anv_device
*device
,
1922 int required_version
,
1923 const char *function
)
1925 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1926 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1927 "cmd parser version %d is required for %s",
1928 required_version
, function
);
1936 void genX(CmdDispatch
)(
1937 VkCommandBuffer commandBuffer
,
1942 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1943 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1944 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1946 if (anv_batch_has_error(&cmd_buffer
->batch
))
1949 if (prog_data
->uses_num_work_groups
) {
1950 struct anv_state state
=
1951 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1952 uint32_t *sizes
= state
.map
;
1956 anv_state_flush(cmd_buffer
->device
, state
);
1957 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1958 cmd_buffer
->state
.num_workgroups_bo
=
1959 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1962 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1964 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1965 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1966 ggw
.ThreadDepthCounterMaximum
= 0;
1967 ggw
.ThreadHeightCounterMaximum
= 0;
1968 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1969 ggw
.ThreadGroupIDXDimension
= x
;
1970 ggw
.ThreadGroupIDYDimension
= y
;
1971 ggw
.ThreadGroupIDZDimension
= z
;
1972 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1973 ggw
.BottomExecutionMask
= 0xffffffff;
1976 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1979 #define GPGPU_DISPATCHDIMX 0x2500
1980 #define GPGPU_DISPATCHDIMY 0x2504
1981 #define GPGPU_DISPATCHDIMZ 0x2508
1983 #define MI_PREDICATE_SRC0 0x2400
1984 #define MI_PREDICATE_SRC1 0x2408
1986 void genX(CmdDispatchIndirect
)(
1987 VkCommandBuffer commandBuffer
,
1989 VkDeviceSize offset
)
1991 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1992 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1993 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1994 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1995 struct anv_bo
*bo
= buffer
->bo
;
1996 uint32_t bo_offset
= buffer
->offset
+ offset
;
1997 struct anv_batch
*batch
= &cmd_buffer
->batch
;
2000 /* Linux 4.4 added command parser version 5 which allows the GPGPU
2001 * indirect dispatch registers to be written.
2003 if (verify_cmd_parser(cmd_buffer
->device
, 5,
2004 "vkCmdDispatchIndirect") != VK_SUCCESS
)
2008 if (prog_data
->uses_num_work_groups
) {
2009 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
2010 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2013 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2015 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2016 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2017 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2020 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2021 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2022 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2023 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2025 /* Load compute_dispatch_indirect_x_size into SRC0 */
2026 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2028 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2029 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2030 mip
.LoadOperation
= LOAD_LOAD
;
2031 mip
.CombineOperation
= COMBINE_SET
;
2032 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2035 /* Load compute_dispatch_indirect_y_size into SRC0 */
2036 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2038 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2039 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2040 mip
.LoadOperation
= LOAD_LOAD
;
2041 mip
.CombineOperation
= COMBINE_OR
;
2042 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2045 /* Load compute_dispatch_indirect_z_size into SRC0 */
2046 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2048 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2049 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2050 mip
.LoadOperation
= LOAD_LOAD
;
2051 mip
.CombineOperation
= COMBINE_OR
;
2052 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2055 /* predicate = !predicate; */
2056 #define COMPARE_FALSE 1
2057 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2058 mip
.LoadOperation
= LOAD_LOADINV
;
2059 mip
.CombineOperation
= COMBINE_OR
;
2060 mip
.CompareOperation
= COMPARE_FALSE
;
2064 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2065 ggw
.IndirectParameterEnable
= true;
2066 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2067 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2068 ggw
.ThreadDepthCounterMaximum
= 0;
2069 ggw
.ThreadHeightCounterMaximum
= 0;
2070 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2071 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2072 ggw
.BottomExecutionMask
= 0xffffffff;
2075 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2079 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
2082 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
2085 #if GEN_GEN >= 8 && GEN_GEN < 10
2086 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2088 * Software must clear the COLOR_CALC_STATE Valid field in
2089 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2090 * with Pipeline Select set to GPGPU.
2092 * The internal hardware docs recommend the same workaround for Gen9
2095 if (pipeline
== GPGPU
)
2096 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2099 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2100 * PIPELINE_SELECT [DevBWR+]":
2104 * Software must ensure all the write caches are flushed through a
2105 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2106 * command to invalidate read only caches prior to programming
2107 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2109 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2110 pc
.RenderTargetCacheFlushEnable
= true;
2111 pc
.DepthCacheFlushEnable
= true;
2112 pc
.DCFlushEnable
= true;
2113 pc
.PostSyncOperation
= NoWrite
;
2114 pc
.CommandStreamerStallEnable
= true;
2117 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2118 pc
.TextureCacheInvalidationEnable
= true;
2119 pc
.ConstantCacheInvalidationEnable
= true;
2120 pc
.StateCacheInvalidationEnable
= true;
2121 pc
.InstructionCacheInvalidateEnable
= true;
2122 pc
.PostSyncOperation
= NoWrite
;
2125 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2129 ps
.PipelineSelection
= pipeline
;
2132 cmd_buffer
->state
.current_pipeline
= pipeline
;
2136 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2138 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
2142 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2144 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
2148 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2153 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2155 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2156 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2157 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2158 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2159 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2160 * Depth Flush Bit set, followed by another pipelined depth stall
2161 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2162 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2163 * via a preceding MI_FLUSH)."
2165 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2166 pipe
.DepthStallEnable
= true;
2168 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2169 pipe
.DepthCacheFlushEnable
= true;
2171 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2172 pipe
.DepthStallEnable
= true;
2177 depth_stencil_surface_type(enum isl_surf_dim dim
)
2180 case ISL_SURF_DIM_1D
:
2182 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2184 * Programming Notes:
2185 * The Surface Type of the depth buffer must be the same as the
2186 * Surface Type of the render target(s) (defined in
2187 * SURFACE_STATE), unless either the depth buffer or render
2188 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2189 * surface type not allowed for depth surface and stencil surface.
2192 * If depth/stencil is enabled with 1D render target,
2193 * depth/stencil surface type needs to be set to 2D surface type
2194 * and height set to 1. Depth will use (legacy) TileY and stencil
2195 * will use TileW. For this case only, the Surface Type of the
2196 * depth buffer can be 2D while the Surface Type of the render
2197 * target(s) are 1D, representing an exception to a programming
2204 case ISL_SURF_DIM_2D
:
2206 case ISL_SURF_DIM_3D
:
2208 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2209 * they have the exact same layout as 2D arrays on gen9+, so we can
2217 unreachable("Invalid surface dimension");
2222 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2224 struct anv_device
*device
= cmd_buffer
->device
;
2225 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2226 const struct anv_image_view
*iview
=
2227 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2228 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2229 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2230 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
.attachment
;
2231 const bool has_hiz
= image
!= NULL
&&
2232 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2233 const bool has_stencil
=
2234 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2236 cmd_buffer
->state
.hiz_enabled
= has_hiz
;
2238 /* FIXME: Width and Height are wrong */
2240 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2242 /* Emit 3DSTATE_DEPTH_BUFFER */
2244 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2246 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2247 db
.DepthWriteEnable
= true;
2248 db
.StencilWriteEnable
= has_stencil
;
2249 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2251 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2252 &image
->depth_surface
.isl
);
2254 db
.SurfaceBaseAddress
= (struct anv_address
) {
2256 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2258 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2260 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2261 db
.Height
= image
->extent
.height
- 1;
2262 db
.Width
= image
->extent
.width
- 1;
2263 db
.LOD
= iview
->isl
.base_level
;
2264 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2266 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2268 db
.RenderTargetViewExtent
= iview
->isl
.array_len
- 1;
2272 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2276 /* Even when no depth buffer is present, the hardware requires that
2277 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2279 * If a null depth buffer is bound, the driver must instead bind depth as:
2280 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2281 * 3DSTATE_DEPTH.Width = 1
2282 * 3DSTATE_DEPTH.Height = 1
2283 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2284 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2285 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2286 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2287 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2289 * The PRM is wrong, though. The width and height must be programmed to
2290 * actual framebuffer's width and height, even when neither depth buffer
2291 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2292 * be combined with a stencil buffer so we use D32_FLOAT instead.
2294 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2297 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2299 db
.SurfaceType
= SURFTYPE_2D
;
2301 db
.SurfaceFormat
= D32_FLOAT
;
2302 db
.Width
= MAX2(fb
->width
, 1) - 1;
2303 db
.Height
= MAX2(fb
->height
, 1) - 1;
2304 db
.StencilWriteEnable
= has_stencil
;
2309 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2310 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2311 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2312 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2314 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2317 /* From the SKL PRM Vol2a:
2319 * The interpretation of this field is dependent on Surface Type
2321 * - SURFTYPE_1D: distance in pixels between array slices
2322 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2323 * - SURFTYPE_3D: distance in rows between R - slices
2325 * Unfortunately, the docs aren't 100% accurate here. They fail to
2326 * mention that the 1-D rule only applies to linear 1-D images.
2327 * Since depth and HiZ buffers are always tiled, they are treated as
2328 * 2-D images. Prior to Sky Lake, this field is always in rows.
2331 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2335 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2338 /* Emit 3DSTATE_STENCIL_BUFFER */
2340 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2341 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2342 sb
.StencilBufferEnable
= true;
2344 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2346 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2349 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2351 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2353 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2357 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2360 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2362 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2363 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2364 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2366 * Testing also shows that some variant of this restriction may exist HSW+.
2367 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2368 * both have DepthClearValueValid set. An analysis of such state programming
2369 * on SKL showed that the GPU doesn't register the latter packet's clear
2372 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2374 cp
.DepthClearValueValid
= true;
2375 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2382 * @brief Perform any layout transitions required at the beginning and/or end
2383 * of the current subpass for depth buffers.
2385 * TODO: Consider preprocessing the attachment reference array at render pass
2386 * create time to determine if no layout transition is needed at the
2387 * beginning and/or end of each subpass.
2389 * @param cmd_buffer The command buffer the transition is happening within.
2390 * @param subpass_end If true, marks that the transition is happening at the
2391 * end of the subpass.
2394 cmd_buffer_subpass_transition_layouts(struct anv_cmd_buffer
* const cmd_buffer
,
2395 const bool subpass_end
)
2397 /* We need a non-NULL command buffer. */
2400 const struct anv_cmd_state
* const cmd_state
= &cmd_buffer
->state
;
2401 const struct anv_subpass
* const subpass
= cmd_state
->subpass
;
2403 /* This function must be called within a subpass. */
2406 /* If there are attachment references, the array shouldn't be NULL.
2408 if (subpass
->attachment_count
> 0)
2409 assert(subpass
->attachments
);
2411 /* Iterate over the array of attachment references. */
2412 for (const VkAttachmentReference
*att_ref
= subpass
->attachments
;
2413 att_ref
< subpass
->attachments
+ subpass
->attachment_count
; att_ref
++) {
2415 /* If the attachment is unused, we can't perform a layout transition. */
2416 if (att_ref
->attachment
== VK_ATTACHMENT_UNUSED
)
2419 /* This attachment index shouldn't go out of bounds. */
2420 assert(att_ref
->attachment
< cmd_state
->pass
->attachment_count
);
2422 const struct anv_render_pass_attachment
* const att_desc
=
2423 &cmd_state
->pass
->attachments
[att_ref
->attachment
];
2424 struct anv_attachment_state
* const att_state
=
2425 &cmd_buffer
->state
.attachments
[att_ref
->attachment
];
2427 /* The attachment should not be used in a subpass after its last. */
2428 assert(att_desc
->last_subpass_idx
>= anv_get_subpass_id(cmd_state
));
2430 if (subpass_end
&& anv_get_subpass_id(cmd_state
) <
2431 att_desc
->last_subpass_idx
) {
2432 /* We're calling this function on a buffer twice in one subpass and
2433 * this is not the last use of the buffer. The layout should not have
2434 * changed from the first call and no transition is necessary.
2436 assert(att_ref
->layout
== att_state
->current_layout
);
2440 /* Get the appropriate target layout for this attachment. */
2441 const VkImageLayout target_layout
= subpass_end
?
2442 att_desc
->final_layout
: att_ref
->layout
;
2444 /* The attachment index must be less than the number of attachments
2445 * within the framebuffer.
2447 assert(att_ref
->attachment
< cmd_state
->framebuffer
->attachment_count
);
2449 const struct anv_image
* const image
=
2450 cmd_state
->framebuffer
->attachments
[att_ref
->attachment
]->image
;
2452 /* Perform the layout transition. */
2453 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2454 transition_depth_buffer(cmd_buffer
, image
,
2455 att_state
->current_layout
, target_layout
);
2456 att_state
->aux_usage
=
2457 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
2458 image
->aspects
, target_layout
);
2461 att_state
->current_layout
= target_layout
;
2466 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2467 struct anv_subpass
*subpass
)
2469 cmd_buffer
->state
.subpass
= subpass
;
2471 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2473 /* Perform transitions to the subpass layout before any writes have
2476 cmd_buffer_subpass_transition_layouts(cmd_buffer
, false);
2478 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2480 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2483 void genX(CmdBeginRenderPass
)(
2484 VkCommandBuffer commandBuffer
,
2485 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2486 VkSubpassContents contents
)
2488 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2489 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2490 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2492 cmd_buffer
->state
.framebuffer
= framebuffer
;
2493 cmd_buffer
->state
.pass
= pass
;
2494 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2496 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2498 /* If we failed to setup the attachments we should not try to go further */
2499 if (result
!= VK_SUCCESS
) {
2500 assert(anv_batch_has_error(&cmd_buffer
->batch
));
2504 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2506 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2508 cmd_buffer
->state
.pending_pipe_bits
|=
2509 cmd_buffer
->state
.pass
->subpass_flushes
[0];
2512 void genX(CmdNextSubpass
)(
2513 VkCommandBuffer commandBuffer
,
2514 VkSubpassContents contents
)
2516 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2518 if (anv_batch_has_error(&cmd_buffer
->batch
))
2521 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2523 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2525 /* Perform transitions to the final layout after all writes have occurred.
2527 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2529 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2531 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
2532 cmd_buffer
->state
.pending_pipe_bits
|=
2533 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
2536 void genX(CmdEndRenderPass
)(
2537 VkCommandBuffer commandBuffer
)
2539 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2541 if (anv_batch_has_error(&cmd_buffer
->batch
))
2544 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2546 /* Perform transitions to the final layout after all writes have occurred.
2548 cmd_buffer_subpass_transition_layouts(cmd_buffer
, true);
2550 cmd_buffer
->state
.pending_pipe_bits
|=
2551 cmd_buffer
->state
.pass
->subpass_flushes
[cmd_buffer
->state
.pass
->subpass_count
];
2553 cmd_buffer
->state
.hiz_enabled
= false;
2556 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);
2559 /* Remove references to render pass specific state. This enables us to
2560 * detect whether or not we're in a renderpass.
2562 cmd_buffer
->state
.framebuffer
= NULL
;
2563 cmd_buffer
->state
.pass
= NULL
;
2564 cmd_buffer
->state
.subpass
= NULL
;