2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "common/gen_l3_config.h"
31 #include "genxml/gen_macros.h"
32 #include "genxml/genX_pack.h"
35 emit_lrm(struct anv_batch
*batch
,
36 uint32_t reg
, struct anv_bo
*bo
, uint32_t offset
)
38 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
39 lrm
.RegisterAddress
= reg
;
40 lrm
.MemoryAddress
= (struct anv_address
) { bo
, offset
};
45 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
47 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
48 lri
.RegisterOffset
= reg
;
54 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
56 struct anv_device
*device
= cmd_buffer
->device
;
58 /* Emit a render target cache flush.
60 * This isn't documented anywhere in the PRM. However, it seems to be
61 * necessary prior to changing the surface state base adress. Without
62 * this, we get GPU hangs when using multi-level command buffers which
63 * clear depth, reset state base address, and then go render stuff.
65 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
66 pc
.DCFlushEnable
= true;
67 pc
.RenderTargetCacheFlushEnable
= true;
68 pc
.CommandStreamerStallEnable
= true;
71 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
72 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
73 sba
.GeneralStateMemoryObjectControlState
= GENX(MOCS
);
74 sba
.GeneralStateBaseAddressModifyEnable
= true;
76 sba
.SurfaceStateBaseAddress
=
77 anv_cmd_buffer_surface_base_address(cmd_buffer
);
78 sba
.SurfaceStateMemoryObjectControlState
= GENX(MOCS
);
79 sba
.SurfaceStateBaseAddressModifyEnable
= true;
81 sba
.DynamicStateBaseAddress
=
82 (struct anv_address
) { &device
->dynamic_state_block_pool
.bo
, 0 };
83 sba
.DynamicStateMemoryObjectControlState
= GENX(MOCS
);
84 sba
.DynamicStateBaseAddressModifyEnable
= true;
86 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
87 sba
.IndirectObjectMemoryObjectControlState
= GENX(MOCS
);
88 sba
.IndirectObjectBaseAddressModifyEnable
= true;
90 sba
.InstructionBaseAddress
=
91 (struct anv_address
) { &device
->instruction_block_pool
.bo
, 0 };
92 sba
.InstructionMemoryObjectControlState
= GENX(MOCS
);
93 sba
.InstructionBaseAddressModifyEnable
= true;
96 /* Broadwell requires that we specify a buffer size for a bunch of
97 * these fields. However, since we will be growing the BO's live, we
98 * just set them all to the maximum.
100 sba
.GeneralStateBufferSize
= 0xfffff;
101 sba
.GeneralStateBufferSizeModifyEnable
= true;
102 sba
.DynamicStateBufferSize
= 0xfffff;
103 sba
.DynamicStateBufferSizeModifyEnable
= true;
104 sba
.IndirectObjectBufferSize
= 0xfffff;
105 sba
.IndirectObjectBufferSizeModifyEnable
= true;
106 sba
.InstructionBufferSize
= 0xfffff;
107 sba
.InstructionBuffersizeModifyEnable
= true;
111 /* After re-setting the surface state base address, we have to do some
112 * cache flusing so that the sampler engine will pick up the new
113 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
114 * Shared Function > 3D Sampler > State > State Caching (page 96):
116 * Coherency with system memory in the state cache, like the texture
117 * cache is handled partially by software. It is expected that the
118 * command stream or shader will issue Cache Flush operation or
119 * Cache_Flush sampler message to ensure that the L1 cache remains
120 * coherent with system memory.
124 * Whenever the value of the Dynamic_State_Base_Addr,
125 * Surface_State_Base_Addr are altered, the L1 state cache must be
126 * invalidated to ensure the new surface or sampler state is fetched
127 * from system memory.
129 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
130 * which, according the PIPE_CONTROL instruction documentation in the
133 * Setting this bit is independent of any other bit in this packet.
134 * This bit controls the invalidation of the L1 and L2 state caches
135 * at the top of the pipe i.e. at the parsing time.
137 * Unfortunately, experimentation seems to indicate that state cache
138 * invalidation through a PIPE_CONTROL does nothing whatsoever in
139 * regards to surface state and binding tables. In stead, it seems that
140 * invalidating the texture cache is what is actually needed.
142 * XXX: As far as we have been able to determine through
143 * experimentation, shows that flush the texture cache appears to be
144 * sufficient. The theory here is that all of the sampling/rendering
145 * units cache the binding table in the texture cache. However, we have
146 * yet to be able to actually confirm this.
148 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
149 pc
.TextureCacheInvalidationEnable
= true;
150 pc
.ConstantCacheInvalidationEnable
= true;
151 pc
.StateCacheInvalidationEnable
= true;
156 add_surface_state_reloc(struct anv_cmd_buffer
*cmd_buffer
,
157 struct anv_state state
,
158 struct anv_bo
*bo
, uint32_t offset
)
160 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
162 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
163 state
.offset
+ isl_dev
->ss
.addr_offset
, bo
, offset
);
167 add_image_view_relocs(struct anv_cmd_buffer
*cmd_buffer
,
168 const struct anv_image_view
*iview
,
169 enum isl_aux_usage aux_usage
,
170 struct anv_state state
)
172 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
174 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
175 state
.offset
+ isl_dev
->ss
.addr_offset
,
176 iview
->bo
, iview
->offset
);
178 if (aux_usage
!= ISL_AUX_USAGE_NONE
) {
179 uint32_t aux_offset
= iview
->offset
+ iview
->image
->aux_surface
.offset
;
181 /* On gen7 and prior, the bottom 12 bits of the MCS base address are
182 * used to store other information. This should be ok, however, because
183 * surface buffer addresses are always 4K page alinged.
185 assert((aux_offset
& 0xfff) == 0);
186 uint32_t *aux_addr_dw
= state
.map
+ isl_dev
->ss
.aux_addr_offset
;
187 aux_offset
+= *aux_addr_dw
& 0xfff;
189 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
190 state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
191 iview
->bo
, aux_offset
);
196 color_is_zero_one(VkClearColorValue value
, enum isl_format format
)
198 if (isl_format_has_int_channel(format
)) {
199 for (unsigned i
= 0; i
< 4; i
++) {
200 if (value
.int32
[i
] != 0 && value
.int32
[i
] != 1)
204 for (unsigned i
= 0; i
< 4; i
++) {
205 if (value
.float32
[i
] != 0.0f
&& value
.float32
[i
] != 1.0f
)
214 color_attachment_compute_aux_usage(struct anv_device
*device
,
215 struct anv_attachment_state
*att_state
,
216 struct anv_image_view
*iview
,
217 VkRect2D render_area
,
218 union isl_color_value
*fast_clear_color
)
220 if (iview
->image
->aux_surface
.isl
.size
== 0) {
221 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
222 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
223 att_state
->fast_clear
= false;
227 assert(iview
->image
->aux_surface
.isl
.usage
& ISL_SURF_USAGE_CCS_BIT
);
229 att_state
->clear_color_is_zero_one
=
230 color_is_zero_one(att_state
->clear_value
.color
, iview
->isl
.format
);
232 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
233 /* Start off assuming fast clears are possible */
234 att_state
->fast_clear
= true;
236 /* Potentially, we could do partial fast-clears but doing so has crazy
237 * alignment restrictions. It's easier to just restrict to full size
238 * fast clears for now.
240 if (render_area
.offset
.x
!= 0 ||
241 render_area
.offset
.y
!= 0 ||
242 render_area
.extent
.width
!= iview
->extent
.width
||
243 render_area
.extent
.height
!= iview
->extent
.height
)
244 att_state
->fast_clear
= false;
247 /* On gen7, we can't do multi-LOD or multi-layer fast-clears. We
248 * technically can, but it comes with crazy restrictions that we
249 * don't want to deal with now.
251 if (iview
->isl
.base_level
> 0 ||
252 iview
->isl
.base_array_layer
> 0 ||
253 iview
->isl
.array_len
> 1)
254 att_state
->fast_clear
= false;
257 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
258 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
259 att_state
->fast_clear
= false;
261 if (att_state
->fast_clear
) {
262 memcpy(fast_clear_color
->u32
, att_state
->clear_value
.color
.uint32
,
263 sizeof(fast_clear_color
->u32
));
266 att_state
->fast_clear
= false;
270 * TODO: Consider using a heuristic to determine if temporarily enabling
271 * CCS_E for this image view would be beneficial.
273 * While fast-clear resolves and partial resolves are fairly cheap in the
274 * case where you render to most of the pixels, full resolves are not
275 * because they potentially involve reading and writing the entire
276 * framebuffer. If we can't texture with CCS_E, we should leave it off and
277 * limit ourselves to fast clears.
279 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_CCS_E
) {
280 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_E
;
281 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_E
;
282 } else if (att_state
->fast_clear
) {
283 att_state
->aux_usage
= ISL_AUX_USAGE_CCS_D
;
285 !isl_format_supports_ccs_e(&device
->info
, iview
->isl
.format
)) {
286 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
288 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
289 * setting is only allowed if Surface Format supported for Fast
290 * Clear. In addition, if the surface is bound to the sampling
291 * engine, Surface Format must be supported for Render Target
292 * Compression for surfaces bound to the sampling engine."
294 * In other words, we can't sample from a fast-cleared image if it
295 * doesn't also support color compression.
297 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
298 } else if (GEN_GEN
== 8) {
299 /* Broadwell can sample from fast-cleared images */
300 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
302 /* Ivy Bridge and Haswell cannot */
303 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
306 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
307 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
312 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
314 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
317 /* We only allocate input attachment states for color surfaces. Compression
318 * is not yet enabled for depth textures and stencil doesn't allow
319 * compression so we can just use the texture surface state from the view.
321 return vk_format_is_color(att
->format
);
324 static enum isl_aux_usage
325 layout_to_hiz_usage(VkImageLayout layout
, uint8_t samples
)
328 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
:
329 return ISL_AUX_USAGE_HIZ
;
330 case VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL
:
331 case VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
:
332 if (anv_can_sample_with_hiz(GEN_GEN
, samples
))
333 return ISL_AUX_USAGE_HIZ
;
335 case VK_IMAGE_LAYOUT_GENERAL
:
336 /* This buffer could be used as a source or destination in a transfer
337 * operation. Transfer operations current don't perform HiZ-enabled reads
341 return ISL_AUX_USAGE_NONE
;
345 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
346 * the initial layout is undefined, the HiZ buffer and depth buffer will
347 * represent the same data at the end of this operation.
350 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
351 const struct anv_image
*image
,
352 VkImageLayout initial_layout
,
353 VkImageLayout final_layout
)
357 if (image
->aux_usage
!= ISL_AUX_USAGE_HIZ
|| final_layout
== initial_layout
)
360 const bool hiz_enabled
= layout_to_hiz_usage(initial_layout
, image
->samples
) ==
362 const bool enable_hiz
= layout_to_hiz_usage(final_layout
, image
->samples
) ==
365 enum blorp_hiz_op hiz_op
;
366 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
) {
367 /* We've already initialized the aux HiZ buffer at BindImageMemory time,
368 * so there's no need to perform a HIZ resolve or clear to avoid GPU hangs.
369 * This initial layout indicates that the user doesn't care about the data
370 * that's currently in the buffer, so resolves are not necessary except
371 * for the special case noted below.
373 hiz_op
= BLORP_HIZ_OP_NONE
;
374 } else if (hiz_enabled
&& !enable_hiz
) {
375 hiz_op
= BLORP_HIZ_OP_DEPTH_RESOLVE
;
376 } else if (!hiz_enabled
&& enable_hiz
) {
377 hiz_op
= BLORP_HIZ_OP_HIZ_RESOLVE
;
379 assert(hiz_enabled
== enable_hiz
);
380 /* If the same buffer will be used, no resolves are necessary except for
381 * the special case noted below.
383 hiz_op
= BLORP_HIZ_OP_NONE
;
386 if (hiz_op
!= BLORP_HIZ_OP_NONE
)
387 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, hiz_op
);
389 /* Images that have sampling with HiZ enabled cause all shader sampling to
390 * load data with the HiZ buffer. Therefore, in the case of transitioning to
391 * the general layout - which currently routes all writes to the depth
392 * buffer - we must ensure that the HiZ buffer remains consistent with the
393 * depth buffer by performing an additional HIZ resolve if the operation
394 * required by this transition was not already a HiZ resolve.
396 if (final_layout
== VK_IMAGE_LAYOUT_GENERAL
&&
397 anv_can_sample_with_hiz(GEN_GEN
, image
->samples
) &&
398 hiz_op
!= BLORP_HIZ_OP_HIZ_RESOLVE
) {
399 anv_gen8_hiz_op_resolve(cmd_buffer
, image
, BLORP_HIZ_OP_HIZ_RESOLVE
);
405 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
408 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
409 struct anv_render_pass
*pass
,
410 const VkRenderPassBeginInfo
*begin
)
412 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
413 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
415 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
417 if (pass
->attachment_count
== 0) {
418 state
->attachments
= NULL
;
422 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
423 pass
->attachment_count
*
424 sizeof(state
->attachments
[0]),
425 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
426 if (state
->attachments
== NULL
) {
427 /* FIXME: Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
431 bool need_null_state
= false;
432 unsigned num_states
= 0;
433 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
434 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
437 /* We need a null state for any depth-stencil-only subpasses.
438 * Importantly, this includes depth/stencil clears so we create one
439 * whenever we have depth or stencil
441 need_null_state
= true;
444 if (need_input_attachment_state(&pass
->attachments
[i
]))
447 num_states
+= need_null_state
;
449 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
450 state
->render_pass_states
=
451 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
452 num_states
* ss_stride
, isl_dev
->ss
.align
);
454 struct anv_state next_state
= state
->render_pass_states
;
455 next_state
.alloc_size
= isl_dev
->ss
.size
;
457 if (need_null_state
) {
458 state
->null_surface_state
= next_state
;
459 next_state
.offset
+= ss_stride
;
460 next_state
.map
+= ss_stride
;
463 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
464 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
465 state
->attachments
[i
].color_rt_state
= next_state
;
466 next_state
.offset
+= ss_stride
;
467 next_state
.map
+= ss_stride
;
470 if (need_input_attachment_state(&pass
->attachments
[i
])) {
471 state
->attachments
[i
].input_att_state
= next_state
;
472 next_state
.offset
+= ss_stride
;
473 next_state
.map
+= ss_stride
;
476 assert(next_state
.offset
== state
->render_pass_states
.offset
+
477 state
->render_pass_states
.alloc_size
);
480 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, begin
->framebuffer
);
481 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
483 if (need_null_state
) {
484 struct GENX(RENDER_SURFACE_STATE
) null_ss
= {
485 .SurfaceType
= SURFTYPE_NULL
,
486 .SurfaceArray
= framebuffer
->layers
> 0,
487 .SurfaceFormat
= ISL_FORMAT_R8G8B8A8_UNORM
,
491 .TiledSurface
= true,
493 .Width
= framebuffer
->width
- 1,
494 .Height
= framebuffer
->height
- 1,
495 .Depth
= framebuffer
->layers
- 1,
496 .RenderTargetViewExtent
= framebuffer
->layers
- 1,
498 GENX(RENDER_SURFACE_STATE_pack
)(NULL
, state
->null_surface_state
.map
,
502 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
503 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
504 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
505 VkImageAspectFlags clear_aspects
= 0;
507 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
508 /* color attachment */
509 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
510 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
513 /* depthstencil attachment */
514 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
515 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
516 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
518 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
519 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
520 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
524 state
->attachments
[i
].current_layout
= att
->initial_layout
;
525 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
527 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
529 struct anv_image_view
*iview
= framebuffer
->attachments
[i
];
530 assert(iview
->vk_format
== att
->format
);
532 union isl_color_value clear_color
= { .u32
= { 0, } };
533 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
534 color_attachment_compute_aux_usage(cmd_buffer
->device
,
535 &state
->attachments
[i
],
536 iview
, begin
->renderArea
,
539 struct isl_view view
= iview
->isl
;
540 view
.usage
|= ISL_SURF_USAGE_RENDER_TARGET_BIT
;
541 view
.swizzle
= anv_swizzle_for_render(view
.swizzle
);
542 isl_surf_fill_state(isl_dev
,
543 state
->attachments
[i
].color_rt_state
.map
,
544 .surf
= &iview
->image
->color_surface
.isl
,
546 .aux_surf
= &iview
->image
->aux_surface
.isl
,
547 .aux_usage
= state
->attachments
[i
].aux_usage
,
548 .clear_color
= clear_color
,
549 .mocs
= cmd_buffer
->device
->default_mocs
);
551 add_image_view_relocs(cmd_buffer
, iview
,
552 state
->attachments
[i
].aux_usage
,
553 state
->attachments
[i
].color_rt_state
);
555 if (iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
556 state
->attachments
[i
].aux_usage
=
557 layout_to_hiz_usage(att
->initial_layout
, iview
->image
->samples
);
559 state
->attachments
[i
].aux_usage
= ISL_AUX_USAGE_NONE
;
561 state
->attachments
[i
].input_aux_usage
= ISL_AUX_USAGE_NONE
;
564 if (need_input_attachment_state(&pass
->attachments
[i
])) {
565 struct isl_view view
= iview
->isl
;
566 view
.usage
|= ISL_SURF_USAGE_TEXTURE_BIT
;
567 isl_surf_fill_state(isl_dev
,
568 state
->attachments
[i
].input_att_state
.map
,
569 .surf
= &iview
->image
->color_surface
.isl
,
571 .aux_surf
= &iview
->image
->aux_surface
.isl
,
572 .aux_usage
= state
->attachments
[i
].input_aux_usage
,
573 .clear_color
= clear_color
,
574 .mocs
= cmd_buffer
->device
->default_mocs
);
576 add_image_view_relocs(cmd_buffer
, iview
,
577 state
->attachments
[i
].input_aux_usage
,
578 state
->attachments
[i
].input_att_state
);
582 anv_state_flush(cmd_buffer
->device
, state
->render_pass_states
);
587 genX(BeginCommandBuffer
)(
588 VkCommandBuffer commandBuffer
,
589 const VkCommandBufferBeginInfo
* pBeginInfo
)
591 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
593 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
594 * command buffer's state. Otherwise, we must *reset* its state. In both
597 * From the Vulkan 1.0 spec:
599 * If a command buffer is in the executable state and the command buffer
600 * was allocated from a command pool with the
601 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
602 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
603 * as if vkResetCommandBuffer had been called with
604 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
605 * the command buffer in the recording state.
607 anv_cmd_buffer_reset(cmd_buffer
);
609 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
611 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
612 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
614 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
616 if (cmd_buffer
->usage_flags
&
617 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
618 cmd_buffer
->state
.pass
=
619 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
620 cmd_buffer
->state
.subpass
=
621 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
622 cmd_buffer
->state
.framebuffer
= NULL
;
624 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, cmd_buffer
->state
.pass
,
627 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
634 genX(EndCommandBuffer
)(
635 VkCommandBuffer commandBuffer
)
637 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
639 /* We want every command buffer to start with the PMA fix in a known state,
640 * so we disable it at the end of the command buffer.
642 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
644 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
646 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
652 genX(CmdExecuteCommands
)(
653 VkCommandBuffer commandBuffer
,
654 uint32_t commandBufferCount
,
655 const VkCommandBuffer
* pCmdBuffers
)
657 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
659 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
661 /* The secondary command buffers will assume that the PMA fix is disabled
662 * when they begin executing. Make sure this is true.
664 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
666 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
667 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
669 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
671 if (secondary
->usage_flags
&
672 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
673 /* If we're continuing a render pass from the primary, we need to
674 * copy the surface states for the current subpass into the storage
675 * we allocated for them in BeginCommandBuffer.
677 struct anv_bo
*ss_bo
= &primary
->device
->surface_state_block_pool
.bo
;
678 struct anv_state src_state
= primary
->state
.render_pass_states
;
679 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
680 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
682 genX(cmd_buffer_gpu_memcpy
)(primary
, ss_bo
, dst_state
.offset
,
683 ss_bo
, src_state
.offset
,
684 src_state
.alloc_size
);
687 anv_cmd_buffer_add_secondary(primary
, secondary
);
690 /* Each of the secondary command buffers will use its own state base
691 * address. We need to re-emit state base address for the primary after
692 * all of the secondaries are done.
694 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
697 genX(cmd_buffer_emit_state_base_address
)(primary
);
700 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
701 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
702 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
705 * Program the hardware to use the specified L3 configuration.
708 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
709 const struct gen_l3_config
*cfg
)
712 if (cfg
== cmd_buffer
->state
.current_l3_config
)
715 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
716 fprintf(stderr
, "L3 config transition: ");
717 gen_dump_l3_config(cfg
, stderr
);
720 const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
722 /* According to the hardware docs, the L3 partitioning can only be changed
723 * while the pipeline is completely drained and the caches are flushed,
724 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
726 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
727 pc
.DCFlushEnable
= true;
728 pc
.PostSyncOperation
= NoWrite
;
729 pc
.CommandStreamerStallEnable
= true;
732 /* ...followed by a second pipelined PIPE_CONTROL that initiates
733 * invalidation of the relevant caches. Note that because RO invalidation
734 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
735 * command is processed by the CS) we cannot combine it with the previous
736 * stalling flush as the hardware documentation suggests, because that
737 * would cause the CS to stall on previous rendering *after* RO
738 * invalidation and wouldn't prevent the RO caches from being polluted by
739 * concurrent rendering before the stall completes. This intentionally
740 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
741 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
742 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
743 * already guarantee that there is no concurrent GPGPU kernel execution
744 * (see SKL HSD 2132585).
746 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
747 pc
.TextureCacheInvalidationEnable
= true;
748 pc
.ConstantCacheInvalidationEnable
= true;
749 pc
.InstructionCacheInvalidateEnable
= true;
750 pc
.StateCacheInvalidationEnable
= true;
751 pc
.PostSyncOperation
= NoWrite
;
754 /* Now send a third stalling flush to make sure that invalidation is
755 * complete when the L3 configuration registers are modified.
757 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
758 pc
.DCFlushEnable
= true;
759 pc
.PostSyncOperation
= NoWrite
;
760 pc
.CommandStreamerStallEnable
= true;
765 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
768 anv_pack_struct(&l3cr
, GENX(L3CNTLREG
),
769 .SLMEnable
= has_slm
,
770 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
771 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
772 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
773 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
775 /* Set up the L3 partitioning. */
776 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG_num
), l3cr
);
780 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
781 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
783 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
785 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
788 assert(!cfg
->n
[GEN_L3P_ALL
]);
790 /* When enabled SLM only uses a portion of the L3 on half of the banks,
791 * the matching space on the remaining banks has to be allocated to a
792 * client (URB for all validated configurations) set to the
793 * lower-bandwidth 2-bank address hashing mode.
795 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
796 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
797 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
799 /* Minimum number of ways that can be allocated to the URB. */
800 MAYBE_UNUSED
const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
801 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
803 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
804 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
805 .ConvertDC_UC
= !has_dc
,
806 .ConvertIS_UC
= !has_is
,
807 .ConvertC_UC
= !has_c
,
808 .ConvertT_UC
= !has_t
);
810 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
811 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
812 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
814 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
815 .SLMEnable
= has_slm
,
816 .URBLowBandwidth
= urb_low_bw
,
817 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
819 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
821 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
822 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
824 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
825 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
827 .CAllocation
= cfg
->n
[GEN_L3P_C
],
829 .TAllocation
= cfg
->n
[GEN_L3P_T
],
832 /* Set up the L3 partitioning. */
833 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
834 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
835 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
838 if (cmd_buffer
->device
->instance
->physicalDevice
.cmd_parser_version
>= 4) {
839 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
840 * them disabled to avoid crashing the system hard.
842 uint32_t scratch1
, chicken3
;
843 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
844 .L3AtomicDisable
= !has_dc
);
845 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
846 .L3AtomicDisableMask
= true,
847 .L3AtomicDisable
= !has_dc
);
848 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
849 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
855 cmd_buffer
->state
.current_l3_config
= cfg
;
859 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
861 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
863 /* Flushes are pipelined while invalidations are handled immediately.
864 * Therefore, if we're flushing anything then we need to schedule a stall
865 * before any invalidations can happen.
867 if (bits
& ANV_PIPE_FLUSH_BITS
)
868 bits
|= ANV_PIPE_NEEDS_CS_STALL_BIT
;
870 /* If we're going to do an invalidate and we have a pending CS stall that
871 * has yet to be resolved, we do the CS stall now.
873 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
874 (bits
& ANV_PIPE_NEEDS_CS_STALL_BIT
)) {
875 bits
|= ANV_PIPE_CS_STALL_BIT
;
876 bits
&= ~ANV_PIPE_NEEDS_CS_STALL_BIT
;
879 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
)) {
880 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
881 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
882 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
883 pipe
.RenderTargetCacheFlushEnable
=
884 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
886 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
887 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
888 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
891 * According to the Broadwell documentation, any PIPE_CONTROL with the
892 * "Command Streamer Stall" bit set must also have another bit set,
893 * with five different options:
895 * - Render Target Cache Flush
896 * - Depth Cache Flush
897 * - Stall at Pixel Scoreboard
898 * - Post-Sync Operation
902 * I chose "Stall at Pixel Scoreboard" since that's what we use in
903 * mesa and it seems to work fine. The choice is fairly arbitrary.
905 if ((bits
& ANV_PIPE_CS_STALL_BIT
) &&
906 !(bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_DEPTH_STALL_BIT
|
907 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
)))
908 pipe
.StallAtPixelScoreboard
= true;
911 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
);
914 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
915 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
916 pipe
.StateCacheInvalidationEnable
=
917 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
918 pipe
.ConstantCacheInvalidationEnable
=
919 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
920 pipe
.VFCacheInvalidationEnable
=
921 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
922 pipe
.TextureCacheInvalidationEnable
=
923 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
924 pipe
.InstructionCacheInvalidateEnable
=
925 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
928 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
931 cmd_buffer
->state
.pending_pipe_bits
= bits
;
934 void genX(CmdPipelineBarrier
)(
935 VkCommandBuffer commandBuffer
,
936 VkPipelineStageFlags srcStageMask
,
937 VkPipelineStageFlags destStageMask
,
939 uint32_t memoryBarrierCount
,
940 const VkMemoryBarrier
* pMemoryBarriers
,
941 uint32_t bufferMemoryBarrierCount
,
942 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
943 uint32_t imageMemoryBarrierCount
,
944 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
946 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
949 /* XXX: Right now, we're really dumb and just flush whatever categories
950 * the app asks for. One of these days we may make this a bit better
951 * but right now that's all the hardware allows for in most areas.
953 VkAccessFlags src_flags
= 0;
954 VkAccessFlags dst_flags
= 0;
956 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
957 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
958 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
961 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
962 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
963 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
966 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
967 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
968 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
969 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
970 if (pImageMemoryBarriers
[i
].subresourceRange
.aspectMask
&
971 VK_IMAGE_ASPECT_DEPTH_BIT
) {
972 transition_depth_buffer(cmd_buffer
, image
,
973 pImageMemoryBarriers
[i
].oldLayout
,
974 pImageMemoryBarriers
[i
].newLayout
);
978 enum anv_pipe_bits pipe_bits
= 0;
980 for_each_bit(b
, src_flags
) {
981 switch ((VkAccessFlagBits
)(1 << b
)) {
982 case VK_ACCESS_SHADER_WRITE_BIT
:
983 pipe_bits
|= ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
985 case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
:
986 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
988 case VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
:
989 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
991 case VK_ACCESS_TRANSFER_WRITE_BIT
:
992 pipe_bits
|= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
993 pipe_bits
|= ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
996 break; /* Nothing to do */
1000 for_each_bit(b
, dst_flags
) {
1001 switch ((VkAccessFlagBits
)(1 << b
)) {
1002 case VK_ACCESS_INDIRECT_COMMAND_READ_BIT
:
1003 case VK_ACCESS_INDEX_READ_BIT
:
1004 case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
:
1005 pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1007 case VK_ACCESS_UNIFORM_READ_BIT
:
1008 pipe_bits
|= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
1009 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1011 case VK_ACCESS_SHADER_READ_BIT
:
1012 case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
:
1013 case VK_ACCESS_TRANSFER_READ_BIT
:
1014 pipe_bits
|= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
1017 break; /* Nothing to do */
1021 cmd_buffer
->state
.pending_pipe_bits
|= pipe_bits
;
1025 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1027 VkShaderStageFlags stages
= cmd_buffer
->state
.pipeline
->active_stages
;
1029 /* In order to avoid thrash, we assume that vertex and fragment stages
1030 * always exist. In the rare case where one is missing *and* the other
1031 * uses push concstants, this may be suboptimal. However, avoiding stalls
1032 * seems more important.
1034 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
1036 if (stages
== cmd_buffer
->state
.push_constant_stages
)
1040 const unsigned push_constant_kb
= 32;
1041 #elif GEN_IS_HASWELL
1042 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
1044 const unsigned push_constant_kb
= 16;
1047 const unsigned num_stages
=
1048 _mesa_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
1049 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
1051 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
1052 * units of 2KB. Incidentally, these are the same platforms that have
1053 * 32KB worth of push constant space.
1055 if (push_constant_kb
== 32)
1056 size_per_stage
&= ~1u;
1058 uint32_t kb_used
= 0;
1059 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
1060 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
1061 anv_batch_emit(&cmd_buffer
->batch
,
1062 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
1063 alloc
._3DCommandSubOpcode
= 18 + i
;
1064 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
1065 alloc
.ConstantBufferSize
= push_size
;
1067 kb_used
+= push_size
;
1070 anv_batch_emit(&cmd_buffer
->batch
,
1071 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
1072 alloc
.ConstantBufferOffset
= kb_used
;
1073 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
1076 cmd_buffer
->state
.push_constant_stages
= stages
;
1078 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
1080 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
1081 * the next 3DPRIMITIVE command after programming the
1082 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
1084 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
1085 * pipeline setup, we need to dirty push constants.
1087 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1091 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
1092 gl_shader_stage stage
,
1093 struct anv_state
*bt_state
)
1095 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
1096 struct anv_pipeline
*pipeline
;
1097 uint32_t bias
, state_offset
;
1100 case MESA_SHADER_COMPUTE
:
1101 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1105 pipeline
= cmd_buffer
->state
.pipeline
;
1110 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1111 *bt_state
= (struct anv_state
) { 0, };
1115 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1116 if (bias
+ map
->surface_count
== 0) {
1117 *bt_state
= (struct anv_state
) { 0, };
1121 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
1122 bias
+ map
->surface_count
,
1124 uint32_t *bt_map
= bt_state
->map
;
1126 if (bt_state
->map
== NULL
)
1127 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1129 if (stage
== MESA_SHADER_COMPUTE
&&
1130 get_cs_prog_data(cmd_buffer
->state
.compute_pipeline
)->uses_num_work_groups
) {
1131 struct anv_bo
*bo
= cmd_buffer
->state
.num_workgroups_bo
;
1132 uint32_t bo_offset
= cmd_buffer
->state
.num_workgroups_offset
;
1134 struct anv_state surface_state
;
1136 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
1138 const enum isl_format format
=
1139 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
1140 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
1141 format
, bo_offset
, 12, 1);
1143 bt_map
[0] = surface_state
.offset
+ state_offset
;
1144 add_surface_state_reloc(cmd_buffer
, surface_state
, bo
, bo_offset
);
1147 if (map
->surface_count
== 0)
1150 if (map
->image_count
> 0) {
1152 anv_cmd_buffer_ensure_push_constant_field(cmd_buffer
, stage
, images
);
1153 if (result
!= VK_SUCCESS
)
1156 cmd_buffer
->state
.push_constants_dirty
|= 1 << stage
;
1160 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
1161 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
1163 struct anv_state surface_state
;
1165 if (binding
->set
== ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
) {
1166 /* Color attachment binding */
1167 assert(stage
== MESA_SHADER_FRAGMENT
);
1168 assert(binding
->binding
== 0);
1169 if (binding
->index
< subpass
->color_count
) {
1170 const unsigned att
= subpass
->color_attachments
[binding
->index
];
1171 surface_state
= cmd_buffer
->state
.attachments
[att
].color_rt_state
;
1173 surface_state
= cmd_buffer
->state
.null_surface_state
;
1176 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1180 struct anv_descriptor_set
*set
=
1181 cmd_buffer
->state
.descriptors
[binding
->set
];
1182 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1183 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1185 switch (desc
->type
) {
1186 case VK_DESCRIPTOR_TYPE_SAMPLER
:
1187 /* Nothing for us to do here */
1190 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
1191 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
1192 surface_state
= desc
->image_view
->sampler_surface_state
;
1193 assert(surface_state
.alloc_size
);
1194 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1195 desc
->image_view
->image
->aux_usage
,
1199 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
1200 assert(stage
== MESA_SHADER_FRAGMENT
);
1201 if (desc
->image_view
->aspect_mask
!= VK_IMAGE_ASPECT_COLOR_BIT
) {
1202 /* For depth and stencil input attachments, we treat it like any
1203 * old texture that a user may have bound.
1205 surface_state
= desc
->image_view
->sampler_surface_state
;
1206 assert(surface_state
.alloc_size
);
1207 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1208 desc
->image_view
->image
->aux_usage
,
1211 /* For color input attachments, we create the surface state at
1212 * vkBeginRenderPass time so that we can include aux and clear
1213 * color information.
1215 assert(binding
->input_attachment_index
< subpass
->input_count
);
1216 const unsigned subpass_att
= binding
->input_attachment_index
;
1217 const unsigned att
= subpass
->input_attachments
[subpass_att
];
1218 surface_state
= cmd_buffer
->state
.attachments
[att
].input_att_state
;
1222 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
1223 surface_state
= (binding
->write_only
)
1224 ? desc
->image_view
->writeonly_storage_surface_state
1225 : desc
->image_view
->storage_surface_state
;
1226 assert(surface_state
.alloc_size
);
1227 add_image_view_relocs(cmd_buffer
, desc
->image_view
,
1228 desc
->image_view
->image
->aux_usage
,
1231 struct brw_image_param
*image_param
=
1232 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1234 *image_param
= desc
->image_view
->storage_image_param
;
1235 image_param
->surface_idx
= bias
+ s
;
1239 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
1240 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
1241 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
1242 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
1243 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
1244 surface_state
= desc
->buffer_view
->surface_state
;
1245 assert(surface_state
.alloc_size
);
1246 add_surface_state_reloc(cmd_buffer
, surface_state
,
1247 desc
->buffer_view
->bo
,
1248 desc
->buffer_view
->offset
);
1251 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
1252 surface_state
= (binding
->write_only
)
1253 ? desc
->buffer_view
->writeonly_storage_surface_state
1254 : desc
->buffer_view
->storage_surface_state
;
1255 assert(surface_state
.alloc_size
);
1256 add_surface_state_reloc(cmd_buffer
, surface_state
,
1257 desc
->buffer_view
->bo
,
1258 desc
->buffer_view
->offset
);
1260 struct brw_image_param
*image_param
=
1261 &cmd_buffer
->state
.push_constants
[stage
]->images
[image
++];
1263 *image_param
= desc
->buffer_view
->storage_image_param
;
1264 image_param
->surface_idx
= bias
+ s
;
1268 assert(!"Invalid descriptor type");
1272 bt_map
[bias
+ s
] = surface_state
.offset
+ state_offset
;
1274 assert(image
== map
->image_count
);
1277 anv_state_flush(cmd_buffer
->device
, *bt_state
);
1283 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
1284 gl_shader_stage stage
,
1285 struct anv_state
*state
)
1287 struct anv_pipeline
*pipeline
;
1289 if (stage
== MESA_SHADER_COMPUTE
)
1290 pipeline
= cmd_buffer
->state
.compute_pipeline
;
1292 pipeline
= cmd_buffer
->state
.pipeline
;
1294 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
1295 *state
= (struct anv_state
) { 0, };
1299 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
1300 if (map
->sampler_count
== 0) {
1301 *state
= (struct anv_state
) { 0, };
1305 uint32_t size
= map
->sampler_count
* 16;
1306 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
1308 if (state
->map
== NULL
)
1309 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1311 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
1312 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
1313 struct anv_descriptor_set
*set
=
1314 cmd_buffer
->state
.descriptors
[binding
->set
];
1315 uint32_t offset
= set
->layout
->binding
[binding
->binding
].descriptor_index
;
1316 struct anv_descriptor
*desc
= &set
->descriptors
[offset
+ binding
->index
];
1318 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
1319 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
1322 struct anv_sampler
*sampler
= desc
->sampler
;
1324 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
1325 * happens to be zero.
1327 if (sampler
== NULL
)
1330 memcpy(state
->map
+ (s
* 16),
1331 sampler
->state
, sizeof(sampler
->state
));
1334 anv_state_flush(cmd_buffer
->device
, *state
);
1340 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
)
1342 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
1343 cmd_buffer
->state
.pipeline
->active_stages
;
1345 VkResult result
= VK_SUCCESS
;
1346 anv_foreach_stage(s
, dirty
) {
1347 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1348 if (result
!= VK_SUCCESS
)
1350 result
= emit_binding_table(cmd_buffer
, s
,
1351 &cmd_buffer
->state
.binding_tables
[s
]);
1352 if (result
!= VK_SUCCESS
)
1356 if (result
!= VK_SUCCESS
) {
1357 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1359 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1360 assert(result
== VK_SUCCESS
);
1362 /* Re-emit state base addresses so we get the new surface state base
1363 * address before we start emitting binding tables etc.
1365 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1367 /* Re-emit all active binding tables */
1368 dirty
|= cmd_buffer
->state
.pipeline
->active_stages
;
1369 anv_foreach_stage(s
, dirty
) {
1370 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
1371 if (result
!= VK_SUCCESS
)
1373 result
= emit_binding_table(cmd_buffer
, s
,
1374 &cmd_buffer
->state
.binding_tables
[s
]);
1375 if (result
!= VK_SUCCESS
)
1380 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
1386 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
1389 static const uint32_t sampler_state_opcodes
[] = {
1390 [MESA_SHADER_VERTEX
] = 43,
1391 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
1392 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
1393 [MESA_SHADER_GEOMETRY
] = 46,
1394 [MESA_SHADER_FRAGMENT
] = 47,
1395 [MESA_SHADER_COMPUTE
] = 0,
1398 static const uint32_t binding_table_opcodes
[] = {
1399 [MESA_SHADER_VERTEX
] = 38,
1400 [MESA_SHADER_TESS_CTRL
] = 39,
1401 [MESA_SHADER_TESS_EVAL
] = 40,
1402 [MESA_SHADER_GEOMETRY
] = 41,
1403 [MESA_SHADER_FRAGMENT
] = 42,
1404 [MESA_SHADER_COMPUTE
] = 0,
1407 anv_foreach_stage(s
, stages
) {
1408 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
1409 anv_batch_emit(&cmd_buffer
->batch
,
1410 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
1411 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
1412 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
1416 /* Always emit binding table pointers if we're asked to, since on SKL
1417 * this is what flushes push constants. */
1418 anv_batch_emit(&cmd_buffer
->batch
,
1419 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
1420 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
1421 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
1427 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
1429 static const uint32_t push_constant_opcodes
[] = {
1430 [MESA_SHADER_VERTEX
] = 21,
1431 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
1432 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
1433 [MESA_SHADER_GEOMETRY
] = 22,
1434 [MESA_SHADER_FRAGMENT
] = 23,
1435 [MESA_SHADER_COMPUTE
] = 0,
1438 VkShaderStageFlags flushed
= 0;
1440 anv_foreach_stage(stage
, cmd_buffer
->state
.push_constants_dirty
) {
1441 if (stage
== MESA_SHADER_COMPUTE
)
1444 struct anv_state state
= anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
1446 if (state
.offset
== 0) {
1447 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
)
1448 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
1450 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
1451 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
],
1452 c
.ConstantBody
= (struct GENX(3DSTATE_CONSTANT_BODY
)) {
1454 .PointerToConstantBuffer2
= { &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, state
.offset
},
1455 .ConstantBuffer2ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1457 .PointerToConstantBuffer0
= { .offset
= state
.offset
},
1458 .ConstantBuffer0ReadLength
= DIV_ROUND_UP(state
.alloc_size
, 32),
1464 flushed
|= mesa_to_vk_shader_stage(stage
);
1467 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_ALL_GRAPHICS
;
1473 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1475 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1478 uint32_t vb_emit
= cmd_buffer
->state
.vb_dirty
& pipeline
->vb_used
;
1480 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
1482 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1484 genX(flush_pipeline_select_3d
)(cmd_buffer
);
1487 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
1488 const uint32_t num_dwords
= 1 + num_buffers
* 4;
1490 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
1491 GENX(3DSTATE_VERTEX_BUFFERS
));
1493 for_each_bit(vb
, vb_emit
) {
1494 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
1495 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
1497 struct GENX(VERTEX_BUFFER_STATE
) state
= {
1498 .VertexBufferIndex
= vb
,
1501 .MemoryObjectControlState
= GENX(MOCS
),
1503 .BufferAccessType
= pipeline
->instancing_enable
[vb
] ? INSTANCEDATA
: VERTEXDATA
,
1504 .InstanceDataStepRate
= 1,
1505 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1508 .AddressModifyEnable
= true,
1509 .BufferPitch
= pipeline
->binding_stride
[vb
],
1510 .BufferStartingAddress
= { buffer
->bo
, buffer
->offset
+ offset
},
1513 .BufferSize
= buffer
->size
- offset
1515 .EndAddress
= { buffer
->bo
, buffer
->offset
+ buffer
->size
- 1},
1519 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
1524 cmd_buffer
->state
.vb_dirty
&= ~vb_emit
;
1526 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1527 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1529 /* The exact descriptor layout is pulled from the pipeline, so we need
1530 * to re-emit binding tables on every pipeline change.
1532 cmd_buffer
->state
.descriptors_dirty
|=
1533 cmd_buffer
->state
.pipeline
->active_stages
;
1535 /* If the pipeline changed, we may need to re-allocate push constant
1538 cmd_buffer_alloc_push_constants(cmd_buffer
);
1542 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
1543 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
1544 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
1546 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
1547 * stall needs to be sent just prior to any 3DSTATE_VS,
1548 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
1549 * 3DSTATE_BINDING_TABLE_POINTER_VS,
1550 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
1551 * PIPE_CONTROL needs to be sent before any combination of VS
1552 * associated 3DSTATE."
1554 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1555 pc
.DepthStallEnable
= true;
1556 pc
.PostSyncOperation
= WriteImmediateData
;
1558 (struct anv_address
) { &cmd_buffer
->device
->workaround_bo
, 0 };
1563 /* Render targets live in the same binding table as fragment descriptors */
1564 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
1565 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
1567 /* We emit the binding tables and sampler tables first, then emit push
1568 * constants and then finally emit binding table and sampler table
1569 * pointers. It has to happen in this order, since emitting the binding
1570 * tables may change the push constants (in case of storage images). After
1571 * emitting push constants, on SKL+ we have to emit the corresponding
1572 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
1575 if (cmd_buffer
->state
.descriptors_dirty
)
1576 dirty
= flush_descriptor_sets(cmd_buffer
);
1578 if (cmd_buffer
->state
.push_constants_dirty
) {
1580 /* On Sky Lake and later, the binding table pointers commands are
1581 * what actually flush the changes to push constant state so we need
1582 * to dirty them so they get re-emitted below.
1584 dirty
|= cmd_buffer_flush_push_constants(cmd_buffer
);
1586 cmd_buffer_flush_push_constants(cmd_buffer
);
1591 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
1593 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
1594 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
1596 if (cmd_buffer
->state
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
1597 ANV_CMD_DIRTY_PIPELINE
)) {
1598 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
1599 pipeline
->depth_clamp_enable
);
1602 if (cmd_buffer
->state
.dirty
& ANV_CMD_DIRTY_DYNAMIC_SCISSOR
)
1603 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
1605 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
1607 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1611 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
1612 struct anv_bo
*bo
, uint32_t offset
,
1613 uint32_t size
, uint32_t index
)
1615 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
1616 GENX(3DSTATE_VERTEX_BUFFERS
));
1618 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
1619 &(struct GENX(VERTEX_BUFFER_STATE
)) {
1620 .VertexBufferIndex
= index
,
1621 .AddressModifyEnable
= true,
1624 .MemoryObjectControlState
= GENX(MOCS
),
1625 .BufferStartingAddress
= { bo
, offset
},
1628 .VertexBufferMemoryObjectControlState
= GENX(MOCS
),
1629 .BufferStartingAddress
= { bo
, offset
},
1630 .EndAddress
= { bo
, offset
+ size
},
1636 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
1637 struct anv_bo
*bo
, uint32_t offset
)
1639 emit_vertex_bo(cmd_buffer
, bo
, offset
, 8, ANV_SVGS_VB_INDEX
);
1643 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
1644 uint32_t base_vertex
, uint32_t base_instance
)
1646 struct anv_state id_state
=
1647 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
1649 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
1650 ((uint32_t *)id_state
.map
)[1] = base_instance
;
1652 anv_state_flush(cmd_buffer
->device
, id_state
);
1654 emit_base_vertex_instance_bo(cmd_buffer
,
1655 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
, id_state
.offset
);
1659 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
1661 struct anv_state state
=
1662 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
1664 ((uint32_t *)state
.map
)[0] = draw_index
;
1666 anv_state_flush(cmd_buffer
->device
, state
);
1668 emit_vertex_bo(cmd_buffer
,
1669 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
,
1670 state
.offset
, 4, ANV_DRAWID_VB_INDEX
);
1674 VkCommandBuffer commandBuffer
,
1675 uint32_t vertexCount
,
1676 uint32_t instanceCount
,
1677 uint32_t firstVertex
,
1678 uint32_t firstInstance
)
1680 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1681 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1682 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1684 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1686 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1687 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
1688 if (vs_prog_data
->uses_drawid
)
1689 emit_draw_index(cmd_buffer
, 0);
1691 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1692 prim
.VertexAccessType
= SEQUENTIAL
;
1693 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1694 prim
.VertexCountPerInstance
= vertexCount
;
1695 prim
.StartVertexLocation
= firstVertex
;
1696 prim
.InstanceCount
= instanceCount
;
1697 prim
.StartInstanceLocation
= firstInstance
;
1698 prim
.BaseVertexLocation
= 0;
1702 void genX(CmdDrawIndexed
)(
1703 VkCommandBuffer commandBuffer
,
1704 uint32_t indexCount
,
1705 uint32_t instanceCount
,
1706 uint32_t firstIndex
,
1707 int32_t vertexOffset
,
1708 uint32_t firstInstance
)
1710 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1711 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1712 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1714 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1716 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1717 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
1718 if (vs_prog_data
->uses_drawid
)
1719 emit_draw_index(cmd_buffer
, 0);
1721 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1722 prim
.VertexAccessType
= RANDOM
;
1723 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1724 prim
.VertexCountPerInstance
= indexCount
;
1725 prim
.StartVertexLocation
= firstIndex
;
1726 prim
.InstanceCount
= instanceCount
;
1727 prim
.StartInstanceLocation
= firstInstance
;
1728 prim
.BaseVertexLocation
= vertexOffset
;
1732 /* Auto-Draw / Indirect Registers */
1733 #define GEN7_3DPRIM_END_OFFSET 0x2420
1734 #define GEN7_3DPRIM_START_VERTEX 0x2430
1735 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
1736 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
1737 #define GEN7_3DPRIM_START_INSTANCE 0x243C
1738 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
1740 void genX(CmdDrawIndirect
)(
1741 VkCommandBuffer commandBuffer
,
1743 VkDeviceSize offset
,
1747 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1748 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1749 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1750 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1751 struct anv_bo
*bo
= buffer
->bo
;
1752 uint32_t bo_offset
= buffer
->offset
+ offset
;
1754 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1756 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1757 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 8);
1758 if (vs_prog_data
->uses_drawid
)
1759 emit_draw_index(cmd_buffer
, 0);
1761 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1762 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1763 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1764 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 12);
1765 emit_lri(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, 0);
1767 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1768 prim
.IndirectParameterEnable
= true;
1769 prim
.VertexAccessType
= SEQUENTIAL
;
1770 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1774 void genX(CmdDrawIndexedIndirect
)(
1775 VkCommandBuffer commandBuffer
,
1777 VkDeviceSize offset
,
1781 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1782 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1783 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.pipeline
;
1784 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
1785 struct anv_bo
*bo
= buffer
->bo
;
1786 uint32_t bo_offset
= buffer
->offset
+ offset
;
1788 genX(cmd_buffer_flush_state
)(cmd_buffer
);
1790 /* TODO: We need to stomp base vertex to 0 somehow */
1791 if (vs_prog_data
->uses_basevertex
|| vs_prog_data
->uses_baseinstance
)
1792 emit_base_vertex_instance_bo(cmd_buffer
, bo
, bo_offset
+ 12);
1793 if (vs_prog_data
->uses_drawid
)
1794 emit_draw_index(cmd_buffer
, 0);
1796 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_VERTEX_COUNT
, bo
, bo_offset
);
1797 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
, bo_offset
+ 4);
1798 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_VERTEX
, bo
, bo_offset
+ 8);
1799 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_BASE_VERTEX
, bo
, bo_offset
+ 12);
1800 emit_lrm(&cmd_buffer
->batch
, GEN7_3DPRIM_START_INSTANCE
, bo
, bo_offset
+ 16);
1802 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
1803 prim
.IndirectParameterEnable
= true;
1804 prim
.VertexAccessType
= RANDOM
;
1805 prim
.PrimitiveTopologyType
= pipeline
->topology
;
1810 flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer
)
1812 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1813 struct anv_state surfaces
= { 0, }, samplers
= { 0, };
1816 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1817 if (result
!= VK_SUCCESS
) {
1818 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1819 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
1820 assert(result
== VK_SUCCESS
);
1822 /* Re-emit state base addresses so we get the new surface state base
1823 * address before we start emitting binding tables etc.
1825 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1827 result
= emit_binding_table(cmd_buffer
, MESA_SHADER_COMPUTE
, &surfaces
);
1828 assert(result
== VK_SUCCESS
);
1831 result
= emit_samplers(cmd_buffer
, MESA_SHADER_COMPUTE
, &samplers
);
1832 assert(result
== VK_SUCCESS
);
1834 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
1835 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
1836 .BindingTablePointer
= surfaces
.offset
,
1837 .SamplerStatePointer
= samplers
.offset
,
1839 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
1841 struct anv_state state
=
1842 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
1843 pipeline
->interface_descriptor_data
,
1844 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
1847 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
1848 anv_batch_emit(&cmd_buffer
->batch
,
1849 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
1850 mid
.InterfaceDescriptorTotalLength
= size
;
1851 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
1858 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
1860 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1861 MAYBE_UNUSED VkResult result
;
1863 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
1865 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->urb
.l3_config
);
1867 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
1869 if (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
) {
1870 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
1872 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
1873 * the only bits that are changed are scoreboard related: Scoreboard
1874 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
1875 * these scoreboard related states, a MEDIA_STATE_FLUSH is
1878 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1879 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1881 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
1884 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
1885 (cmd_buffer
->state
.compute_dirty
& ANV_CMD_DIRTY_PIPELINE
)) {
1886 /* FIXME: figure out descriptors for gen7 */
1887 result
= flush_compute_descriptor_set(cmd_buffer
);
1888 assert(result
== VK_SUCCESS
);
1889 cmd_buffer
->state
.descriptors_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
1892 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
1893 struct anv_state push_state
=
1894 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
1896 if (push_state
.alloc_size
) {
1897 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
1898 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
1899 curbe
.CURBEDataStartAddress
= push_state
.offset
;
1904 cmd_buffer
->state
.compute_dirty
= 0;
1906 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1912 verify_cmd_parser(const struct anv_device
*device
,
1913 int required_version
,
1914 const char *function
)
1916 if (device
->instance
->physicalDevice
.cmd_parser_version
< required_version
) {
1917 return vk_errorf(VK_ERROR_FEATURE_NOT_PRESENT
,
1918 "cmd parser version %d is required for %s",
1919 required_version
, function
);
1927 void genX(CmdDispatch
)(
1928 VkCommandBuffer commandBuffer
,
1933 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1934 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1935 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1937 if (prog_data
->uses_num_work_groups
) {
1938 struct anv_state state
=
1939 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
1940 uint32_t *sizes
= state
.map
;
1944 anv_state_flush(cmd_buffer
->device
, state
);
1945 cmd_buffer
->state
.num_workgroups_offset
= state
.offset
;
1946 cmd_buffer
->state
.num_workgroups_bo
=
1947 &cmd_buffer
->device
->dynamic_state_block_pool
.bo
;
1950 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
1952 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
1953 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
1954 ggw
.ThreadDepthCounterMaximum
= 0;
1955 ggw
.ThreadHeightCounterMaximum
= 0;
1956 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
1957 ggw
.ThreadGroupIDXDimension
= x
;
1958 ggw
.ThreadGroupIDYDimension
= y
;
1959 ggw
.ThreadGroupIDZDimension
= z
;
1960 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
1961 ggw
.BottomExecutionMask
= 0xffffffff;
1964 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
1967 #define GPGPU_DISPATCHDIMX 0x2500
1968 #define GPGPU_DISPATCHDIMY 0x2504
1969 #define GPGPU_DISPATCHDIMZ 0x2508
1971 #define MI_PREDICATE_SRC0 0x2400
1972 #define MI_PREDICATE_SRC1 0x2408
1974 void genX(CmdDispatchIndirect
)(
1975 VkCommandBuffer commandBuffer
,
1977 VkDeviceSize offset
)
1979 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1980 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
1981 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute_pipeline
;
1982 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
1983 struct anv_bo
*bo
= buffer
->bo
;
1984 uint32_t bo_offset
= buffer
->offset
+ offset
;
1985 struct anv_batch
*batch
= &cmd_buffer
->batch
;
1988 /* Linux 4.4 added command parser version 5 which allows the GPGPU
1989 * indirect dispatch registers to be written.
1991 if (verify_cmd_parser(cmd_buffer
->device
, 5,
1992 "vkCmdDispatchIndirect") != VK_SUCCESS
)
1996 if (prog_data
->uses_num_work_groups
) {
1997 cmd_buffer
->state
.num_workgroups_offset
= bo_offset
;
1998 cmd_buffer
->state
.num_workgroups_bo
= bo
;
2001 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
2003 emit_lrm(batch
, GPGPU_DISPATCHDIMX
, bo
, bo_offset
);
2004 emit_lrm(batch
, GPGPU_DISPATCHDIMY
, bo
, bo_offset
+ 4);
2005 emit_lrm(batch
, GPGPU_DISPATCHDIMZ
, bo
, bo_offset
+ 8);
2008 /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
2009 emit_lri(batch
, MI_PREDICATE_SRC0
+ 4, 0);
2010 emit_lri(batch
, MI_PREDICATE_SRC1
+ 0, 0);
2011 emit_lri(batch
, MI_PREDICATE_SRC1
+ 4, 0);
2013 /* Load compute_dispatch_indirect_x_size into SRC0 */
2014 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 0);
2016 /* predicate = (compute_dispatch_indirect_x_size == 0); */
2017 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2018 mip
.LoadOperation
= LOAD_LOAD
;
2019 mip
.CombineOperation
= COMBINE_SET
;
2020 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2023 /* Load compute_dispatch_indirect_y_size into SRC0 */
2024 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 4);
2026 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
2027 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2028 mip
.LoadOperation
= LOAD_LOAD
;
2029 mip
.CombineOperation
= COMBINE_OR
;
2030 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2033 /* Load compute_dispatch_indirect_z_size into SRC0 */
2034 emit_lrm(batch
, MI_PREDICATE_SRC0
, bo
, bo_offset
+ 8);
2036 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
2037 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2038 mip
.LoadOperation
= LOAD_LOAD
;
2039 mip
.CombineOperation
= COMBINE_OR
;
2040 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
2043 /* predicate = !predicate; */
2044 #define COMPARE_FALSE 1
2045 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
2046 mip
.LoadOperation
= LOAD_LOADINV
;
2047 mip
.CombineOperation
= COMBINE_OR
;
2048 mip
.CompareOperation
= COMPARE_FALSE
;
2052 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
2053 ggw
.IndirectParameterEnable
= true;
2054 ggw
.PredicateEnable
= GEN_GEN
<= 7;
2055 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
2056 ggw
.ThreadDepthCounterMaximum
= 0;
2057 ggw
.ThreadHeightCounterMaximum
= 0;
2058 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
2059 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
2060 ggw
.BottomExecutionMask
= 0xffffffff;
2063 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
2067 flush_pipeline_before_pipeline_select(struct anv_cmd_buffer
*cmd_buffer
,
2070 #if GEN_GEN >= 8 && GEN_GEN < 10
2071 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
2073 * Software must clear the COLOR_CALC_STATE Valid field in
2074 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
2075 * with Pipeline Select set to GPGPU.
2077 * The internal hardware docs recommend the same workaround for Gen9
2080 if (pipeline
== GPGPU
)
2081 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
2083 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
2084 * PIPELINE_SELECT [DevBWR+]":
2088 * Software must ensure all the write caches are flushed through a
2089 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
2090 * command to invalidate read only caches prior to programming
2091 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
2093 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2094 pc
.RenderTargetCacheFlushEnable
= true;
2095 pc
.DepthCacheFlushEnable
= true;
2096 pc
.DCFlushEnable
= true;
2097 pc
.PostSyncOperation
= NoWrite
;
2098 pc
.CommandStreamerStallEnable
= true;
2101 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
2102 pc
.TextureCacheInvalidationEnable
= true;
2103 pc
.ConstantCacheInvalidationEnable
= true;
2104 pc
.StateCacheInvalidationEnable
= true;
2105 pc
.InstructionCacheInvalidateEnable
= true;
2106 pc
.PostSyncOperation
= NoWrite
;
2112 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
2114 if (cmd_buffer
->state
.current_pipeline
!= _3D
) {
2115 flush_pipeline_before_pipeline_select(cmd_buffer
, _3D
);
2117 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2121 ps
.PipelineSelection
= _3D
;
2124 cmd_buffer
->state
.current_pipeline
= _3D
;
2129 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
2131 if (cmd_buffer
->state
.current_pipeline
!= GPGPU
) {
2132 flush_pipeline_before_pipeline_select(cmd_buffer
, GPGPU
);
2134 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
2138 ps
.PipelineSelection
= GPGPU
;
2141 cmd_buffer
->state
.current_pipeline
= GPGPU
;
2146 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
2151 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
2153 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
2154 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
2155 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
2156 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
2157 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
2158 * Depth Flush Bit set, followed by another pipelined depth stall
2159 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
2160 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
2161 * via a preceding MI_FLUSH)."
2163 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2164 pipe
.DepthStallEnable
= true;
2166 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2167 pipe
.DepthCacheFlushEnable
= true;
2169 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2170 pipe
.DepthStallEnable
= true;
2175 depth_stencil_surface_type(enum isl_surf_dim dim
)
2178 case ISL_SURF_DIM_1D
:
2180 /* From the Sky Lake PRM, 3DSTATAE_DEPTH_BUFFER::SurfaceType
2182 * Programming Notes:
2183 * The Surface Type of the depth buffer must be the same as the
2184 * Surface Type of the render target(s) (defined in
2185 * SURFACE_STATE), unless either the depth buffer or render
2186 * targets are SURFTYPE_NULL (see exception below for SKL). 1D
2187 * surface type not allowed for depth surface and stencil surface.
2190 * If depth/stencil is enabled with 1D render target,
2191 * depth/stencil surface type needs to be set to 2D surface type
2192 * and height set to 1. Depth will use (legacy) TileY and stencil
2193 * will use TileW. For this case only, the Surface Type of the
2194 * depth buffer can be 2D while the Surface Type of the render
2195 * target(s) are 1D, representing an exception to a programming
2202 case ISL_SURF_DIM_2D
:
2204 case ISL_SURF_DIM_3D
:
2206 /* The Sky Lake docs list the value for 3D as "Reserved". However,
2207 * they have the exact same layout as 2D arrays on gen9+, so we can
2215 unreachable("Invalid surface dimension");
2220 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
2222 struct anv_device
*device
= cmd_buffer
->device
;
2223 const struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
2224 const struct anv_image_view
*iview
=
2225 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2226 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
2227 const bool has_depth
= image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
);
2228 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2229 const bool has_hiz
= image
!= NULL
&&
2230 cmd_buffer
->state
.attachments
[ds
].aux_usage
== ISL_AUX_USAGE_HIZ
;
2231 const bool has_stencil
=
2232 image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
2234 cmd_buffer
->state
.hiz_enabled
= has_hiz
;
2236 /* FIXME: Width and Height are wrong */
2238 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
2240 /* Emit 3DSTATE_DEPTH_BUFFER */
2242 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2244 depth_stencil_surface_type(image
->depth_surface
.isl
.dim
);
2245 db
.DepthWriteEnable
= true;
2246 db
.StencilWriteEnable
= has_stencil
;
2247 db
.HierarchicalDepthBufferEnable
= has_hiz
;
2249 db
.SurfaceFormat
= isl_surf_get_depth_format(&device
->isl_dev
,
2250 &image
->depth_surface
.isl
);
2252 db
.SurfaceBaseAddress
= (struct anv_address
) {
2254 .offset
= image
->offset
+ image
->depth_surface
.offset
,
2256 db
.DepthBufferObjectControlState
= GENX(MOCS
);
2258 db
.SurfacePitch
= image
->depth_surface
.isl
.row_pitch
- 1;
2259 db
.Height
= image
->extent
.height
- 1;
2260 db
.Width
= image
->extent
.width
- 1;
2261 db
.LOD
= iview
->isl
.base_level
;
2262 db
.MinimumArrayElement
= iview
->isl
.base_array_layer
;
2264 assert(image
->depth_surface
.isl
.dim
!= ISL_SURF_DIM_3D
);
2266 db
.RenderTargetViewExtent
=
2267 iview
->isl
.array_len
- iview
->isl
.base_array_layer
- 1;
2271 isl_surf_get_array_pitch_el_rows(&image
->depth_surface
.isl
) >> 2;
2275 /* Even when no depth buffer is present, the hardware requires that
2276 * 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
2278 * If a null depth buffer is bound, the driver must instead bind depth as:
2279 * 3DSTATE_DEPTH.SurfaceType = SURFTYPE_2D
2280 * 3DSTATE_DEPTH.Width = 1
2281 * 3DSTATE_DEPTH.Height = 1
2282 * 3DSTATE_DEPTH.SuraceFormat = D16_UNORM
2283 * 3DSTATE_DEPTH.SurfaceBaseAddress = 0
2284 * 3DSTATE_DEPTH.HierarchicalDepthBufferEnable = 0
2285 * 3DSTATE_WM_DEPTH_STENCIL.DepthTestEnable = 0
2286 * 3DSTATE_WM_DEPTH_STENCIL.DepthBufferWriteEnable = 0
2288 * The PRM is wrong, though. The width and height must be programmed to
2289 * actual framebuffer's width and height, even when neither depth buffer
2290 * nor stencil buffer is present. Also, D16_UNORM is not allowed to
2291 * be combined with a stencil buffer so we use D32_FLOAT instead.
2293 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_DEPTH_BUFFER
), db
) {
2296 depth_stencil_surface_type(image
->stencil_surface
.isl
.dim
);
2298 db
.SurfaceType
= SURFTYPE_2D
;
2300 db
.SurfaceFormat
= D32_FLOAT
;
2301 db
.Width
= MAX2(fb
->width
, 1) - 1;
2302 db
.Height
= MAX2(fb
->height
, 1) - 1;
2303 db
.StencilWriteEnable
= has_stencil
;
2308 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
) {
2309 hdb
.HierarchicalDepthBufferObjectControlState
= GENX(MOCS
);
2310 hdb
.SurfacePitch
= image
->aux_surface
.isl
.row_pitch
- 1;
2311 hdb
.SurfaceBaseAddress
= (struct anv_address
) {
2313 .offset
= image
->offset
+ image
->aux_surface
.offset
,
2316 /* From the SKL PRM Vol2a:
2318 * The interpretation of this field is dependent on Surface Type
2320 * - SURFTYPE_1D: distance in pixels between array slices
2321 * - SURFTYPE_2D/CUBE: distance in rows between array slices
2322 * - SURFTYPE_3D: distance in rows between R - slices
2324 * Unfortunately, the docs aren't 100% accurate here. They fail to
2325 * mention that the 1-D rule only applies to linear 1-D images.
2326 * Since depth and HiZ buffers are always tiled, they are treated as
2327 * 2-D images. Prior to Sky Lake, this field is always in rows.
2330 isl_surf_get_array_pitch_sa_rows(&image
->aux_surface
.isl
) >> 2;
2334 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_HIER_DEPTH_BUFFER
), hdb
);
2337 /* Emit 3DSTATE_STENCIL_BUFFER */
2339 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
) {
2340 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2341 sb
.StencilBufferEnable
= true;
2343 sb
.StencilBufferObjectControlState
= GENX(MOCS
);
2345 sb
.SurfacePitch
= image
->stencil_surface
.isl
.row_pitch
- 1;
2348 sb
.SurfaceQPitch
= isl_surf_get_array_pitch_el_rows(&image
->stencil_surface
.isl
) >> 2;
2350 sb
.SurfaceBaseAddress
= (struct anv_address
) {
2352 .offset
= image
->offset
+ image
->stencil_surface
.offset
,
2356 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_STENCIL_BUFFER
), sb
);
2359 /* From the IVB PRM Vol2P1, 11.5.5.4 3DSTATE_CLEAR_PARAMS:
2361 * 3DSTATE_CLEAR_PARAMS must always be programmed in the along with
2362 * the other Depth/Stencil state commands(i.e. 3DSTATE_DEPTH_BUFFER,
2363 * 3DSTATE_STENCIL_BUFFER, or 3DSTATE_HIER_DEPTH_BUFFER)
2365 * Testing also shows that some variant of this restriction may exist HSW+.
2366 * On BDW+, it is not possible to emit 2 of these packets consecutively when
2367 * both have DepthClearValueValid set. An analysis of such state programming
2368 * on SKL showed that the GPU doesn't register the latter packet's clear
2371 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CLEAR_PARAMS
), cp
) {
2373 cp
.DepthClearValueValid
= true;
2374 cp
.DepthClearValue
= ANV_HZ_FC_VAL
;
2380 genX(cmd_buffer_set_subpass
)(struct anv_cmd_buffer
*cmd_buffer
,
2381 struct anv_subpass
*subpass
)
2383 cmd_buffer
->state
.subpass
= subpass
;
2385 cmd_buffer
->state
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
2387 const struct anv_image_view
*iview
=
2388 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2390 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2391 const uint32_t ds
= subpass
->depth_stencil_attachment
;
2392 transition_depth_buffer(cmd_buffer
, iview
->image
,
2393 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2394 cmd_buffer
->state
.subpass
->depth_stencil_layout
);
2395 cmd_buffer
->state
.attachments
[ds
].current_layout
=
2396 cmd_buffer
->state
.subpass
->depth_stencil_layout
;
2397 cmd_buffer
->state
.attachments
[ds
].aux_usage
=
2398 layout_to_hiz_usage(cmd_buffer
->state
.subpass
->depth_stencil_layout
,
2399 iview
->image
->samples
);
2402 cmd_buffer_emit_depth_stencil(cmd_buffer
);
2404 anv_cmd_buffer_clear_subpass(cmd_buffer
);
2407 void genX(CmdBeginRenderPass
)(
2408 VkCommandBuffer commandBuffer
,
2409 const VkRenderPassBeginInfo
* pRenderPassBegin
,
2410 VkSubpassContents contents
)
2412 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2413 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2414 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2416 cmd_buffer
->state
.framebuffer
= framebuffer
;
2417 cmd_buffer
->state
.pass
= pass
;
2418 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
2419 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
2421 genX(flush_pipeline_select_3d
)(cmd_buffer
);
2423 genX(cmd_buffer_set_subpass
)(cmd_buffer
, pass
->subpasses
);
2426 void genX(CmdNextSubpass
)(
2427 VkCommandBuffer commandBuffer
,
2428 VkSubpassContents contents
)
2430 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2432 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2434 const struct anv_image_view
*iview
=
2435 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2437 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2438 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2440 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2441 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2442 transition_depth_buffer(cmd_buffer
, iview
->image
,
2443 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2444 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2448 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2449 genX(cmd_buffer_set_subpass
)(cmd_buffer
, cmd_buffer
->state
.subpass
+ 1);
2452 void genX(CmdEndRenderPass
)(
2453 VkCommandBuffer commandBuffer
)
2455 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2457 const struct anv_image_view
*iview
=
2458 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
2460 if (iview
&& iview
->image
->aux_usage
== ISL_AUX_USAGE_HIZ
) {
2461 const uint32_t ds
= cmd_buffer
->state
.subpass
->depth_stencil_attachment
;
2463 if (cmd_buffer
->state
.subpass
- cmd_buffer
->state
.pass
->subpasses
==
2464 cmd_buffer
->state
.pass
->attachments
[ds
].last_subpass_idx
) {
2465 transition_depth_buffer(cmd_buffer
, iview
->image
,
2466 cmd_buffer
->state
.attachments
[ds
].current_layout
,
2467 cmd_buffer
->state
.pass
->attachments
[ds
].final_layout
);
2471 anv_cmd_buffer_resolve_subpass(cmd_buffer
);
2473 cmd_buffer
->state
.hiz_enabled
= false;
2476 anv_dump_add_framebuffer(cmd_buffer
, cmd_buffer
->state
.framebuffer
);