2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
27 #include "anv_private.h"
28 #include "vk_format_info.h"
30 #include "util/fast_idiv_by_const.h"
32 #include "common/gen_aux_map.h"
33 #include "common/gen_l3_config.h"
34 #include "genxml/gen_macros.h"
35 #include "genxml/genX_pack.h"
37 /* We reserve GPR 14 and 15 for conditional rendering */
38 #define GEN_MI_BUILDER_NUM_ALLOC_GPRS 14
39 #define __gen_get_batch_dwords anv_batch_emit_dwords
40 #define __gen_address_offset anv_address_add
41 #include "common/gen_mi_builder.h"
43 static void genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
47 emit_lri(struct anv_batch
*batch
, uint32_t reg
, uint32_t imm
)
49 anv_batch_emit(batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
50 lri
.RegisterOffset
= reg
;
56 genX(cmd_buffer_emit_state_base_address
)(struct anv_cmd_buffer
*cmd_buffer
)
58 struct anv_device
*device
= cmd_buffer
->device
;
59 UNUSED
const struct gen_device_info
*devinfo
= &device
->info
;
60 uint32_t mocs
= device
->isl_dev
.mocs
.internal
;
62 /* If we are emitting a new state base address we probably need to re-emit
65 cmd_buffer
->state
.descriptors_dirty
|= ~0;
67 /* Emit a render target cache flush.
69 * This isn't documented anywhere in the PRM. However, it seems to be
70 * necessary prior to changing the surface state base adress. Without
71 * this, we get GPU hangs when using multi-level command buffers which
72 * clear depth, reset state base address, and then go render stuff.
74 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
75 pc
.DCFlushEnable
= true;
76 pc
.RenderTargetCacheFlushEnable
= true;
77 pc
.CommandStreamerStallEnable
= true;
79 pc
.TileCacheFlushEnable
= true;
82 /* GEN:BUG:1606662791:
84 * Software must program PIPE_CONTROL command with "HDC Pipeline
85 * Flush" prior to programming of the below two non-pipeline state :
86 * * STATE_BASE_ADDRESS
87 * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
89 if (devinfo
->revision
== 0 /* A0 */)
90 pc
.HDCPipelineFlushEnable
= true;
95 /* GEN:BUG:1607854226:
97 * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
98 * mode by putting the pipeline temporarily in 3D mode.
100 uint32_t gen12_wa_pipeline
= cmd_buffer
->state
.current_pipeline
;
101 genX(flush_pipeline_select_3d
)(cmd_buffer
);
104 anv_batch_emit(&cmd_buffer
->batch
, GENX(STATE_BASE_ADDRESS
), sba
) {
105 sba
.GeneralStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
106 sba
.GeneralStateMOCS
= mocs
;
107 sba
.GeneralStateBaseAddressModifyEnable
= true;
109 sba
.StatelessDataPortAccessMOCS
= mocs
;
111 sba
.SurfaceStateBaseAddress
=
112 anv_cmd_buffer_surface_base_address(cmd_buffer
);
113 sba
.SurfaceStateMOCS
= mocs
;
114 sba
.SurfaceStateBaseAddressModifyEnable
= true;
116 sba
.DynamicStateBaseAddress
=
117 (struct anv_address
) { device
->dynamic_state_pool
.block_pool
.bo
, 0 };
118 sba
.DynamicStateMOCS
= mocs
;
119 sba
.DynamicStateBaseAddressModifyEnable
= true;
121 sba
.IndirectObjectBaseAddress
= (struct anv_address
) { NULL
, 0 };
122 sba
.IndirectObjectMOCS
= mocs
;
123 sba
.IndirectObjectBaseAddressModifyEnable
= true;
125 sba
.InstructionBaseAddress
=
126 (struct anv_address
) { device
->instruction_state_pool
.block_pool
.bo
, 0 };
127 sba
.InstructionMOCS
= mocs
;
128 sba
.InstructionBaseAddressModifyEnable
= true;
131 /* Broadwell requires that we specify a buffer size for a bunch of
132 * these fields. However, since we will be growing the BO's live, we
133 * just set them all to the maximum.
135 sba
.GeneralStateBufferSize
= 0xfffff;
136 sba
.IndirectObjectBufferSize
= 0xfffff;
137 if (device
->physical
->use_softpin
) {
138 /* With softpin, we use fixed addresses so we actually know how big
139 * our base addresses are.
141 sba
.DynamicStateBufferSize
= DYNAMIC_STATE_POOL_SIZE
/ 4096;
142 sba
.InstructionBufferSize
= INSTRUCTION_STATE_POOL_SIZE
/ 4096;
144 sba
.DynamicStateBufferSize
= 0xfffff;
145 sba
.InstructionBufferSize
= 0xfffff;
147 sba
.GeneralStateBufferSizeModifyEnable
= true;
148 sba
.IndirectObjectBufferSizeModifyEnable
= true;
149 sba
.DynamicStateBufferSizeModifyEnable
= true;
150 sba
.InstructionBuffersizeModifyEnable
= true;
152 /* On gen7, we have upper bounds instead. According to the docs,
153 * setting an upper bound of zero means that no bounds checking is
154 * performed so, in theory, we should be able to leave them zero.
155 * However, border color is broken and the GPU bounds-checks anyway.
156 * To avoid this and other potential problems, we may as well set it
159 sba
.GeneralStateAccessUpperBound
=
160 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
161 sba
.GeneralStateAccessUpperBoundModifyEnable
= true;
162 sba
.DynamicStateAccessUpperBound
=
163 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
164 sba
.DynamicStateAccessUpperBoundModifyEnable
= true;
165 sba
.InstructionAccessUpperBound
=
166 (struct anv_address
) { .bo
= NULL
, .offset
= 0xfffff000 };
167 sba
.InstructionAccessUpperBoundModifyEnable
= true;
170 if (cmd_buffer
->device
->physical
->use_softpin
) {
171 sba
.BindlessSurfaceStateBaseAddress
= (struct anv_address
) {
172 .bo
= device
->surface_state_pool
.block_pool
.bo
,
175 sba
.BindlessSurfaceStateSize
= (1 << 20) - 1;
177 sba
.BindlessSurfaceStateBaseAddress
= ANV_NULL_ADDRESS
;
178 sba
.BindlessSurfaceStateSize
= 0;
180 sba
.BindlessSurfaceStateMOCS
= mocs
;
181 sba
.BindlessSurfaceStateBaseAddressModifyEnable
= true;
184 sba
.BindlessSamplerStateBaseAddress
= (struct anv_address
) { NULL
, 0 };
185 sba
.BindlessSamplerStateMOCS
= mocs
;
186 sba
.BindlessSamplerStateBaseAddressModifyEnable
= true;
187 sba
.BindlessSamplerStateBufferSize
= 0;
192 /* GEN:BUG:1607854226:
194 * Put the pipeline back into its current mode.
196 if (gen12_wa_pipeline
!= UINT32_MAX
)
197 genX(flush_pipeline_select
)(cmd_buffer
, gen12_wa_pipeline
);
200 /* After re-setting the surface state base address, we have to do some
201 * cache flusing so that the sampler engine will pick up the new
202 * SURFACE_STATE objects and binding tables. From the Broadwell PRM,
203 * Shared Function > 3D Sampler > State > State Caching (page 96):
205 * Coherency with system memory in the state cache, like the texture
206 * cache is handled partially by software. It is expected that the
207 * command stream or shader will issue Cache Flush operation or
208 * Cache_Flush sampler message to ensure that the L1 cache remains
209 * coherent with system memory.
213 * Whenever the value of the Dynamic_State_Base_Addr,
214 * Surface_State_Base_Addr are altered, the L1 state cache must be
215 * invalidated to ensure the new surface or sampler state is fetched
216 * from system memory.
218 * The PIPE_CONTROL command has a "State Cache Invalidation Enable" bit
219 * which, according the PIPE_CONTROL instruction documentation in the
222 * Setting this bit is independent of any other bit in this packet.
223 * This bit controls the invalidation of the L1 and L2 state caches
224 * at the top of the pipe i.e. at the parsing time.
226 * Unfortunately, experimentation seems to indicate that state cache
227 * invalidation through a PIPE_CONTROL does nothing whatsoever in
228 * regards to surface state and binding tables. In stead, it seems that
229 * invalidating the texture cache is what is actually needed.
231 * XXX: As far as we have been able to determine through
232 * experimentation, shows that flush the texture cache appears to be
233 * sufficient. The theory here is that all of the sampling/rendering
234 * units cache the binding table in the texture cache. However, we have
235 * yet to be able to actually confirm this.
237 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
238 pc
.TextureCacheInvalidationEnable
= true;
239 pc
.ConstantCacheInvalidationEnable
= true;
240 pc
.StateCacheInvalidationEnable
= true;
245 add_surface_reloc(struct anv_cmd_buffer
*cmd_buffer
,
246 struct anv_state state
, struct anv_address addr
)
248 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
251 anv_reloc_list_add(&cmd_buffer
->surface_relocs
, &cmd_buffer
->pool
->alloc
,
252 state
.offset
+ isl_dev
->ss
.addr_offset
,
253 addr
.bo
, addr
.offset
, NULL
);
254 if (result
!= VK_SUCCESS
)
255 anv_batch_set_error(&cmd_buffer
->batch
, result
);
259 add_surface_state_relocs(struct anv_cmd_buffer
*cmd_buffer
,
260 struct anv_surface_state state
)
262 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
264 assert(!anv_address_is_null(state
.address
));
265 add_surface_reloc(cmd_buffer
, state
.state
, state
.address
);
267 if (!anv_address_is_null(state
.aux_address
)) {
269 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
270 &cmd_buffer
->pool
->alloc
,
271 state
.state
.offset
+ isl_dev
->ss
.aux_addr_offset
,
272 state
.aux_address
.bo
,
273 state
.aux_address
.offset
,
275 if (result
!= VK_SUCCESS
)
276 anv_batch_set_error(&cmd_buffer
->batch
, result
);
279 if (!anv_address_is_null(state
.clear_address
)) {
281 anv_reloc_list_add(&cmd_buffer
->surface_relocs
,
282 &cmd_buffer
->pool
->alloc
,
284 isl_dev
->ss
.clear_color_state_offset
,
285 state
.clear_address
.bo
,
286 state
.clear_address
.offset
,
288 if (result
!= VK_SUCCESS
)
289 anv_batch_set_error(&cmd_buffer
->batch
, result
);
294 color_attachment_compute_aux_usage(struct anv_device
* device
,
295 struct anv_cmd_state
* cmd_state
,
296 uint32_t att
, VkRect2D render_area
,
297 union isl_color_value
*fast_clear_color
)
299 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
300 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
302 assert(iview
->n_planes
== 1);
304 if (iview
->planes
[0].isl
.base_array_layer
>=
305 anv_image_aux_layers(iview
->image
, VK_IMAGE_ASPECT_COLOR_BIT
,
306 iview
->planes
[0].isl
.base_level
)) {
307 /* There is no aux buffer which corresponds to the level and layer(s)
310 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
311 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
312 att_state
->fast_clear
= false;
316 att_state
->aux_usage
=
317 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
318 VK_IMAGE_ASPECT_COLOR_BIT
,
319 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
,
320 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
);
322 /* If we don't have aux, then we should have returned early in the layer
323 * check above. If we got here, we must have something.
325 assert(att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
);
327 if (att_state
->aux_usage
== ISL_AUX_USAGE_CCS_E
||
328 att_state
->aux_usage
== ISL_AUX_USAGE_MCS
) {
329 att_state
->input_aux_usage
= att_state
->aux_usage
;
331 /* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
333 * "If Number of Multisamples is MULTISAMPLECOUNT_1, AUX_CCS_D
334 * setting is only allowed if Surface Format supported for Fast
335 * Clear. In addition, if the surface is bound to the sampling
336 * engine, Surface Format must be supported for Render Target
337 * Compression for surfaces bound to the sampling engine."
339 * In other words, we can only sample from a fast-cleared image if it
340 * also supports color compression.
342 if (isl_format_supports_ccs_e(&device
->info
, iview
->planes
[0].isl
.format
) &&
343 isl_format_supports_ccs_d(&device
->info
, iview
->planes
[0].isl
.format
)) {
344 att_state
->input_aux_usage
= ISL_AUX_USAGE_CCS_D
;
346 /* While fast-clear resolves and partial resolves are fairly cheap in the
347 * case where you render to most of the pixels, full resolves are not
348 * because they potentially involve reading and writing the entire
349 * framebuffer. If we can't texture with CCS_E, we should leave it off and
350 * limit ourselves to fast clears.
352 if (cmd_state
->pass
->attachments
[att
].first_subpass_layout
==
353 VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
) {
354 anv_perf_warn(device
, iview
->image
,
355 "Not temporarily enabling CCS_E.");
358 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
362 assert(iview
->image
->planes
[0].aux_surface
.isl
.usage
&
363 (ISL_SURF_USAGE_CCS_BIT
| ISL_SURF_USAGE_MCS_BIT
));
365 union isl_color_value clear_color
= {};
366 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
368 att_state
->clear_color_is_zero_one
=
369 isl_color_value_is_zero_one(clear_color
, iview
->planes
[0].isl
.format
);
370 att_state
->clear_color_is_zero
=
371 isl_color_value_is_zero(clear_color
, iview
->planes
[0].isl
.format
);
373 if (att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
374 /* Start by getting the fast clear type. We use the first subpass
375 * layout here because we don't want to fast-clear if the first subpass
376 * to use the attachment can't handle fast-clears.
378 enum anv_fast_clear_type fast_clear_type
=
379 anv_layout_to_fast_clear_type(&device
->info
, iview
->image
,
380 VK_IMAGE_ASPECT_COLOR_BIT
,
381 cmd_state
->pass
->attachments
[att
].first_subpass_layout
);
382 switch (fast_clear_type
) {
383 case ANV_FAST_CLEAR_NONE
:
384 att_state
->fast_clear
= false;
386 case ANV_FAST_CLEAR_DEFAULT_VALUE
:
387 att_state
->fast_clear
= att_state
->clear_color_is_zero
;
389 case ANV_FAST_CLEAR_ANY
:
390 att_state
->fast_clear
= true;
394 /* Potentially, we could do partial fast-clears but doing so has crazy
395 * alignment restrictions. It's easier to just restrict to full size
396 * fast clears for now.
398 if (render_area
.offset
.x
!= 0 ||
399 render_area
.offset
.y
!= 0 ||
400 render_area
.extent
.width
!= iview
->extent
.width
||
401 render_area
.extent
.height
!= iview
->extent
.height
)
402 att_state
->fast_clear
= false;
404 /* On Broadwell and earlier, we can only handle 0/1 clear colors */
405 if (GEN_GEN
<= 8 && !att_state
->clear_color_is_zero_one
)
406 att_state
->fast_clear
= false;
408 /* We only allow fast clears to the first slice of an image (level 0,
409 * layer 0) and only for the entire slice. This guarantees us that, at
410 * any given time, there is only one clear color on any given image at
411 * any given time. At the time of our testing (Jan 17, 2018), there
412 * were no known applications which would benefit from fast-clearing
413 * more than just the first slice.
415 if (att_state
->fast_clear
&&
416 (iview
->planes
[0].isl
.base_level
> 0 ||
417 iview
->planes
[0].isl
.base_array_layer
> 0)) {
418 anv_perf_warn(device
, iview
->image
,
419 "Rendering with multi-lod or multi-layer framebuffer "
420 "with LOAD_OP_LOAD and baseMipLevel > 0 or "
421 "baseArrayLayer > 0. Not fast clearing.");
422 att_state
->fast_clear
= false;
423 } else if (att_state
->fast_clear
&& cmd_state
->framebuffer
->layers
> 1) {
424 anv_perf_warn(device
, iview
->image
,
425 "Rendering to a multi-layer framebuffer with "
426 "LOAD_OP_CLEAR. Only fast-clearing the first slice");
429 if (att_state
->fast_clear
)
430 *fast_clear_color
= clear_color
;
432 att_state
->fast_clear
= false;
437 depth_stencil_attachment_compute_aux_usage(struct anv_device
*device
,
438 struct anv_cmd_state
*cmd_state
,
439 uint32_t att
, VkRect2D render_area
)
441 struct anv_render_pass_attachment
*pass_att
=
442 &cmd_state
->pass
->attachments
[att
];
443 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[att
];
444 struct anv_image_view
*iview
= cmd_state
->attachments
[att
].image_view
;
446 /* These will be initialized after the first subpass transition. */
447 att_state
->aux_usage
= ISL_AUX_USAGE_NONE
;
448 att_state
->input_aux_usage
= ISL_AUX_USAGE_NONE
;
450 /* This is unused for depth/stencil but valgrind complains if it
453 att_state
->clear_color_is_zero_one
= false;
456 /* We don't do any HiZ or depth fast-clears on gen7 yet */
457 att_state
->fast_clear
= false;
461 if (!(att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
462 /* If we're just clearing stencil, we can always HiZ clear */
463 att_state
->fast_clear
= true;
467 /* Default to false for now */
468 att_state
->fast_clear
= false;
470 /* We must have depth in order to have HiZ */
471 if (!(iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
))
474 const enum isl_aux_usage first_subpass_aux_usage
=
475 anv_layout_to_aux_usage(&device
->info
, iview
->image
,
476 VK_IMAGE_ASPECT_DEPTH_BIT
,
477 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
478 pass_att
->first_subpass_layout
);
479 if (!blorp_can_hiz_clear_depth(&device
->info
,
480 &iview
->image
->planes
[0].surface
.isl
,
481 first_subpass_aux_usage
,
482 iview
->planes
[0].isl
.base_level
,
483 iview
->planes
[0].isl
.base_array_layer
,
484 render_area
.offset
.x
,
485 render_area
.offset
.y
,
486 render_area
.offset
.x
+
487 render_area
.extent
.width
,
488 render_area
.offset
.y
+
489 render_area
.extent
.height
))
492 if (att_state
->clear_value
.depthStencil
.depth
!= ANV_HZ_FC_VAL
)
495 if (GEN_GEN
== 8 && anv_can_sample_with_hiz(&device
->info
, iview
->image
)) {
496 /* Only gen9+ supports returning ANV_HZ_FC_VAL when sampling a
497 * fast-cleared portion of a HiZ buffer. Testing has revealed that Gen8
498 * only supports returning 0.0f. Gens prior to gen8 do not support this
504 /* If we got here, then we can fast clear */
505 att_state
->fast_clear
= true;
509 need_input_attachment_state(const struct anv_render_pass_attachment
*att
)
511 if (!(att
->usage
& VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
))
514 /* We only allocate input attachment states for color surfaces. Compression
515 * is not yet enabled for depth textures and stencil doesn't allow
516 * compression so we can just use the texture surface state from the view.
518 return vk_format_is_color(att
->format
);
521 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
522 * the initial layout is undefined, the HiZ buffer and depth buffer will
523 * represent the same data at the end of this operation.
526 transition_depth_buffer(struct anv_cmd_buffer
*cmd_buffer
,
527 const struct anv_image
*image
,
528 VkImageLayout initial_layout
,
529 VkImageLayout final_layout
)
531 uint32_t depth_plane
=
532 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
533 if (image
->planes
[depth_plane
].aux_usage
== ISL_AUX_USAGE_NONE
)
536 const enum isl_aux_state initial_state
=
537 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
538 VK_IMAGE_ASPECT_DEPTH_BIT
,
540 const enum isl_aux_state final_state
=
541 anv_layout_to_aux_state(&cmd_buffer
->device
->info
, image
,
542 VK_IMAGE_ASPECT_DEPTH_BIT
,
545 const bool initial_depth_valid
=
546 isl_aux_state_has_valid_primary(initial_state
);
547 const bool initial_hiz_valid
=
548 isl_aux_state_has_valid_aux(initial_state
);
549 const bool final_needs_depth
=
550 isl_aux_state_has_valid_primary(final_state
);
551 const bool final_needs_hiz
=
552 isl_aux_state_has_valid_aux(final_state
);
554 /* Getting into the pass-through state for Depth is tricky and involves
555 * both a resolve and an ambiguate. We don't handle that state right now
556 * as anv_layout_to_aux_state never returns it.
558 assert(final_state
!= ISL_AUX_STATE_PASS_THROUGH
);
560 if (final_needs_depth
&& !initial_depth_valid
) {
561 assert(initial_hiz_valid
);
562 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
563 0, 0, 1, ISL_AUX_OP_FULL_RESOLVE
);
564 } else if (final_needs_hiz
&& !initial_hiz_valid
) {
565 assert(initial_depth_valid
);
566 anv_image_hiz_op(cmd_buffer
, image
, VK_IMAGE_ASPECT_DEPTH_BIT
,
567 0, 0, 1, ISL_AUX_OP_AMBIGUATE
);
572 vk_image_layout_stencil_write_optimal(VkImageLayout layout
)
574 return layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
575 layout
== VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
||
576 layout
== VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
;
579 /* Transitions a HiZ-enabled depth buffer from one layout to another. Unless
580 * the initial layout is undefined, the HiZ buffer and depth buffer will
581 * represent the same data at the end of this operation.
584 transition_stencil_buffer(struct anv_cmd_buffer
*cmd_buffer
,
585 const struct anv_image
*image
,
586 uint32_t base_level
, uint32_t level_count
,
587 uint32_t base_layer
, uint32_t layer_count
,
588 VkImageLayout initial_layout
,
589 VkImageLayout final_layout
)
592 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
593 VK_IMAGE_ASPECT_STENCIL_BIT
);
595 /* On gen7, we have to store a texturable version of the stencil buffer in
596 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
597 * forth at strategic points. Stencil writes are only allowed in following
600 * - VK_IMAGE_LAYOUT_GENERAL
601 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
602 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
603 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
604 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
606 * For general, we have no nice opportunity to transition so we do the copy
607 * to the shadow unconditionally at the end of the subpass. For transfer
608 * destinations, we can update it as part of the transfer op. For the other
609 * layouts, we delay the copy until a transition into some other layout.
611 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
612 vk_image_layout_stencil_write_optimal(initial_layout
) &&
613 !vk_image_layout_stencil_write_optimal(final_layout
)) {
614 anv_image_copy_to_shadow(cmd_buffer
, image
,
615 VK_IMAGE_ASPECT_STENCIL_BIT
,
616 base_level
, level_count
,
617 base_layer
, layer_count
);
619 #endif /* GEN_GEN == 7 */
622 #define MI_PREDICATE_SRC0 0x2400
623 #define MI_PREDICATE_SRC1 0x2408
624 #define MI_PREDICATE_RESULT 0x2418
627 set_image_compressed_bit(struct anv_cmd_buffer
*cmd_buffer
,
628 const struct anv_image
*image
,
629 VkImageAspectFlagBits aspect
,
631 uint32_t base_layer
, uint32_t layer_count
,
634 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
636 /* We only have compression tracking for CCS_E */
637 if (image
->planes
[plane
].aux_usage
!= ISL_AUX_USAGE_CCS_E
)
640 for (uint32_t a
= 0; a
< layer_count
; a
++) {
641 uint32_t layer
= base_layer
+ a
;
642 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
643 sdi
.Address
= anv_image_get_compression_state_addr(cmd_buffer
->device
,
646 sdi
.ImmediateData
= compressed
? UINT32_MAX
: 0;
652 set_image_fast_clear_state(struct anv_cmd_buffer
*cmd_buffer
,
653 const struct anv_image
*image
,
654 VkImageAspectFlagBits aspect
,
655 enum anv_fast_clear_type fast_clear
)
657 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
658 sdi
.Address
= anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
660 sdi
.ImmediateData
= fast_clear
;
663 /* Whenever we have fast-clear, we consider that slice to be compressed.
664 * This makes building predicates much easier.
666 if (fast_clear
!= ANV_FAST_CLEAR_NONE
)
667 set_image_compressed_bit(cmd_buffer
, image
, aspect
, 0, 0, 1, true);
670 /* This is only really practical on haswell and above because it requires
671 * MI math in order to get it correct.
673 #if GEN_GEN >= 8 || GEN_IS_HASWELL
675 anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
676 const struct anv_image
*image
,
677 VkImageAspectFlagBits aspect
,
678 uint32_t level
, uint32_t array_layer
,
679 enum isl_aux_op resolve_op
,
680 enum anv_fast_clear_type fast_clear_supported
)
682 struct gen_mi_builder b
;
683 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
685 const struct gen_mi_value fast_clear_type
=
686 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
689 if (resolve_op
== ISL_AUX_OP_FULL_RESOLVE
) {
690 /* In this case, we're doing a full resolve which means we want the
691 * resolve to happen if any compression (including fast-clears) is
694 * In order to simplify the logic a bit, we make the assumption that,
695 * if the first slice has been fast-cleared, it is also marked as
696 * compressed. See also set_image_fast_clear_state.
698 const struct gen_mi_value compression_state
=
699 gen_mi_mem32(anv_image_get_compression_state_addr(cmd_buffer
->device
,
701 level
, array_layer
));
702 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
704 gen_mi_store(&b
, compression_state
, gen_mi_imm(0));
706 if (level
== 0 && array_layer
== 0) {
707 /* If the predicate is true, we want to write 0 to the fast clear type
708 * and, if it's false, leave it alone. We can do this by writing
710 * clear_type = clear_type & ~predicate;
712 struct gen_mi_value new_fast_clear_type
=
713 gen_mi_iand(&b
, fast_clear_type
,
714 gen_mi_inot(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
)));
715 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
717 } else if (level
== 0 && array_layer
== 0) {
718 /* In this case, we are doing a partial resolve to get rid of fast-clear
719 * colors. We don't care about the compression state but we do care
720 * about how much fast clear is allowed by the final layout.
722 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
723 assert(fast_clear_supported
< ANV_FAST_CLEAR_ANY
);
725 /* We need to compute (fast_clear_supported < image->fast_clear) */
726 struct gen_mi_value pred
=
727 gen_mi_ult(&b
, gen_mi_imm(fast_clear_supported
), fast_clear_type
);
728 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
729 gen_mi_value_ref(&b
, pred
));
731 /* If the predicate is true, we want to write 0 to the fast clear type
732 * and, if it's false, leave it alone. We can do this by writing
734 * clear_type = clear_type & ~predicate;
736 struct gen_mi_value new_fast_clear_type
=
737 gen_mi_iand(&b
, fast_clear_type
, gen_mi_inot(&b
, pred
));
738 gen_mi_store(&b
, fast_clear_type
, new_fast_clear_type
);
740 /* In this case, we're trying to do a partial resolve on a slice that
741 * doesn't have clear color. There's nothing to do.
743 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
747 /* Set src1 to 0 and use a != condition */
748 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
750 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
751 mip
.LoadOperation
= LOAD_LOADINV
;
752 mip
.CombineOperation
= COMBINE_SET
;
753 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
756 #endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
760 anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer
*cmd_buffer
,
761 const struct anv_image
*image
,
762 VkImageAspectFlagBits aspect
,
763 uint32_t level
, uint32_t array_layer
,
764 enum isl_aux_op resolve_op
,
765 enum anv_fast_clear_type fast_clear_supported
)
767 struct gen_mi_builder b
;
768 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
770 struct gen_mi_value fast_clear_type_mem
=
771 gen_mi_mem32(anv_image_get_fast_clear_type_addr(cmd_buffer
->device
,
774 /* This only works for partial resolves and only when the clear color is
775 * all or nothing. On the upside, this emits less command streamer code
776 * and works on Ivybridge and Bay Trail.
778 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
779 assert(fast_clear_supported
!= ANV_FAST_CLEAR_ANY
);
781 /* We don't support fast clears on anything other than the first slice. */
782 if (level
> 0 || array_layer
> 0)
785 /* On gen8, we don't have a concept of default clear colors because we
786 * can't sample from CCS surfaces. It's enough to just load the fast clear
787 * state into the predicate register.
789 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), fast_clear_type_mem
);
790 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
791 gen_mi_store(&b
, fast_clear_type_mem
, gen_mi_imm(0));
793 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
794 mip
.LoadOperation
= LOAD_LOADINV
;
795 mip
.CombineOperation
= COMBINE_SET
;
796 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
799 #endif /* GEN_GEN <= 8 */
802 anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
803 const struct anv_image
*image
,
804 enum isl_format format
,
805 VkImageAspectFlagBits aspect
,
806 uint32_t level
, uint32_t array_layer
,
807 enum isl_aux_op resolve_op
,
808 enum anv_fast_clear_type fast_clear_supported
)
810 const uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
813 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
814 aspect
, level
, array_layer
,
815 resolve_op
, fast_clear_supported
);
816 #else /* GEN_GEN <= 8 */
817 anv_cmd_simple_resolve_predicate(cmd_buffer
, image
,
818 aspect
, level
, array_layer
,
819 resolve_op
, fast_clear_supported
);
822 /* CCS_D only supports full resolves and BLORP will assert on us if we try
823 * to do a partial resolve on a CCS_D surface.
825 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
826 image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_D
)
827 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
829 anv_image_ccs_op(cmd_buffer
, image
, format
, aspect
, level
,
830 array_layer
, 1, resolve_op
, NULL
, true);
834 anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer
*cmd_buffer
,
835 const struct anv_image
*image
,
836 enum isl_format format
,
837 VkImageAspectFlagBits aspect
,
838 uint32_t array_layer
,
839 enum isl_aux_op resolve_op
,
840 enum anv_fast_clear_type fast_clear_supported
)
842 assert(aspect
== VK_IMAGE_ASPECT_COLOR_BIT
);
843 assert(resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
);
845 #if GEN_GEN >= 8 || GEN_IS_HASWELL
846 anv_cmd_compute_resolve_predicate(cmd_buffer
, image
,
847 aspect
, 0, array_layer
,
848 resolve_op
, fast_clear_supported
);
850 anv_image_mcs_op(cmd_buffer
, image
, format
, aspect
,
851 array_layer
, 1, resolve_op
, NULL
, true);
853 unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
858 genX(cmd_buffer_mark_image_written
)(struct anv_cmd_buffer
*cmd_buffer
,
859 const struct anv_image
*image
,
860 VkImageAspectFlagBits aspect
,
861 enum isl_aux_usage aux_usage
,
864 uint32_t layer_count
)
866 /* The aspect must be exactly one of the image aspects. */
867 assert(util_bitcount(aspect
) == 1 && (aspect
& image
->aspects
));
869 /* The only compression types with more than just fast-clears are MCS,
870 * CCS_E, and HiZ. With HiZ we just trust the layout and don't actually
871 * track the current fast-clear and compression state. This leaves us
872 * with just MCS and CCS_E.
874 if (aux_usage
!= ISL_AUX_USAGE_CCS_E
&&
875 aux_usage
!= ISL_AUX_USAGE_MCS
)
878 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
879 level
, base_layer
, layer_count
, true);
883 init_fast_clear_color(struct anv_cmd_buffer
*cmd_buffer
,
884 const struct anv_image
*image
,
885 VkImageAspectFlagBits aspect
)
887 assert(cmd_buffer
&& image
);
888 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
890 set_image_fast_clear_state(cmd_buffer
, image
, aspect
,
891 ANV_FAST_CLEAR_NONE
);
893 /* Initialize the struct fields that are accessed for fast-clears so that
894 * the HW restrictions on the field values are satisfied.
896 struct anv_address addr
=
897 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
900 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
901 const unsigned num_dwords
= GEN_GEN
>= 10 ?
902 isl_dev
->ss
.clear_color_state_size
/ 4 :
903 isl_dev
->ss
.clear_value_size
/ 4;
904 for (unsigned i
= 0; i
< num_dwords
; i
++) {
905 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
907 sdi
.Address
.offset
+= i
* 4;
908 sdi
.ImmediateData
= 0;
912 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_DATA_IMM
), sdi
) {
914 if (GEN_GEN
>= 8 || GEN_IS_HASWELL
) {
915 /* Pre-SKL, the dword containing the clear values also contains
916 * other fields, so we need to initialize those fields to match the
917 * values that would be in a color attachment.
919 sdi
.ImmediateData
= ISL_CHANNEL_SELECT_RED
<< 25 |
920 ISL_CHANNEL_SELECT_GREEN
<< 22 |
921 ISL_CHANNEL_SELECT_BLUE
<< 19 |
922 ISL_CHANNEL_SELECT_ALPHA
<< 16;
923 } else if (GEN_GEN
== 7) {
924 /* On IVB, the dword containing the clear values also contains
925 * other fields that must be zero or can be zero.
927 sdi
.ImmediateData
= 0;
933 /* Copy the fast-clear value dword(s) between a surface state object and an
934 * image's fast clear state buffer.
937 genX(copy_fast_clear_dwords
)(struct anv_cmd_buffer
*cmd_buffer
,
938 struct anv_state surface_state
,
939 const struct anv_image
*image
,
940 VkImageAspectFlagBits aspect
,
941 bool copy_from_surface_state
)
943 assert(cmd_buffer
&& image
);
944 assert(image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
946 struct anv_address ss_clear_addr
= {
947 .bo
= cmd_buffer
->device
->surface_state_pool
.block_pool
.bo
,
948 .offset
= surface_state
.offset
+
949 cmd_buffer
->device
->isl_dev
.ss
.clear_value_offset
,
951 const struct anv_address entry_addr
=
952 anv_image_get_clear_color_addr(cmd_buffer
->device
, image
, aspect
);
953 unsigned copy_size
= cmd_buffer
->device
->isl_dev
.ss
.clear_value_size
;
956 /* On gen7, the combination of commands used here(MI_LOAD_REGISTER_MEM
957 * and MI_STORE_REGISTER_MEM) can cause GPU hangs if any rendering is
958 * in-flight when they are issued even if the memory touched is not
959 * currently active for rendering. The weird bit is that it is not the
960 * MI_LOAD/STORE_REGISTER_MEM commands which hang but rather the in-flight
961 * rendering hangs such that the next stalling command after the
962 * MI_LOAD/STORE_REGISTER_MEM commands will catch the hang.
964 * It is unclear exactly why this hang occurs. Both MI commands come with
965 * warnings about the 3D pipeline but that doesn't seem to fully explain
966 * it. My (Jason's) best theory is that it has something to do with the
967 * fact that we're using a GPU state register as our temporary and that
968 * something with reading/writing it is causing problems.
970 * In order to work around this issue, we emit a PIPE_CONTROL with the
971 * command streamer stall bit set.
973 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
974 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
977 struct gen_mi_builder b
;
978 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
980 if (copy_from_surface_state
) {
981 gen_mi_memcpy(&b
, entry_addr
, ss_clear_addr
, copy_size
);
983 gen_mi_memcpy(&b
, ss_clear_addr
, entry_addr
, copy_size
);
985 /* Updating a surface state object may require that the state cache be
986 * invalidated. From the SKL PRM, Shared Functions -> State -> State
989 * Whenever the RENDER_SURFACE_STATE object in memory pointed to by
990 * the Binding Table Pointer (BTP) and Binding Table Index (BTI) is
991 * modified [...], the L1 state cache must be invalidated to ensure
992 * the new surface or sampler state is fetched from system memory.
994 * In testing, SKL doesn't actually seem to need this, but HSW does.
996 cmd_buffer
->state
.pending_pipe_bits
|=
997 ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
1001 #define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
1005 anv_image_init_aux_tt(struct anv_cmd_buffer
*cmd_buffer
,
1006 const struct anv_image
*image
,
1007 VkImageAspectFlagBits aspect
,
1008 uint32_t base_level
, uint32_t level_count
,
1009 uint32_t base_layer
, uint32_t layer_count
)
1011 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1013 uint64_t base_address
=
1014 anv_address_physical(image
->planes
[plane
].address
);
1016 const struct isl_surf
*isl_surf
= &image
->planes
[plane
].surface
.isl
;
1017 uint64_t format_bits
= gen_aux_map_format_bits_for_isl_surf(isl_surf
);
1019 /* We're about to live-update the AUX-TT. We really don't want anyone else
1020 * trying to read it while we're doing this. We could probably get away
1021 * with not having this stall in some cases if we were really careful but
1022 * it's better to play it safe. Full stall the GPU.
1024 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
1025 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1027 struct gen_mi_builder b
;
1028 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
1030 for (uint32_t a
= 0; a
< layer_count
; a
++) {
1031 const uint32_t layer
= base_layer
+ a
;
1033 uint64_t start_offset_B
= UINT64_MAX
, end_offset_B
= 0;
1034 for (uint32_t l
= 0; l
< level_count
; l
++) {
1035 const uint32_t level
= base_level
+ l
;
1037 uint32_t logical_array_layer
, logical_z_offset_px
;
1038 if (image
->type
== VK_IMAGE_TYPE_3D
) {
1039 logical_array_layer
= 0;
1041 /* If the given miplevel does not have this layer, then any higher
1042 * miplevels won't either because miplevels only get smaller the
1045 assert(layer
< image
->extent
.depth
);
1046 if (layer
>= anv_minify(image
->extent
.depth
, level
))
1048 logical_z_offset_px
= layer
;
1050 assert(layer
< image
->array_size
);
1051 logical_array_layer
= layer
;
1052 logical_z_offset_px
= 0;
1055 uint32_t slice_start_offset_B
, slice_end_offset_B
;
1056 isl_surf_get_image_range_B_tile(isl_surf
, level
,
1057 logical_array_layer
,
1058 logical_z_offset_px
,
1059 &slice_start_offset_B
,
1060 &slice_end_offset_B
);
1062 start_offset_B
= MIN2(start_offset_B
, slice_start_offset_B
);
1063 end_offset_B
= MAX2(end_offset_B
, slice_end_offset_B
);
1066 /* Aux operates 64K at a time */
1067 start_offset_B
= align_down_u64(start_offset_B
, 64 * 1024);
1068 end_offset_B
= align_u64(end_offset_B
, 64 * 1024);
1070 for (uint64_t offset
= start_offset_B
;
1071 offset
< end_offset_B
; offset
+= 64 * 1024) {
1072 uint64_t address
= base_address
+ offset
;
1074 uint64_t aux_entry_addr64
, *aux_entry_map
;
1075 aux_entry_map
= gen_aux_map_get_entry(cmd_buffer
->device
->aux_map_ctx
,
1076 address
, &aux_entry_addr64
);
1078 assert(cmd_buffer
->device
->physical
->use_softpin
);
1079 struct anv_address aux_entry_address
= {
1081 .offset
= aux_entry_addr64
,
1084 const uint64_t old_aux_entry
= READ_ONCE(*aux_entry_map
);
1085 uint64_t new_aux_entry
=
1086 (old_aux_entry
& GEN_AUX_MAP_ADDRESS_MASK
) | format_bits
;
1088 if (isl_aux_usage_has_ccs(image
->planes
[plane
].aux_usage
))
1089 new_aux_entry
|= GEN_AUX_MAP_ENTRY_VALID_BIT
;
1091 gen_mi_store(&b
, gen_mi_mem64(aux_entry_address
),
1092 gen_mi_imm(new_aux_entry
));
1096 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1098 #endif /* GEN_GEN == 12 */
1101 * @brief Transitions a color buffer from one layout to another.
1103 * See section 6.1.1. Image Layout Transitions of the Vulkan 1.0.50 spec for
1106 * @param level_count VK_REMAINING_MIP_LEVELS isn't supported.
1107 * @param layer_count VK_REMAINING_ARRAY_LAYERS isn't supported. For 3D images,
1108 * this represents the maximum layers to transition at each
1109 * specified miplevel.
1112 transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer
,
1113 const struct anv_image
*image
,
1114 VkImageAspectFlagBits aspect
,
1115 const uint32_t base_level
, uint32_t level_count
,
1116 uint32_t base_layer
, uint32_t layer_count
,
1117 VkImageLayout initial_layout
,
1118 VkImageLayout final_layout
)
1120 struct anv_device
*device
= cmd_buffer
->device
;
1121 const struct gen_device_info
*devinfo
= &device
->info
;
1122 /* Validate the inputs. */
1124 assert(image
&& image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
);
1125 /* These values aren't supported for simplicity's sake. */
1126 assert(level_count
!= VK_REMAINING_MIP_LEVELS
&&
1127 layer_count
!= VK_REMAINING_ARRAY_LAYERS
);
1128 /* Ensure the subresource range is valid. */
1129 UNUSED
uint64_t last_level_num
= base_level
+ level_count
;
1130 const uint32_t max_depth
= anv_minify(image
->extent
.depth
, base_level
);
1131 UNUSED
const uint32_t image_layers
= MAX2(image
->array_size
, max_depth
);
1132 assert((uint64_t)base_layer
+ layer_count
<= image_layers
);
1133 assert(last_level_num
<= image
->levels
);
1134 /* The spec disallows these final layouts. */
1135 assert(final_layout
!= VK_IMAGE_LAYOUT_UNDEFINED
&&
1136 final_layout
!= VK_IMAGE_LAYOUT_PREINITIALIZED
);
1138 /* No work is necessary if the layout stays the same or if this subresource
1139 * range lacks auxiliary data.
1141 if (initial_layout
== final_layout
)
1144 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
, aspect
);
1146 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
1147 final_layout
== VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL
) {
1148 /* This surface is a linear compressed image with a tiled shadow surface
1149 * for texturing. The client is about to use it in READ_ONLY_OPTIMAL so
1150 * we need to ensure the shadow copy is up-to-date.
1152 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1153 assert(image
->planes
[plane
].surface
.isl
.tiling
== ISL_TILING_LINEAR
);
1154 assert(image
->planes
[plane
].shadow_surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1155 assert(isl_format_is_compressed(image
->planes
[plane
].surface
.isl
.format
));
1157 anv_image_copy_to_shadow(cmd_buffer
, image
,
1158 VK_IMAGE_ASPECT_COLOR_BIT
,
1159 base_level
, level_count
,
1160 base_layer
, layer_count
);
1163 if (base_layer
>= anv_image_aux_layers(image
, aspect
, base_level
))
1166 assert(image
->planes
[plane
].surface
.isl
.tiling
!= ISL_TILING_LINEAR
);
1168 if (initial_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
1169 initial_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
) {
1171 if (device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
) {
1172 anv_image_init_aux_tt(cmd_buffer
, image
, aspect
,
1173 base_level
, level_count
,
1174 base_layer
, layer_count
);
1177 assert(!(device
->physical
->has_implicit_ccs
&& devinfo
->has_aux_map
));
1180 /* A subresource in the undefined layout may have been aliased and
1181 * populated with any arrangement of bits. Therefore, we must initialize
1182 * the related aux buffer and clear buffer entry with desirable values.
1183 * An initial layout of PREINITIALIZED is the same as UNDEFINED for
1184 * images with VK_IMAGE_TILING_OPTIMAL.
1186 * Initialize the relevant clear buffer entries.
1188 if (base_level
== 0 && base_layer
== 0)
1189 init_fast_clear_color(cmd_buffer
, image
, aspect
);
1191 /* Initialize the aux buffers to enable correct rendering. In order to
1192 * ensure that things such as storage images work correctly, aux buffers
1193 * need to be initialized to valid data.
1195 * Having an aux buffer with invalid data is a problem for two reasons:
1197 * 1) Having an invalid value in the buffer can confuse the hardware.
1198 * For instance, with CCS_E on SKL, a two-bit CCS value of 2 is
1199 * invalid and leads to the hardware doing strange things. It
1200 * doesn't hang as far as we can tell but rendering corruption can
1203 * 2) If this transition is into the GENERAL layout and we then use the
1204 * image as a storage image, then we must have the aux buffer in the
1205 * pass-through state so that, if we then go to texture from the
1206 * image, we get the results of our storage image writes and not the
1207 * fast clear color or other random data.
1209 * For CCS both of the problems above are real demonstrable issues. In
1210 * that case, the only thing we can do is to perform an ambiguate to
1211 * transition the aux surface into the pass-through state.
1213 * For MCS, (2) is never an issue because we don't support multisampled
1214 * storage images. In theory, issue (1) is a problem with MCS but we've
1215 * never seen it in the wild. For 4x and 16x, all bit patters could, in
1216 * theory, be interpreted as something but we don't know that all bit
1217 * patterns are actually valid. For 2x and 8x, you could easily end up
1218 * with the MCS referring to an invalid plane because not all bits of
1219 * the MCS value are actually used. Even though we've never seen issues
1220 * in the wild, it's best to play it safe and initialize the MCS. We
1221 * can use a fast-clear for MCS because we only ever touch from render
1222 * and texture (no image load store).
1224 if (image
->samples
== 1) {
1225 for (uint32_t l
= 0; l
< level_count
; l
++) {
1226 const uint32_t level
= base_level
+ l
;
1228 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1229 if (base_layer
>= aux_layers
)
1230 break; /* We will only get fewer layers as level increases */
1231 uint32_t level_layer_count
=
1232 MIN2(layer_count
, aux_layers
- base_layer
);
1234 anv_image_ccs_op(cmd_buffer
, image
,
1235 image
->planes
[plane
].surface
.isl
.format
,
1236 aspect
, level
, base_layer
, level_layer_count
,
1237 ISL_AUX_OP_AMBIGUATE
, NULL
, false);
1239 if (image
->planes
[plane
].aux_usage
== ISL_AUX_USAGE_CCS_E
) {
1240 set_image_compressed_bit(cmd_buffer
, image
, aspect
,
1241 level
, base_layer
, level_layer_count
,
1246 if (image
->samples
== 4 || image
->samples
== 16) {
1247 anv_perf_warn(cmd_buffer
->device
, image
,
1248 "Doing a potentially unnecessary fast-clear to "
1249 "define an MCS buffer.");
1252 assert(base_level
== 0 && level_count
== 1);
1253 anv_image_mcs_op(cmd_buffer
, image
,
1254 image
->planes
[plane
].surface
.isl
.format
,
1255 aspect
, base_layer
, layer_count
,
1256 ISL_AUX_OP_FAST_CLEAR
, NULL
, false);
1261 const enum isl_aux_usage initial_aux_usage
=
1262 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, initial_layout
);
1263 const enum isl_aux_usage final_aux_usage
=
1264 anv_layout_to_aux_usage(devinfo
, image
, aspect
, 0, final_layout
);
1266 /* The current code assumes that there is no mixing of CCS_E and CCS_D.
1267 * We can handle transitions between CCS_D/E to and from NONE. What we
1268 * don't yet handle is switching between CCS_E and CCS_D within a given
1269 * image. Doing so in a performant way requires more detailed aux state
1270 * tracking such as what is done in i965. For now, just assume that we
1271 * only have one type of compression.
1273 assert(initial_aux_usage
== ISL_AUX_USAGE_NONE
||
1274 final_aux_usage
== ISL_AUX_USAGE_NONE
||
1275 initial_aux_usage
== final_aux_usage
);
1277 /* If initial aux usage is NONE, there is nothing to resolve */
1278 if (initial_aux_usage
== ISL_AUX_USAGE_NONE
)
1281 enum isl_aux_op resolve_op
= ISL_AUX_OP_NONE
;
1283 /* If the initial layout supports more fast clear than the final layout
1284 * then we need at least a partial resolve.
1286 const enum anv_fast_clear_type initial_fast_clear
=
1287 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, initial_layout
);
1288 const enum anv_fast_clear_type final_fast_clear
=
1289 anv_layout_to_fast_clear_type(devinfo
, image
, aspect
, final_layout
);
1290 if (final_fast_clear
< initial_fast_clear
)
1291 resolve_op
= ISL_AUX_OP_PARTIAL_RESOLVE
;
1293 if (initial_aux_usage
== ISL_AUX_USAGE_CCS_E
&&
1294 final_aux_usage
!= ISL_AUX_USAGE_CCS_E
)
1295 resolve_op
= ISL_AUX_OP_FULL_RESOLVE
;
1297 if (resolve_op
== ISL_AUX_OP_NONE
)
1300 /* Perform a resolve to synchronize data between the main and aux buffer.
1301 * Before we begin, we must satisfy the cache flushing requirement specified
1302 * in the Sky Lake PRM Vol. 7, "MCS Buffer for Render Target(s)":
1304 * Any transition from any value in {Clear, Render, Resolve} to a
1305 * different value in {Clear, Render, Resolve} requires end of pipe
1308 * We perform a flush of the write cache before and after the clear and
1309 * resolve operations to meet this requirement.
1311 * Unlike other drawing, fast clear operations are not properly
1312 * synchronized. The first PIPE_CONTROL here likely ensures that the
1313 * contents of the previous render or clear hit the render target before we
1314 * resolve and the second likely ensures that the resolve is complete before
1315 * we do any more rendering or clearing.
1317 cmd_buffer
->state
.pending_pipe_bits
|=
1318 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1320 for (uint32_t l
= 0; l
< level_count
; l
++) {
1321 uint32_t level
= base_level
+ l
;
1323 uint32_t aux_layers
= anv_image_aux_layers(image
, aspect
, level
);
1324 if (base_layer
>= aux_layers
)
1325 break; /* We will only get fewer layers as level increases */
1326 uint32_t level_layer_count
=
1327 MIN2(layer_count
, aux_layers
- base_layer
);
1329 for (uint32_t a
= 0; a
< level_layer_count
; a
++) {
1330 uint32_t array_layer
= base_layer
+ a
;
1331 if (image
->samples
== 1) {
1332 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
1333 image
->planes
[plane
].surface
.isl
.format
,
1334 aspect
, level
, array_layer
, resolve_op
,
1337 /* We only support fast-clear on the first layer so partial
1338 * resolves should not be used on other layers as they will use
1339 * the clear color stored in memory that is only valid for layer0.
1341 if (resolve_op
== ISL_AUX_OP_PARTIAL_RESOLVE
&&
1345 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
1346 image
->planes
[plane
].surface
.isl
.format
,
1347 aspect
, array_layer
, resolve_op
,
1353 cmd_buffer
->state
.pending_pipe_bits
|=
1354 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
| ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
1358 * Setup anv_cmd_state::attachments for vkCmdBeginRenderPass.
1361 genX(cmd_buffer_setup_attachments
)(struct anv_cmd_buffer
*cmd_buffer
,
1362 struct anv_render_pass
*pass
,
1363 const VkRenderPassBeginInfo
*begin
)
1365 const struct isl_device
*isl_dev
= &cmd_buffer
->device
->isl_dev
;
1366 struct anv_cmd_state
*state
= &cmd_buffer
->state
;
1367 struct anv_framebuffer
*framebuffer
= cmd_buffer
->state
.framebuffer
;
1369 vk_free(&cmd_buffer
->pool
->alloc
, state
->attachments
);
1371 if (pass
->attachment_count
> 0) {
1372 state
->attachments
= vk_alloc(&cmd_buffer
->pool
->alloc
,
1373 pass
->attachment_count
*
1374 sizeof(state
->attachments
[0]),
1375 8, VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1376 if (state
->attachments
== NULL
) {
1377 /* Propagate VK_ERROR_OUT_OF_HOST_MEMORY to vkEndCommandBuffer */
1378 return anv_batch_set_error(&cmd_buffer
->batch
,
1379 VK_ERROR_OUT_OF_HOST_MEMORY
);
1382 state
->attachments
= NULL
;
1385 /* Reserve one for the NULL state. */
1386 unsigned num_states
= 1;
1387 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1388 if (vk_format_is_color(pass
->attachments
[i
].format
))
1391 if (need_input_attachment_state(&pass
->attachments
[i
]))
1395 const uint32_t ss_stride
= align_u32(isl_dev
->ss
.size
, isl_dev
->ss
.align
);
1396 state
->render_pass_states
=
1397 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
,
1398 num_states
* ss_stride
, isl_dev
->ss
.align
);
1400 struct anv_state next_state
= state
->render_pass_states
;
1401 next_state
.alloc_size
= isl_dev
->ss
.size
;
1403 state
->null_surface_state
= next_state
;
1404 next_state
.offset
+= ss_stride
;
1405 next_state
.map
+= ss_stride
;
1407 const VkRenderPassAttachmentBeginInfoKHR
*begin_attachment
=
1408 vk_find_struct_const(begin
, RENDER_PASS_ATTACHMENT_BEGIN_INFO_KHR
);
1410 if (begin
&& !begin_attachment
)
1411 assert(pass
->attachment_count
== framebuffer
->attachment_count
);
1413 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1414 if (vk_format_is_color(pass
->attachments
[i
].format
)) {
1415 state
->attachments
[i
].color
.state
= next_state
;
1416 next_state
.offset
+= ss_stride
;
1417 next_state
.map
+= ss_stride
;
1420 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1421 state
->attachments
[i
].input
.state
= next_state
;
1422 next_state
.offset
+= ss_stride
;
1423 next_state
.map
+= ss_stride
;
1426 if (begin_attachment
&& begin_attachment
->attachmentCount
!= 0) {
1427 assert(begin_attachment
->attachmentCount
== pass
->attachment_count
);
1428 ANV_FROM_HANDLE(anv_image_view
, iview
, begin_attachment
->pAttachments
[i
]);
1429 cmd_buffer
->state
.attachments
[i
].image_view
= iview
;
1430 } else if (framebuffer
&& i
< framebuffer
->attachment_count
) {
1431 cmd_buffer
->state
.attachments
[i
].image_view
= framebuffer
->attachments
[i
];
1434 assert(next_state
.offset
== state
->render_pass_states
.offset
+
1435 state
->render_pass_states
.alloc_size
);
1438 isl_null_fill_state(isl_dev
, state
->null_surface_state
.map
,
1439 isl_extent3d(framebuffer
->width
,
1440 framebuffer
->height
,
1441 framebuffer
->layers
));
1443 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1444 struct anv_render_pass_attachment
*att
= &pass
->attachments
[i
];
1445 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1446 VkImageAspectFlags clear_aspects
= 0;
1447 VkImageAspectFlags load_aspects
= 0;
1449 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1450 /* color attachment */
1451 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1452 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1453 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1454 load_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1457 /* depthstencil attachment */
1458 if (att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
1459 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1460 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1461 } else if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1462 load_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1465 if (att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
1466 if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1467 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1468 } else if (att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_LOAD
) {
1469 load_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1474 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1475 state
->attachments
[i
].current_stencil_layout
= att
->stencil_initial_layout
;
1476 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1477 state
->attachments
[i
].pending_load_aspects
= load_aspects
;
1479 state
->attachments
[i
].clear_value
= begin
->pClearValues
[i
];
1481 struct anv_image_view
*iview
= cmd_buffer
->state
.attachments
[i
].image_view
;
1482 anv_assert(iview
->vk_format
== att
->format
);
1484 const uint32_t num_layers
= iview
->planes
[0].isl
.array_len
;
1485 state
->attachments
[i
].pending_clear_views
= (1 << num_layers
) - 1;
1487 union isl_color_value clear_color
= { .u32
= { 0, } };
1488 if (att_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
1489 anv_assert(iview
->n_planes
== 1);
1490 assert(att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
1491 color_attachment_compute_aux_usage(cmd_buffer
->device
,
1492 state
, i
, begin
->renderArea
,
1495 anv_image_fill_surface_state(cmd_buffer
->device
,
1497 VK_IMAGE_ASPECT_COLOR_BIT
,
1498 &iview
->planes
[0].isl
,
1499 ISL_SURF_USAGE_RENDER_TARGET_BIT
,
1500 state
->attachments
[i
].aux_usage
,
1503 &state
->attachments
[i
].color
,
1506 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].color
);
1508 depth_stencil_attachment_compute_aux_usage(cmd_buffer
->device
,
1513 if (need_input_attachment_state(&pass
->attachments
[i
])) {
1514 anv_image_fill_surface_state(cmd_buffer
->device
,
1516 VK_IMAGE_ASPECT_COLOR_BIT
,
1517 &iview
->planes
[0].isl
,
1518 ISL_SURF_USAGE_TEXTURE_BIT
,
1519 state
->attachments
[i
].input_aux_usage
,
1522 &state
->attachments
[i
].input
,
1525 add_surface_state_relocs(cmd_buffer
, state
->attachments
[i
].input
);
1534 genX(BeginCommandBuffer
)(
1535 VkCommandBuffer commandBuffer
,
1536 const VkCommandBufferBeginInfo
* pBeginInfo
)
1538 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1540 /* If this is the first vkBeginCommandBuffer, we must *initialize* the
1541 * command buffer's state. Otherwise, we must *reset* its state. In both
1542 * cases we reset it.
1544 * From the Vulkan 1.0 spec:
1546 * If a command buffer is in the executable state and the command buffer
1547 * was allocated from a command pool with the
1548 * VK_COMMAND_POOL_CREATE_RESET_COMMAND_BUFFER_BIT flag set, then
1549 * vkBeginCommandBuffer implicitly resets the command buffer, behaving
1550 * as if vkResetCommandBuffer had been called with
1551 * VK_COMMAND_BUFFER_RESET_RELEASE_RESOURCES_BIT not set. It then puts
1552 * the command buffer in the recording state.
1554 anv_cmd_buffer_reset(cmd_buffer
);
1556 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1558 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
||
1559 !(cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
));
1561 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
1563 /* We sometimes store vertex data in the dynamic state buffer for blorp
1564 * operations and our dynamic state stream may re-use data from previous
1565 * command buffers. In order to prevent stale cache data, we flush the VF
1566 * cache. We could do this on every blorp call but that's not really
1567 * needed as all of the data will get written by the CPU prior to the GPU
1568 * executing anything. The chances are fairly high that they will use
1569 * blorp at least once per primary command buffer so it shouldn't be
1572 * There is also a workaround on gen8 which requires us to invalidate the
1573 * VF cache occasionally. It's easier if we can assume we start with a
1574 * fresh cache (See also genX(cmd_buffer_set_binding_for_gen8_vb_flush).)
1576 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1578 /* Re-emit the aux table register in every command buffer. This way we're
1579 * ensured that we have the table even if this command buffer doesn't
1580 * initialize any images.
1582 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
;
1584 /* We send an "Indirect State Pointers Disable" packet at
1585 * EndCommandBuffer, so all push contant packets are ignored during a
1586 * context restore. Documentation says after that command, we need to
1587 * emit push constants again before any rendering operation. So we
1588 * flag them dirty here to make sure they get emitted.
1590 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
1592 VkResult result
= VK_SUCCESS
;
1593 if (cmd_buffer
->usage_flags
&
1594 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1595 assert(pBeginInfo
->pInheritanceInfo
);
1596 cmd_buffer
->state
.pass
=
1597 anv_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1598 cmd_buffer
->state
.subpass
=
1599 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1601 /* This is optional in the inheritance info. */
1602 cmd_buffer
->state
.framebuffer
=
1603 anv_framebuffer_from_handle(pBeginInfo
->pInheritanceInfo
->framebuffer
);
1605 result
= genX(cmd_buffer_setup_attachments
)(cmd_buffer
,
1606 cmd_buffer
->state
.pass
, NULL
);
1608 /* Record that HiZ is enabled if we can. */
1609 if (cmd_buffer
->state
.framebuffer
) {
1610 const struct anv_image_view
* const iview
=
1611 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
1614 VkImageLayout layout
=
1615 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->layout
;
1617 enum isl_aux_usage aux_usage
=
1618 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, iview
->image
,
1619 VK_IMAGE_ASPECT_DEPTH_BIT
,
1620 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
1623 cmd_buffer
->state
.hiz_enabled
= aux_usage
== ISL_AUX_USAGE_HIZ
;
1627 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
1630 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1631 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1632 const VkCommandBufferInheritanceConditionalRenderingInfoEXT
*conditional_rendering_info
=
1633 vk_find_struct_const(pBeginInfo
->pInheritanceInfo
->pNext
, COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT
);
1635 /* If secondary buffer supports conditional rendering
1636 * we should emit commands as if conditional rendering is enabled.
1638 cmd_buffer
->state
.conditional_render_enabled
=
1639 conditional_rendering_info
&& conditional_rendering_info
->conditionalRenderingEnable
;
1646 /* From the PRM, Volume 2a:
1648 * "Indirect State Pointers Disable
1650 * At the completion of the post-sync operation associated with this pipe
1651 * control packet, the indirect state pointers in the hardware are
1652 * considered invalid; the indirect pointers are not saved in the context.
1653 * If any new indirect state commands are executed in the command stream
1654 * while the pipe control is pending, the new indirect state commands are
1657 * [DevIVB+]: Using Invalidate State Pointer (ISP) only inhibits context
1658 * restoring of Push Constant (3DSTATE_CONSTANT_*) commands. Push Constant
1659 * commands are only considered as Indirect State Pointers. Once ISP is
1660 * issued in a context, SW must initialize by programming push constant
1661 * commands for all the shaders (at least to zero length) before attempting
1662 * any rendering operation for the same context."
1664 * 3DSTATE_CONSTANT_* packets are restored during a context restore,
1665 * even though they point to a BO that has been already unreferenced at
1666 * the end of the previous batch buffer. This has been fine so far since
1667 * we are protected by these scratch page (every address not covered by
1668 * a BO should be pointing to the scratch page). But on CNL, it is
1669 * causing a GPU hang during context restore at the 3DSTATE_CONSTANT_*
1672 * The flag "Indirect State Pointers Disable" in PIPE_CONTROL tells the
1673 * hardware to ignore previous 3DSTATE_CONSTANT_* packets during a
1674 * context restore, so the mentioned hang doesn't happen. However,
1675 * software must program push constant commands for all stages prior to
1676 * rendering anything. So we flag them dirty in BeginCommandBuffer.
1678 * Finally, we also make sure to stall at pixel scoreboard to make sure the
1679 * constants have been loaded into the EUs prior to disable the push constants
1680 * so that it doesn't hang a previous 3DPRIMITIVE.
1683 emit_isp_disable(struct anv_cmd_buffer
*cmd_buffer
)
1685 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1686 pc
.StallAtPixelScoreboard
= true;
1687 pc
.CommandStreamerStallEnable
= true;
1689 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1690 pc
.IndirectStatePointersDisable
= true;
1691 pc
.CommandStreamerStallEnable
= true;
1696 genX(EndCommandBuffer
)(
1697 VkCommandBuffer commandBuffer
)
1699 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
1701 if (anv_batch_has_error(&cmd_buffer
->batch
))
1702 return cmd_buffer
->batch
.status
;
1704 /* We want every command buffer to start with the PMA fix in a known state,
1705 * so we disable it at the end of the command buffer.
1707 genX(cmd_buffer_enable_pma_fix
)(cmd_buffer
, false);
1709 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
1711 emit_isp_disable(cmd_buffer
);
1713 anv_cmd_buffer_end_batch_buffer(cmd_buffer
);
1719 genX(CmdExecuteCommands
)(
1720 VkCommandBuffer commandBuffer
,
1721 uint32_t commandBufferCount
,
1722 const VkCommandBuffer
* pCmdBuffers
)
1724 ANV_FROM_HANDLE(anv_cmd_buffer
, primary
, commandBuffer
);
1726 assert(primary
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1728 if (anv_batch_has_error(&primary
->batch
))
1731 /* The secondary command buffers will assume that the PMA fix is disabled
1732 * when they begin executing. Make sure this is true.
1734 genX(cmd_buffer_enable_pma_fix
)(primary
, false);
1736 /* The secondary command buffer doesn't know which textures etc. have been
1737 * flushed prior to their execution. Apply those flushes now.
1739 genX(cmd_buffer_apply_pipe_flushes
)(primary
);
1741 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1742 ANV_FROM_HANDLE(anv_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
1744 assert(secondary
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
);
1745 assert(!anv_batch_has_error(&secondary
->batch
));
1747 #if GEN_GEN >= 8 || GEN_IS_HASWELL
1748 if (secondary
->state
.conditional_render_enabled
) {
1749 if (!primary
->state
.conditional_render_enabled
) {
1750 /* Secondary buffer is constructed as if it will be executed
1751 * with conditional rendering, we should satisfy this dependency
1752 * regardless of conditional rendering being enabled in primary.
1754 struct gen_mi_builder b
;
1755 gen_mi_builder_init(&b
, &primary
->batch
);
1756 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
1757 gen_mi_imm(UINT64_MAX
));
1762 if (secondary
->usage_flags
&
1763 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1764 /* If we're continuing a render pass from the primary, we need to
1765 * copy the surface states for the current subpass into the storage
1766 * we allocated for them in BeginCommandBuffer.
1768 struct anv_bo
*ss_bo
=
1769 primary
->device
->surface_state_pool
.block_pool
.bo
;
1770 struct anv_state src_state
= primary
->state
.render_pass_states
;
1771 struct anv_state dst_state
= secondary
->state
.render_pass_states
;
1772 assert(src_state
.alloc_size
== dst_state
.alloc_size
);
1774 genX(cmd_buffer_so_memcpy
)(primary
,
1775 (struct anv_address
) {
1777 .offset
= dst_state
.offset
,
1779 (struct anv_address
) {
1781 .offset
= src_state
.offset
,
1783 src_state
.alloc_size
);
1786 anv_cmd_buffer_add_secondary(primary
, secondary
);
1789 /* The secondary isn't counted in our VF cache tracking so we need to
1790 * invalidate the whole thing.
1792 if (GEN_GEN
>= 8 && GEN_GEN
<= 9) {
1793 primary
->state
.pending_pipe_bits
|=
1794 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
1797 /* The secondary may have selected a different pipeline (3D or compute) and
1798 * may have changed the current L3$ configuration. Reset our tracking
1799 * variables to invalid values to ensure that we re-emit these in the case
1800 * where we do any draws or compute dispatches from the primary after the
1801 * secondary has returned.
1803 primary
->state
.current_pipeline
= UINT32_MAX
;
1804 primary
->state
.current_l3_config
= NULL
;
1805 primary
->state
.current_hash_scale
= 0;
1807 /* Each of the secondary command buffers will use its own state base
1808 * address. We need to re-emit state base address for the primary after
1809 * all of the secondaries are done.
1811 * TODO: Maybe we want to make this a dirty bit to avoid extra state base
1814 genX(cmd_buffer_emit_state_base_address
)(primary
);
1817 #define IVB_L3SQCREG1_SQGHPCI_DEFAULT 0x00730000
1818 #define VLV_L3SQCREG1_SQGHPCI_DEFAULT 0x00d30000
1819 #define HSW_L3SQCREG1_SQGHPCI_DEFAULT 0x00610000
1822 * Program the hardware to use the specified L3 configuration.
1825 genX(cmd_buffer_config_l3
)(struct anv_cmd_buffer
*cmd_buffer
,
1826 const struct gen_l3_config
*cfg
)
1829 if (cfg
== cmd_buffer
->state
.current_l3_config
)
1832 if (unlikely(INTEL_DEBUG
& DEBUG_L3
)) {
1833 intel_logd("L3 config transition: ");
1834 gen_dump_l3_config(cfg
, stderr
);
1837 UNUSED
const bool has_slm
= cfg
->n
[GEN_L3P_SLM
];
1839 /* According to the hardware docs, the L3 partitioning can only be changed
1840 * while the pipeline is completely drained and the caches are flushed,
1841 * which involves a first PIPE_CONTROL flush which stalls the pipeline...
1843 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1844 pc
.DCFlushEnable
= true;
1845 pc
.PostSyncOperation
= NoWrite
;
1846 pc
.CommandStreamerStallEnable
= true;
1849 /* ...followed by a second pipelined PIPE_CONTROL that initiates
1850 * invalidation of the relevant caches. Note that because RO invalidation
1851 * happens at the top of the pipeline (i.e. right away as the PIPE_CONTROL
1852 * command is processed by the CS) we cannot combine it with the previous
1853 * stalling flush as the hardware documentation suggests, because that
1854 * would cause the CS to stall on previous rendering *after* RO
1855 * invalidation and wouldn't prevent the RO caches from being polluted by
1856 * concurrent rendering before the stall completes. This intentionally
1857 * doesn't implement the SKL+ hardware workaround suggesting to enable CS
1858 * stall on PIPE_CONTROLs with the texture cache invalidation bit set for
1859 * GPGPU workloads because the previous and subsequent PIPE_CONTROLs
1860 * already guarantee that there is no concurrent GPGPU kernel execution
1861 * (see SKL HSD 2132585).
1863 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1864 pc
.TextureCacheInvalidationEnable
= true;
1865 pc
.ConstantCacheInvalidationEnable
= true;
1866 pc
.InstructionCacheInvalidateEnable
= true;
1867 pc
.StateCacheInvalidationEnable
= true;
1868 pc
.PostSyncOperation
= NoWrite
;
1871 /* Now send a third stalling flush to make sure that invalidation is
1872 * complete when the L3 configuration registers are modified.
1874 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
1875 pc
.DCFlushEnable
= true;
1876 pc
.PostSyncOperation
= NoWrite
;
1877 pc
.CommandStreamerStallEnable
= true;
1882 assert(!cfg
->n
[GEN_L3P_IS
] && !cfg
->n
[GEN_L3P_C
] && !cfg
->n
[GEN_L3P_T
]);
1885 #define L3_ALLOCATION_REG GENX(L3ALLOC)
1886 #define L3_ALLOCATION_REG_num GENX(L3ALLOC_num)
1888 #define L3_ALLOCATION_REG GENX(L3CNTLREG)
1889 #define L3_ALLOCATION_REG_num GENX(L3CNTLREG_num)
1893 anv_pack_struct(&l3cr
, L3_ALLOCATION_REG
,
1895 .SLMEnable
= has_slm
,
1898 /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
1899 * in L3CNTLREG register. The default setting of the bit is not the
1900 * desirable behavior.
1902 .ErrorDetectionBehaviorControl
= true,
1903 .UseFullWays
= true,
1905 .URBAllocation
= cfg
->n
[GEN_L3P_URB
],
1906 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1907 .DCAllocation
= cfg
->n
[GEN_L3P_DC
],
1908 .AllAllocation
= cfg
->n
[GEN_L3P_ALL
]);
1910 /* Set up the L3 partitioning. */
1911 emit_lri(&cmd_buffer
->batch
, L3_ALLOCATION_REG_num
, l3cr
);
1915 const bool has_dc
= cfg
->n
[GEN_L3P_DC
] || cfg
->n
[GEN_L3P_ALL
];
1916 const bool has_is
= cfg
->n
[GEN_L3P_IS
] || cfg
->n
[GEN_L3P_RO
] ||
1917 cfg
->n
[GEN_L3P_ALL
];
1918 const bool has_c
= cfg
->n
[GEN_L3P_C
] || cfg
->n
[GEN_L3P_RO
] ||
1919 cfg
->n
[GEN_L3P_ALL
];
1920 const bool has_t
= cfg
->n
[GEN_L3P_T
] || cfg
->n
[GEN_L3P_RO
] ||
1921 cfg
->n
[GEN_L3P_ALL
];
1923 assert(!cfg
->n
[GEN_L3P_ALL
]);
1925 /* When enabled SLM only uses a portion of the L3 on half of the banks,
1926 * the matching space on the remaining banks has to be allocated to a
1927 * client (URB for all validated configurations) set to the
1928 * lower-bandwidth 2-bank address hashing mode.
1930 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1931 const bool urb_low_bw
= has_slm
&& !devinfo
->is_baytrail
;
1932 assert(!urb_low_bw
|| cfg
->n
[GEN_L3P_URB
] == cfg
->n
[GEN_L3P_SLM
]);
1934 /* Minimum number of ways that can be allocated to the URB. */
1935 const unsigned n0_urb
= devinfo
->is_baytrail
? 32 : 0;
1936 assert(cfg
->n
[GEN_L3P_URB
] >= n0_urb
);
1938 uint32_t l3sqcr1
, l3cr2
, l3cr3
;
1939 anv_pack_struct(&l3sqcr1
, GENX(L3SQCREG1
),
1940 .ConvertDC_UC
= !has_dc
,
1941 .ConvertIS_UC
= !has_is
,
1942 .ConvertC_UC
= !has_c
,
1943 .ConvertT_UC
= !has_t
);
1945 GEN_IS_HASWELL
? HSW_L3SQCREG1_SQGHPCI_DEFAULT
:
1946 devinfo
->is_baytrail
? VLV_L3SQCREG1_SQGHPCI_DEFAULT
:
1947 IVB_L3SQCREG1_SQGHPCI_DEFAULT
;
1949 anv_pack_struct(&l3cr2
, GENX(L3CNTLREG2
),
1950 .SLMEnable
= has_slm
,
1951 .URBLowBandwidth
= urb_low_bw
,
1952 .URBAllocation
= cfg
->n
[GEN_L3P_URB
] - n0_urb
,
1954 .ALLAllocation
= cfg
->n
[GEN_L3P_ALL
],
1956 .ROAllocation
= cfg
->n
[GEN_L3P_RO
],
1957 .DCAllocation
= cfg
->n
[GEN_L3P_DC
]);
1959 anv_pack_struct(&l3cr3
, GENX(L3CNTLREG3
),
1960 .ISAllocation
= cfg
->n
[GEN_L3P_IS
],
1961 .ISLowBandwidth
= 0,
1962 .CAllocation
= cfg
->n
[GEN_L3P_C
],
1964 .TAllocation
= cfg
->n
[GEN_L3P_T
],
1965 .TLowBandwidth
= 0);
1967 /* Set up the L3 partitioning. */
1968 emit_lri(&cmd_buffer
->batch
, GENX(L3SQCREG1_num
), l3sqcr1
);
1969 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG2_num
), l3cr2
);
1970 emit_lri(&cmd_buffer
->batch
, GENX(L3CNTLREG3_num
), l3cr3
);
1973 if (cmd_buffer
->device
->physical
->cmd_parser_version
>= 4) {
1974 /* Enable L3 atomics on HSW if we have a DC partition, otherwise keep
1975 * them disabled to avoid crashing the system hard.
1977 uint32_t scratch1
, chicken3
;
1978 anv_pack_struct(&scratch1
, GENX(SCRATCH1
),
1979 .L3AtomicDisable
= !has_dc
);
1980 anv_pack_struct(&chicken3
, GENX(CHICKEN3
),
1981 .L3AtomicDisableMask
= true,
1982 .L3AtomicDisable
= !has_dc
);
1983 emit_lri(&cmd_buffer
->batch
, GENX(SCRATCH1_num
), scratch1
);
1984 emit_lri(&cmd_buffer
->batch
, GENX(CHICKEN3_num
), chicken3
);
1990 cmd_buffer
->state
.current_l3_config
= cfg
;
1994 genX(cmd_buffer_apply_pipe_flushes
)(struct anv_cmd_buffer
*cmd_buffer
)
1996 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
1997 enum anv_pipe_bits bits
= cmd_buffer
->state
.pending_pipe_bits
;
1999 if (cmd_buffer
->device
->physical
->always_flush_cache
)
2000 bits
|= ANV_PIPE_FLUSH_BITS
| ANV_PIPE_INVALIDATE_BITS
;
2003 * From Sandybridge PRM, volume 2, "1.7.2 End-of-Pipe Synchronization":
2005 * Write synchronization is a special case of end-of-pipe
2006 * synchronization that requires that the render cache and/or depth
2007 * related caches are flushed to memory, where the data will become
2008 * globally visible. This type of synchronization is required prior to
2009 * SW (CPU) actually reading the result data from memory, or initiating
2010 * an operation that will use as a read surface (such as a texture
2011 * surface) a previous render target and/or depth/stencil buffer
2014 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2016 * Exercising the write cache flush bits (Render Target Cache Flush
2017 * Enable, Depth Cache Flush Enable, DC Flush) in PIPE_CONTROL only
2018 * ensures the write caches are flushed and doesn't guarantee the data
2019 * is globally visible.
2021 * SW can track the completion of the end-of-pipe-synchronization by
2022 * using "Notify Enable" and "PostSync Operation - Write Immediate
2023 * Data" in the PIPE_CONTROL command.
2025 * In other words, flushes are pipelined while invalidations are handled
2026 * immediately. Therefore, if we're flushing anything then we need to
2027 * schedule an end-of-pipe sync before any invalidations can happen.
2029 if (bits
& ANV_PIPE_FLUSH_BITS
)
2030 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2033 /* HSD 1209978178: docs say that before programming the aux table:
2035 * "Driver must ensure that the engine is IDLE but ensure it doesn't
2036 * add extra flushes in the case it knows that the engine is already
2039 if (GEN_GEN
== 12 && ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
)
2040 bits
|= ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2042 /* If we're going to do an invalidate and we have a pending end-of-pipe
2043 * sync that has yet to be resolved, we do the end-of-pipe sync now.
2045 if ((bits
& ANV_PIPE_INVALIDATE_BITS
) &&
2046 (bits
& ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
)) {
2047 bits
|= ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
2048 bits
&= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT
;
2051 if (GEN_GEN
>= 12 &&
2052 ((bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
) ||
2053 (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
))) {
2054 /* From the PIPE_CONTROL instruction table, bit 28 (Tile Cache Flush
2057 * Unified Cache (Tile Cache Disabled):
2059 * When the Color and Depth (Z) streams are enabled to be cached in
2060 * the DC space of L2, Software must use "Render Target Cache Flush
2061 * Enable" and "Depth Cache Flush Enable" along with "Tile Cache
2062 * Flush" for getting the color and depth (Z) write data to be
2063 * globally observable. In this mode of operation it is not required
2064 * to set "CS Stall" upon setting "Tile Cache Flush" bit.
2066 bits
|= ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2069 /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
2070 * invalidates the instruction cache
2072 if (GEN_GEN
== 12 && (bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
))
2073 bits
|= ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2075 if ((GEN_GEN
>= 8 && GEN_GEN
<= 9) &&
2076 (bits
& ANV_PIPE_CS_STALL_BIT
) &&
2077 (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
)) {
2078 /* If we are doing a VF cache invalidate AND a CS stall (it must be
2079 * both) then we can reset our vertex cache tracking.
2081 memset(cmd_buffer
->state
.gfx
.vb_dirty_ranges
, 0,
2082 sizeof(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
2083 memset(&cmd_buffer
->state
.gfx
.ib_dirty_range
, 0,
2084 sizeof(cmd_buffer
->state
.gfx
.ib_dirty_range
));
2087 /* Project: SKL / Argument: LRI Post Sync Operation [23]
2089 * "PIPECONTROL command with “Command Streamer Stall Enable” must be
2090 * programmed prior to programming a PIPECONTROL command with "LRI
2091 * Post Sync Operation" in GPGPU mode of operation (i.e when
2092 * PIPELINE_SELECT command is set to GPGPU mode of operation)."
2094 * The same text exists a few rows below for Post Sync Op.
2096 * On Gen12 this is GEN:BUG:1607156449.
2098 if (bits
& ANV_PIPE_POST_SYNC_BIT
) {
2099 if ((GEN_GEN
== 9 || (GEN_GEN
== 12 && devinfo
->revision
== 0 /* A0 */)) &&
2100 cmd_buffer
->state
.current_pipeline
== GPGPU
)
2101 bits
|= ANV_PIPE_CS_STALL_BIT
;
2102 bits
&= ~ANV_PIPE_POST_SYNC_BIT
;
2105 if (bits
& (ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2106 ANV_PIPE_END_OF_PIPE_SYNC_BIT
)) {
2107 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2109 pipe
.TileCacheFlushEnable
= bits
& ANV_PIPE_TILE_CACHE_FLUSH_BIT
;
2111 pipe
.DepthCacheFlushEnable
= bits
& ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
2112 pipe
.DCFlushEnable
= bits
& ANV_PIPE_DATA_CACHE_FLUSH_BIT
;
2113 pipe
.RenderTargetCacheFlushEnable
=
2114 bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
2116 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must
2117 * be set with any PIPE_CONTROL with Depth Flush Enable bit set.
2120 pipe
.DepthStallEnable
=
2121 pipe
.DepthCacheFlushEnable
|| (bits
& ANV_PIPE_DEPTH_STALL_BIT
);
2123 pipe
.DepthStallEnable
= bits
& ANV_PIPE_DEPTH_STALL_BIT
;
2126 pipe
.CommandStreamerStallEnable
= bits
& ANV_PIPE_CS_STALL_BIT
;
2127 pipe
.StallAtPixelScoreboard
= bits
& ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
2129 /* From Sandybridge PRM, volume 2, "1.7.3.1 Writing a Value to Memory":
2131 * "The most common action to perform upon reaching a
2132 * synchronization point is to write a value out to memory. An
2133 * immediate value (included with the synchronization command) may
2137 * From Broadwell PRM, volume 7, "End-of-Pipe Synchronization":
2139 * "In case the data flushed out by the render engine is to be
2140 * read back in to the render engine in coherent manner, then the
2141 * render engine has to wait for the fence completion before
2142 * accessing the flushed data. This can be achieved by following
2143 * means on various products: PIPE_CONTROL command with CS Stall
2144 * and the required write caches flushed with Post-Sync-Operation
2145 * as Write Immediate Data.
2148 * - Workload-1 (3D/GPGPU/MEDIA)
2149 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2150 * Immediate Data, Required Write Cache Flush bits set)
2151 * - Workload-2 (Can use the data produce or output by
2154 if (bits
& ANV_PIPE_END_OF_PIPE_SYNC_BIT
) {
2155 pipe
.CommandStreamerStallEnable
= true;
2156 pipe
.PostSyncOperation
= WriteImmediateData
;
2157 pipe
.Address
= (struct anv_address
) {
2158 .bo
= cmd_buffer
->device
->workaround_bo
,
2164 * According to the Broadwell documentation, any PIPE_CONTROL with the
2165 * "Command Streamer Stall" bit set must also have another bit set,
2166 * with five different options:
2168 * - Render Target Cache Flush
2169 * - Depth Cache Flush
2170 * - Stall at Pixel Scoreboard
2171 * - Post-Sync Operation
2175 * I chose "Stall at Pixel Scoreboard" since that's what we use in
2176 * mesa and it seems to work fine. The choice is fairly arbitrary.
2178 if (pipe
.CommandStreamerStallEnable
&&
2179 !pipe
.RenderTargetCacheFlushEnable
&&
2180 !pipe
.DepthCacheFlushEnable
&&
2181 !pipe
.StallAtPixelScoreboard
&&
2182 !pipe
.PostSyncOperation
&&
2183 !pipe
.DepthStallEnable
&&
2184 !pipe
.DCFlushEnable
)
2185 pipe
.StallAtPixelScoreboard
= true;
2188 /* If a render target flush was emitted, then we can toggle off the bit
2189 * saying that render target writes are ongoing.
2191 if (bits
& ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
)
2192 bits
&= ~(ANV_PIPE_RENDER_TARGET_BUFFER_WRITES
);
2194 if (GEN_IS_HASWELL
) {
2195 /* Haswell needs addition work-arounds:
2197 * From Haswell PRM, volume 2, part 1, "End-of-Pipe Synchronization":
2200 * PIPE_CONTROL command with the CS Stall and the required write
2201 * caches flushed with Post-SyncOperation as Write Immediate Data
2202 * followed by eight dummy MI_STORE_DATA_IMM (write to scratch
2207 * - PIPE_CONTROL (CS Stall, Post-Sync-Operation Write
2208 * Immediate Data, Required Write Cache Flush bits set)
2209 * - MI_STORE_DATA_IMM (8 times) (Dummy data, Scratch Address)
2210 * - Workload-2 (Can use the data produce or output by
2213 * Unfortunately, both the PRMs and the internal docs are a bit
2214 * out-of-date in this regard. What the windows driver does (and
2215 * this appears to actually work) is to emit a register read from the
2216 * memory address written by the pipe control above.
2218 * What register we load into doesn't matter. We choose an indirect
2219 * rendering register because we know it always exists and it's one
2220 * of the first registers the command parser allows us to write. If
2221 * you don't have command parser support in your kernel (pre-4.2),
2222 * this will get turned into MI_NOOP and you won't get the
2223 * workaround. Unfortunately, there's just not much we can do in
2224 * that case. This register is perfectly safe to write since we
2225 * always re-load all of the indirect draw registers right before
2226 * 3DPRIMITIVE when needed anyway.
2228 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
2229 lrm
.RegisterAddress
= 0x243C; /* GEN7_3DPRIM_START_INSTANCE */
2230 lrm
.MemoryAddress
= (struct anv_address
) {
2231 .bo
= cmd_buffer
->device
->workaround_bo
,
2237 bits
&= ~(ANV_PIPE_FLUSH_BITS
| ANV_PIPE_CS_STALL_BIT
|
2238 ANV_PIPE_END_OF_PIPE_SYNC_BIT
);
2241 if (bits
& ANV_PIPE_INVALIDATE_BITS
) {
2242 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2244 * "If the VF Cache Invalidation Enable is set to a 1 in a
2245 * PIPE_CONTROL, a separate Null PIPE_CONTROL, all bitfields sets to
2246 * 0, with the VF Cache Invalidation Enable set to 0 needs to be sent
2247 * prior to the PIPE_CONTROL with VF Cache Invalidation Enable set to
2250 * This appears to hang Broadwell, so we restrict it to just gen9.
2252 if (GEN_GEN
== 9 && (bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
))
2253 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
);
2255 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
2256 pipe
.StateCacheInvalidationEnable
=
2257 bits
& ANV_PIPE_STATE_CACHE_INVALIDATE_BIT
;
2258 pipe
.ConstantCacheInvalidationEnable
=
2259 bits
& ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT
;
2260 pipe
.VFCacheInvalidationEnable
=
2261 bits
& ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
2262 pipe
.TextureCacheInvalidationEnable
=
2263 bits
& ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
;
2264 pipe
.InstructionCacheInvalidateEnable
=
2265 bits
& ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT
;
2267 /* From the SKL PRM, Vol. 2a, "PIPE_CONTROL",
2269 * "When VF Cache Invalidate is set “Post Sync Operation” must be
2270 * enabled to “Write Immediate Data” or “Write PS Depth Count” or
2271 * “Write Timestamp”.
2273 if (GEN_GEN
== 9 && pipe
.VFCacheInvalidationEnable
) {
2274 pipe
.PostSyncOperation
= WriteImmediateData
;
2276 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
2281 if ((bits
& ANV_PIPE_AUX_TABLE_INVALIDATE_BIT
) &&
2282 cmd_buffer
->device
->info
.has_aux_map
) {
2283 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
2284 lri
.RegisterOffset
= GENX(GFX_CCS_AUX_INV_num
);
2290 bits
&= ~ANV_PIPE_INVALIDATE_BITS
;
2293 cmd_buffer
->state
.pending_pipe_bits
= bits
;
2296 void genX(CmdPipelineBarrier
)(
2297 VkCommandBuffer commandBuffer
,
2298 VkPipelineStageFlags srcStageMask
,
2299 VkPipelineStageFlags destStageMask
,
2301 uint32_t memoryBarrierCount
,
2302 const VkMemoryBarrier
* pMemoryBarriers
,
2303 uint32_t bufferMemoryBarrierCount
,
2304 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
2305 uint32_t imageMemoryBarrierCount
,
2306 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
2308 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
2310 /* XXX: Right now, we're really dumb and just flush whatever categories
2311 * the app asks for. One of these days we may make this a bit better
2312 * but right now that's all the hardware allows for in most areas.
2314 VkAccessFlags src_flags
= 0;
2315 VkAccessFlags dst_flags
= 0;
2317 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
2318 src_flags
|= pMemoryBarriers
[i
].srcAccessMask
;
2319 dst_flags
|= pMemoryBarriers
[i
].dstAccessMask
;
2322 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
2323 src_flags
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
2324 dst_flags
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
2327 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
2328 src_flags
|= pImageMemoryBarriers
[i
].srcAccessMask
;
2329 dst_flags
|= pImageMemoryBarriers
[i
].dstAccessMask
;
2330 ANV_FROM_HANDLE(anv_image
, image
, pImageMemoryBarriers
[i
].image
);
2331 const VkImageSubresourceRange
*range
=
2332 &pImageMemoryBarriers
[i
].subresourceRange
;
2334 uint32_t base_layer
, layer_count
;
2335 if (image
->type
== VK_IMAGE_TYPE_3D
) {
2337 layer_count
= anv_minify(image
->extent
.depth
, range
->baseMipLevel
);
2339 base_layer
= range
->baseArrayLayer
;
2340 layer_count
= anv_get_layerCount(image
, range
);
2343 if (range
->aspectMask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
2344 transition_depth_buffer(cmd_buffer
, image
,
2345 pImageMemoryBarriers
[i
].oldLayout
,
2346 pImageMemoryBarriers
[i
].newLayout
);
2349 if (range
->aspectMask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
2350 transition_stencil_buffer(cmd_buffer
, image
,
2351 range
->baseMipLevel
,
2352 anv_get_levelCount(image
, range
),
2353 base_layer
, layer_count
,
2354 pImageMemoryBarriers
[i
].oldLayout
,
2355 pImageMemoryBarriers
[i
].newLayout
);
2358 if (range
->aspectMask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
2359 VkImageAspectFlags color_aspects
=
2360 anv_image_expand_aspects(image
, range
->aspectMask
);
2361 uint32_t aspect_bit
;
2362 anv_foreach_image_aspect_bit(aspect_bit
, image
, color_aspects
) {
2363 transition_color_buffer(cmd_buffer
, image
, 1UL << aspect_bit
,
2364 range
->baseMipLevel
,
2365 anv_get_levelCount(image
, range
),
2366 base_layer
, layer_count
,
2367 pImageMemoryBarriers
[i
].oldLayout
,
2368 pImageMemoryBarriers
[i
].newLayout
);
2373 cmd_buffer
->state
.pending_pipe_bits
|=
2374 anv_pipe_flush_bits_for_access_flags(src_flags
) |
2375 anv_pipe_invalidate_bits_for_access_flags(dst_flags
);
2379 cmd_buffer_alloc_push_constants(struct anv_cmd_buffer
*cmd_buffer
)
2381 VkShaderStageFlags stages
=
2382 cmd_buffer
->state
.gfx
.base
.pipeline
->active_stages
;
2384 /* In order to avoid thrash, we assume that vertex and fragment stages
2385 * always exist. In the rare case where one is missing *and* the other
2386 * uses push concstants, this may be suboptimal. However, avoiding stalls
2387 * seems more important.
2389 stages
|= VK_SHADER_STAGE_FRAGMENT_BIT
| VK_SHADER_STAGE_VERTEX_BIT
;
2391 if (stages
== cmd_buffer
->state
.push_constant_stages
)
2395 const unsigned push_constant_kb
= 32;
2396 #elif GEN_IS_HASWELL
2397 const unsigned push_constant_kb
= cmd_buffer
->device
->info
.gt
== 3 ? 32 : 16;
2399 const unsigned push_constant_kb
= 16;
2402 const unsigned num_stages
=
2403 util_bitcount(stages
& VK_SHADER_STAGE_ALL_GRAPHICS
);
2404 unsigned size_per_stage
= push_constant_kb
/ num_stages
;
2406 /* Broadwell+ and Haswell gt3 require that the push constant sizes be in
2407 * units of 2KB. Incidentally, these are the same platforms that have
2408 * 32KB worth of push constant space.
2410 if (push_constant_kb
== 32)
2411 size_per_stage
&= ~1u;
2413 uint32_t kb_used
= 0;
2414 for (int i
= MESA_SHADER_VERTEX
; i
< MESA_SHADER_FRAGMENT
; i
++) {
2415 unsigned push_size
= (stages
& (1 << i
)) ? size_per_stage
: 0;
2416 anv_batch_emit(&cmd_buffer
->batch
,
2417 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_VS
), alloc
) {
2418 alloc
._3DCommandSubOpcode
= 18 + i
;
2419 alloc
.ConstantBufferOffset
= (push_size
> 0) ? kb_used
: 0;
2420 alloc
.ConstantBufferSize
= push_size
;
2422 kb_used
+= push_size
;
2425 anv_batch_emit(&cmd_buffer
->batch
,
2426 GENX(3DSTATE_PUSH_CONSTANT_ALLOC_PS
), alloc
) {
2427 alloc
.ConstantBufferOffset
= kb_used
;
2428 alloc
.ConstantBufferSize
= push_constant_kb
- kb_used
;
2431 cmd_buffer
->state
.push_constant_stages
= stages
;
2433 /* From the BDW PRM for 3DSTATE_PUSH_CONSTANT_ALLOC_VS:
2435 * "The 3DSTATE_CONSTANT_VS must be reprogrammed prior to
2436 * the next 3DPRIMITIVE command after programming the
2437 * 3DSTATE_PUSH_CONSTANT_ALLOC_VS"
2439 * Since 3DSTATE_PUSH_CONSTANT_ALLOC_VS is programmed as part of
2440 * pipeline setup, we need to dirty push constants.
2442 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_ALL_GRAPHICS
;
2445 static struct anv_address
2446 anv_descriptor_set_address(struct anv_cmd_buffer
*cmd_buffer
,
2447 struct anv_descriptor_set
*set
)
2450 /* This is a normal descriptor set */
2451 return (struct anv_address
) {
2452 .bo
= set
->pool
->bo
,
2453 .offset
= set
->desc_mem
.offset
,
2456 /* This is a push descriptor set. We have to flag it as used on the GPU
2457 * so that the next time we push descriptors, we grab a new memory.
2459 struct anv_push_descriptor_set
*push_set
=
2460 (struct anv_push_descriptor_set
*)set
;
2461 push_set
->set_used_on_gpu
= true;
2463 return (struct anv_address
) {
2464 .bo
= cmd_buffer
->dynamic_state_stream
.state_pool
->block_pool
.bo
,
2465 .offset
= set
->desc_mem
.offset
,
2470 static struct anv_cmd_pipeline_state
*
2471 pipe_state_for_stage(struct anv_cmd_buffer
*cmd_buffer
,
2472 gl_shader_stage stage
)
2475 case MESA_SHADER_COMPUTE
:
2476 return &cmd_buffer
->state
.compute
.base
;
2478 case MESA_SHADER_VERTEX
:
2479 case MESA_SHADER_TESS_CTRL
:
2480 case MESA_SHADER_TESS_EVAL
:
2481 case MESA_SHADER_GEOMETRY
:
2482 case MESA_SHADER_FRAGMENT
:
2483 return &cmd_buffer
->state
.gfx
.base
;
2486 unreachable("invalid stage");
2491 emit_binding_table(struct anv_cmd_buffer
*cmd_buffer
,
2492 gl_shader_stage stage
,
2493 struct anv_state
*bt_state
)
2495 struct anv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
2496 uint32_t state_offset
;
2498 struct anv_cmd_pipeline_state
*pipe_state
=
2499 pipe_state_for_stage(cmd_buffer
, stage
);
2500 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2502 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2503 *bt_state
= (struct anv_state
) { 0, };
2507 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2508 if (map
->surface_count
== 0) {
2509 *bt_state
= (struct anv_state
) { 0, };
2513 *bt_state
= anv_cmd_buffer_alloc_binding_table(cmd_buffer
,
2516 uint32_t *bt_map
= bt_state
->map
;
2518 if (bt_state
->map
== NULL
)
2519 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2521 /* We only need to emit relocs if we're not using softpin. If we are using
2522 * softpin then we always keep all user-allocated memory objects resident.
2524 const bool need_client_mem_relocs
=
2525 !cmd_buffer
->device
->physical
->use_softpin
;
2527 for (uint32_t s
= 0; s
< map
->surface_count
; s
++) {
2528 struct anv_pipeline_binding
*binding
= &map
->surface_to_descriptor
[s
];
2530 struct anv_state surface_state
;
2532 switch (binding
->set
) {
2533 case ANV_DESCRIPTOR_SET_NULL
:
2537 case ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS
:
2538 /* Color attachment binding */
2539 assert(stage
== MESA_SHADER_FRAGMENT
);
2540 if (binding
->index
< subpass
->color_count
) {
2541 const unsigned att
=
2542 subpass
->color_attachments
[binding
->index
].attachment
;
2544 /* From the Vulkan 1.0.46 spec:
2546 * "If any color or depth/stencil attachments are
2547 * VK_ATTACHMENT_UNUSED, then no writes occur for those
2550 if (att
== VK_ATTACHMENT_UNUSED
) {
2551 surface_state
= cmd_buffer
->state
.null_surface_state
;
2553 surface_state
= cmd_buffer
->state
.attachments
[att
].color
.state
;
2556 surface_state
= cmd_buffer
->state
.null_surface_state
;
2559 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2562 case ANV_DESCRIPTOR_SET_SHADER_CONSTANTS
: {
2563 struct anv_state surface_state
=
2564 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2566 struct anv_address constant_data
= {
2567 .bo
= pipeline
->device
->dynamic_state_pool
.block_pool
.bo
,
2568 .offset
= pipeline
->shaders
[stage
]->constant_data
.offset
,
2570 unsigned constant_data_size
=
2571 pipeline
->shaders
[stage
]->constant_data_size
;
2573 const enum isl_format format
=
2574 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
);
2575 anv_fill_buffer_surface_state(cmd_buffer
->device
,
2576 surface_state
, format
,
2577 constant_data
, constant_data_size
, 1);
2579 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2580 add_surface_reloc(cmd_buffer
, surface_state
, constant_data
);
2584 case ANV_DESCRIPTOR_SET_NUM_WORK_GROUPS
: {
2585 /* This is always the first binding for compute shaders */
2586 assert(stage
== MESA_SHADER_COMPUTE
&& s
== 0);
2588 struct anv_state surface_state
=
2589 anv_cmd_buffer_alloc_surface_state(cmd_buffer
);
2591 const enum isl_format format
=
2592 anv_isl_format_for_descriptor_type(VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
);
2593 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2595 cmd_buffer
->state
.compute
.num_workgroups
,
2597 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2598 if (need_client_mem_relocs
) {
2599 add_surface_reloc(cmd_buffer
, surface_state
,
2600 cmd_buffer
->state
.compute
.num_workgroups
);
2605 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2606 /* This is a descriptor set buffer so the set index is actually
2607 * given by binding->binding. (Yes, that's confusing.)
2609 struct anv_descriptor_set
*set
=
2610 pipe_state
->descriptors
[binding
->index
];
2611 assert(set
->desc_mem
.alloc_size
);
2612 assert(set
->desc_surface_state
.alloc_size
);
2613 bt_map
[s
] = set
->desc_surface_state
.offset
+ state_offset
;
2614 add_surface_reloc(cmd_buffer
, set
->desc_surface_state
,
2615 anv_descriptor_set_address(cmd_buffer
, set
));
2620 assert(binding
->set
< MAX_SETS
);
2621 const struct anv_descriptor
*desc
=
2622 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2624 switch (desc
->type
) {
2625 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2626 /* Nothing for us to do here */
2629 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2630 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
: {
2631 struct anv_surface_state sstate
=
2632 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2633 desc
->image_view
->planes
[binding
->plane
].general_sampler_surface_state
:
2634 desc
->image_view
->planes
[binding
->plane
].optimal_sampler_surface_state
;
2635 surface_state
= sstate
.state
;
2636 assert(surface_state
.alloc_size
);
2637 if (need_client_mem_relocs
)
2638 add_surface_state_relocs(cmd_buffer
, sstate
);
2641 case VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT
:
2642 assert(stage
== MESA_SHADER_FRAGMENT
);
2643 if ((desc
->image_view
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) == 0) {
2644 /* For depth and stencil input attachments, we treat it like any
2645 * old texture that a user may have bound.
2647 assert(desc
->image_view
->n_planes
== 1);
2648 struct anv_surface_state sstate
=
2649 (desc
->layout
== VK_IMAGE_LAYOUT_GENERAL
) ?
2650 desc
->image_view
->planes
[0].general_sampler_surface_state
:
2651 desc
->image_view
->planes
[0].optimal_sampler_surface_state
;
2652 surface_state
= sstate
.state
;
2653 assert(surface_state
.alloc_size
);
2654 if (need_client_mem_relocs
)
2655 add_surface_state_relocs(cmd_buffer
, sstate
);
2657 /* For color input attachments, we create the surface state at
2658 * vkBeginRenderPass time so that we can include aux and clear
2659 * color information.
2661 assert(binding
->input_attachment_index
< subpass
->input_count
);
2662 const unsigned subpass_att
= binding
->input_attachment_index
;
2663 const unsigned att
= subpass
->input_attachments
[subpass_att
].attachment
;
2664 surface_state
= cmd_buffer
->state
.attachments
[att
].input
.state
;
2668 case VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
: {
2669 struct anv_surface_state sstate
= (binding
->write_only
)
2670 ? desc
->image_view
->planes
[binding
->plane
].writeonly_storage_surface_state
2671 : desc
->image_view
->planes
[binding
->plane
].storage_surface_state
;
2672 surface_state
= sstate
.state
;
2673 assert(surface_state
.alloc_size
);
2674 if (need_client_mem_relocs
)
2675 add_surface_state_relocs(cmd_buffer
, sstate
);
2679 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2680 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2681 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2682 surface_state
= desc
->buffer_view
->surface_state
;
2683 assert(surface_state
.alloc_size
);
2684 if (need_client_mem_relocs
) {
2685 add_surface_reloc(cmd_buffer
, surface_state
,
2686 desc
->buffer_view
->address
);
2690 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2691 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
: {
2692 /* Compute the offset within the buffer */
2693 struct anv_push_constants
*push
=
2694 &cmd_buffer
->state
.push_constants
[stage
];
2696 uint32_t dynamic_offset
=
2697 push
->dynamic_offsets
[binding
->dynamic_offset_index
];
2698 uint64_t offset
= desc
->offset
+ dynamic_offset
;
2699 /* Clamp to the buffer size */
2700 offset
= MIN2(offset
, desc
->buffer
->size
);
2701 /* Clamp the range to the buffer size */
2702 uint32_t range
= MIN2(desc
->range
, desc
->buffer
->size
- offset
);
2704 struct anv_address address
=
2705 anv_address_add(desc
->buffer
->address
, offset
);
2708 anv_state_stream_alloc(&cmd_buffer
->surface_state_stream
, 64, 64);
2709 enum isl_format format
=
2710 anv_isl_format_for_descriptor_type(desc
->type
);
2712 anv_fill_buffer_surface_state(cmd_buffer
->device
, surface_state
,
2713 format
, address
, range
, 1);
2714 if (need_client_mem_relocs
)
2715 add_surface_reloc(cmd_buffer
, surface_state
, address
);
2719 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2720 surface_state
= (binding
->write_only
)
2721 ? desc
->buffer_view
->writeonly_storage_surface_state
2722 : desc
->buffer_view
->storage_surface_state
;
2723 assert(surface_state
.alloc_size
);
2724 if (need_client_mem_relocs
) {
2725 add_surface_reloc(cmd_buffer
, surface_state
,
2726 desc
->buffer_view
->address
);
2731 assert(!"Invalid descriptor type");
2734 bt_map
[s
] = surface_state
.offset
+ state_offset
;
2744 emit_samplers(struct anv_cmd_buffer
*cmd_buffer
,
2745 gl_shader_stage stage
,
2746 struct anv_state
*state
)
2748 struct anv_cmd_pipeline_state
*pipe_state
=
2749 pipe_state_for_stage(cmd_buffer
, stage
);
2750 struct anv_pipeline
*pipeline
= pipe_state
->pipeline
;
2752 if (!anv_pipeline_has_stage(pipeline
, stage
)) {
2753 *state
= (struct anv_state
) { 0, };
2757 struct anv_pipeline_bind_map
*map
= &pipeline
->shaders
[stage
]->bind_map
;
2758 if (map
->sampler_count
== 0) {
2759 *state
= (struct anv_state
) { 0, };
2763 uint32_t size
= map
->sampler_count
* 16;
2764 *state
= anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, size
, 32);
2766 if (state
->map
== NULL
)
2767 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2769 for (uint32_t s
= 0; s
< map
->sampler_count
; s
++) {
2770 struct anv_pipeline_binding
*binding
= &map
->sampler_to_descriptor
[s
];
2771 const struct anv_descriptor
*desc
=
2772 &pipe_state
->descriptors
[binding
->set
]->descriptors
[binding
->index
];
2774 if (desc
->type
!= VK_DESCRIPTOR_TYPE_SAMPLER
&&
2775 desc
->type
!= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
)
2778 struct anv_sampler
*sampler
= desc
->sampler
;
2780 /* This can happen if we have an unfilled slot since TYPE_SAMPLER
2781 * happens to be zero.
2783 if (sampler
== NULL
)
2786 memcpy(state
->map
+ (s
* 16),
2787 sampler
->state
[binding
->plane
], sizeof(sampler
->state
[0]));
2794 flush_descriptor_sets(struct anv_cmd_buffer
*cmd_buffer
,
2795 struct anv_pipeline
*pipeline
)
2797 VkShaderStageFlags dirty
= cmd_buffer
->state
.descriptors_dirty
&
2798 pipeline
->active_stages
;
2800 VkResult result
= VK_SUCCESS
;
2801 anv_foreach_stage(s
, dirty
) {
2802 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2803 if (result
!= VK_SUCCESS
)
2805 result
= emit_binding_table(cmd_buffer
, s
,
2806 &cmd_buffer
->state
.binding_tables
[s
]);
2807 if (result
!= VK_SUCCESS
)
2811 if (result
!= VK_SUCCESS
) {
2812 assert(result
== VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2814 result
= anv_cmd_buffer_new_binding_table_block(cmd_buffer
);
2815 if (result
!= VK_SUCCESS
)
2818 /* Re-emit state base addresses so we get the new surface state base
2819 * address before we start emitting binding tables etc.
2821 genX(cmd_buffer_emit_state_base_address
)(cmd_buffer
);
2823 /* Re-emit all active binding tables */
2824 dirty
|= pipeline
->active_stages
;
2825 anv_foreach_stage(s
, dirty
) {
2826 result
= emit_samplers(cmd_buffer
, s
, &cmd_buffer
->state
.samplers
[s
]);
2827 if (result
!= VK_SUCCESS
) {
2828 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2831 result
= emit_binding_table(cmd_buffer
, s
,
2832 &cmd_buffer
->state
.binding_tables
[s
]);
2833 if (result
!= VK_SUCCESS
) {
2834 anv_batch_set_error(&cmd_buffer
->batch
, result
);
2840 cmd_buffer
->state
.descriptors_dirty
&= ~dirty
;
2846 cmd_buffer_emit_descriptor_pointers(struct anv_cmd_buffer
*cmd_buffer
,
2849 static const uint32_t sampler_state_opcodes
[] = {
2850 [MESA_SHADER_VERTEX
] = 43,
2851 [MESA_SHADER_TESS_CTRL
] = 44, /* HS */
2852 [MESA_SHADER_TESS_EVAL
] = 45, /* DS */
2853 [MESA_SHADER_GEOMETRY
] = 46,
2854 [MESA_SHADER_FRAGMENT
] = 47,
2855 [MESA_SHADER_COMPUTE
] = 0,
2858 static const uint32_t binding_table_opcodes
[] = {
2859 [MESA_SHADER_VERTEX
] = 38,
2860 [MESA_SHADER_TESS_CTRL
] = 39,
2861 [MESA_SHADER_TESS_EVAL
] = 40,
2862 [MESA_SHADER_GEOMETRY
] = 41,
2863 [MESA_SHADER_FRAGMENT
] = 42,
2864 [MESA_SHADER_COMPUTE
] = 0,
2867 anv_foreach_stage(s
, stages
) {
2868 assert(s
< ARRAY_SIZE(binding_table_opcodes
));
2869 assert(binding_table_opcodes
[s
] > 0);
2871 if (cmd_buffer
->state
.samplers
[s
].alloc_size
> 0) {
2872 anv_batch_emit(&cmd_buffer
->batch
,
2873 GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS
), ssp
) {
2874 ssp
._3DCommandSubOpcode
= sampler_state_opcodes
[s
];
2875 ssp
.PointertoVSSamplerState
= cmd_buffer
->state
.samplers
[s
].offset
;
2879 /* Always emit binding table pointers if we're asked to, since on SKL
2880 * this is what flushes push constants. */
2881 anv_batch_emit(&cmd_buffer
->batch
,
2882 GENX(3DSTATE_BINDING_TABLE_POINTERS_VS
), btp
) {
2883 btp
._3DCommandSubOpcode
= binding_table_opcodes
[s
];
2884 btp
.PointertoVSBindingTable
= cmd_buffer
->state
.binding_tables
[s
].offset
;
2889 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2890 static struct anv_address
2891 get_push_range_address(struct anv_cmd_buffer
*cmd_buffer
,
2892 gl_shader_stage stage
,
2893 const struct anv_push_range
*range
)
2895 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2896 switch (range
->set
) {
2897 case ANV_DESCRIPTOR_SET_DESCRIPTORS
: {
2898 /* This is a descriptor set buffer so the set index is
2899 * actually given by binding->binding. (Yes, that's
2902 struct anv_descriptor_set
*set
=
2903 gfx_state
->base
.descriptors
[range
->index
];
2904 return anv_descriptor_set_address(cmd_buffer
, set
);
2908 case ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
: {
2909 struct anv_state state
=
2910 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
2911 return (struct anv_address
) {
2912 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
2913 .offset
= state
.offset
,
2919 assert(range
->set
< MAX_SETS
);
2920 struct anv_descriptor_set
*set
=
2921 gfx_state
->base
.descriptors
[range
->set
];
2922 const struct anv_descriptor
*desc
=
2923 &set
->descriptors
[range
->index
];
2925 if (desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
) {
2926 return desc
->buffer_view
->address
;
2928 assert(desc
->type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
);
2929 struct anv_push_constants
*push
=
2930 &cmd_buffer
->state
.push_constants
[stage
];
2931 uint32_t dynamic_offset
=
2932 push
->dynamic_offsets
[range
->dynamic_offset_index
];
2933 return anv_address_add(desc
->buffer
->address
,
2934 desc
->offset
+ dynamic_offset
);
2942 cmd_buffer_emit_push_constant(struct anv_cmd_buffer
*cmd_buffer
,
2943 gl_shader_stage stage
, unsigned buffer_count
)
2945 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
2946 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
2948 static const uint32_t push_constant_opcodes
[] = {
2949 [MESA_SHADER_VERTEX
] = 21,
2950 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
2951 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
2952 [MESA_SHADER_GEOMETRY
] = 22,
2953 [MESA_SHADER_FRAGMENT
] = 23,
2954 [MESA_SHADER_COMPUTE
] = 0,
2957 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
2958 assert(push_constant_opcodes
[stage
] > 0);
2960 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_VS
), c
) {
2961 c
._3DCommandSubOpcode
= push_constant_opcodes
[stage
];
2963 if (anv_pipeline_has_stage(pipeline
, stage
)) {
2964 const struct anv_pipeline_bind_map
*bind_map
=
2965 &pipeline
->shaders
[stage
]->bind_map
;
2968 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
2971 #if GEN_GEN >= 8 || GEN_IS_HASWELL
2972 /* The Skylake PRM contains the following restriction:
2974 * "The driver must ensure The following case does not occur
2975 * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
2976 * buffer 3 read length equal to zero committed followed by a
2977 * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
2980 * To avoid this, we program the buffers in the highest slots.
2981 * This way, slot 0 is only used if slot 3 is also used.
2983 assert(buffer_count
<= 4);
2984 const unsigned shift
= 4 - buffer_count
;
2985 for (unsigned i
= 0; i
< buffer_count
; i
++) {
2986 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
2988 /* At this point we only have non-empty ranges */
2989 assert(range
->length
> 0);
2991 /* For Ivy Bridge, make sure we only set the first range (actual
2994 assert((GEN_GEN
>= 8 || GEN_IS_HASWELL
) || i
== 0);
2996 const struct anv_address addr
=
2997 get_push_range_address(cmd_buffer
, stage
, range
);
2998 c
.ConstantBody
.ReadLength
[i
+ shift
] = range
->length
;
2999 c
.ConstantBody
.Buffer
[i
+ shift
] =
3000 anv_address_add(addr
, range
->start
* 32);
3003 /* For Ivy Bridge, push constants are relative to dynamic state
3004 * base address and we only ever push actual push constants.
3006 if (bind_map
->push_ranges
[0].length
> 0) {
3007 assert(bind_map
->push_ranges
[0].set
==
3008 ANV_DESCRIPTOR_SET_PUSH_CONSTANTS
);
3009 struct anv_state state
=
3010 anv_cmd_buffer_push_constants(cmd_buffer
, stage
);
3011 c
.ConstantBody
.ReadLength
[0] = bind_map
->push_ranges
[0].length
;
3012 c
.ConstantBody
.Buffer
[0].bo
= NULL
;
3013 c
.ConstantBody
.Buffer
[0].offset
= state
.offset
;
3015 assert(bind_map
->push_ranges
[1].length
== 0);
3016 assert(bind_map
->push_ranges
[2].length
== 0);
3017 assert(bind_map
->push_ranges
[3].length
== 0);
3025 cmd_buffer_emit_push_constant_all(struct anv_cmd_buffer
*cmd_buffer
,
3026 uint32_t shader_mask
, uint32_t count
)
3029 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CONSTANT_ALL
), c
) {
3030 c
.ShaderUpdateEnable
= shader_mask
;
3031 c
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
;
3036 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3037 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
3039 static const uint32_t push_constant_opcodes
[] = {
3040 [MESA_SHADER_VERTEX
] = 21,
3041 [MESA_SHADER_TESS_CTRL
] = 25, /* HS */
3042 [MESA_SHADER_TESS_EVAL
] = 26, /* DS */
3043 [MESA_SHADER_GEOMETRY
] = 22,
3044 [MESA_SHADER_FRAGMENT
] = 23,
3045 [MESA_SHADER_COMPUTE
] = 0,
3048 gl_shader_stage stage
= vk_to_mesa_shader_stage(shader_mask
);
3049 assert(stage
< ARRAY_SIZE(push_constant_opcodes
));
3050 assert(push_constant_opcodes
[stage
] > 0);
3052 const struct anv_pipeline_bind_map
*bind_map
=
3053 &pipeline
->shaders
[stage
]->bind_map
;
3056 const uint32_t buffers
= (1 << count
) - 1;
3057 const uint32_t num_dwords
= 2 + 2 * count
;
3059 dw
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3060 GENX(3DSTATE_CONSTANT_ALL
),
3061 .ShaderUpdateEnable
= shader_mask
,
3062 .PointerBufferMask
= buffers
,
3063 .MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
);
3065 for (int i
= 0; i
< count
; i
++) {
3066 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3067 const struct anv_address addr
=
3068 get_push_range_address(cmd_buffer
, stage
, range
);
3070 GENX(3DSTATE_CONSTANT_ALL_DATA_pack
)(
3071 &cmd_buffer
->batch
, dw
+ 2 + i
* 2,
3072 &(struct GENX(3DSTATE_CONSTANT_ALL_DATA
)) {
3073 .PointerToConstantBuffer
= anv_address_add(addr
, range
->start
* 32),
3074 .ConstantBufferReadLength
= range
->length
,
3081 cmd_buffer_flush_push_constants(struct anv_cmd_buffer
*cmd_buffer
,
3082 VkShaderStageFlags dirty_stages
)
3084 VkShaderStageFlags flushed
= 0;
3085 const struct anv_cmd_graphics_state
*gfx_state
= &cmd_buffer
->state
.gfx
;
3086 const struct anv_pipeline
*pipeline
= gfx_state
->base
.pipeline
;
3089 uint32_t nobuffer_stages
= 0;
3092 anv_foreach_stage(stage
, dirty_stages
) {
3093 unsigned buffer_count
= 0;
3094 flushed
|= mesa_to_vk_shader_stage(stage
);
3095 UNUSED
uint32_t max_push_range
= 0;
3097 if (anv_pipeline_has_stage(pipeline
, stage
)) {
3098 const struct anv_pipeline_bind_map
*bind_map
=
3099 &pipeline
->shaders
[stage
]->bind_map
;
3101 for (unsigned i
= 0; i
< 4; i
++) {
3102 const struct anv_push_range
*range
= &bind_map
->push_ranges
[i
];
3103 if (range
->length
> 0) {
3105 max_push_range
= MAX2(max_push_range
, range
->length
);
3111 /* If this stage doesn't have any push constants, emit it later in a
3112 * single CONSTANT_ALL packet.
3114 if (buffer_count
== 0) {
3115 nobuffer_stages
|= 1 << stage
;
3119 /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
3120 * contains only 5 bits, so we can only use it for buffers smaller than
3123 if (max_push_range
< 32) {
3124 cmd_buffer_emit_push_constant_all(cmd_buffer
, 1 << stage
,
3130 cmd_buffer_emit_push_constant(cmd_buffer
, stage
, buffer_count
);
3134 if (nobuffer_stages
)
3135 cmd_buffer_emit_push_constant_all(cmd_buffer
, nobuffer_stages
, 0);
3138 cmd_buffer
->state
.push_constants_dirty
&= ~flushed
;
3142 genX(cmd_buffer_flush_state
)(struct anv_cmd_buffer
*cmd_buffer
)
3144 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3147 uint32_t vb_emit
= cmd_buffer
->state
.gfx
.vb_dirty
& pipeline
->vb_used
;
3148 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
)
3149 vb_emit
|= pipeline
->vb_used
;
3151 assert((pipeline
->active_stages
& VK_SHADER_STAGE_COMPUTE_BIT
) == 0);
3153 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->l3_config
);
3155 genX(cmd_buffer_emit_hashing_mode
)(cmd_buffer
, UINT_MAX
, UINT_MAX
, 1);
3157 genX(flush_pipeline_select_3d
)(cmd_buffer
);
3160 const uint32_t num_buffers
= __builtin_popcount(vb_emit
);
3161 const uint32_t num_dwords
= 1 + num_buffers
* 4;
3163 p
= anv_batch_emitn(&cmd_buffer
->batch
, num_dwords
,
3164 GENX(3DSTATE_VERTEX_BUFFERS
));
3166 for_each_bit(vb
, vb_emit
) {
3167 struct anv_buffer
*buffer
= cmd_buffer
->state
.vertex_bindings
[vb
].buffer
;
3168 uint32_t offset
= cmd_buffer
->state
.vertex_bindings
[vb
].offset
;
3170 struct GENX(VERTEX_BUFFER_STATE
) state
= {
3171 .VertexBufferIndex
= vb
,
3173 .MOCS
= anv_mocs_for_bo(cmd_buffer
->device
, buffer
->address
.bo
),
3175 .BufferAccessType
= pipeline
->vb
[vb
].instanced
? INSTANCEDATA
: VERTEXDATA
,
3176 .InstanceDataStepRate
= pipeline
->vb
[vb
].instance_divisor
,
3179 .AddressModifyEnable
= true,
3180 .BufferPitch
= pipeline
->vb
[vb
].stride
,
3181 .BufferStartingAddress
= anv_address_add(buffer
->address
, offset
),
3184 .BufferSize
= buffer
->size
- offset
3186 .EndAddress
= anv_address_add(buffer
->address
, buffer
->size
- 1),
3190 #if GEN_GEN >= 8 && GEN_GEN <= 9
3191 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
, vb
,
3192 state
.BufferStartingAddress
,
3196 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, &p
[1 + i
* 4], &state
);
3201 cmd_buffer
->state
.gfx
.vb_dirty
&= ~vb_emit
;
3204 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_XFB_ENABLE
) {
3205 /* We don't need any per-buffer dirty tracking because you're not
3206 * allowed to bind different XFB buffers while XFB is enabled.
3208 for (unsigned idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3209 struct anv_xfb_binding
*xfb
= &cmd_buffer
->state
.xfb_bindings
[idx
];
3210 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_SO_BUFFER
), sob
) {
3212 sob
.SOBufferIndex
= idx
;
3214 sob
._3DCommandOpcode
= 0;
3215 sob
._3DCommandSubOpcode
= SO_BUFFER_INDEX_0_CMD
+ idx
;
3218 if (cmd_buffer
->state
.xfb_enabled
&& xfb
->buffer
&& xfb
->size
!= 0) {
3219 sob
.SOBufferEnable
= true;
3220 sob
.MOCS
= cmd_buffer
->device
->isl_dev
.mocs
.internal
,
3221 sob
.StreamOffsetWriteEnable
= false;
3222 sob
.SurfaceBaseAddress
= anv_address_add(xfb
->buffer
->address
,
3224 /* Size is in DWords - 1 */
3225 sob
.SurfaceSize
= xfb
->size
/ 4 - 1;
3230 /* CNL and later require a CS stall after 3DSTATE_SO_BUFFER */
3232 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3236 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_PIPELINE
) {
3237 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
3239 /* If the pipeline changed, we may need to re-allocate push constant
3242 cmd_buffer_alloc_push_constants(cmd_buffer
);
3246 if (cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_VERTEX_BIT
||
3247 cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_VERTEX_BIT
) {
3248 /* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
3250 * "A PIPE_CONTROL with Post-Sync Operation set to 1h and a depth
3251 * stall needs to be sent just prior to any 3DSTATE_VS,
3252 * 3DSTATE_URB_VS, 3DSTATE_CONSTANT_VS,
3253 * 3DSTATE_BINDING_TABLE_POINTER_VS,
3254 * 3DSTATE_SAMPLER_STATE_POINTER_VS command. Only one
3255 * PIPE_CONTROL needs to be sent before any combination of VS
3256 * associated 3DSTATE."
3258 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
3259 pc
.DepthStallEnable
= true;
3260 pc
.PostSyncOperation
= WriteImmediateData
;
3262 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
3267 /* Render targets live in the same binding table as fragment descriptors */
3268 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_RENDER_TARGETS
)
3269 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_FRAGMENT_BIT
;
3271 /* We emit the binding tables and sampler tables first, then emit push
3272 * constants and then finally emit binding table and sampler table
3273 * pointers. It has to happen in this order, since emitting the binding
3274 * tables may change the push constants (in case of storage images). After
3275 * emitting push constants, on SKL+ we have to emit the corresponding
3276 * 3DSTATE_BINDING_TABLE_POINTER_* for the push constants to take effect.
3279 if (cmd_buffer
->state
.descriptors_dirty
)
3280 dirty
= flush_descriptor_sets(cmd_buffer
, pipeline
);
3282 if (dirty
|| cmd_buffer
->state
.push_constants_dirty
) {
3283 /* Because we're pushing UBOs, we have to push whenever either
3284 * descriptors or push constants is dirty.
3286 dirty
|= cmd_buffer
->state
.push_constants_dirty
;
3287 dirty
&= ANV_STAGE_MASK
& VK_SHADER_STAGE_ALL_GRAPHICS
;
3288 cmd_buffer_flush_push_constants(cmd_buffer
, dirty
);
3292 cmd_buffer_emit_descriptor_pointers(cmd_buffer
, dirty
);
3294 if (cmd_buffer
->state
.gfx
.dirty
& ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
)
3295 gen8_cmd_buffer_emit_viewport(cmd_buffer
);
3297 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_VIEWPORT
|
3298 ANV_CMD_DIRTY_PIPELINE
)) {
3299 gen8_cmd_buffer_emit_depth_viewport(cmd_buffer
,
3300 pipeline
->depth_clamp_enable
);
3303 if (cmd_buffer
->state
.gfx
.dirty
& (ANV_CMD_DIRTY_DYNAMIC_SCISSOR
|
3304 ANV_CMD_DIRTY_RENDER_TARGETS
))
3305 gen7_cmd_buffer_emit_scissor(cmd_buffer
);
3307 genX(cmd_buffer_flush_dynamic_state
)(cmd_buffer
);
3311 emit_vertex_bo(struct anv_cmd_buffer
*cmd_buffer
,
3312 struct anv_address addr
,
3313 uint32_t size
, uint32_t index
)
3315 uint32_t *p
= anv_batch_emitn(&cmd_buffer
->batch
, 5,
3316 GENX(3DSTATE_VERTEX_BUFFERS
));
3318 GENX(VERTEX_BUFFER_STATE_pack
)(&cmd_buffer
->batch
, p
+ 1,
3319 &(struct GENX(VERTEX_BUFFER_STATE
)) {
3320 .VertexBufferIndex
= index
,
3321 .AddressModifyEnable
= true,
3323 .MOCS
= addr
.bo
? anv_mocs_for_bo(cmd_buffer
->device
, addr
.bo
) : 0,
3324 .NullVertexBuffer
= size
== 0,
3326 .BufferStartingAddress
= addr
,
3329 .BufferStartingAddress
= addr
,
3330 .EndAddress
= anv_address_add(addr
, size
),
3334 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(cmd_buffer
,
3339 emit_base_vertex_instance_bo(struct anv_cmd_buffer
*cmd_buffer
,
3340 struct anv_address addr
)
3342 emit_vertex_bo(cmd_buffer
, addr
, addr
.bo
? 8 : 0, ANV_SVGS_VB_INDEX
);
3346 emit_base_vertex_instance(struct anv_cmd_buffer
*cmd_buffer
,
3347 uint32_t base_vertex
, uint32_t base_instance
)
3349 if (base_vertex
== 0 && base_instance
== 0) {
3350 emit_base_vertex_instance_bo(cmd_buffer
, ANV_NULL_ADDRESS
);
3352 struct anv_state id_state
=
3353 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 8, 4);
3355 ((uint32_t *)id_state
.map
)[0] = base_vertex
;
3356 ((uint32_t *)id_state
.map
)[1] = base_instance
;
3358 struct anv_address addr
= {
3359 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3360 .offset
= id_state
.offset
,
3363 emit_base_vertex_instance_bo(cmd_buffer
, addr
);
3368 emit_draw_index(struct anv_cmd_buffer
*cmd_buffer
, uint32_t draw_index
)
3370 struct anv_state state
=
3371 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 4, 4);
3373 ((uint32_t *)state
.map
)[0] = draw_index
;
3375 struct anv_address addr
= {
3376 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
3377 .offset
= state
.offset
,
3380 emit_vertex_bo(cmd_buffer
, addr
, 4, ANV_DRAWID_VB_INDEX
);
3384 update_dirty_vbs_for_gen8_vb_flush(struct anv_cmd_buffer
*cmd_buffer
,
3385 uint32_t access_type
)
3387 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3388 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3390 uint64_t vb_used
= pipeline
->vb_used
;
3391 if (vs_prog_data
->uses_firstvertex
||
3392 vs_prog_data
->uses_baseinstance
)
3393 vb_used
|= 1ull << ANV_SVGS_VB_INDEX
;
3394 if (vs_prog_data
->uses_drawid
)
3395 vb_used
|= 1ull << ANV_DRAWID_VB_INDEX
;
3397 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(cmd_buffer
,
3398 access_type
== RANDOM
,
3403 VkCommandBuffer commandBuffer
,
3404 uint32_t vertexCount
,
3405 uint32_t instanceCount
,
3406 uint32_t firstVertex
,
3407 uint32_t firstInstance
)
3409 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3410 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3411 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3413 if (anv_batch_has_error(&cmd_buffer
->batch
))
3416 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3418 if (cmd_buffer
->state
.conditional_render_enabled
)
3419 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3421 if (vs_prog_data
->uses_firstvertex
||
3422 vs_prog_data
->uses_baseinstance
)
3423 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3424 if (vs_prog_data
->uses_drawid
)
3425 emit_draw_index(cmd_buffer
, 0);
3427 /* Emitting draw index or vertex index BOs may result in needing
3428 * additional VF cache flushes.
3430 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3432 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3433 * different views. We need to multiply instanceCount by the view count.
3435 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3437 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3438 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3439 prim
.VertexAccessType
= SEQUENTIAL
;
3440 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3441 prim
.VertexCountPerInstance
= vertexCount
;
3442 prim
.StartVertexLocation
= firstVertex
;
3443 prim
.InstanceCount
= instanceCount
;
3444 prim
.StartInstanceLocation
= firstInstance
;
3445 prim
.BaseVertexLocation
= 0;
3448 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3451 void genX(CmdDrawIndexed
)(
3452 VkCommandBuffer commandBuffer
,
3453 uint32_t indexCount
,
3454 uint32_t instanceCount
,
3455 uint32_t firstIndex
,
3456 int32_t vertexOffset
,
3457 uint32_t firstInstance
)
3459 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3460 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3461 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3463 if (anv_batch_has_error(&cmd_buffer
->batch
))
3466 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3468 if (cmd_buffer
->state
.conditional_render_enabled
)
3469 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3471 if (vs_prog_data
->uses_firstvertex
||
3472 vs_prog_data
->uses_baseinstance
)
3473 emit_base_vertex_instance(cmd_buffer
, vertexOffset
, firstInstance
);
3474 if (vs_prog_data
->uses_drawid
)
3475 emit_draw_index(cmd_buffer
, 0);
3477 /* Emitting draw index or vertex index BOs may result in needing
3478 * additional VF cache flushes.
3480 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3482 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3483 * different views. We need to multiply instanceCount by the view count.
3485 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3487 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3488 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3489 prim
.VertexAccessType
= RANDOM
;
3490 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3491 prim
.VertexCountPerInstance
= indexCount
;
3492 prim
.StartVertexLocation
= firstIndex
;
3493 prim
.InstanceCount
= instanceCount
;
3494 prim
.StartInstanceLocation
= firstInstance
;
3495 prim
.BaseVertexLocation
= vertexOffset
;
3498 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3501 /* Auto-Draw / Indirect Registers */
3502 #define GEN7_3DPRIM_END_OFFSET 0x2420
3503 #define GEN7_3DPRIM_START_VERTEX 0x2430
3504 #define GEN7_3DPRIM_VERTEX_COUNT 0x2434
3505 #define GEN7_3DPRIM_INSTANCE_COUNT 0x2438
3506 #define GEN7_3DPRIM_START_INSTANCE 0x243C
3507 #define GEN7_3DPRIM_BASE_VERTEX 0x2440
3509 void genX(CmdDrawIndirectByteCountEXT
)(
3510 VkCommandBuffer commandBuffer
,
3511 uint32_t instanceCount
,
3512 uint32_t firstInstance
,
3513 VkBuffer counterBuffer
,
3514 VkDeviceSize counterBufferOffset
,
3515 uint32_t counterOffset
,
3516 uint32_t vertexStride
)
3518 #if GEN_IS_HASWELL || GEN_GEN >= 8
3519 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3520 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, counterBuffer
);
3521 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3522 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3524 /* firstVertex is always zero for this draw function */
3525 const uint32_t firstVertex
= 0;
3527 if (anv_batch_has_error(&cmd_buffer
->batch
))
3530 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3532 if (vs_prog_data
->uses_firstvertex
||
3533 vs_prog_data
->uses_baseinstance
)
3534 emit_base_vertex_instance(cmd_buffer
, firstVertex
, firstInstance
);
3535 if (vs_prog_data
->uses_drawid
)
3536 emit_draw_index(cmd_buffer
, 0);
3538 /* Emitting draw index or vertex index BOs may result in needing
3539 * additional VF cache flushes.
3541 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3543 /* Our implementation of VK_KHR_multiview uses instancing to draw the
3544 * different views. We need to multiply instanceCount by the view count.
3546 instanceCount
*= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3548 struct gen_mi_builder b
;
3549 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3550 struct gen_mi_value count
=
3551 gen_mi_mem32(anv_address_add(counter_buffer
->address
,
3552 counterBufferOffset
));
3554 count
= gen_mi_isub(&b
, count
, gen_mi_imm(counterOffset
));
3555 count
= gen_mi_udiv32_imm(&b
, count
, vertexStride
);
3556 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
), count
);
3558 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3559 gen_mi_imm(firstVertex
));
3560 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
),
3561 gen_mi_imm(instanceCount
));
3562 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3563 gen_mi_imm(firstInstance
));
3564 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3566 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3567 prim
.IndirectParameterEnable
= true;
3568 prim
.VertexAccessType
= SEQUENTIAL
;
3569 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3572 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3573 #endif /* GEN_IS_HASWELL || GEN_GEN >= 8 */
3577 load_indirect_parameters(struct anv_cmd_buffer
*cmd_buffer
,
3578 struct anv_address addr
,
3581 struct gen_mi_builder b
;
3582 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3584 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_VERTEX_COUNT
),
3585 gen_mi_mem32(anv_address_add(addr
, 0)));
3587 struct gen_mi_value instance_count
= gen_mi_mem32(anv_address_add(addr
, 4));
3588 unsigned view_count
= anv_subpass_view_count(cmd_buffer
->state
.subpass
);
3589 if (view_count
> 1) {
3590 #if GEN_IS_HASWELL || GEN_GEN >= 8
3591 instance_count
= gen_mi_imul_imm(&b
, instance_count
, view_count
);
3593 anv_finishme("Multiview + indirect draw requires MI_MATH; "
3594 "MI_MATH is not supported on Ivy Bridge");
3597 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_INSTANCE_COUNT
), instance_count
);
3599 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_VERTEX
),
3600 gen_mi_mem32(anv_address_add(addr
, 8)));
3603 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
),
3604 gen_mi_mem32(anv_address_add(addr
, 12)));
3605 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3606 gen_mi_mem32(anv_address_add(addr
, 16)));
3608 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_START_INSTANCE
),
3609 gen_mi_mem32(anv_address_add(addr
, 12)));
3610 gen_mi_store(&b
, gen_mi_reg32(GEN7_3DPRIM_BASE_VERTEX
), gen_mi_imm(0));
3614 void genX(CmdDrawIndirect
)(
3615 VkCommandBuffer commandBuffer
,
3617 VkDeviceSize offset
,
3621 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3622 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3623 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3624 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3626 if (anv_batch_has_error(&cmd_buffer
->batch
))
3629 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3631 if (cmd_buffer
->state
.conditional_render_enabled
)
3632 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3634 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3635 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3637 if (vs_prog_data
->uses_firstvertex
||
3638 vs_prog_data
->uses_baseinstance
)
3639 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3640 if (vs_prog_data
->uses_drawid
)
3641 emit_draw_index(cmd_buffer
, i
);
3643 /* Emitting draw index or vertex index BOs may result in needing
3644 * additional VF cache flushes.
3646 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3648 load_indirect_parameters(cmd_buffer
, draw
, false);
3650 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3651 prim
.IndirectParameterEnable
= true;
3652 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3653 prim
.VertexAccessType
= SEQUENTIAL
;
3654 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3657 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3663 void genX(CmdDrawIndexedIndirect
)(
3664 VkCommandBuffer commandBuffer
,
3666 VkDeviceSize offset
,
3670 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3671 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3672 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.gfx
.base
.pipeline
;
3673 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3675 if (anv_batch_has_error(&cmd_buffer
->batch
))
3678 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3680 if (cmd_buffer
->state
.conditional_render_enabled
)
3681 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
3683 for (uint32_t i
= 0; i
< drawCount
; i
++) {
3684 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3686 /* TODO: We need to stomp base vertex to 0 somehow */
3687 if (vs_prog_data
->uses_firstvertex
||
3688 vs_prog_data
->uses_baseinstance
)
3689 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3690 if (vs_prog_data
->uses_drawid
)
3691 emit_draw_index(cmd_buffer
, i
);
3693 /* Emitting draw index or vertex index BOs may result in needing
3694 * additional VF cache flushes.
3696 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3698 load_indirect_parameters(cmd_buffer
, draw
, true);
3700 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3701 prim
.IndirectParameterEnable
= true;
3702 prim
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
3703 prim
.VertexAccessType
= RANDOM
;
3704 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3707 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3713 #define TMP_DRAW_COUNT_REG 0x2670 /* MI_ALU_REG14 */
3716 prepare_for_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3717 struct anv_address count_address
,
3718 const bool conditional_render_enabled
)
3720 struct gen_mi_builder b
;
3721 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3723 if (conditional_render_enabled
) {
3724 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3725 gen_mi_store(&b
, gen_mi_reg64(TMP_DRAW_COUNT_REG
),
3726 gen_mi_mem32(count_address
));
3729 /* Upload the current draw count from the draw parameters buffer to
3730 * MI_PREDICATE_SRC0.
3732 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
3733 gen_mi_mem32(count_address
));
3735 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
+ 4), gen_mi_imm(0));
3740 emit_draw_count_predicate(struct anv_cmd_buffer
*cmd_buffer
,
3741 uint32_t draw_index
)
3743 struct gen_mi_builder b
;
3744 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3746 /* Upload the index of the current primitive to MI_PREDICATE_SRC1. */
3747 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC1
), gen_mi_imm(draw_index
));
3749 if (draw_index
== 0) {
3750 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3751 mip
.LoadOperation
= LOAD_LOADINV
;
3752 mip
.CombineOperation
= COMBINE_SET
;
3753 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3756 /* While draw_index < draw_count the predicate's result will be
3757 * (draw_index == draw_count) ^ TRUE = TRUE
3758 * When draw_index == draw_count the result is
3759 * (TRUE) ^ TRUE = FALSE
3760 * After this all results will be:
3761 * (FALSE) ^ FALSE = FALSE
3763 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3764 mip
.LoadOperation
= LOAD_LOAD
;
3765 mip
.CombineOperation
= COMBINE_XOR
;
3766 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3771 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3773 emit_draw_count_predicate_with_conditional_render(
3774 struct anv_cmd_buffer
*cmd_buffer
,
3775 uint32_t draw_index
)
3777 struct gen_mi_builder b
;
3778 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
3780 struct gen_mi_value pred
= gen_mi_ult(&b
, gen_mi_imm(draw_index
),
3781 gen_mi_reg64(TMP_DRAW_COUNT_REG
));
3782 pred
= gen_mi_iand(&b
, pred
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
));
3785 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_RESULT
), pred
);
3787 /* MI_PREDICATE_RESULT is not whitelisted in i915 command parser
3788 * so we emit MI_PREDICATE to set it.
3791 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), pred
);
3792 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
3794 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
3795 mip
.LoadOperation
= LOAD_LOADINV
;
3796 mip
.CombineOperation
= COMBINE_SET
;
3797 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
3803 void genX(CmdDrawIndirectCount
)(
3804 VkCommandBuffer commandBuffer
,
3806 VkDeviceSize offset
,
3807 VkBuffer _countBuffer
,
3808 VkDeviceSize countBufferOffset
,
3809 uint32_t maxDrawCount
,
3812 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3813 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3814 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3815 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3816 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3817 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3819 if (anv_batch_has_error(&cmd_buffer
->batch
))
3822 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3824 struct anv_address count_address
=
3825 anv_address_add(count_buffer
->address
, countBufferOffset
);
3827 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3828 cmd_state
->conditional_render_enabled
);
3830 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3831 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3833 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3834 if (cmd_state
->conditional_render_enabled
) {
3835 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3837 emit_draw_count_predicate(cmd_buffer
, i
);
3840 emit_draw_count_predicate(cmd_buffer
, i
);
3843 if (vs_prog_data
->uses_firstvertex
||
3844 vs_prog_data
->uses_baseinstance
)
3845 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 8));
3846 if (vs_prog_data
->uses_drawid
)
3847 emit_draw_index(cmd_buffer
, i
);
3849 /* Emitting draw index or vertex index BOs may result in needing
3850 * additional VF cache flushes.
3852 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3854 load_indirect_parameters(cmd_buffer
, draw
, false);
3856 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3857 prim
.IndirectParameterEnable
= true;
3858 prim
.PredicateEnable
= true;
3859 prim
.VertexAccessType
= SEQUENTIAL
;
3860 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3863 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, SEQUENTIAL
);
3869 void genX(CmdDrawIndexedIndirectCount
)(
3870 VkCommandBuffer commandBuffer
,
3872 VkDeviceSize offset
,
3873 VkBuffer _countBuffer
,
3874 VkDeviceSize countBufferOffset
,
3875 uint32_t maxDrawCount
,
3878 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3879 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
3880 ANV_FROM_HANDLE(anv_buffer
, count_buffer
, _countBuffer
);
3881 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
3882 struct anv_pipeline
*pipeline
= cmd_state
->gfx
.base
.pipeline
;
3883 const struct brw_vs_prog_data
*vs_prog_data
= get_vs_prog_data(pipeline
);
3885 if (anv_batch_has_error(&cmd_buffer
->batch
))
3888 genX(cmd_buffer_flush_state
)(cmd_buffer
);
3890 struct anv_address count_address
=
3891 anv_address_add(count_buffer
->address
, countBufferOffset
);
3893 prepare_for_draw_count_predicate(cmd_buffer
, count_address
,
3894 cmd_state
->conditional_render_enabled
);
3896 for (uint32_t i
= 0; i
< maxDrawCount
; i
++) {
3897 struct anv_address draw
= anv_address_add(buffer
->address
, offset
);
3899 #if GEN_GEN >= 8 || GEN_IS_HASWELL
3900 if (cmd_state
->conditional_render_enabled
) {
3901 emit_draw_count_predicate_with_conditional_render(cmd_buffer
, i
);
3903 emit_draw_count_predicate(cmd_buffer
, i
);
3906 emit_draw_count_predicate(cmd_buffer
, i
);
3909 /* TODO: We need to stomp base vertex to 0 somehow */
3910 if (vs_prog_data
->uses_firstvertex
||
3911 vs_prog_data
->uses_baseinstance
)
3912 emit_base_vertex_instance_bo(cmd_buffer
, anv_address_add(draw
, 12));
3913 if (vs_prog_data
->uses_drawid
)
3914 emit_draw_index(cmd_buffer
, i
);
3916 /* Emitting draw index or vertex index BOs may result in needing
3917 * additional VF cache flushes.
3919 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3921 load_indirect_parameters(cmd_buffer
, draw
, true);
3923 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DPRIMITIVE
), prim
) {
3924 prim
.IndirectParameterEnable
= true;
3925 prim
.PredicateEnable
= true;
3926 prim
.VertexAccessType
= RANDOM
;
3927 prim
.PrimitiveTopologyType
= pipeline
->topology
;
3930 update_dirty_vbs_for_gen8_vb_flush(cmd_buffer
, RANDOM
);
3936 void genX(CmdBeginTransformFeedbackEXT
)(
3937 VkCommandBuffer commandBuffer
,
3938 uint32_t firstCounterBuffer
,
3939 uint32_t counterBufferCount
,
3940 const VkBuffer
* pCounterBuffers
,
3941 const VkDeviceSize
* pCounterBufferOffsets
)
3943 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3945 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3946 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
3947 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
3949 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
3951 * "Ssoftware must ensure that no HW stream output operations can be in
3952 * process or otherwise pending at the point that the MI_LOAD/STORE
3953 * commands are processed. This will likely require a pipeline flush."
3955 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
3956 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
3958 for (uint32_t idx
= 0; idx
< MAX_XFB_BUFFERS
; idx
++) {
3959 /* If we have a counter buffer, this is a resume so we need to load the
3960 * value into the streamout offset register. Otherwise, this is a begin
3961 * and we need to reset it to zero.
3963 if (pCounterBuffers
&&
3964 idx
>= firstCounterBuffer
&&
3965 idx
- firstCounterBuffer
< counterBufferCount
&&
3966 pCounterBuffers
[idx
- firstCounterBuffer
] != VK_NULL_HANDLE
) {
3967 uint32_t cb_idx
= idx
- firstCounterBuffer
;
3968 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
3969 uint64_t offset
= pCounterBufferOffsets
?
3970 pCounterBufferOffsets
[cb_idx
] : 0;
3972 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_MEM
), lrm
) {
3973 lrm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3974 lrm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
3978 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_LOAD_REGISTER_IMM
), lri
) {
3979 lri
.RegisterOffset
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
3985 cmd_buffer
->state
.xfb_enabled
= true;
3986 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
3989 void genX(CmdEndTransformFeedbackEXT
)(
3990 VkCommandBuffer commandBuffer
,
3991 uint32_t firstCounterBuffer
,
3992 uint32_t counterBufferCount
,
3993 const VkBuffer
* pCounterBuffers
,
3994 const VkDeviceSize
* pCounterBufferOffsets
)
3996 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
3998 assert(firstCounterBuffer
< MAX_XFB_BUFFERS
);
3999 assert(counterBufferCount
<= MAX_XFB_BUFFERS
);
4000 assert(firstCounterBuffer
+ counterBufferCount
<= MAX_XFB_BUFFERS
);
4002 /* From the SKL PRM Vol. 2c, SO_WRITE_OFFSET:
4004 * "Ssoftware must ensure that no HW stream output operations can be in
4005 * process or otherwise pending at the point that the MI_LOAD/STORE
4006 * commands are processed. This will likely require a pipeline flush."
4008 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4009 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4011 for (uint32_t cb_idx
= 0; cb_idx
< counterBufferCount
; cb_idx
++) {
4012 unsigned idx
= firstCounterBuffer
+ cb_idx
;
4014 /* If we have a counter buffer, this is a resume so we need to load the
4015 * value into the streamout offset register. Otherwise, this is a begin
4016 * and we need to reset it to zero.
4018 if (pCounterBuffers
&&
4019 cb_idx
< counterBufferCount
&&
4020 pCounterBuffers
[cb_idx
] != VK_NULL_HANDLE
) {
4021 ANV_FROM_HANDLE(anv_buffer
, counter_buffer
, pCounterBuffers
[cb_idx
]);
4022 uint64_t offset
= pCounterBufferOffsets
?
4023 pCounterBufferOffsets
[cb_idx
] : 0;
4025 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_STORE_REGISTER_MEM
), srm
) {
4026 srm
.MemoryAddress
= anv_address_add(counter_buffer
->address
,
4028 srm
.RegisterAddress
= GENX(SO_WRITE_OFFSET0_num
) + idx
* 4;
4033 cmd_buffer
->state
.xfb_enabled
= false;
4034 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_XFB_ENABLE
;
4038 genX(cmd_buffer_flush_compute_state
)(struct anv_cmd_buffer
*cmd_buffer
)
4040 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
4042 assert(pipeline
->active_stages
== VK_SHADER_STAGE_COMPUTE_BIT
);
4044 genX(cmd_buffer_config_l3
)(cmd_buffer
, pipeline
->l3_config
);
4046 genX(flush_pipeline_select_gpgpu
)(cmd_buffer
);
4048 if (cmd_buffer
->state
.compute
.pipeline_dirty
) {
4049 /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
4051 * "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
4052 * the only bits that are changed are scoreboard related: Scoreboard
4053 * Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
4054 * these scoreboard related states, a MEDIA_STATE_FLUSH is
4057 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_CS_STALL_BIT
;
4058 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4060 anv_batch_emit_batch(&cmd_buffer
->batch
, &pipeline
->batch
);
4062 /* The workgroup size of the pipeline affects our push constant layout
4063 * so flag push constants as dirty if we change the pipeline.
4065 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4068 if ((cmd_buffer
->state
.descriptors_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) ||
4069 cmd_buffer
->state
.compute
.pipeline_dirty
) {
4070 flush_descriptor_sets(cmd_buffer
, pipeline
);
4072 uint32_t iface_desc_data_dw
[GENX(INTERFACE_DESCRIPTOR_DATA_length
)];
4073 struct GENX(INTERFACE_DESCRIPTOR_DATA
) desc
= {
4074 .BindingTablePointer
=
4075 cmd_buffer
->state
.binding_tables
[MESA_SHADER_COMPUTE
].offset
,
4076 .SamplerStatePointer
=
4077 cmd_buffer
->state
.samplers
[MESA_SHADER_COMPUTE
].offset
,
4079 GENX(INTERFACE_DESCRIPTOR_DATA_pack
)(NULL
, iface_desc_data_dw
, &desc
);
4081 struct anv_state state
=
4082 anv_cmd_buffer_merge_dynamic(cmd_buffer
, iface_desc_data_dw
,
4083 pipeline
->interface_descriptor_data
,
4084 GENX(INTERFACE_DESCRIPTOR_DATA_length
),
4087 uint32_t size
= GENX(INTERFACE_DESCRIPTOR_DATA_length
) * sizeof(uint32_t);
4088 anv_batch_emit(&cmd_buffer
->batch
,
4089 GENX(MEDIA_INTERFACE_DESCRIPTOR_LOAD
), mid
) {
4090 mid
.InterfaceDescriptorTotalLength
= size
;
4091 mid
.InterfaceDescriptorDataStartAddress
= state
.offset
;
4095 if (cmd_buffer
->state
.push_constants_dirty
& VK_SHADER_STAGE_COMPUTE_BIT
) {
4096 struct anv_state push_state
=
4097 anv_cmd_buffer_cs_push_constants(cmd_buffer
);
4099 if (push_state
.alloc_size
) {
4100 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_CURBE_LOAD
), curbe
) {
4101 curbe
.CURBETotalDataLength
= push_state
.alloc_size
;
4102 curbe
.CURBEDataStartAddress
= push_state
.offset
;
4106 cmd_buffer
->state
.push_constants_dirty
&= ~VK_SHADER_STAGE_COMPUTE_BIT
;
4109 cmd_buffer
->state
.compute
.pipeline_dirty
= false;
4111 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4117 verify_cmd_parser(const struct anv_device
*device
,
4118 int required_version
,
4119 const char *function
)
4121 if (device
->physical
->cmd_parser_version
< required_version
) {
4122 return vk_errorf(device
, device
->physical
,
4123 VK_ERROR_FEATURE_NOT_PRESENT
,
4124 "cmd parser version %d is required for %s",
4125 required_version
, function
);
4134 anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer
*cmd_buffer
,
4135 uint32_t baseGroupX
,
4136 uint32_t baseGroupY
,
4137 uint32_t baseGroupZ
)
4139 if (anv_batch_has_error(&cmd_buffer
->batch
))
4142 struct anv_push_constants
*push
=
4143 &cmd_buffer
->state
.push_constants
[MESA_SHADER_COMPUTE
];
4144 if (push
->cs
.base_work_group_id
[0] != baseGroupX
||
4145 push
->cs
.base_work_group_id
[1] != baseGroupY
||
4146 push
->cs
.base_work_group_id
[2] != baseGroupZ
) {
4147 push
->cs
.base_work_group_id
[0] = baseGroupX
;
4148 push
->cs
.base_work_group_id
[1] = baseGroupY
;
4149 push
->cs
.base_work_group_id
[2] = baseGroupZ
;
4151 cmd_buffer
->state
.push_constants_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4155 void genX(CmdDispatch
)(
4156 VkCommandBuffer commandBuffer
,
4161 genX(CmdDispatchBase
)(commandBuffer
, 0, 0, 0, x
, y
, z
);
4164 void genX(CmdDispatchBase
)(
4165 VkCommandBuffer commandBuffer
,
4166 uint32_t baseGroupX
,
4167 uint32_t baseGroupY
,
4168 uint32_t baseGroupZ
,
4169 uint32_t groupCountX
,
4170 uint32_t groupCountY
,
4171 uint32_t groupCountZ
)
4173 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4174 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
4175 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4177 anv_cmd_buffer_push_base_group_id(cmd_buffer
, baseGroupX
,
4178 baseGroupY
, baseGroupZ
);
4180 if (anv_batch_has_error(&cmd_buffer
->batch
))
4183 if (prog_data
->uses_num_work_groups
) {
4184 struct anv_state state
=
4185 anv_cmd_buffer_alloc_dynamic_state(cmd_buffer
, 12, 4);
4186 uint32_t *sizes
= state
.map
;
4187 sizes
[0] = groupCountX
;
4188 sizes
[1] = groupCountY
;
4189 sizes
[2] = groupCountZ
;
4190 cmd_buffer
->state
.compute
.num_workgroups
= (struct anv_address
) {
4191 .bo
= cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
4192 .offset
= state
.offset
,
4195 /* The num_workgroups buffer goes in the binding table */
4196 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4199 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4201 if (cmd_buffer
->state
.conditional_render_enabled
)
4202 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4204 anv_batch_emit(&cmd_buffer
->batch
, GENX(GPGPU_WALKER
), ggw
) {
4205 ggw
.PredicateEnable
= cmd_buffer
->state
.conditional_render_enabled
;
4206 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4207 ggw
.ThreadDepthCounterMaximum
= 0;
4208 ggw
.ThreadHeightCounterMaximum
= 0;
4209 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
4210 ggw
.ThreadGroupIDXDimension
= groupCountX
;
4211 ggw
.ThreadGroupIDYDimension
= groupCountY
;
4212 ggw
.ThreadGroupIDZDimension
= groupCountZ
;
4213 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4214 ggw
.BottomExecutionMask
= 0xffffffff;
4217 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4220 #define GPGPU_DISPATCHDIMX 0x2500
4221 #define GPGPU_DISPATCHDIMY 0x2504
4222 #define GPGPU_DISPATCHDIMZ 0x2508
4224 void genX(CmdDispatchIndirect
)(
4225 VkCommandBuffer commandBuffer
,
4227 VkDeviceSize offset
)
4229 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
4230 ANV_FROM_HANDLE(anv_buffer
, buffer
, _buffer
);
4231 struct anv_pipeline
*pipeline
= cmd_buffer
->state
.compute
.base
.pipeline
;
4232 const struct brw_cs_prog_data
*prog_data
= get_cs_prog_data(pipeline
);
4233 struct anv_address addr
= anv_address_add(buffer
->address
, offset
);
4234 struct anv_batch
*batch
= &cmd_buffer
->batch
;
4236 anv_cmd_buffer_push_base_group_id(cmd_buffer
, 0, 0, 0);
4239 /* Linux 4.4 added command parser version 5 which allows the GPGPU
4240 * indirect dispatch registers to be written.
4242 if (verify_cmd_parser(cmd_buffer
->device
, 5,
4243 "vkCmdDispatchIndirect") != VK_SUCCESS
)
4247 if (prog_data
->uses_num_work_groups
) {
4248 cmd_buffer
->state
.compute
.num_workgroups
= addr
;
4250 /* The num_workgroups buffer goes in the binding table */
4251 cmd_buffer
->state
.descriptors_dirty
|= VK_SHADER_STAGE_COMPUTE_BIT
;
4254 genX(cmd_buffer_flush_compute_state
)(cmd_buffer
);
4256 struct gen_mi_builder b
;
4257 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
4259 struct gen_mi_value size_x
= gen_mi_mem32(anv_address_add(addr
, 0));
4260 struct gen_mi_value size_y
= gen_mi_mem32(anv_address_add(addr
, 4));
4261 struct gen_mi_value size_z
= gen_mi_mem32(anv_address_add(addr
, 8));
4263 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMX
), size_x
);
4264 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMY
), size_y
);
4265 gen_mi_store(&b
, gen_mi_reg32(GPGPU_DISPATCHDIMZ
), size_z
);
4268 /* predicate = (compute_dispatch_indirect_x_size == 0); */
4269 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
), size_x
);
4270 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
4271 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4272 mip
.LoadOperation
= LOAD_LOAD
;
4273 mip
.CombineOperation
= COMBINE_SET
;
4274 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4277 /* predicate |= (compute_dispatch_indirect_y_size == 0); */
4278 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_y
);
4279 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4280 mip
.LoadOperation
= LOAD_LOAD
;
4281 mip
.CombineOperation
= COMBINE_OR
;
4282 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4285 /* predicate |= (compute_dispatch_indirect_z_size == 0); */
4286 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
), size_z
);
4287 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4288 mip
.LoadOperation
= LOAD_LOAD
;
4289 mip
.CombineOperation
= COMBINE_OR
;
4290 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4293 /* predicate = !predicate; */
4294 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4295 mip
.LoadOperation
= LOAD_LOADINV
;
4296 mip
.CombineOperation
= COMBINE_OR
;
4297 mip
.CompareOperation
= COMPARE_FALSE
;
4301 if (cmd_buffer
->state
.conditional_render_enabled
) {
4302 /* predicate &= !(conditional_rendering_predicate == 0); */
4303 gen_mi_store(&b
, gen_mi_reg32(MI_PREDICATE_SRC0
),
4304 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
4305 anv_batch_emit(batch
, GENX(MI_PREDICATE
), mip
) {
4306 mip
.LoadOperation
= LOAD_LOADINV
;
4307 mip
.CombineOperation
= COMBINE_AND
;
4308 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
4313 #else /* GEN_GEN > 7 */
4314 if (cmd_buffer
->state
.conditional_render_enabled
)
4315 genX(cmd_emit_conditional_render_predicate
)(cmd_buffer
);
4318 anv_batch_emit(batch
, GENX(GPGPU_WALKER
), ggw
) {
4319 ggw
.IndirectParameterEnable
= true;
4320 ggw
.PredicateEnable
= GEN_GEN
<= 7 ||
4321 cmd_buffer
->state
.conditional_render_enabled
;
4322 ggw
.SIMDSize
= prog_data
->simd_size
/ 16;
4323 ggw
.ThreadDepthCounterMaximum
= 0;
4324 ggw
.ThreadHeightCounterMaximum
= 0;
4325 ggw
.ThreadWidthCounterMaximum
= prog_data
->threads
- 1;
4326 ggw
.RightExecutionMask
= pipeline
->cs_right_mask
;
4327 ggw
.BottomExecutionMask
= 0xffffffff;
4330 anv_batch_emit(batch
, GENX(MEDIA_STATE_FLUSH
), msf
);
4334 genX(flush_pipeline_select
)(struct anv_cmd_buffer
*cmd_buffer
,
4337 UNUSED
const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4339 if (cmd_buffer
->state
.current_pipeline
== pipeline
)
4342 #if GEN_GEN >= 8 && GEN_GEN < 10
4343 /* From the Broadwell PRM, Volume 2a: Instructions, PIPELINE_SELECT:
4345 * Software must clear the COLOR_CALC_STATE Valid field in
4346 * 3DSTATE_CC_STATE_POINTERS command prior to send a PIPELINE_SELECT
4347 * with Pipeline Select set to GPGPU.
4349 * The internal hardware docs recommend the same workaround for Gen9
4352 if (pipeline
== GPGPU
)
4353 anv_batch_emit(&cmd_buffer
->batch
, GENX(3DSTATE_CC_STATE_POINTERS
), t
);
4357 if (pipeline
== _3D
) {
4358 /* There is a mid-object preemption workaround which requires you to
4359 * re-emit MEDIA_VFE_STATE after switching from GPGPU to 3D. However,
4360 * even without preemption, we have issues with geometry flickering when
4361 * GPGPU and 3D are back-to-back and this seems to fix it. We don't
4364 const uint32_t subslices
=
4365 MAX2(cmd_buffer
->device
->physical
->subslice_total
, 1);
4366 anv_batch_emit(&cmd_buffer
->batch
, GENX(MEDIA_VFE_STATE
), vfe
) {
4367 vfe
.MaximumNumberofThreads
=
4368 devinfo
->max_cs_threads
* subslices
- 1;
4369 vfe
.NumberofURBEntries
= 2;
4370 vfe
.URBEntryAllocationSize
= 2;
4373 /* We just emitted a dummy MEDIA_VFE_STATE so now that packet is
4374 * invalid. Set the compute pipeline to dirty to force a re-emit of the
4375 * pipeline in case we get back-to-back dispatch calls with the same
4376 * pipeline and a PIPELINE_SELECT in between.
4378 cmd_buffer
->state
.compute
.pipeline_dirty
= true;
4382 /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
4383 * PIPELINE_SELECT [DevBWR+]":
4387 * Software must ensure all the write caches are flushed through a
4388 * stalling PIPE_CONTROL command followed by another PIPE_CONTROL
4389 * command to invalidate read only caches prior to programming
4390 * MI_PIPELINE_SELECT command to change the Pipeline Select Mode.
4392 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4393 pc
.RenderTargetCacheFlushEnable
= true;
4394 pc
.DepthCacheFlushEnable
= true;
4395 pc
.DCFlushEnable
= true;
4396 pc
.PostSyncOperation
= NoWrite
;
4397 pc
.CommandStreamerStallEnable
= true;
4399 pc
.TileCacheFlushEnable
= true;
4401 /* GEN:BUG:1409600907: "PIPE_CONTROL with Depth Stall Enable bit must be
4402 * set with any PIPE_CONTROL with Depth Flush Enable bit set.
4404 pc
.DepthStallEnable
= true;
4408 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4409 pc
.TextureCacheInvalidationEnable
= true;
4410 pc
.ConstantCacheInvalidationEnable
= true;
4411 pc
.StateCacheInvalidationEnable
= true;
4412 pc
.InstructionCacheInvalidateEnable
= true;
4413 pc
.PostSyncOperation
= NoWrite
;
4415 pc
.TileCacheFlushEnable
= true;
4419 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPELINE_SELECT
), ps
) {
4423 ps
.PipelineSelection
= pipeline
;
4427 if (devinfo
->is_geminilake
) {
4430 * "This chicken bit works around a hardware issue with barrier logic
4431 * encountered when switching between GPGPU and 3D pipelines. To
4432 * workaround the issue, this mode bit should be set after a pipeline
4436 anv_pack_struct(&scec
, GENX(SLICE_COMMON_ECO_CHICKEN1
),
4438 pipeline
== GPGPU
? GLK_BARRIER_MODE_GPGPU
4439 : GLK_BARRIER_MODE_3D_HULL
,
4440 .GLKBarrierModeMask
= 1);
4441 emit_lri(&cmd_buffer
->batch
, GENX(SLICE_COMMON_ECO_CHICKEN1_num
), scec
);
4445 cmd_buffer
->state
.current_pipeline
= pipeline
;
4449 genX(flush_pipeline_select_3d
)(struct anv_cmd_buffer
*cmd_buffer
)
4451 genX(flush_pipeline_select
)(cmd_buffer
, _3D
);
4455 genX(flush_pipeline_select_gpgpu
)(struct anv_cmd_buffer
*cmd_buffer
)
4457 genX(flush_pipeline_select
)(cmd_buffer
, GPGPU
);
4461 genX(cmd_buffer_emit_gen7_depth_flush
)(struct anv_cmd_buffer
*cmd_buffer
)
4466 /* From the Haswell PRM, documentation for 3DSTATE_DEPTH_BUFFER:
4468 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e., any
4469 * combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
4470 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
4471 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
4472 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
4473 * Depth Flush Bit set, followed by another pipelined depth stall
4474 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
4475 * guarantee that the pipeline from WM onwards is already flushed (e.g.,
4476 * via a preceding MI_FLUSH)."
4478 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4479 pipe
.DepthStallEnable
= true;
4481 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4482 pipe
.DepthCacheFlushEnable
= true;
4484 pipe
.TileCacheFlushEnable
= true;
4487 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pipe
) {
4488 pipe
.DepthStallEnable
= true;
4492 /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
4494 * "The VF cache needs to be invalidated before binding and then using
4495 * Vertex Buffers that overlap with any previously bound Vertex Buffer
4496 * (at a 64B granularity) since the last invalidation. A VF cache
4497 * invalidate is performed by setting the "VF Cache Invalidation Enable"
4498 * bit in PIPE_CONTROL."
4500 * This is implemented by carefully tracking all vertex and index buffer
4501 * bindings and flushing if the cache ever ends up with a range in the cache
4502 * that would exceed 4 GiB. This is implemented in three parts:
4504 * 1. genX(cmd_buffer_set_binding_for_gen8_vb_flush)() which must be called
4505 * every time a 3DSTATE_VERTEX_BUFFER packet is emitted and informs the
4506 * tracking code of the new binding. If this new binding would cause
4507 * the cache to have a too-large range on the next draw call, a pipeline
4508 * stall and VF cache invalidate are added to pending_pipeline_bits.
4510 * 2. genX(cmd_buffer_apply_pipe_flushes)() resets the cache tracking to
4511 * empty whenever we emit a VF invalidate.
4513 * 3. genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush)() must be called
4514 * after every 3DPRIMITIVE and copies the bound range into the dirty
4515 * range for each used buffer. This has to be a separate step because
4516 * we don't always re-bind all buffers and so 1. can't know which
4517 * buffers are actually bound.
4520 genX(cmd_buffer_set_binding_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4522 struct anv_address vb_address
,
4525 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4526 !cmd_buffer
->device
->physical
->use_softpin
)
4529 struct anv_vb_cache_range
*bound
, *dirty
;
4530 if (vb_index
== -1) {
4531 bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4532 dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4534 assert(vb_index
>= 0);
4535 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4536 assert(vb_index
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4537 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[vb_index
];
4538 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[vb_index
];
4547 assert(vb_address
.bo
&& (vb_address
.bo
->flags
& EXEC_OBJECT_PINNED
));
4548 bound
->start
= gen_48b_address(anv_address_physical(vb_address
));
4549 bound
->end
= bound
->start
+ vb_size
;
4550 assert(bound
->end
> bound
->start
); /* No overflow */
4552 /* Align everything to a cache line */
4553 bound
->start
&= ~(64ull - 1ull);
4554 bound
->end
= align_u64(bound
->end
, 64);
4556 /* Compute the dirty range */
4557 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4558 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4560 /* If our range is larger than 32 bits, we have to flush */
4561 assert(bound
->end
- bound
->start
<= (1ull << 32));
4562 if (dirty
->end
- dirty
->start
> (1ull << 32)) {
4563 cmd_buffer
->state
.pending_pipe_bits
|=
4564 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_VF_CACHE_INVALIDATE_BIT
;
4569 genX(cmd_buffer_update_dirty_vbs_for_gen8_vb_flush
)(struct anv_cmd_buffer
*cmd_buffer
,
4570 uint32_t access_type
,
4573 if (GEN_GEN
< 8 || GEN_GEN
> 9 ||
4574 !cmd_buffer
->device
->physical
->use_softpin
)
4577 if (access_type
== RANDOM
) {
4578 /* We have an index buffer */
4579 struct anv_vb_cache_range
*bound
= &cmd_buffer
->state
.gfx
.ib_bound_range
;
4580 struct anv_vb_cache_range
*dirty
= &cmd_buffer
->state
.gfx
.ib_dirty_range
;
4582 if (bound
->end
> bound
->start
) {
4583 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4584 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4588 uint64_t mask
= vb_used
;
4590 int i
= u_bit_scan64(&mask
);
4592 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_bound_ranges
));
4593 assert(i
< ARRAY_SIZE(cmd_buffer
->state
.gfx
.vb_dirty_ranges
));
4595 struct anv_vb_cache_range
*bound
, *dirty
;
4596 bound
= &cmd_buffer
->state
.gfx
.vb_bound_ranges
[i
];
4597 dirty
= &cmd_buffer
->state
.gfx
.vb_dirty_ranges
[i
];
4599 if (bound
->end
> bound
->start
) {
4600 dirty
->start
= MIN2(dirty
->start
, bound
->start
);
4601 dirty
->end
= MAX2(dirty
->end
, bound
->end
);
4607 * Update the pixel hashing modes that determine the balancing of PS threads
4608 * across subslices and slices.
4610 * \param width Width bound of the rendering area (already scaled down if \p
4611 * scale is greater than 1).
4612 * \param height Height bound of the rendering area (already scaled down if \p
4613 * scale is greater than 1).
4614 * \param scale The number of framebuffer samples that could potentially be
4615 * affected by an individual channel of the PS thread. This is
4616 * typically one for single-sampled rendering, but for operations
4617 * like CCS resolves and fast clears a single PS invocation may
4618 * update a huge number of pixels, in which case a finer
4619 * balancing is desirable in order to maximally utilize the
4620 * bandwidth available. UINT_MAX can be used as shorthand for
4621 * "finest hashing mode available".
4624 genX(cmd_buffer_emit_hashing_mode
)(struct anv_cmd_buffer
*cmd_buffer
,
4625 unsigned width
, unsigned height
,
4629 const struct gen_device_info
*devinfo
= &cmd_buffer
->device
->info
;
4630 const unsigned slice_hashing
[] = {
4631 /* Because all Gen9 platforms with more than one slice require
4632 * three-way subslice hashing, a single "normal" 16x16 slice hashing
4633 * block is guaranteed to suffer from substantial imbalance, with one
4634 * subslice receiving twice as much work as the other two in the
4637 * The performance impact of that would be particularly severe when
4638 * three-way hashing is also in use for slice balancing (which is the
4639 * case for all Gen9 GT4 platforms), because one of the slices
4640 * receives one every three 16x16 blocks in either direction, which
4641 * is roughly the periodicity of the underlying subslice imbalance
4642 * pattern ("roughly" because in reality the hardware's
4643 * implementation of three-way hashing doesn't do exact modulo 3
4644 * arithmetic, which somewhat decreases the magnitude of this effect
4645 * in practice). This leads to a systematic subslice imbalance
4646 * within that slice regardless of the size of the primitive. The
4647 * 32x32 hashing mode guarantees that the subslice imbalance within a
4648 * single slice hashing block is minimal, largely eliminating this
4652 /* Finest slice hashing mode available. */
4655 const unsigned subslice_hashing
[] = {
4656 /* 16x16 would provide a slight cache locality benefit especially
4657 * visible in the sampler L1 cache efficiency of low-bandwidth
4658 * non-LLC platforms, but it comes at the cost of greater subslice
4659 * imbalance for primitives of dimensions approximately intermediate
4660 * between 16x4 and 16x16.
4663 /* Finest subslice hashing mode available. */
4666 /* Dimensions of the smallest hashing block of a given hashing mode. If
4667 * the rendering area is smaller than this there can't possibly be any
4668 * benefit from switching to this mode, so we optimize out the
4671 const unsigned min_size
[][2] = {
4675 const unsigned idx
= scale
> 1;
4677 if (cmd_buffer
->state
.current_hash_scale
!= scale
&&
4678 (width
> min_size
[idx
][0] || height
> min_size
[idx
][1])) {
4681 anv_pack_struct(>_mode
, GENX(GT_MODE
),
4682 .SliceHashing
= (devinfo
->num_slices
> 1 ? slice_hashing
[idx
] : 0),
4683 .SliceHashingMask
= (devinfo
->num_slices
> 1 ? -1 : 0),
4684 .SubsliceHashing
= subslice_hashing
[idx
],
4685 .SubsliceHashingMask
= -1);
4687 cmd_buffer
->state
.pending_pipe_bits
|=
4688 ANV_PIPE_CS_STALL_BIT
| ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
4689 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4691 emit_lri(&cmd_buffer
->batch
, GENX(GT_MODE_num
), gt_mode
);
4693 cmd_buffer
->state
.current_hash_scale
= scale
;
4699 cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer
*cmd_buffer
)
4701 struct anv_device
*device
= cmd_buffer
->device
;
4702 const struct anv_image_view
*iview
=
4703 anv_cmd_buffer_get_depth_stencil_view(cmd_buffer
);
4704 const struct anv_image
*image
= iview
? iview
->image
: NULL
;
4706 /* FIXME: Width and Height are wrong */
4708 genX(cmd_buffer_emit_gen7_depth_flush
)(cmd_buffer
);
4710 uint32_t *dw
= anv_batch_emit_dwords(&cmd_buffer
->batch
,
4711 device
->isl_dev
.ds
.size
/ 4);
4715 struct isl_depth_stencil_hiz_emit_info info
= { };
4718 info
.view
= &iview
->planes
[0].isl
;
4720 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
)) {
4721 uint32_t depth_plane
=
4722 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_DEPTH_BIT
);
4723 const struct anv_surface
*surface
= &image
->planes
[depth_plane
].surface
;
4725 info
.depth_surf
= &surface
->isl
;
4727 info
.depth_address
=
4728 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4729 dw
+ device
->isl_dev
.ds
.depth_offset
/ 4,
4730 image
->planes
[depth_plane
].address
.bo
,
4731 image
->planes
[depth_plane
].address
.offset
+
4734 anv_mocs_for_bo(device
, image
->planes
[depth_plane
].address
.bo
);
4737 cmd_buffer
->state
.subpass
->depth_stencil_attachment
->attachment
;
4738 info
.hiz_usage
= cmd_buffer
->state
.attachments
[ds
].aux_usage
;
4739 if (info
.hiz_usage
== ISL_AUX_USAGE_HIZ
) {
4740 info
.hiz_surf
= &image
->planes
[depth_plane
].aux_surface
.isl
;
4743 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4744 dw
+ device
->isl_dev
.ds
.hiz_offset
/ 4,
4745 image
->planes
[depth_plane
].address
.bo
,
4746 image
->planes
[depth_plane
].address
.offset
+
4747 image
->planes
[depth_plane
].aux_surface
.offset
);
4749 info
.depth_clear_value
= ANV_HZ_FC_VAL
;
4753 if (image
&& (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4754 uint32_t stencil_plane
=
4755 anv_image_aspect_to_plane(image
->aspects
, VK_IMAGE_ASPECT_STENCIL_BIT
);
4756 const struct anv_surface
*surface
= &image
->planes
[stencil_plane
].surface
;
4758 info
.stencil_surf
= &surface
->isl
;
4760 info
.stencil_address
=
4761 anv_batch_emit_reloc(&cmd_buffer
->batch
,
4762 dw
+ device
->isl_dev
.ds
.stencil_offset
/ 4,
4763 image
->planes
[stencil_plane
].address
.bo
,
4764 image
->planes
[stencil_plane
].address
.offset
+
4767 anv_mocs_for_bo(device
, image
->planes
[stencil_plane
].address
.bo
);
4770 isl_emit_depth_stencil_hiz_s(&device
->isl_dev
, dw
, &info
);
4772 if (GEN_GEN
>= 12) {
4773 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
4774 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
4776 /* GEN:BUG:1408224581
4778 * Workaround: Gen12LP Astep only An additional pipe control with
4779 * post-sync = store dword operation would be required.( w/a is to
4780 * have an additional pipe control after the stencil state whenever
4781 * the surface state bits of this state is changing).
4783 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
4784 pc
.PostSyncOperation
= WriteImmediateData
;
4786 (struct anv_address
) { cmd_buffer
->device
->workaround_bo
, 0 };
4789 cmd_buffer
->state
.hiz_enabled
= info
.hiz_usage
== ISL_AUX_USAGE_HIZ
;
4793 * This ANDs the view mask of the current subpass with the pending clear
4794 * views in the attachment to get the mask of views active in the subpass
4795 * that still need to be cleared.
4797 static inline uint32_t
4798 get_multiview_subpass_clear_mask(const struct anv_cmd_state
*cmd_state
,
4799 const struct anv_attachment_state
*att_state
)
4801 return cmd_state
->subpass
->view_mask
& att_state
->pending_clear_views
;
4805 do_first_layer_clear(const struct anv_cmd_state
*cmd_state
,
4806 const struct anv_attachment_state
*att_state
)
4808 if (!cmd_state
->subpass
->view_mask
)
4811 uint32_t pending_clear_mask
=
4812 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
4814 return pending_clear_mask
& 1;
4818 current_subpass_is_last_for_attachment(const struct anv_cmd_state
*cmd_state
,
4821 const uint32_t last_subpass_idx
=
4822 cmd_state
->pass
->attachments
[att_idx
].last_subpass_idx
;
4823 const struct anv_subpass
*last_subpass
=
4824 &cmd_state
->pass
->subpasses
[last_subpass_idx
];
4825 return last_subpass
== cmd_state
->subpass
;
4829 cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer
,
4830 uint32_t subpass_id
)
4832 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
4833 struct anv_subpass
*subpass
= &cmd_state
->pass
->subpasses
[subpass_id
];
4834 cmd_state
->subpass
= subpass
;
4836 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_RENDER_TARGETS
;
4838 /* Our implementation of VK_KHR_multiview uses instancing to draw the
4839 * different views. If the client asks for instancing, we need to use the
4840 * Instance Data Step Rate to ensure that we repeat the client's
4841 * per-instance data once for each view. Since this bit is in
4842 * VERTEX_BUFFER_STATE on gen7, we need to dirty vertex buffers at the top
4846 cmd_buffer
->state
.gfx
.vb_dirty
|= ~0;
4848 /* It is possible to start a render pass with an old pipeline. Because the
4849 * render pass and subpass index are both baked into the pipeline, this is
4850 * highly unlikely. In order to do so, it requires that you have a render
4851 * pass with a single subpass and that you use that render pass twice
4852 * back-to-back and use the same pipeline at the start of the second render
4853 * pass as at the end of the first. In order to avoid unpredictable issues
4854 * with this edge case, we just dirty the pipeline at the start of every
4857 cmd_buffer
->state
.gfx
.dirty
|= ANV_CMD_DIRTY_PIPELINE
;
4859 /* Accumulate any subpass flushes that need to happen before the subpass */
4860 cmd_buffer
->state
.pending_pipe_bits
|=
4861 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
];
4863 VkRect2D render_area
= cmd_buffer
->state
.render_area
;
4864 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
4866 bool is_multiview
= subpass
->view_mask
!= 0;
4868 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
4869 const uint32_t a
= subpass
->attachments
[i
].attachment
;
4870 if (a
== VK_ATTACHMENT_UNUSED
)
4873 assert(a
< cmd_state
->pass
->attachment_count
);
4874 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
4876 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
4877 const struct anv_image
*image
= iview
->image
;
4879 /* A resolve is necessary before use as an input attachment if the clear
4880 * color or auxiliary buffer usage isn't supported by the sampler.
4882 const bool input_needs_resolve
=
4883 (att_state
->fast_clear
&& !att_state
->clear_color_is_zero_one
) ||
4884 att_state
->input_aux_usage
!= att_state
->aux_usage
;
4886 VkImageLayout target_layout
;
4887 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
&&
4888 !input_needs_resolve
) {
4889 /* Layout transitions before the final only help to enable sampling
4890 * as an input attachment. If the input attachment supports sampling
4891 * using the auxiliary surface, we can skip such transitions by
4892 * making the target layout one that is CCS-aware.
4894 target_layout
= VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
4896 target_layout
= subpass
->attachments
[i
].layout
;
4899 VkImageLayout target_stencil_layout
=
4900 subpass
->attachments
[i
].stencil_layout
;
4902 uint32_t base_layer
, layer_count
;
4903 if (image
->type
== VK_IMAGE_TYPE_3D
) {
4905 layer_count
= anv_minify(iview
->image
->extent
.depth
,
4906 iview
->planes
[0].isl
.base_level
);
4908 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
4909 layer_count
= fb
->layers
;
4912 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
4913 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4914 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
4915 iview
->planes
[0].isl
.base_level
, 1,
4916 base_layer
, layer_count
,
4917 att_state
->current_layout
, target_layout
);
4920 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
4921 transition_depth_buffer(cmd_buffer
, image
,
4922 att_state
->current_layout
, target_layout
);
4923 att_state
->aux_usage
=
4924 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, image
,
4925 VK_IMAGE_ASPECT_DEPTH_BIT
,
4926 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
,
4930 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
4931 transition_stencil_buffer(cmd_buffer
, image
,
4932 iview
->planes
[0].isl
.base_level
, 1,
4933 base_layer
, layer_count
,
4934 att_state
->current_stencil_layout
,
4935 target_stencil_layout
);
4937 att_state
->current_layout
= target_layout
;
4938 att_state
->current_stencil_layout
= target_stencil_layout
;
4940 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4941 assert(att_state
->pending_clear_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4943 /* Multi-planar images are not supported as attachments */
4944 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
4945 assert(image
->n_planes
== 1);
4947 uint32_t base_clear_layer
= iview
->planes
[0].isl
.base_array_layer
;
4948 uint32_t clear_layer_count
= fb
->layers
;
4950 if (att_state
->fast_clear
&&
4951 do_first_layer_clear(cmd_state
, att_state
)) {
4952 /* We only support fast-clears on the first layer */
4953 assert(iview
->planes
[0].isl
.base_level
== 0);
4954 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
4956 union isl_color_value clear_color
= {};
4957 anv_clear_color_from_att_state(&clear_color
, att_state
, iview
);
4958 if (iview
->image
->samples
== 1) {
4959 anv_image_ccs_op(cmd_buffer
, image
,
4960 iview
->planes
[0].isl
.format
,
4961 VK_IMAGE_ASPECT_COLOR_BIT
,
4962 0, 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4966 anv_image_mcs_op(cmd_buffer
, image
,
4967 iview
->planes
[0].isl
.format
,
4968 VK_IMAGE_ASPECT_COLOR_BIT
,
4969 0, 1, ISL_AUX_OP_FAST_CLEAR
,
4974 clear_layer_count
--;
4976 att_state
->pending_clear_views
&= ~1;
4978 if (att_state
->clear_color_is_zero
) {
4979 /* This image has the auxiliary buffer enabled. We can mark the
4980 * subresource as not needing a resolve because the clear color
4981 * will match what's in every RENDER_SURFACE_STATE object when
4982 * it's being used for sampling.
4984 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4985 VK_IMAGE_ASPECT_COLOR_BIT
,
4986 ANV_FAST_CLEAR_DEFAULT_VALUE
);
4988 set_image_fast_clear_state(cmd_buffer
, iview
->image
,
4989 VK_IMAGE_ASPECT_COLOR_BIT
,
4990 ANV_FAST_CLEAR_ANY
);
4994 /* From the VkFramebufferCreateInfo spec:
4996 * "If the render pass uses multiview, then layers must be one and each
4997 * attachment requires a number of layers that is greater than the
4998 * maximum bit index set in the view mask in the subpasses in which it
5001 * So if multiview is active we ignore the number of layers in the
5002 * framebuffer and instead we honor the view mask from the subpass.
5005 assert(image
->n_planes
== 1);
5006 uint32_t pending_clear_mask
=
5007 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5010 for_each_bit(layer_idx
, pending_clear_mask
) {
5012 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5014 anv_image_clear_color(cmd_buffer
, image
,
5015 VK_IMAGE_ASPECT_COLOR_BIT
,
5016 att_state
->aux_usage
,
5017 iview
->planes
[0].isl
.format
,
5018 iview
->planes
[0].isl
.swizzle
,
5019 iview
->planes
[0].isl
.base_level
,
5022 vk_to_isl_color(att_state
->clear_value
.color
));
5025 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5026 } else if (clear_layer_count
> 0) {
5027 assert(image
->n_planes
== 1);
5028 anv_image_clear_color(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5029 att_state
->aux_usage
,
5030 iview
->planes
[0].isl
.format
,
5031 iview
->planes
[0].isl
.swizzle
,
5032 iview
->planes
[0].isl
.base_level
,
5033 base_clear_layer
, clear_layer_count
,
5035 vk_to_isl_color(att_state
->clear_value
.color
));
5037 } else if (att_state
->pending_clear_aspects
& (VK_IMAGE_ASPECT_DEPTH_BIT
|
5038 VK_IMAGE_ASPECT_STENCIL_BIT
)) {
5039 if (att_state
->fast_clear
&& !is_multiview
) {
5040 /* We currently only support HiZ for single-layer images */
5041 if (att_state
->pending_clear_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5042 assert(iview
->image
->planes
[0].aux_usage
== ISL_AUX_USAGE_HIZ
);
5043 assert(iview
->planes
[0].isl
.base_level
== 0);
5044 assert(iview
->planes
[0].isl
.base_array_layer
== 0);
5045 assert(fb
->layers
== 1);
5048 anv_image_hiz_clear(cmd_buffer
, image
,
5049 att_state
->pending_clear_aspects
,
5050 iview
->planes
[0].isl
.base_level
,
5051 iview
->planes
[0].isl
.base_array_layer
,
5052 fb
->layers
, render_area
,
5053 att_state
->clear_value
.depthStencil
.stencil
);
5054 } else if (is_multiview
) {
5055 uint32_t pending_clear_mask
=
5056 get_multiview_subpass_clear_mask(cmd_state
, att_state
);
5059 for_each_bit(layer_idx
, pending_clear_mask
) {
5061 iview
->planes
[0].isl
.base_array_layer
+ layer_idx
;
5063 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5064 att_state
->pending_clear_aspects
,
5065 att_state
->aux_usage
,
5066 iview
->planes
[0].isl
.base_level
,
5069 att_state
->clear_value
.depthStencil
.depth
,
5070 att_state
->clear_value
.depthStencil
.stencil
);
5073 att_state
->pending_clear_views
&= ~pending_clear_mask
;
5075 anv_image_clear_depth_stencil(cmd_buffer
, image
,
5076 att_state
->pending_clear_aspects
,
5077 att_state
->aux_usage
,
5078 iview
->planes
[0].isl
.base_level
,
5079 iview
->planes
[0].isl
.base_array_layer
,
5080 fb
->layers
, render_area
,
5081 att_state
->clear_value
.depthStencil
.depth
,
5082 att_state
->clear_value
.depthStencil
.stencil
);
5085 assert(att_state
->pending_clear_aspects
== 0);
5089 (att_state
->pending_load_aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5090 image
->planes
[0].aux_usage
!= ISL_AUX_USAGE_NONE
&&
5091 iview
->planes
[0].isl
.base_level
== 0 &&
5092 iview
->planes
[0].isl
.base_array_layer
== 0) {
5093 if (att_state
->aux_usage
!= ISL_AUX_USAGE_NONE
) {
5094 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->color
.state
,
5095 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5096 false /* copy to ss */);
5099 if (need_input_attachment_state(&cmd_state
->pass
->attachments
[a
]) &&
5100 att_state
->input_aux_usage
!= ISL_AUX_USAGE_NONE
) {
5101 genX(copy_fast_clear_dwords
)(cmd_buffer
, att_state
->input
.state
,
5102 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5103 false /* copy to ss */);
5107 if (subpass
->attachments
[i
].usage
==
5108 VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
) {
5109 /* We assume that if we're starting a subpass, we're going to do some
5110 * rendering so we may end up with compressed data.
5112 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, iview
->image
,
5113 VK_IMAGE_ASPECT_COLOR_BIT
,
5114 att_state
->aux_usage
,
5115 iview
->planes
[0].isl
.base_level
,
5116 iview
->planes
[0].isl
.base_array_layer
,
5118 } else if (subpass
->attachments
[i
].usage
==
5119 VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
) {
5120 /* We may be writing depth or stencil so we need to mark the surface.
5121 * Unfortunately, there's no way to know at this point whether the
5122 * depth or stencil tests used will actually write to the surface.
5124 * Even though stencil may be plane 1, it always shares a base_level
5127 const struct isl_view
*ds_view
= &iview
->planes
[0].isl
;
5128 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5129 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
5130 VK_IMAGE_ASPECT_DEPTH_BIT
,
5131 att_state
->aux_usage
,
5132 ds_view
->base_level
,
5133 ds_view
->base_array_layer
,
5136 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5137 /* Even though stencil may be plane 1, it always shares a
5138 * base_level with depth.
5140 genX(cmd_buffer_mark_image_written
)(cmd_buffer
, image
,
5141 VK_IMAGE_ASPECT_STENCIL_BIT
,
5143 ds_view
->base_level
,
5144 ds_view
->base_array_layer
,
5149 /* If multiview is enabled, then we are only done clearing when we no
5150 * longer have pending layers to clear, or when we have processed the
5151 * last subpass that uses this attachment.
5153 if (!is_multiview
||
5154 att_state
->pending_clear_views
== 0 ||
5155 current_subpass_is_last_for_attachment(cmd_state
, a
)) {
5156 att_state
->pending_clear_aspects
= 0;
5159 att_state
->pending_load_aspects
= 0;
5163 /* The PIPE_CONTROL command description says:
5165 * "Whenever a Binding Table Index (BTI) used by a Render Taget Message
5166 * points to a different RENDER_SURFACE_STATE, SW must issue a Render
5167 * Target Cache Flush by enabling this bit. When render target flush
5168 * is set due to new association of BTI, PS Scoreboard Stall bit must
5169 * be set in this packet."
5171 cmd_buffer
->state
.pending_pipe_bits
|=
5172 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
|
5173 ANV_PIPE_STALL_AT_SCOREBOARD_BIT
;
5177 /* GEN:BUG:14010455700
5179 * ISL will change some CHICKEN registers depending on the depth surface
5180 * format, along with emitting the depth and stencil packets. In that case,
5181 * we want to do a depth flush and stall, so the pipeline is not using these
5182 * settings while we change the registers.
5184 cmd_buffer
->state
.pending_pipe_bits
|=
5185 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
|
5186 ANV_PIPE_DEPTH_STALL_BIT
|
5187 ANV_PIPE_END_OF_PIPE_SYNC_BIT
;
5188 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5191 cmd_buffer_emit_depth_stencil(cmd_buffer
);
5194 static enum blorp_filter
5195 vk_to_blorp_resolve_mode(VkResolveModeFlagBitsKHR vk_mode
)
5198 case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
:
5199 return BLORP_FILTER_SAMPLE_0
;
5200 case VK_RESOLVE_MODE_AVERAGE_BIT_KHR
:
5201 return BLORP_FILTER_AVERAGE
;
5202 case VK_RESOLVE_MODE_MIN_BIT_KHR
:
5203 return BLORP_FILTER_MIN_SAMPLE
;
5204 case VK_RESOLVE_MODE_MAX_BIT_KHR
:
5205 return BLORP_FILTER_MAX_SAMPLE
;
5207 return BLORP_FILTER_NONE
;
5212 cmd_buffer_end_subpass(struct anv_cmd_buffer
*cmd_buffer
)
5214 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5215 struct anv_subpass
*subpass
= cmd_state
->subpass
;
5216 uint32_t subpass_id
= anv_get_subpass_id(&cmd_buffer
->state
);
5217 struct anv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
5219 if (subpass
->has_color_resolve
) {
5220 /* We are about to do some MSAA resolves. We need to flush so that the
5221 * result of writes to the MSAA color attachments show up in the sampler
5222 * when we blit to the single-sampled resolve target.
5224 cmd_buffer
->state
.pending_pipe_bits
|=
5225 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5226 ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT
;
5228 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
5229 uint32_t src_att
= subpass
->color_attachments
[i
].attachment
;
5230 uint32_t dst_att
= subpass
->resolve_attachments
[i
].attachment
;
5232 if (dst_att
== VK_ATTACHMENT_UNUSED
)
5235 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5236 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5238 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5239 /* From the Vulkan 1.0 spec:
5241 * If the first use of an attachment in a render pass is as a
5242 * resolve attachment, then the loadOp is effectively ignored
5243 * as the resolve is guaranteed to overwrite all pixels in the
5246 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5249 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5250 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5252 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5254 enum isl_aux_usage src_aux_usage
=
5255 cmd_buffer
->state
.attachments
[src_att
].aux_usage
;
5256 enum isl_aux_usage dst_aux_usage
=
5257 cmd_buffer
->state
.attachments
[dst_att
].aux_usage
;
5259 assert(src_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
&&
5260 dst_iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
);
5262 anv_image_msaa_resolve(cmd_buffer
,
5263 src_iview
->image
, src_aux_usage
,
5264 src_iview
->planes
[0].isl
.base_level
,
5265 src_iview
->planes
[0].isl
.base_array_layer
,
5266 dst_iview
->image
, dst_aux_usage
,
5267 dst_iview
->planes
[0].isl
.base_level
,
5268 dst_iview
->planes
[0].isl
.base_array_layer
,
5269 VK_IMAGE_ASPECT_COLOR_BIT
,
5270 render_area
.offset
.x
, render_area
.offset
.y
,
5271 render_area
.offset
.x
, render_area
.offset
.y
,
5272 render_area
.extent
.width
,
5273 render_area
.extent
.height
,
5274 fb
->layers
, BLORP_FILTER_NONE
);
5278 if (subpass
->ds_resolve_attachment
) {
5279 /* We are about to do some MSAA resolves. We need to flush so that the
5280 * result of writes to the MSAA depth attachments show up in the sampler
5281 * when we blit to the single-sampled resolve target.
5283 cmd_buffer
->state
.pending_pipe_bits
|=
5284 ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT
|
5285 ANV_PIPE_DEPTH_CACHE_FLUSH_BIT
;
5287 uint32_t src_att
= subpass
->depth_stencil_attachment
->attachment
;
5288 uint32_t dst_att
= subpass
->ds_resolve_attachment
->attachment
;
5290 assert(src_att
< cmd_buffer
->state
.pass
->attachment_count
);
5291 assert(dst_att
< cmd_buffer
->state
.pass
->attachment_count
);
5293 if (cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
) {
5294 /* From the Vulkan 1.0 spec:
5296 * If the first use of an attachment in a render pass is as a
5297 * resolve attachment, then the loadOp is effectively ignored
5298 * as the resolve is guaranteed to overwrite all pixels in the
5301 cmd_buffer
->state
.attachments
[dst_att
].pending_clear_aspects
= 0;
5304 struct anv_image_view
*src_iview
= cmd_state
->attachments
[src_att
].image_view
;
5305 struct anv_image_view
*dst_iview
= cmd_state
->attachments
[dst_att
].image_view
;
5307 const VkRect2D render_area
= cmd_buffer
->state
.render_area
;
5309 struct anv_attachment_state
*src_state
=
5310 &cmd_state
->attachments
[src_att
];
5311 struct anv_attachment_state
*dst_state
=
5312 &cmd_state
->attachments
[dst_att
];
5314 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
5315 subpass
->depth_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5317 /* MSAA resolves sample from the source attachment. Transition the
5318 * depth attachment first to get rid of any HiZ that we may not be
5321 transition_depth_buffer(cmd_buffer
, src_iview
->image
,
5322 src_state
->current_layout
,
5323 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5324 src_state
->aux_usage
=
5325 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, src_iview
->image
,
5326 VK_IMAGE_ASPECT_DEPTH_BIT
,
5327 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
,
5328 VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
);
5329 src_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5331 /* MSAA resolves write to the resolve attachment as if it were any
5332 * other transfer op. Transition the resolve attachment accordingly.
5334 VkImageLayout dst_initial_layout
= dst_state
->current_layout
;
5336 /* If our render area is the entire size of the image, we're going to
5337 * blow it all away so we can claim the initial layout is UNDEFINED
5338 * and we'll get a HiZ ambiguate instead of a resolve.
5340 if (dst_iview
->image
->type
!= VK_IMAGE_TYPE_3D
&&
5341 render_area
.offset
.x
== 0 && render_area
.offset
.y
== 0 &&
5342 render_area
.extent
.width
== dst_iview
->extent
.width
&&
5343 render_area
.extent
.height
== dst_iview
->extent
.height
)
5344 dst_initial_layout
= VK_IMAGE_LAYOUT_UNDEFINED
;
5346 transition_depth_buffer(cmd_buffer
, dst_iview
->image
,
5348 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5349 dst_state
->aux_usage
=
5350 anv_layout_to_aux_usage(&cmd_buffer
->device
->info
, dst_iview
->image
,
5351 VK_IMAGE_ASPECT_DEPTH_BIT
,
5352 VK_IMAGE_USAGE_TRANSFER_DST_BIT
,
5353 VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
);
5354 dst_state
->current_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5356 enum blorp_filter filter
=
5357 vk_to_blorp_resolve_mode(subpass
->depth_resolve_mode
);
5359 anv_image_msaa_resolve(cmd_buffer
,
5360 src_iview
->image
, src_state
->aux_usage
,
5361 src_iview
->planes
[0].isl
.base_level
,
5362 src_iview
->planes
[0].isl
.base_array_layer
,
5363 dst_iview
->image
, dst_state
->aux_usage
,
5364 dst_iview
->planes
[0].isl
.base_level
,
5365 dst_iview
->planes
[0].isl
.base_array_layer
,
5366 VK_IMAGE_ASPECT_DEPTH_BIT
,
5367 render_area
.offset
.x
, render_area
.offset
.y
,
5368 render_area
.offset
.x
, render_area
.offset
.y
,
5369 render_area
.extent
.width
,
5370 render_area
.extent
.height
,
5371 fb
->layers
, filter
);
5374 if ((src_iview
->image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
5375 subpass
->stencil_resolve_mode
!= VK_RESOLVE_MODE_NONE_KHR
) {
5377 src_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL
;
5378 dst_state
->current_stencil_layout
= VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
;
5380 enum isl_aux_usage src_aux_usage
= ISL_AUX_USAGE_NONE
;
5381 enum isl_aux_usage dst_aux_usage
= ISL_AUX_USAGE_NONE
;
5383 enum blorp_filter filter
=
5384 vk_to_blorp_resolve_mode(subpass
->stencil_resolve_mode
);
5386 anv_image_msaa_resolve(cmd_buffer
,
5387 src_iview
->image
, src_aux_usage
,
5388 src_iview
->planes
[0].isl
.base_level
,
5389 src_iview
->planes
[0].isl
.base_array_layer
,
5390 dst_iview
->image
, dst_aux_usage
,
5391 dst_iview
->planes
[0].isl
.base_level
,
5392 dst_iview
->planes
[0].isl
.base_array_layer
,
5393 VK_IMAGE_ASPECT_STENCIL_BIT
,
5394 render_area
.offset
.x
, render_area
.offset
.y
,
5395 render_area
.offset
.x
, render_area
.offset
.y
,
5396 render_area
.extent
.width
,
5397 render_area
.extent
.height
,
5398 fb
->layers
, filter
);
5403 /* On gen7, we have to store a texturable version of the stencil buffer in
5404 * a shadow whenever VK_IMAGE_USAGE_SAMPLED_BIT is set and copy back and
5405 * forth at strategic points. Stencil writes are only allowed in following
5408 * - VK_IMAGE_LAYOUT_GENERAL
5409 * - VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
5410 * - VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
5411 * - VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL
5412 * - VK_IMAGE_LAYOUT_STENCIL_ATTACHMENT_OPTIMAL_KHR
5414 * For general, we have no nice opportunity to transition so we do the copy
5415 * to the shadow unconditionally at the end of the subpass. For transfer
5416 * destinations, we can update it as part of the transfer op. For the other
5417 * layouts, we delay the copy until a transition into some other layout.
5419 if (subpass
->depth_stencil_attachment
) {
5420 uint32_t a
= subpass
->depth_stencil_attachment
->attachment
;
5421 assert(a
!= VK_ATTACHMENT_UNUSED
);
5423 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5424 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;;
5425 const struct anv_image
*image
= iview
->image
;
5427 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5428 uint32_t plane
= anv_image_aspect_to_plane(image
->aspects
,
5429 VK_IMAGE_ASPECT_STENCIL_BIT
);
5431 if (image
->planes
[plane
].shadow_surface
.isl
.size_B
> 0 &&
5432 att_state
->current_stencil_layout
== VK_IMAGE_LAYOUT_GENERAL
) {
5433 assert(image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
);
5434 anv_image_copy_to_shadow(cmd_buffer
, image
,
5435 VK_IMAGE_ASPECT_STENCIL_BIT
,
5436 iview
->planes
[plane
].isl
.base_level
, 1,
5437 iview
->planes
[plane
].isl
.base_array_layer
,
5442 #endif /* GEN_GEN == 7 */
5444 for (uint32_t i
= 0; i
< subpass
->attachment_count
; ++i
) {
5445 const uint32_t a
= subpass
->attachments
[i
].attachment
;
5446 if (a
== VK_ATTACHMENT_UNUSED
)
5449 if (cmd_state
->pass
->attachments
[a
].last_subpass_idx
!= subpass_id
)
5452 assert(a
< cmd_state
->pass
->attachment_count
);
5453 struct anv_attachment_state
*att_state
= &cmd_state
->attachments
[a
];
5454 struct anv_image_view
*iview
= cmd_state
->attachments
[a
].image_view
;
5455 const struct anv_image
*image
= iview
->image
;
5457 if ((image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) &&
5458 image
->vk_format
!= iview
->vk_format
) {
5459 enum anv_fast_clear_type fast_clear_type
=
5460 anv_layout_to_fast_clear_type(&cmd_buffer
->device
->info
,
5461 image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5462 att_state
->current_layout
);
5464 /* If any clear color was used, flush it down the aux surfaces. If we
5465 * don't do it now using the view's format we might use the clear
5466 * color incorrectly in the following resolves (for example with an
5467 * SRGB view & a UNORM image).
5469 if (fast_clear_type
!= ANV_FAST_CLEAR_NONE
) {
5470 anv_perf_warn(cmd_buffer
->device
, iview
,
5471 "Doing a partial resolve to get rid of clear color at the "
5472 "end of a renderpass due to an image/view format mismatch");
5474 uint32_t base_layer
, layer_count
;
5475 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5477 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5478 iview
->planes
[0].isl
.base_level
);
5480 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5481 layer_count
= fb
->layers
;
5484 for (uint32_t a
= 0; a
< layer_count
; a
++) {
5485 uint32_t array_layer
= base_layer
+ a
;
5486 if (image
->samples
== 1) {
5487 anv_cmd_predicated_ccs_resolve(cmd_buffer
, image
,
5488 iview
->planes
[0].isl
.format
,
5489 VK_IMAGE_ASPECT_COLOR_BIT
,
5490 iview
->planes
[0].isl
.base_level
,
5492 ISL_AUX_OP_PARTIAL_RESOLVE
,
5493 ANV_FAST_CLEAR_NONE
);
5495 anv_cmd_predicated_mcs_resolve(cmd_buffer
, image
,
5496 iview
->planes
[0].isl
.format
,
5497 VK_IMAGE_ASPECT_COLOR_BIT
,
5499 ISL_AUX_OP_PARTIAL_RESOLVE
,
5500 ANV_FAST_CLEAR_NONE
);
5506 /* Transition the image into the final layout for this render pass */
5507 VkImageLayout target_layout
=
5508 cmd_state
->pass
->attachments
[a
].final_layout
;
5509 VkImageLayout target_stencil_layout
=
5510 cmd_state
->pass
->attachments
[a
].stencil_final_layout
;
5512 uint32_t base_layer
, layer_count
;
5513 if (image
->type
== VK_IMAGE_TYPE_3D
) {
5515 layer_count
= anv_minify(iview
->image
->extent
.depth
,
5516 iview
->planes
[0].isl
.base_level
);
5518 base_layer
= iview
->planes
[0].isl
.base_array_layer
;
5519 layer_count
= fb
->layers
;
5522 if (image
->aspects
& VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV
) {
5523 assert(image
->aspects
== VK_IMAGE_ASPECT_COLOR_BIT
);
5524 transition_color_buffer(cmd_buffer
, image
, VK_IMAGE_ASPECT_COLOR_BIT
,
5525 iview
->planes
[0].isl
.base_level
, 1,
5526 base_layer
, layer_count
,
5527 att_state
->current_layout
, target_layout
);
5530 if (image
->aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) {
5531 transition_depth_buffer(cmd_buffer
, image
,
5532 att_state
->current_layout
, target_layout
);
5535 if (image
->aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) {
5536 transition_stencil_buffer(cmd_buffer
, image
,
5537 iview
->planes
[0].isl
.base_level
, 1,
5538 base_layer
, layer_count
,
5539 att_state
->current_stencil_layout
,
5540 target_stencil_layout
);
5544 /* Accumulate any subpass flushes that need to happen after the subpass.
5545 * Yes, they do get accumulated twice in the NextSubpass case but since
5546 * genX_CmdNextSubpass just calls end/begin back-to-back, we just end up
5547 * ORing the bits in twice so it's harmless.
5549 cmd_buffer
->state
.pending_pipe_bits
|=
5550 cmd_buffer
->state
.pass
->subpass_flushes
[subpass_id
+ 1];
5553 void genX(CmdBeginRenderPass
)(
5554 VkCommandBuffer commandBuffer
,
5555 const VkRenderPassBeginInfo
* pRenderPassBegin
,
5556 VkSubpassContents contents
)
5558 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5559 ANV_FROM_HANDLE(anv_render_pass
, pass
, pRenderPassBegin
->renderPass
);
5560 ANV_FROM_HANDLE(anv_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
5562 cmd_buffer
->state
.framebuffer
= framebuffer
;
5563 cmd_buffer
->state
.pass
= pass
;
5564 cmd_buffer
->state
.render_area
= pRenderPassBegin
->renderArea
;
5566 genX(cmd_buffer_setup_attachments
)(cmd_buffer
, pass
, pRenderPassBegin
);
5568 /* If we failed to setup the attachments we should not try to go further */
5569 if (result
!= VK_SUCCESS
) {
5570 assert(anv_batch_has_error(&cmd_buffer
->batch
));
5574 genX(flush_pipeline_select_3d
)(cmd_buffer
);
5576 cmd_buffer_begin_subpass(cmd_buffer
, 0);
5579 void genX(CmdBeginRenderPass2
)(
5580 VkCommandBuffer commandBuffer
,
5581 const VkRenderPassBeginInfo
* pRenderPassBeginInfo
,
5582 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
)
5584 genX(CmdBeginRenderPass
)(commandBuffer
, pRenderPassBeginInfo
,
5585 pSubpassBeginInfo
->contents
);
5588 void genX(CmdNextSubpass
)(
5589 VkCommandBuffer commandBuffer
,
5590 VkSubpassContents contents
)
5592 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5594 if (anv_batch_has_error(&cmd_buffer
->batch
))
5597 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
5599 uint32_t prev_subpass
= anv_get_subpass_id(&cmd_buffer
->state
);
5600 cmd_buffer_end_subpass(cmd_buffer
);
5601 cmd_buffer_begin_subpass(cmd_buffer
, prev_subpass
+ 1);
5604 void genX(CmdNextSubpass2
)(
5605 VkCommandBuffer commandBuffer
,
5606 const VkSubpassBeginInfoKHR
* pSubpassBeginInfo
,
5607 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5609 genX(CmdNextSubpass
)(commandBuffer
, pSubpassBeginInfo
->contents
);
5612 void genX(CmdEndRenderPass
)(
5613 VkCommandBuffer commandBuffer
)
5615 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5617 if (anv_batch_has_error(&cmd_buffer
->batch
))
5620 cmd_buffer_end_subpass(cmd_buffer
);
5622 cmd_buffer
->state
.hiz_enabled
= false;
5625 anv_dump_add_attachments(cmd_buffer
);
5628 /* Remove references to render pass specific state. This enables us to
5629 * detect whether or not we're in a renderpass.
5631 cmd_buffer
->state
.framebuffer
= NULL
;
5632 cmd_buffer
->state
.pass
= NULL
;
5633 cmd_buffer
->state
.subpass
= NULL
;
5636 void genX(CmdEndRenderPass2
)(
5637 VkCommandBuffer commandBuffer
,
5638 const VkSubpassEndInfoKHR
* pSubpassEndInfo
)
5640 genX(CmdEndRenderPass
)(commandBuffer
);
5644 genX(cmd_emit_conditional_render_predicate
)(struct anv_cmd_buffer
*cmd_buffer
)
5646 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5647 struct gen_mi_builder b
;
5648 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5650 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC0
),
5651 gen_mi_reg32(ANV_PREDICATE_RESULT_REG
));
5652 gen_mi_store(&b
, gen_mi_reg64(MI_PREDICATE_SRC1
), gen_mi_imm(0));
5654 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_PREDICATE
), mip
) {
5655 mip
.LoadOperation
= LOAD_LOADINV
;
5656 mip
.CombineOperation
= COMBINE_SET
;
5657 mip
.CompareOperation
= COMPARE_SRCS_EQUAL
;
5662 #if GEN_GEN >= 8 || GEN_IS_HASWELL
5663 void genX(CmdBeginConditionalRenderingEXT
)(
5664 VkCommandBuffer commandBuffer
,
5665 const VkConditionalRenderingBeginInfoEXT
* pConditionalRenderingBegin
)
5667 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5668 ANV_FROM_HANDLE(anv_buffer
, buffer
, pConditionalRenderingBegin
->buffer
);
5669 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5670 struct anv_address value_address
=
5671 anv_address_add(buffer
->address
, pConditionalRenderingBegin
->offset
);
5673 const bool isInverted
= pConditionalRenderingBegin
->flags
&
5674 VK_CONDITIONAL_RENDERING_INVERTED_BIT_EXT
;
5676 cmd_state
->conditional_render_enabled
= true;
5678 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5680 struct gen_mi_builder b
;
5681 gen_mi_builder_init(&b
, &cmd_buffer
->batch
);
5683 /* Section 19.4 of the Vulkan 1.1.85 spec says:
5685 * If the value of the predicate in buffer memory changes
5686 * while conditional rendering is active, the rendering commands
5687 * may be discarded in an implementation-dependent way.
5688 * Some implementations may latch the value of the predicate
5689 * upon beginning conditional rendering while others
5690 * may read it before every rendering command.
5692 * So it's perfectly fine to read a value from the buffer once.
5694 struct gen_mi_value value
= gen_mi_mem32(value_address
);
5696 /* Precompute predicate result, it is necessary to support secondary
5697 * command buffers since it is unknown if conditional rendering is
5698 * inverted when populating them.
5700 gen_mi_store(&b
, gen_mi_reg64(ANV_PREDICATE_RESULT_REG
),
5701 isInverted
? gen_mi_uge(&b
, gen_mi_imm(0), value
) :
5702 gen_mi_ult(&b
, gen_mi_imm(0), value
));
5705 void genX(CmdEndConditionalRenderingEXT
)(
5706 VkCommandBuffer commandBuffer
)
5708 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5709 struct anv_cmd_state
*cmd_state
= &cmd_buffer
->state
;
5711 cmd_state
->conditional_render_enabled
= false;
5715 /* Set of stage bits for which are pipelined, i.e. they get queued by the
5716 * command streamer for later execution.
5718 #define ANV_PIPELINE_STAGE_PIPELINED_BITS \
5719 (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
5720 VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
5721 VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
5722 VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
5723 VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
5724 VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
5725 VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
5726 VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
5727 VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
5728 VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
5729 VK_PIPELINE_STAGE_TRANSFER_BIT | \
5730 VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
5731 VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
5732 VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
5734 void genX(CmdSetEvent
)(
5735 VkCommandBuffer commandBuffer
,
5737 VkPipelineStageFlags stageMask
)
5739 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5740 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5742 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5743 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5745 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5746 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5747 pc
.StallAtPixelScoreboard
= true;
5748 pc
.CommandStreamerStallEnable
= true;
5751 pc
.DestinationAddressType
= DAT_PPGTT
,
5752 pc
.PostSyncOperation
= WriteImmediateData
,
5753 pc
.Address
= (struct anv_address
) {
5754 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5757 pc
.ImmediateData
= VK_EVENT_SET
;
5761 void genX(CmdResetEvent
)(
5762 VkCommandBuffer commandBuffer
,
5764 VkPipelineStageFlags stageMask
)
5766 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5767 ANV_FROM_HANDLE(anv_event
, event
, _event
);
5769 cmd_buffer
->state
.pending_pipe_bits
|= ANV_PIPE_POST_SYNC_BIT
;
5770 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5772 anv_batch_emit(&cmd_buffer
->batch
, GENX(PIPE_CONTROL
), pc
) {
5773 if (stageMask
& ANV_PIPELINE_STAGE_PIPELINED_BITS
) {
5774 pc
.StallAtPixelScoreboard
= true;
5775 pc
.CommandStreamerStallEnable
= true;
5778 pc
.DestinationAddressType
= DAT_PPGTT
;
5779 pc
.PostSyncOperation
= WriteImmediateData
;
5780 pc
.Address
= (struct anv_address
) {
5781 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5784 pc
.ImmediateData
= VK_EVENT_RESET
;
5788 void genX(CmdWaitEvents
)(
5789 VkCommandBuffer commandBuffer
,
5790 uint32_t eventCount
,
5791 const VkEvent
* pEvents
,
5792 VkPipelineStageFlags srcStageMask
,
5793 VkPipelineStageFlags destStageMask
,
5794 uint32_t memoryBarrierCount
,
5795 const VkMemoryBarrier
* pMemoryBarriers
,
5796 uint32_t bufferMemoryBarrierCount
,
5797 const VkBufferMemoryBarrier
* pBufferMemoryBarriers
,
5798 uint32_t imageMemoryBarrierCount
,
5799 const VkImageMemoryBarrier
* pImageMemoryBarriers
)
5802 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5804 for (uint32_t i
= 0; i
< eventCount
; i
++) {
5805 ANV_FROM_HANDLE(anv_event
, event
, pEvents
[i
]);
5807 anv_batch_emit(&cmd_buffer
->batch
, GENX(MI_SEMAPHORE_WAIT
), sem
) {
5808 sem
.WaitMode
= PollingMode
,
5809 sem
.CompareOperation
= COMPARE_SAD_EQUAL_SDD
,
5810 sem
.SemaphoreDataDword
= VK_EVENT_SET
,
5811 sem
.SemaphoreAddress
= (struct anv_address
) {
5812 cmd_buffer
->device
->dynamic_state_pool
.block_pool
.bo
,
5818 anv_finishme("Implement events on gen7");
5821 genX(CmdPipelineBarrier
)(commandBuffer
, srcStageMask
, destStageMask
,
5822 false, /* byRegion */
5823 memoryBarrierCount
, pMemoryBarriers
,
5824 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
5825 imageMemoryBarrierCount
, pImageMemoryBarriers
);
5828 VkResult
genX(CmdSetPerformanceOverrideINTEL
)(
5829 VkCommandBuffer commandBuffer
,
5830 const VkPerformanceOverrideInfoINTEL
* pOverrideInfo
)
5832 ANV_FROM_HANDLE(anv_cmd_buffer
, cmd_buffer
, commandBuffer
);
5834 switch (pOverrideInfo
->type
) {
5835 case VK_PERFORMANCE_OVERRIDE_TYPE_NULL_HARDWARE_INTEL
: {
5839 anv_pack_struct(&dw
, GENX(CS_DEBUG_MODE2
),
5840 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5841 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5842 ._3DRenderingInstructionDisableMask
= true,
5843 .MediaInstructionDisableMask
= true);
5844 emit_lri(&cmd_buffer
->batch
, GENX(CS_DEBUG_MODE2_num
), dw
);
5846 anv_pack_struct(&dw
, GENX(INSTPM
),
5847 ._3DRenderingInstructionDisable
= pOverrideInfo
->enable
,
5848 .MediaInstructionDisable
= pOverrideInfo
->enable
,
5849 ._3DRenderingInstructionDisableMask
= true,
5850 .MediaInstructionDisableMask
= true);
5851 emit_lri(&cmd_buffer
->batch
, GENX(INSTPM_num
), dw
);
5856 case VK_PERFORMANCE_OVERRIDE_TYPE_FLUSH_GPU_CACHES_INTEL
:
5857 if (pOverrideInfo
->enable
) {
5858 /* FLUSH ALL THE THINGS! As requested by the MDAPI team. */
5859 cmd_buffer
->state
.pending_pipe_bits
|=
5860 ANV_PIPE_FLUSH_BITS
|
5861 ANV_PIPE_INVALIDATE_BITS
;
5862 genX(cmd_buffer_apply_pipe_flushes
)(cmd_buffer
);
5867 unreachable("Invalid override");
5873 VkResult
genX(CmdSetPerformanceStreamMarkerINTEL
)(
5874 VkCommandBuffer commandBuffer
,
5875 const VkPerformanceStreamMarkerInfoINTEL
* pMarkerInfo
)
5877 /* TODO: Waiting on the register to write, might depend on generation. */