src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35 #include "main/texformat.h"
  36
  37 #include "tnl/t_context.h"
  38 #include "tnl/t_vertex.h"
  39
  40 #include "intel_batchbuffer.h"
  41 #include "intel_tex.h"
  42 #include "intel_regions.h"
  43 #include "intel_tris.h"
  44 #include "intel_fbo.h"
  45 #include "intel_chipset.h"
  46
  47 #include "i915_reg.h"
  48 #include "i915_context.h"
  49
  50 #include "glapi/glapi.h"
  51
  52 static void
  53 i915_render_prevalidate(struct intel_context *intel)
  54 {
  55    struct i915_context *i915 = i915_context(&intel->ctx);
  56
  57    if (!intel->Fallback)
  58        i915ValidateFragmentProgram(i915);
  59 }
  60
  61 static void
  62 i915_render_start(struct intel_context *intel)
  63 {
  64 }
  65
  66
  67 static void
  68 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  69 {
  70    struct i915_context *i915 = i915_context(&intel->ctx);
  71    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  72
  73    st1 &= ~ST1_ENABLE;
  74
  75    switch (rprim) {
  76    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  77    case GL_TRIANGLES:
  78       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  79          st1 |= ST1_ENABLE;
  80       break;
  81    case GL_LINES:
  82    case GL_POINTS:
  83    default:
  84       break;
  85    }
  86
  87    i915->intel.reduced_primitive = rprim;
  88
  89    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  90       INTEL_FIREVERTICES(intel);
  91
  92       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  93       i915->state.Stipple[I915_STPREG_ST1] = st1;
  94    }
  95 }
  96
  97
  98 /* Pull apart the vertex format registers and figure out how large a
  99  * vertex is supposed to be.
 100  */
 101 static GLboolean
 102 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
 103 {
 104    struct i915_context *i915 = i915_context(&intel->ctx);
 105    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
 106    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 107    int i, sz = 0;
 108
 109    switch (lis4 & S4_VFMT_XYZW_MASK) {
 110    case S4_VFMT_XY:
 111       sz = 2;
 112       break;
 113    case S4_VFMT_XYZ:
 114       sz = 3;
 115       break;
 116    case S4_VFMT_XYW:
 117       sz = 3;
 118       break;
 119    case S4_VFMT_XYZW:
 120       sz = 4;
 121       break;
 122    default:
 123       fprintf(stderr, "no xyzw specified\n");
 124       return 0;
 125    }
 126
 127    if (lis4 & S4_VFMT_SPEC_FOG)
 128       sz++;
 129    if (lis4 & S4_VFMT_COLOR)
 130       sz++;
 131    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 132       sz++;
 133    if (lis4 & S4_VFMT_POINT_WIDTH)
 134       sz++;
 135    if (lis4 & S4_VFMT_FOG_PARAM)
 136       sz++;
 137
 138    for (i = 0; i < 8; i++) {
 139       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 140       case TEXCOORDFMT_2D:
 141          sz += 2;
 142          break;
 143       case TEXCOORDFMT_3D:
 144          sz += 3;
 145          break;
 146       case TEXCOORDFMT_4D:
 147          sz += 4;
 148          break;
 149       case TEXCOORDFMT_1D:
 150          sz += 1;
 151          break;
 152       case TEXCOORDFMT_2D_16:
 153          sz += 1;
 154          break;
 155       case TEXCOORDFMT_4D_16:
 156          sz += 2;
 157          break;
 158       case TEXCOORDFMT_NOT_PRESENT:
 159          break;
 160       default:
 161          fprintf(stderr, "bad texcoord fmt %d\n", i);
 162          return GL_FALSE;
 163       }
 164       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 165    }
 166
 167    if (sz != expected)
 168       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 169
 170    return sz == expected;
 171 }
 172
 173
 174 static void
 175 i915_emit_invarient_state(struct intel_context *intel)
 176 {
 177    BATCH_LOCALS;
 178
 179    BEGIN_BATCH(20, IGNORE_CLIPRECTS);
 180
 181    OUT_BATCH(_3DSTATE_AA_CMD |
 182              AA_LINE_ECAAR_WIDTH_ENABLE |
 183              AA_LINE_ECAAR_WIDTH_1_0 |
 184              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 185
 186    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 187    OUT_BATCH(0);
 188
 189    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 190    OUT_BATCH(0);
 191
 192    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 193    OUT_BATCH(0);
 194
 195    /* Don't support texture crossbar yet */
 196    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 197              CSB_TCB(0, 0) |
 198              CSB_TCB(1, 1) |
 199              CSB_TCB(2, 2) |
 200              CSB_TCB(3, 3) |
 201              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 202
 203    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 204              ENABLE_POINT_RASTER_RULE |
 205              OGL_POINT_RASTER_RULE |
 206              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 207              ENABLE_TRI_FAN_PROVOKE_VRTX |
 208              LINE_STRIP_PROVOKE_VRTX(1) |
 209              TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
 210
 211    /* Need to initialize this to zero.
 212     */
 213    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 214    OUT_BATCH(0);
 215
 216    /* XXX: Use this */
 217    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 218
 219    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 220    OUT_BATCH(0);
 221    OUT_BATCH(0);
 222
 223    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 224
 225    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 226    OUT_BATCH(0);
 227
 228
 229    /* Don't support twosided stencil yet */
 230    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 231    OUT_BATCH(0);
 232
 233    ADVANCE_BATCH();
 234 }
 235
 236
 237 #define emit(intel, state, size )                    \
 238    intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 239
 240 static GLuint
 241 get_dirty(struct i915_hw_state *state)
 242 {
 243    GLuint dirty;
 244
 245    /* Workaround the multitex hang - if one texture unit state is
 246     * modified, emit all texture units.
 247     */
 248    dirty = state->active & ~state->emitted;
 249    if (dirty & I915_UPLOAD_TEX_ALL)
 250       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 251    dirty = state->active & ~state->emitted;
 252    return dirty;
 253 }
 254
 255
 256 static GLuint
 257 get_state_size(struct i915_hw_state *state)
 258 {
 259    GLuint dirty = get_dirty(state);
 260    GLuint i;
 261    GLuint sz = 0;
 262
 263    if (dirty & I915_UPLOAD_INVARIENT)
 264       sz += 30 * 4;
 265
 266    if (dirty & I915_UPLOAD_CTX)
 267       sz += sizeof(state->Ctx);
 268
 269    if (dirty & I915_UPLOAD_BUFFERS)
 270       sz += sizeof(state->Buffer);
 271
 272    if (dirty & I915_UPLOAD_STIPPLE)
 273       sz += sizeof(state->Stipple);
 274
 275    if (dirty & I915_UPLOAD_FOG)
 276       sz += sizeof(state->Fog);
 277
 278    if (dirty & I915_UPLOAD_TEX_ALL) {
 279       int nr = 0;
 280       for (i = 0; i < I915_TEX_UNITS; i++)
 281          if (dirty & I915_UPLOAD_TEX(i))
 282             nr++;
 283
 284       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 285    }
 286
 287    if (dirty & I915_UPLOAD_CONSTANTS)
 288       sz += state->ConstantSize * sizeof(GLuint);
 289
 290    if (dirty & I915_UPLOAD_PROGRAM)
 291       sz += state->ProgramSize * sizeof(GLuint);
 292
 293    return sz;
 294 }
 295
 296 /* Push the state into the sarea and/or texture memory.
 297  */
 298 static void
 299 i915_emit_state(struct intel_context *intel)
 300 {
 301    struct i915_context *i915 = i915_context(&intel->ctx);
 302    struct i915_hw_state *state = i915->current;
 303    int i, count, aper_count;
 304    GLuint dirty;
 305    dri_bo *aper_array[3 + I915_TEX_UNITS];
 306    GET_CURRENT_CONTEXT(ctx);
 307    BATCH_LOCALS;
 308
 309    /* We don't hold the lock at this point, so want to make sure that
 310     * there won't be a buffer wrap between the state emits and the primitive
 311     * emit header.
 312     *
 313     * It might be better to talk about explicit places where
 314     * scheduling is allowed, rather than assume that it is whenever a
 315     * batchbuffer fills up.
 316     *
 317     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
 318     * will be emitted under.
 319     */
 320    intel_batchbuffer_require_space(intel->batch,
 321                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 322                                    LOOP_CLIPRECTS);
 323    count = 0;
 324  again:
 325    aper_count = 0;
 326    dirty = get_dirty(state);
 327
 328    aper_array[aper_count++] = intel->batch->buf;
 329    if (dirty & I915_UPLOAD_BUFFERS) {
 330       aper_array[aper_count++] = state->draw_region->buffer;
 331       if (state->depth_region)
 332          aper_array[aper_count++] = state->depth_region->buffer;
 333    }
 334
 335    if (dirty & I915_UPLOAD_TEX_ALL) {
 336       for (i = 0; i < I915_TEX_UNITS; i++) {
 337          if (dirty & I915_UPLOAD_TEX(i)) {
 338             if (state->tex_buffer[i]) {
 339                aper_array[aper_count++] = state->tex_buffer[i];
 340             }
 341          }
 342       }
 343    }
 344
 345    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 346        if (count == 0) {
 347            count++;
 348            intel_batchbuffer_flush(intel->batch);
 349            goto again;
 350        } else {
 351            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 352            assert(0);
 353        }
 354    }
 355
 356    /* work out list of buffers to emit */
 357
 358    /* Do this here as we may have flushed the batchbuffer above,
 359     * causing more state to be dirty!
 360     */
 361    dirty = get_dirty(state);
 362    state->emitted |= dirty;
 363    assert(get_dirty(state) == 0);
 364
 365    if (INTEL_DEBUG & DEBUG_STATE)
 366       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 367
 368    if (dirty & I915_UPLOAD_INVARIENT) {
 369       if (INTEL_DEBUG & DEBUG_STATE)
 370          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 371       i915_emit_invarient_state(intel);
 372    }
 373
 374    if (dirty & I915_UPLOAD_CTX) {
 375       if (INTEL_DEBUG & DEBUG_STATE)
 376          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 377
 378       emit(intel, state->Ctx, sizeof(state->Ctx));
 379    }
 380
 381    if (dirty & I915_UPLOAD_BUFFERS) {
 382       GLuint count = 9;
 383
 384       if (INTEL_DEBUG & DEBUG_STATE)
 385          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 386
 387       if (state->depth_region)
 388           count += 3;
 389
 390       if (intel->constant_cliprect)
 391           count += 6;
 392
 393       BEGIN_BATCH(count, IGNORE_CLIPRECTS);
 394       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 395       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 396       OUT_RELOC(state->draw_region->buffer,
 397                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 398                 state->draw_region->draw_offset);
 399
 400       if (state->depth_region) {
 401          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 402          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 403          OUT_RELOC(state->depth_region->buffer,
 404                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 405                    state->depth_region->draw_offset);
 406       }
 407
 408       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 409       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 410       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 411       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 412       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 413       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 414
 415       if (intel->constant_cliprect) {
 416          assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
 417          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 418          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 419          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 420          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 421          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 422          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 423       }
 424
 425       ADVANCE_BATCH();
 426    }
 427
 428    if (dirty & I915_UPLOAD_STIPPLE) {
 429       if (INTEL_DEBUG & DEBUG_STATE)
 430          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 431       emit(intel, state->Stipple, sizeof(state->Stipple));
 432    }
 433
 434    if (dirty & I915_UPLOAD_FOG) {
 435       if (INTEL_DEBUG & DEBUG_STATE)
 436          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 437       emit(intel, state->Fog, sizeof(state->Fog));
 438    }
 439
 440    /* Combine all the dirty texture state into a single command to
 441     * avoid lockups on I915 hardware.
 442     */
 443    if (dirty & I915_UPLOAD_TEX_ALL) {
 444       int nr = 0;
 445
 446       for (i = 0; i < I915_TEX_UNITS; i++)
 447          if (dirty & I915_UPLOAD_TEX(i))
 448             nr++;
 449
 450       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 451       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 452       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 453       for (i = 0; i < I915_TEX_UNITS; i++)
 454          if (dirty & I915_UPLOAD_TEX(i)) {
 455
 456             if (state->tex_buffer[i]) {
 457                OUT_RELOC(state->tex_buffer[i],
 458                          I915_GEM_DOMAIN_SAMPLER, 0,
 459                          state->tex_offset[i]);
 460             }
 461             else if (state == &i915->meta) {
 462                assert(i == 0);
 463                OUT_BATCH(0);
 464             }
 465             else {
 466                OUT_BATCH(state->tex_offset[i]);
 467             }
 468
 469             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 470             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 471          }
 472       ADVANCE_BATCH();
 473
 474       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 475       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 476       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 477       for (i = 0; i < I915_TEX_UNITS; i++)
 478          if (dirty & I915_UPLOAD_TEX(i)) {
 479             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 480             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 481             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 482          }
 483       ADVANCE_BATCH();
 484    }
 485
 486    if (dirty & I915_UPLOAD_CONSTANTS) {
 487       if (INTEL_DEBUG & DEBUG_STATE)
 488          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 489       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 490    }
 491
 492    if (dirty & I915_UPLOAD_PROGRAM) {
 493       if (state->ProgramSize) {
 494          if (INTEL_DEBUG & DEBUG_STATE)
 495             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 496
 497          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 498
 499          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 500          if (INTEL_DEBUG & DEBUG_STATE)
 501             i915_disassemble_program(state->Program, state->ProgramSize);
 502       }
 503    }
 504
 505    intel->batch->dirty_state &= ~dirty;
 506    assert(get_dirty(state) == 0);
 507    assert((intel->batch->dirty_state & (1<<1)) == 0);
 508 }
 509
 510 static void
 511 i915_destroy_context(struct intel_context *intel)
 512 {
 513    GLuint i;
 514    struct i915_context *i915 = i915_context(&intel->ctx);
 515
 516    intel_region_release(&i915->state.draw_region);
 517    intel_region_release(&i915->state.depth_region);
 518    intel_region_release(&i915->meta.draw_region);
 519    intel_region_release(&i915->meta.depth_region);
 520    intel_region_release(&i915->initial.draw_region);
 521    intel_region_release(&i915->initial.depth_region);
 522
 523    for (i = 0; i < I915_TEX_UNITS; i++) {
 524       if (i915->state.tex_buffer[i] != NULL) {
 525          dri_bo_unreference(i915->state.tex_buffer[i]);
 526          i915->state.tex_buffer[i] = NULL;
 527       }
 528    }
 529
 530    _tnl_free_vertices(&intel->ctx);
 531 }
 532
 533 void
 534 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 535                              uint32_t buffer_id)
 536 {
 537    state[0] = _3DSTATE_BUF_INFO_CMD;
 538    state[1] = buffer_id;
 539
 540    if (region != NULL) {
 541       state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
 542
 543       if (region->tiling != I915_TILING_NONE) {
 544          state[1] |= BUF_3D_TILED_SURFACE;
 545          if (region->tiling == I915_TILING_Y)
 546             state[1] |= BUF_3D_TILE_WALK_Y;
 547       }
 548    }
 549 }
 550
 551 /**
 552  * Set the drawing regions for the color and depth/stencil buffers.
 553  * This involves setting the pitch, cpp and buffer ID/location.
 554  * Also set pixel format for color and Z rendering
 555  * Used for setting both regular and meta state.
 556  */
 557 void
 558 i915_state_draw_region(struct intel_context *intel,
 559                        struct i915_hw_state *state,
 560                        struct intel_region *color_region,
 561                        struct intel_region *depth_region)
 562 {
 563    struct i915_context *i915 = i915_context(&intel->ctx);
 564    GLcontext *ctx = &intel->ctx;
 565    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 566    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 567    GLuint value;
 568
 569    ASSERT(state == &i915->state || state == &i915->meta);
 570
 571    if (state->draw_region != color_region) {
 572       intel_region_release(&state->draw_region);
 573       intel_region_reference(&state->draw_region, color_region);
 574    }
 575    if (state->depth_region != depth_region) {
 576       intel_region_release(&state->depth_region);
 577       intel_region_reference(&state->depth_region, depth_region);
 578    }
 579
 580    /*
 581     * Set stride/cpp values
 582     */
 583    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
 584                                 color_region, BUF_3D_ID_COLOR_BACK);
 585
 586    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
 587                                 depth_region, BUF_3D_ID_DEPTH);
 588
 589    /*
 590     * Compute/set I915_DESTREG_DV1 value
 591     */
 592    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 593             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 594             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 595    if (irb != NULL) {
 596       switch (irb->texformat->MesaFormat) {
 597       case MESA_FORMAT_ARGB8888:
 598          value |= DV_PF_8888;
 599          break;
 600       case MESA_FORMAT_RGB565:
 601          value |= DV_PF_565 | DITHER_FULL_ALWAYS;
 602          break;
 603       case MESA_FORMAT_ARGB1555:
 604          value |= DV_PF_1555 | DITHER_FULL_ALWAYS;
 605          break;
 606       case MESA_FORMAT_ARGB4444:
 607          value |= DV_PF_4444 | DITHER_FULL_ALWAYS;
 608          break;
 609       default:
 610          _mesa_problem(ctx, "Bad renderbuffer format: %d\n",
 611                        irb->texformat->MesaFormat);
 612       }
 613    }
 614
 615    /* This isn't quite safe, thus being hidden behind an option.  When changing
 616     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
 617     * can only be set when a depth buffer is already defined.
 618     */
 619    if (IS_945(intel->intelScreen->deviceID) && intel->use_early_z &&
 620        depth_region->tiling != I915_TILING_NONE)
 621       value |= CLASSIC_EARLY_DEPTH;
 622
 623    if (depth_region && depth_region->cpp == 4) {
 624       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 625    }
 626    else {
 627       value |= DEPTH_FRMT_16_FIXED;
 628    }
 629    state->Buffer[I915_DESTREG_DV1] = value;
 630
 631    if (intel->constant_cliprect) {
 632       state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
 633       state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
 634       state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
 635       state->Buffer[I915_DESTREG_DRAWRECT3] =
 636          (ctx->DrawBuffer->Width & 0xffff) |
 637          (ctx->DrawBuffer->Height << 16);
 638       state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
 639       state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
 640    } else {
 641       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 642       state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
 643       state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
 644       state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
 645       state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
 646       state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
 647    }
 648
 649    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 650 }
 651
 652
 653 static void
 654 i915_set_draw_region(struct intel_context *intel,
 655                      struct intel_region *color_regions[],
 656                      struct intel_region *depth_region,
 657                      GLuint num_regions)
 658 {
 659    struct i915_context *i915 = i915_context(&intel->ctx);
 660    i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
 661 }
 662
 663
 664
 665 static void
 666 i915_new_batch(struct intel_context *intel)
 667 {
 668    struct i915_context *i915 = i915_context(&intel->ctx);
 669
 670    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 671     * Using hardware contexts would be an alternative, but they have some
 672     * difficulties associated with them (physical address requirements).
 673     */
 674    i915->state.emitted = 0;
 675
 676    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 677    assert(!intel->no_batch_wrap);
 678 }
 679
 680 static GLuint
 681 i915_flush_cmd(void)
 682 {
 683    return MI_FLUSH | FLUSH_MAP_CACHE;
 684 }
 685
 686 static void
 687 i915_assert_not_dirty( struct intel_context *intel )
 688 {
 689    struct i915_context *i915 = i915_context(&intel->ctx);
 690    struct i915_hw_state *state = i915->current;
 691    GLuint dirty = get_dirty(state);
 692    assert(!dirty);
 693 }
 694
 695 static void
 696 i915_note_unlock( struct intel_context *intel )
 697 {
 698     /* nothing */
 699 }
 700
 701
 702 void
 703 i915InitVtbl(struct i915_context *i915)
 704 {
 705    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 706    i915->intel.vtbl.destroy = i915_destroy_context;
 707    i915->intel.vtbl.emit_state = i915_emit_state;
 708    i915->intel.vtbl.new_batch = i915_new_batch;
 709    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 710    i915->intel.vtbl.render_start = i915_render_start;
 711    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 712    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 713    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 714    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
 715    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 716    i915->intel.vtbl.note_unlock = i915_note_unlock;
 717    i915->intel.vtbl.finish_batch = intel_finish_vb;
 718 }