src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_tex.h"
  41 #include "intel_regions.h"
  42 #include "intel_tris.h"
  43
  44 #include "i915_reg.h"
  45 #include "i915_context.h"
  46
  47 #include "glapi/glapi.h"
  48
  49 static void
  50 i915_render_prevalidate(struct intel_context *intel)
  51 {
  52    struct i915_context *i915 = i915_context(&intel->ctx);
  53
  54    if (!intel->Fallback)
  55        i915ValidateFragmentProgram(i915);
  56 }
  57
  58 static void
  59 i915_render_start(struct intel_context *intel)
  60 {
  61 }
  62
  63
  64 static void
  65 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  66 {
  67    struct i915_context *i915 = i915_context(&intel->ctx);
  68    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  69
  70    st1 &= ~ST1_ENABLE;
  71
  72    switch (rprim) {
  73    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  74    case GL_TRIANGLES:
  75       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  76          st1 |= ST1_ENABLE;
  77       break;
  78    case GL_LINES:
  79    case GL_POINTS:
  80    default:
  81       break;
  82    }
  83
  84    i915->intel.reduced_primitive = rprim;
  85
  86    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  87       INTEL_FIREVERTICES(intel);
  88
  89       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  90       i915->state.Stipple[I915_STPREG_ST1] = st1;
  91    }
  92 }
  93
  94
  95 /* Pull apart the vertex format registers and figure out how large a
  96  * vertex is supposed to be.
  97  */
  98 static GLboolean
  99 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
 100 {
 101    struct i915_context *i915 = i915_context(&intel->ctx);
 102    int lis2 = i915->current->Ctx[I915_CTXREG_LIS2];
 103    int lis4 = i915->current->Ctx[I915_CTXREG_LIS4];
 104    int i, sz = 0;
 105
 106    switch (lis4 & S4_VFMT_XYZW_MASK) {
 107    case S4_VFMT_XY:
 108       sz = 2;
 109       break;
 110    case S4_VFMT_XYZ:
 111       sz = 3;
 112       break;
 113    case S4_VFMT_XYW:
 114       sz = 3;
 115       break;
 116    case S4_VFMT_XYZW:
 117       sz = 4;
 118       break;
 119    default:
 120       fprintf(stderr, "no xyzw specified\n");
 121       return 0;
 122    }
 123
 124    if (lis4 & S4_VFMT_SPEC_FOG)
 125       sz++;
 126    if (lis4 & S4_VFMT_COLOR)
 127       sz++;
 128    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 129       sz++;
 130    if (lis4 & S4_VFMT_POINT_WIDTH)
 131       sz++;
 132    if (lis4 & S4_VFMT_FOG_PARAM)
 133       sz++;
 134
 135    for (i = 0; i < 8; i++) {
 136       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 137       case TEXCOORDFMT_2D:
 138          sz += 2;
 139          break;
 140       case TEXCOORDFMT_3D:
 141          sz += 3;
 142          break;
 143       case TEXCOORDFMT_4D:
 144          sz += 4;
 145          break;
 146       case TEXCOORDFMT_1D:
 147          sz += 1;
 148          break;
 149       case TEXCOORDFMT_2D_16:
 150          sz += 1;
 151          break;
 152       case TEXCOORDFMT_4D_16:
 153          sz += 2;
 154          break;
 155       case TEXCOORDFMT_NOT_PRESENT:
 156          break;
 157       default:
 158          fprintf(stderr, "bad texcoord fmt %d\n", i);
 159          return GL_FALSE;
 160       }
 161       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 162    }
 163
 164    if (sz != expected)
 165       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 166
 167    return sz == expected;
 168 }
 169
 170
 171 static void
 172 i915_emit_invarient_state(struct intel_context *intel)
 173 {
 174    BATCH_LOCALS;
 175
 176    BEGIN_BATCH(200, IGNORE_CLIPRECTS);
 177
 178    OUT_BATCH(_3DSTATE_AA_CMD |
 179              AA_LINE_ECAAR_WIDTH_ENABLE |
 180              AA_LINE_ECAAR_WIDTH_1_0 |
 181              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 182
 183    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 184    OUT_BATCH(0);
 185
 186    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 187    OUT_BATCH(0);
 188
 189    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 190    OUT_BATCH(0);
 191
 192    /* Don't support texture crossbar yet */
 193    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 194              CSB_TCB(0, 0) |
 195              CSB_TCB(1, 1) |
 196              CSB_TCB(2, 2) |
 197              CSB_TCB(3, 3) |
 198              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 199
 200    OUT_BATCH(_3DSTATE_RASTER_RULES_CMD |
 201              ENABLE_POINT_RASTER_RULE |
 202              OGL_POINT_RASTER_RULE |
 203              ENABLE_LINE_STRIP_PROVOKE_VRTX |
 204              ENABLE_TRI_FAN_PROVOKE_VRTX |
 205              LINE_STRIP_PROVOKE_VRTX(1) |
 206              TRI_FAN_PROVOKE_VRTX(2) | ENABLE_TEXKILL_3D_4D | TEXKILL_4D);
 207
 208    /* Need to initialize this to zero.
 209     */
 210    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 211    OUT_BATCH(0);
 212
 213    /* XXX: Use this */
 214    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 215
 216    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 217    OUT_BATCH(0);
 218    OUT_BATCH(0);
 219
 220    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 221
 222    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 223    OUT_BATCH(0);
 224
 225
 226    /* Don't support twosided stencil yet */
 227    OUT_BATCH(_3DSTATE_BACKFACE_STENCIL_OPS | BFO_ENABLE_STENCIL_TWO_SIDE | 0);
 228    OUT_BATCH(0);
 229
 230    ADVANCE_BATCH();
 231 }
 232
 233
 234 #define emit(intel, state, size )                    \
 235    intel_batchbuffer_data(intel->batch, state, size, IGNORE_CLIPRECTS )
 236
 237 static GLuint
 238 get_dirty(struct i915_hw_state *state)
 239 {
 240    GLuint dirty;
 241
 242    /* Workaround the multitex hang - if one texture unit state is
 243     * modified, emit all texture units.
 244     */
 245    dirty = state->active & ~state->emitted;
 246    if (dirty & I915_UPLOAD_TEX_ALL)
 247       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 248    dirty = state->active & ~state->emitted;
 249    return dirty;
 250 }
 251
 252
 253 static GLuint
 254 get_state_size(struct i915_hw_state *state)
 255 {
 256    GLuint dirty = get_dirty(state);
 257    GLuint i;
 258    GLuint sz = 0;
 259
 260    if (dirty & I915_UPLOAD_INVARIENT)
 261       sz += 30 * 4;
 262
 263    if (dirty & I915_UPLOAD_CTX)
 264       sz += sizeof(state->Ctx);
 265
 266    if (dirty & I915_UPLOAD_BUFFERS)
 267       sz += sizeof(state->Buffer);
 268
 269    if (dirty & I915_UPLOAD_STIPPLE)
 270       sz += sizeof(state->Stipple);
 271
 272    if (dirty & I915_UPLOAD_FOG)
 273       sz += sizeof(state->Fog);
 274
 275    if (dirty & I915_UPLOAD_TEX_ALL) {
 276       int nr = 0;
 277       for (i = 0; i < I915_TEX_UNITS; i++)
 278          if (dirty & I915_UPLOAD_TEX(i))
 279             nr++;
 280
 281       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 282    }
 283
 284    if (dirty & I915_UPLOAD_CONSTANTS)
 285       sz += state->ConstantSize * sizeof(GLuint);
 286
 287    if (dirty & I915_UPLOAD_PROGRAM)
 288       sz += state->ProgramSize * sizeof(GLuint);
 289
 290    return sz;
 291 }
 292
 293 /* Push the state into the sarea and/or texture memory.
 294  */
 295 static void
 296 i915_emit_state(struct intel_context *intel)
 297 {
 298    struct i915_context *i915 = i915_context(&intel->ctx);
 299    struct i915_hw_state *state = i915->current;
 300    int i, count, aper_count;
 301    GLuint dirty;
 302    dri_bo *aper_array[3 + I915_TEX_UNITS];
 303    GET_CURRENT_CONTEXT(ctx);
 304    BATCH_LOCALS;
 305
 306    /* We don't hold the lock at this point, so want to make sure that
 307     * there won't be a buffer wrap between the state emits and the primitive
 308     * emit header.
 309     *
 310     * It might be better to talk about explicit places where
 311     * scheduling is allowed, rather than assume that it is whenever a
 312     * batchbuffer fills up.
 313     *
 314     * Set the space as LOOP_CLIPRECTS now, since that's what our primitives
 315     * will be emitted under.
 316     */
 317    intel_batchbuffer_require_space(intel->batch,
 318                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 319                                    LOOP_CLIPRECTS);
 320    count = 0;
 321  again:
 322    aper_count = 0;
 323    dirty = get_dirty(state);
 324
 325    aper_array[aper_count++] = intel->batch->buf;
 326    if (dirty & I915_UPLOAD_BUFFERS) {
 327       aper_array[aper_count++] = state->draw_region->buffer;
 328       if (state->depth_region)
 329          aper_array[aper_count++] = state->depth_region->buffer;
 330    }
 331
 332    if (dirty & I915_UPLOAD_TEX_ALL) {
 333       for (i = 0; i < I915_TEX_UNITS; i++) {
 334          if (dirty & I915_UPLOAD_TEX(i)) {
 335             if (state->tex_buffer[i]) {
 336                aper_array[aper_count++] = state->tex_buffer[i];
 337             }
 338          }
 339       }
 340    }
 341
 342    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 343        if (count == 0) {
 344            count++;
 345            intel_batchbuffer_flush(intel->batch);
 346            goto again;
 347        } else {
 348            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 349            assert(0);
 350        }
 351    }
 352
 353    /* work out list of buffers to emit */
 354
 355    /* Do this here as we may have flushed the batchbuffer above,
 356     * causing more state to be dirty!
 357     */
 358    dirty = get_dirty(state);
 359    state->emitted |= dirty;
 360    assert(get_dirty(state) == 0);
 361
 362    if (INTEL_DEBUG & DEBUG_STATE)
 363       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 364
 365    if (dirty & I915_UPLOAD_INVARIENT) {
 366       if (INTEL_DEBUG & DEBUG_STATE)
 367          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 368       i915_emit_invarient_state(intel);
 369    }
 370
 371    if (dirty & I915_UPLOAD_CTX) {
 372       if (INTEL_DEBUG & DEBUG_STATE)
 373          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 374
 375       emit(intel, state->Ctx, sizeof(state->Ctx));
 376    }
 377
 378    if (dirty & I915_UPLOAD_BUFFERS) {
 379       if (INTEL_DEBUG & DEBUG_STATE)
 380          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 381       BEGIN_BATCH(I915_DEST_SETUP_SIZE + 2, IGNORE_CLIPRECTS);
 382       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 383       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 384       OUT_RELOC(state->draw_region->buffer,
 385                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 386                 state->draw_region->draw_offset);
 387
 388       if (state->depth_region) {
 389          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 390          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 391          OUT_RELOC(state->depth_region->buffer,
 392                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 393                    state->depth_region->draw_offset);
 394       }
 395
 396       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 397       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 398       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 399       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 400       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 401       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 402
 403       if (intel->constant_cliprect) {
 404          assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP);
 405          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 406          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 407          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 408          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 409          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 410          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 411       }
 412
 413       ADVANCE_BATCH();
 414    }
 415
 416    if (dirty & I915_UPLOAD_STIPPLE) {
 417       if (INTEL_DEBUG & DEBUG_STATE)
 418          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 419       emit(intel, state->Stipple, sizeof(state->Stipple));
 420    }
 421
 422    if (dirty & I915_UPLOAD_FOG) {
 423       if (INTEL_DEBUG & DEBUG_STATE)
 424          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 425       emit(intel, state->Fog, sizeof(state->Fog));
 426    }
 427
 428    /* Combine all the dirty texture state into a single command to
 429     * avoid lockups on I915 hardware.
 430     */
 431    if (dirty & I915_UPLOAD_TEX_ALL) {
 432       int nr = 0;
 433
 434       for (i = 0; i < I915_TEX_UNITS; i++)
 435          if (dirty & I915_UPLOAD_TEX(i))
 436             nr++;
 437
 438       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 439       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 440       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 441       for (i = 0; i < I915_TEX_UNITS; i++)
 442          if (dirty & I915_UPLOAD_TEX(i)) {
 443
 444             if (state->tex_buffer[i]) {
 445                OUT_RELOC(state->tex_buffer[i],
 446                          I915_GEM_DOMAIN_SAMPLER, 0,
 447                          state->tex_offset[i]);
 448             }
 449             else if (state == &i915->meta) {
 450                assert(i == 0);
 451                OUT_BATCH(0);
 452             }
 453             else {
 454                OUT_BATCH(state->tex_offset[i]);
 455             }
 456
 457             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 458             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 459          }
 460       ADVANCE_BATCH();
 461
 462       BEGIN_BATCH(2 + nr * 3, IGNORE_CLIPRECTS);
 463       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 464       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 465       for (i = 0; i < I915_TEX_UNITS; i++)
 466          if (dirty & I915_UPLOAD_TEX(i)) {
 467             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 468             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 469             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 470          }
 471       ADVANCE_BATCH();
 472    }
 473
 474    if (dirty & I915_UPLOAD_CONSTANTS) {
 475       if (INTEL_DEBUG & DEBUG_STATE)
 476          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 477       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 478    }
 479
 480    if (dirty & I915_UPLOAD_PROGRAM) {
 481       if (state->ProgramSize) {
 482          if (INTEL_DEBUG & DEBUG_STATE)
 483             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 484
 485          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 486
 487          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 488          if (INTEL_DEBUG & DEBUG_STATE)
 489             i915_disassemble_program(state->Program, state->ProgramSize);
 490       }
 491    }
 492
 493    intel->batch->dirty_state &= ~dirty;
 494    assert(get_dirty(state) == 0);
 495    assert((intel->batch->dirty_state & (1<<1)) == 0);
 496 }
 497
 498 static void
 499 i915_destroy_context(struct intel_context *intel)
 500 {
 501    GLuint i;
 502    struct i915_context *i915 = i915_context(&intel->ctx);
 503
 504    intel_region_release(&i915->state.draw_region);
 505    intel_region_release(&i915->state.depth_region);
 506    intel_region_release(&i915->meta.draw_region);
 507    intel_region_release(&i915->meta.depth_region);
 508    intel_region_release(&i915->initial.draw_region);
 509    intel_region_release(&i915->initial.depth_region);
 510
 511    for (i = 0; i < I915_TEX_UNITS; i++) {
 512       if (i915->state.tex_buffer[i] != NULL) {
 513          dri_bo_unreference(i915->state.tex_buffer[i]);
 514          i915->state.tex_buffer[i] = NULL;
 515       }
 516    }
 517
 518    _tnl_free_vertices(&intel->ctx);
 519 }
 520
 521
 522 /**
 523  * Set the drawing regions for the color and depth/stencil buffers.
 524  * This involves setting the pitch, cpp and buffer ID/location.
 525  * Also set pixel format for color and Z rendering
 526  * Used for setting both regular and meta state.
 527  */
 528 void
 529 i915_state_draw_region(struct intel_context *intel,
 530                        struct i915_hw_state *state,
 531                        struct intel_region *color_region,
 532                        struct intel_region *depth_region)
 533 {
 534    struct i915_context *i915 = i915_context(&intel->ctx);
 535    GLcontext *ctx = &intel->ctx;
 536    GLuint value;
 537
 538    ASSERT(state == &i915->state || state == &i915->meta);
 539
 540    if (state->draw_region != color_region) {
 541       intel_region_release(&state->draw_region);
 542       intel_region_reference(&state->draw_region, color_region);
 543    }
 544    if (state->depth_region != depth_region) {
 545       intel_region_release(&state->depth_region);
 546       intel_region_reference(&state->depth_region, depth_region);
 547    }
 548
 549    /*
 550     * Set stride/cpp values
 551     */
 552    if (color_region) {
 553       state->Buffer[I915_DESTREG_CBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 554       state->Buffer[I915_DESTREG_CBUFADDR1] =
 555          (BUF_3D_ID_COLOR_BACK |
 556           BUF_3D_PITCH(color_region->pitch * color_region->cpp) |
 557           BUF_3D_USE_FENCE);
 558    }
 559
 560    if (depth_region) {
 561       state->Buffer[I915_DESTREG_DBUFADDR0] = _3DSTATE_BUF_INFO_CMD;
 562       state->Buffer[I915_DESTREG_DBUFADDR1] =
 563          (BUF_3D_ID_DEPTH |
 564           BUF_3D_PITCH(depth_region->pitch * depth_region->cpp) |
 565           BUF_3D_USE_FENCE);
 566    }
 567
 568    /*
 569     * Compute/set I915_DESTREG_DV1 value
 570     */
 571    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 572             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 573             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 574    if (color_region && color_region->cpp == 4) {
 575       value |= DV_PF_8888;
 576    }
 577    else {
 578       value |= (DITHER_FULL_ALWAYS | DV_PF_565);
 579    }
 580    if (depth_region && depth_region->cpp == 4) {
 581       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 582    }
 583    else {
 584       value |= DEPTH_FRMT_16_FIXED;
 585    }
 586    state->Buffer[I915_DESTREG_DV1] = value;
 587
 588    if (intel->constant_cliprect) {
 589       state->Buffer[I915_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
 590       state->Buffer[I915_DESTREG_DRAWRECT1] = 0;
 591       state->Buffer[I915_DESTREG_DRAWRECT2] = 0; /* xmin, ymin */
 592       state->Buffer[I915_DESTREG_DRAWRECT3] =
 593          (ctx->DrawBuffer->Width & 0xffff) |
 594          (ctx->DrawBuffer->Height << 16);
 595       state->Buffer[I915_DESTREG_DRAWRECT4] = 0; /* xoff, yoff */
 596       state->Buffer[I915_DESTREG_DRAWRECT5] = 0;
 597    } else {
 598       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 599       state->Buffer[I915_DESTREG_DRAWRECT1] = MI_NOOP;
 600       state->Buffer[I915_DESTREG_DRAWRECT2] = MI_NOOP;
 601       state->Buffer[I915_DESTREG_DRAWRECT3] = MI_NOOP;
 602       state->Buffer[I915_DESTREG_DRAWRECT4] = MI_NOOP;
 603       state->Buffer[I915_DESTREG_DRAWRECT5] = MI_NOOP;
 604    }
 605
 606    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 607 }
 608
 609
 610 static void
 611 i915_set_draw_region(struct intel_context *intel,
 612                      struct intel_region *color_regions[],
 613                      struct intel_region *depth_region,
 614                      GLuint num_regions)
 615 {
 616    struct i915_context *i915 = i915_context(&intel->ctx);
 617    i915_state_draw_region(intel, &i915->state, color_regions[0], depth_region);
 618 }
 619
 620
 621
 622 static void
 623 i915_new_batch(struct intel_context *intel)
 624 {
 625    struct i915_context *i915 = i915_context(&intel->ctx);
 626
 627    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 628     * Using hardware contexts would be an alternative, but they have some
 629     * difficulties associated with them (physical address requirements).
 630     */
 631    i915->state.emitted = 0;
 632
 633    /* Check that we didn't just wrap our batchbuffer at a bad time. */
 634    assert(!intel->no_batch_wrap);
 635 }
 636
 637 static GLuint
 638 i915_flush_cmd(void)
 639 {
 640    return MI_FLUSH | FLUSH_MAP_CACHE;
 641 }
 642
 643 static void
 644 i915_assert_not_dirty( struct intel_context *intel )
 645 {
 646    struct i915_context *i915 = i915_context(&intel->ctx);
 647    struct i915_hw_state *state = i915->current;
 648    GLuint dirty = get_dirty(state);
 649    assert(!dirty);
 650 }
 651
 652 static void
 653 i915_note_unlock( struct intel_context *intel )
 654 {
 655     /* nothing */
 656 }
 657
 658
 659 void
 660 i915InitVtbl(struct i915_context *i915)
 661 {
 662    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 663    i915->intel.vtbl.destroy = i915_destroy_context;
 664    i915->intel.vtbl.emit_state = i915_emit_state;
 665    i915->intel.vtbl.new_batch = i915_new_batch;
 666    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 667    i915->intel.vtbl.render_start = i915_render_start;
 668    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 669    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 670    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 671    i915->intel.vtbl.flush_cmd = i915_flush_cmd;
 672    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 673    i915->intel.vtbl.note_unlock = i915_note_unlock;
 674    i915->intel.vtbl.finish_batch = intel_finish_vb;
 675 }