src/mesa/drivers/dri/i915/i915_vtbl.c

   1 /**************************************************************************
   2  *
   3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  19  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  21  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  22  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  23  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  24  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28
  29
  30 #include "main/glheader.h"
  31 #include "main/mtypes.h"
  32 #include "main/imports.h"
  33 #include "main/macros.h"
  34 #include "main/colormac.h"
  35
  36 #include "tnl/t_context.h"
  37 #include "tnl/t_vertex.h"
  38
  39 #include "intel_batchbuffer.h"
  40 #include "intel_regions.h"
  41 #include "intel_tris.h"
  42 #include "intel_fbo.h"
  43
  44 #include "i915_reg.h"
  45 #include "i915_context.h"
  46
  47 static void
  48 i915_render_prevalidate(struct intel_context *intel)
  49 {
  50    struct i915_context *i915 = i915_context(&intel->ctx);
  51
  52    i915ValidateFragmentProgram(i915);
  53 }
  54
  55 static void
  56 i915_render_start(struct intel_context *intel)
  57 {
  58    intel_prepare_render(intel);
  59 }
  60
  61
  62 static void
  63 i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
  64 {
  65    struct i915_context *i915 = i915_context(&intel->ctx);
  66    GLuint st1 = i915->state.Stipple[I915_STPREG_ST1];
  67
  68    st1 &= ~ST1_ENABLE;
  69
  70    switch (rprim) {
  71    case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
  72    case GL_TRIANGLES:
  73       if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
  74          st1 |= ST1_ENABLE;
  75       break;
  76    case GL_LINES:
  77    case GL_POINTS:
  78    default:
  79       break;
  80    }
  81
  82    i915->intel.reduced_primitive = rprim;
  83
  84    if (st1 != i915->state.Stipple[I915_STPREG_ST1]) {
  85       INTEL_FIREVERTICES(intel);
  86
  87       I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE);
  88       i915->state.Stipple[I915_STPREG_ST1] = st1;
  89    }
  90 }
  91
  92
  93 /* Pull apart the vertex format registers and figure out how large a
  94  * vertex is supposed to be.
  95  */
  96 static GLboolean
  97 i915_check_vertex_size(struct intel_context *intel, GLuint expected)
  98 {
  99    struct i915_context *i915 = i915_context(&intel->ctx);
 100    int lis2 = i915->state.Ctx[I915_CTXREG_LIS2];
 101    int lis4 = i915->state.Ctx[I915_CTXREG_LIS4];
 102    int i, sz = 0;
 103
 104    switch (lis4 & S4_VFMT_XYZW_MASK) {
 105    case S4_VFMT_XY:
 106       sz = 2;
 107       break;
 108    case S4_VFMT_XYZ:
 109       sz = 3;
 110       break;
 111    case S4_VFMT_XYW:
 112       sz = 3;
 113       break;
 114    case S4_VFMT_XYZW:
 115       sz = 4;
 116       break;
 117    default:
 118       fprintf(stderr, "no xyzw specified\n");
 119       return 0;
 120    }
 121
 122    if (lis4 & S4_VFMT_SPEC_FOG)
 123       sz++;
 124    if (lis4 & S4_VFMT_COLOR)
 125       sz++;
 126    if (lis4 & S4_VFMT_DEPTH_OFFSET)
 127       sz++;
 128    if (lis4 & S4_VFMT_POINT_WIDTH)
 129       sz++;
 130    if (lis4 & S4_VFMT_FOG_PARAM)
 131       sz++;
 132
 133    for (i = 0; i < 8; i++) {
 134       switch (lis2 & S2_TEXCOORD_FMT0_MASK) {
 135       case TEXCOORDFMT_2D:
 136          sz += 2;
 137          break;
 138       case TEXCOORDFMT_3D:
 139          sz += 3;
 140          break;
 141       case TEXCOORDFMT_4D:
 142          sz += 4;
 143          break;
 144       case TEXCOORDFMT_1D:
 145          sz += 1;
 146          break;
 147       case TEXCOORDFMT_2D_16:
 148          sz += 1;
 149          break;
 150       case TEXCOORDFMT_4D_16:
 151          sz += 2;
 152          break;
 153       case TEXCOORDFMT_NOT_PRESENT:
 154          break;
 155       default:
 156          fprintf(stderr, "bad texcoord fmt %d\n", i);
 157          return GL_FALSE;
 158       }
 159       lis2 >>= S2_TEXCOORD_FMT1_SHIFT;
 160    }
 161
 162    if (sz != expected)
 163       fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
 164
 165    return sz == expected;
 166 }
 167
 168
 169 static void
 170 i915_emit_invarient_state(struct intel_context *intel)
 171 {
 172    BATCH_LOCALS;
 173
 174    BEGIN_BATCH(17);
 175
 176    OUT_BATCH(_3DSTATE_AA_CMD |
 177              AA_LINE_ECAAR_WIDTH_ENABLE |
 178              AA_LINE_ECAAR_WIDTH_1_0 |
 179              AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
 180
 181    OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
 182    OUT_BATCH(0);
 183
 184    OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
 185    OUT_BATCH(0);
 186
 187    OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
 188    OUT_BATCH(0);
 189
 190    /* Don't support texture crossbar yet */
 191    OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS |
 192              CSB_TCB(0, 0) |
 193              CSB_TCB(1, 1) |
 194              CSB_TCB(2, 2) |
 195              CSB_TCB(3, 3) |
 196              CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
 197
 198    /* Need to initialize this to zero.
 199     */
 200    OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0));
 201    OUT_BATCH(0);
 202
 203    /* XXX: Use this */
 204    OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
 205
 206    OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD);
 207    OUT_BATCH(0);
 208    OUT_BATCH(0);
 209
 210    OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE);
 211
 212    OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0);       /* disable indirect state */
 213    OUT_BATCH(0);
 214
 215    ADVANCE_BATCH();
 216 }
 217
 218
 219 #define emit(intel, state, size )                    \
 220    intel_batchbuffer_data(intel, state, size, false)
 221
 222 static GLuint
 223 get_dirty(struct i915_hw_state *state)
 224 {
 225    GLuint dirty;
 226
 227    /* Workaround the multitex hang - if one texture unit state is
 228     * modified, emit all texture units.
 229     */
 230    dirty = state->active & ~state->emitted;
 231    if (dirty & I915_UPLOAD_TEX_ALL)
 232       state->emitted &= ~I915_UPLOAD_TEX_ALL;
 233    dirty = state->active & ~state->emitted;
 234    return dirty;
 235 }
 236
 237
 238 static GLuint
 239 get_state_size(struct i915_hw_state *state)
 240 {
 241    GLuint dirty = get_dirty(state);
 242    GLuint i;
 243    GLuint sz = 0;
 244
 245    if (dirty & I915_UPLOAD_INVARIENT)
 246       sz += 30 * 4;
 247
 248    if (dirty & I915_UPLOAD_RASTER_RULES)
 249       sz += sizeof(state->RasterRules);
 250
 251    if (dirty & I915_UPLOAD_CTX)
 252       sz += sizeof(state->Ctx);
 253
 254    if (dirty & I915_UPLOAD_BLEND)
 255       sz += sizeof(state->Blend);
 256
 257    if (dirty & I915_UPLOAD_BUFFERS)
 258       sz += sizeof(state->Buffer);
 259
 260    if (dirty & I915_UPLOAD_STIPPLE)
 261       sz += sizeof(state->Stipple);
 262
 263    if (dirty & I915_UPLOAD_FOG)
 264       sz += sizeof(state->Fog);
 265
 266    if (dirty & I915_UPLOAD_TEX_ALL) {
 267       int nr = 0;
 268       for (i = 0; i < I915_TEX_UNITS; i++)
 269          if (dirty & I915_UPLOAD_TEX(i))
 270             nr++;
 271
 272       sz += (2 + nr * 3) * sizeof(GLuint) * 2;
 273    }
 274
 275    if (dirty & I915_UPLOAD_CONSTANTS)
 276       sz += state->ConstantSize * sizeof(GLuint);
 277
 278    if (dirty & I915_UPLOAD_PROGRAM)
 279       sz += state->ProgramSize * sizeof(GLuint);
 280
 281    return sz;
 282 }
 283
 284 /* Push the state into the sarea and/or texture memory.
 285  */
 286 static void
 287 i915_emit_state(struct intel_context *intel)
 288 {
 289    struct i915_context *i915 = i915_context(&intel->ctx);
 290    struct i915_hw_state *state = &i915->state;
 291    int i, count, aper_count;
 292    GLuint dirty;
 293    drm_intel_bo *aper_array[3 + I915_TEX_UNITS];
 294    GET_CURRENT_CONTEXT(ctx);
 295    BATCH_LOCALS;
 296
 297    /* We don't hold the lock at this point, so want to make sure that
 298     * there won't be a buffer wrap between the state emits and the primitive
 299     * emit header.
 300     *
 301     * It might be better to talk about explicit places where
 302     * scheduling is allowed, rather than assume that it is whenever a
 303     * batchbuffer fills up.
 304     */
 305    intel_batchbuffer_require_space(intel,
 306                                    get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
 307                                    false);
 308    count = 0;
 309  again:
 310    if (intel->batch.bo == NULL) {
 311       _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 312       assert(0);
 313    }
 314    aper_count = 0;
 315    dirty = get_dirty(state);
 316
 317    aper_array[aper_count++] = intel->batch.bo;
 318    if (dirty & I915_UPLOAD_BUFFERS) {
 319       aper_array[aper_count++] = state->draw_region->buffer;
 320       if (state->depth_region)
 321          aper_array[aper_count++] = state->depth_region->buffer;
 322    }
 323
 324    if (dirty & I915_UPLOAD_TEX_ALL) {
 325       for (i = 0; i < I915_TEX_UNITS; i++) {
 326          if (dirty & I915_UPLOAD_TEX(i)) {
 327             if (state->tex_buffer[i]) {
 328                aper_array[aper_count++] = state->tex_buffer[i];
 329             }
 330          }
 331       }
 332    }
 333
 334    if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
 335        if (count == 0) {
 336            count++;
 337            intel_batchbuffer_flush(intel);
 338            goto again;
 339        } else {
 340            _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state");
 341            assert(0);
 342        }
 343    }
 344
 345    /* work out list of buffers to emit */
 346
 347    /* Do this here as we may have flushed the batchbuffer above,
 348     * causing more state to be dirty!
 349     */
 350    dirty = get_dirty(state);
 351    state->emitted |= dirty;
 352    assert(get_dirty(state) == 0);
 353
 354    if (INTEL_DEBUG & DEBUG_STATE)
 355       fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty);
 356
 357    if (dirty & I915_UPLOAD_INVARIENT) {
 358       if (INTEL_DEBUG & DEBUG_STATE)
 359          fprintf(stderr, "I915_UPLOAD_INVARIENT:\n");
 360       i915_emit_invarient_state(intel);
 361    }
 362
 363    if (dirty & I915_UPLOAD_RASTER_RULES) {
 364       if (INTEL_DEBUG & DEBUG_STATE)
 365          fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n");
 366       emit(intel, state->RasterRules, sizeof(state->RasterRules));
 367    }
 368
 369    if (dirty & I915_UPLOAD_CTX) {
 370       if (INTEL_DEBUG & DEBUG_STATE)
 371          fprintf(stderr, "I915_UPLOAD_CTX:\n");
 372
 373       emit(intel, state->Ctx, sizeof(state->Ctx));
 374    }
 375
 376    if (dirty & I915_UPLOAD_BLEND) {
 377       if (INTEL_DEBUG & DEBUG_STATE)
 378          fprintf(stderr, "I915_UPLOAD_BLEND:\n");
 379
 380       emit(intel, state->Blend, sizeof(state->Blend));
 381    }
 382
 383    if (dirty & I915_UPLOAD_BUFFERS) {
 384       GLuint count;
 385
 386       if (INTEL_DEBUG & DEBUG_STATE)
 387          fprintf(stderr, "I915_UPLOAD_BUFFERS:\n");
 388
 389       count = 14;
 390       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 391          count++;
 392       if (state->depth_region)
 393          count += 3;
 394
 395       BEGIN_BATCH(count);
 396       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]);
 397       OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]);
 398       OUT_RELOC(state->draw_region->buffer,
 399                 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 400
 401       if (state->depth_region) {
 402          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]);
 403          OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]);
 404          OUT_RELOC(state->depth_region->buffer,
 405                    I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
 406       }
 407
 408       OUT_BATCH(state->Buffer[I915_DESTREG_DV0]);
 409       OUT_BATCH(state->Buffer[I915_DESTREG_DV1]);
 410       OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]);
 411       OUT_BATCH(state->Buffer[I915_DESTREG_SR0]);
 412       OUT_BATCH(state->Buffer[I915_DESTREG_SR1]);
 413       OUT_BATCH(state->Buffer[I915_DESTREG_SR2]);
 414
 415       if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP)
 416          OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]);
 417       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]);
 418       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]);
 419       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]);
 420       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]);
 421       OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]);
 422
 423       ADVANCE_BATCH();
 424    }
 425
 426    if (dirty & I915_UPLOAD_STIPPLE) {
 427       if (INTEL_DEBUG & DEBUG_STATE)
 428          fprintf(stderr, "I915_UPLOAD_STIPPLE:\n");
 429       emit(intel, state->Stipple, sizeof(state->Stipple));
 430    }
 431
 432    if (dirty & I915_UPLOAD_FOG) {
 433       if (INTEL_DEBUG & DEBUG_STATE)
 434          fprintf(stderr, "I915_UPLOAD_FOG:\n");
 435       emit(intel, state->Fog, sizeof(state->Fog));
 436    }
 437
 438    /* Combine all the dirty texture state into a single command to
 439     * avoid lockups on I915 hardware.
 440     */
 441    if (dirty & I915_UPLOAD_TEX_ALL) {
 442       int nr = 0;
 443       GLuint unwind;
 444
 445       for (i = 0; i < I915_TEX_UNITS; i++)
 446          if (dirty & I915_UPLOAD_TEX(i))
 447             nr++;
 448
 449       BEGIN_BATCH(2 + nr * 3);
 450       OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr));
 451       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 452       for (i = 0; i < I915_TEX_UNITS; i++)
 453          if (dirty & I915_UPLOAD_TEX(i)) {
 454             OUT_RELOC(state->tex_buffer[i],
 455                       I915_GEM_DOMAIN_SAMPLER, 0,
 456                       state->tex_offset[i]);
 457
 458             OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]);
 459             OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]);
 460          }
 461       ADVANCE_BATCH();
 462
 463       unwind = intel->batch.used;
 464       BEGIN_BATCH(2 + nr * 3);
 465       OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr));
 466       OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT);
 467       for (i = 0; i < I915_TEX_UNITS; i++)
 468          if (dirty & I915_UPLOAD_TEX(i)) {
 469             OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]);
 470             OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]);
 471             OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]);
 472          }
 473       ADVANCE_BATCH();
 474       if (i915->last_sampler &&
 475           memcmp(intel->batch.map + i915->last_sampler,
 476                  intel->batch.map + unwind,
 477                  (2 + nr*3)*sizeof(int)) == 0)
 478           intel->batch.used = unwind;
 479       else
 480           i915->last_sampler = unwind;
 481    }
 482
 483    if (dirty & I915_UPLOAD_CONSTANTS) {
 484       if (INTEL_DEBUG & DEBUG_STATE)
 485          fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n");
 486       emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint));
 487    }
 488
 489    if (dirty & I915_UPLOAD_PROGRAM) {
 490       if (state->ProgramSize) {
 491          if (INTEL_DEBUG & DEBUG_STATE)
 492             fprintf(stderr, "I915_UPLOAD_PROGRAM:\n");
 493
 494          assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize);
 495
 496          emit(intel, state->Program, state->ProgramSize * sizeof(GLuint));
 497          if (INTEL_DEBUG & DEBUG_STATE)
 498             i915_disassemble_program(state->Program, state->ProgramSize);
 499       }
 500    }
 501
 502    assert(get_dirty(state) == 0);
 503 }
 504
 505 static void
 506 i915_destroy_context(struct intel_context *intel)
 507 {
 508    GLuint i;
 509    struct i915_context *i915 = i915_context(&intel->ctx);
 510
 511    intel_region_release(&i915->state.draw_region);
 512    intel_region_release(&i915->state.depth_region);
 513
 514    for (i = 0; i < I915_TEX_UNITS; i++) {
 515       if (i915->state.tex_buffer[i] != NULL) {
 516          drm_intel_bo_unreference(i915->state.tex_buffer[i]);
 517          i915->state.tex_buffer[i] = NULL;
 518       }
 519    }
 520
 521    _tnl_free_vertices(&intel->ctx);
 522 }
 523
 524 void
 525 i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
 526                              uint32_t buffer_id)
 527 {
 528    state[0] = _3DSTATE_BUF_INFO_CMD;
 529    state[1] = buffer_id;
 530
 531    if (region != NULL) {
 532       state[1] |= BUF_3D_PITCH(region->pitch * region->cpp);
 533
 534       if (region->tiling != I915_TILING_NONE) {
 535          state[1] |= BUF_3D_TILED_SURFACE;
 536          if (region->tiling == I915_TILING_Y)
 537             state[1] |= BUF_3D_TILE_WALK_Y;
 538       }
 539    }
 540 }
 541
 542 static uint32_t i915_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
 543 {
 544    [MESA_FORMAT_ARGB8888] = DV_PF_8888,
 545    [MESA_FORMAT_XRGB8888] = DV_PF_8888,
 546    [MESA_FORMAT_RGB565] = DV_PF_565 | DITHER_FULL_ALWAYS,
 547    [MESA_FORMAT_ARGB1555] = DV_PF_1555 | DITHER_FULL_ALWAYS,
 548    [MESA_FORMAT_ARGB4444] = DV_PF_4444 | DITHER_FULL_ALWAYS,
 549 };
 550
 551 static bool
 552 i915_render_target_supported(gl_format format)
 553 {
 554    if (format == MESA_FORMAT_S8_Z24 ||
 555        format == MESA_FORMAT_X8_Z24 ||
 556        format == MESA_FORMAT_Z16) {
 557       return true;
 558    }
 559
 560    return i915_render_target_format_for_mesa_format[format] != 0;
 561 }
 562
 563 static void
 564 i915_set_draw_region(struct intel_context *intel,
 565                      struct intel_region *color_regions[],
 566                      struct intel_region *depth_region,
 567                      GLuint num_regions)
 568 {
 569    struct i915_context *i915 = i915_context(&intel->ctx);
 570    struct gl_context *ctx = &intel->ctx;
 571    struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
 572    struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 573    GLuint value;
 574    struct i915_hw_state *state = &i915->state;
 575    uint32_t draw_x, draw_y, draw_offset;
 576
 577    if (state->draw_region != color_regions[0]) {
 578       intel_region_release(&state->draw_region);
 579       intel_region_reference(&state->draw_region, color_regions[0]);
 580    }
 581    if (state->depth_region != depth_region) {
 582       intel_region_release(&state->depth_region);
 583       intel_region_reference(&state->depth_region, depth_region);
 584    }
 585
 586    /*
 587     * Set stride/cpp values
 588     */
 589    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0],
 590                                 color_regions[0], BUF_3D_ID_COLOR_BACK);
 591
 592    i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0],
 593                                 depth_region, BUF_3D_ID_DEPTH);
 594
 595    /*
 596     * Compute/set I915_DESTREG_DV1 value
 597     */
 598    value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
 599             DSTORG_VERT_BIAS(0x8) |     /* .5 */
 600             LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL);
 601    if (irb != NULL) {
 602       value |= i915_render_target_format_for_mesa_format[irb->Base.Format];
 603    }
 604
 605    /* This isn't quite safe, thus being hidden behind an option.  When changing
 606     * the value of this bit, the pipeline needs to be MI_FLUSHed.  And it
 607     * can only be set when a depth buffer is already defined.
 608     */
 609    if (intel->is_945 && intel->use_early_z &&
 610        depth_region->tiling != I915_TILING_NONE)
 611       value |= CLASSIC_EARLY_DEPTH;
 612
 613    if (depth_region && depth_region->cpp == 4) {
 614       value |= DEPTH_FRMT_24_FIXED_8_OTHER;
 615    }
 616    else {
 617       value |= DEPTH_FRMT_16_FIXED;
 618    }
 619    state->Buffer[I915_DESTREG_DV1] = value;
 620
 621    /* We set up the drawing rectangle to be offset into the color
 622     * region's location in the miptree.  If it doesn't match with
 623     * depth's offsets, we can't render to it.
 624     *
 625     * (Well, not actually true -- the hw grew a bit to let depth's
 626     * offset get forced to 0,0.  We may want to use that if people are
 627     * hitting that case.  Also, some configurations may be supportable
 628     * by tweaking the start offset of the buffers around, which we
 629     * can't do in general due to tiling)
 630     */
 631    FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 632             (depth_region && color_regions[0]) &&
 633             (depth_region->draw_x != color_regions[0]->draw_x ||
 634              depth_region->draw_y != color_regions[0]->draw_y));
 635
 636    if (color_regions[0]) {
 637       draw_x = color_regions[0]->draw_x;
 638       draw_y = color_regions[0]->draw_y;
 639    } else if (depth_region) {
 640       draw_x = depth_region->draw_x;
 641       draw_y = depth_region->draw_y;
 642    } else {
 643       draw_x = 0;
 644       draw_y = 0;
 645    }
 646
 647    draw_offset = (draw_y << 16) | draw_x;
 648
 649    /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
 650    if (draw_offset != i915->last_draw_offset) {
 651       FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
 652                (ctx->DrawBuffer->Width + draw_x > 2048) ||
 653                (ctx->DrawBuffer->Height + draw_y > 2048));
 654
 655       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE;
 656       i915->last_draw_offset = draw_offset;
 657    } else
 658       state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP;
 659
 660    state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO;
 661    state->Buffer[I915_DESTREG_DRAWRECT2] = 0;
 662    state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset;
 663    state->Buffer[I915_DESTREG_DRAWRECT4] =
 664       ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) |
 665       ((ctx->DrawBuffer->Height + draw_y - 1) << 16);
 666    state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset;
 667
 668    I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS);
 669 }
 670
 671
 672
 673 static void
 674 i915_new_batch(struct intel_context *intel)
 675 {
 676    struct i915_context *i915 = i915_context(&intel->ctx);
 677
 678    /* Mark all state as needing to be emitted when starting a new batchbuffer.
 679     * Using hardware contexts would be an alternative, but they have some
 680     * difficulties associated with them (physical address requirements).
 681     */
 682    i915->state.emitted = 0;
 683    i915->last_draw_offset = 0;
 684    i915->last_sampler = 0;
 685
 686    i915->current_vb_bo = NULL;
 687    i915->current_vertex_size = 0;
 688 }
 689
 690 static void
 691 i915_assert_not_dirty( struct intel_context *intel )
 692 {
 693    struct i915_context *i915 = i915_context(&intel->ctx);
 694    GLuint dirty = get_dirty(&i915->state);
 695    assert(!dirty);
 696    (void) dirty;
 697 }
 698
 699 void
 700 i915InitVtbl(struct i915_context *i915)
 701 {
 702    i915->intel.vtbl.check_vertex_size = i915_check_vertex_size;
 703    i915->intel.vtbl.destroy = i915_destroy_context;
 704    i915->intel.vtbl.emit_state = i915_emit_state;
 705    i915->intel.vtbl.new_batch = i915_new_batch;
 706    i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state;
 707    i915->intel.vtbl.render_start = i915_render_start;
 708    i915->intel.vtbl.render_prevalidate = i915_render_prevalidate;
 709    i915->intel.vtbl.set_draw_region = i915_set_draw_region;
 710    i915->intel.vtbl.update_texture_state = i915UpdateTextureState;
 711    i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty;
 712    i915->intel.vtbl.finish_batch = intel_finish_vb;
 713    i915->intel.vtbl.render_target_supported = i915_render_target_supported;
 714 }