1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
30 #include "main/glheader.h"
31 #include "main/mtypes.h"
32 #include "main/imports.h"
33 #include "main/macros.h"
34 #include "main/colormac.h"
36 #include "tnl/t_context.h"
37 #include "tnl/t_vertex.h"
39 #include "intel_batchbuffer.h"
40 #include "intel_regions.h"
41 #include "intel_tris.h"
42 #include "intel_fbo.h"
45 #include "i915_context.h"
48 i915_render_prevalidate(struct intel_context
*intel
)
50 struct i915_context
*i915
= i915_context(&intel
->ctx
);
52 i915ValidateFragmentProgram(i915
);
56 i915_render_start(struct intel_context
*intel
)
58 intel_prepare_render(intel
);
63 i915_reduced_primitive_state(struct intel_context
*intel
, GLenum rprim
)
65 struct i915_context
*i915
= i915_context(&intel
->ctx
);
66 GLuint st1
= i915
->state
.Stipple
[I915_STPREG_ST1
];
71 case GL_QUADS
: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */
73 if (intel
->ctx
.Polygon
.StippleFlag
&& intel
->hw_stipple
)
82 i915
->intel
.reduced_primitive
= rprim
;
84 if (st1
!= i915
->state
.Stipple
[I915_STPREG_ST1
]) {
85 INTEL_FIREVERTICES(intel
);
87 I915_STATECHANGE(i915
, I915_UPLOAD_STIPPLE
);
88 i915
->state
.Stipple
[I915_STPREG_ST1
] = st1
;
93 /* Pull apart the vertex format registers and figure out how large a
94 * vertex is supposed to be.
97 i915_check_vertex_size(struct intel_context
*intel
, GLuint expected
)
99 struct i915_context
*i915
= i915_context(&intel
->ctx
);
100 int lis2
= i915
->state
.Ctx
[I915_CTXREG_LIS2
];
101 int lis4
= i915
->state
.Ctx
[I915_CTXREG_LIS4
];
104 switch (lis4
& S4_VFMT_XYZW_MASK
) {
118 fprintf(stderr
, "no xyzw specified\n");
122 if (lis4
& S4_VFMT_SPEC_FOG
)
124 if (lis4
& S4_VFMT_COLOR
)
126 if (lis4
& S4_VFMT_DEPTH_OFFSET
)
128 if (lis4
& S4_VFMT_POINT_WIDTH
)
130 if (lis4
& S4_VFMT_FOG_PARAM
)
133 for (i
= 0; i
< 8; i
++) {
134 switch (lis2
& S2_TEXCOORD_FMT0_MASK
) {
147 case TEXCOORDFMT_2D_16
:
150 case TEXCOORDFMT_4D_16
:
153 case TEXCOORDFMT_NOT_PRESENT
:
156 fprintf(stderr
, "bad texcoord fmt %d\n", i
);
159 lis2
>>= S2_TEXCOORD_FMT1_SHIFT
;
163 fprintf(stderr
, "vertex size mismatch %d/%d\n", sz
, expected
);
165 return sz
== expected
;
170 i915_emit_invarient_state(struct intel_context
*intel
)
176 OUT_BATCH(_3DSTATE_AA_CMD
|
177 AA_LINE_ECAAR_WIDTH_ENABLE
|
178 AA_LINE_ECAAR_WIDTH_1_0
|
179 AA_LINE_REGION_WIDTH_ENABLE
| AA_LINE_REGION_WIDTH_1_0
);
181 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD
);
184 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD
);
187 OUT_BATCH(_3DSTATE_DFLT_Z_CMD
);
190 /* Don't support texture crossbar yet */
191 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS
|
196 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7));
198 /* Need to initialize this to zero.
200 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1
| I1_LOAD_S(3) | (0));
204 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD
| DISABLE_SCISSOR_RECT
);
206 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD
);
210 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE
);
212 OUT_BATCH(_3DSTATE_LOAD_INDIRECT
| 0); /* disable indirect state */
219 #define emit(intel, state, size ) \
220 intel_batchbuffer_data(intel, state, size, false)
223 get_dirty(struct i915_hw_state
*state
)
227 /* Workaround the multitex hang - if one texture unit state is
228 * modified, emit all texture units.
230 dirty
= state
->active
& ~state
->emitted
;
231 if (dirty
& I915_UPLOAD_TEX_ALL
)
232 state
->emitted
&= ~I915_UPLOAD_TEX_ALL
;
233 dirty
= state
->active
& ~state
->emitted
;
239 get_state_size(struct i915_hw_state
*state
)
241 GLuint dirty
= get_dirty(state
);
245 if (dirty
& I915_UPLOAD_INVARIENT
)
248 if (dirty
& I915_UPLOAD_RASTER_RULES
)
249 sz
+= sizeof(state
->RasterRules
);
251 if (dirty
& I915_UPLOAD_CTX
)
252 sz
+= sizeof(state
->Ctx
);
254 if (dirty
& I915_UPLOAD_BLEND
)
255 sz
+= sizeof(state
->Blend
);
257 if (dirty
& I915_UPLOAD_BUFFERS
)
258 sz
+= sizeof(state
->Buffer
);
260 if (dirty
& I915_UPLOAD_STIPPLE
)
261 sz
+= sizeof(state
->Stipple
);
263 if (dirty
& I915_UPLOAD_TEX_ALL
) {
265 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
266 if (dirty
& I915_UPLOAD_TEX(i
))
269 sz
+= (2 + nr
* 3) * sizeof(GLuint
) * 2;
272 if (dirty
& I915_UPLOAD_CONSTANTS
)
273 sz
+= state
->ConstantSize
* sizeof(GLuint
);
275 if (dirty
& I915_UPLOAD_PROGRAM
)
276 sz
+= state
->ProgramSize
* sizeof(GLuint
);
281 /* Push the state into the sarea and/or texture memory.
284 i915_emit_state(struct intel_context
*intel
)
286 struct i915_context
*i915
= i915_context(&intel
->ctx
);
287 struct i915_hw_state
*state
= &i915
->state
;
288 int i
, count
, aper_count
;
290 drm_intel_bo
*aper_array
[3 + I915_TEX_UNITS
];
291 GET_CURRENT_CONTEXT(ctx
);
294 /* We don't hold the lock at this point, so want to make sure that
295 * there won't be a buffer wrap between the state emits and the primitive
298 * It might be better to talk about explicit places where
299 * scheduling is allowed, rather than assume that it is whenever a
300 * batchbuffer fills up.
302 intel_batchbuffer_require_space(intel
,
303 get_state_size(state
) + INTEL_PRIM_EMIT_SIZE
,
307 if (intel
->batch
.bo
== NULL
) {
308 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
312 dirty
= get_dirty(state
);
314 aper_array
[aper_count
++] = intel
->batch
.bo
;
315 if (dirty
& I915_UPLOAD_BUFFERS
) {
316 aper_array
[aper_count
++] = state
->draw_region
->buffer
;
317 if (state
->depth_region
)
318 aper_array
[aper_count
++] = state
->depth_region
->buffer
;
321 if (dirty
& I915_UPLOAD_TEX_ALL
) {
322 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
323 if (dirty
& I915_UPLOAD_TEX(i
)) {
324 if (state
->tex_buffer
[i
]) {
325 aper_array
[aper_count
++] = state
->tex_buffer
[i
];
331 if (dri_bufmgr_check_aperture_space(aper_array
, aper_count
)) {
334 intel_batchbuffer_flush(intel
);
337 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "i915 emit state");
342 /* work out list of buffers to emit */
344 /* Do this here as we may have flushed the batchbuffer above,
345 * causing more state to be dirty!
347 dirty
= get_dirty(state
);
348 state
->emitted
|= dirty
;
349 assert(get_dirty(state
) == 0);
351 if (INTEL_DEBUG
& DEBUG_STATE
)
352 fprintf(stderr
, "%s dirty: %x\n", __FUNCTION__
, dirty
);
354 if (dirty
& I915_UPLOAD_INVARIENT
) {
355 if (INTEL_DEBUG
& DEBUG_STATE
)
356 fprintf(stderr
, "I915_UPLOAD_INVARIENT:\n");
357 i915_emit_invarient_state(intel
);
360 if (dirty
& I915_UPLOAD_RASTER_RULES
) {
361 if (INTEL_DEBUG
& DEBUG_STATE
)
362 fprintf(stderr
, "I915_UPLOAD_RASTER_RULES:\n");
363 emit(intel
, state
->RasterRules
, sizeof(state
->RasterRules
));
366 if (dirty
& I915_UPLOAD_CTX
) {
367 if (INTEL_DEBUG
& DEBUG_STATE
)
368 fprintf(stderr
, "I915_UPLOAD_CTX:\n");
370 emit(intel
, state
->Ctx
, sizeof(state
->Ctx
));
373 if (dirty
& I915_UPLOAD_BLEND
) {
374 if (INTEL_DEBUG
& DEBUG_STATE
)
375 fprintf(stderr
, "I915_UPLOAD_BLEND:\n");
377 emit(intel
, state
->Blend
, sizeof(state
->Blend
));
380 if (dirty
& I915_UPLOAD_BUFFERS
) {
383 if (INTEL_DEBUG
& DEBUG_STATE
)
384 fprintf(stderr
, "I915_UPLOAD_BUFFERS:\n");
387 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
389 if (state
->depth_region
)
393 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR0
]);
394 OUT_BATCH(state
->Buffer
[I915_DESTREG_CBUFADDR1
]);
395 OUT_RELOC(state
->draw_region
->buffer
,
396 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
398 if (state
->depth_region
) {
399 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR0
]);
400 OUT_BATCH(state
->Buffer
[I915_DESTREG_DBUFADDR1
]);
401 OUT_RELOC(state
->depth_region
->buffer
,
402 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
, 0);
405 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV0
]);
406 OUT_BATCH(state
->Buffer
[I915_DESTREG_DV1
]);
407 OUT_BATCH(state
->Buffer
[I915_DESTREG_SENABLE
]);
408 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR0
]);
409 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR1
]);
410 OUT_BATCH(state
->Buffer
[I915_DESTREG_SR2
]);
412 if (state
->Buffer
[I915_DESTREG_DRAWRECT0
] != MI_NOOP
)
413 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT0
]);
414 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT1
]);
415 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT2
]);
416 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT3
]);
417 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT4
]);
418 OUT_BATCH(state
->Buffer
[I915_DESTREG_DRAWRECT5
]);
423 if (dirty
& I915_UPLOAD_STIPPLE
) {
424 if (INTEL_DEBUG
& DEBUG_STATE
)
425 fprintf(stderr
, "I915_UPLOAD_STIPPLE:\n");
426 emit(intel
, state
->Stipple
, sizeof(state
->Stipple
));
429 /* Combine all the dirty texture state into a single command to
430 * avoid lockups on I915 hardware.
432 if (dirty
& I915_UPLOAD_TEX_ALL
) {
436 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
437 if (dirty
& I915_UPLOAD_TEX(i
))
440 BEGIN_BATCH(2 + nr
* 3);
441 OUT_BATCH(_3DSTATE_MAP_STATE
| (3 * nr
));
442 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
443 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
444 if (dirty
& I915_UPLOAD_TEX(i
)) {
445 OUT_RELOC(state
->tex_buffer
[i
],
446 I915_GEM_DOMAIN_SAMPLER
, 0,
447 state
->tex_offset
[i
]);
449 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS3
]);
450 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_MS4
]);
454 unwind
= intel
->batch
.used
;
455 BEGIN_BATCH(2 + nr
* 3);
456 OUT_BATCH(_3DSTATE_SAMPLER_STATE
| (3 * nr
));
457 OUT_BATCH((dirty
& I915_UPLOAD_TEX_ALL
) >> I915_UPLOAD_TEX_0_SHIFT
);
458 for (i
= 0; i
< I915_TEX_UNITS
; i
++)
459 if (dirty
& I915_UPLOAD_TEX(i
)) {
460 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS2
]);
461 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS3
]);
462 OUT_BATCH(state
->Tex
[i
][I915_TEXREG_SS4
]);
465 if (i915
->last_sampler
&&
466 memcmp(intel
->batch
.map
+ i915
->last_sampler
,
467 intel
->batch
.map
+ unwind
,
468 (2 + nr
*3)*sizeof(int)) == 0)
469 intel
->batch
.used
= unwind
;
471 i915
->last_sampler
= unwind
;
474 if (dirty
& I915_UPLOAD_CONSTANTS
) {
475 if (INTEL_DEBUG
& DEBUG_STATE
)
476 fprintf(stderr
, "I915_UPLOAD_CONSTANTS:\n");
477 emit(intel
, state
->Constant
, state
->ConstantSize
* sizeof(GLuint
));
480 if (dirty
& I915_UPLOAD_PROGRAM
) {
481 if (state
->ProgramSize
) {
482 if (INTEL_DEBUG
& DEBUG_STATE
)
483 fprintf(stderr
, "I915_UPLOAD_PROGRAM:\n");
485 assert((state
->Program
[0] & 0x1ff) + 2 == state
->ProgramSize
);
487 emit(intel
, state
->Program
, state
->ProgramSize
* sizeof(GLuint
));
488 if (INTEL_DEBUG
& DEBUG_STATE
)
489 i915_disassemble_program(state
->Program
, state
->ProgramSize
);
493 assert(get_dirty(state
) == 0);
497 i915_destroy_context(struct intel_context
*intel
)
500 struct i915_context
*i915
= i915_context(&intel
->ctx
);
502 intel_region_release(&i915
->state
.draw_region
);
503 intel_region_release(&i915
->state
.depth_region
);
505 for (i
= 0; i
< I915_TEX_UNITS
; i
++) {
506 if (i915
->state
.tex_buffer
[i
] != NULL
) {
507 drm_intel_bo_unreference(i915
->state
.tex_buffer
[i
]);
508 i915
->state
.tex_buffer
[i
] = NULL
;
512 _tnl_free_vertices(&intel
->ctx
);
516 i915_set_buf_info_for_region(uint32_t *state
, struct intel_region
*region
,
519 state
[0] = _3DSTATE_BUF_INFO_CMD
;
520 state
[1] = buffer_id
;
522 if (region
!= NULL
) {
523 state
[1] |= BUF_3D_PITCH(region
->pitch
* region
->cpp
);
525 if (region
->tiling
!= I915_TILING_NONE
) {
526 state
[1] |= BUF_3D_TILED_SURFACE
;
527 if (region
->tiling
== I915_TILING_Y
)
528 state
[1] |= BUF_3D_TILE_WALK_Y
;
533 static uint32_t i915_render_target_format_for_mesa_format
[MESA_FORMAT_COUNT
] =
535 [MESA_FORMAT_ARGB8888
] = DV_PF_8888
,
536 [MESA_FORMAT_XRGB8888
] = DV_PF_8888
,
537 [MESA_FORMAT_RGB565
] = DV_PF_565
| DITHER_FULL_ALWAYS
,
538 [MESA_FORMAT_ARGB1555
] = DV_PF_1555
| DITHER_FULL_ALWAYS
,
539 [MESA_FORMAT_ARGB4444
] = DV_PF_4444
| DITHER_FULL_ALWAYS
,
543 i915_render_target_supported(gl_format format
)
545 if (format
== MESA_FORMAT_S8_Z24
||
546 format
== MESA_FORMAT_X8_Z24
||
547 format
== MESA_FORMAT_Z16
) {
551 return i915_render_target_format_for_mesa_format
[format
] != 0;
555 i915_set_draw_region(struct intel_context
*intel
,
556 struct intel_region
*color_regions
[],
557 struct intel_region
*depth_region
,
560 struct i915_context
*i915
= i915_context(&intel
->ctx
);
561 struct gl_context
*ctx
= &intel
->ctx
;
562 struct gl_renderbuffer
*rb
= ctx
->DrawBuffer
->_ColorDrawBuffers
[0];
563 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
565 struct i915_hw_state
*state
= &i915
->state
;
566 uint32_t draw_x
, draw_y
, draw_offset
;
568 if (state
->draw_region
!= color_regions
[0]) {
569 intel_region_release(&state
->draw_region
);
570 intel_region_reference(&state
->draw_region
, color_regions
[0]);
572 if (state
->depth_region
!= depth_region
) {
573 intel_region_release(&state
->depth_region
);
574 intel_region_reference(&state
->depth_region
, depth_region
);
578 * Set stride/cpp values
580 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_CBUFADDR0
],
581 color_regions
[0], BUF_3D_ID_COLOR_BACK
);
583 i915_set_buf_info_for_region(&state
->Buffer
[I915_DESTREG_DBUFADDR0
],
584 depth_region
, BUF_3D_ID_DEPTH
);
587 * Compute/set I915_DESTREG_DV1 value
589 value
= (DSTORG_HORT_BIAS(0x8) | /* .5 */
590 DSTORG_VERT_BIAS(0x8) | /* .5 */
591 LOD_PRECLAMP_OGL
| TEX_DEFAULT_COLOR_OGL
);
593 value
|= i915_render_target_format_for_mesa_format
[irb
->Base
.Format
];
596 /* This isn't quite safe, thus being hidden behind an option. When changing
597 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it
598 * can only be set when a depth buffer is already defined.
600 if (intel
->is_945
&& intel
->use_early_z
&&
601 depth_region
->tiling
!= I915_TILING_NONE
)
602 value
|= CLASSIC_EARLY_DEPTH
;
604 if (depth_region
&& depth_region
->cpp
== 4) {
605 value
|= DEPTH_FRMT_24_FIXED_8_OTHER
;
608 value
|= DEPTH_FRMT_16_FIXED
;
610 state
->Buffer
[I915_DESTREG_DV1
] = value
;
612 /* We set up the drawing rectangle to be offset into the color
613 * region's location in the miptree. If it doesn't match with
614 * depth's offsets, we can't render to it.
616 * (Well, not actually true -- the hw grew a bit to let depth's
617 * offset get forced to 0,0. We may want to use that if people are
618 * hitting that case. Also, some configurations may be supportable
619 * by tweaking the start offset of the buffers around, which we
620 * can't do in general due to tiling)
622 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
623 (depth_region
&& color_regions
[0]) &&
624 (depth_region
->draw_x
!= color_regions
[0]->draw_x
||
625 depth_region
->draw_y
!= color_regions
[0]->draw_y
));
627 if (color_regions
[0]) {
628 draw_x
= color_regions
[0]->draw_x
;
629 draw_y
= color_regions
[0]->draw_y
;
630 } else if (depth_region
) {
631 draw_x
= depth_region
->draw_x
;
632 draw_y
= depth_region
->draw_y
;
638 draw_offset
= (draw_y
<< 16) | draw_x
;
640 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */
641 if (draw_offset
!= i915
->last_draw_offset
) {
642 FALLBACK(intel
, I915_FALLBACK_DRAW_OFFSET
,
643 (ctx
->DrawBuffer
->Width
+ draw_x
> 2048) ||
644 (ctx
->DrawBuffer
->Height
+ draw_y
> 2048));
646 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_FLUSH
| INHIBIT_FLUSH_RENDER_CACHE
;
647 i915
->last_draw_offset
= draw_offset
;
649 state
->Buffer
[I915_DESTREG_DRAWRECT0
] = MI_NOOP
;
651 state
->Buffer
[I915_DESTREG_DRAWRECT1
] = _3DSTATE_DRAWRECT_INFO
;
652 state
->Buffer
[I915_DESTREG_DRAWRECT2
] = 0;
653 state
->Buffer
[I915_DESTREG_DRAWRECT3
] = draw_offset
;
654 state
->Buffer
[I915_DESTREG_DRAWRECT4
] =
655 ((ctx
->DrawBuffer
->Width
+ draw_x
- 1) & 0xffff) |
656 ((ctx
->DrawBuffer
->Height
+ draw_y
- 1) << 16);
657 state
->Buffer
[I915_DESTREG_DRAWRECT5
] = draw_offset
;
659 I915_STATECHANGE(i915
, I915_UPLOAD_BUFFERS
);
665 i915_new_batch(struct intel_context
*intel
)
667 struct i915_context
*i915
= i915_context(&intel
->ctx
);
669 /* Mark all state as needing to be emitted when starting a new batchbuffer.
670 * Using hardware contexts would be an alternative, but they have some
671 * difficulties associated with them (physical address requirements).
673 i915
->state
.emitted
= 0;
674 i915
->last_draw_offset
= 0;
675 i915
->last_sampler
= 0;
677 i915
->current_vb_bo
= NULL
;
678 i915
->current_vertex_size
= 0;
682 i915_assert_not_dirty( struct intel_context
*intel
)
684 struct i915_context
*i915
= i915_context(&intel
->ctx
);
685 GLuint dirty
= get_dirty(&i915
->state
);
691 i915InitVtbl(struct i915_context
*i915
)
693 i915
->intel
.vtbl
.check_vertex_size
= i915_check_vertex_size
;
694 i915
->intel
.vtbl
.destroy
= i915_destroy_context
;
695 i915
->intel
.vtbl
.emit_state
= i915_emit_state
;
696 i915
->intel
.vtbl
.new_batch
= i915_new_batch
;
697 i915
->intel
.vtbl
.reduced_primitive_state
= i915_reduced_primitive_state
;
698 i915
->intel
.vtbl
.render_start
= i915_render_start
;
699 i915
->intel
.vtbl
.render_prevalidate
= i915_render_prevalidate
;
700 i915
->intel
.vtbl
.set_draw_region
= i915_set_draw_region
;
701 i915
->intel
.vtbl
.update_texture_state
= i915UpdateTextureState
;
702 i915
->intel
.vtbl
.assert_not_dirty
= i915_assert_not_dirty
;
703 i915
->intel
.vtbl
.finish_batch
= intel_finish_vb
;
704 i915
->intel
.vtbl
.render_target_supported
= i915_render_target_supported
;