src/mesa/drivers/dri/i965/brw_blorp.h

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #pragma once
  25
  26 #include <stdint.h>
  27
  28 #include "brw_reg.h"
  29 #include "intel_mipmap_tree.h"
  30
  31 struct brw_context;
  32
  33 #ifdef __cplusplus
  34 extern "C" {
  35 #endif
  36
  37 void
  38 brw_blorp_blit_miptrees(struct brw_context *brw,
  39                         struct intel_mipmap_tree *src_mt,
  40                         unsigned src_level, unsigned src_layer,
  41                         mesa_format src_format, int src_swizzle,
  42                         struct intel_mipmap_tree *dst_mt,
  43                         unsigned dst_level, unsigned dst_layer,
  44                         mesa_format dst_format,
  45                         float src_x0, float src_y0,
  46                         float src_x1, float src_y1,
  47                         float dst_x0, float dst_y0,
  48                         float dst_x1, float dst_y1,
  49                         GLenum filter, bool mirror_x, bool mirror_y,
  50                         bool decode_srgb, bool encode_srgb);
  51
  52 bool
  53 brw_blorp_clear_color(struct brw_context *brw, struct gl_framebuffer *fb,
  54                       GLbitfield mask, bool partial_clear, bool encode_srgb);
  55
  56 void
  57 brw_blorp_resolve_color(struct brw_context *brw,
  58                         struct intel_mipmap_tree *mt);
  59
  60 /**
  61  * Binding table indices used by BLORP.
  62  */
  63 enum {
  64    BRW_BLORP_RENDERBUFFER_BINDING_TABLE_INDEX,
  65    BRW_BLORP_TEXTURE_BINDING_TABLE_INDEX,
  66    BRW_BLORP_NUM_BINDING_TABLE_ENTRIES
  67 };
  68
  69 struct brw_blorp_surface_info
  70 {
  71    struct intel_mipmap_tree *mt;
  72
  73    /**
  74     * The miplevel to use.
  75     */
  76    uint32_t level;
  77
  78    /**
  79     * The 2D layer within the miplevel. Combined, level and layer define the
  80     * 2D miptree slice to use.
  81     *
  82     * Note: if mt is a 2D multisample array texture on Gen7+ using
  83     * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, layer is the physical
  84     * layer holding sample 0.  So, for example, if mt->num_samples == 4, then
  85     * logical layer n corresponds to layer == 4*n.
  86     */
  87    uint32_t layer;
  88
  89    /**
  90     * Width of the miplevel to be used.  For surfaces using
  91     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  92     */
  93    uint32_t width;
  94
  95    /**
  96     * Height of the miplevel to be used.  For surfaces using
  97     * INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not pixels.
  98     */
  99    uint32_t height;
 100
 101    /**
 102     * X offset within the surface to texture from (or render to).  For
 103     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 104     * pixels.
 105     */
 106    uint32_t x_offset;
 107
 108    /**
 109     * Y offset within the surface to texture from (or render to).  For
 110     * surfaces using INTEL_MSAA_LAYOUT_IMS, this is measured in samples, not
 111     * pixels.
 112     */
 113    uint32_t y_offset;
 114
 115    /* Setting this flag indicates that the buffer's contents are W-tiled
 116     * stencil data, but the surface state should be set up for Y tiled
 117     * MESA_FORMAT_R_UNORM8 data (this is necessary because surface states don't
 118     * support W tiling).
 119     *
 120     * Since W tiles are 64 pixels wide by 64 pixels high, whereas Y tiles of
 121     * MESA_FORMAT_R_UNORM8 data are 128 pixels wide by 32 pixels high, the width and
 122     * pitch stored in the surface state will be multiplied by 2, and the
 123     * height will be halved.  Also, since W and Y tiles store their data in a
 124     * different order, the width and height will be rounded up to a multiple
 125     * of the tile size, to ensure that the WM program can access the full
 126     * width and height of the buffer.
 127     */
 128    bool map_stencil_as_y_tiled;
 129
 130    unsigned num_samples;
 131
 132    /**
 133     * Indicates if we use the standard miptree layout (ALL_LOD_IN_EACH_SLICE),
 134     * or if we tightly pack array slices at each LOD (ALL_SLICES_AT_EACH_LOD).
 135     *
 136     * If ALL_SLICES_AT_EACH_LOD is set, then ARYSPC_LOD0 can be used. Ignored
 137     * prior to Gen7.
 138     */
 139    enum miptree_array_layout array_layout;
 140
 141    /**
 142     * Format that should be used when setting up the surface state for this
 143     * surface.  Should correspond to one of the BRW_SURFACEFORMAT_* enums.
 144     */
 145    uint32_t brw_surfaceformat;
 146
 147    /**
 148     * For MSAA surfaces, MSAA layout that should be used when setting up the
 149     * surface state for this surface.
 150     */
 151    enum intel_msaa_layout msaa_layout;
 152
 153    /**
 154     * In order to support cases where RGBA format is backing client requested
 155     * RGB, one needs to have means to force alpha channel to one when user
 156     * requested RGB surface is used as blit source. This is possible by
 157     * setting source swizzle for the texture surface.
 158     */
 159    int swizzle;
 160 };
 161
 162 void
 163 brw_blorp_surface_info_init(struct brw_context *brw,
 164                             struct brw_blorp_surface_info *info,
 165                             struct intel_mipmap_tree *mt,
 166                             unsigned int level, unsigned int layer,
 167                             mesa_format format, bool is_render_target);
 168
 169 uint32_t
 170 brw_blorp_compute_tile_offsets(const struct brw_blorp_surface_info *info,
 171                                uint32_t *tile_x, uint32_t *tile_y);
 172
 173
 174
 175 struct brw_blorp_coord_transform
 176 {
 177    float multiplier;
 178    float offset;
 179 };
 180
 181 struct brw_blorp_wm_push_constants
 182 {
 183    uint32_t dst_x0;
 184    uint32_t dst_x1;
 185    uint32_t dst_y0;
 186    uint32_t dst_y1;
 187    /* Top right coordinates of the rectangular grid used for scaled blitting */
 188    float rect_grid_x1;
 189    float rect_grid_y1;
 190    struct brw_blorp_coord_transform x_transform;
 191    struct brw_blorp_coord_transform y_transform;
 192
 193    /* Minimum layer setting works for all the textures types but texture_3d
 194     * for which the setting has no effect. Use the z-coordinate instead.
 195     */
 196    uint32_t src_z;
 197
 198    /* Pad out to an integral number of registers */
 199    uint32_t pad[5];
 200 };
 201
 202 /* Every 32 bytes of push constant data constitutes one GEN register. */
 203 static const unsigned int BRW_BLORP_NUM_PUSH_CONST_REGS =
 204    sizeof(struct brw_blorp_wm_push_constants) / 32;
 205
 206 struct brw_blorp_prog_data
 207 {
 208    unsigned int first_curbe_grf;
 209
 210    /**
 211     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 212     * than one sample per pixel.
 213     */
 214    bool persample_msaa_dispatch;
 215 };
 216
 217 struct brw_blorp_params
 218 {
 219    uint32_t x0;
 220    uint32_t y0;
 221    uint32_t x1;
 222    uint32_t y1;
 223    struct brw_blorp_surface_info depth;
 224    uint32_t depth_format;
 225    struct brw_blorp_surface_info src;
 226    struct brw_blorp_surface_info dst;
 227    enum gen6_hiz_op hiz_op;
 228    unsigned fast_clear_op;
 229    bool color_write_disable[4];
 230    struct brw_blorp_wm_push_constants wm_push_consts;
 231    unsigned num_varyings;
 232    unsigned num_draw_buffers;
 233    unsigned num_layers;
 234    uint32_t wm_prog_kernel;
 235    struct brw_blorp_prog_data *wm_prog_data;
 236 };
 237
 238 void
 239 brw_blorp_params_init(struct brw_blorp_params *params);
 240
 241 void
 242 brw_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 243
 244 void
 245 gen6_blorp_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
 246                     unsigned level, unsigned layer, enum gen6_hiz_op op);
 247
 248 void
 249 gen6_blorp_exec(struct brw_context *brw,
 250                 const struct brw_blorp_params *params);
 251
 252 void
 253 gen7_blorp_exec(struct brw_context *brw,
 254                 const struct brw_blorp_params *params);
 255
 256 void
 257 gen8_blorp_exec(struct brw_context *brw, const struct brw_blorp_params *params);
 258
 259 struct brw_blorp_blit_prog_key
 260 {
 261    /* Number of samples per pixel that have been configured in the surface
 262     * state for texturing from.
 263     */
 264    unsigned tex_samples;
 265
 266    /* MSAA layout that has been configured in the surface state for texturing
 267     * from.
 268     */
 269    enum intel_msaa_layout tex_layout;
 270
 271    /* Actual number of samples per pixel in the source image. */
 272    unsigned src_samples;
 273
 274    /* Actual MSAA layout used by the source image. */
 275    enum intel_msaa_layout src_layout;
 276
 277    /* Number of samples per pixel that have been configured in the render
 278     * target.
 279     */
 280    unsigned rt_samples;
 281
 282    /* MSAA layout that has been configured in the render target. */
 283    enum intel_msaa_layout rt_layout;
 284
 285    /* Actual number of samples per pixel in the destination image. */
 286    unsigned dst_samples;
 287
 288    /* Actual MSAA layout used by the destination image. */
 289    enum intel_msaa_layout dst_layout;
 290
 291    /* Type of the data to be read from the texture (one of
 292     * BRW_REGISTER_TYPE_{UD,D,F}).
 293     */
 294    enum brw_reg_type texture_data_type;
 295
 296    /* True if the source image is W tiled.  If true, the surface state for the
 297     * source image must be configured as Y tiled, and tex_samples must be 0.
 298     */
 299    bool src_tiled_w;
 300
 301    /* True if the destination image is W tiled.  If true, the surface state
 302     * for the render target must be configured as Y tiled, and rt_samples must
 303     * be 0.
 304     */
 305    bool dst_tiled_w;
 306
 307    /* True if all source samples should be blended together to produce each
 308     * destination pixel.  If true, src_tiled_w must be false, tex_samples must
 309     * equal src_samples, and tex_samples must be nonzero.
 310     */
 311    bool blend;
 312
 313    /* True if the rectangle being sent through the rendering pipeline might be
 314     * larger than the destination rectangle, so the WM program should kill any
 315     * pixels that are outside the destination rectangle.
 316     */
 317    bool use_kill;
 318
 319    /**
 320     * True if the WM program should be run in MSDISPMODE_PERSAMPLE with more
 321     * than one sample per pixel.
 322     */
 323    bool persample_msaa_dispatch;
 324
 325    /* True for scaled blitting. */
 326    bool blit_scaled;
 327
 328    /* Scale factors between the pixel grid and the grid of samples. We're
 329     * using grid of samples for bilinear filetring in multisample scaled blits.
 330     */
 331    float x_scale;
 332    float y_scale;
 333
 334    /* True for blits with filter = GL_LINEAR. */
 335    bool bilinear_filter;
 336 };
 337
 338 /**
 339  * \name BLORP internals
 340  * \{
 341  *
 342  * Used internally by gen6_blorp_exec() and gen7_blorp_exec().
 343  */
 344
 345 void
 346 gen6_blorp_init(struct brw_context *brw);
 347
 348 void
 349 gen6_blorp_emit_vertices(struct brw_context *brw,
 350                          const struct brw_blorp_params *params);
 351
 352 uint32_t
 353 gen6_blorp_emit_blend_state(struct brw_context *brw,
 354                             const struct brw_blorp_params *params);
 355
 356 uint32_t
 357 gen6_blorp_emit_cc_state(struct brw_context *brw);
 358
 359 uint32_t
 360 gen6_blorp_emit_wm_constants(struct brw_context *brw,
 361                              const struct brw_blorp_params *params);
 362
 363 void
 364 gen6_blorp_emit_vs_disable(struct brw_context *brw,
 365                            const struct brw_blorp_params *params);
 366
 367 uint32_t
 368 gen6_blorp_emit_binding_table(struct brw_context *brw,
 369                               uint32_t wm_surf_offset_renderbuffer,
 370                               uint32_t wm_surf_offset_texture);
 371
 372 uint32_t
 373 gen6_blorp_emit_depth_stencil_state(struct brw_context *brw,
 374                                     const struct brw_blorp_params *params);
 375
 376 void
 377 gen6_blorp_emit_gs_disable(struct brw_context *brw,
 378                            const struct brw_blorp_params *params);
 379
 380 void
 381 gen6_blorp_emit_clip_disable(struct brw_context *brw);
 382
 383 void
 384 gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
 385                                   const struct brw_blorp_params *params);
 386
 387 uint32_t
 388 gen6_blorp_emit_sampler_state(struct brw_context *brw,
 389                               unsigned tex_filter, unsigned max_lod,
 390                               bool non_normalized_coords);
 391 void
 392 gen7_blorp_emit_urb_config(struct brw_context *brw);
 393
 394 void
 395 gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
 396                                     uint32_t cc_blend_state_offset);
 397
 398 void
 399 gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
 400                                  uint32_t cc_state_offset);
 401
 402 void
 403 gen7_blorp_emit_cc_viewport(struct brw_context *brw);
 404
 405 void
 406 gen7_blorp_emit_te_disable(struct brw_context *brw);
 407
 408 void
 409 gen7_blorp_emit_binding_table_pointers_ps(struct brw_context *brw,
 410                                           uint32_t wm_bind_bo_offset);
 411
 412 void
 413 gen7_blorp_emit_sampler_state_pointers_ps(struct brw_context *brw,
 414                                           uint32_t sampler_offset);
 415
 416 void
 417 gen7_blorp_emit_clear_params(struct brw_context *brw,
 418                              const struct brw_blorp_params *params);
 419
 420 void
 421 gen7_blorp_emit_constant_ps(struct brw_context *brw,
 422                             uint32_t wm_push_const_offset);
 423
 424 void
 425 gen7_blorp_emit_constant_ps_disable(struct brw_context *brw);
 426
 427 void
 428 gen7_blorp_emit_primitive(struct brw_context *brw,
 429                           const struct brw_blorp_params *params);
 430
 431 /** \} */
 432
 433 #ifdef __cplusplus
 434 } /* end extern "C" */
 435 #endif /* __cplusplus */