2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "main/context.h"
25 #include "main/teximage.h"
26 #include "main/fbobject.h"
28 #include "intel_fbo.h"
30 #include "brw_blorp.h"
31 #include "brw_context.h"
32 #include "brw_blorp_blit_eu.h"
33 #include "brw_state.h"
34 #include "brw_meta_util.h"
36 #define FILE_DEBUG_FLAG DEBUG_BLORP
38 static struct intel_mipmap_tree
*
39 find_miptree(GLbitfield buffer_bit
, struct intel_renderbuffer
*irb
)
41 struct intel_mipmap_tree
*mt
= irb
->mt
;
42 if (buffer_bit
== GL_STENCIL_BUFFER_BIT
&& mt
->stencil_mt
)
49 * Note: if the src (or dst) is a 2D multisample array texture on Gen7+ using
50 * INTEL_MSAA_LAYOUT_UMS or INTEL_MSAA_LAYOUT_CMS, src_layer (dst_layer) is
51 * the physical layer holding sample 0. So, for example, if
52 * src_mt->num_samples == 4, then logical layer n corresponds to src_layer ==
56 brw_blorp_blit_miptrees(struct brw_context
*brw
,
57 struct intel_mipmap_tree
*src_mt
,
58 unsigned src_level
, unsigned src_layer
,
59 mesa_format src_format
, int src_swizzle
,
60 struct intel_mipmap_tree
*dst_mt
,
61 unsigned dst_level
, unsigned dst_layer
,
62 mesa_format dst_format
,
63 float src_x0
, float src_y0
,
64 float src_x1
, float src_y1
,
65 float dst_x0
, float dst_y0
,
66 float dst_x1
, float dst_y1
,
67 GLenum filter
, bool mirror_x
, bool mirror_y
,
68 bool decode_srgb
, bool encode_srgb
)
70 /* Get ready to blit. This includes depth resolving the src and dst
71 * buffers if necessary. Note: it's not necessary to do a color resolve on
72 * the destination buffer because we use the standard render path to render
73 * to destination color buffers, and the standard render path is
75 * Lossless compression is only introduced for gen9 onwards whereas
76 * blorp is not supported even for gen8. Therefore it should be impossible
77 * to end up here with single sampled compressed surfaces.
79 assert(!intel_miptree_is_lossless_compressed(brw
, src_mt
));
80 assert(!intel_miptree_is_lossless_compressed(brw
, dst_mt
));
81 intel_miptree_resolve_color(brw
, src_mt
, 0);
82 intel_miptree_slice_resolve_depth(brw
, src_mt
, src_level
, src_layer
);
83 intel_miptree_slice_resolve_depth(brw
, dst_mt
, dst_level
, dst_layer
);
85 DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
86 "to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
88 src_mt
->num_samples
, _mesa_get_format_name(src_mt
->format
), src_mt
,
89 src_level
, src_layer
, src_x0
, src_y0
, src_x1
, src_y1
,
90 dst_mt
->num_samples
, _mesa_get_format_name(dst_mt
->format
), dst_mt
,
91 dst_level
, dst_layer
, dst_x0
, dst_y0
, dst_x1
, dst_y1
,
94 if (!decode_srgb
&& _mesa_get_format_color_encoding(src_format
) == GL_SRGB
)
95 src_format
= _mesa_get_srgb_format_linear(src_format
);
97 if (!encode_srgb
&& _mesa_get_format_color_encoding(dst_format
) == GL_SRGB
)
98 dst_format
= _mesa_get_srgb_format_linear(dst_format
);
100 brw_blorp_blit_params
params(brw
,
101 src_mt
, src_level
, src_layer
, src_format
,
102 dst_mt
, dst_level
, dst_layer
, dst_format
,
107 filter
, mirror_x
, mirror_y
);
108 params
.src
.swizzle
= src_swizzle
;
110 brw_blorp_exec(brw
, ¶ms
);
112 intel_miptree_slice_set_needs_hiz_resolve(dst_mt
, dst_level
, dst_layer
);
116 blorp_get_texture_swizzle(const struct intel_renderbuffer
*irb
)
118 return irb
->Base
.Base
._BaseFormat
== GL_RGB
?
119 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_Y
, SWIZZLE_Z
, SWIZZLE_ONE
) :
124 do_blorp_blit(struct brw_context
*brw
, GLbitfield buffer_bit
,
125 struct intel_renderbuffer
*src_irb
, mesa_format src_format
,
126 struct intel_renderbuffer
*dst_irb
, mesa_format dst_format
,
127 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
128 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
129 GLenum filter
, bool mirror_x
, bool mirror_y
)
131 /* Find source/dst miptrees */
132 struct intel_mipmap_tree
*src_mt
= find_miptree(buffer_bit
, src_irb
);
133 struct intel_mipmap_tree
*dst_mt
= find_miptree(buffer_bit
, dst_irb
);
135 const bool es3
= _mesa_is_gles3(&brw
->ctx
);
137 brw_blorp_blit_miptrees(brw
,
138 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
139 src_format
, blorp_get_texture_swizzle(src_irb
),
140 dst_mt
, dst_irb
->mt_level
, dst_irb
->mt_layer
,
142 srcX0
, srcY0
, srcX1
, srcY1
,
143 dstX0
, dstY0
, dstX1
, dstY1
,
144 filter
, mirror_x
, mirror_y
,
147 dst_irb
->need_downsample
= true;
151 try_blorp_blit(struct brw_context
*brw
,
152 const struct gl_framebuffer
*read_fb
,
153 const struct gl_framebuffer
*draw_fb
,
154 GLfloat srcX0
, GLfloat srcY0
, GLfloat srcX1
, GLfloat srcY1
,
155 GLfloat dstX0
, GLfloat dstY0
, GLfloat dstX1
, GLfloat dstY1
,
156 GLenum filter
, GLbitfield buffer_bit
)
158 struct gl_context
*ctx
= &brw
->ctx
;
160 /* Sync up the state of window system buffers. We need to do this before
161 * we go looking for the buffers.
163 intel_prepare_render(brw
);
165 bool mirror_x
, mirror_y
;
166 if (brw_meta_mirror_clip_and_scissor(ctx
, read_fb
, draw_fb
,
167 &srcX0
, &srcY0
, &srcX1
, &srcY1
,
168 &dstX0
, &dstY0
, &dstX1
, &dstY1
,
169 &mirror_x
, &mirror_y
))
173 struct intel_renderbuffer
*src_irb
;
174 struct intel_renderbuffer
*dst_irb
;
175 struct intel_mipmap_tree
*src_mt
;
176 struct intel_mipmap_tree
*dst_mt
;
177 switch (buffer_bit
) {
178 case GL_COLOR_BUFFER_BIT
:
179 src_irb
= intel_renderbuffer(read_fb
->_ColorReadBuffer
);
180 for (unsigned i
= 0; i
< draw_fb
->_NumColorDrawBuffers
; ++i
) {
181 dst_irb
= intel_renderbuffer(draw_fb
->_ColorDrawBuffers
[i
]);
183 do_blorp_blit(brw
, buffer_bit
,
184 src_irb
, src_irb
->Base
.Base
.Format
,
185 dst_irb
, dst_irb
->Base
.Base
.Format
,
186 srcX0
, srcY0
, srcX1
, srcY1
,
187 dstX0
, dstY0
, dstX1
, dstY1
,
188 filter
, mirror_x
, mirror_y
);
191 case GL_DEPTH_BUFFER_BIT
:
193 intel_renderbuffer(read_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
195 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_DEPTH
].Renderbuffer
);
196 src_mt
= find_miptree(buffer_bit
, src_irb
);
197 dst_mt
= find_miptree(buffer_bit
, dst_irb
);
199 /* We can't handle format conversions between Z24 and other formats
200 * since we have to lie about the surface format. See the comments in
201 * brw_blorp_surface_info::set().
203 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
204 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
))
207 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
208 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
209 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
210 filter
, mirror_x
, mirror_y
);
212 case GL_STENCIL_BUFFER_BIT
:
214 intel_renderbuffer(read_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
216 intel_renderbuffer(draw_fb
->Attachment
[BUFFER_STENCIL
].Renderbuffer
);
217 do_blorp_blit(brw
, buffer_bit
, src_irb
, MESA_FORMAT_NONE
,
218 dst_irb
, MESA_FORMAT_NONE
, srcX0
, srcY0
,
219 srcX1
, srcY1
, dstX0
, dstY0
, dstX1
, dstY1
,
220 filter
, mirror_x
, mirror_y
);
223 unreachable("not reached");
230 brw_blorp_copytexsubimage(struct brw_context
*brw
,
231 struct gl_renderbuffer
*src_rb
,
232 struct gl_texture_image
*dst_image
,
234 int srcX0
, int srcY0
,
235 int dstX0
, int dstY0
,
236 int width
, int height
)
238 struct gl_context
*ctx
= &brw
->ctx
;
239 struct intel_renderbuffer
*src_irb
= intel_renderbuffer(src_rb
);
240 struct intel_texture_image
*intel_image
= intel_texture_image(dst_image
);
242 /* No pixel transfer operations (zoom, bias, mapping), just a blit */
243 if (brw
->ctx
._ImageTransferState
)
246 /* Sync up the state of window system buffers. We need to do this before
247 * we go looking at the src renderbuffer's miptree.
249 intel_prepare_render(brw
);
251 struct intel_mipmap_tree
*src_mt
= src_irb
->mt
;
252 struct intel_mipmap_tree
*dst_mt
= intel_image
->mt
;
254 /* There is support only for four and eight samples. */
255 if (src_mt
->num_samples
== 2 || dst_mt
->num_samples
== 2 ||
256 src_mt
->num_samples
> 8 || dst_mt
->num_samples
> 8)
259 /* BLORP is only supported from Gen6 onwards. */
263 if (_mesa_get_format_base_format(src_rb
->Format
) !=
264 _mesa_get_format_base_format(dst_image
->TexFormat
)) {
268 /* We can't handle format conversions between Z24 and other formats since
269 * we have to lie about the surface format. See the comments in
270 * brw_blorp_surface_info::set().
272 if ((src_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
) !=
273 (dst_mt
->format
== MESA_FORMAT_Z24_UNORM_X8_UINT
)) {
277 if (!brw
->format_supported_as_render_target
[dst_image
->TexFormat
])
280 /* Source clipping shouldn't be necessary, since copytexsubimage (in
281 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
284 * Destination clipping shouldn't be necessary since the restrictions on
285 * glCopyTexSubImage prevent the user from specifying a destination rectangle
286 * that falls outside the bounds of the destination texture.
287 * See error_check_subtexture_dimensions().
290 int srcY1
= srcY0
+ height
;
291 int srcX1
= srcX0
+ width
;
292 int dstX1
= dstX0
+ width
;
293 int dstY1
= dstY0
+ height
;
295 /* Account for the fact that in the system framebuffer, the origin is at
298 bool mirror_y
= false;
299 if (_mesa_is_winsys_fbo(ctx
->ReadBuffer
)) {
300 GLint tmp
= src_rb
->Height
- srcY0
;
301 srcY0
= src_rb
->Height
- srcY1
;
306 /* Account for face selection and texture view MinLayer */
307 int dst_slice
= slice
+ dst_image
->TexObject
->MinLayer
+ dst_image
->Face
;
308 int dst_level
= dst_image
->Level
+ dst_image
->TexObject
->MinLevel
;
310 brw_blorp_blit_miptrees(brw
,
311 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
312 src_rb
->Format
, blorp_get_texture_swizzle(src_irb
),
313 dst_mt
, dst_level
, dst_slice
,
314 dst_image
->TexFormat
,
315 srcX0
, srcY0
, srcX1
, srcY1
,
316 dstX0
, dstY0
, dstX1
, dstY1
,
317 GL_NEAREST
, false, mirror_y
,
320 /* If we're copying to a packed depth stencil texture and the source
321 * framebuffer has separate stencil, we need to also copy the stencil data
324 src_rb
= ctx
->ReadBuffer
->Attachment
[BUFFER_STENCIL
].Renderbuffer
;
325 if (_mesa_get_format_bits(dst_image
->TexFormat
, GL_STENCIL_BITS
) > 0 &&
327 src_irb
= intel_renderbuffer(src_rb
);
328 src_mt
= src_irb
->mt
;
330 if (src_mt
->stencil_mt
)
331 src_mt
= src_mt
->stencil_mt
;
332 if (dst_mt
->stencil_mt
)
333 dst_mt
= dst_mt
->stencil_mt
;
335 if (src_mt
!= dst_mt
) {
336 brw_blorp_blit_miptrees(brw
,
337 src_mt
, src_irb
->mt_level
, src_irb
->mt_layer
,
339 blorp_get_texture_swizzle(src_irb
),
340 dst_mt
, dst_level
, dst_slice
,
342 srcX0
, srcY0
, srcX1
, srcY1
,
343 dstX0
, dstY0
, dstX1
, dstY1
,
344 GL_NEAREST
, false, mirror_y
,
354 brw_blorp_framebuffer(struct brw_context
*brw
,
355 struct gl_framebuffer
*readFb
,
356 struct gl_framebuffer
*drawFb
,
357 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
358 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
359 GLbitfield mask
, GLenum filter
)
361 /* BLORP is not supported before Gen6. */
365 /* There is support only for four and eight samples. */
366 if (readFb
->Visual
.samples
== 2 || drawFb
->Visual
.samples
== 2 ||
367 readFb
->Visual
.samples
> 8 || drawFb
->Visual
.samples
> 8)
370 static GLbitfield buffer_bits
[] = {
373 GL_STENCIL_BUFFER_BIT
,
376 for (unsigned int i
= 0; i
< ARRAY_SIZE(buffer_bits
); ++i
) {
377 if ((mask
& buffer_bits
[i
]) &&
378 try_blorp_blit(brw
, readFb
, drawFb
,
379 srcX0
, srcY0
, srcX1
, srcY1
,
380 dstX0
, dstY0
, dstX1
, dstY1
,
381 filter
, buffer_bits
[i
])) {
382 mask
&= ~buffer_bits
[i
];
391 * Enum to specify the order of arguments in a sampler message
393 enum sampler_message_arg
395 SAMPLER_MESSAGE_ARG_U_FLOAT
,
396 SAMPLER_MESSAGE_ARG_V_FLOAT
,
397 SAMPLER_MESSAGE_ARG_U_INT
,
398 SAMPLER_MESSAGE_ARG_V_INT
,
399 SAMPLER_MESSAGE_ARG_R_INT
,
400 SAMPLER_MESSAGE_ARG_SI_INT
,
401 SAMPLER_MESSAGE_ARG_MCS_INT
,
402 SAMPLER_MESSAGE_ARG_ZERO_INT
,
406 * Generator for WM programs used in BLORP blits.
408 * The bulk of the work done by the WM program is to wrap and unwrap the
409 * coordinate transformations used by the hardware to store surfaces in
410 * memory. The hardware transforms a pixel location (X, Y, S) (where S is the
411 * sample index for a multisampled surface) to a memory offset by the
412 * following formulas:
414 * offset = tile(tiling_format, encode_msaa(num_samples, layout, X, Y, S))
415 * (X, Y, S) = decode_msaa(num_samples, layout, detile(tiling_format, offset))
417 * For a single-sampled surface, or for a multisampled surface using
418 * INTEL_MSAA_LAYOUT_UMS, encode_msaa() and decode_msaa are the identity
421 * encode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
422 * decode_msaa(1, NONE, X, Y, 0) = (X, Y, 0)
423 * encode_msaa(n, UMS, X, Y, S) = (X, Y, S)
424 * decode_msaa(n, UMS, X, Y, S) = (X, Y, S)
426 * For a 4x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
427 * embeds the sample number into bit 1 of the X and Y coordinates:
429 * encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
430 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
431 * Y' = (Y & ~0b1 ) << 1 | (S & 0b10) | (Y & 0b1)
432 * decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
433 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
434 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
435 * S = (Y & 0b10) | (X & 0b10) >> 1
437 * For an 8x multisampled surface using INTEL_MSAA_LAYOUT_IMS, encode_msaa()
438 * embeds the sample number into bits 1 and 2 of the X coordinate and bit 1 of
441 * encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
442 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1 | (X & 0b1)
443 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
444 * decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
445 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
446 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
447 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
449 * For X tiling, tile() combines together the low-order bits of the X and Y
450 * coordinates in the pattern 0byyyxxxxxxxxx, creating 4k tiles that are 512
451 * bytes wide and 8 rows high:
453 * tile(x_tiled, X, Y, S) = A
454 * where A = tile_num << 12 | offset
455 * tile_num = (Y' >> 3) * tile_pitch + (X' >> 9)
456 * offset = (Y' & 0b111) << 9
457 * | (X & 0b111111111)
459 * Y' = Y + S * qpitch
460 * detile(x_tiled, A) = (X, Y, S)
464 * Y' = (tile_num / tile_pitch) << 3
465 * | (A & 0b111000000000) >> 9
466 * X' = (tile_num % tile_pitch) << 9
467 * | (A & 0b111111111)
469 * (In all tiling formulas, cpp is the number of bytes occupied by a single
470 * sample ("chars per pixel"), tile_pitch is the number of 4k tiles required
471 * to fill the width of the surface, and qpitch is the spacing (in rows)
472 * between array slices).
474 * For Y tiling, tile() combines together the low-order bits of the X and Y
475 * coordinates in the pattern 0bxxxyyyyyxxxx, creating 4k tiles that are 128
476 * bytes wide and 32 rows high:
478 * tile(y_tiled, X, Y, S) = A
479 * where A = tile_num << 12 | offset
480 * tile_num = (Y' >> 5) * tile_pitch + (X' >> 7)
481 * offset = (X' & 0b1110000) << 5
482 * | (Y' & 0b11111) << 4
485 * Y' = Y + S * qpitch
486 * detile(y_tiled, A) = (X, Y, S)
490 * Y' = (tile_num / tile_pitch) << 5
491 * | (A & 0b111110000) >> 4
492 * X' = (tile_num % tile_pitch) << 7
493 * | (A & 0b111000000000) >> 5
496 * For W tiling, tile() combines together the low-order bits of the X and Y
497 * coordinates in the pattern 0bxxxyyyyxyxyx, creating 4k tiles that are 64
498 * bytes wide and 64 rows high (note that W tiling is only used for stencil
499 * buffers, which always have cpp = 1 and S=0):
501 * tile(w_tiled, X, Y, S) = A
502 * where A = tile_num << 12 | offset
503 * tile_num = (Y' >> 6) * tile_pitch + (X' >> 6)
504 * offset = (X' & 0b111000) << 6
505 * | (Y' & 0b111100) << 3
506 * | (X' & 0b100) << 2
512 * Y' = Y + S * qpitch
513 * detile(w_tiled, A) = (X, Y, S)
514 * where X = X' / cpp = X'
515 * Y = Y' % qpitch = Y'
517 * Y' = (tile_num / tile_pitch) << 6
518 * | (A & 0b111100000) >> 3
519 * | (A & 0b1000) >> 2
521 * X' = (tile_num % tile_pitch) << 6
522 * | (A & 0b111000000000) >> 6
523 * | (A & 0b10000) >> 2
527 * Finally, for a non-tiled surface, tile() simply combines together the X and
528 * Y coordinates in the natural way:
530 * tile(untiled, X, Y, S) = A
531 * where A = Y * pitch + X'
533 * Y' = Y + S * qpitch
534 * detile(untiled, A) = (X, Y, S)
541 * (In these formulas, pitch is the number of bytes occupied by a single row
544 class brw_blorp_blit_program
: public brw_blorp_eu_emitter
547 brw_blorp_blit_program(struct brw_context
*brw
,
548 const brw_blorp_blit_prog_key
*key
);
550 const GLuint
*compile(struct brw_context
*brw
, bool debug_flag
,
551 GLuint
*program_size
);
553 brw_blorp_prog_data prog_data
;
557 void alloc_push_const_regs(int base_reg
);
558 void compute_frag_coords();
559 void translate_tiling(bool old_tiled_w
, bool new_tiled_w
);
560 void encode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
561 void decode_msaa(unsigned num_samples
, intel_msaa_layout layout
);
562 void translate_dst_to_src();
563 void clamp_tex_coords(struct brw_reg regX
, struct brw_reg regY
,
564 struct brw_reg clampX0
, struct brw_reg clampY0
,
565 struct brw_reg clampX1
, struct brw_reg clampY1
);
566 void single_to_blend();
567 void manual_blend_average(unsigned num_samples
);
568 void manual_blend_bilinear(unsigned num_samples
);
569 void sample(struct brw_reg dst
);
570 void texel_fetch(struct brw_reg dst
);
572 void texture_lookup(struct brw_reg dst
, enum opcode op
,
573 const sampler_message_arg
*args
, int num_args
);
574 void render_target_write();
577 * Base-2 logarithm of the maximum number of samples that can be blended.
579 static const unsigned LOG2_MAX_BLEND_SAMPLES
= 3;
581 struct brw_context
*brw
;
582 const brw_blorp_blit_prog_key
*key
;
584 /* Thread dispatch header */
587 /* Pixel X/Y coordinates (always in R1). */
591 struct brw_reg dst_x0
;
592 struct brw_reg dst_x1
;
593 struct brw_reg dst_y0
;
594 struct brw_reg dst_y1
;
595 /* Top right coordinates of the rectangular grid used for scaled blitting */
596 struct brw_reg rect_grid_x1
;
597 struct brw_reg rect_grid_y1
;
599 struct brw_reg multiplier
;
600 struct brw_reg offset
;
601 } x_transform
, y_transform
;
602 struct brw_reg src_z
;
604 /* Data read from texture (4 vec16's per array element) */
605 struct brw_reg texture_data
[LOG2_MAX_BLEND_SAMPLES
+ 1];
607 /* Auxiliary storage for the contents of the MCS surface.
609 * Since the sampler always returns 8 registers worth of data, this is 8
610 * registers wide, even though we only use the first 2 registers of it.
612 struct brw_reg mcs_data
;
614 /* X coordinates. We have two of them so that we can perform coordinate
615 * transformations easily.
617 struct brw_reg x_coords
[2];
619 /* Y coordinates. We have two of them so that we can perform coordinate
620 * transformations easily.
622 struct brw_reg y_coords
[2];
624 /* X, Y coordinates of the pixel from which we need to fetch the specific
625 * sample. These are used for multisample scaled blitting.
627 struct brw_reg x_sample_coords
;
628 struct brw_reg y_sample_coords
;
630 /* Fractional parts of the x and y coordinates, used as bilinear interpolation coefficients */
631 struct brw_reg x_frac
;
632 struct brw_reg y_frac
;
634 /* Which element of x_coords and y_coords is currently in use.
638 /* True if, at the point in the program currently being compiled, the
639 * sample index is known to be zero.
643 /* Register storing the sample index when s_is_zero is false. */
644 struct brw_reg sample_index
;
650 /* MRF used for sampling and render target writes */
654 brw_blorp_blit_program::brw_blorp_blit_program(
655 struct brw_context
*brw
, const brw_blorp_blit_prog_key
*key
)
656 : brw_blorp_eu_emitter(), brw(brw
), key(key
)
661 brw_blorp_blit_program::compile(struct brw_context
*brw
, bool debug_flag
,
662 GLuint
*program_size
)
665 if (key
->dst_tiled_w
&& key
->rt_samples
> 0) {
666 /* If the destination image is W tiled and multisampled, then the thread
667 * must be dispatched once per sample, not once per pixel. This is
668 * necessary because after conversion between W and Y tiling, there's no
669 * guarantee that all samples corresponding to a single pixel will still
672 assert(key
->persample_msaa_dispatch
);
676 /* We are blending, which means we won't have an opportunity to
677 * translate the tiling and sample count for the texture surface. So
678 * the surface state for the texture must be configured with the correct
679 * tiling and sample count.
681 assert(!key
->src_tiled_w
);
682 assert(key
->tex_samples
== key
->src_samples
);
683 assert(key
->tex_layout
== key
->src_layout
);
684 assert(key
->tex_samples
> 0);
687 if (key
->persample_msaa_dispatch
) {
688 /* It only makes sense to do persample dispatch if the render target is
689 * configured as multisampled.
691 assert(key
->rt_samples
> 0);
694 /* Make sure layout is consistent with sample count */
695 assert((key
->tex_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
696 (key
->tex_samples
== 0));
697 assert((key
->rt_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
698 (key
->rt_samples
== 0));
699 assert((key
->src_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
700 (key
->src_samples
== 0));
701 assert((key
->dst_layout
== INTEL_MSAA_LAYOUT_NONE
) ==
702 (key
->dst_samples
== 0));
704 /* Set up prog_data */
705 memset(&prog_data
, 0, sizeof(prog_data
));
706 prog_data
.persample_msaa_dispatch
= key
->persample_msaa_dispatch
;
709 compute_frag_coords();
711 /* Render target and texture hardware don't support W tiling until Gen8. */
712 const bool rt_tiled_w
= false;
713 const bool tex_tiled_w
= brw
->gen
>= 8 && key
->src_tiled_w
;
715 /* The address that data will be written to is determined by the
716 * coordinates supplied to the WM thread and the tiling and sample count of
717 * the render target, according to the formula:
719 * (X, Y, S) = decode_msaa(rt_samples, detile(rt_tiling, offset))
721 * If the actual tiling and sample count of the destination surface are not
722 * the same as the configuration of the render target, then these
723 * coordinates are wrong and we have to adjust them to compensate for the
726 if (rt_tiled_w
!= key
->dst_tiled_w
||
727 key
->rt_samples
!= key
->dst_samples
||
728 key
->rt_layout
!= key
->dst_layout
) {
729 encode_msaa(key
->rt_samples
, key
->rt_layout
);
730 /* Now (X, Y, S) = detile(rt_tiling, offset) */
731 translate_tiling(rt_tiled_w
, key
->dst_tiled_w
);
732 /* Now (X, Y, S) = detile(dst_tiling, offset) */
733 decode_msaa(key
->dst_samples
, key
->dst_layout
);
736 /* Now (X, Y, S) = decode_msaa(dst_samples, detile(dst_tiling, offset)).
738 * That is: X, Y and S now contain the true coordinates and sample index of
739 * the data that the WM thread should output.
741 * If we need to kill pixels that are outside the destination rectangle,
742 * now is the time to do it.
746 emit_kill_if_outside_rect(x_coords
[xy_coord_index
],
747 y_coords
[xy_coord_index
],
748 dst_x0
, dst_x1
, dst_y0
, dst_y1
);
750 /* Next, apply a translation to obtain coordinates in the source image. */
751 translate_dst_to_src();
753 /* If the source image is not multisampled, then we want to fetch sample
754 * number 0, because that's the only sample there is.
756 if (key
->src_samples
== 0)
759 /* X, Y, and S are now the coordinates of the pixel in the source image
760 * that we want to texture from. Exception: if we are blending, then S is
761 * irrelevant, because we are going to fetch all samples.
763 if (key
->blend
&& !key
->blit_scaled
) {
765 /* Gen6 hardware an automatically blend using the SAMPLE message */
767 sample(texture_data
[0]);
769 /* Gen7+ hardware doesn't automaticaly blend. */
770 manual_blend_average(key
->src_samples
);
772 } else if(key
->blend
&& key
->blit_scaled
) {
773 manual_blend_bilinear(key
->src_samples
);
775 /* We aren't blending, which means we just want to fetch a single sample
776 * from the source surface. The address that we want to fetch from is
777 * related to the X, Y and S values according to the formula:
779 * (X, Y, S) = decode_msaa(src_samples, detile(src_tiling, offset)).
781 * If the actual tiling and sample count of the source surface are not
782 * the same as the configuration of the texture, then we need to adjust
783 * the coordinates to compensate for the difference.
785 if ((tex_tiled_w
!= key
->src_tiled_w
||
786 key
->tex_samples
!= key
->src_samples
||
787 key
->tex_layout
!= key
->src_layout
) &&
788 !key
->bilinear_filter
) {
789 encode_msaa(key
->src_samples
, key
->src_layout
);
790 /* Now (X, Y, S) = detile(src_tiling, offset) */
791 translate_tiling(key
->src_tiled_w
, tex_tiled_w
);
792 /* Now (X, Y, S) = detile(tex_tiling, offset) */
793 decode_msaa(key
->tex_samples
, key
->tex_layout
);
796 if (key
->bilinear_filter
) {
797 sample(texture_data
[0]);
800 /* Now (X, Y, S) = decode_msaa(tex_samples, detile(tex_tiling, offset)).
802 * In other words: X, Y, and S now contain values which, when passed to
803 * the texturing unit, will cause data to be read from the correct
804 * memory location. So we can fetch the texel now.
806 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
808 texel_fetch(texture_data
[0]);
812 /* Finally, write the fetched (or blended) value to the render target and
813 * terminate the thread.
815 render_target_write();
817 return get_program(brw
, debug_flag
, program_size
);
821 brw_blorp_blit_program::alloc_push_const_regs(int base_reg
)
823 #define CONST_LOC(name) offsetof(brw_blorp_wm_push_constants, name)
824 #define ALLOC_REG(name, type) \
826 retype(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, \
827 base_reg + CONST_LOC(name) / 32, \
828 (CONST_LOC(name) % 32) / 4), type)
830 ALLOC_REG(dst_x0
, BRW_REGISTER_TYPE_UD
);
831 ALLOC_REG(dst_x1
, BRW_REGISTER_TYPE_UD
);
832 ALLOC_REG(dst_y0
, BRW_REGISTER_TYPE_UD
);
833 ALLOC_REG(dst_y1
, BRW_REGISTER_TYPE_UD
);
834 ALLOC_REG(rect_grid_x1
, BRW_REGISTER_TYPE_F
);
835 ALLOC_REG(rect_grid_y1
, BRW_REGISTER_TYPE_F
);
836 ALLOC_REG(x_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
837 ALLOC_REG(x_transform
.offset
, BRW_REGISTER_TYPE_F
);
838 ALLOC_REG(y_transform
.multiplier
, BRW_REGISTER_TYPE_F
);
839 ALLOC_REG(y_transform
.offset
, BRW_REGISTER_TYPE_F
);
840 ALLOC_REG(src_z
, BRW_REGISTER_TYPE_UD
);
846 brw_blorp_blit_program::alloc_regs()
849 this->R0
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
850 this->R1
= retype(brw_vec8_grf(reg
++, 0), BRW_REGISTER_TYPE_UW
);
851 prog_data
.first_curbe_grf
= reg
;
852 alloc_push_const_regs(reg
);
853 reg
+= BRW_BLORP_NUM_PUSH_CONST_REGS
;
854 for (unsigned i
= 0; i
< ARRAY_SIZE(texture_data
); ++i
) {
855 this->texture_data
[i
] =
856 retype(vec16(brw_vec8_grf(reg
, 0)), key
->texture_data_type
);
860 retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
); reg
+= 8;
862 for (int i
= 0; i
< 2; ++i
) {
864 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
867 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
871 if (key
->blit_scaled
&& key
->blend
) {
872 this->x_sample_coords
= brw_vec8_grf(reg
, 0);
874 this->y_sample_coords
= brw_vec8_grf(reg
, 0);
876 this->x_frac
= brw_vec8_grf(reg
, 0);
878 this->y_frac
= brw_vec8_grf(reg
, 0);
882 this->xy_coord_index
= 0;
884 = retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
886 this->t1
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
888 this->t2
= retype(brw_vec8_grf(reg
, 0), BRW_REGISTER_TYPE_UD
);
891 /* Make sure we didn't run out of registers */
892 assert(reg
<= GEN7_MRF_HACK_START
);
895 this->base_mrf
= mrf
;
898 /* In the code that follows, X and Y can be used to quickly refer to the
899 * active elements of x_coords and y_coords, and Xp and Yp ("X prime" and "Y
900 * prime") to the inactive elements.
902 * S can be used to quickly refer to sample_index.
904 #define X x_coords[xy_coord_index]
905 #define Y y_coords[xy_coord_index]
906 #define Xp x_coords[!xy_coord_index]
907 #define Yp y_coords[!xy_coord_index]
908 #define S sample_index
910 /* Quickly swap the roles of (X, Y) and (Xp, Yp). Saves us from having to do
911 * MOVs to transfor (Xp, Yp) to (X, Y) after a coordinate transformation.
913 #define SWAP_XY_AND_XPYP() xy_coord_index = !xy_coord_index;
916 * Emit code to compute the X and Y coordinates of the pixels being rendered
917 * by this WM invocation.
919 * Assuming the render target is set up for Y tiling, these (X, Y) values are
920 * related to the address offset where outputs will be written by the formula:
922 * (X, Y, S) = decode_msaa(detile(offset)).
924 * (See brw_blorp_blit_program).
927 brw_blorp_blit_program::compute_frag_coords()
929 /* R1.2[15:0] = X coordinate of upper left pixel of subspan 0 (pixel 0)
930 * R1.3[15:0] = X coordinate of upper left pixel of subspan 1 (pixel 4)
931 * R1.4[15:0] = X coordinate of upper left pixel of subspan 2 (pixel 8)
932 * R1.5[15:0] = X coordinate of upper left pixel of subspan 3 (pixel 12)
934 * Pixels within a subspan are laid out in this arrangement:
938 * So, to compute the coordinates of each pixel, we need to read every 2nd
939 * 16-bit value (vstride=2) from R1, starting at the 4th 16-bit value
940 * (suboffset=4), and duplicate each value 4 times (hstride=0, width=4).
941 * In other words, the data we want to access is R1.4<2;4,0>UW.
943 * Then, we need to add the repeating sequence (0, 1, 0, 1, ...) to the
944 * result, since pixels n+1 and n+3 are in the right half of the subspan.
946 emit_add(vec16(retype(X
, BRW_REGISTER_TYPE_UW
)),
947 stride(suboffset(R1
, 4), 2, 4, 0), brw_imm_v(0x10101010));
949 /* Similarly, Y coordinates for subspans come from R1.2[31:16] through
950 * R1.5[31:16], so to get pixel Y coordinates we need to start at the 5th
951 * 16-bit value instead of the 4th (R1.5<2;4,0>UW instead of
954 * And we need to add the repeating sequence (0, 0, 1, 1, ...), since
955 * pixels n+2 and n+3 are in the bottom half of the subspan.
957 emit_add(vec16(retype(Y
, BRW_REGISTER_TYPE_UW
)),
958 stride(suboffset(R1
, 5), 2, 4, 0), brw_imm_v(0x11001100));
960 /* Move the coordinates to UD registers. */
961 emit_mov(vec16(Xp
), retype(X
, BRW_REGISTER_TYPE_UW
));
962 emit_mov(vec16(Yp
), retype(Y
, BRW_REGISTER_TYPE_UW
));
965 if (key
->persample_msaa_dispatch
) {
966 switch (key
->rt_samples
) {
968 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 4.
969 * Therefore, subspan 0 will represent sample 0, subspan 1 will
970 * represent sample 1, and so on.
972 * So we need to populate S with the sequence (0, 0, 0, 0, 1, 1, 1,
973 * 1, 2, 2, 2, 2, 3, 3, 3, 3). The easiest way to do this is to
974 * populate a temporary variable with the sequence (0, 1, 2, 3), and
975 * then copy from it using vstride=1, width=4, hstride=0.
977 struct brw_reg t1_uw1
= retype(t1
, BRW_REGISTER_TYPE_UW
);
978 emit_mov(vec16(t1_uw1
), brw_imm_v(0x3210));
979 /* Move to UD sample_index register. */
980 emit_mov_8(S
, stride(t1_uw1
, 1, 4, 0));
981 emit_mov_8(offset(S
, 1), suboffset(stride(t1_uw1
, 1, 4, 0), 2));
985 /* The WM will be run in MSDISPMODE_PERSAMPLE with num_samples == 8.
986 * Therefore, subspan 0 will represent sample N (where N is 0 or 4),
987 * subspan 1 will represent sample 1, and so on. We can find the
988 * value of N by looking at R0.0 bits 7:6 ("Starting Sample Pair
989 * Index") and multiplying by two (since samples are always delivered
990 * in pairs). That is, we compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 &
993 * Then we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1, 2,
994 * 2, 2, 2, 3, 3, 3, 3), which we compute by populating a temporary
995 * variable with the sequence (0, 1, 2, 3), and then reading from it
996 * using vstride=1, width=4, hstride=0.
998 struct brw_reg t1_ud1
= vec1(retype(t1
, BRW_REGISTER_TYPE_UD
));
999 struct brw_reg t2_uw1
= retype(t2
, BRW_REGISTER_TYPE_UW
);
1000 struct brw_reg r0_ud1
= vec1(retype(R0
, BRW_REGISTER_TYPE_UD
));
1001 emit_and(t1_ud1
, r0_ud1
, brw_imm_ud(0xc0));
1002 emit_shr(t1_ud1
, t1_ud1
, brw_imm_ud(5));
1003 emit_mov(vec16(t2_uw1
), brw_imm_v(0x3210));
1004 emit_add(vec16(S
), retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1005 stride(t2_uw1
, 1, 4, 0));
1006 emit_add_8(offset(S
, 1),
1007 retype(t1_ud1
, BRW_REGISTER_TYPE_UW
),
1008 suboffset(stride(t2_uw1
, 1, 4, 0), 2));
1012 unreachable("Unrecognized sample count in "
1013 "brw_blorp_blit_program::compute_frag_coords()");
1017 /* Either the destination surface is single-sampled, or the WM will be
1018 * run in MSDISPMODE_PERPIXEL (which causes a single fragment dispatch
1019 * per pixel). In either case, it's not meaningful to compute a sample
1020 * value. Just set it to 0.
1027 * Emit code to compensate for the difference between Y and W tiling.
1029 * This code modifies the X and Y coordinates according to the formula:
1031 * (X', Y', S') = detile(new_tiling, tile(old_tiling, X, Y, S))
1033 * (See brw_blorp_blit_program).
1035 * It can only translate between W and Y tiling, so new_tiling and old_tiling
1036 * are booleans where true represents W tiling and false represents Y tiling.
1039 brw_blorp_blit_program::translate_tiling(bool old_tiled_w
, bool new_tiled_w
)
1041 if (old_tiled_w
== new_tiled_w
)
1044 /* In the code that follows, we can safely assume that S = 0, because W
1045 * tiling formats always use IMS layout.
1050 /* Given X and Y coordinates that describe an address using Y tiling,
1051 * translate to the X and Y coordinates that describe the same address
1054 * If we break down the low order bits of X and Y, using a
1055 * single letter to represent each low-order bit:
1057 * X = A << 7 | 0bBCDEFGH
1058 * Y = J << 5 | 0bKLMNP (1)
1060 * Then we can apply the Y tiling formula to see the memory offset being
1063 * offset = (J * tile_pitch + A) << 12 | 0bBCDKLMNPEFGH (2)
1065 * If we apply the W detiling formula to this memory location, that the
1066 * corresponding X' and Y' coordinates are:
1068 * X' = A << 6 | 0bBCDPFH (3)
1069 * Y' = J << 6 | 0bKLMNEG
1071 * Combining (1) and (3), we see that to transform (X, Y) to (X', Y'),
1072 * we need to make the following computation:
1074 * X' = (X & ~0b1011) >> 1 | (Y & 0b1) << 2 | X & 0b1 (4)
1075 * Y' = (Y & ~0b1) << 1 | (X & 0b1000) >> 2 | (X & 0b10) >> 1
1077 emit_and(t1
, X
, brw_imm_uw(0xfff4)); /* X & ~0b1011 */
1078 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1011) >> 1 */
1079 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1080 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b1) << 2 */
1081 emit_or(t1
, t1
, t2
); /* (X & ~0b1011) >> 1 | (Y & 0b1) << 2 */
1082 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1083 emit_or(Xp
, t1
, t2
);
1084 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1085 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1086 emit_and(t2
, X
, brw_imm_uw(8)); /* X & 0b1000 */
1087 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b1000) >> 2 */
1088 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (X & 0b1000) >> 2 */
1089 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1090 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1091 emit_or(Yp
, t1
, t2
);
1094 /* Applying the same logic as above, but in reverse, we obtain the
1097 * X' = (X & ~0b101) << 1 | (Y & 0b10) << 2 | (Y & 0b1) << 1 | X & 0b1
1098 * Y' = (Y & ~0b11) >> 1 | (X & 0b100) >> 2
1100 emit_and(t1
, X
, brw_imm_uw(0xfffa)); /* X & ~0b101 */
1101 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b101) << 1 */
1102 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1103 emit_shl(t2
, t2
, brw_imm_uw(2)); /* (Y & 0b10) << 2 */
1104 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2 */
1105 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1106 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (Y & 0b1) << 1 */
1107 emit_or(t1
, t1
, t2
); /* (X & ~0b101) << 1 | (Y & 0b10) << 2
1109 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1110 emit_or(Xp
, t1
, t2
);
1111 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1112 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1113 emit_and(t2
, X
, brw_imm_uw(4)); /* X & 0b100 */
1114 emit_shr(t2
, t2
, brw_imm_uw(2)); /* (X & 0b100) >> 2 */
1115 emit_or(Yp
, t1
, t2
);
1121 * Emit code to compensate for the difference between MSAA and non-MSAA
1124 * This code modifies the X and Y coordinates according to the formula:
1126 * (X', Y', S') = encode_msaa(num_samples, IMS, X, Y, S)
1128 * (See brw_blorp_blit_program).
1131 brw_blorp_blit_program::encode_msaa(unsigned num_samples
,
1132 intel_msaa_layout layout
)
1135 case INTEL_MSAA_LAYOUT_NONE
:
1136 /* No translation necessary, and S should already be zero. */
1139 case INTEL_MSAA_LAYOUT_CMS
:
1140 /* We can't compensate for compressed layout since at this point in the
1141 * program we haven't read from the MCS buffer.
1143 unreachable("Bad layout in encode_msaa");
1144 case INTEL_MSAA_LAYOUT_UMS
:
1145 /* No translation necessary. */
1147 case INTEL_MSAA_LAYOUT_IMS
:
1148 switch (num_samples
) {
1150 /* encode_msaa(4, IMS, X, Y, S) = (X', Y', 0)
1151 * where X' = (X & ~0b1) << 1 | (S & 0b1) << 1 | (X & 0b1)
1152 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1154 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1156 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1157 emit_or(t1
, t1
, t2
); /* (X & ~0b1) | (S & 0b1) */
1159 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b1) << 1
1161 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1162 emit_or(Xp
, t1
, t2
);
1163 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1164 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1166 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1167 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1169 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1170 emit_or(Yp
, t1
, t2
);
1173 /* encode_msaa(8, IMS, X, Y, S) = (X', Y', 0)
1174 * where X' = (X & ~0b1) << 2 | (S & 0b100) | (S & 0b1) << 1
1176 * Y' = (Y & ~0b1) << 1 | (S & 0b10) | (Y & 0b1)
1178 emit_and(t1
, X
, brw_imm_uw(0xfffe)); /* X & ~0b1 */
1179 emit_shl(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b1) << 2 */
1181 emit_and(t2
, S
, brw_imm_uw(4)); /* S & 0b100 */
1182 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100) */
1183 emit_and(t2
, S
, brw_imm_uw(1)); /* S & 0b1 */
1184 emit_shl(t2
, t2
, brw_imm_uw(1)); /* (S & 0b1) << 1 */
1185 emit_or(t1
, t1
, t2
); /* (X & ~0b1) << 2 | (S & 0b100)
1188 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1189 emit_or(Xp
, t1
, t2
);
1190 emit_and(t1
, Y
, brw_imm_uw(0xfffe)); /* Y & ~0b1 */
1191 emit_shl(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b1) << 1 */
1193 emit_and(t2
, S
, brw_imm_uw(2)); /* S & 0b10 */
1194 emit_or(t1
, t1
, t2
); /* (Y & ~0b1) << 1 | (S & 0b10) */
1196 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1197 emit_or(Yp
, t1
, t2
);
1207 * Emit code to compensate for the difference between MSAA and non-MSAA
1210 * This code modifies the X and Y coordinates according to the formula:
1212 * (X', Y', S) = decode_msaa(num_samples, IMS, X, Y, S)
1214 * (See brw_blorp_blit_program).
1217 brw_blorp_blit_program::decode_msaa(unsigned num_samples
,
1218 intel_msaa_layout layout
)
1221 case INTEL_MSAA_LAYOUT_NONE
:
1222 /* No translation necessary, and S should already be zero. */
1225 case INTEL_MSAA_LAYOUT_CMS
:
1226 /* We can't compensate for compressed layout since at this point in the
1227 * program we don't have access to the MCS buffer.
1229 unreachable("Bad layout in encode_msaa");
1230 case INTEL_MSAA_LAYOUT_UMS
:
1231 /* No translation necessary. */
1233 case INTEL_MSAA_LAYOUT_IMS
:
1235 switch (num_samples
) {
1237 /* decode_msaa(4, IMS, X, Y, 0) = (X', Y', S)
1238 * where X' = (X & ~0b11) >> 1 | (X & 0b1)
1239 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1240 * S = (Y & 0b10) | (X & 0b10) >> 1
1242 emit_and(t1
, X
, brw_imm_uw(0xfffc)); /* X & ~0b11 */
1243 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (X & ~0b11) >> 1 */
1244 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1245 emit_or(Xp
, t1
, t2
);
1246 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1247 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1248 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1249 emit_or(Yp
, t1
, t2
);
1250 emit_and(t1
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1251 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1252 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1256 /* decode_msaa(8, IMS, X, Y, 0) = (X', Y', S)
1257 * where X' = (X & ~0b111) >> 2 | (X & 0b1)
1258 * Y' = (Y & ~0b11) >> 1 | (Y & 0b1)
1259 * S = (X & 0b100) | (Y & 0b10) | (X & 0b10) >> 1
1261 emit_and(t1
, X
, brw_imm_uw(0xfff8)); /* X & ~0b111 */
1262 emit_shr(t1
, t1
, brw_imm_uw(2)); /* (X & ~0b111) >> 2 */
1263 emit_and(t2
, X
, brw_imm_uw(1)); /* X & 0b1 */
1264 emit_or(Xp
, t1
, t2
);
1265 emit_and(t1
, Y
, brw_imm_uw(0xfffc)); /* Y & ~0b11 */
1266 emit_shr(t1
, t1
, brw_imm_uw(1)); /* (Y & ~0b11) >> 1 */
1267 emit_and(t2
, Y
, brw_imm_uw(1)); /* Y & 0b1 */
1268 emit_or(Yp
, t1
, t2
);
1269 emit_and(t1
, X
, brw_imm_uw(4)); /* X & 0b100 */
1270 emit_and(t2
, Y
, brw_imm_uw(2)); /* Y & 0b10 */
1271 emit_or(t1
, t1
, t2
); /* (X & 0b100) | (Y & 0b10) */
1272 emit_and(t2
, X
, brw_imm_uw(2)); /* X & 0b10 */
1273 emit_shr(t2
, t2
, brw_imm_uw(1)); /* (X & 0b10) >> 1 */
1284 * Emit code to translate from destination (X, Y) coordinates to source (X, Y)
1288 brw_blorp_blit_program::translate_dst_to_src()
1290 struct brw_reg X_f
= retype(X
, BRW_REGISTER_TYPE_F
);
1291 struct brw_reg Y_f
= retype(Y
, BRW_REGISTER_TYPE_F
);
1292 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1293 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1295 /* Move the UD coordinates to float registers. */
1298 /* Scale and offset */
1299 emit_mad(X_f
, x_transform
.offset
, Xp_f
, x_transform
.multiplier
);
1300 emit_mad(Y_f
, y_transform
.offset
, Yp_f
, y_transform
.multiplier
);
1301 if (key
->blit_scaled
&& key
->blend
) {
1302 /* Translate coordinates to lay out the samples in a rectangular grid
1303 * roughly corresponding to sample locations.
1305 emit_mul(X_f
, X_f
, brw_imm_f(key
->x_scale
));
1306 emit_mul(Y_f
, Y_f
, brw_imm_f(key
->y_scale
));
1307 /* Adjust coordinates so that integers represent pixel centers rather
1310 emit_add(X_f
, X_f
, brw_imm_f(-0.5));
1311 emit_add(Y_f
, Y_f
, brw_imm_f(-0.5));
1313 /* Clamp the X, Y texture coordinates to properly handle the sampling of
1314 * texels on texture edges.
1316 clamp_tex_coords(X_f
, Y_f
,
1317 brw_imm_f(0.0), brw_imm_f(0.0),
1318 rect_grid_x1
, rect_grid_y1
);
1320 /* Store the fractional parts to be used as bilinear interpolation
1323 emit_frc(x_frac
, X_f
);
1324 emit_frc(y_frac
, Y_f
);
1326 /* Round the float coordinates down to nearest integer */
1327 emit_rndd(Xp_f
, X_f
);
1328 emit_rndd(Yp_f
, Y_f
);
1329 emit_mul(X_f
, Xp_f
, brw_imm_f(1.0f
/ key
->x_scale
));
1330 emit_mul(Y_f
, Yp_f
, brw_imm_f(1.0f
/ key
->y_scale
));
1332 } else if (!key
->bilinear_filter
) {
1333 /* Round the float coordinates down to nearest integer by moving to
1343 brw_blorp_blit_program::clamp_tex_coords(struct brw_reg regX
,
1344 struct brw_reg regY
,
1345 struct brw_reg clampX0
,
1346 struct brw_reg clampY0
,
1347 struct brw_reg clampX1
,
1348 struct brw_reg clampY1
)
1350 emit_max(regX
, regX
, clampX0
);
1351 emit_max(regY
, regY
, clampY0
);
1352 emit_min(regX
, regX
, clampX1
);
1353 emit_min(regY
, regY
, clampY1
);
1357 * Emit code to transform the X and Y coordinates as needed for blending
1358 * together the different samples in an MSAA texture.
1361 brw_blorp_blit_program::single_to_blend()
1363 /* When looking up samples in an MSAA texture using the SAMPLE message,
1364 * Gen6 requires the texture coordinates to be odd integers (so that they
1365 * correspond to the center of a 2x2 block representing the four samples
1366 * that maxe up a pixel). So we need to multiply our X and Y coordinates
1367 * each by 2 and then add 1.
1369 emit_shl(t1
, X
, brw_imm_w(1));
1370 emit_shl(t2
, Y
, brw_imm_w(1));
1371 emit_add(Xp
, t1
, brw_imm_w(1));
1372 emit_add(Yp
, t2
, brw_imm_w(1));
1378 * Count the number of trailing 1 bits in the given value. For example:
1380 * count_trailing_one_bits(0) == 0
1381 * count_trailing_one_bits(7) == 3
1382 * count_trailing_one_bits(11) == 2
1384 static inline int count_trailing_one_bits(unsigned value
)
1386 #ifdef HAVE___BUILTIN_CTZ
1387 return __builtin_ctz(~value
);
1389 return _mesa_bitcount(value
& ~(value
+ 1));
1395 brw_blorp_blit_program::manual_blend_average(unsigned num_samples
)
1397 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1400 /* We add together samples using a binary tree structure, e.g. for 4x MSAA:
1402 * result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
1404 * This ensures that when all samples have the same value, no numerical
1405 * precision is lost, since each addition operation always adds two equal
1406 * values, and summing two equal floating point values does not lose
1409 * We perform this computation by treating the texture_data array as a
1410 * stack and performing the following operations:
1412 * - push sample 0 onto stack
1413 * - push sample 1 onto stack
1414 * - add top two stack entries
1415 * - push sample 2 onto stack
1416 * - push sample 3 onto stack
1417 * - add top two stack entries
1418 * - add top two stack entries
1419 * - divide top stack entry by 4
1421 * Note that after pushing sample i onto the stack, the number of add
1422 * operations we do is equal to the number of trailing 1 bits in i. This
1423 * works provided the total number of samples is a power of two, which it
1424 * always is for i965.
1426 * For integer formats, we replace the add operations with average
1427 * operations and skip the final division.
1429 unsigned stack_depth
= 0;
1430 for (unsigned i
= 0; i
< num_samples
; ++i
) {
1431 assert(stack_depth
== _mesa_bitcount(i
)); /* Loop invariant */
1433 /* Push sample i onto the stack */
1434 assert(stack_depth
< ARRAY_SIZE(texture_data
));
1439 emit_mov(vec16(S
), brw_imm_ud(i
));
1441 texel_fetch(texture_data
[stack_depth
++]);
1443 if (i
== 0 && key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
) {
1444 /* The Ivy Bridge PRM, Vol4 Part1 p27 (Multisample Control Surface)
1445 * suggests an optimization:
1447 * "A simple optimization with probable large return in
1448 * performance is to compare the MCS value to zero (indicating
1449 * all samples are on sample slice 0), and sample only from
1450 * sample slice 0 using ld2dss if MCS is zero."
1452 * Note that in the case where the MCS value is zero, sampling from
1453 * sample slice 0 using ld2dss and sampling from sample 0 using
1454 * ld2dms are equivalent (since all samples are on sample slice 0).
1455 * Since we have already sampled from sample 0, all we need to do is
1456 * skip the remaining fetches and averaging if MCS is zero.
1458 emit_cmp_if(BRW_CONDITIONAL_NZ
, mcs_data
, brw_imm_ud(0));
1461 /* Do count_trailing_one_bits(i) times */
1462 for (int j
= count_trailing_one_bits(i
); j
-- > 0; ) {
1463 assert(stack_depth
>= 2);
1466 /* TODO: should use a smaller loop bound for non_RGBA formats */
1467 for (int k
= 0; k
< 4; ++k
) {
1468 emit_combine(key
->texture_data_type
== BRW_REGISTER_TYPE_F
?
1469 BRW_OPCODE_ADD
: BRW_OPCODE_AVG
,
1470 offset(texture_data
[stack_depth
- 1], 2*k
),
1471 offset(vec8(texture_data
[stack_depth
- 1]), 2*k
),
1472 offset(vec8(texture_data
[stack_depth
]), 2*k
));
1477 /* We should have just 1 sample on the stack now. */
1478 assert(stack_depth
== 1);
1480 if (key
->texture_data_type
== BRW_REGISTER_TYPE_F
) {
1481 /* Scale the result down by a factor of num_samples */
1482 /* TODO: should use a smaller loop bound for non-RGBA formats */
1483 for (int j
= 0; j
< 4; ++j
) {
1484 emit_mul(offset(texture_data
[0], 2*j
),
1485 offset(vec8(texture_data
[0]), 2*j
),
1486 brw_imm_f(1.0f
/ num_samples
));
1490 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1495 brw_blorp_blit_program::manual_blend_bilinear(unsigned num_samples
)
1497 /* We do this computation by performing the following operations:
1499 * In case of 4x, 8x MSAA:
1500 * - Compute the pixel coordinates and sample numbers (a, b, c, d)
1501 * which are later used for interpolation
1502 * - linearly interpolate samples a and b in X
1503 * - linearly interpolate samples c and d in X
1504 * - linearly interpolate the results of last two operations in Y
1506 * result = lrp(lrp(a + b) + lrp(c + d))
1508 struct brw_reg Xp_f
= retype(Xp
, BRW_REGISTER_TYPE_F
);
1509 struct brw_reg Yp_f
= retype(Yp
, BRW_REGISTER_TYPE_F
);
1510 struct brw_reg t1_f
= retype(t1
, BRW_REGISTER_TYPE_F
);
1511 struct brw_reg t2_f
= retype(t2
, BRW_REGISTER_TYPE_F
);
1513 for (unsigned i
= 0; i
< 4; ++i
) {
1514 assert(i
< ARRAY_SIZE(texture_data
));
1517 /* Compute pixel coordinates */
1518 emit_add(vec16(x_sample_coords
), Xp_f
,
1519 brw_imm_f((float)(i
& 0x1) * (1.0f
/ key
->x_scale
)));
1520 emit_add(vec16(y_sample_coords
), Yp_f
,
1521 brw_imm_f((float)((i
>> 1) & 0x1) * (1.0f
/ key
->y_scale
)));
1522 emit_mov(vec16(X
), x_sample_coords
);
1523 emit_mov(vec16(Y
), y_sample_coords
);
1525 /* The MCS value we fetch has to match up with the pixel that we're
1526 * sampling from. Since we sample from different pixels in each
1527 * iteration of this "for" loop, the call to mcs_fetch() should be
1528 * here inside the loop after computing the pixel coordinates.
1530 if (key
->tex_layout
== INTEL_MSAA_LAYOUT_CMS
)
1533 /* Compute sample index and map the sample index to a sample number.
1534 * Sample index layout shows the numbering of slots in a rectangular
1535 * grid of samples with in a pixel. Sample number layout shows the
1536 * rectangular grid of samples roughly corresponding to the real sample
1537 * locations with in a pixel.
1538 * In case of 4x MSAA, layout of sample indices matches the layout of
1546 * In case of 8x MSAA the two layouts don't match.
1547 * sample index layout : --------- sample number layout : ---------
1548 * | 0 | 1 | | 5 | 2 |
1549 * --------- ---------
1550 * | 2 | 3 | | 4 | 6 |
1551 * --------- ---------
1552 * | 4 | 5 | | 0 | 3 |
1553 * --------- ---------
1554 * | 6 | 7 | | 7 | 1 |
1555 * --------- ---------
1557 emit_frc(vec16(t1_f
), x_sample_coords
);
1558 emit_frc(vec16(t2_f
), y_sample_coords
);
1559 emit_mul(vec16(t1_f
), t1_f
, brw_imm_f(key
->x_scale
));
1560 emit_mul(vec16(t2_f
), t2_f
, brw_imm_f(key
->x_scale
* key
->y_scale
));
1561 emit_add(vec16(t1_f
), t1_f
, t2_f
);
1562 emit_mov(vec16(S
), t1_f
);
1564 if (num_samples
== 8) {
1565 /* Map the sample index to a sample number */
1566 emit_cmp_if(BRW_CONDITIONAL_L
, S
, brw_imm_d(4));
1568 emit_mov(vec16(t2
), brw_imm_d(5));
1569 emit_if_eq_mov(S
, 1, vec16(t2
), 2);
1570 emit_if_eq_mov(S
, 2, vec16(t2
), 4);
1571 emit_if_eq_mov(S
, 3, vec16(t2
), 6);
1575 emit_mov(vec16(t2
), brw_imm_d(0));
1576 emit_if_eq_mov(S
, 5, vec16(t2
), 3);
1577 emit_if_eq_mov(S
, 6, vec16(t2
), 7);
1578 emit_if_eq_mov(S
, 7, vec16(t2
), 1);
1581 emit_mov(vec16(S
), t2
);
1583 texel_fetch(texture_data
[i
]);
1586 #define SAMPLE(x, y) offset(texture_data[x], y)
1587 for (int index
= 3; index
> 0; ) {
1588 /* Since we're doing SIMD16, 4 color channels fits in to 8 registers.
1589 * Counter value of 8 in 'for' loop below is used to interpolate all
1590 * the color components.
1592 for (int k
= 0; k
< 8; k
+= 2)
1593 emit_lrp(vec8(SAMPLE(index
- 1, k
)),
1595 vec8(SAMPLE(index
, k
)),
1596 vec8(SAMPLE(index
- 1, k
)));
1599 for (int k
= 0; k
< 8; k
+= 2)
1600 emit_lrp(vec8(SAMPLE(0, k
)),
1603 vec8(SAMPLE(0, k
)));
1608 * Emit code to look up a value in the texture using the SAMPLE message (which
1609 * does blending of MSAA surfaces).
1612 brw_blorp_blit_program::sample(struct brw_reg dst
)
1614 static const sampler_message_arg args
[2] = {
1615 SAMPLER_MESSAGE_ARG_U_FLOAT
,
1616 SAMPLER_MESSAGE_ARG_V_FLOAT
1619 texture_lookup(dst
, SHADER_OPCODE_TEX
, args
, ARRAY_SIZE(args
));
1623 * Emit code to look up a value in the texture using the SAMPLE_LD message
1624 * (which does a simple texel fetch).
1627 brw_blorp_blit_program::texel_fetch(struct brw_reg dst
)
1629 static const sampler_message_arg gen6_args
[5] = {
1630 SAMPLER_MESSAGE_ARG_U_INT
,
1631 SAMPLER_MESSAGE_ARG_V_INT
,
1632 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* R */
1633 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1634 SAMPLER_MESSAGE_ARG_SI_INT
1636 static const sampler_message_arg gen7_ld_args
[] = {
1637 SAMPLER_MESSAGE_ARG_U_INT
,
1638 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1639 SAMPLER_MESSAGE_ARG_V_INT
,
1640 SAMPLER_MESSAGE_ARG_R_INT
1642 static const sampler_message_arg gen7_ld2dss_args
[3] = {
1643 SAMPLER_MESSAGE_ARG_SI_INT
,
1644 SAMPLER_MESSAGE_ARG_U_INT
,
1645 SAMPLER_MESSAGE_ARG_V_INT
1647 static const sampler_message_arg gen7_ld2dms_args
[4] = {
1648 SAMPLER_MESSAGE_ARG_SI_INT
,
1649 SAMPLER_MESSAGE_ARG_MCS_INT
,
1650 SAMPLER_MESSAGE_ARG_U_INT
,
1651 SAMPLER_MESSAGE_ARG_V_INT
1653 static const sampler_message_arg gen9_ld_args
[] = {
1654 SAMPLER_MESSAGE_ARG_U_INT
,
1655 SAMPLER_MESSAGE_ARG_V_INT
,
1656 SAMPLER_MESSAGE_ARG_ZERO_INT
, /* LOD */
1657 SAMPLER_MESSAGE_ARG_R_INT
1662 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen6_args
, s_is_zero
? 2 : 5);
1667 switch (key
->tex_layout
) {
1668 case INTEL_MSAA_LAYOUT_IMS
:
1669 /* From the Ivy Bridge PRM, Vol4 Part1 p72 (Multisampled Surface Storage
1672 * If this field is MSFMT_DEPTH_STENCIL
1673 * [a.k.a. INTEL_MSAA_LAYOUT_IMS], the only sampling engine
1674 * messages allowed are "ld2dms", "resinfo", and "sampleinfo".
1676 * So fall through to emit the same message as we use for
1677 * INTEL_MSAA_LAYOUT_CMS.
1679 case INTEL_MSAA_LAYOUT_CMS
:
1680 texture_lookup(dst
, SHADER_OPCODE_TXF_CMS
,
1681 gen7_ld2dms_args
, ARRAY_SIZE(gen7_ld2dms_args
));
1683 case INTEL_MSAA_LAYOUT_UMS
:
1684 texture_lookup(dst
, SHADER_OPCODE_TXF_UMS
,
1685 gen7_ld2dss_args
, ARRAY_SIZE(gen7_ld2dss_args
));
1687 case INTEL_MSAA_LAYOUT_NONE
:
1690 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen7_ld_args
,
1691 ARRAY_SIZE(gen7_ld_args
));
1693 texture_lookup(dst
, SHADER_OPCODE_TXF
, gen9_ld_args
,
1694 ARRAY_SIZE(gen9_ld_args
));
1700 unreachable("Should not get here.");
1705 brw_blorp_blit_program::mcs_fetch()
1707 static const sampler_message_arg gen7_ld_mcs_args
[2] = {
1708 SAMPLER_MESSAGE_ARG_U_INT
,
1709 SAMPLER_MESSAGE_ARG_V_INT
1711 texture_lookup(vec16(mcs_data
), SHADER_OPCODE_TXF_MCS
,
1712 gen7_ld_mcs_args
, ARRAY_SIZE(gen7_ld_mcs_args
));
1716 brw_blorp_blit_program::texture_lookup(struct brw_reg dst
,
1718 const sampler_message_arg
*args
,
1721 struct brw_reg mrf
=
1722 retype(vec16(brw_message_reg(base_mrf
)), BRW_REGISTER_TYPE_UD
);
1723 for (int arg
= 0; arg
< num_args
; ++arg
) {
1724 switch (args
[arg
]) {
1725 case SAMPLER_MESSAGE_ARG_U_FLOAT
:
1726 if (key
->bilinear_filter
)
1727 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1728 retype(X
, BRW_REGISTER_TYPE_F
));
1730 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), X
);
1732 case SAMPLER_MESSAGE_ARG_V_FLOAT
:
1733 if (key
->bilinear_filter
)
1734 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
),
1735 retype(Y
, BRW_REGISTER_TYPE_F
));
1737 emit_mov(retype(mrf
, BRW_REGISTER_TYPE_F
), Y
);
1739 case SAMPLER_MESSAGE_ARG_U_INT
:
1742 case SAMPLER_MESSAGE_ARG_V_INT
:
1745 case SAMPLER_MESSAGE_ARG_R_INT
:
1746 emit_mov(mrf
, src_z
);
1748 case SAMPLER_MESSAGE_ARG_SI_INT
:
1749 /* Note: on Gen7, this code may be reached with s_is_zero==true
1750 * because in Gen7's ld2dss message, the sample index is the first
1751 * argument. When this happens, we need to move a 0 into the
1752 * appropriate message register.
1755 emit_mov(mrf
, brw_imm_ud(0));
1759 case SAMPLER_MESSAGE_ARG_MCS_INT
:
1760 switch (key
->tex_layout
) {
1761 case INTEL_MSAA_LAYOUT_CMS
:
1762 emit_mov(mrf
, mcs_data
);
1764 case INTEL_MSAA_LAYOUT_IMS
:
1765 /* When sampling from an IMS surface, MCS data is not relevant,
1766 * and the hardware ignores it. So don't bother populating it.
1770 /* We shouldn't be trying to send MCS data with any other
1773 assert (!"Unsupported layout for MCS data");
1777 case SAMPLER_MESSAGE_ARG_ZERO_INT
:
1778 emit_mov(mrf
, brw_imm_ud(0));
1784 emit_texture_lookup(retype(dst
, BRW_REGISTER_TYPE_UW
) /* dest */,
1787 mrf
.nr
- base_mrf
/* msg_length */);
1795 #undef SWAP_XY_AND_XPYP
1798 brw_blorp_blit_program::render_target_write()
1800 struct brw_reg mrf_rt_write
=
1801 retype(vec16(brw_message_reg(base_mrf
)), key
->texture_data_type
);
1804 /* If we may have killed pixels, then we need to send R0 and R1 in a header
1805 * so that the render target knows which pixels we killed.
1807 bool use_header
= key
->use_kill
;
1809 /* Copy R0/1 to MRF */
1810 emit_mov(retype(mrf_rt_write
, BRW_REGISTER_TYPE_UD
),
1811 retype(R0
, BRW_REGISTER_TYPE_UD
));
1815 /* Copy texture data to MRFs */
1816 for (int i
= 0; i
< 4; ++i
) {
1817 /* E.g. mov(16) m2.0<1>:f r2.0<8;8,1>:f { Align1, H1 } */
1818 emit_mov(offset(mrf_rt_write
, mrf_offset
),
1819 offset(vec8(texture_data
[0]), 2*i
));
1823 /* Now write to the render target and terminate the thread */
1824 emit_render_target_write(
1826 brw
->gen
< 8 ? base_mrf
: -1,
1827 mrf_offset
/* msg_length. TODO: Should be smaller for non-RGBA formats. */,
1833 brw_blorp_coord_transform_params::setup(GLfloat src0
, GLfloat src1
,
1834 GLfloat dst0
, GLfloat dst1
,
1837 float scale
= (src1
- src0
) / (dst1
- dst0
);
1839 /* When not mirroring a coordinate (say, X), we need:
1840 * src_x - src_x0 = (dst_x - dst_x0 + 0.5) * scale
1842 * src_x = src_x0 + (dst_x - dst_x0 + 0.5) * scale
1844 * blorp program uses "round toward zero" to convert the
1845 * transformed floating point coordinates to integer coordinates,
1846 * whereas the behaviour we actually want is "round to nearest",
1847 * so 0.5 provides the necessary correction.
1850 offset
= src0
+ (-dst0
+ 0.5f
) * scale
;
1852 /* When mirroring X we need:
1853 * src_x - src_x0 = dst_x1 - dst_x - 0.5
1855 * src_x = src_x0 + (dst_x1 -dst_x - 0.5) * scale
1857 multiplier
= -scale
;
1858 offset
= src0
+ (dst1
- 0.5f
) * scale
;
1864 * Determine which MSAA layout the GPU pipeline should be configured for,
1865 * based on the chip generation, the number of samples, and the true layout of
1866 * the image in memory.
1868 inline intel_msaa_layout
1869 compute_msaa_layout_for_pipeline(struct brw_context
*brw
, unsigned num_samples
,
1870 intel_msaa_layout true_layout
)
1872 if (num_samples
<= 1) {
1873 /* When configuring the GPU for non-MSAA, we can still accommodate IMS
1874 * format buffers, by transforming coordinates appropriately.
1876 assert(true_layout
== INTEL_MSAA_LAYOUT_NONE
||
1877 true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1878 return INTEL_MSAA_LAYOUT_NONE
;
1880 assert(true_layout
!= INTEL_MSAA_LAYOUT_NONE
);
1883 /* Prior to Gen7, all MSAA surfaces use IMS layout. */
1884 if (brw
->gen
== 6) {
1885 assert(true_layout
== INTEL_MSAA_LAYOUT_IMS
);
1892 brw_blorp_blit_params::brw_blorp_blit_params(struct brw_context
*brw
,
1893 struct intel_mipmap_tree
*src_mt
,
1894 unsigned src_level
, unsigned src_layer
,
1895 mesa_format src_format
,
1896 struct intel_mipmap_tree
*dst_mt
,
1897 unsigned dst_level
, unsigned dst_layer
,
1898 mesa_format dst_format
,
1899 GLfloat src_x0
, GLfloat src_y0
,
1900 GLfloat src_x1
, GLfloat src_y1
,
1901 GLfloat dst_x0
, GLfloat dst_y0
,
1902 GLfloat dst_x1
, GLfloat dst_y1
,
1904 bool mirror_x
, bool mirror_y
)
1906 src
.set(brw
, src_mt
, src_level
, src_layer
, src_format
, false);
1907 dst
.set(brw
, dst_mt
, dst_level
, dst_layer
, dst_format
, true);
1909 /* Even though we do multisample resolves at the time of the blit, OpenGL
1910 * specification defines them as if they happen at the time of rendering,
1911 * which means that the type of averaging we do during the resolve should
1912 * only depend on the source format; the destination format should be
1913 * ignored. But, specification doesn't seem to be strict about it.
1915 * It has been observed that mulitisample resolves produce slightly better
1916 * looking images when averaging is done using destination format. NVIDIA's
1917 * proprietary OpenGL driver also follow this approach. So, we choose to
1918 * follow it in our driver.
1920 * When multisampling, if the source and destination formats are equal
1921 * (aside from the color space), we choose to blit in sRGB space to get
1922 * this higher quality image.
1924 if (src
.num_samples
> 1 &&
1925 _mesa_get_format_color_encoding(dst_mt
->format
) == GL_SRGB
&&
1926 _mesa_get_srgb_format_linear(src_mt
->format
) ==
1927 _mesa_get_srgb_format_linear(dst_mt
->format
)) {
1928 assert(brw
->format_supported_as_render_target
[dst_mt
->format
]);
1929 dst
.brw_surfaceformat
= brw
->render_target_format
[dst_mt
->format
];
1930 src
.brw_surfaceformat
= brw_format_for_mesa_format(dst_mt
->format
);
1933 /* When doing a multisample resolve of a GL_LUMINANCE32F or GL_INTENSITY32F
1934 * texture, the above code configures the source format for L32_FLOAT or
1935 * I32_FLOAT, and the destination format for R32_FLOAT. On Sandy Bridge,
1936 * the SAMPLE message appears to handle multisampled L32_FLOAT and
1937 * I32_FLOAT textures incorrectly, resulting in blocky artifacts. So work
1938 * around the problem by using a source format of R32_FLOAT. This
1939 * shouldn't affect rendering correctness, since the destination format is
1940 * R32_FLOAT, so only the contents of the red channel matters.
1942 if (brw
->gen
== 6 && src
.num_samples
> 1 && dst
.num_samples
<= 1 &&
1943 src_mt
->format
== dst_mt
->format
&&
1944 dst
.brw_surfaceformat
== BRW_SURFACEFORMAT_R32_FLOAT
) {
1945 src
.brw_surfaceformat
= dst
.brw_surfaceformat
;
1949 memset(&wm_prog_key
, 0, sizeof(wm_prog_key
));
1951 /* texture_data_type indicates the register type that should be used to
1952 * manipulate texture data.
1954 switch (_mesa_get_format_datatype(src_mt
->format
)) {
1955 case GL_UNSIGNED_NORMALIZED
:
1956 case GL_SIGNED_NORMALIZED
:
1958 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1960 case GL_UNSIGNED_INT
:
1961 if (src_mt
->format
== MESA_FORMAT_S_UINT8
) {
1962 /* We process stencil as though it's an unsigned normalized color */
1963 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_F
;
1965 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_UD
;
1969 wm_prog_key
.texture_data_type
= BRW_REGISTER_TYPE_D
;
1972 unreachable("Unrecognized blorp format");
1976 /* Gen7's rendering hardware only supports the IMS layout for depth and
1977 * stencil render targets. Blorp always maps its destination surface as
1978 * a color render target (even if it's actually a depth or stencil
1979 * buffer). So if the destination is IMS, we'll have to map it as a
1980 * single-sampled texture and interleave the samples ourselves.
1982 if (dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
)
1983 dst
.num_samples
= 0;
1986 if (dst
.map_stencil_as_y_tiled
&& dst
.num_samples
> 1) {
1987 /* If the destination surface is a W-tiled multisampled stencil buffer
1988 * that we're mapping as Y tiled, then we need to arrange for the WM
1989 * program to run once per sample rather than once per pixel, because
1990 * the memory layout of related samples doesn't match between W and Y
1993 wm_prog_key
.persample_msaa_dispatch
= true;
1996 if (src
.num_samples
> 0 && dst
.num_samples
> 1) {
1997 /* We are blitting from a multisample buffer to a multisample buffer, so
1998 * we must preserve samples within a pixel. This means we have to
1999 * arrange for the WM program to run once per sample rather than once
2002 wm_prog_key
.persample_msaa_dispatch
= true;
2005 /* Scaled blitting or not. */
2006 wm_prog_key
.blit_scaled
=
2007 ((dst_x1
- dst_x0
) == (src_x1
- src_x0
) &&
2008 (dst_y1
- dst_y0
) == (src_y1
- src_y0
)) ? false : true;
2010 /* Scaling factors used for bilinear filtering in multisample scaled
2013 wm_prog_key
.x_scale
= 2.0f
;
2014 wm_prog_key
.y_scale
= src_mt
->num_samples
/ 2.0f
;
2016 if (filter
== GL_LINEAR
&& src
.num_samples
<= 1 && dst
.num_samples
<= 1)
2017 wm_prog_key
.bilinear_filter
= true;
2019 GLenum base_format
= _mesa_get_format_base_format(src_mt
->format
);
2020 if (base_format
!= GL_DEPTH_COMPONENT
&& /* TODO: what about depth/stencil? */
2021 base_format
!= GL_STENCIL_INDEX
&&
2022 src_mt
->num_samples
> 1 && dst_mt
->num_samples
<= 1) {
2023 /* We are downsampling a color buffer, so blend. */
2024 wm_prog_key
.blend
= true;
2027 /* src_samples and dst_samples are the true sample counts */
2028 wm_prog_key
.src_samples
= src_mt
->num_samples
;
2029 wm_prog_key
.dst_samples
= dst_mt
->num_samples
;
2031 /* tex_samples and rt_samples are the sample counts that are set up in
2034 wm_prog_key
.tex_samples
= src
.num_samples
;
2035 wm_prog_key
.rt_samples
= dst
.num_samples
;
2037 /* tex_layout and rt_layout indicate the MSAA layout the GPU pipeline will
2038 * use to access the source and destination surfaces.
2040 wm_prog_key
.tex_layout
=
2041 compute_msaa_layout_for_pipeline(brw
, src
.num_samples
, src
.msaa_layout
);
2042 wm_prog_key
.rt_layout
=
2043 compute_msaa_layout_for_pipeline(brw
, dst
.num_samples
, dst
.msaa_layout
);
2045 /* src_layout and dst_layout indicate the true MSAA layout used by src and
2048 wm_prog_key
.src_layout
= src_mt
->msaa_layout
;
2049 wm_prog_key
.dst_layout
= dst_mt
->msaa_layout
;
2051 wm_prog_key
.src_tiled_w
= src
.map_stencil_as_y_tiled
;
2052 wm_prog_key
.dst_tiled_w
= dst
.map_stencil_as_y_tiled
;
2053 /* Round floating point values to nearest integer to avoid "off by one texel"
2054 * kind of errors when blitting.
2056 x0
= wm_push_consts
.dst_x0
= roundf(dst_x0
);
2057 y0
= wm_push_consts
.dst_y0
= roundf(dst_y0
);
2058 x1
= wm_push_consts
.dst_x1
= roundf(dst_x1
);
2059 y1
= wm_push_consts
.dst_y1
= roundf(dst_y1
);
2060 wm_push_consts
.rect_grid_x1
= (minify(src_mt
->logical_width0
, src_level
) *
2061 wm_prog_key
.x_scale
- 1.0f
);
2062 wm_push_consts
.rect_grid_y1
= (minify(src_mt
->logical_height0
, src_level
) *
2063 wm_prog_key
.y_scale
- 1.0f
);
2065 wm_push_consts
.x_transform
.setup(src_x0
, src_x1
, dst_x0
, dst_x1
, mirror_x
);
2066 wm_push_consts
.y_transform
.setup(src_y0
, src_y1
, dst_y0
, dst_y1
, mirror_y
);
2068 wm_push_consts
.src_z
= src
.mt
->target
== GL_TEXTURE_3D
? src
.layer
: 0;
2070 if (dst
.num_samples
<= 1 && dst_mt
->num_samples
> 1) {
2071 /* We must expand the rectangle we send through the rendering pipeline,
2072 * to account for the fact that we are mapping the destination region as
2073 * single-sampled when it is in fact multisampled. We must also align
2074 * it to a multiple of the multisampling pattern, because the
2075 * differences between multisampled and single-sampled surface formats
2076 * will mean that pixels are scrambled within the multisampling pattern.
2077 * TODO: what if this makes the coordinates too large?
2079 * Note: this only works if the destination surface uses the IMS layout.
2080 * If it's UMS, then we have no choice but to set up the rendering
2081 * pipeline as multisampled.
2083 assert(dst_mt
->msaa_layout
== INTEL_MSAA_LAYOUT_IMS
);
2084 switch (dst_mt
->num_samples
) {
2086 x0
= ROUND_DOWN_TO(x0
* 2, 4);
2087 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2088 x1
= ALIGN(x1
* 2, 4);
2089 y1
= ALIGN(y1
* 2, 4);
2092 x0
= ROUND_DOWN_TO(x0
* 4, 8);
2093 y0
= ROUND_DOWN_TO(y0
* 2, 4);
2094 x1
= ALIGN(x1
* 4, 8);
2095 y1
= ALIGN(y1
* 2, 4);
2098 unreachable("Unrecognized sample count in brw_blorp_blit_params ctor");
2100 wm_prog_key
.use_kill
= true;
2103 if (dst
.map_stencil_as_y_tiled
) {
2104 /* We must modify the rectangle we send through the rendering pipeline
2105 * (and the size and x/y offset of the destination surface), to account
2106 * for the fact that we are mapping it as Y-tiled when it is in fact
2109 * Both Y tiling and W tiling can be understood as organizations of
2110 * 32-byte sub-tiles; within each 32-byte sub-tile, the layout of pixels
2111 * is different, but the layout of the 32-byte sub-tiles within the 4k
2112 * tile is the same (8 sub-tiles across by 16 sub-tiles down, in
2113 * column-major order). In Y tiling, the sub-tiles are 16 bytes wide
2114 * and 2 rows high; in W tiling, they are 8 bytes wide and 4 rows high.
2116 * Therefore, to account for the layout differences within the 32-byte
2117 * sub-tiles, we must expand the rectangle so the X coordinates of its
2118 * edges are multiples of 8 (the W sub-tile width), and its Y
2119 * coordinates of its edges are multiples of 4 (the W sub-tile height).
2120 * Then we need to scale the X and Y coordinates of the rectangle to
2121 * account for the differences in aspect ratio between the Y and W
2122 * sub-tiles. We need to modify the layer width and height similarly.
2124 * A correction needs to be applied when MSAA is in use: since
2125 * INTEL_MSAA_LAYOUT_IMS uses an interleaving pattern whose height is 4,
2126 * we need to align the Y coordinates to multiples of 8, so that when
2127 * they are divided by two they are still multiples of 4.
2129 * Note: Since the x/y offset of the surface will be applied using the
2130 * SURFACE_STATE command packet, it will be invisible to the swizzling
2131 * code in the shader; therefore it needs to be in a multiple of the
2132 * 32-byte sub-tile size. Fortunately it is, since the sub-tile is 8
2133 * pixels wide and 4 pixels high (when viewed as a W-tiled stencil
2134 * buffer), and the miplevel alignment used for stencil buffers is 8
2135 * pixels horizontally and either 4 or 8 pixels vertically (see
2136 * intel_horizontal_texture_alignment_unit() and
2137 * intel_vertical_texture_alignment_unit()).
2139 * Note: Also, since the SURFACE_STATE command packet can only apply
2140 * offsets that are multiples of 4 pixels horizontally and 2 pixels
2141 * vertically, it is important that the offsets will be multiples of
2142 * these sizes after they are converted into Y-tiled coordinates.
2143 * Fortunately they will be, since we know from above that the offsets
2144 * are a multiple of the 32-byte sub-tile size, and in Y-tiled
2145 * coordinates the sub-tile is 16 pixels wide and 2 pixels high.
2147 * TODO: what if this makes the coordinates (or the texture size) too
2150 const unsigned x_align
= 8, y_align
= dst
.num_samples
!= 0 ? 8 : 4;
2151 x0
= ROUND_DOWN_TO(x0
, x_align
) * 2;
2152 y0
= ROUND_DOWN_TO(y0
, y_align
) / 2;
2153 x1
= ALIGN(x1
, x_align
) * 2;
2154 y1
= ALIGN(y1
, y_align
) / 2;
2155 dst
.width
= ALIGN(dst
.width
, x_align
) * 2;
2156 dst
.height
= ALIGN(dst
.height
, y_align
) / 2;
2159 wm_prog_key
.use_kill
= true;
2162 if (src
.map_stencil_as_y_tiled
) {
2163 /* We must modify the size and x/y offset of the source surface to
2164 * account for the fact that we are mapping it as Y-tiled when it is in
2167 * See the comments above concerning x/y offset alignment for the
2168 * destination surface.
2170 * TODO: what if this makes the texture size too large?
2172 const unsigned x_align
= 8, y_align
= src
.num_samples
!= 0 ? 8 : 4;
2173 src
.width
= ALIGN(src
.width
, x_align
) * 2;
2174 src
.height
= ALIGN(src
.height
, y_align
) / 2;
2181 brw_blorp_blit_params::get_wm_prog(struct brw_context
*brw
,
2182 brw_blorp_prog_data
**prog_data
) const
2184 uint32_t prog_offset
= 0;
2185 if (!brw_search_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
2186 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2187 &prog_offset
, prog_data
)) {
2188 brw_blorp_blit_program
prog(brw
, &this->wm_prog_key
);
2189 GLuint program_size
;
2190 const GLuint
*program
= prog
.compile(brw
, INTEL_DEBUG
& DEBUG_BLORP
,
2192 brw_upload_cache(&brw
->cache
, BRW_CACHE_BLORP_PROG
,
2193 &this->wm_prog_key
, sizeof(this->wm_prog_key
),
2194 program
, program_size
,
2195 &prog
.prog_data
, sizeof(prog
.prog_data
),
2196 &prog_offset
, prog_data
);