2 * Copyright © 2007 Red Hat Inc.
3 * Copyright © 2007-2017 Intel Corporation
4 * Copyright © 2006 VMware, Inc.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 * Authors: Thomas Hellström <thellstrom@vmware.com>
29 * Keith Whitwell <keithw@vmware.com>
30 * Eric Anholt <eric@anholt.net>
31 * Dave Airlie <airlied@linux.ie>
39 #include <util/u_atomic.h>
46 #include <sys/ioctl.h>
48 #include <sys/types.h>
52 #include "common/gen_clflush.h"
53 #include "dev/gen_debug.h"
54 #include "common/gen_gem.h"
55 #include "dev/gen_device_info.h"
56 #include "libdrm_macros.h"
57 #include "main/macros.h"
58 #include "util/macros.h"
59 #include "util/hash_table.h"
60 #include "util/list.h"
61 #include "util/u_dynarray.h"
63 #include "brw_bufmgr.h"
64 #include "brw_context.h"
67 #include "drm-uapi/i915_drm.h"
77 /* VALGRIND_FREELIKE_BLOCK unfortunately does not actually undo the earlier
78 * VALGRIND_MALLOCLIKE_BLOCK but instead leaves vg convinced the memory is
79 * leaked. All because it does not call VG(cli_free) from its
80 * VG_USERREQ__FREELIKE_BLOCK handler. Instead of treating the memory like
81 * and allocation, we mark it available for use upon mmapping and remove
84 #define VG_DEFINED(ptr, size) VG(VALGRIND_MAKE_MEM_DEFINED(ptr, size))
85 #define VG_NOACCESS(ptr, size) VG(VALGRIND_MAKE_MEM_NOACCESS(ptr, size))
87 #define PAGE_SIZE 4096
89 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
92 atomic_add_unless(int *v
, int add
, int unless
)
96 while (c
!= unless
&& (old
= p_atomic_cmpxchg(v
, c
, c
+ add
)) != c
)
102 * i965 fixed-size bucketing VMA allocator.
104 * The BO cache maintains "cache buckets" for buffers of various sizes.
105 * All buffers in a given bucket are identically sized - when allocating,
106 * we always round up to the bucket size. This means that virtually all
107 * allocations are fixed-size; only buffers which are too large to fit in
108 * a bucket can be variably-sized.
110 * We create an allocator for each bucket. Each contains a free-list, where
111 * each node contains a <starting address, 64-bit bitmap> pair. Each bit
112 * represents a bucket-sized block of memory. (At the first level, each
113 * bit corresponds to a page. For the second bucket, bits correspond to
114 * two pages, and so on.) 1 means a block is free, and 0 means it's in-use.
115 * The lowest bit in the bitmap is for the first block.
117 * This makes allocations cheap - any bit of any node will do. We can pick
118 * the head of the list and use ffs() to find a free block. If there are
119 * none, we allocate 64 blocks from a larger allocator - either a bigger
120 * bucketing allocator, or a fallback top-level allocator for large objects.
122 struct vma_bucket_node
{
123 uint64_t start_address
;
127 struct bo_cache_bucket
{
128 /** List of cached BOs. */
129 struct list_head head
;
131 /** Size of this bucket, in bytes. */
134 /** List of vma_bucket_nodes. */
135 struct util_dynarray vma_list
[BRW_MEMZONE_COUNT
];
143 /** Array of lists of cached gem objects of power-of-two sizes */
144 struct bo_cache_bucket cache_bucket
[14 * 4];
148 struct hash_table
*name_table
;
149 struct hash_table
*handle_table
;
151 struct util_vma_heap vma_allocator
[BRW_MEMZONE_COUNT
];
157 uint64_t initial_kflags
;
160 static int bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
163 static void bo_free(struct brw_bo
*bo
);
165 static uint64_t vma_alloc(struct brw_bufmgr
*bufmgr
,
166 enum brw_memory_zone memzone
,
167 uint64_t size
, uint64_t alignment
);
170 key_hash_uint(const void *key
)
172 return _mesa_hash_data(key
, 4);
176 key_uint_equal(const void *a
, const void *b
)
178 return *((unsigned *) a
) == *((unsigned *) b
);
181 static struct brw_bo
*
182 hash_find_bo(struct hash_table
*ht
, unsigned int key
)
184 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, &key
);
185 return entry
? (struct brw_bo
*) entry
->data
: NULL
;
189 bo_tile_size(struct brw_bufmgr
*bufmgr
, uint64_t size
, uint32_t tiling
)
191 if (tiling
== I915_TILING_NONE
)
194 /* 965+ just need multiples of page size for tiling */
195 return ALIGN(size
, PAGE_SIZE
);
199 * Round a given pitch up to the minimum required for X tiling on a
200 * given chip. We use 512 as the minimum to allow for a later tiling
204 bo_tile_pitch(struct brw_bufmgr
*bufmgr
, uint32_t pitch
, uint32_t tiling
)
206 unsigned long tile_width
;
208 /* If untiled, then just align it so that we can do rendering
209 * to it with the 3D engine.
211 if (tiling
== I915_TILING_NONE
)
212 return ALIGN(pitch
, 64);
214 if (tiling
== I915_TILING_X
)
219 /* 965 is flexible */
220 return ALIGN(pitch
, tile_width
);
224 * This function finds the correct bucket fit for the input size.
225 * The function works with O(1) complexity when the requested size
226 * was queried instead of iterating the size through all the buckets.
228 static struct bo_cache_bucket
*
229 bucket_for_size(struct brw_bufmgr
*bufmgr
, uint64_t size
)
231 /* Calculating the pages and rounding up to the page size. */
232 const unsigned pages
= (size
+ PAGE_SIZE
- 1) / PAGE_SIZE
;
234 /* Row Bucket sizes clz((x-1) | 3) Row Column
235 * in pages stride size
236 * 0: 1 2 3 4 -> 30 30 30 30 4 1
237 * 1: 5 6 7 8 -> 29 29 29 29 4 1
238 * 2: 10 12 14 16 -> 28 28 28 28 8 2
239 * 3: 20 24 28 32 -> 27 27 27 27 16 4
241 const unsigned row
= 30 - __builtin_clz((pages
- 1) | 3);
242 const unsigned row_max_pages
= 4 << row
;
244 /* The '& ~2' is the special case for row 1. In row 1, max pages /
245 * 2 is 2, but the previous row maximum is zero (because there is
246 * no previous row). All row maximum sizes are power of 2, so that
247 * is the only case where that bit will be set.
249 const unsigned prev_row_max_pages
= (row_max_pages
/ 2) & ~2;
250 int col_size_log2
= row
- 1;
251 col_size_log2
+= (col_size_log2
< 0);
253 const unsigned col
= (pages
- prev_row_max_pages
+
254 ((1 << col_size_log2
) - 1)) >> col_size_log2
;
256 /* Calculating the index based on the row and column. */
257 const unsigned index
= (row
* 4) + (col
- 1);
259 return (index
< bufmgr
->num_buckets
) ?
260 &bufmgr
->cache_bucket
[index
] : NULL
;
263 static enum brw_memory_zone
264 memzone_for_address(uint64_t address
)
266 const uint64_t _4GB
= 1ull << 32;
269 return BRW_MEMZONE_OTHER
;
271 return BRW_MEMZONE_LOW_4G
;
275 bucket_vma_alloc(struct brw_bufmgr
*bufmgr
,
276 struct bo_cache_bucket
*bucket
,
277 enum brw_memory_zone memzone
)
279 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
280 struct vma_bucket_node
*node
;
282 if (vma_list
->size
== 0) {
283 /* This bucket allocator is out of space - allocate a new block of
284 * memory for 64 blocks from a larger allocator (either a larger
285 * bucket or util_vma).
287 * We align the address to the node size (64 blocks) so that
288 * bucket_vma_free can easily compute the starting address of this
289 * block by rounding any address we return down to the node size.
291 * Set the first bit used, and return the start address.
293 uint64_t node_size
= 64ull * bucket
->size
;
294 node
= util_dynarray_grow(vma_list
, struct vma_bucket_node
, 1);
299 uint64_t addr
= vma_alloc(bufmgr
, memzone
, node_size
, node_size
);
300 node
->start_address
= gen_48b_address(addr
);
301 node
->bitmap
= ~1ull;
302 return node
->start_address
;
305 /* Pick any bit from any node - they're all the right size and free. */
306 node
= util_dynarray_top_ptr(vma_list
, struct vma_bucket_node
);
307 int bit
= ffsll(node
->bitmap
) - 1;
308 assert(bit
>= 0 && bit
<= 63);
310 /* Reserve the memory by clearing the bit. */
311 assert((node
->bitmap
& (1ull << bit
)) != 0ull);
312 node
->bitmap
&= ~(1ull << bit
);
314 uint64_t addr
= node
->start_address
+ bit
* bucket
->size
;
316 /* If this node is now completely full, remove it from the free list. */
317 if (node
->bitmap
== 0ull) {
318 (void) util_dynarray_pop(vma_list
, struct vma_bucket_node
);
325 bucket_vma_free(struct bo_cache_bucket
*bucket
, uint64_t address
)
327 enum brw_memory_zone memzone
= memzone_for_address(address
);
328 struct util_dynarray
*vma_list
= &bucket
->vma_list
[memzone
];
329 const uint64_t node_bytes
= 64ull * bucket
->size
;
330 struct vma_bucket_node
*node
= NULL
;
332 /* bucket_vma_alloc allocates 64 blocks at a time, and aligns it to
333 * that 64 block size. So, we can round down to get the starting address.
335 uint64_t start
= (address
/ node_bytes
) * node_bytes
;
337 /* Dividing the offset from start by bucket size gives us the bit index. */
338 int bit
= (address
- start
) / bucket
->size
;
340 assert(start
+ bit
* bucket
->size
== address
);
342 util_dynarray_foreach(vma_list
, struct vma_bucket_node
, cur
) {
343 if (cur
->start_address
== start
) {
350 /* No node - the whole group of 64 blocks must have been in-use. */
351 node
= util_dynarray_grow(vma_list
, struct vma_bucket_node
, 1);
354 return; /* bogus, leaks some GPU VMA, but nothing we can do... */
356 node
->start_address
= start
;
360 /* Set the bit to return the memory. */
361 assert((node
->bitmap
& (1ull << bit
)) == 0ull);
362 node
->bitmap
|= 1ull << bit
;
364 /* The block might be entirely free now, and if so, we could return it
365 * to the larger allocator. But we may as well hang on to it, in case
366 * we get more allocations at this block size.
370 static struct bo_cache_bucket
*
371 get_bucket_allocator(struct brw_bufmgr
*bufmgr
, uint64_t size
)
373 /* Skip using the bucket allocator for very large sizes, as it allocates
374 * 64 of them and this can balloon rather quickly.
376 if (size
> 1024 * PAGE_SIZE
)
379 struct bo_cache_bucket
*bucket
= bucket_for_size(bufmgr
, size
);
381 if (bucket
&& bucket
->size
== size
)
388 * Allocate a section of virtual memory for a buffer, assigning an address.
390 * This uses either the bucket allocator for the given size, or the large
391 * object allocator (util_vma).
394 vma_alloc(struct brw_bufmgr
*bufmgr
,
395 enum brw_memory_zone memzone
,
399 /* Without softpin support, we let the kernel assign addresses. */
400 assert(brw_using_softpin(bufmgr
));
402 alignment
= ALIGN(alignment
, PAGE_SIZE
);
404 struct bo_cache_bucket
*bucket
= get_bucket_allocator(bufmgr
, size
);
408 addr
= bucket_vma_alloc(bufmgr
, bucket
, memzone
);
410 addr
= util_vma_heap_alloc(&bufmgr
->vma_allocator
[memzone
], size
,
414 assert((addr
>> 48ull) == 0);
415 assert((addr
% alignment
) == 0);
417 return gen_canonical_address(addr
);
421 * Free a virtual memory area, allowing the address to be reused.
424 vma_free(struct brw_bufmgr
*bufmgr
,
428 assert(brw_using_softpin(bufmgr
));
430 /* Un-canonicalize the address. */
431 address
= gen_48b_address(address
);
436 struct bo_cache_bucket
*bucket
= get_bucket_allocator(bufmgr
, size
);
439 bucket_vma_free(bucket
, address
);
441 enum brw_memory_zone memzone
= memzone_for_address(address
);
442 util_vma_heap_free(&bufmgr
->vma_allocator
[memzone
], address
, size
);
447 brw_bo_busy(struct brw_bo
*bo
)
449 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
450 struct drm_i915_gem_busy busy
= { .handle
= bo
->gem_handle
};
452 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_BUSY
, &busy
);
454 bo
->idle
= !busy
.busy
;
461 brw_bo_madvise(struct brw_bo
*bo
, int state
)
463 struct drm_i915_gem_madvise madv
= {
464 .handle
= bo
->gem_handle
,
469 drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_MADVISE
, &madv
);
471 return madv
.retained
;
474 /* drop the oldest entries that have been purged by the kernel */
476 brw_bo_cache_purge_bucket(struct brw_bufmgr
*bufmgr
,
477 struct bo_cache_bucket
*bucket
)
479 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
480 if (brw_bo_madvise(bo
, I915_MADV_DONTNEED
))
488 static struct brw_bo
*
489 bo_alloc_internal(struct brw_bufmgr
*bufmgr
,
492 enum brw_memory_zone memzone
,
494 uint32_t tiling_mode
,
499 struct bo_cache_bucket
*bucket
;
500 bool alloc_from_cache
;
505 if (flags
& BO_ALLOC_BUSY
)
508 if (flags
& BO_ALLOC_ZEROED
)
511 /* BUSY does doesn't really jive with ZEROED as we have to wait for it to
512 * be idle before we can memset. Just disallow that combination.
514 assert(!(busy
&& zeroed
));
516 /* Round the allocated size up to a power of two number of pages. */
517 bucket
= bucket_for_size(bufmgr
, size
);
519 /* If we don't have caching at this size, don't actually round the
522 if (bucket
== NULL
) {
523 unsigned int page_size
= getpagesize();
524 bo_size
= size
== 0 ? page_size
: ALIGN(size
, page_size
);
526 bo_size
= bucket
->size
;
530 mtx_lock(&bufmgr
->lock
);
531 /* Get a buffer out of the cache if available */
533 alloc_from_cache
= false;
534 if (bucket
!= NULL
&& !list_empty(&bucket
->head
)) {
535 if (busy
&& !zeroed
) {
536 /* Allocate new render-target BOs from the tail (MRU)
537 * of the list, as it will likely be hot in the GPU
538 * cache and in the aperture for us. If the caller
539 * asked us to zero the buffer, we don't want this
540 * because we are going to mmap it.
542 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.prev
, head
);
544 alloc_from_cache
= true;
546 /* For non-render-target BOs (where we're probably
547 * going to map it first thing in order to fill it
548 * with data), check if the last BO in the cache is
549 * unbusy, and only reuse in that case. Otherwise,
550 * allocating a new buffer is probably faster than
551 * waiting for the GPU to finish.
553 bo
= LIST_ENTRY(struct brw_bo
, bucket
->head
.next
, head
);
554 if (!brw_bo_busy(bo
)) {
555 alloc_from_cache
= true;
560 if (alloc_from_cache
) {
561 if (!brw_bo_madvise(bo
, I915_MADV_WILLNEED
)) {
563 brw_bo_cache_purge_bucket(bufmgr
, bucket
);
567 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
)) {
573 void *map
= brw_bo_map(NULL
, bo
, MAP_WRITE
| MAP_RAW
);
578 memset(map
, 0, bo_size
);
583 if (alloc_from_cache
) {
584 /* If the cache BO isn't in the right memory zone, free the old
585 * memory and assign it a new address.
587 if ((bo
->kflags
& EXEC_OBJECT_PINNED
) &&
588 memzone
!= memzone_for_address(bo
->gtt_offset
)) {
589 vma_free(bufmgr
, bo
->gtt_offset
, bo
->size
);
590 bo
->gtt_offset
= 0ull;
593 bo
= calloc(1, sizeof(*bo
));
600 struct drm_i915_gem_create create
= { .size
= bo_size
};
602 /* All new BOs we get from the kernel are zeroed, so we don't need to
603 * worry about that here.
605 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CREATE
, &create
);
611 bo
->gem_handle
= create
.handle
;
615 bo
->tiling_mode
= I915_TILING_NONE
;
616 bo
->swizzle_mode
= I915_BIT_6_SWIZZLE_NONE
;
619 if (bo_set_tiling_internal(bo
, tiling_mode
, stride
))
622 /* Calling set_domain() will allocate pages for the BO outside of the
623 * struct mutex lock in the kernel, which is more efficient than waiting
624 * to create them during the first execbuf that uses the BO.
626 struct drm_i915_gem_set_domain sd
= {
627 .handle
= bo
->gem_handle
,
628 .read_domains
= I915_GEM_DOMAIN_CPU
,
632 if (drmIoctl(bo
->bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_DOMAIN
, &sd
) != 0)
637 p_atomic_set(&bo
->refcount
, 1);
639 bo
->cache_coherent
= bufmgr
->has_llc
;
641 bo
->kflags
= bufmgr
->initial_kflags
;
643 if ((bo
->kflags
& EXEC_OBJECT_PINNED
) && bo
->gtt_offset
== 0ull) {
644 bo
->gtt_offset
= vma_alloc(bufmgr
, memzone
, bo
->size
, 1);
646 if (bo
->gtt_offset
== 0ull)
650 mtx_unlock(&bufmgr
->lock
);
652 DBG("bo_create: buf %d (%s) %llub\n", bo
->gem_handle
, bo
->name
,
653 (unsigned long long) size
);
660 mtx_unlock(&bufmgr
->lock
);
665 brw_bo_alloc(struct brw_bufmgr
*bufmgr
,
666 const char *name
, uint64_t size
,
667 enum brw_memory_zone memzone
)
669 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
670 0, I915_TILING_NONE
, 0);
674 brw_bo_alloc_tiled(struct brw_bufmgr
*bufmgr
, const char *name
,
675 uint64_t size
, enum brw_memory_zone memzone
,
676 uint32_t tiling_mode
, uint32_t pitch
,
679 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
680 flags
, tiling_mode
, pitch
);
684 brw_bo_alloc_tiled_2d(struct brw_bufmgr
*bufmgr
, const char *name
,
685 int x
, int y
, int cpp
, enum brw_memory_zone memzone
,
686 uint32_t tiling
, uint32_t *pitch
, unsigned flags
)
690 unsigned long aligned_y
, height_alignment
;
692 /* If we're tiled, our allocations are in 8 or 32-row blocks,
693 * so failure to align our height means that we won't allocate
696 * If we're untiled, we still have to align to 2 rows high
697 * because the data port accesses 2x2 blocks even if the
698 * bottom row isn't to be rendered, so failure to align means
699 * we could walk off the end of the GTT and fault. This is
700 * documented on 965, and may be the case on older chipsets
701 * too so we try to be careful.
704 height_alignment
= 2;
706 if (tiling
== I915_TILING_X
)
707 height_alignment
= 8;
708 else if (tiling
== I915_TILING_Y
)
709 height_alignment
= 32;
710 aligned_y
= ALIGN(y
, height_alignment
);
713 stride
= bo_tile_pitch(bufmgr
, stride
, tiling
);
714 size
= stride
* aligned_y
;
715 size
= bo_tile_size(bufmgr
, size
, tiling
);
718 if (tiling
== I915_TILING_NONE
)
721 return bo_alloc_internal(bufmgr
, name
, size
, memzone
,
722 flags
, tiling
, stride
);
726 * Returns a brw_bo wrapping the given buffer object handle.
728 * This can be used when one application needs to pass a buffer object
732 brw_bo_gem_create_from_name(struct brw_bufmgr
*bufmgr
,
733 const char *name
, unsigned int handle
)
737 /* At the moment most applications only have a few named bo.
738 * For instance, in a DRI client only the render buffers passed
739 * between X and the client are named. And since X returns the
740 * alternating names for the front/back buffer a linear search
741 * provides a sufficiently fast match.
743 mtx_lock(&bufmgr
->lock
);
744 bo
= hash_find_bo(bufmgr
->name_table
, handle
);
746 brw_bo_reference(bo
);
750 struct drm_gem_open open_arg
= { .name
= handle
};
751 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_OPEN
, &open_arg
);
753 DBG("Couldn't reference %s handle 0x%08x: %s\n",
754 name
, handle
, strerror(errno
));
758 /* Now see if someone has used a prime handle to get this
759 * object from the kernel before by looking through the list
760 * again for a matching gem_handle
762 bo
= hash_find_bo(bufmgr
->handle_table
, open_arg
.handle
);
764 brw_bo_reference(bo
);
768 bo
= calloc(1, sizeof(*bo
));
772 p_atomic_set(&bo
->refcount
, 1);
774 bo
->size
= open_arg
.size
;
777 bo
->gem_handle
= open_arg
.handle
;
779 bo
->global_name
= handle
;
780 bo
->reusable
= false;
782 bo
->kflags
= bufmgr
->initial_kflags
;
784 if (bo
->kflags
& EXEC_OBJECT_PINNED
)
785 bo
->gtt_offset
= vma_alloc(bufmgr
, BRW_MEMZONE_OTHER
, bo
->size
, 1);
787 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
788 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
790 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
791 ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
);
795 bo
->tiling_mode
= get_tiling
.tiling_mode
;
796 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
797 /* XXX stride is unknown */
798 DBG("bo_create_from_handle: %d (%s)\n", handle
, bo
->name
);
801 mtx_unlock(&bufmgr
->lock
);
806 mtx_unlock(&bufmgr
->lock
);
811 bo_free(struct brw_bo
*bo
)
813 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
816 VG_NOACCESS(bo
->map_cpu
, bo
->size
);
817 drm_munmap(bo
->map_cpu
, bo
->size
);
820 VG_NOACCESS(bo
->map_wc
, bo
->size
);
821 drm_munmap(bo
->map_wc
, bo
->size
);
824 VG_NOACCESS(bo
->map_gtt
, bo
->size
);
825 drm_munmap(bo
->map_gtt
, bo
->size
);
829 struct hash_entry
*entry
;
831 if (bo
->global_name
) {
832 entry
= _mesa_hash_table_search(bufmgr
->name_table
, &bo
->global_name
);
833 _mesa_hash_table_remove(bufmgr
->name_table
, entry
);
836 entry
= _mesa_hash_table_search(bufmgr
->handle_table
, &bo
->gem_handle
);
837 _mesa_hash_table_remove(bufmgr
->handle_table
, entry
);
840 /* Close this object */
841 struct drm_gem_close close
= { .handle
= bo
->gem_handle
};
842 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_CLOSE
, &close
);
844 DBG("DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
845 bo
->gem_handle
, bo
->name
, strerror(errno
));
848 if (bo
->kflags
& EXEC_OBJECT_PINNED
)
849 vma_free(bo
->bufmgr
, bo
->gtt_offset
, bo
->size
);
854 /** Frees all cached buffers significantly older than @time. */
856 cleanup_bo_cache(struct brw_bufmgr
*bufmgr
, time_t time
)
860 if (bufmgr
->time
== time
)
863 for (i
= 0; i
< bufmgr
->num_buckets
; i
++) {
864 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
866 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
867 if (time
- bo
->free_time
<= 1)
880 bo_unreference_final(struct brw_bo
*bo
, time_t time
)
882 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
883 struct bo_cache_bucket
*bucket
;
885 DBG("bo_unreference final: %d (%s)\n", bo
->gem_handle
, bo
->name
);
887 bucket
= bucket_for_size(bufmgr
, bo
->size
);
888 /* Put the buffer into our internal cache for reuse if we can. */
889 if (bufmgr
->bo_reuse
&& bo
->reusable
&& bucket
!= NULL
&&
890 brw_bo_madvise(bo
, I915_MADV_DONTNEED
)) {
891 bo
->free_time
= time
;
895 list_addtail(&bo
->head
, &bucket
->head
);
902 brw_bo_unreference(struct brw_bo
*bo
)
907 assert(p_atomic_read(&bo
->refcount
) > 0);
909 if (atomic_add_unless(&bo
->refcount
, -1, 1)) {
910 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
911 struct timespec time
;
913 clock_gettime(CLOCK_MONOTONIC
, &time
);
915 mtx_lock(&bufmgr
->lock
);
917 if (p_atomic_dec_zero(&bo
->refcount
)) {
918 bo_unreference_final(bo
, time
.tv_sec
);
919 cleanup_bo_cache(bufmgr
, time
.tv_sec
);
922 mtx_unlock(&bufmgr
->lock
);
927 bo_wait_with_stall_warning(struct brw_context
*brw
,
931 bool busy
= brw
&& brw
->perf_debug
&& !bo
->idle
;
932 double elapsed
= unlikely(busy
) ? -get_time() : 0.0;
934 brw_bo_wait_rendering(bo
);
936 if (unlikely(busy
)) {
937 elapsed
+= get_time();
938 if (elapsed
> 1e-5) /* 0.01ms */
939 perf_debug("%s a busy \"%s\" BO stalled and took %.03f ms.\n",
940 action
, bo
->name
, elapsed
* 1000);
945 print_flags(unsigned flags
)
947 if (flags
& MAP_READ
)
949 if (flags
& MAP_WRITE
)
951 if (flags
& MAP_ASYNC
)
953 if (flags
& MAP_PERSISTENT
)
955 if (flags
& MAP_COHERENT
)
963 brw_bo_map_cpu(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
965 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
967 /* We disallow CPU maps for writing to non-coherent buffers, as the
968 * CPU map can become invalidated when a batch is flushed out, which
969 * can happen at unpredictable times. You should use WC maps instead.
971 assert(bo
->cache_coherent
|| !(flags
& MAP_WRITE
));
974 DBG("brw_bo_map_cpu: %d (%s)\n", bo
->gem_handle
, bo
->name
);
976 struct drm_i915_gem_mmap mmap_arg
= {
977 .handle
= bo
->gem_handle
,
980 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
982 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
983 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
986 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
987 VG_DEFINED(map
, bo
->size
);
989 if (p_atomic_cmpxchg(&bo
->map_cpu
, NULL
, map
)) {
990 VG_NOACCESS(map
, bo
->size
);
991 drm_munmap(map
, bo
->size
);
996 DBG("brw_bo_map_cpu: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
,
1000 if (!(flags
& MAP_ASYNC
)) {
1001 bo_wait_with_stall_warning(brw
, bo
, "CPU mapping");
1004 if (!bo
->cache_coherent
&& !bo
->bufmgr
->has_llc
) {
1005 /* If we're reusing an existing CPU mapping, the CPU caches may
1006 * contain stale data from the last time we read from that mapping.
1007 * (With the BO cache, it might even be data from a previous buffer!)
1008 * Even if it's a brand new mapping, the kernel may have zeroed the
1009 * buffer via CPU writes.
1011 * We need to invalidate those cachelines so that we see the latest
1012 * contents, and so long as we only read from the CPU mmap we do not
1013 * need to write those cachelines back afterwards.
1015 * On LLC, the emprical evidence suggests that writes from the GPU
1016 * that bypass the LLC (i.e. for scanout) do *invalidate* the CPU
1017 * cachelines. (Other reads, such as the display engine, bypass the
1018 * LLC entirely requiring us to keep dirty pixels for the scanout
1019 * out of any cache.)
1021 gen_invalidate_range(bo
->map_cpu
, bo
->size
);
1028 brw_bo_map_wc(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
1030 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1032 if (!bufmgr
->has_mmap_wc
)
1036 DBG("brw_bo_map_wc: %d (%s)\n", bo
->gem_handle
, bo
->name
);
1038 struct drm_i915_gem_mmap mmap_arg
= {
1039 .handle
= bo
->gem_handle
,
1041 .flags
= I915_MMAP_WC
,
1043 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP
, &mmap_arg
);
1045 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1046 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1050 void *map
= (void *) (uintptr_t) mmap_arg
.addr_ptr
;
1051 VG_DEFINED(map
, bo
->size
);
1053 if (p_atomic_cmpxchg(&bo
->map_wc
, NULL
, map
)) {
1054 VG_NOACCESS(map
, bo
->size
);
1055 drm_munmap(map
, bo
->size
);
1060 DBG("brw_bo_map_wc: %d (%s) -> %p\n", bo
->gem_handle
, bo
->name
, bo
->map_wc
);
1063 if (!(flags
& MAP_ASYNC
)) {
1064 bo_wait_with_stall_warning(brw
, bo
, "WC mapping");
1071 * Perform an uncached mapping via the GTT.
1073 * Write access through the GTT is not quite fully coherent. On low power
1074 * systems especially, like modern Atoms, we can observe reads from RAM before
1075 * the write via GTT has landed. A write memory barrier that flushes the Write
1076 * Combining Buffer (i.e. sfence/mfence) is not sufficient to order the later
1077 * read after the write as the GTT write suffers a small delay through the GTT
1078 * indirection. The kernel uses an uncached mmio read to ensure the GTT write
1079 * is ordered with reads (either by the GPU, WB or WC) and unconditionally
1080 * flushes prior to execbuf submission. However, if we are not informing the
1081 * kernel about our GTT writes, it will not flush before earlier access, such
1082 * as when using the cmdparser. Similarly, we need to be careful if we should
1083 * ever issue a CPU read immediately following a GTT write.
1085 * Telling the kernel about write access also has one more important
1086 * side-effect. Upon receiving notification about the write, it cancels any
1087 * scanout buffering for FBC/PSR and friends. Later FBC/PSR is then flushed by
1088 * either SW_FINISH or DIRTYFB. The presumption is that we never write to the
1089 * actual scanout via a mmaping, only to a backbuffer and so all the FBC/PSR
1090 * tracking is handled on the buffer exchange instead.
1093 brw_bo_map_gtt(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
1095 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1097 /* Get a mapping of the buffer if we haven't before. */
1098 if (bo
->map_gtt
== NULL
) {
1099 DBG("bo_map_gtt: mmap %d (%s)\n", bo
->gem_handle
, bo
->name
);
1101 struct drm_i915_gem_mmap_gtt mmap_arg
= { .handle
= bo
->gem_handle
};
1103 /* Get the fake offset back... */
1104 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_MMAP_GTT
, &mmap_arg
);
1106 DBG("%s:%d: Error preparing buffer map %d (%s): %s .\n",
1107 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1112 void *map
= drm_mmap(0, bo
->size
, PROT_READ
| PROT_WRITE
,
1113 MAP_SHARED
, bufmgr
->fd
, mmap_arg
.offset
);
1114 if (map
== MAP_FAILED
) {
1115 DBG("%s:%d: Error mapping buffer %d (%s): %s .\n",
1116 __FILE__
, __LINE__
, bo
->gem_handle
, bo
->name
, strerror(errno
));
1120 /* We don't need to use VALGRIND_MALLOCLIKE_BLOCK because Valgrind will
1121 * already intercept this mmap call. However, for consistency between
1122 * all the mmap paths, we mark the pointer as defined now and mark it
1123 * as inaccessible afterwards.
1125 VG_DEFINED(map
, bo
->size
);
1127 if (p_atomic_cmpxchg(&bo
->map_gtt
, NULL
, map
)) {
1128 VG_NOACCESS(map
, bo
->size
);
1129 drm_munmap(map
, bo
->size
);
1132 assert(bo
->map_gtt
);
1134 DBG("bo_map_gtt: %d (%s) -> %p, ", bo
->gem_handle
, bo
->name
, bo
->map_gtt
);
1137 if (!(flags
& MAP_ASYNC
)) {
1138 bo_wait_with_stall_warning(brw
, bo
, "GTT mapping");
1145 can_map_cpu(struct brw_bo
*bo
, unsigned flags
)
1147 if (bo
->cache_coherent
)
1150 /* Even if the buffer itself is not cache-coherent (such as a scanout), on
1151 * an LLC platform reads always are coherent (as they are performed via the
1152 * central system agent). It is just the writes that we need to take special
1153 * care to ensure that land in main memory and not stick in the CPU cache.
1155 if (!(flags
& MAP_WRITE
) && bo
->bufmgr
->has_llc
)
1158 /* If PERSISTENT or COHERENT are set, the mmapping needs to remain valid
1159 * across batch flushes where the kernel will change cache domains of the
1160 * bo, invalidating continued access to the CPU mmap on non-LLC device.
1162 * Similarly, ASYNC typically means that the buffer will be accessed via
1163 * both the CPU and the GPU simultaneously. Batches may be executed that
1164 * use the BO even while it is mapped. While OpenGL technically disallows
1165 * most drawing while non-persistent mappings are active, we may still use
1166 * the GPU for blits or other operations, causing batches to happen at
1167 * inconvenient times.
1169 if (flags
& (MAP_PERSISTENT
| MAP_COHERENT
| MAP_ASYNC
))
1172 return !(flags
& MAP_WRITE
);
1176 brw_bo_map(struct brw_context
*brw
, struct brw_bo
*bo
, unsigned flags
)
1178 if (bo
->tiling_mode
!= I915_TILING_NONE
&& !(flags
& MAP_RAW
))
1179 return brw_bo_map_gtt(brw
, bo
, flags
);
1183 if (can_map_cpu(bo
, flags
))
1184 map
= brw_bo_map_cpu(brw
, bo
, flags
);
1186 map
= brw_bo_map_wc(brw
, bo
, flags
);
1188 /* Allow the attempt to fail by falling back to the GTT where necessary.
1190 * Not every buffer can be mmaped directly using the CPU (or WC), for
1191 * example buffers that wrap stolen memory or are imported from other
1192 * devices. For those, we have little choice but to use a GTT mmapping.
1193 * However, if we use a slow GTT mmapping for reads where we expected fast
1194 * access, that order of magnitude difference in throughput will be clearly
1195 * expressed by angry users.
1197 * We skip MAP_RAW because we want to avoid map_gtt's fence detiling.
1199 if (!map
&& !(flags
& MAP_RAW
)) {
1201 perf_debug("Fallback GTT mapping for %s with access flags %x\n",
1204 map
= brw_bo_map_gtt(brw
, bo
, flags
);
1211 brw_bo_subdata(struct brw_bo
*bo
, uint64_t offset
,
1212 uint64_t size
, const void *data
)
1214 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1216 struct drm_i915_gem_pwrite pwrite
= {
1217 .handle
= bo
->gem_handle
,
1220 .data_ptr
= (uint64_t) (uintptr_t) data
,
1223 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_PWRITE
, &pwrite
);
1226 DBG("%s:%d: Error writing data to buffer %d: "
1227 "(%"PRIu64
" %"PRIu64
") %s .\n",
1228 __FILE__
, __LINE__
, bo
->gem_handle
, offset
, size
, strerror(errno
));
1234 /** Waits for all GPU rendering with the object to have completed. */
1236 brw_bo_wait_rendering(struct brw_bo
*bo
)
1238 /* We require a kernel recent enough for WAIT_IOCTL support.
1239 * See intel_init_bufmgr()
1241 brw_bo_wait(bo
, -1);
1245 * Waits on a BO for the given amount of time.
1247 * @bo: buffer object to wait for
1248 * @timeout_ns: amount of time to wait in nanoseconds.
1249 * If value is less than 0, an infinite wait will occur.
1251 * Returns 0 if the wait was successful ie. the last batch referencing the
1252 * object has completed within the allotted time. Otherwise some negative return
1253 * value describes the error. Of particular interest is -ETIME when the wait has
1254 * failed to yield the desired result.
1256 * Similar to brw_bo_wait_rendering except a timeout parameter allows
1257 * the operation to give up after a certain amount of time. Another subtle
1258 * difference is the internal locking semantics are different (this variant does
1259 * not hold the lock for the duration of the wait). This makes the wait subject
1260 * to a larger userspace race window.
1262 * The implementation shall wait until the object is no longer actively
1263 * referenced within a batch buffer at the time of the call. The wait will
1264 * not guarantee that the buffer is re-issued via another thread, or an flinked
1265 * handle. Userspace must make sure this race does not occur if such precision
1268 * Note that some kernels have broken the inifite wait for negative values
1269 * promise, upgrade to latest stable kernels if this is the case.
1272 brw_bo_wait(struct brw_bo
*bo
, int64_t timeout_ns
)
1274 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1276 /* If we know it's idle, don't bother with the kernel round trip */
1277 if (bo
->idle
&& !bo
->external
)
1280 struct drm_i915_gem_wait wait
= {
1281 .bo_handle
= bo
->gem_handle
,
1282 .timeout_ns
= timeout_ns
,
1284 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_WAIT
, &wait
);
1294 brw_bufmgr_destroy(struct brw_bufmgr
*bufmgr
)
1296 mtx_destroy(&bufmgr
->lock
);
1298 /* Free any cached buffer objects we were going to reuse */
1299 for (int i
= 0; i
< bufmgr
->num_buckets
; i
++) {
1300 struct bo_cache_bucket
*bucket
= &bufmgr
->cache_bucket
[i
];
1302 list_for_each_entry_safe(struct brw_bo
, bo
, &bucket
->head
, head
) {
1303 list_del(&bo
->head
);
1308 if (brw_using_softpin(bufmgr
)) {
1309 for (int z
= 0; z
< BRW_MEMZONE_COUNT
; z
++) {
1310 util_dynarray_fini(&bucket
->vma_list
[z
]);
1315 _mesa_hash_table_destroy(bufmgr
->name_table
, NULL
);
1316 _mesa_hash_table_destroy(bufmgr
->handle_table
, NULL
);
1318 if (brw_using_softpin(bufmgr
)) {
1319 for (int z
= 0; z
< BRW_MEMZONE_COUNT
; z
++) {
1320 util_vma_heap_finish(&bufmgr
->vma_allocator
[z
]);
1328 bo_set_tiling_internal(struct brw_bo
*bo
, uint32_t tiling_mode
,
1331 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1332 struct drm_i915_gem_set_tiling set_tiling
;
1335 if (bo
->global_name
== 0 &&
1336 tiling_mode
== bo
->tiling_mode
&& stride
== bo
->stride
)
1339 memset(&set_tiling
, 0, sizeof(set_tiling
));
1341 /* set_tiling is slightly broken and overwrites the
1342 * input on the error path, so we have to open code
1345 set_tiling
.handle
= bo
->gem_handle
;
1346 set_tiling
.tiling_mode
= tiling_mode
;
1347 set_tiling
.stride
= stride
;
1349 ret
= ioctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_SET_TILING
, &set_tiling
);
1350 } while (ret
== -1 && (errno
== EINTR
|| errno
== EAGAIN
));
1354 bo
->tiling_mode
= set_tiling
.tiling_mode
;
1355 bo
->swizzle_mode
= set_tiling
.swizzle_mode
;
1356 bo
->stride
= set_tiling
.stride
;
1361 brw_bo_get_tiling(struct brw_bo
*bo
, uint32_t *tiling_mode
,
1362 uint32_t *swizzle_mode
)
1364 *tiling_mode
= bo
->tiling_mode
;
1365 *swizzle_mode
= bo
->swizzle_mode
;
1369 static struct brw_bo
*
1370 brw_bo_gem_create_from_prime_internal(struct brw_bufmgr
*bufmgr
, int prime_fd
,
1371 int tiling_mode
, uint32_t stride
)
1376 mtx_lock(&bufmgr
->lock
);
1377 int ret
= drmPrimeFDToHandle(bufmgr
->fd
, prime_fd
, &handle
);
1379 DBG("create_from_prime: failed to obtain handle from fd: %s\n",
1381 mtx_unlock(&bufmgr
->lock
);
1386 * See if the kernel has already returned this buffer to us. Just as
1387 * for named buffers, we must not create two bo's pointing at the same
1390 bo
= hash_find_bo(bufmgr
->handle_table
, handle
);
1392 brw_bo_reference(bo
);
1396 bo
= calloc(1, sizeof(*bo
));
1400 p_atomic_set(&bo
->refcount
, 1);
1402 /* Determine size of bo. The fd-to-handle ioctl really should
1403 * return the size, but it doesn't. If we have kernel 3.12 or
1404 * later, we can lseek on the prime fd to get the size. Older
1405 * kernels will just fail, in which case we fall back to the
1406 * provided (estimated or guess size). */
1407 ret
= lseek(prime_fd
, 0, SEEK_END
);
1411 bo
->bufmgr
= bufmgr
;
1413 bo
->gem_handle
= handle
;
1414 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1417 bo
->reusable
= false;
1418 bo
->external
= true;
1419 bo
->kflags
= bufmgr
->initial_kflags
;
1421 if (bo
->kflags
& EXEC_OBJECT_PINNED
) {
1422 assert(bo
->size
> 0);
1423 bo
->gtt_offset
= vma_alloc(bufmgr
, BRW_MEMZONE_OTHER
, bo
->size
, 1);
1426 if (tiling_mode
< 0) {
1427 struct drm_i915_gem_get_tiling get_tiling
= { .handle
= bo
->gem_handle
};
1428 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_GET_TILING
, &get_tiling
))
1431 bo
->tiling_mode
= get_tiling
.tiling_mode
;
1432 bo
->swizzle_mode
= get_tiling
.swizzle_mode
;
1433 /* XXX stride is unknown */
1435 bo_set_tiling_internal(bo
, tiling_mode
, stride
);
1439 mtx_unlock(&bufmgr
->lock
);
1444 mtx_unlock(&bufmgr
->lock
);
1449 brw_bo_gem_create_from_prime(struct brw_bufmgr
*bufmgr
, int prime_fd
)
1451 return brw_bo_gem_create_from_prime_internal(bufmgr
, prime_fd
, -1, 0);
1455 brw_bo_gem_create_from_prime_tiled(struct brw_bufmgr
*bufmgr
, int prime_fd
,
1456 uint32_t tiling_mode
, uint32_t stride
)
1458 assert(tiling_mode
== I915_TILING_NONE
||
1459 tiling_mode
== I915_TILING_X
||
1460 tiling_mode
== I915_TILING_Y
);
1462 return brw_bo_gem_create_from_prime_internal(bufmgr
, prime_fd
,
1463 tiling_mode
, stride
);
1467 brw_bo_make_external(struct brw_bo
*bo
)
1469 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1471 if (!bo
->external
) {
1472 mtx_lock(&bufmgr
->lock
);
1473 if (!bo
->external
) {
1474 _mesa_hash_table_insert(bufmgr
->handle_table
, &bo
->gem_handle
, bo
);
1475 bo
->external
= true;
1477 mtx_unlock(&bufmgr
->lock
);
1482 brw_bo_gem_export_to_prime(struct brw_bo
*bo
, int *prime_fd
)
1484 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1486 brw_bo_make_external(bo
);
1488 if (drmPrimeHandleToFD(bufmgr
->fd
, bo
->gem_handle
,
1489 DRM_CLOEXEC
, prime_fd
) != 0)
1492 bo
->reusable
= false;
1498 brw_bo_export_gem_handle(struct brw_bo
*bo
)
1500 brw_bo_make_external(bo
);
1502 return bo
->gem_handle
;
1506 brw_bo_flink(struct brw_bo
*bo
, uint32_t *name
)
1508 struct brw_bufmgr
*bufmgr
= bo
->bufmgr
;
1510 if (!bo
->global_name
) {
1511 struct drm_gem_flink flink
= { .handle
= bo
->gem_handle
};
1513 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_GEM_FLINK
, &flink
))
1516 brw_bo_make_external(bo
);
1517 mtx_lock(&bufmgr
->lock
);
1518 if (!bo
->global_name
) {
1519 bo
->global_name
= flink
.name
;
1520 _mesa_hash_table_insert(bufmgr
->name_table
, &bo
->global_name
, bo
);
1522 mtx_unlock(&bufmgr
->lock
);
1524 bo
->reusable
= false;
1527 *name
= bo
->global_name
;
1532 add_bucket(struct brw_bufmgr
*bufmgr
, int size
)
1534 unsigned int i
= bufmgr
->num_buckets
;
1536 assert(i
< ARRAY_SIZE(bufmgr
->cache_bucket
));
1538 list_inithead(&bufmgr
->cache_bucket
[i
].head
);
1539 if (brw_using_softpin(bufmgr
)) {
1540 for (int z
= 0; z
< BRW_MEMZONE_COUNT
; z
++)
1541 util_dynarray_init(&bufmgr
->cache_bucket
[i
].vma_list
[z
], NULL
);
1543 bufmgr
->cache_bucket
[i
].size
= size
;
1544 bufmgr
->num_buckets
++;
1546 assert(bucket_for_size(bufmgr
, size
) == &bufmgr
->cache_bucket
[i
]);
1547 assert(bucket_for_size(bufmgr
, size
- 2048) == &bufmgr
->cache_bucket
[i
]);
1548 assert(bucket_for_size(bufmgr
, size
+ 1) != &bufmgr
->cache_bucket
[i
]);
1552 init_cache_buckets(struct brw_bufmgr
*bufmgr
)
1554 uint64_t size
, cache_max_size
= 64 * 1024 * 1024;
1556 /* OK, so power of two buckets was too wasteful of memory.
1557 * Give 3 other sizes between each power of two, to hopefully
1558 * cover things accurately enough. (The alternative is
1559 * probably to just go for exact matching of sizes, and assume
1560 * that for things like composited window resize the tiled
1561 * width/height alignment and rounding of sizes to pages will
1562 * get us useful cache hit rates anyway)
1564 add_bucket(bufmgr
, PAGE_SIZE
);
1565 add_bucket(bufmgr
, PAGE_SIZE
* 2);
1566 add_bucket(bufmgr
, PAGE_SIZE
* 3);
1568 /* Initialize the linked lists for BO reuse cache. */
1569 for (size
= 4 * PAGE_SIZE
; size
<= cache_max_size
; size
*= 2) {
1570 add_bucket(bufmgr
, size
);
1572 add_bucket(bufmgr
, size
+ size
* 1 / 4);
1573 add_bucket(bufmgr
, size
+ size
* 2 / 4);
1574 add_bucket(bufmgr
, size
+ size
* 3 / 4);
1579 brw_create_hw_context(struct brw_bufmgr
*bufmgr
)
1581 struct drm_i915_gem_context_create create
= { };
1582 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_CREATE
, &create
);
1584 DBG("DRM_IOCTL_I915_GEM_CONTEXT_CREATE failed: %s\n", strerror(errno
));
1588 return create
.ctx_id
;
1592 brw_hw_context_set_priority(struct brw_bufmgr
*bufmgr
,
1596 struct drm_i915_gem_context_param p
= {
1598 .param
= I915_CONTEXT_PARAM_PRIORITY
,
1604 if (drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM
, &p
))
1611 brw_destroy_hw_context(struct brw_bufmgr
*bufmgr
, uint32_t ctx_id
)
1613 struct drm_i915_gem_context_destroy d
= { .ctx_id
= ctx_id
};
1616 drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_GEM_CONTEXT_DESTROY
, &d
) != 0) {
1617 fprintf(stderr
, "DRM_IOCTL_I915_GEM_CONTEXT_DESTROY failed: %s\n",
1623 brw_reg_read(struct brw_bufmgr
*bufmgr
, uint32_t offset
, uint64_t *result
)
1625 struct drm_i915_reg_read reg_read
= { .offset
= offset
};
1626 int ret
= drmIoctl(bufmgr
->fd
, DRM_IOCTL_I915_REG_READ
, ®_read
);
1628 *result
= reg_read
.val
;
1633 gem_param(int fd
, int name
)
1635 int v
= -1; /* No param uses (yet) the sign bit, reserve it for errors */
1637 struct drm_i915_getparam gp
= { .param
= name
, .value
= &v
};
1638 if (drmIoctl(fd
, DRM_IOCTL_I915_GETPARAM
, &gp
))
1645 gem_context_getparam(int fd
, uint32_t context
, uint64_t param
, uint64_t *value
)
1647 struct drm_i915_gem_context_param gp
= {
1652 if (drmIoctl(fd
, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
, &gp
))
1661 brw_using_softpin(struct brw_bufmgr
*bufmgr
)
1663 return bufmgr
->initial_kflags
& EXEC_OBJECT_PINNED
;
1667 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1668 * and manage map buffer objections.
1670 * \param fd File descriptor of the opened DRM device.
1673 brw_bufmgr_init(struct gen_device_info
*devinfo
, int fd
, bool bo_reuse
)
1675 struct brw_bufmgr
*bufmgr
;
1677 bufmgr
= calloc(1, sizeof(*bufmgr
));
1681 /* Handles to buffer objects belong to the device fd and are not
1682 * reference counted by the kernel. If the same fd is used by
1683 * multiple parties (threads sharing the same screen bufmgr, or
1684 * even worse the same device fd passed to multiple libraries)
1685 * ownership of those handles is shared by those independent parties.
1687 * Don't do this! Ensure that each library/bufmgr has its own device
1688 * fd so that its namespace does not clash with another.
1692 if (mtx_init(&bufmgr
->lock
, mtx_plain
) != 0) {
1698 if (gem_context_getparam(fd
, 0, I915_CONTEXT_PARAM_GTT_SIZE
, >t_size
))
1701 bufmgr
->has_llc
= devinfo
->has_llc
;
1702 bufmgr
->has_mmap_wc
= gem_param(fd
, I915_PARAM_MMAP_VERSION
) > 0;
1703 bufmgr
->bo_reuse
= bo_reuse
;
1705 const uint64_t _4GB
= 4ull << 30;
1707 /* The STATE_BASE_ADDRESS size field can only hold 1 page shy of 4GB */
1708 const uint64_t _4GB_minus_1
= _4GB
- PAGE_SIZE
;
1710 if (devinfo
->gen
>= 8 && gtt_size
> _4GB
) {
1711 bufmgr
->initial_kflags
|= EXEC_OBJECT_SUPPORTS_48B_ADDRESS
;
1713 /* Allocate VMA in userspace if we have softpin and full PPGTT. */
1714 if (gem_param(fd
, I915_PARAM_HAS_EXEC_SOFTPIN
) > 0 &&
1715 gem_param(fd
, I915_PARAM_HAS_ALIASING_PPGTT
) > 1) {
1716 bufmgr
->initial_kflags
|= EXEC_OBJECT_PINNED
;
1718 util_vma_heap_init(&bufmgr
->vma_allocator
[BRW_MEMZONE_LOW_4G
],
1719 PAGE_SIZE
, _4GB_minus_1
);
1721 /* Leave the last 4GB out of the high vma range, so that no state
1722 * base address + size can overflow 48 bits.
1724 util_vma_heap_init(&bufmgr
->vma_allocator
[BRW_MEMZONE_OTHER
],
1725 1 * _4GB
, gtt_size
- 2 * _4GB
);
1726 } else if (devinfo
->gen
>= 10) {
1727 /* Softpin landed in 4.5, but GVT used an aliasing PPGTT until
1728 * kernel commit 6b3816d69628becb7ff35978aa0751798b4a940a in
1729 * 4.14. Gen10+ GVT hasn't landed yet, so it's not actually a
1730 * problem - but extending this requirement back to earlier gens
1731 * might actually mean requiring 4.14.
1733 fprintf(stderr
, "i965 requires softpin (Kernel 4.5) on Gen10+.");
1739 init_cache_buckets(bufmgr
);
1741 bufmgr
->name_table
=
1742 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);
1743 bufmgr
->handle_table
=
1744 _mesa_hash_table_create(NULL
, key_hash_uint
, key_uint_equal
);