src/mesa/drivers/dri/i965/brw_bufmgr.h

   1 /*
   2  * Copyright © 2008-2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 /**
  29  * @file brw_bufmgr.h
  30  *
  31  * Public definitions of Intel-specific bufmgr functions.
  32  */
  33
  34 #ifndef INTEL_BUFMGR_H
  35 #define INTEL_BUFMGR_H
  36
  37 #include <stdbool.h>
  38 #include <stdint.h>
  39 #include <stdio.h>
  40 #include "util/list.h"
  41
  42 #if defined(__cplusplus)
  43 extern "C" {
  44 #endif
  45
  46 struct gen_device_info;
  47 struct brw_context;
  48
  49 struct brw_bo {
  50    /**
  51     * Size in bytes of the buffer object.
  52     *
  53     * The size may be larger than the size originally requested for the
  54     * allocation, such as being aligned to page size.
  55     */
  56    uint64_t size;
  57
  58    /**
  59     * Alignment requirement for object
  60     *
  61     * Used for GTT mapping & pinning the object.
  62     */
  63    uint64_t align;
  64
  65    /** Buffer manager context associated with this buffer object */
  66    struct brw_bufmgr *bufmgr;
  67
  68    /** The GEM handle for this buffer object. */
  69    uint32_t gem_handle;
  70
  71    /**
  72     * Last seen card virtual address (offset from the beginning of the
  73     * aperture) for the object.  This should be used to fill relocation
  74     * entries when calling brw_bo_emit_reloc()
  75     */
  76    uint64_t offset64;
  77
  78    /**
  79     * Boolean of whether the GPU is definitely not accessing the buffer.
  80     *
  81     * This is only valid when reusable, since non-reusable
  82     * buffers are those that have been shared with other
  83     * processes, so we don't know their state.
  84     */
  85    bool idle;
  86
  87    int refcount;
  88    const char *name;
  89
  90 #ifndef EXEC_OBJECT_CAPTURE
  91 #define EXEC_OBJECT_CAPTURE            (1<<7)
  92 #endif
  93    uint64_t kflags;
  94
  95    /**
  96     * Kenel-assigned global name for this object
  97     *
  98     * List contains both flink named and prime fd'd objects
  99     */
 100    unsigned int global_name;
 101
 102    /**
 103     * Current tiling mode
 104     */
 105    uint32_t tiling_mode;
 106    uint32_t swizzle_mode;
 107    uint32_t stride;
 108
 109    time_t free_time;
 110
 111    /** Mapped address for the buffer, saved across map/unmap cycles */
 112    void *map_cpu;
 113    /** GTT virtual address for the buffer, saved across map/unmap cycles */
 114    void *map_gtt;
 115    /** WC CPU address for the buffer, saved across map/unmap cycles */
 116    void *map_wc;
 117
 118    /** BO cache list */
 119    struct list_head head;
 120
 121    /**
 122     * Boolean of whether this buffer can be re-used
 123     */
 124    bool reusable;
 125
 126    /**
 127     * Boolean of whether this buffer has been shared with an external client.
 128     */
 129    bool external;
 130
 131    /**
 132     * Boolean of whether this buffer is cache coherent
 133     */
 134    bool cache_coherent;
 135 };
 136
 137 #define BO_ALLOC_FOR_RENDER (1<<0)
 138 #define BO_ALLOC_ZEROED     (1<<1)
 139
 140 /**
 141  * Allocate a buffer object.
 142  *
 143  * Buffer objects are not necessarily initially mapped into CPU virtual
 144  * address space or graphics device aperture.  They must be mapped
 145  * using brw_bo_map() to be used by the CPU.
 146  */
 147 struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
 148                             uint64_t size, uint64_t alignment);
 149
 150 /**
 151  * Allocate a tiled buffer object.
 152  *
 153  * Alignment for tiled objects is set automatically; the 'flags'
 154  * argument provides a hint about how the object will be used initially.
 155  *
 156  * Valid tiling formats are:
 157  *  I915_TILING_NONE
 158  *  I915_TILING_X
 159  *  I915_TILING_Y
 160  */
 161 struct brw_bo *brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr,
 162                                   const char *name,
 163                                   uint64_t size,
 164                                   uint32_t tiling_mode,
 165                                   uint32_t pitch,
 166                                   unsigned flags);
 167
 168 /**
 169  * Allocate a tiled buffer object.
 170  *
 171  * Alignment for tiled objects is set automatically; the 'flags'
 172  * argument provides a hint about how the object will be used initially.
 173  *
 174  * Valid tiling formats are:
 175  *  I915_TILING_NONE
 176  *  I915_TILING_X
 177  *  I915_TILING_Y
 178  *
 179  * Note the tiling format may be rejected; callers should check the
 180  * 'tiling_mode' field on return, as well as the pitch value, which
 181  * may have been rounded up to accommodate for tiling restrictions.
 182  */
 183 struct brw_bo *brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr,
 184                                      const char *name,
 185                                      int x, int y, int cpp,
 186                                      uint32_t tiling_mode,
 187                                      uint32_t *pitch,
 188                                      unsigned flags);
 189
 190 /** Takes a reference on a buffer object */
 191 void brw_bo_reference(struct brw_bo *bo);
 192
 193 /**
 194  * Releases a reference on a buffer object, freeing the data if
 195  * no references remain.
 196  */
 197 void brw_bo_unreference(struct brw_bo *bo);
 198
 199 /* Must match MapBufferRange interface (for convenience) */
 200 #define MAP_READ        GL_MAP_READ_BIT
 201 #define MAP_WRITE       GL_MAP_WRITE_BIT
 202 #define MAP_ASYNC       GL_MAP_UNSYNCHRONIZED_BIT
 203 #define MAP_PERSISTENT  GL_MAP_PERSISTENT_BIT
 204 #define MAP_COHERENT    GL_MAP_COHERENT_BIT
 205 /* internal */
 206 #define MAP_INTERNAL_MASK       (0xff << 24)
 207 #define MAP_RAW                 (0x01 << 24)
 208
 209 /**
 210  * Maps the buffer into userspace.
 211  *
 212  * This function will block waiting for any existing execution on the
 213  * buffer to complete, first.  The resulting mapping is returned.
 214  */
 215 MUST_CHECK void *brw_bo_map(struct brw_context *brw, struct brw_bo *bo, unsigned flags);
 216
 217 /**
 218  * Reduces the refcount on the userspace mapping of the buffer
 219  * object.
 220  */
 221 static inline int brw_bo_unmap(struct brw_bo *bo) { return 0; }
 222
 223 /** Write data into an object. */
 224 int brw_bo_subdata(struct brw_bo *bo, uint64_t offset,
 225                    uint64_t size, const void *data);
 226 /**
 227  * Waits for rendering to an object by the GPU to have completed.
 228  *
 229  * This is not required for any access to the BO by bo_map,
 230  * bo_subdata, etc.  It is merely a way for the driver to implement
 231  * glFinish.
 232  */
 233 void brw_bo_wait_rendering(struct brw_bo *bo);
 234
 235 /**
 236  * Tears down the buffer manager instance.
 237  */
 238 void brw_bufmgr_destroy(struct brw_bufmgr *bufmgr);
 239
 240 /**
 241  * Get the current tiling (and resulting swizzling) mode for the bo.
 242  *
 243  * \param buf Buffer to get tiling mode for
 244  * \param tiling_mode returned tiling mode
 245  * \param swizzle_mode returned swizzling mode
 246  */
 247 int brw_bo_get_tiling(struct brw_bo *bo, uint32_t *tiling_mode,
 248                       uint32_t *swizzle_mode);
 249
 250 /**
 251  * Create a visible name for a buffer which can be used by other apps
 252  *
 253  * \param buf Buffer to create a name for
 254  * \param name Returned name
 255  */
 256 int brw_bo_flink(struct brw_bo *bo, uint32_t *name);
 257
 258 /**
 259  * Returns 1 if mapping the buffer for write could cause the process
 260  * to block, due to the object being active in the GPU.
 261  */
 262 int brw_bo_busy(struct brw_bo *bo);
 263
 264 /**
 265  * Specify the volatility of the buffer.
 266  * \param bo Buffer to create a name for
 267  * \param madv The purgeable status
 268  *
 269  * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
 270  * reclaimed under memory pressure. If you subsequently require the buffer,
 271  * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
 272  *
 273  * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
 274  * marked as I915_MADV_DONTNEED.
 275  */
 276 int brw_bo_madvise(struct brw_bo *bo, int madv);
 277
 278 /* drm_bacon_bufmgr_gem.c */
 279 struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo,
 280                                    int fd, int batch_size);
 281 struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
 282                                            const char *name,
 283                                            unsigned int handle);
 284 void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr);
 285
 286 int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns);
 287
 288 uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr);
 289 void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id);
 290
 291 int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd);
 292 struct brw_bo *brw_bo_gem_create_from_prime(struct brw_bufmgr *bufmgr,
 293                                             int prime_fd);
 294
 295 int brw_reg_read(struct brw_bufmgr *bufmgr, uint32_t offset,
 296                  uint64_t *result);
 297
 298 /** @{ */
 299
 300 #if defined(__cplusplus)
 301 }
 302 #endif
 303 #endif /* INTEL_BUFMGR_H */