src/mesa/drivers/dri/i965/brw_clip_state.c

   1 /*
   2  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
   3  Intel funded Tungsten Graphics to
   4  develop this 3D driver.
   5
   6  Permission is hereby granted, free of charge, to any person obtaining
   7  a copy of this software and associated documentation files (the
   8  "Software"), to deal in the Software without restriction, including
   9  without limitation the rights to use, copy, modify, merge, publish,
  10  distribute, sublicense, and/or sell copies of the Software, and to
  11  permit persons to whom the Software is furnished to do so, subject to
  12  the following conditions:
  13
  14  The above copyright notice and this permission notice (including the
  15  next paragraph) shall be included in all copies or substantial
  16  portions of the Software.
  17
  18  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25
  26  **********************************************************************/
  27  /*
  28   * Authors:
  29   *   Keith Whitwell <keithw@vmware.com>
  30   */
  31
  32 #include "brw_context.h"
  33 #include "brw_state.h"
  34 #include "brw_defines.h"
  35
  36 static void
  37 upload_clip_vp(struct brw_context *brw)
  38 {
  39    struct gl_context *ctx = &brw->ctx;
  40    struct brw_clipper_viewport *vp;
  41
  42    vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
  43                         sizeof(*vp), 32, &brw->clip.vp_offset);
  44
  45    const float maximum_post_clamp_delta = 4096;
  46    float gbx = maximum_post_clamp_delta / (float) ctx->Viewport.Width;
  47    float gby = maximum_post_clamp_delta / (float) ctx->Viewport.Height;
  48
  49    vp->xmin = -gbx;
  50    vp->xmax = gbx;
  51    vp->ymin = -gby;
  52    vp->ymax = gby;
  53 }
  54
  55 static void
  56 brw_upload_clip_unit(struct brw_context *brw)
  57 {
  58    struct gl_context *ctx = &brw->ctx;
  59    struct brw_clip_unit_state *clip;
  60
  61    /* _NEW_BUFFERS */
  62    struct gl_framebuffer *fb = ctx->DrawBuffer;
  63
  64    upload_clip_vp(brw);
  65
  66    clip = brw_state_batch(brw, AUB_TRACE_CLIP_STATE,
  67                           sizeof(*clip), 32, &brw->clip.state_offset);
  68    memset(clip, 0, sizeof(*clip));
  69
  70    /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_CLIP_PROG */
  71    clip->thread0.grf_reg_count = (ALIGN(brw->clip.prog_data->total_grf, 16) /
  72                                  16 - 1);
  73    clip->thread0.kernel_start_pointer =
  74       brw_program_reloc(brw,
  75                         brw->clip.state_offset +
  76                         offsetof(struct brw_clip_unit_state, thread0),
  77                         brw->clip.prog_offset +
  78                         (clip->thread0.grf_reg_count << 1)) >> 6;
  79
  80    clip->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754;
  81    clip->thread1.single_program_flow = 1;
  82
  83    clip->thread3.urb_entry_read_length = brw->clip.prog_data->urb_read_length;
  84    clip->thread3.const_urb_entry_read_length =
  85       brw->clip.prog_data->curb_read_length;
  86
  87    /* BRW_NEW_CURBE_OFFSETS */
  88    clip->thread3.const_urb_entry_read_offset = brw->curbe.clip_start * 2;
  89    clip->thread3.dispatch_grf_start_reg = 1;
  90    clip->thread3.urb_entry_read_offset = 0;
  91
  92    /* BRW_NEW_URB_FENCE */
  93    clip->thread4.nr_urb_entries = brw->urb.nr_clip_entries;
  94    clip->thread4.urb_entry_allocation_size = brw->urb.vsize - 1;
  95    /* If we have enough clip URB entries to run two threads, do so.
  96     */
  97    if (brw->urb.nr_clip_entries >= 10) {
  98       /* Half of the URB entries go to each thread, and it has to be an
  99        * even number.
 100        */
 101       assert(brw->urb.nr_clip_entries % 2 == 0);
 102
 103       /* Although up to 16 concurrent Clip threads are allowed on Ironlake,
 104        * only 2 threads can output VUEs at a time.
 105        */
 106       if (brw->gen == 5)
 107          clip->thread4.max_threads = 16 - 1;
 108       else
 109          clip->thread4.max_threads = 2 - 1;
 110    } else {
 111       assert(brw->urb.nr_clip_entries >= 5);
 112       clip->thread4.max_threads = 1 - 1;
 113    }
 114
 115    if (unlikely(INTEL_DEBUG & DEBUG_STATS))
 116       clip->thread4.stats_enable = 1;
 117
 118    /* _NEW_TRANSFORM */
 119    if (brw->gen == 5 || brw->is_g4x)
 120       clip->clip5.userclip_enable_flags = ctx->Transform.ClipPlanesEnabled;
 121    else
 122       /* Up to 6 actual clip flags, plus the 7th for negative RHW workaround. */
 123       clip->clip5.userclip_enable_flags = (ctx->Transform.ClipPlanesEnabled & 0x3f) | 0x40;
 124
 125    clip->clip5.userclip_must_clip = 1;
 126
 127    /* enable guardband clipping if we can */
 128    if (ctx->Viewport.X == 0 &&
 129        ctx->Viewport.Y == 0 &&
 130        ctx->Viewport.Width == fb->Width &&
 131        ctx->Viewport.Height == fb->Height)
 132    {
 133       clip->clip5.guard_band_enable = 1;
 134       clip->clip6.clipper_viewport_state_ptr =
 135          (brw->batch.bo->offset + brw->clip.vp_offset) >> 5;
 136
 137       /* emit clip viewport relocation */
 138       drm_intel_bo_emit_reloc(brw->batch.bo,
 139                               (brw->clip.state_offset +
 140                                offsetof(struct brw_clip_unit_state, clip6)),
 141                               brw->batch.bo, brw->clip.vp_offset,
 142                               I915_GEM_DOMAIN_INSTRUCTION, 0);
 143    }
 144
 145    /* _NEW_TRANSFORM */
 146    if (!ctx->Transform.DepthClamp)
 147       clip->clip5.viewport_z_clip_enable = 1;
 148    clip->clip5.viewport_xy_clip_enable = 1;
 149    clip->clip5.vertex_position_space = BRW_CLIP_NDCSPACE;
 150    clip->clip5.api_mode = BRW_CLIP_API_OGL;
 151    clip->clip5.clip_mode = brw->clip.prog_data->clip_mode;
 152
 153    if (brw->is_g4x)
 154       clip->clip5.negative_w_clip_test = 1;
 155
 156    clip->viewport_xmin = -1;
 157    clip->viewport_xmax = 1;
 158    clip->viewport_ymin = -1;
 159    clip->viewport_ymax = 1;
 160
 161    brw->state.dirty.cache |= CACHE_NEW_CLIP_UNIT;
 162 }
 163
 164 const struct brw_tracked_state brw_clip_unit = {
 165    .dirty = {
 166       .mesa  = _NEW_TRANSFORM | _NEW_BUFFERS | _NEW_VIEWPORT,
 167       .brw   = (BRW_NEW_BATCH |
 168                 BRW_NEW_PROGRAM_CACHE |
 169                 BRW_NEW_CURBE_OFFSETS |
 170                 BRW_NEW_URB_FENCE),
 171       .cache = CACHE_NEW_CLIP_PROG
 172    },
 173    .emit = brw_upload_clip_unit,
 174 };