src/mesa/drivers/dri/i965/brw_compute.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <sys/errno.h>
  25
  26 #include "main/condrender.h"
  27 #include "main/mtypes.h"
  28 #include "main/state.h"
  29 #include "brw_context.h"
  30 #include "brw_draw.h"
  31 #include "brw_state.h"
  32 #include "intel_batchbuffer.h"
  33 #include "intel_buffer_objects.h"
  34 #include "brw_defines.h"
  35
  36
  37 static void
  38 prepare_indirect_gpgpu_walker(struct brw_context *brw)
  39 {
  40    GLintptr indirect_offset = brw->compute.num_work_groups_offset;
  41    struct brw_bo *bo = brw->compute.num_work_groups_bo;
  42
  43    brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMX, bo, indirect_offset + 0);
  44    brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMY, bo, indirect_offset + 4);
  45    brw_load_register_mem(brw, GEN7_GPGPU_DISPATCHDIMZ, bo, indirect_offset + 8);
  46
  47    if (brw->gen > 7)
  48       return;
  49
  50    /* Clear upper 32-bits of SRC0 and all 64-bits of SRC1 */
  51    BEGIN_BATCH(7);
  52    OUT_BATCH(MI_LOAD_REGISTER_IMM | (7 - 2));
  53    OUT_BATCH(MI_PREDICATE_SRC0 + 4);
  54    OUT_BATCH(0u);
  55    OUT_BATCH(MI_PREDICATE_SRC1 + 0);
  56    OUT_BATCH(0u);
  57    OUT_BATCH(MI_PREDICATE_SRC1 + 4);
  58    OUT_BATCH(0u);
  59    ADVANCE_BATCH();
  60
  61    /* Load compute_dispatch_indirect_x_size into SRC0 */
  62    brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 0);
  63
  64    /* predicate = (compute_dispatch_indirect_x_size == 0); */
  65    BEGIN_BATCH(1);
  66    OUT_BATCH(GEN7_MI_PREDICATE |
  67              MI_PREDICATE_LOADOP_LOAD |
  68              MI_PREDICATE_COMBINEOP_SET |
  69              MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
  70    ADVANCE_BATCH();
  71
  72    /* Load compute_dispatch_indirect_y_size into SRC0 */
  73    brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 4);
  74
  75    /* predicate |= (compute_dispatch_indirect_y_size == 0); */
  76    BEGIN_BATCH(1);
  77    OUT_BATCH(GEN7_MI_PREDICATE |
  78              MI_PREDICATE_LOADOP_LOAD |
  79              MI_PREDICATE_COMBINEOP_OR |
  80              MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
  81    ADVANCE_BATCH();
  82
  83    /* Load compute_dispatch_indirect_z_size into SRC0 */
  84    brw_load_register_mem(brw, MI_PREDICATE_SRC0, bo, indirect_offset + 8);
  85
  86    /* predicate |= (compute_dispatch_indirect_z_size == 0); */
  87    BEGIN_BATCH(1);
  88    OUT_BATCH(GEN7_MI_PREDICATE |
  89              MI_PREDICATE_LOADOP_LOAD |
  90              MI_PREDICATE_COMBINEOP_OR |
  91              MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
  92    ADVANCE_BATCH();
  93
  94    /* predicate = !predicate; */
  95    BEGIN_BATCH(1);
  96    OUT_BATCH(GEN7_MI_PREDICATE |
  97              MI_PREDICATE_LOADOP_LOADINV |
  98              MI_PREDICATE_COMBINEOP_OR |
  99              MI_PREDICATE_COMPAREOP_FALSE);
 100    ADVANCE_BATCH();
 101 }
 102
 103 static void
 104 brw_emit_gpgpu_walker(struct brw_context *brw)
 105 {
 106    const struct brw_cs_prog_data *prog_data =
 107       brw_cs_prog_data(brw->cs.base.prog_data);
 108
 109    const GLuint *num_groups = brw->compute.num_work_groups;
 110    uint32_t indirect_flag;
 111
 112    if (brw->compute.num_work_groups_bo == NULL) {
 113       indirect_flag = 0;
 114    } else {
 115       indirect_flag =
 116          GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE |
 117          (brw->gen == 7 ? GEN7_GPGPU_PREDICATE_ENABLE : 0);
 118       prepare_indirect_gpgpu_walker(brw);
 119    }
 120
 121    const unsigned simd_size = prog_data->simd_size;
 122    unsigned group_size = prog_data->local_size[0] *
 123       prog_data->local_size[1] * prog_data->local_size[2];
 124    unsigned thread_width_max =
 125       (group_size + simd_size - 1) / simd_size;
 126
 127    uint32_t right_mask = 0xffffffffu >> (32 - simd_size);
 128    const unsigned right_non_aligned = group_size & (simd_size - 1);
 129    if (right_non_aligned != 0)
 130       right_mask >>= (simd_size - right_non_aligned);
 131
 132    uint32_t dwords = brw->gen < 8 ? 11 : 15;
 133    BEGIN_BATCH(dwords);
 134    OUT_BATCH(GPGPU_WALKER << 16 | (dwords - 2) | indirect_flag);
 135    OUT_BATCH(0);
 136    if (brw->gen >= 8) {
 137       OUT_BATCH(0);                     /* Indirect Data Length */
 138       OUT_BATCH(0);                     /* Indirect Data Start Address */
 139    }
 140    assert(thread_width_max <= brw->screen->devinfo.max_cs_threads);
 141    OUT_BATCH(SET_FIELD(simd_size / 16, GPGPU_WALKER_SIMD_SIZE) |
 142              SET_FIELD(thread_width_max - 1, GPGPU_WALKER_THREAD_WIDTH_MAX));
 143    OUT_BATCH(0);                        /* Thread Group ID Starting X */
 144    if (brw->gen >= 8)
 145       OUT_BATCH(0);                     /* MBZ */
 146    OUT_BATCH(num_groups[0]);            /* Thread Group ID X Dimension */
 147    OUT_BATCH(0);                        /* Thread Group ID Starting Y */
 148    if (brw->gen >= 8)
 149       OUT_BATCH(0);                     /* MBZ */
 150    OUT_BATCH(num_groups[1]);            /* Thread Group ID Y Dimension */
 151    OUT_BATCH(0);                        /* Thread Group ID Starting/Resume Z */
 152    OUT_BATCH(num_groups[2]);            /* Thread Group ID Z Dimension */
 153    OUT_BATCH(right_mask);               /* Right Execution Mask */
 154    OUT_BATCH(0xffffffff);               /* Bottom Execution Mask */
 155    ADVANCE_BATCH();
 156
 157    BEGIN_BATCH(2);
 158    OUT_BATCH(MEDIA_STATE_FLUSH << 16 | (2 - 2));
 159    OUT_BATCH(0);
 160    ADVANCE_BATCH();
 161 }
 162
 163
 164 static void
 165 brw_dispatch_compute_common(struct gl_context *ctx)
 166 {
 167    struct brw_context *brw = brw_context(ctx);
 168    int estimated_buffer_space_needed;
 169    bool fail_next = false;
 170
 171    if (!_mesa_check_conditional_render(ctx))
 172       return;
 173
 174    if (ctx->NewState)
 175       _mesa_update_state(ctx);
 176
 177    brw_validate_textures(brw);
 178
 179    brw_predraw_resolve_inputs(brw);
 180
 181    const int sampler_state_size = 16; /* 16 bytes */
 182    estimated_buffer_space_needed = 512; /* batchbuffer commands */
 183    estimated_buffer_space_needed += (BRW_MAX_TEX_UNIT *
 184                                      (sampler_state_size +
 185                                       sizeof(struct gen5_sampler_default_color)));
 186    estimated_buffer_space_needed += 1024; /* push constants */
 187    estimated_buffer_space_needed += 512; /* misc. pad */
 188
 189    /* Flush the batch if it's approaching full, so that we don't wrap while
 190     * we've got validated state that needs to be in the same batch as the
 191     * primitives.
 192     */
 193    intel_batchbuffer_require_space(brw, estimated_buffer_space_needed,
 194                                    RENDER_RING);
 195    intel_batchbuffer_save_state(brw);
 196
 197  retry:
 198    brw->no_batch_wrap = true;
 199    brw_upload_compute_state(brw);
 200
 201    brw_emit_gpgpu_walker(brw);
 202
 203    brw->no_batch_wrap = false;
 204
 205    if (!brw_batch_has_aperture_space(brw, 0)) {
 206       if (!fail_next) {
 207          intel_batchbuffer_reset_to_saved(brw);
 208          intel_batchbuffer_flush(brw);
 209          fail_next = true;
 210          goto retry;
 211       } else {
 212          int ret = intel_batchbuffer_flush(brw);
 213          WARN_ONCE(ret == -ENOSPC,
 214                    "i965: Single compute shader dispatch "
 215                    "exceeded available aperture space\n");
 216       }
 217    }
 218
 219    /* Now that we know we haven't run out of aperture space, we can safely
 220     * reset the dirty bits.
 221     */
 222    brw_compute_state_finished(brw);
 223
 224    if (brw->always_flush_batch)
 225       intel_batchbuffer_flush(brw);
 226
 227    brw_program_cache_check_size(brw);
 228
 229    /* Note: since compute shaders can't write to framebuffers, there's no need
 230     * to call brw_postdraw_set_buffers_need_resolve().
 231     */
 232 }
 233
 234 static void
 235 brw_dispatch_compute(struct gl_context *ctx, const GLuint *num_groups) {
 236    struct brw_context *brw = brw_context(ctx);
 237
 238    brw->compute.num_work_groups_bo = NULL;
 239    brw->compute.num_work_groups = num_groups;
 240    ctx->NewDriverState |= BRW_NEW_CS_WORK_GROUPS;
 241
 242    brw_dispatch_compute_common(ctx);
 243 }
 244
 245 static void
 246 brw_dispatch_compute_indirect(struct gl_context *ctx, GLintptr indirect)
 247 {
 248    struct brw_context *brw = brw_context(ctx);
 249    static const GLuint indirect_group_counts[3] = { 0, 0, 0 };
 250    struct gl_buffer_object *indirect_buffer = ctx->DispatchIndirectBuffer;
 251    struct brw_bo *bo =
 252       intel_bufferobj_buffer(brw,
 253                              intel_buffer_object(indirect_buffer),
 254                              indirect, 3 * sizeof(GLuint), false);
 255
 256    brw->compute.num_work_groups_bo = bo;
 257    brw->compute.num_work_groups_offset = indirect;
 258    brw->compute.num_work_groups = indirect_group_counts;
 259    ctx->NewDriverState |= BRW_NEW_CS_WORK_GROUPS;
 260
 261    brw_dispatch_compute_common(ctx);
 262 }
 263
 264 void
 265 brw_init_compute_functions(struct dd_function_table *functions)
 266 {
 267    functions->DispatchCompute = brw_dispatch_compute;
 268    functions->DispatchComputeIndirect = brw_dispatch_compute_indirect;
 269 }