2 Copyright 2003 VMware, Inc.
3 Copyright (C) Intel Corp. 2006. All Rights Reserved.
4 Intel funded Tungsten Graphics to
5 develop this 3D driver.
7 Permission is hereby granted, free of charge, to any person obtaining
8 a copy of this software and associated documentation files (the
9 "Software"), to deal in the Software without restriction, including
10 without limitation the rights to use, copy, modify, merge, publish,
11 distribute, sublicense, and/or sell copies of the Software, and to
12 permit persons to whom the Software is furnished to do so, subject to
13 the following conditions:
15 The above copyright notice and this permission notice (including the
16 next paragraph) shall be included in all copies or substantial
17 portions of the Software.
19 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 **********************************************************************/
30 * Keith Whitwell <keithw@vmware.com>
34 #include "compiler/nir/nir.h"
35 #include "main/api_exec.h"
36 #include "main/context.h"
37 #include "main/fbobject.h"
38 #include "main/extensions.h"
39 #include "main/imports.h"
40 #include "main/macros.h"
41 #include "main/points.h"
42 #include "main/version.h"
43 #include "main/vtxfmt.h"
44 #include "main/texobj.h"
45 #include "main/framebuffer.h"
46 #include "main/stencil.h"
47 #include "main/state.h"
51 #include "drivers/common/driverfuncs.h"
52 #include "drivers/common/meta.h"
55 #include "brw_context.h"
56 #include "brw_defines.h"
57 #include "brw_blorp.h"
59 #include "brw_state.h"
61 #include "intel_batchbuffer.h"
62 #include "intel_buffer_objects.h"
63 #include "intel_buffers.h"
64 #include "intel_fbo.h"
65 #include "intel_mipmap_tree.h"
66 #include "intel_pixel.h"
67 #include "intel_image.h"
68 #include "intel_tex.h"
69 #include "intel_tex_obj.h"
71 #include "swrast_setup/swrast_setup.h"
73 #include "tnl/t_pipeline.h"
74 #include "util/ralloc.h"
75 #include "util/debug.h"
76 #include "util/disk_cache.h"
79 #include "common/gen_defines.h"
81 #include "compiler/spirv/nir_spirv.h"
82 /***************************************
83 * Mesa's Driver Functions
84 ***************************************/
86 const char *const brw_vendor_string
= "Intel Open Source Technology Center";
89 get_bsw_model(const struct intel_screen
*screen
)
91 switch (screen
->eu_total
) {
102 brw_get_renderer_string(const struct intel_screen
*screen
)
105 static char buffer
[128];
108 switch (screen
->deviceID
) {
110 #define CHIPSET(id, symbol, str) case id: chipset = str; break;
111 #include "pci_ids/i965_pci_ids.h"
113 chipset
= "Unknown Intel Chipset";
117 /* Braswell branding is funny, so we have to fix it up here */
118 if (screen
->deviceID
== 0x22B1) {
119 bsw
= strdup(chipset
);
120 char *needle
= strstr(bsw
, "XXX");
122 memcpy(needle
, get_bsw_model(screen
), 3);
127 (void) driGetRendererString(buffer
, chipset
, 0);
132 static const GLubyte
*
133 intel_get_string(struct gl_context
* ctx
, GLenum name
)
135 const struct brw_context
*const brw
= brw_context(ctx
);
139 return (GLubyte
*) brw_vendor_string
;
143 (GLubyte
*) brw_get_renderer_string(brw
->screen
);
151 intel_viewport(struct gl_context
*ctx
)
153 struct brw_context
*brw
= brw_context(ctx
);
154 __DRIcontext
*driContext
= brw
->driContext
;
156 if (_mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
157 if (driContext
->driDrawablePriv
)
158 dri2InvalidateDrawable(driContext
->driDrawablePriv
);
159 if (driContext
->driReadablePriv
)
160 dri2InvalidateDrawable(driContext
->driReadablePriv
);
165 intel_update_framebuffer(struct gl_context
*ctx
,
166 struct gl_framebuffer
*fb
)
168 struct brw_context
*brw
= brw_context(ctx
);
170 /* Quantize the derived default number of samples
172 fb
->DefaultGeometry
._NumSamples
=
173 intel_quantize_num_samples(brw
->screen
,
174 fb
->DefaultGeometry
.NumSamples
);
178 intel_update_state(struct gl_context
* ctx
)
180 GLuint new_state
= ctx
->NewState
;
181 struct brw_context
*brw
= brw_context(ctx
);
183 if (ctx
->swrast_context
)
184 _swrast_InvalidateState(ctx
, new_state
);
186 brw
->NewGLState
|= new_state
;
188 if (new_state
& (_NEW_SCISSOR
| _NEW_BUFFERS
| _NEW_VIEWPORT
))
189 _mesa_update_draw_buffer_bounds(ctx
, ctx
->DrawBuffer
);
191 if (new_state
& (_NEW_STENCIL
| _NEW_BUFFERS
)) {
192 brw
->stencil_enabled
= _mesa_stencil_is_enabled(ctx
);
193 brw
->stencil_two_sided
= _mesa_stencil_is_two_sided(ctx
);
194 brw
->stencil_write_enabled
=
195 _mesa_stencil_is_write_enabled(ctx
, brw
->stencil_two_sided
);
198 if (new_state
& _NEW_POLYGON
)
199 brw
->polygon_front_bit
= _mesa_polygon_get_front_bit(ctx
);
201 if (new_state
& _NEW_BUFFERS
) {
202 intel_update_framebuffer(ctx
, ctx
->DrawBuffer
);
203 if (ctx
->DrawBuffer
!= ctx
->ReadBuffer
)
204 intel_update_framebuffer(ctx
, ctx
->ReadBuffer
);
208 #define flushFront(screen) ((screen)->image.loader ? (screen)->image.loader->flushFrontBuffer : (screen)->dri2.loader->flushFrontBuffer)
211 intel_flush_front(struct gl_context
*ctx
)
213 struct brw_context
*brw
= brw_context(ctx
);
214 __DRIcontext
*driContext
= brw
->driContext
;
215 __DRIdrawable
*driDrawable
= driContext
->driDrawablePriv
;
216 __DRIscreen
*const dri_screen
= brw
->screen
->driScrnPriv
;
218 if (brw
->front_buffer_dirty
&& _mesa_is_winsys_fbo(ctx
->DrawBuffer
)) {
219 if (flushFront(dri_screen
) && driDrawable
&&
220 driDrawable
->loaderPrivate
) {
222 /* Resolve before flushing FAKE_FRONT_LEFT to FRONT_LEFT.
224 * This potentially resolves both front and back buffer. It
225 * is unnecessary to resolve the back, but harms nothing except
226 * performance. And no one cares about front-buffer render
229 intel_resolve_for_dri2_flush(brw
, driDrawable
);
230 intel_batchbuffer_flush(brw
);
232 flushFront(dri_screen
)(driDrawable
, driDrawable
->loaderPrivate
);
234 /* We set the dirty bit in intel_prepare_render() if we're
235 * front buffer rendering once we get there.
237 brw
->front_buffer_dirty
= false;
243 intel_glFlush(struct gl_context
*ctx
)
245 struct brw_context
*brw
= brw_context(ctx
);
247 intel_batchbuffer_flush(brw
);
248 intel_flush_front(ctx
);
250 brw
->need_flush_throttle
= true;
254 intel_finish(struct gl_context
* ctx
)
256 struct brw_context
*brw
= brw_context(ctx
);
260 if (brw
->batch
.last_bo
)
261 brw_bo_wait_rendering(brw
->batch
.last_bo
);
265 brw_init_driver_functions(struct brw_context
*brw
,
266 struct dd_function_table
*functions
)
268 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
270 _mesa_init_driver_functions(functions
);
272 /* GLX uses DRI2 invalidate events to handle window resizing.
273 * Unfortunately, EGL does not - libEGL is written in XCB (not Xlib),
274 * which doesn't provide a mechanism for snooping the event queues.
276 * So EGL still relies on viewport hacks to handle window resizing.
277 * This should go away with DRI3000.
279 if (!brw
->driContext
->driScreenPriv
->dri2
.useInvalidate
)
280 functions
->Viewport
= intel_viewport
;
282 functions
->Flush
= intel_glFlush
;
283 functions
->Finish
= intel_finish
;
284 functions
->GetString
= intel_get_string
;
285 functions
->UpdateState
= intel_update_state
;
287 brw_init_draw_functions(functions
);
288 intelInitTextureFuncs(functions
);
289 intelInitTextureImageFuncs(functions
);
290 intelInitTextureCopyImageFuncs(functions
);
291 intelInitCopyImageFuncs(functions
);
292 intelInitClearFuncs(functions
);
293 intelInitBufferFuncs(functions
);
294 intelInitPixelFuncs(functions
);
295 intelInitBufferObjectFuncs(functions
);
296 brw_init_syncobj_functions(functions
);
297 brw_init_object_purgeable_functions(functions
);
299 brwInitFragProgFuncs( functions
);
300 brw_init_common_queryobj_functions(functions
);
301 if (devinfo
->gen
>= 8 || devinfo
->is_haswell
)
302 hsw_init_queryobj_functions(functions
);
303 else if (devinfo
->gen
>= 6)
304 gen6_init_queryobj_functions(functions
);
306 gen4_init_queryobj_functions(functions
);
307 brw_init_compute_functions(functions
);
308 brw_init_conditional_render_functions(functions
);
310 functions
->GenerateMipmap
= brw_generate_mipmap
;
312 functions
->QueryInternalFormat
= brw_query_internal_format
;
314 functions
->NewTransformFeedback
= brw_new_transform_feedback
;
315 functions
->DeleteTransformFeedback
= brw_delete_transform_feedback
;
316 if (can_do_mi_math_and_lrr(brw
->screen
)) {
317 functions
->BeginTransformFeedback
= hsw_begin_transform_feedback
;
318 functions
->EndTransformFeedback
= hsw_end_transform_feedback
;
319 functions
->PauseTransformFeedback
= hsw_pause_transform_feedback
;
320 functions
->ResumeTransformFeedback
= hsw_resume_transform_feedback
;
321 } else if (devinfo
->gen
>= 7) {
322 functions
->BeginTransformFeedback
= gen7_begin_transform_feedback
;
323 functions
->EndTransformFeedback
= gen7_end_transform_feedback
;
324 functions
->PauseTransformFeedback
= gen7_pause_transform_feedback
;
325 functions
->ResumeTransformFeedback
= gen7_resume_transform_feedback
;
326 functions
->GetTransformFeedbackVertexCount
=
327 brw_get_transform_feedback_vertex_count
;
329 functions
->BeginTransformFeedback
= brw_begin_transform_feedback
;
330 functions
->EndTransformFeedback
= brw_end_transform_feedback
;
331 functions
->PauseTransformFeedback
= brw_pause_transform_feedback
;
332 functions
->ResumeTransformFeedback
= brw_resume_transform_feedback
;
333 functions
->GetTransformFeedbackVertexCount
=
334 brw_get_transform_feedback_vertex_count
;
337 if (devinfo
->gen
>= 6)
338 functions
->GetSamplePosition
= gen6_get_sample_position
;
340 /* GL_ARB_get_program_binary */
341 brw_program_binary_init(brw
->screen
->deviceID
);
342 functions
->GetProgramBinaryDriverSHA1
= brw_get_program_binary_driver_sha1
;
343 functions
->ProgramBinarySerializeDriverBlob
= brw_program_serialize_nir
;
344 functions
->ProgramBinaryDeserializeDriverBlob
=
345 brw_deserialize_program_binary
;
349 brw_initialize_spirv_supported_capabilities(struct brw_context
*brw
)
351 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
352 struct gl_context
*ctx
= &brw
->ctx
;
354 /* The following SPIR-V capabilities are only supported on gen7+. In theory
355 * you should enable the extension only on gen7+, but just in case let's
358 assert(devinfo
->gen
>= 7);
360 ctx
->Const
.SpirVCapabilities
.float64
= devinfo
->gen
>= 8;
361 ctx
->Const
.SpirVCapabilities
.int64
= devinfo
->gen
>= 8;
362 ctx
->Const
.SpirVCapabilities
.tessellation
= true;
363 ctx
->Const
.SpirVCapabilities
.draw_parameters
= true;
364 ctx
->Const
.SpirVCapabilities
.image_write_without_format
= true;
365 ctx
->Const
.SpirVCapabilities
.variable_pointers
= true;
369 brw_initialize_context_constants(struct brw_context
*brw
)
371 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
372 struct gl_context
*ctx
= &brw
->ctx
;
373 const struct brw_compiler
*compiler
= brw
->screen
->compiler
;
375 const bool stage_exists
[MESA_SHADER_STAGES
] = {
376 [MESA_SHADER_VERTEX
] = true,
377 [MESA_SHADER_TESS_CTRL
] = devinfo
->gen
>= 7,
378 [MESA_SHADER_TESS_EVAL
] = devinfo
->gen
>= 7,
379 [MESA_SHADER_GEOMETRY
] = devinfo
->gen
>= 6,
380 [MESA_SHADER_FRAGMENT
] = true,
381 [MESA_SHADER_COMPUTE
] =
382 (_mesa_is_desktop_gl(ctx
) &&
383 ctx
->Const
.MaxComputeWorkGroupSize
[0] >= 1024) ||
384 (ctx
->API
== API_OPENGLES2
&&
385 ctx
->Const
.MaxComputeWorkGroupSize
[0] >= 128),
388 unsigned num_stages
= 0;
389 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
394 unsigned max_samplers
=
395 devinfo
->gen
>= 8 || devinfo
->is_haswell
? BRW_MAX_TEX_UNIT
: 16;
397 ctx
->Const
.MaxDualSourceDrawBuffers
= 1;
398 ctx
->Const
.MaxDrawBuffers
= BRW_MAX_DRAW_BUFFERS
;
399 ctx
->Const
.MaxCombinedShaderOutputResources
=
400 MAX_IMAGE_UNITS
+ BRW_MAX_DRAW_BUFFERS
;
402 /* The timestamp register we can read for glGetTimestamp() is
403 * sometimes only 32 bits, before scaling to nanoseconds (depending
406 * Once scaled to nanoseconds the timestamp would roll over at a
407 * non-power-of-two, so an application couldn't use
408 * GL_QUERY_COUNTER_BITS to handle rollover correctly. Instead, we
409 * report 36 bits and truncate at that (rolling over 5 times as
410 * often as the HW counter), and when the 32-bit counter rolls
411 * over, it happens to also be at a rollover in the reported value
412 * from near (1<<36) to 0.
414 * The low 32 bits rolls over in ~343 seconds. Our 36-bit result
415 * rolls over every ~69 seconds.
417 ctx
->Const
.QueryCounterBits
.Timestamp
= 36;
419 ctx
->Const
.MaxTextureCoordUnits
= 8; /* Mesa limit */
420 ctx
->Const
.MaxImageUnits
= MAX_IMAGE_UNITS
;
421 if (devinfo
->gen
>= 7) {
422 ctx
->Const
.MaxRenderbufferSize
= 16384;
423 ctx
->Const
.MaxTextureLevels
= MIN2(15 /* 16384 */, MAX_TEXTURE_LEVELS
);
424 ctx
->Const
.MaxCubeTextureLevels
= 15; /* 16384 */
426 ctx
->Const
.MaxRenderbufferSize
= 8192;
427 ctx
->Const
.MaxTextureLevels
= MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS
);
428 ctx
->Const
.MaxCubeTextureLevels
= 14; /* 8192 */
430 ctx
->Const
.Max3DTextureLevels
= 12; /* 2048 */
431 ctx
->Const
.MaxArrayTextureLayers
= devinfo
->gen
>= 7 ? 2048 : 512;
432 ctx
->Const
.MaxTextureMbytes
= 1536;
433 ctx
->Const
.MaxTextureRectSize
= devinfo
->gen
>= 7 ? 16384 : 8192;
434 ctx
->Const
.MaxTextureMaxAnisotropy
= 16.0;
435 ctx
->Const
.MaxTextureLodBias
= 15.0;
436 ctx
->Const
.StripTextureBorder
= true;
437 if (devinfo
->gen
>= 7) {
438 ctx
->Const
.MaxProgramTextureGatherComponents
= 4;
439 ctx
->Const
.MinProgramTextureGatherOffset
= -32;
440 ctx
->Const
.MaxProgramTextureGatherOffset
= 31;
441 } else if (devinfo
->gen
== 6) {
442 ctx
->Const
.MaxProgramTextureGatherComponents
= 1;
443 ctx
->Const
.MinProgramTextureGatherOffset
= -8;
444 ctx
->Const
.MaxProgramTextureGatherOffset
= 7;
447 ctx
->Const
.MaxUniformBlockSize
= 65536;
449 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
450 struct gl_program_constants
*prog
= &ctx
->Const
.Program
[i
];
452 if (!stage_exists
[i
])
455 prog
->MaxTextureImageUnits
= max_samplers
;
457 prog
->MaxUniformBlocks
= BRW_MAX_UBO
;
458 prog
->MaxCombinedUniformComponents
=
459 prog
->MaxUniformComponents
+
460 ctx
->Const
.MaxUniformBlockSize
/ 4 * prog
->MaxUniformBlocks
;
462 prog
->MaxAtomicCounters
= MAX_ATOMIC_COUNTERS
;
463 prog
->MaxAtomicBuffers
= BRW_MAX_ABO
;
464 prog
->MaxImageUniforms
= compiler
->scalar_stage
[i
] ? BRW_MAX_IMAGES
: 0;
465 prog
->MaxShaderStorageBlocks
= BRW_MAX_SSBO
;
468 ctx
->Const
.MaxTextureUnits
=
469 MIN2(ctx
->Const
.MaxTextureCoordUnits
,
470 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxTextureImageUnits
);
472 ctx
->Const
.MaxUniformBufferBindings
= num_stages
* BRW_MAX_UBO
;
473 ctx
->Const
.MaxCombinedUniformBlocks
= num_stages
* BRW_MAX_UBO
;
474 ctx
->Const
.MaxCombinedAtomicBuffers
= num_stages
* BRW_MAX_ABO
;
475 ctx
->Const
.MaxCombinedShaderStorageBlocks
= num_stages
* BRW_MAX_SSBO
;
476 ctx
->Const
.MaxShaderStorageBufferBindings
= num_stages
* BRW_MAX_SSBO
;
477 ctx
->Const
.MaxCombinedTextureImageUnits
= num_stages
* max_samplers
;
478 ctx
->Const
.MaxCombinedImageUniforms
= num_stages
* BRW_MAX_IMAGES
;
481 /* Hardware only supports a limited number of transform feedback buffers.
482 * So we need to override the Mesa default (which is based only on software
485 ctx
->Const
.MaxTransformFeedbackBuffers
= BRW_MAX_SOL_BUFFERS
;
487 /* On Gen6, in the worst case, we use up one binding table entry per
488 * transform feedback component (see comments above the definition of
489 * BRW_MAX_SOL_BINDINGS, in brw_context.h), so we need to advertise a value
490 * for MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS equal to
491 * BRW_MAX_SOL_BINDINGS.
493 * In "separate components" mode, we need to divide this value by
494 * BRW_MAX_SOL_BUFFERS, so that the total number of binding table entries
495 * used up by all buffers will not exceed BRW_MAX_SOL_BINDINGS.
497 ctx
->Const
.MaxTransformFeedbackInterleavedComponents
= BRW_MAX_SOL_BINDINGS
;
498 ctx
->Const
.MaxTransformFeedbackSeparateComponents
=
499 BRW_MAX_SOL_BINDINGS
/ BRW_MAX_SOL_BUFFERS
;
501 ctx
->Const
.AlwaysUseGetTransformFeedbackVertexCount
=
502 !can_do_mi_math_and_lrr(brw
->screen
);
505 const int *msaa_modes
= intel_supported_msaa_modes(brw
->screen
);
506 const int clamp_max_samples
=
507 driQueryOptioni(&brw
->optionCache
, "clamp_max_samples");
509 if (clamp_max_samples
< 0) {
510 max_samples
= msaa_modes
[0];
512 /* Select the largest supported MSAA mode that does not exceed
516 for (int i
= 0; msaa_modes
[i
] != 0; ++i
) {
517 if (msaa_modes
[i
] <= clamp_max_samples
) {
518 max_samples
= msaa_modes
[i
];
524 ctx
->Const
.MaxSamples
= max_samples
;
525 ctx
->Const
.MaxColorTextureSamples
= max_samples
;
526 ctx
->Const
.MaxDepthTextureSamples
= max_samples
;
527 ctx
->Const
.MaxIntegerSamples
= max_samples
;
528 ctx
->Const
.MaxImageSamples
= 0;
530 /* gen6_set_sample_maps() sets SampleMap{2,4,8}x variables which are used
531 * to map indices of rectangular grid to sample numbers within a pixel.
532 * These variables are used by GL_EXT_framebuffer_multisample_blit_scaled
533 * extension implementation. For more details see the comment above
534 * gen6_set_sample_maps() definition.
536 gen6_set_sample_maps(ctx
);
538 ctx
->Const
.MinLineWidth
= 1.0;
539 ctx
->Const
.MinLineWidthAA
= 1.0;
540 if (devinfo
->gen
>= 6) {
541 ctx
->Const
.MaxLineWidth
= 7.375;
542 ctx
->Const
.MaxLineWidthAA
= 7.375;
543 ctx
->Const
.LineWidthGranularity
= 0.125;
545 ctx
->Const
.MaxLineWidth
= 7.0;
546 ctx
->Const
.MaxLineWidthAA
= 7.0;
547 ctx
->Const
.LineWidthGranularity
= 0.5;
550 /* For non-antialiased lines, we have to round the line width to the
551 * nearest whole number. Make sure that we don't advertise a line
552 * width that, when rounded, will be beyond the actual hardware
555 assert(roundf(ctx
->Const
.MaxLineWidth
) <= ctx
->Const
.MaxLineWidth
);
557 ctx
->Const
.MinPointSize
= 1.0;
558 ctx
->Const
.MinPointSizeAA
= 1.0;
559 ctx
->Const
.MaxPointSize
= 255.0;
560 ctx
->Const
.MaxPointSizeAA
= 255.0;
561 ctx
->Const
.PointSizeGranularity
= 1.0;
563 if (devinfo
->gen
>= 5 || devinfo
->is_g4x
)
564 ctx
->Const
.MaxClipPlanes
= 8;
566 ctx
->Const
.GLSLTessLevelsAsInputs
= true;
567 ctx
->Const
.PrimitiveRestartForPatches
= true;
569 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeInstructions
= 16 * 1024;
570 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxAluInstructions
= 0;
571 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxTexInstructions
= 0;
572 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxTexIndirections
= 0;
573 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeAluInstructions
= 0;
574 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeTexInstructions
= 0;
575 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeTexIndirections
= 0;
576 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeAttribs
= 16;
577 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeTemps
= 256;
578 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeAddressRegs
= 1;
579 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeParameters
= 1024;
580 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxEnvParams
=
581 MIN2(ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxNativeParameters
,
582 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxEnvParams
);
584 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeInstructions
= 1024;
585 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeAluInstructions
= 1024;
586 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeTexInstructions
= 1024;
587 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeTexIndirections
= 1024;
588 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeAttribs
= 12;
589 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeTemps
= 256;
590 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeAddressRegs
= 0;
591 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeParameters
= 1024;
592 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxEnvParams
=
593 MIN2(ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxNativeParameters
,
594 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxEnvParams
);
596 /* Fragment shaders use real, 32-bit twos-complement integers for all
599 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].LowInt
.RangeMin
= 31;
600 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].LowInt
.RangeMax
= 30;
601 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].LowInt
.Precision
= 0;
602 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].HighInt
= ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].LowInt
;
603 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MediumInt
= ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].LowInt
;
605 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].LowInt
.RangeMin
= 31;
606 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].LowInt
.RangeMax
= 30;
607 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].LowInt
.Precision
= 0;
608 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].HighInt
= ctx
->Const
.Program
[MESA_SHADER_VERTEX
].LowInt
;
609 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MediumInt
= ctx
->Const
.Program
[MESA_SHADER_VERTEX
].LowInt
;
611 /* Gen6 converts quads to polygon in beginning of 3D pipeline,
612 * but we're not sure how it's actually done for vertex order,
613 * that affect provoking vertex decision. Always use last vertex
614 * convention for quad primitive which works as expected for now.
616 if (devinfo
->gen
>= 6)
617 ctx
->Const
.QuadsFollowProvokingVertexConvention
= false;
619 ctx
->Const
.NativeIntegers
= true;
621 /* Regarding the CMP instruction, the Ivybridge PRM says:
623 * "For each enabled channel 0b or 1b is assigned to the appropriate flag
624 * bit and 0/all zeros or all ones (e.g, byte 0xFF, word 0xFFFF, DWord
625 * 0xFFFFFFFF) is assigned to dst."
627 * but PRMs for earlier generations say
629 * "In dword format, one GRF may store up to 8 results. When the register
630 * is used later as a vector of Booleans, as only LSB at each channel
631 * contains meaning [sic] data, software should make sure all higher bits
632 * are masked out (e.g. by 'and-ing' an [sic] 0x01 constant)."
634 * We select the representation of a true boolean uniform to be ~0, and fix
635 * the results of Gen <= 5 CMP instruction's with -(result & 1).
637 ctx
->Const
.UniformBooleanTrue
= ~0;
639 /* From the gen4 PRM, volume 4 page 127:
641 * "For SURFTYPE_BUFFER non-rendertarget surfaces, this field specifies
642 * the base address of the first element of the surface, computed in
643 * software by adding the surface base address to the byte offset of
644 * the element in the buffer."
646 * However, unaligned accesses are slower, so enforce buffer alignment.
648 * In order to push UBO data, 3DSTATE_CONSTANT_XS imposes an additional
649 * restriction: the start of the buffer needs to be 32B aligned.
651 ctx
->Const
.UniformBufferOffsetAlignment
= 32;
653 /* ShaderStorageBufferOffsetAlignment should be a cacheline (64 bytes) so
654 * that we can safely have the CPU and GPU writing the same SSBO on
655 * non-cachecoherent systems (our Atom CPUs). With UBOs, the GPU never
656 * writes, so there's no problem. For an SSBO, the GPU and the CPU can
657 * be updating disjoint regions of the buffer simultaneously and that will
658 * break if the regions overlap the same cacheline.
660 ctx
->Const
.ShaderStorageBufferOffsetAlignment
= 64;
661 ctx
->Const
.TextureBufferOffsetAlignment
= 16;
662 ctx
->Const
.MaxTextureBufferSize
= 128 * 1024 * 1024;
664 if (devinfo
->gen
>= 6) {
665 ctx
->Const
.MaxVarying
= 32;
666 ctx
->Const
.Program
[MESA_SHADER_VERTEX
].MaxOutputComponents
= 128;
667 ctx
->Const
.Program
[MESA_SHADER_GEOMETRY
].MaxInputComponents
=
668 compiler
->scalar_stage
[MESA_SHADER_GEOMETRY
] ? 128 : 64;
669 ctx
->Const
.Program
[MESA_SHADER_GEOMETRY
].MaxOutputComponents
= 128;
670 ctx
->Const
.Program
[MESA_SHADER_FRAGMENT
].MaxInputComponents
= 128;
671 ctx
->Const
.Program
[MESA_SHADER_TESS_CTRL
].MaxInputComponents
= 128;
672 ctx
->Const
.Program
[MESA_SHADER_TESS_CTRL
].MaxOutputComponents
= 128;
673 ctx
->Const
.Program
[MESA_SHADER_TESS_EVAL
].MaxInputComponents
= 128;
674 ctx
->Const
.Program
[MESA_SHADER_TESS_EVAL
].MaxOutputComponents
= 128;
677 /* We want the GLSL compiler to emit code that uses condition codes */
678 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
679 ctx
->Const
.ShaderCompilerOptions
[i
] =
680 brw
->screen
->compiler
->glsl_compiler_options
[i
];
683 if (devinfo
->gen
>= 7) {
684 ctx
->Const
.MaxViewportWidth
= 32768;
685 ctx
->Const
.MaxViewportHeight
= 32768;
688 /* ARB_viewport_array, OES_viewport_array */
689 if (devinfo
->gen
>= 6) {
690 ctx
->Const
.MaxViewports
= GEN6_NUM_VIEWPORTS
;
691 ctx
->Const
.ViewportSubpixelBits
= 0;
693 /* Cast to float before negating because MaxViewportWidth is unsigned.
695 ctx
->Const
.ViewportBounds
.Min
= -(float)ctx
->Const
.MaxViewportWidth
;
696 ctx
->Const
.ViewportBounds
.Max
= ctx
->Const
.MaxViewportWidth
;
699 /* ARB_gpu_shader5 */
700 if (devinfo
->gen
>= 7)
701 ctx
->Const
.MaxVertexStreams
= MIN2(4, MAX_VERTEX_STREAMS
);
703 /* ARB_framebuffer_no_attachments */
704 ctx
->Const
.MaxFramebufferWidth
= 16384;
705 ctx
->Const
.MaxFramebufferHeight
= 16384;
706 ctx
->Const
.MaxFramebufferLayers
= ctx
->Const
.MaxArrayTextureLayers
;
707 ctx
->Const
.MaxFramebufferSamples
= max_samples
;
709 /* OES_primitive_bounding_box */
710 ctx
->Const
.NoPrimitiveBoundingBoxOutput
= true;
712 /* TODO: We should be able to use STD430 packing by default on all hardware
713 * but some piglit tests [1] currently fail on SNB when this is enabled.
714 * The problem is the messages we're using for doing uniform pulls
715 * in the vec4 back-end on SNB is the OWORD block load instruction, which
716 * takes its offset in units of OWORDS (16 bytes). On IVB+, we use the
717 * sampler which doesn't have these restrictions.
719 * In the scalar back-end, we use the sampler for dynamic uniform loads and
720 * pull an entire cache line at a time for constant offset loads both of
721 * which support almost any alignment.
723 * [1] glsl-1.40/uniform_buffer/vs-float-array-variable-index.shader_test
725 if (devinfo
->gen
>= 7)
726 ctx
->Const
.UseSTD430AsDefaultPacking
= true;
728 if (!(ctx
->Const
.ContextFlags
& GL_CONTEXT_FLAG_DEBUG_BIT
))
729 ctx
->Const
.AllowMappedBuffersDuringExecution
= true;
731 /* GL_ARB_get_program_binary */
732 ctx
->Const
.NumProgramBinaryFormats
= 1;
736 brw_initialize_cs_context_constants(struct brw_context
*brw
)
738 struct gl_context
*ctx
= &brw
->ctx
;
739 const struct intel_screen
*screen
= brw
->screen
;
740 struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
742 /* FINISHME: Do this for all platforms that the kernel supports */
743 if (devinfo
->is_cherryview
&&
744 screen
->subslice_total
> 0 && screen
->eu_total
> 0) {
745 /* Logical CS threads = EUs per subslice * 7 threads per EU */
746 uint32_t max_cs_threads
= screen
->eu_total
/ screen
->subslice_total
* 7;
748 /* Fuse configurations may give more threads than expected, never less. */
749 if (max_cs_threads
> devinfo
->max_cs_threads
)
750 devinfo
->max_cs_threads
= max_cs_threads
;
753 /* Maximum number of scalar compute shader invocations that can be run in
754 * parallel in the same subslice assuming SIMD32 dispatch.
756 * We don't advertise more than 64 threads, because we are limited to 64 by
757 * our usage of thread_width_max in the gpgpu walker command. This only
758 * currently impacts Haswell, which otherwise might be able to advertise 70
759 * threads. With SIMD32 and 64 threads, Haswell still provides twice the
760 * required the number of invocation needed for ARB_compute_shader.
762 const unsigned max_threads
= MIN2(64, devinfo
->max_cs_threads
);
763 const uint32_t max_invocations
= 32 * max_threads
;
764 ctx
->Const
.MaxComputeWorkGroupSize
[0] = max_invocations
;
765 ctx
->Const
.MaxComputeWorkGroupSize
[1] = max_invocations
;
766 ctx
->Const
.MaxComputeWorkGroupSize
[2] = max_invocations
;
767 ctx
->Const
.MaxComputeWorkGroupInvocations
= max_invocations
;
768 ctx
->Const
.MaxComputeSharedMemorySize
= 64 * 1024;
772 * Process driconf (drirc) options, setting appropriate context flags.
774 * intelInitExtensions still pokes at optionCache directly, in order to
775 * avoid advertising various extensions. No flags are set, so it makes
776 * sense to continue doing that there.
779 brw_process_driconf_options(struct brw_context
*brw
)
781 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
782 struct gl_context
*ctx
= &brw
->ctx
;
784 driOptionCache
*options
= &brw
->optionCache
;
785 driParseConfigFiles(options
, &brw
->screen
->optionCache
,
786 brw
->driContext
->driScreenPriv
->myNum
, "i965");
788 int bo_reuse_mode
= driQueryOptioni(options
, "bo_reuse");
789 switch (bo_reuse_mode
) {
790 case DRI_CONF_BO_REUSE_DISABLED
:
792 case DRI_CONF_BO_REUSE_ALL
:
793 brw_bufmgr_enable_reuse(brw
->bufmgr
);
797 if (INTEL_DEBUG
& DEBUG_NO_HIZ
) {
798 brw
->has_hiz
= false;
799 /* On gen6, you can only do separate stencil with HIZ. */
800 if (devinfo
->gen
== 6)
801 brw
->has_separate_stencil
= false;
804 if (driQueryOptionb(options
, "mesa_no_error"))
805 ctx
->Const
.ContextFlags
|= GL_CONTEXT_FLAG_NO_ERROR_BIT_KHR
;
807 if (driQueryOptionb(options
, "always_flush_batch")) {
808 fprintf(stderr
, "flushing batchbuffer before/after each draw call\n");
809 brw
->always_flush_batch
= true;
812 if (driQueryOptionb(options
, "always_flush_cache")) {
813 fprintf(stderr
, "flushing GPU caches before/after each draw call\n");
814 brw
->always_flush_cache
= true;
817 if (driQueryOptionb(options
, "disable_throttling")) {
818 fprintf(stderr
, "disabling flush throttling\n");
819 brw
->disable_throttling
= true;
822 brw
->precompile
= driQueryOptionb(&brw
->optionCache
, "shader_precompile");
824 if (driQueryOptionb(&brw
->optionCache
, "precise_trig"))
825 brw
->screen
->compiler
->precise_trig
= true;
827 ctx
->Const
.ForceGLSLExtensionsWarn
=
828 driQueryOptionb(options
, "force_glsl_extensions_warn");
830 ctx
->Const
.ForceGLSLVersion
=
831 driQueryOptioni(options
, "force_glsl_version");
833 ctx
->Const
.DisableGLSLLineContinuations
=
834 driQueryOptionb(options
, "disable_glsl_line_continuations");
836 ctx
->Const
.AllowGLSLExtensionDirectiveMidShader
=
837 driQueryOptionb(options
, "allow_glsl_extension_directive_midshader");
839 ctx
->Const
.AllowGLSLBuiltinVariableRedeclaration
=
840 driQueryOptionb(options
, "allow_glsl_builtin_variable_redeclaration");
842 ctx
->Const
.AllowHigherCompatVersion
=
843 driQueryOptionb(options
, "allow_higher_compat_version");
845 ctx
->Const
.ForceGLSLAbsSqrt
=
846 driQueryOptionb(options
, "force_glsl_abs_sqrt");
848 ctx
->Const
.GLSLZeroInit
= driQueryOptionb(options
, "glsl_zero_init");
850 brw
->dual_color_blend_by_location
=
851 driQueryOptionb(options
, "dual_color_blend_by_location");
853 ctx
->Const
.AllowGLSLCrossStageInterpolationMismatch
=
854 driQueryOptionb(options
, "allow_glsl_cross_stage_interpolation_mismatch");
856 ctx
->Const
.dri_config_options_sha1
= ralloc_array(brw
, unsigned char, 20);
857 driComputeOptionsSha1(&brw
->screen
->optionCache
,
858 ctx
->Const
.dri_config_options_sha1
);
862 brwCreateContext(gl_api api
,
863 const struct gl_config
*mesaVis
,
864 __DRIcontext
*driContextPriv
,
865 const struct __DriverContextConfig
*ctx_config
,
866 unsigned *dri_ctx_error
,
867 void *sharedContextPrivate
)
869 struct gl_context
*shareCtx
= (struct gl_context
*) sharedContextPrivate
;
870 struct intel_screen
*screen
= driContextPriv
->driScreenPriv
->driverPrivate
;
871 const struct gen_device_info
*devinfo
= &screen
->devinfo
;
872 struct dd_function_table functions
;
874 /* Only allow the __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS flag if the kernel
875 * provides us with context reset notifications.
877 uint32_t allowed_flags
= __DRI_CTX_FLAG_DEBUG
|
878 __DRI_CTX_FLAG_FORWARD_COMPATIBLE
|
879 __DRI_CTX_FLAG_NO_ERROR
;
881 if (screen
->has_context_reset_notification
)
882 allowed_flags
|= __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS
;
884 if (ctx_config
->flags
& ~allowed_flags
) {
885 *dri_ctx_error
= __DRI_CTX_ERROR_UNKNOWN_FLAG
;
889 if (ctx_config
->attribute_mask
&
890 ~(__DRIVER_CONTEXT_ATTRIB_RESET_STRATEGY
|
891 __DRIVER_CONTEXT_ATTRIB_PRIORITY
)) {
892 *dri_ctx_error
= __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE
;
897 ((ctx_config
->attribute_mask
& __DRIVER_CONTEXT_ATTRIB_RESET_STRATEGY
) &&
898 ctx_config
->reset_strategy
!= __DRI_CTX_RESET_NO_NOTIFICATION
);
900 struct brw_context
*brw
= rzalloc(NULL
, struct brw_context
);
902 fprintf(stderr
, "%s: failed to alloc context\n", __func__
);
903 *dri_ctx_error
= __DRI_CTX_ERROR_NO_MEMORY
;
907 driContextPriv
->driverPrivate
= brw
;
908 brw
->driContext
= driContextPriv
;
909 brw
->screen
= screen
;
910 brw
->bufmgr
= screen
->bufmgr
;
912 brw
->has_hiz
= devinfo
->has_hiz_and_separate_stencil
;
913 brw
->has_separate_stencil
= devinfo
->has_hiz_and_separate_stencil
;
915 brw
->has_swizzling
= screen
->hw_has_swizzling
;
917 brw
->isl_dev
= screen
->isl_dev
;
919 brw
->vs
.base
.stage
= MESA_SHADER_VERTEX
;
920 brw
->tcs
.base
.stage
= MESA_SHADER_TESS_CTRL
;
921 brw
->tes
.base
.stage
= MESA_SHADER_TESS_EVAL
;
922 brw
->gs
.base
.stage
= MESA_SHADER_GEOMETRY
;
923 brw
->wm
.base
.stage
= MESA_SHADER_FRAGMENT
;
924 brw
->cs
.base
.stage
= MESA_SHADER_COMPUTE
;
925 if (devinfo
->gen
>= 8) {
926 brw
->vtbl
.emit_depth_stencil_hiz
= gen8_emit_depth_stencil_hiz
;
927 } else if (devinfo
->gen
>= 7) {
928 brw
->vtbl
.emit_depth_stencil_hiz
= gen7_emit_depth_stencil_hiz
;
929 } else if (devinfo
->gen
>= 6) {
930 brw
->vtbl
.emit_depth_stencil_hiz
= gen6_emit_depth_stencil_hiz
;
932 brw
->vtbl
.emit_depth_stencil_hiz
= brw_emit_depth_stencil_hiz
;
935 brw_init_driver_functions(brw
, &functions
);
938 functions
.GetGraphicsResetStatus
= brw_get_graphics_reset_status
;
940 struct gl_context
*ctx
= &brw
->ctx
;
942 if (!_mesa_initialize_context(ctx
, api
, mesaVis
, shareCtx
, &functions
)) {
943 *dri_ctx_error
= __DRI_CTX_ERROR_NO_MEMORY
;
944 fprintf(stderr
, "%s: failed to init mesa context\n", __func__
);
945 intelDestroyContext(driContextPriv
);
949 driContextSetFlags(ctx
, ctx_config
->flags
);
951 /* Initialize the software rasterizer and helper modules.
953 * As of GL 3.1 core, the gen4+ driver doesn't need the swrast context for
954 * software fallbacks (which we have to support on legacy GL to do weird
955 * glDrawPixels(), glBitmap(), and other functions).
957 if (api
!= API_OPENGL_CORE
&& api
!= API_OPENGLES2
) {
958 _swrast_CreateContext(ctx
);
961 _vbo_CreateContext(ctx
);
962 if (ctx
->swrast_context
) {
963 _tnl_CreateContext(ctx
);
964 TNL_CONTEXT(ctx
)->Driver
.RunPipeline
= _tnl_run_pipeline
;
965 _swsetup_CreateContext(ctx
);
967 /* Configure swrast to match hardware characteristics: */
968 _swrast_allow_pixel_fog(ctx
, false);
969 _swrast_allow_vertex_fog(ctx
, true);
972 _mesa_meta_init(ctx
);
974 brw_process_driconf_options(brw
);
976 if (INTEL_DEBUG
& DEBUG_PERF
)
977 brw
->perf_debug
= true;
979 brw_initialize_cs_context_constants(brw
);
980 brw_initialize_context_constants(brw
);
982 ctx
->Const
.ResetStrategy
= notify_reset
983 ? GL_LOSE_CONTEXT_ON_RESET_ARB
: GL_NO_RESET_NOTIFICATION_ARB
;
985 /* Reinitialize the context point state. It depends on ctx->Const values. */
986 _mesa_init_point(ctx
);
990 intel_batchbuffer_init(brw
);
992 if (devinfo
->gen
>= 6) {
993 /* Create a new hardware context. Using a hardware context means that
994 * our GPU state will be saved/restored on context switch, allowing us
995 * to assume that the GPU is in the same state we left it in.
997 * This is required for transform feedback buffer offsets, query objects,
998 * and also allows us to reduce how much state we have to emit.
1000 brw
->hw_ctx
= brw_create_hw_context(brw
->bufmgr
);
1003 fprintf(stderr
, "Failed to create hardware context.\n");
1004 intelDestroyContext(driContextPriv
);
1008 int hw_priority
= GEN_CONTEXT_MEDIUM_PRIORITY
;
1009 if (ctx_config
->attribute_mask
& __DRIVER_CONTEXT_ATTRIB_PRIORITY
) {
1010 switch (ctx_config
->priority
) {
1011 case __DRI_CTX_PRIORITY_LOW
:
1012 hw_priority
= GEN_CONTEXT_LOW_PRIORITY
;
1014 case __DRI_CTX_PRIORITY_HIGH
:
1015 hw_priority
= GEN_CONTEXT_HIGH_PRIORITY
;
1019 if (hw_priority
!= I915_CONTEXT_DEFAULT_PRIORITY
&&
1020 brw_hw_context_set_priority(brw
->bufmgr
, brw
->hw_ctx
, hw_priority
)) {
1022 "Failed to set priority [%d:%d] for hardware context.\n",
1023 ctx_config
->priority
, hw_priority
);
1024 intelDestroyContext(driContextPriv
);
1029 if (brw_init_pipe_control(brw
, devinfo
)) {
1030 *dri_ctx_error
= __DRI_CTX_ERROR_NO_MEMORY
;
1031 intelDestroyContext(driContextPriv
);
1035 if (devinfo
->gen
== 11) {
1037 "WARNING: i965 does not fully support Gen11 yet.\n"
1038 "Instability or lower performance might occur.\n");
1042 brw_upload_init(&brw
->upload
, brw
->bufmgr
, 65536);
1044 brw_init_state(brw
);
1046 intelInitExtensions(ctx
);
1048 brw_init_surface_formats(brw
);
1050 brw_blorp_init(brw
);
1052 brw
->urb
.size
= devinfo
->urb
.size
;
1054 if (devinfo
->gen
== 6)
1055 brw
->urb
.gs_present
= false;
1057 brw
->prim_restart
.in_progress
= false;
1058 brw
->prim_restart
.enable_cut_index
= false;
1059 brw
->gs
.enabled
= false;
1060 brw
->clip
.viewport_count
= 1;
1062 brw
->predicate
.state
= BRW_PREDICATE_STATE_RENDER
;
1064 brw
->max_gtt_map_object_size
= screen
->max_gtt_map_object_size
;
1066 ctx
->VertexProgram
._MaintainTnlProgram
= true;
1067 ctx
->FragmentProgram
._MaintainTexEnvProgram
= true;
1069 brw_draw_init( brw
);
1071 if ((ctx_config
->flags
& __DRI_CTX_FLAG_DEBUG
) != 0) {
1072 /* Turn on some extra GL_ARB_debug_output generation. */
1073 brw
->perf_debug
= true;
1076 if ((ctx_config
->flags
& __DRI_CTX_FLAG_ROBUST_BUFFER_ACCESS
) != 0) {
1077 ctx
->Const
.ContextFlags
|= GL_CONTEXT_FLAG_ROBUST_ACCESS_BIT_ARB
;
1078 ctx
->Const
.RobustAccess
= GL_TRUE
;
1081 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
1082 brw_init_shader_time(brw
);
1084 _mesa_override_extensions(ctx
);
1085 _mesa_compute_version(ctx
);
1087 /* GL_ARB_gl_spirv */
1088 if (ctx
->Extensions
.ARB_gl_spirv
)
1089 brw_initialize_spirv_supported_capabilities(brw
);
1091 _mesa_initialize_dispatch_tables(ctx
);
1092 _mesa_initialize_vbo_vtxfmt(ctx
);
1094 if (ctx
->Extensions
.INTEL_performance_query
)
1095 brw_init_performance_queries(brw
);
1097 vbo_use_buffer_objects(ctx
);
1098 vbo_always_unmap_buffers(ctx
);
1100 brw
->ctx
.Cache
= brw
->screen
->disk_cache
;
1106 intelDestroyContext(__DRIcontext
* driContextPriv
)
1108 struct brw_context
*brw
=
1109 (struct brw_context
*) driContextPriv
->driverPrivate
;
1110 struct gl_context
*ctx
= &brw
->ctx
;
1111 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1113 _mesa_meta_free(&brw
->ctx
);
1115 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
) {
1116 /* Force a report. */
1117 brw
->shader_time
.report_time
= 0;
1119 brw_collect_and_report_shader_time(brw
);
1120 brw_destroy_shader_time(brw
);
1123 if (devinfo
->gen
>= 6)
1124 blorp_finish(&brw
->blorp
);
1126 brw_destroy_state(brw
);
1127 brw_draw_destroy(brw
);
1129 brw_bo_unreference(brw
->curbe
.curbe_bo
);
1131 brw_bo_unreference(brw
->vs
.base
.scratch_bo
);
1132 brw_bo_unreference(brw
->tcs
.base
.scratch_bo
);
1133 brw_bo_unreference(brw
->tes
.base
.scratch_bo
);
1134 brw_bo_unreference(brw
->gs
.base
.scratch_bo
);
1135 brw_bo_unreference(brw
->wm
.base
.scratch_bo
);
1137 brw_bo_unreference(brw
->vs
.base
.push_const_bo
);
1138 brw_bo_unreference(brw
->tcs
.base
.push_const_bo
);
1139 brw_bo_unreference(brw
->tes
.base
.push_const_bo
);
1140 brw_bo_unreference(brw
->gs
.base
.push_const_bo
);
1141 brw_bo_unreference(brw
->wm
.base
.push_const_bo
);
1143 brw_destroy_hw_context(brw
->bufmgr
, brw
->hw_ctx
);
1145 if (ctx
->swrast_context
) {
1146 _swsetup_DestroyContext(&brw
->ctx
);
1147 _tnl_DestroyContext(&brw
->ctx
);
1149 _vbo_DestroyContext(&brw
->ctx
);
1151 if (ctx
->swrast_context
)
1152 _swrast_DestroyContext(&brw
->ctx
);
1154 brw_fini_pipe_control(brw
);
1155 intel_batchbuffer_free(&brw
->batch
);
1157 brw_bo_unreference(brw
->throttle_batch
[1]);
1158 brw_bo_unreference(brw
->throttle_batch
[0]);
1159 brw
->throttle_batch
[1] = NULL
;
1160 brw
->throttle_batch
[0] = NULL
;
1162 driDestroyOptionCache(&brw
->optionCache
);
1164 /* free the Mesa context */
1165 _mesa_free_context_data(&brw
->ctx
);
1168 driContextPriv
->driverPrivate
= NULL
;
1172 intelUnbindContext(__DRIcontext
* driContextPriv
)
1174 /* Unset current context and dispath table */
1175 _mesa_make_current(NULL
, NULL
, NULL
);
1181 * Fixes up the context for GLES23 with our default-to-sRGB-capable behavior
1182 * on window system framebuffers.
1184 * Desktop GL is fairly reasonable in its handling of sRGB: You can ask if
1185 * your renderbuffer can do sRGB encode, and you can flip a switch that does
1186 * sRGB encode if the renderbuffer can handle it. You can ask specifically
1187 * for a visual where you're guaranteed to be capable, but it turns out that
1188 * everyone just makes all their ARGB8888 visuals capable and doesn't offer
1189 * incapable ones, because there's no difference between the two in resources
1190 * used. Applications thus get built that accidentally rely on the default
1191 * visual choice being sRGB, so we make ours sRGB capable. Everything sounds
1194 * But for GLES2/3, they decided that it was silly to not turn on sRGB encode
1195 * for sRGB renderbuffers you made with the GL_EXT_texture_sRGB equivalent.
1196 * So they removed the enable knob and made it "if the renderbuffer is sRGB
1197 * capable, do sRGB encode". Then, for your window system renderbuffers, you
1198 * can ask for sRGB visuals and get sRGB encode, or not ask for sRGB visuals
1199 * and get no sRGB encode (assuming that both kinds of visual are available).
1200 * Thus our choice to support sRGB by default on our visuals for desktop would
1201 * result in broken rendering of GLES apps that aren't expecting sRGB encode.
1203 * Unfortunately, renderbuffer setup happens before a context is created. So
1204 * in intel_screen.c we always set up sRGB, and here, if you're a GLES2/3
1205 * context (without an sRGB visual), we go turn that back off before anyone
1209 intel_gles3_srgb_workaround(struct brw_context
*brw
,
1210 struct gl_framebuffer
*fb
)
1212 struct gl_context
*ctx
= &brw
->ctx
;
1214 if (_mesa_is_desktop_gl(ctx
) || !fb
->Visual
.sRGBCapable
)
1217 for (int i
= 0; i
< BUFFER_COUNT
; i
++) {
1218 struct gl_renderbuffer
*rb
= fb
->Attachment
[i
].Renderbuffer
;
1220 /* Check if sRGB was specifically asked for. */
1221 struct intel_renderbuffer
*irb
= intel_get_renderbuffer(fb
, i
);
1222 if (irb
&& irb
->need_srgb
)
1226 rb
->Format
= _mesa_get_srgb_format_linear(rb
->Format
);
1228 /* Disable sRGB from framebuffers that are not compatible. */
1229 fb
->Visual
.sRGBCapable
= false;
1233 intelMakeCurrent(__DRIcontext
* driContextPriv
,
1234 __DRIdrawable
* driDrawPriv
,
1235 __DRIdrawable
* driReadPriv
)
1237 struct brw_context
*brw
;
1240 brw
= (struct brw_context
*) driContextPriv
->driverPrivate
;
1244 if (driContextPriv
) {
1245 struct gl_context
*ctx
= &brw
->ctx
;
1246 struct gl_framebuffer
*fb
, *readFb
;
1248 if (driDrawPriv
== NULL
) {
1249 fb
= _mesa_get_incomplete_framebuffer();
1251 fb
= driDrawPriv
->driverPrivate
;
1252 driContextPriv
->dri2
.draw_stamp
= driDrawPriv
->dri2
.stamp
- 1;
1255 if (driReadPriv
== NULL
) {
1256 readFb
= _mesa_get_incomplete_framebuffer();
1258 readFb
= driReadPriv
->driverPrivate
;
1259 driContextPriv
->dri2
.read_stamp
= driReadPriv
->dri2
.stamp
- 1;
1262 /* The sRGB workaround changes the renderbuffer's format. We must change
1263 * the format before the renderbuffer's miptree get's allocated, otherwise
1264 * the formats of the renderbuffer and its miptree will differ.
1266 intel_gles3_srgb_workaround(brw
, fb
);
1267 intel_gles3_srgb_workaround(brw
, readFb
);
1269 /* If the context viewport hasn't been initialized, force a call out to
1270 * the loader to get buffers so we have a drawable size for the initial
1272 if (!brw
->ctx
.ViewportInitialized
)
1273 intel_prepare_render(brw
);
1275 _mesa_make_current(ctx
, fb
, readFb
);
1277 _mesa_make_current(NULL
, NULL
, NULL
);
1284 intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1285 __DRIdrawable
*drawable
)
1287 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
1289 if (devinfo
->gen
< 6) {
1290 /* MSAA and fast color clear are not supported, so don't waste time
1291 * checking whether a resolve is needed.
1296 struct gl_framebuffer
*fb
= drawable
->driverPrivate
;
1297 struct intel_renderbuffer
*rb
;
1299 /* Usually, only the back buffer will need to be downsampled. However,
1300 * the front buffer will also need it if the user has rendered into it.
1302 static const gl_buffer_index buffers
[2] = {
1307 for (int i
= 0; i
< 2; ++i
) {
1308 rb
= intel_get_renderbuffer(fb
, buffers
[i
]);
1309 if (rb
== NULL
|| rb
->mt
== NULL
)
1311 if (rb
->mt
->surf
.samples
== 1) {
1312 assert(rb
->mt_layer
== 0 && rb
->mt_level
== 0 &&
1313 rb
->layer_count
== 1);
1314 intel_miptree_prepare_external(brw
, rb
->mt
);
1316 intel_renderbuffer_downsample(brw
, rb
);
1318 /* Call prepare_external on the single-sample miptree to do any
1319 * needed resolves prior to handing it off to the window system.
1320 * This is needed in the case that rb->singlesample_mt is Y-tiled
1321 * with CCS_E enabled but without I915_FORMAT_MOD_Y_TILED_CCS_E. In
1322 * this case, the MSAA resolve above will write compressed data into
1323 * rb->singlesample_mt.
1325 * TODO: Some day, if we decide to care about the tiny performance
1326 * hit we're taking by doing the MSAA resolve and then a CCS resolve,
1327 * we could detect this case and just allocate the single-sampled
1328 * miptree without aux. However, that would be a lot of plumbing and
1329 * this is a rather exotic case so it's not really worth it.
1331 intel_miptree_prepare_external(brw
, rb
->singlesample_mt
);
1337 intel_bits_per_pixel(const struct intel_renderbuffer
*rb
)
1339 return _mesa_get_format_bytes(intel_rb_format(rb
)) * 8;
1343 intel_query_dri2_buffers(struct brw_context
*brw
,
1344 __DRIdrawable
*drawable
,
1345 __DRIbuffer
**buffers
,
1349 intel_process_dri2_buffer(struct brw_context
*brw
,
1350 __DRIdrawable
*drawable
,
1351 __DRIbuffer
*buffer
,
1352 struct intel_renderbuffer
*rb
,
1353 const char *buffer_name
);
1356 intel_update_image_buffers(struct brw_context
*brw
, __DRIdrawable
*drawable
);
1359 intel_update_dri2_buffers(struct brw_context
*brw
, __DRIdrawable
*drawable
)
1361 struct gl_framebuffer
*fb
= drawable
->driverPrivate
;
1362 struct intel_renderbuffer
*rb
;
1363 __DRIbuffer
*buffers
= NULL
;
1365 const char *region_name
;
1367 /* Set this up front, so that in case our buffers get invalidated
1368 * while we're getting new buffers, we don't clobber the stamp and
1369 * thus ignore the invalidate. */
1370 drawable
->lastStamp
= drawable
->dri2
.stamp
;
1372 if (unlikely(INTEL_DEBUG
& DEBUG_DRI
))
1373 fprintf(stderr
, "enter %s, drawable %p\n", __func__
, drawable
);
1375 intel_query_dri2_buffers(brw
, drawable
, &buffers
, &count
);
1377 if (buffers
== NULL
)
1380 for (int i
= 0; i
< count
; i
++) {
1381 switch (buffers
[i
].attachment
) {
1382 case __DRI_BUFFER_FRONT_LEFT
:
1383 rb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
1384 region_name
= "dri2 front buffer";
1387 case __DRI_BUFFER_FAKE_FRONT_LEFT
:
1388 rb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
1389 region_name
= "dri2 fake front buffer";
1392 case __DRI_BUFFER_BACK_LEFT
:
1393 rb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
1394 region_name
= "dri2 back buffer";
1397 case __DRI_BUFFER_DEPTH
:
1398 case __DRI_BUFFER_HIZ
:
1399 case __DRI_BUFFER_DEPTH_STENCIL
:
1400 case __DRI_BUFFER_STENCIL
:
1401 case __DRI_BUFFER_ACCUM
:
1404 "unhandled buffer attach event, attachment type %d\n",
1405 buffers
[i
].attachment
);
1409 intel_process_dri2_buffer(brw
, drawable
, &buffers
[i
], rb
, region_name
);
1415 intel_update_renderbuffers(__DRIcontext
*context
, __DRIdrawable
*drawable
)
1417 struct brw_context
*brw
= context
->driverPrivate
;
1418 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
1420 /* Set this up front, so that in case our buffers get invalidated
1421 * while we're getting new buffers, we don't clobber the stamp and
1422 * thus ignore the invalidate. */
1423 drawable
->lastStamp
= drawable
->dri2
.stamp
;
1425 if (unlikely(INTEL_DEBUG
& DEBUG_DRI
))
1426 fprintf(stderr
, "enter %s, drawable %p\n", __func__
, drawable
);
1428 if (dri_screen
->image
.loader
)
1429 intel_update_image_buffers(brw
, drawable
);
1431 intel_update_dri2_buffers(brw
, drawable
);
1433 driUpdateFramebufferSize(&brw
->ctx
, drawable
);
1437 * intel_prepare_render should be called anywhere that curent read/drawbuffer
1438 * state is required.
1441 intel_prepare_render(struct brw_context
*brw
)
1443 struct gl_context
*ctx
= &brw
->ctx
;
1444 __DRIcontext
*driContext
= brw
->driContext
;
1445 __DRIdrawable
*drawable
;
1447 drawable
= driContext
->driDrawablePriv
;
1448 if (drawable
&& drawable
->dri2
.stamp
!= driContext
->dri2
.draw_stamp
) {
1449 if (drawable
->lastStamp
!= drawable
->dri2
.stamp
)
1450 intel_update_renderbuffers(driContext
, drawable
);
1451 driContext
->dri2
.draw_stamp
= drawable
->dri2
.stamp
;
1454 drawable
= driContext
->driReadablePriv
;
1455 if (drawable
&& drawable
->dri2
.stamp
!= driContext
->dri2
.read_stamp
) {
1456 if (drawable
->lastStamp
!= drawable
->dri2
.stamp
)
1457 intel_update_renderbuffers(driContext
, drawable
);
1458 driContext
->dri2
.read_stamp
= drawable
->dri2
.stamp
;
1461 /* If we're currently rendering to the front buffer, the rendering
1462 * that will happen next will probably dirty the front buffer. So
1463 * mark it as dirty here.
1465 if (_mesa_is_front_buffer_drawing(ctx
->DrawBuffer
))
1466 brw
->front_buffer_dirty
= true;
1470 * \brief Query DRI2 to obtain a DRIdrawable's buffers.
1472 * To determine which DRI buffers to request, examine the renderbuffers
1473 * attached to the drawable's framebuffer. Then request the buffers with
1474 * DRI2GetBuffers() or DRI2GetBuffersWithFormat().
1476 * This is called from intel_update_renderbuffers().
1478 * \param drawable Drawable whose buffers are queried.
1479 * \param buffers [out] List of buffers returned by DRI2 query.
1480 * \param buffer_count [out] Number of buffers returned.
1482 * \see intel_update_renderbuffers()
1483 * \see DRI2GetBuffers()
1484 * \see DRI2GetBuffersWithFormat()
1487 intel_query_dri2_buffers(struct brw_context
*brw
,
1488 __DRIdrawable
*drawable
,
1489 __DRIbuffer
**buffers
,
1492 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
1493 struct gl_framebuffer
*fb
= drawable
->driverPrivate
;
1495 unsigned attachments
[8];
1497 struct intel_renderbuffer
*front_rb
;
1498 struct intel_renderbuffer
*back_rb
;
1500 front_rb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
1501 back_rb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
1503 memset(attachments
, 0, sizeof(attachments
));
1504 if ((_mesa_is_front_buffer_drawing(fb
) ||
1505 _mesa_is_front_buffer_reading(fb
) ||
1506 !back_rb
) && front_rb
) {
1507 /* If a fake front buffer is in use, then querying for
1508 * __DRI_BUFFER_FRONT_LEFT will cause the server to copy the image from
1509 * the real front buffer to the fake front buffer. So before doing the
1510 * query, we need to make sure all the pending drawing has landed in the
1511 * real front buffer.
1513 intel_batchbuffer_flush(brw
);
1514 intel_flush_front(&brw
->ctx
);
1516 attachments
[i
++] = __DRI_BUFFER_FRONT_LEFT
;
1517 attachments
[i
++] = intel_bits_per_pixel(front_rb
);
1518 } else if (front_rb
&& brw
->front_buffer_dirty
) {
1519 /* We have pending front buffer rendering, but we aren't querying for a
1520 * front buffer. If the front buffer we have is a fake front buffer,
1521 * the X server is going to throw it away when it processes the query.
1522 * So before doing the query, make sure all the pending drawing has
1523 * landed in the real front buffer.
1525 intel_batchbuffer_flush(brw
);
1526 intel_flush_front(&brw
->ctx
);
1530 attachments
[i
++] = __DRI_BUFFER_BACK_LEFT
;
1531 attachments
[i
++] = intel_bits_per_pixel(back_rb
);
1534 assert(i
<= ARRAY_SIZE(attachments
));
1537 dri_screen
->dri2
.loader
->getBuffersWithFormat(drawable
,
1542 drawable
->loaderPrivate
);
1546 * \brief Assign a DRI buffer's DRM region to a renderbuffer.
1548 * This is called from intel_update_renderbuffers().
1551 * DRI buffers whose attachment point is DRI2BufferStencil or
1552 * DRI2BufferDepthStencil are handled as special cases.
1554 * \param buffer_name is a human readable name, such as "dri2 front buffer",
1555 * that is passed to brw_bo_gem_create_from_name().
1557 * \see intel_update_renderbuffers()
1560 intel_process_dri2_buffer(struct brw_context
*brw
,
1561 __DRIdrawable
*drawable
,
1562 __DRIbuffer
*buffer
,
1563 struct intel_renderbuffer
*rb
,
1564 const char *buffer_name
)
1566 struct gl_framebuffer
*fb
= drawable
->driverPrivate
;
1572 unsigned num_samples
= rb
->Base
.Base
.NumSamples
;
1574 /* We try to avoid closing and reopening the same BO name, because the first
1575 * use of a mapping of the buffer involves a bunch of page faulting which is
1576 * moderately expensive.
1578 struct intel_mipmap_tree
*last_mt
;
1579 if (num_samples
== 0)
1582 last_mt
= rb
->singlesample_mt
;
1584 uint32_t old_name
= 0;
1586 /* The bo already has a name because the miptree was created by a
1587 * previous call to intel_process_dri2_buffer(). If a bo already has a
1588 * name, then brw_bo_flink() is a low-cost getter. It does not
1589 * create a new name.
1591 brw_bo_flink(last_mt
->bo
, &old_name
);
1594 if (old_name
== buffer
->name
)
1597 if (unlikely(INTEL_DEBUG
& DEBUG_DRI
)) {
1599 "attaching buffer %d, at %d, cpp %d, pitch %d\n",
1600 buffer
->name
, buffer
->attachment
,
1601 buffer
->cpp
, buffer
->pitch
);
1604 bo
= brw_bo_gem_create_from_name(brw
->bufmgr
, buffer_name
,
1608 "Failed to open BO for returned DRI2 buffer "
1609 "(%dx%d, %s, named %d).\n"
1610 "This is likely a bug in the X Server that will lead to a "
1612 drawable
->w
, drawable
->h
, buffer_name
, buffer
->name
);
1616 uint32_t tiling
, swizzle
;
1617 brw_bo_get_tiling(bo
, &tiling
, &swizzle
);
1619 struct intel_mipmap_tree
*mt
=
1620 intel_miptree_create_for_bo(brw
,
1622 intel_rb_format(rb
),
1628 isl_tiling_from_i915_tiling(tiling
),
1629 MIPTREE_CREATE_DEFAULT
);
1631 brw_bo_unreference(bo
);
1635 /* We got this BO from X11. We cana't assume that we have coherent texture
1636 * access because X may suddenly decide to use it for scan-out which would
1637 * destroy coherency.
1639 bo
->cache_coherent
= false;
1641 if (!intel_update_winsys_renderbuffer_miptree(brw
, rb
, mt
,
1642 drawable
->w
, drawable
->h
,
1644 brw_bo_unreference(bo
);
1645 intel_miptree_release(&mt
);
1649 if (_mesa_is_front_buffer_drawing(fb
) &&
1650 (buffer
->attachment
== __DRI_BUFFER_FRONT_LEFT
||
1651 buffer
->attachment
== __DRI_BUFFER_FAKE_FRONT_LEFT
) &&
1652 rb
->Base
.Base
.NumSamples
> 1) {
1653 intel_renderbuffer_upsample(brw
, rb
);
1658 brw_bo_unreference(bo
);
1662 * \brief Query DRI image loader to obtain a DRIdrawable's buffers.
1664 * To determine which DRI buffers to request, examine the renderbuffers
1665 * attached to the drawable's framebuffer. Then request the buffers from
1668 * This is called from intel_update_renderbuffers().
1670 * \param drawable Drawable whose buffers are queried.
1671 * \param buffers [out] List of buffers returned by DRI2 query.
1672 * \param buffer_count [out] Number of buffers returned.
1674 * \see intel_update_renderbuffers()
1678 intel_update_image_buffer(struct brw_context
*intel
,
1679 __DRIdrawable
*drawable
,
1680 struct intel_renderbuffer
*rb
,
1682 enum __DRIimageBufferMask buffer_type
)
1684 struct gl_framebuffer
*fb
= drawable
->driverPrivate
;
1686 if (!rb
|| !buffer
->bo
)
1689 unsigned num_samples
= rb
->Base
.Base
.NumSamples
;
1691 /* Check and see if we're already bound to the right
1694 struct intel_mipmap_tree
*last_mt
;
1695 if (num_samples
== 0)
1698 last_mt
= rb
->singlesample_mt
;
1700 if (last_mt
&& last_mt
->bo
== buffer
->bo
)
1703 struct intel_mipmap_tree
*mt
=
1704 intel_miptree_create_for_dri_image(intel
, buffer
, GL_TEXTURE_2D
,
1705 intel_rb_format(rb
), true);
1709 if (!intel_update_winsys_renderbuffer_miptree(intel
, rb
, mt
,
1710 buffer
->width
, buffer
->height
,
1712 intel_miptree_release(&mt
);
1716 if (_mesa_is_front_buffer_drawing(fb
) &&
1717 buffer_type
== __DRI_IMAGE_BUFFER_FRONT
&&
1718 rb
->Base
.Base
.NumSamples
> 1) {
1719 intel_renderbuffer_upsample(intel
, rb
);
1724 intel_update_image_buffers(struct brw_context
*brw
, __DRIdrawable
*drawable
)
1726 struct gl_framebuffer
*fb
= drawable
->driverPrivate
;
1727 __DRIscreen
*dri_screen
= brw
->screen
->driScrnPriv
;
1728 struct intel_renderbuffer
*front_rb
;
1729 struct intel_renderbuffer
*back_rb
;
1730 struct __DRIimageList images
;
1732 uint32_t buffer_mask
= 0;
1735 front_rb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
1736 back_rb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
1739 format
= intel_rb_format(back_rb
);
1741 format
= intel_rb_format(front_rb
);
1745 if (front_rb
&& (_mesa_is_front_buffer_drawing(fb
) ||
1746 _mesa_is_front_buffer_reading(fb
) || !back_rb
)) {
1747 buffer_mask
|= __DRI_IMAGE_BUFFER_FRONT
;
1751 buffer_mask
|= __DRI_IMAGE_BUFFER_BACK
;
1753 ret
= dri_screen
->image
.loader
->getBuffers(drawable
,
1754 driGLFormatToImageFormat(format
),
1755 &drawable
->dri2
.stamp
,
1756 drawable
->loaderPrivate
,
1762 if (images
.image_mask
& __DRI_IMAGE_BUFFER_FRONT
) {
1763 drawable
->w
= images
.front
->width
;
1764 drawable
->h
= images
.front
->height
;
1765 intel_update_image_buffer(brw
,
1769 __DRI_IMAGE_BUFFER_FRONT
);
1772 if (images
.image_mask
& __DRI_IMAGE_BUFFER_BACK
) {
1773 drawable
->w
= images
.back
->width
;
1774 drawable
->h
= images
.back
->height
;
1775 intel_update_image_buffer(brw
,
1779 __DRI_IMAGE_BUFFER_BACK
);