2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keithw@vmware.com>
33 #ifndef BRWCONTEXT_INC
34 #define BRWCONTEXT_INC
37 #include "main/macros.h"
38 #include "main/mtypes.h"
39 #include "brw_structs.h"
40 #include "compiler/brw_compiler.h"
43 #include "blorp/blorp.h"
45 #include <brw_bufmgr.h>
47 #include "common/gen_debug.h"
48 #include "intel_screen.h"
49 #include "intel_tex_obj.h"
56 * URB - uniform resource buffer. A mid-sized buffer which is
57 * partitioned between the fixed function units and used for passing
58 * values (vertices, primitives, constants) between them.
60 * CURBE - constant URB entry. An urb region (entry) used to hold
61 * constant values which the fixed function units can be instructed to
62 * preload into the GRF when spawning a thread.
64 * VUE - vertex URB entry. An urb entry holding a vertex and usually
65 * a vertex header. The header contains control information and
66 * things like primitive type, Begin/end flags and clip codes.
68 * PUE - primitive URB entry. An urb entry produced by the setup (SF)
69 * unit holding rasterization and interpolation parameters.
71 * GRF - general register file. One of several register files
72 * addressable by programmed threads. The inputs (r0, payload, curbe,
73 * urb) of the thread are preloaded to this area before the thread is
74 * spawned. The registers are individually 8 dwords wide and suitable
75 * for general usage. Registers holding thread input values are not
76 * special and may be overwritten.
78 * MRF - message register file. Threads communicate (and terminate)
79 * by sending messages. Message parameters are placed in contiguous
80 * MRF registers. All program output is via these messages. URB
81 * entries are populated by sending a message to the shared URB
82 * function containing the new data, together with a control word,
83 * often an unmodified copy of R0.
85 * R0 - GRF register 0. Typically holds control information used when
86 * sending messages to other threads.
88 * EU or GEN4 EU: The name of the programmable subsystem of the
89 * i965 hardware. Threads are executed by the EU, the registers
90 * described above are part of the EU architecture.
92 * Fixed function units:
94 * CS - Command streamer. Notional first unit, little software
95 * interaction. Holds the URB entries used for constant data, ie the
98 * VF/VS - Vertex Fetch / Vertex Shader. The fixed function part of
99 * this unit is responsible for pulling vertices out of vertex buffers
100 * in vram and injecting them into the processing pipe as VUEs. If
101 * enabled, it first passes them to a VS thread which is a good place
102 * for the driver to implement any active vertex shader.
104 * HS - Hull Shader (Tessellation Control Shader)
106 * TE - Tessellation Engine (Tessellation Primitive Generation)
108 * DS - Domain Shader (Tessellation Evaluation Shader)
110 * GS - Geometry Shader. This corresponds to a new DX10 concept. If
111 * enabled, incoming strips etc are passed to GS threads in individual
112 * line/triangle/point units. The GS thread may perform arbitary
113 * computation and emit whatever primtives with whatever vertices it
114 * chooses. This makes GS an excellent place to implement GL's
115 * unfilled polygon modes, though of course it is capable of much
116 * more. Additionally, GS is used to translate away primitives not
117 * handled by latter units, including Quads and Lineloops.
119 * CS - Clipper. Mesa's clipping algorithms are imported to run on
120 * this unit. The fixed function part performs cliptesting against
121 * the 6 fixed clipplanes and makes descisions on whether or not the
122 * incoming primitive needs to be passed to a thread for clipping.
123 * User clip planes are handled via cooperation with the VS thread.
125 * SF - Strips Fans or Setup: Triangles are prepared for
126 * rasterization. Interpolation coefficients are calculated.
127 * Flatshading and two-side lighting usually performed here.
129 * WM - Windower. Interpolation of vertex attributes performed here.
130 * Fragment shader implemented here. SIMD aspects of EU taken full
131 * advantage of, as pixels are processed in blocks of 16.
133 * CC - Color Calculator. No EU threads associated with this unit.
134 * Handles blending and (presumably) depth and stencil testing.
139 struct brw_vs_prog_key
;
140 struct brw_vue_prog_key
;
141 struct brw_wm_prog_key
;
142 struct brw_wm_prog_data
;
143 struct brw_cs_prog_key
;
144 struct brw_cs_prog_data
;
148 BRW_COMPUTE_PIPELINE
,
155 BRW_CACHE_BLORP_PROG
,
158 BRW_CACHE_FF_GS_PROG
,
169 /* brw_cache_ids must come first - see brw_program_cache.c */
170 BRW_STATE_URB_FENCE
= BRW_MAX_CACHE
,
171 BRW_STATE_FRAGMENT_PROGRAM
,
172 BRW_STATE_GEOMETRY_PROGRAM
,
173 BRW_STATE_TESS_PROGRAMS
,
174 BRW_STATE_VERTEX_PROGRAM
,
175 BRW_STATE_REDUCED_PRIMITIVE
,
176 BRW_STATE_PATCH_PRIMITIVE
,
181 BRW_STATE_BINDING_TABLE_POINTERS
,
184 BRW_STATE_DEFAULT_TESS_LEVELS
,
186 BRW_STATE_INDEX_BUFFER
,
187 BRW_STATE_VS_CONSTBUF
,
188 BRW_STATE_TCS_CONSTBUF
,
189 BRW_STATE_TES_CONSTBUF
,
190 BRW_STATE_GS_CONSTBUF
,
191 BRW_STATE_PROGRAM_CACHE
,
192 BRW_STATE_STATE_BASE_ADDRESS
,
193 BRW_STATE_VUE_MAP_GEOM_OUT
,
194 BRW_STATE_TRANSFORM_FEEDBACK
,
195 BRW_STATE_RASTERIZER_DISCARD
,
197 BRW_STATE_UNIFORM_BUFFER
,
198 BRW_STATE_IMAGE_UNITS
,
199 BRW_STATE_META_IN_PROGRESS
,
200 BRW_STATE_PUSH_CONSTANT_ALLOCATION
,
201 BRW_STATE_NUM_SAMPLES
,
202 BRW_STATE_TEXTURE_BUFFER
,
203 BRW_STATE_GEN4_UNIT_STATE
,
207 BRW_STATE_SAMPLER_STATE_TABLE
,
208 BRW_STATE_VS_ATTRIB_WORKAROUNDS
,
209 BRW_STATE_COMPUTE_PROGRAM
,
210 BRW_STATE_CS_WORK_GROUPS
,
214 BRW_STATE_VIEWPORT_COUNT
,
215 BRW_STATE_CONSERVATIVE_RASTERIZATION
,
222 * BRW_NEW_*_PROG_DATA and BRW_NEW_*_PROGRAM are similar, but distinct.
224 * BRW_NEW_*_PROGRAM relates to the gl_shader_program/gl_program structures.
225 * When the currently bound shader program differs from the previous draw
226 * call, these will be flagged. They cover brw->{stage}_program and
227 * ctx->{Stage}Program->_Current.
229 * BRW_NEW_*_PROG_DATA is flagged when the effective shaders change, from a
230 * driver perspective. Even if the same shader is bound at the API level,
231 * we may need to switch between multiple versions of that shader to handle
232 * changes in non-orthagonal state.
234 * Additionally, multiple shader programs may have identical vertex shaders
235 * (for example), or compile down to the same code in the backend. We combine
236 * those into a single program cache entry.
238 * BRW_NEW_*_PROG_DATA occurs when switching program cache entries, which
239 * covers the brw_*_prog_data structures, and brw->*.prog_offset.
241 #define BRW_NEW_FS_PROG_DATA (1ull << BRW_CACHE_FS_PROG)
242 /* XXX: The BRW_NEW_BLORP_BLIT_PROG_DATA dirty bit is unused (as BLORP doesn't
243 * use the normal state upload paths), but the cache is still used. To avoid
244 * polluting the brw_program_cache code with special cases, we retain the
245 * dirty bit for now. It should eventually be removed.
247 #define BRW_NEW_BLORP_BLIT_PROG_DATA (1ull << BRW_CACHE_BLORP_PROG)
248 #define BRW_NEW_SF_PROG_DATA (1ull << BRW_CACHE_SF_PROG)
249 #define BRW_NEW_VS_PROG_DATA (1ull << BRW_CACHE_VS_PROG)
250 #define BRW_NEW_FF_GS_PROG_DATA (1ull << BRW_CACHE_FF_GS_PROG)
251 #define BRW_NEW_GS_PROG_DATA (1ull << BRW_CACHE_GS_PROG)
252 #define BRW_NEW_TCS_PROG_DATA (1ull << BRW_CACHE_TCS_PROG)
253 #define BRW_NEW_TES_PROG_DATA (1ull << BRW_CACHE_TES_PROG)
254 #define BRW_NEW_CLIP_PROG_DATA (1ull << BRW_CACHE_CLIP_PROG)
255 #define BRW_NEW_CS_PROG_DATA (1ull << BRW_CACHE_CS_PROG)
256 #define BRW_NEW_URB_FENCE (1ull << BRW_STATE_URB_FENCE)
257 #define BRW_NEW_FRAGMENT_PROGRAM (1ull << BRW_STATE_FRAGMENT_PROGRAM)
258 #define BRW_NEW_GEOMETRY_PROGRAM (1ull << BRW_STATE_GEOMETRY_PROGRAM)
259 #define BRW_NEW_TESS_PROGRAMS (1ull << BRW_STATE_TESS_PROGRAMS)
260 #define BRW_NEW_VERTEX_PROGRAM (1ull << BRW_STATE_VERTEX_PROGRAM)
261 #define BRW_NEW_REDUCED_PRIMITIVE (1ull << BRW_STATE_REDUCED_PRIMITIVE)
262 #define BRW_NEW_PATCH_PRIMITIVE (1ull << BRW_STATE_PATCH_PRIMITIVE)
263 #define BRW_NEW_PRIMITIVE (1ull << BRW_STATE_PRIMITIVE)
264 #define BRW_NEW_CONTEXT (1ull << BRW_STATE_CONTEXT)
265 #define BRW_NEW_PSP (1ull << BRW_STATE_PSP)
266 #define BRW_NEW_SURFACES (1ull << BRW_STATE_SURFACES)
267 #define BRW_NEW_BINDING_TABLE_POINTERS (1ull << BRW_STATE_BINDING_TABLE_POINTERS)
268 #define BRW_NEW_INDICES (1ull << BRW_STATE_INDICES)
269 #define BRW_NEW_VERTICES (1ull << BRW_STATE_VERTICES)
270 #define BRW_NEW_DEFAULT_TESS_LEVELS (1ull << BRW_STATE_DEFAULT_TESS_LEVELS)
272 * Used for any batch entry with a relocated pointer that will be used
273 * by any 3D rendering.
275 #define BRW_NEW_BATCH (1ull << BRW_STATE_BATCH)
276 /** \see brw.state.depth_region */
277 #define BRW_NEW_INDEX_BUFFER (1ull << BRW_STATE_INDEX_BUFFER)
278 #define BRW_NEW_VS_CONSTBUF (1ull << BRW_STATE_VS_CONSTBUF)
279 #define BRW_NEW_TCS_CONSTBUF (1ull << BRW_STATE_TCS_CONSTBUF)
280 #define BRW_NEW_TES_CONSTBUF (1ull << BRW_STATE_TES_CONSTBUF)
281 #define BRW_NEW_GS_CONSTBUF (1ull << BRW_STATE_GS_CONSTBUF)
282 #define BRW_NEW_PROGRAM_CACHE (1ull << BRW_STATE_PROGRAM_CACHE)
283 #define BRW_NEW_STATE_BASE_ADDRESS (1ull << BRW_STATE_STATE_BASE_ADDRESS)
284 #define BRW_NEW_VUE_MAP_GEOM_OUT (1ull << BRW_STATE_VUE_MAP_GEOM_OUT)
285 #define BRW_NEW_VIEWPORT_COUNT (1ull << BRW_STATE_VIEWPORT_COUNT)
286 #define BRW_NEW_TRANSFORM_FEEDBACK (1ull << BRW_STATE_TRANSFORM_FEEDBACK)
287 #define BRW_NEW_RASTERIZER_DISCARD (1ull << BRW_STATE_RASTERIZER_DISCARD)
288 #define BRW_NEW_STATS_WM (1ull << BRW_STATE_STATS_WM)
289 #define BRW_NEW_UNIFORM_BUFFER (1ull << BRW_STATE_UNIFORM_BUFFER)
290 #define BRW_NEW_IMAGE_UNITS (1ull << BRW_STATE_IMAGE_UNITS)
291 #define BRW_NEW_META_IN_PROGRESS (1ull << BRW_STATE_META_IN_PROGRESS)
292 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << BRW_STATE_PUSH_CONSTANT_ALLOCATION)
293 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
294 #define BRW_NEW_TEXTURE_BUFFER (1ull << BRW_STATE_TEXTURE_BUFFER)
295 #define BRW_NEW_GEN4_UNIT_STATE (1ull << BRW_STATE_GEN4_UNIT_STATE)
296 #define BRW_NEW_CC_VP (1ull << BRW_STATE_CC_VP)
297 #define BRW_NEW_SF_VP (1ull << BRW_STATE_SF_VP)
298 #define BRW_NEW_CLIP_VP (1ull << BRW_STATE_CLIP_VP)
299 #define BRW_NEW_SAMPLER_STATE_TABLE (1ull << BRW_STATE_SAMPLER_STATE_TABLE)
300 #define BRW_NEW_VS_ATTRIB_WORKAROUNDS (1ull << BRW_STATE_VS_ATTRIB_WORKAROUNDS)
301 #define BRW_NEW_COMPUTE_PROGRAM (1ull << BRW_STATE_COMPUTE_PROGRAM)
302 #define BRW_NEW_CS_WORK_GROUPS (1ull << BRW_STATE_CS_WORK_GROUPS)
303 #define BRW_NEW_URB_SIZE (1ull << BRW_STATE_URB_SIZE)
304 #define BRW_NEW_CC_STATE (1ull << BRW_STATE_CC_STATE)
305 #define BRW_NEW_BLORP (1ull << BRW_STATE_BLORP)
306 #define BRW_NEW_CONSERVATIVE_RASTERIZATION (1ull << BRW_STATE_CONSERVATIVE_RASTERIZATION)
307 #define BRW_NEW_DRAW_CALL (1ull << BRW_STATE_DRAW_CALL)
308 #define BRW_NEW_AUX_STATE (1ull << BRW_STATE_AUX)
310 struct brw_state_flags
{
311 /** State update flags signalled by mesa internals */
314 * State update flags signalled as the result of brw_tracked_state updates
320 /** Subclass of Mesa program */
322 struct gl_program program
;
329 struct brw_ff_gs_prog_data
{
330 GLuint urb_read_length
;
334 * Gen6 transform feedback: Amount by which the streaming vertex buffer
335 * indices should be incremented each time the GS is invoked.
337 unsigned svbi_postincrement_value
;
340 /** Number of texture sampler units */
341 #define BRW_MAX_TEX_UNIT 32
343 /** Max number of UBOs in a shader */
344 #define BRW_MAX_UBO 14
346 /** Max number of SSBOs in a shader */
347 #define BRW_MAX_SSBO 12
349 /** Max number of atomic counter buffer objects in a shader */
350 #define BRW_MAX_ABO 16
352 /** Max number of image uniforms in a shader */
353 #define BRW_MAX_IMAGES 32
355 /** Maximum number of actual buffers used for stream output */
356 #define BRW_MAX_SOL_BUFFERS 4
358 #define BRW_MAX_SURFACES (BRW_MAX_DRAW_BUFFERS + \
359 BRW_MAX_TEX_UNIT * 2 + /* normal, gather */ \
364 2 + /* shader time, pull constants */ \
365 1 /* cs num work groups */)
368 struct brw_context
*brw
;
370 struct brw_cache_item
**items
;
373 GLuint size
, n_items
;
375 uint32_t next_offset
;
378 /* Considered adding a member to this struct to document which flags
379 * an update might raise so that ordering of the state atoms can be
380 * checked or derived at runtime. Dropped the idea in favor of having
381 * a debug mode where the state is monitored for flags which are
382 * raised that have already been tested against.
384 struct brw_tracked_state
{
385 struct brw_state_flags dirty
;
386 void (*emit
)( struct brw_context
*brw
);
389 enum shader_time_shader_type
{
400 struct brw_vertex_buffer
{
401 /** Buffer object containing the uploaded vertex data */
405 /** Byte stride between elements in the uploaded array */
409 struct brw_vertex_element
{
410 const struct gl_vertex_array
*glarray
;
414 /** Offset of the first element within the buffer object */
418 struct brw_query_object
{
419 struct gl_query_object Base
;
421 /** Last query BO associated with this query. */
424 /** Last index in bo with query data for this object. */
427 /** True if we know the batch has been flushed since we ended the query. */
437 struct brw_reloc_list
{
438 struct drm_i915_gem_relocation_entry
*relocs
;
440 int reloc_array_size
;
443 struct intel_batchbuffer
{
444 /** Current batchbuffer being queued up. */
446 /** Last BO submitted to the hardware. Used for glFinish(). */
447 struct brw_bo
*last_bo
;
448 /** Current statebuffer being queued up. */
449 struct brw_bo
*state_bo
;
452 uint16_t emit
, total
;
454 uint16_t reserved_space
;
457 uint32_t *batch_cpu_map
;
458 uint32_t *state_cpu_map
;
462 enum brw_gpu_ring ring
;
463 bool use_batch_first
;
464 bool needs_sol_reset
;
465 bool state_base_address_emitted
;
468 struct brw_reloc_list batch_relocs
;
469 struct brw_reloc_list state_relocs
;
470 unsigned int valid_reloc_flags
;
472 /** The validation list */
473 struct drm_i915_gem_exec_object2
*validation_list
;
474 struct brw_bo
**exec_bos
;
478 /** The amount of aperture space (in bytes) used by all exec_bos */
483 int batch_reloc_count
;
484 int state_reloc_count
;
488 /** Map from batch offset to brw_state_batch data (with DEBUG_BATCH) */
489 struct hash_table
*state_batch_sizes
;
492 #define BRW_MAX_XFB_STREAMS 4
494 struct brw_transform_feedback_object
{
495 struct gl_transform_feedback_object base
;
497 /** A buffer to hold SO_WRITE_OFFSET(n) values while paused. */
498 struct brw_bo
*offset_bo
;
500 /** If true, SO_WRITE_OFFSET(n) should be reset to zero at next use. */
503 /** The most recent primitive mode (GL_TRIANGLES/GL_POINTS/GL_LINES). */
504 GLenum primitive_mode
;
507 * The maximum number of vertices that we can write without overflowing
508 * any of the buffers currently being used for transform feedback.
513 * Count of primitives generated during this transform feedback operation.
516 uint64_t prims_generated
[BRW_MAX_XFB_STREAMS
];
517 struct brw_bo
*prim_count_bo
;
518 unsigned prim_count_buffer_index
; /**< in number of uint64_t units */
522 * Number of vertices written between last Begin/EndTransformFeedback().
524 * Used to implement DrawTransformFeedback().
526 uint64_t vertices_written
[BRW_MAX_XFB_STREAMS
];
527 bool vertices_written_valid
;
531 * Data shared between each programmable stage in the pipeline (vs, gs, and
534 struct brw_stage_state
536 gl_shader_stage stage
;
537 struct brw_stage_prog_data
*prog_data
;
540 * Optional scratch buffer used to store spilled register values and
541 * variably-indexed GRF arrays.
543 * The contents of this buffer are short-lived so the same memory can be
544 * re-used at will for multiple shader programs (executed by the same fixed
545 * function). However reusing a scratch BO for which shader invocations
546 * are still in flight with a per-thread scratch slot size other than the
547 * original can cause threads with different scratch slot size and FFTID
548 * (which may be executed in parallel depending on the shader stage and
549 * hardware generation) to map to an overlapping region of the scratch
550 * space, which can potentially lead to mutual scratch space corruption.
551 * For that reason if you borrow this scratch buffer you should only be
552 * using the slot size given by the \c per_thread_scratch member below,
553 * unless you're taking additional measures to synchronize thread execution
554 * across slot size changes.
556 struct brw_bo
*scratch_bo
;
559 * Scratch slot size allocated for each thread in the buffer object given
562 uint32_t per_thread_scratch
;
564 /** Offset in the program cache to the program */
565 uint32_t prog_offset
;
567 /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */
568 uint32_t state_offset
;
570 struct brw_bo
*push_const_bo
; /* NULL if using the batchbuffer */
571 uint32_t push_const_offset
; /* Offset in the push constant BO or batch */
572 int push_const_size
; /* in 256-bit register increments */
574 /* Binding table: pointers to SURFACE_STATE entries. */
575 uint32_t bind_bo_offset
;
576 uint32_t surf_offset
[BRW_MAX_SURFACES
];
578 /** SAMPLER_STATE count and table offset */
579 uint32_t sampler_count
;
580 uint32_t sampler_offset
;
582 struct brw_image_param image_param
[BRW_MAX_IMAGES
];
584 /** Need to re-emit 3DSTATE_CONSTANT_XS? */
585 bool push_constants_dirty
;
588 enum brw_predicate_state
{
589 /* The first two states are used if we can determine whether to draw
590 * without having to look at the values in the query object buffer. This
591 * will happen if there is no conditional render in progress, if the query
592 * object is already completed or if something else has already added
593 * samples to the preliminary result such as via a BLT command.
595 BRW_PREDICATE_STATE_RENDER
,
596 BRW_PREDICATE_STATE_DONT_RENDER
,
597 /* In this case whether to draw or not depends on the result of an
598 * MI_PREDICATE command so the predicate enable bit needs to be checked.
600 BRW_PREDICATE_STATE_USE_BIT
,
601 /* In this case, either MI_PREDICATE doesn't exist or we lack the
602 * necessary kernel features to use it. Stall for the query result.
604 BRW_PREDICATE_STATE_STALL_FOR_QUERY
,
609 struct gen_l3_config
;
611 enum brw_query_kind
{
616 struct brw_perf_query_register_prog
{
621 struct brw_perf_query_info
623 enum brw_query_kind kind
;
626 struct brw_perf_query_counter
*counters
;
631 uint64_t oa_metrics_set_id
;
634 /* For indexing into the accumulator[] ... */
636 int gpu_clock_offset
;
641 /* Register programming for a given query */
642 struct brw_perf_query_register_prog
*flex_regs
;
643 uint32_t n_flex_regs
;
645 struct brw_perf_query_register_prog
*mux_regs
;
648 struct brw_perf_query_register_prog
*b_counter_regs
;
649 uint32_t n_b_counter_regs
;
653 * brw_context is derived from gl_context.
657 struct gl_context ctx
; /**< base class, must be first field */
662 * Send the appropriate state packets to configure depth, stencil, and
663 * HiZ buffers (i965+ only)
665 void (*emit_depth_stencil_hiz
)(struct brw_context
*brw
,
666 struct intel_mipmap_tree
*depth_mt
,
667 uint32_t depth_offset
,
668 uint32_t depthbuffer_format
,
669 uint32_t depth_surface_type
,
670 struct intel_mipmap_tree
*stencil_mt
,
671 bool hiz
, bool separate_stencil
,
672 uint32_t width
, uint32_t height
,
673 uint32_t tile_x
, uint32_t tile_y
);
676 * Emit an MI_REPORT_PERF_COUNT command packet.
678 * This asks the GPU to write a report of the current OA counter values
679 * into @bo at the given offset and containing the given @report_id
680 * which we can cross-reference when parsing the report (gen7+ only).
682 void (*emit_mi_report_perf_count
)(struct brw_context
*brw
,
684 uint32_t offset_in_bytes
,
688 struct brw_bufmgr
*bufmgr
;
692 /** BO for post-sync nonzero writes for gen6 workaround. */
693 struct brw_bo
*workaround_bo
;
694 uint8_t pipe_controls_since_last_cs_stall
;
697 * Set of struct brw_bo * that have been rendered to within this batchbuffer
698 * and would need flushing before being used from another cache domain that
699 * isn't coherent with it (i.e. the sampler).
701 struct set
*render_cache
;
704 * Set of struct brw_bo * that have been used as a depth buffer within this
705 * batchbuffer and would need flushing before being used from another cache
706 * domain that isn't coherent with it (i.e. the sampler).
708 struct set
*depth_cache
;
711 * Number of resets observed in the system at context creation.
713 * This is tracked in the context so that we can determine that another
714 * reset has occurred.
716 uint32_t reset_count
;
718 struct intel_batchbuffer batch
;
723 uint32_t next_offset
;
727 * Set if rendering has occurred to the drawable's front buffer.
729 * This is used in the DRI2 case to detect that glFlush should also copy
730 * the contents of the fake front buffer to the real front buffer.
732 bool front_buffer_dirty
;
734 /** Framerate throttling: @{ */
735 struct brw_bo
*throttle_batch
[2];
737 /* Limit the number of outstanding SwapBuffers by waiting for an earlier
738 * frame of rendering to complete. This gives a very precise cap to the
739 * latency between input and output such that rendering never gets more
740 * than a frame behind the user. (With the caveat that we technically are
741 * not using the SwapBuffers itself as a barrier but the first batch
742 * submitted afterwards, which may be immediately prior to the next
745 bool need_swap_throttle
;
747 /** General throttling, not caught by throttling between SwapBuffers */
748 bool need_flush_throttle
;
758 bool always_flush_batch
;
759 bool always_flush_cache
;
760 bool disable_throttling
;
762 bool dual_color_blend_by_location
;
764 driOptionCache optionCache
;
767 GLuint primitive
; /**< Hardware primitive, such as _3DPRIM_TRILIST. */
769 GLenum reduced_primitive
;
772 * Set if we're either a debug context or the INTEL_DEBUG=perf environment
773 * variable is set, this is the flag indicating to do expensive work that
774 * might lead to a perf_debug() call.
778 uint64_t max_gtt_map_object_size
;
781 bool has_separate_stencil
;
784 /** Derived stencil states. */
785 bool stencil_enabled
;
786 bool stencil_two_sided
;
787 bool stencil_write_enabled
;
788 /** Derived polygon state. */
789 bool polygon_front_bit
; /**< 0=GL_CCW, 1=GL_CW */
791 struct isl_device isl_dev
;
793 struct blorp_context blorp
;
797 struct brw_state_flags pipelines
[BRW_NUM_PIPELINES
];
800 enum brw_pipeline last_pipeline
;
802 struct brw_cache cache
;
804 /* Whether a meta-operation is in progress. */
805 bool meta_in_progress
;
807 /* Whether the last depth/stencil packets were both NULL. */
808 bool no_depth_or_stencil
;
810 /* The last PMA stall bits programmed. */
811 uint32_t pma_stall_bits
;
815 /** The value of gl_BaseVertex for the current _mesa_prim. */
818 /** The value of gl_BaseInstance for the current _mesa_prim. */
823 * Buffer and offset used for GL_ARB_shader_draw_parameters
824 * (for now, only gl_BaseVertex).
826 struct brw_bo
*draw_params_bo
;
827 uint32_t draw_params_offset
;
830 * The value of gl_DrawID for the current _mesa_prim. This always comes
831 * in from it's own vertex buffer since it's not part of the indirect
835 struct brw_bo
*draw_id_bo
;
836 uint32_t draw_id_offset
;
839 * Pointer to the the buffer storing the indirect draw parameters. It
840 * currently only stores the number of requested draw calls but more
841 * parameters could potentially be added.
843 struct brw_bo
*draw_params_count_bo
;
844 uint32_t draw_params_count_offset
;
849 * For gl_NumWorkGroups: If num_work_groups_bo is non NULL, then it is
850 * an indirect call, and num_work_groups_offset is valid. Otherwise,
851 * num_work_groups is set based on glDispatchCompute.
853 struct brw_bo
*num_work_groups_bo
;
854 GLintptr num_work_groups_offset
;
855 const GLuint
*num_work_groups
;
859 struct brw_vertex_element inputs
[VERT_ATTRIB_MAX
];
860 struct brw_vertex_buffer buffers
[VERT_ATTRIB_MAX
];
862 struct brw_vertex_element
*enabled
[VERT_ATTRIB_MAX
];
866 /* Summary of size and varying of active arrays, so we can check
867 * for changes to this state:
869 bool index_bounds_valid
;
870 unsigned int min_index
, max_index
;
872 /* Offset from start of vertex buffer so we can avoid redefining
873 * the same VB packed over and over again.
875 unsigned int start_vertex_bias
;
878 * Certain vertex attribute formats aren't natively handled by the
879 * hardware and require special VS code to fix up their values.
881 * These bitfields indicate which workarounds are needed.
883 uint8_t attrib_wa_flags
[VERT_ATTRIB_MAX
];
888 * Index buffer for this draw_prims call.
890 * Updates are signaled by BRW_NEW_INDICES.
892 const struct _mesa_index_buffer
*ib
;
894 /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */
899 /* Offset to index buffer index to use in CMD_3D_PRIM so that we can
900 * avoid re-uploading the IB packet over and over if we're actually
901 * referencing the same index buffer.
903 unsigned int start_vertex_offset
;
906 /* Active vertex program:
908 struct gl_program
*programs
[MESA_SHADER_STAGES
];
911 * Number of samples in ctx->DrawBuffer, updated by BRW_NEW_NUM_SAMPLES so
912 * that we don't have to reemit that state every time we change FBOs.
916 /* BRW_NEW_URB_ALLOCATIONS:
919 GLuint vsize
; /* vertex size plus header in urb registers */
920 GLuint gsize
; /* GS output size in urb registers */
921 GLuint hsize
; /* Tessellation control output size in urb registers */
922 GLuint dsize
; /* Tessellation evaluation output size in urb registers */
923 GLuint csize
; /* constant buffer size in urb registers */
924 GLuint sfsize
; /* setup data size in urb registers */
928 GLuint nr_vs_entries
;
929 GLuint nr_hs_entries
;
930 GLuint nr_ds_entries
;
931 GLuint nr_gs_entries
;
932 GLuint nr_clip_entries
;
933 GLuint nr_sf_entries
;
934 GLuint nr_cs_entries
;
944 * URB size in the current configuration. The units this is expressed
945 * in are somewhat inconsistent, see gen_device_info::urb::size.
947 * FINISHME: Represent the URB size consistently in KB on all platforms.
951 /* True if the most recently sent _3DSTATE_URB message allocated
952 * URB space for the GS.
956 /* True if the most recently sent _3DSTATE_URB message allocated
957 * URB space for the HS and DS.
963 /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
965 GLuint wm_start
; /**< pos of first wm const in CURBE buffer */
966 GLuint wm_size
; /**< number of float[4] consts, multiple of 16 */
974 * Pointer to the (intel_upload.c-generated) BO containing the uniforms
975 * for upload to the CURBE.
977 struct brw_bo
*curbe_bo
;
978 /** Offset within curbe_bo of space for current curbe entry */
983 * Layout of vertex data exiting the geometry portion of the pipleine.
984 * This comes from the last enabled shader stage (GS, DS, or VS).
986 * BRW_NEW_VUE_MAP_GEOM_OUT is flagged when the VUE map changes.
988 struct brw_vue_map vue_map_geom_out
;
991 struct brw_stage_state base
;
995 struct brw_stage_state base
;
999 struct brw_stage_state base
;
1003 struct brw_stage_state base
;
1006 * True if the 3DSTATE_GS command most recently emitted to the 3D
1007 * pipeline enabled the GS; false otherwise.
1013 struct brw_ff_gs_prog_data
*prog_data
;
1016 /** Offset in the program cache to the CLIP program pre-gen6 */
1017 uint32_t prog_offset
;
1018 uint32_t state_offset
;
1020 uint32_t bind_bo_offset
;
1022 * Surface offsets for the binding table. We only need surfaces to
1023 * implement transform feedback so BRW_MAX_SOL_BINDINGS is all that we
1024 * need in this case.
1026 uint32_t surf_offset
[BRW_MAX_SOL_BINDINGS
];
1030 struct brw_clip_prog_data
*prog_data
;
1032 /** Offset in the program cache to the CLIP program pre-gen6 */
1033 uint32_t prog_offset
;
1035 /* Offset in the batch to the CLIP state on pre-gen6. */
1036 uint32_t state_offset
;
1038 /* As of gen6, this is the offset in the batch to the CLIP VP,
1044 * The number of viewports to use. If gl_ViewportIndex is written,
1045 * we can have up to ctx->Const.MaxViewports viewports. If not,
1046 * the viewport index is always 0, so we can only emit one.
1048 uint8_t viewport_count
;
1053 struct brw_sf_prog_data
*prog_data
;
1055 /** Offset in the program cache to the CLIP program pre-gen6 */
1056 uint32_t prog_offset
;
1057 uint32_t state_offset
;
1062 struct brw_stage_state base
;
1065 * Buffer object used in place of multisampled null render targets on
1066 * Gen6. See brw_emit_null_surface_state().
1068 struct brw_bo
*multisampled_null_render_target_bo
;
1074 struct brw_stage_state base
;
1078 uint32_t state_offset
;
1079 uint32_t blend_state_offset
;
1080 uint32_t depth_stencil_state_offset
;
1085 struct brw_query_object
*obj
;
1090 enum brw_predicate_state state
;
1095 /* Variables referenced in the XML meta data for OA performance
1096 * counters, e.g in the normalization equations.
1098 * All uint64_t for consistent operand types in generated code
1101 uint64_t timestamp_frequency
; /** $GpuTimestampFrequency */
1102 uint64_t n_eus
; /** $EuCoresTotalCount */
1103 uint64_t n_eu_slices
; /** $EuSlicesTotalCount */
1104 uint64_t n_eu_sub_slices
; /** $EuSubslicesTotalCount */
1105 uint64_t eu_threads_count
; /** $EuThreadsCount */
1106 uint64_t slice_mask
; /** $SliceMask */
1107 uint64_t subslice_mask
; /** $SubsliceMask */
1108 uint64_t gt_min_freq
; /** $GpuMinFrequency */
1109 uint64_t gt_max_freq
; /** $GpuMaxFrequency */
1110 uint64_t revision
; /** $SkuRevisionId */
1113 /* OA metric sets, indexed by GUID, as know by Mesa at build time,
1114 * to cross-reference with the GUIDs of configs advertised by the
1117 struct hash_table
*oa_metrics_table
;
1119 struct brw_perf_query_info
*queries
;
1122 /* The i915 perf stream we open to setup + enable the OA counters */
1125 /* An i915 perf stream fd gives exclusive access to the OA unit that will
1126 * report counter snapshots for a specific counter set/profile in a
1127 * specific layout/format so we can only start OA queries that are
1128 * compatible with the currently open fd...
1130 int current_oa_metrics_set_id
;
1131 int current_oa_format
;
1133 /* List of buffers containing OA reports */
1134 struct exec_list sample_buffers
;
1136 /* Cached list of empty sample buffers */
1137 struct exec_list free_sample_buffers
;
1139 int n_active_oa_queries
;
1140 int n_active_pipeline_stats_queries
;
1142 /* The number of queries depending on running OA counters which
1143 * extends beyond brw_end_perf_query() since we need to wait until
1144 * the last MI_RPC command has parsed by the GPU.
1146 * Accurate accounting is important here as emitting an
1147 * MI_REPORT_PERF_COUNT command while the OA unit is disabled will
1148 * effectively hang the gpu.
1152 /* To help catch an spurious problem with the hardware or perf
1153 * forwarding samples, we emit each MI_REPORT_PERF_COUNT command
1154 * with a unique ID that we can explicitly check for...
1156 int next_query_start_report_id
;
1159 * An array of queries whose results haven't yet been assembled
1160 * based on the data in buffer objects.
1162 * These may be active, or have already ended. However, the
1163 * results have not been requested.
1165 struct brw_perf_query_object
**unaccumulated
;
1166 int unaccumulated_elements
;
1167 int unaccumulated_array_size
;
1169 /* The total number of query objects so we can relinquish
1170 * our exclusive access to perf if the application deletes
1171 * all of its objects. (NB: We only disable perf while
1172 * there are no active queries)
1174 int n_query_instances
;
1177 int num_atoms
[BRW_NUM_PIPELINES
];
1178 const struct brw_tracked_state render_atoms
[76];
1179 const struct brw_tracked_state compute_atoms
[11];
1181 const enum isl_format
*mesa_to_isl_render_format
;
1182 const bool *mesa_format_supports_render
;
1184 /* PrimitiveRestart */
1187 bool enable_cut_index
;
1190 /** Computed depth/stencil/hiz state from the current attached
1191 * renderbuffers, valid only during the drawing state upload loop after
1192 * brw_workaround_depthstencil_alignment().
1195 /* Inter-tile (page-aligned) byte offsets. */
1196 uint32_t depth_offset
;
1197 /* Intra-tile x,y offsets for drawing to combined depth-stencil. Only
1200 uint32_t tile_x
, tile_y
;
1203 uint32_t num_instances
;
1208 const struct gen_l3_config
*config
;
1215 enum shader_time_shader_type
*types
;
1216 struct shader_times
*cumulative
;
1222 struct brw_fast_clear_state
*fast_clear_state
;
1224 /* Array of flags telling if auxiliary buffer is disabled for corresponding
1225 * renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
1226 * auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
1228 * This is needed in case the same underlying buffer is also configured
1229 * to be sampled but with a format that the sampling engine can't treat
1230 * compressed or fast cleared.
1232 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
];
1234 __DRIcontext
*driContext
;
1235 struct intel_screen
*screen
;
1239 extern void intelInitClearFuncs(struct dd_function_table
*functions
);
1241 /*======================================================================
1244 extern const char *const brw_vendor_string
;
1247 brw_get_renderer_string(const struct intel_screen
*screen
);
1250 DRI_CONF_BO_REUSE_DISABLED
,
1251 DRI_CONF_BO_REUSE_ALL
1254 void intel_update_renderbuffers(__DRIcontext
*context
,
1255 __DRIdrawable
*drawable
);
1256 void intel_prepare_render(struct brw_context
*brw
);
1258 void brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
);
1260 void intel_resolve_for_dri2_flush(struct brw_context
*brw
,
1261 __DRIdrawable
*drawable
);
1263 GLboolean
brwCreateContext(gl_api api
,
1264 const struct gl_config
*mesaVis
,
1265 __DRIcontext
*driContextPriv
,
1266 const struct __DriverContextConfig
*ctx_config
,
1268 void *sharedContextPrivate
);
1270 /*======================================================================
1274 brw_meta_resolve_color(struct brw_context
*brw
,
1275 struct intel_mipmap_tree
*mt
);
1277 /*======================================================================
1280 void brw_workaround_depthstencil_alignment(struct brw_context
*brw
,
1281 GLbitfield clear_mask
);
1283 /* brw_object_purgeable.c */
1284 void brw_init_object_purgeable_functions(struct dd_function_table
*functions
);
1286 /*======================================================================
1289 void brw_init_common_queryobj_functions(struct dd_function_table
*functions
);
1290 void gen4_init_queryobj_functions(struct dd_function_table
*functions
);
1291 void brw_emit_query_begin(struct brw_context
*brw
);
1292 void brw_emit_query_end(struct brw_context
*brw
);
1293 void brw_query_counter(struct gl_context
*ctx
, struct gl_query_object
*q
);
1294 bool brw_is_query_pipelined(struct brw_query_object
*query
);
1295 uint64_t brw_timebase_scale(struct brw_context
*brw
, uint64_t gpu_timestamp
);
1296 uint64_t brw_raw_timestamp_delta(struct brw_context
*brw
,
1297 uint64_t time0
, uint64_t time1
);
1299 /** gen6_queryobj.c */
1300 void gen6_init_queryobj_functions(struct dd_function_table
*functions
);
1301 void brw_write_timestamp(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1302 void brw_write_depth_count(struct brw_context
*brw
, struct brw_bo
*bo
, int idx
);
1304 /** hsw_queryobj.c */
1305 void hsw_overflow_result_to_gpr0(struct brw_context
*brw
,
1306 struct brw_query_object
*query
,
1308 void hsw_init_queryobj_functions(struct dd_function_table
*functions
);
1310 /** brw_conditional_render.c */
1311 void brw_init_conditional_render_functions(struct dd_function_table
*functions
);
1312 bool brw_check_conditional_render(struct brw_context
*brw
);
1314 /** intel_batchbuffer.c */
1315 void brw_load_register_mem(struct brw_context
*brw
,
1319 void brw_load_register_mem64(struct brw_context
*brw
,
1323 void brw_store_register_mem32(struct brw_context
*brw
,
1324 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1325 void brw_store_register_mem64(struct brw_context
*brw
,
1326 struct brw_bo
*bo
, uint32_t reg
, uint32_t offset
);
1327 void brw_load_register_imm32(struct brw_context
*brw
,
1328 uint32_t reg
, uint32_t imm
);
1329 void brw_load_register_imm64(struct brw_context
*brw
,
1330 uint32_t reg
, uint64_t imm
);
1331 void brw_load_register_reg(struct brw_context
*brw
, uint32_t src
,
1333 void brw_load_register_reg64(struct brw_context
*brw
, uint32_t src
,
1335 void brw_store_data_imm32(struct brw_context
*brw
, struct brw_bo
*bo
,
1336 uint32_t offset
, uint32_t imm
);
1337 void brw_store_data_imm64(struct brw_context
*brw
, struct brw_bo
*bo
,
1338 uint32_t offset
, uint64_t imm
);
1340 /*======================================================================
1341 * intel_tex_validate.c
1343 void brw_validate_textures( struct brw_context
*brw
);
1346 /*======================================================================
1350 key_debug(struct brw_context
*brw
, const char *name
, int a
, int b
)
1353 perf_debug(" %s %d->%d\n", name
, a
, b
);
1359 void brwInitFragProgFuncs( struct dd_function_table
*functions
);
1361 void brw_get_scratch_bo(struct brw_context
*brw
,
1362 struct brw_bo
**scratch_bo
, int size
);
1363 void brw_alloc_stage_scratch(struct brw_context
*brw
,
1364 struct brw_stage_state
*stage_state
,
1365 unsigned per_thread_size
);
1366 void brw_init_shader_time(struct brw_context
*brw
);
1367 int brw_get_shader_time_index(struct brw_context
*brw
,
1368 struct gl_program
*prog
,
1369 enum shader_time_shader_type type
,
1371 void brw_collect_and_report_shader_time(struct brw_context
*brw
);
1372 void brw_destroy_shader_time(struct brw_context
*brw
);
1376 void brw_calculate_urb_fence(struct brw_context
*brw
, unsigned csize
,
1377 unsigned vsize
, unsigned sfsize
);
1378 void brw_upload_urb_fence(struct brw_context
*brw
);
1382 void brw_upload_cs_urb_state(struct brw_context
*brw
);
1385 gl_clip_plane
*brw_select_clip_planes(struct gl_context
*ctx
);
1387 /* brw_draw_upload.c */
1388 unsigned brw_get_vertex_surface_type(struct brw_context
*brw
,
1389 const struct gl_vertex_array
*glarray
);
1391 static inline unsigned
1392 brw_get_index_type(unsigned index_size
)
1394 /* The hw needs 0x00, 0x01, and 0x02 for ubyte, ushort, and uint,
1397 return index_size
>> 1;
1400 void brw_prepare_vertices(struct brw_context
*brw
);
1402 /* brw_wm_surface_state.c */
1403 void brw_update_buffer_texture_surface(struct gl_context
*ctx
,
1405 uint32_t *surf_offset
);
1407 brw_update_sol_surface(struct brw_context
*brw
,
1408 struct gl_buffer_object
*buffer_obj
,
1409 uint32_t *out_offset
, unsigned num_vector_components
,
1410 unsigned stride_dwords
, unsigned offset_dwords
);
1411 void brw_upload_ubo_surfaces(struct brw_context
*brw
, struct gl_program
*prog
,
1412 struct brw_stage_state
*stage_state
,
1413 struct brw_stage_prog_data
*prog_data
);
1414 void brw_upload_image_surfaces(struct brw_context
*brw
,
1415 const struct gl_program
*prog
,
1416 struct brw_stage_state
*stage_state
,
1417 struct brw_stage_prog_data
*prog_data
);
1419 /* brw_surface_formats.c */
1420 void intel_screen_init_surface_formats(struct intel_screen
*screen
);
1421 void brw_init_surface_formats(struct brw_context
*brw
);
1422 bool brw_render_target_supported(struct brw_context
*brw
,
1423 struct gl_renderbuffer
*rb
);
1424 uint32_t brw_depth_format(struct brw_context
*brw
, mesa_format format
);
1426 /* brw_performance_query.c */
1427 void brw_init_performance_queries(struct brw_context
*brw
);
1429 /* intel_extensions.c */
1430 extern void intelInitExtensions(struct gl_context
*ctx
);
1433 extern int intel_translate_shadow_compare_func(GLenum func
);
1434 extern int intel_translate_compare_func(GLenum func
);
1435 extern int intel_translate_stencil_op(GLenum op
);
1436 extern int intel_translate_logic_op(GLenum opcode
);
1439 void brw_init_syncobj_functions(struct dd_function_table
*functions
);
1442 struct gl_transform_feedback_object
*
1443 brw_new_transform_feedback(struct gl_context
*ctx
, GLuint name
);
1445 brw_delete_transform_feedback(struct gl_context
*ctx
,
1446 struct gl_transform_feedback_object
*obj
);
1448 brw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1449 struct gl_transform_feedback_object
*obj
);
1451 brw_end_transform_feedback(struct gl_context
*ctx
,
1452 struct gl_transform_feedback_object
*obj
);
1454 brw_pause_transform_feedback(struct gl_context
*ctx
,
1455 struct gl_transform_feedback_object
*obj
);
1457 brw_resume_transform_feedback(struct gl_context
*ctx
,
1458 struct gl_transform_feedback_object
*obj
);
1460 brw_save_primitives_written_counters(struct brw_context
*brw
,
1461 struct brw_transform_feedback_object
*obj
);
1463 brw_compute_xfb_vertices_written(struct brw_context
*brw
,
1464 struct brw_transform_feedback_object
*obj
);
1466 brw_get_transform_feedback_vertex_count(struct gl_context
*ctx
,
1467 struct gl_transform_feedback_object
*obj
,
1470 /* gen7_sol_state.c */
1472 gen7_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1473 struct gl_transform_feedback_object
*obj
);
1475 gen7_end_transform_feedback(struct gl_context
*ctx
,
1476 struct gl_transform_feedback_object
*obj
);
1478 gen7_pause_transform_feedback(struct gl_context
*ctx
,
1479 struct gl_transform_feedback_object
*obj
);
1481 gen7_resume_transform_feedback(struct gl_context
*ctx
,
1482 struct gl_transform_feedback_object
*obj
);
1486 hsw_begin_transform_feedback(struct gl_context
*ctx
, GLenum mode
,
1487 struct gl_transform_feedback_object
*obj
);
1489 hsw_end_transform_feedback(struct gl_context
*ctx
,
1490 struct gl_transform_feedback_object
*obj
);
1492 hsw_pause_transform_feedback(struct gl_context
*ctx
,
1493 struct gl_transform_feedback_object
*obj
);
1495 hsw_resume_transform_feedback(struct gl_context
*ctx
,
1496 struct gl_transform_feedback_object
*obj
);
1498 /* brw_blorp_blit.cpp */
1500 brw_blorp_framebuffer(struct brw_context
*brw
,
1501 struct gl_framebuffer
*readFb
,
1502 struct gl_framebuffer
*drawFb
,
1503 GLint srcX0
, GLint srcY0
, GLint srcX1
, GLint srcY1
,
1504 GLint dstX0
, GLint dstY0
, GLint dstX1
, GLint dstY1
,
1505 GLbitfield mask
, GLenum filter
);
1508 brw_blorp_copytexsubimage(struct brw_context
*brw
,
1509 struct gl_renderbuffer
*src_rb
,
1510 struct gl_texture_image
*dst_image
,
1512 int srcX0
, int srcY0
,
1513 int dstX0
, int dstY0
,
1514 int width
, int height
);
1517 gen6_get_sample_position(struct gl_context
*ctx
,
1518 struct gl_framebuffer
*fb
,
1522 gen6_set_sample_maps(struct gl_context
*ctx
);
1524 /* gen8_multisample_state.c */
1525 void gen8_emit_3dstate_sample_pattern(struct brw_context
*brw
);
1529 gen7_emit_push_constant_state(struct brw_context
*brw
, unsigned vs_size
,
1530 unsigned hs_size
, unsigned ds_size
,
1531 unsigned gs_size
, unsigned fs_size
);
1534 gen6_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1535 bool gs_present
, unsigned gs_size
);
1537 gen7_upload_urb(struct brw_context
*brw
, unsigned vs_size
,
1538 bool gs_present
, bool tess_present
);
1542 brw_get_graphics_reset_status(struct gl_context
*ctx
);
1544 brw_check_for_reset(struct brw_context
*brw
);
1548 brw_init_compute_functions(struct dd_function_table
*functions
);
1550 /*======================================================================
1551 * Inline conversion functions. These are better-typed than the
1552 * macros used previously:
1554 static inline struct brw_context
*
1555 brw_context( struct gl_context
*ctx
)
1557 return (struct brw_context
*)ctx
;
1560 static inline struct brw_program
*
1561 brw_program(struct gl_program
*p
)
1563 return (struct brw_program
*) p
;
1566 static inline const struct brw_program
*
1567 brw_program_const(const struct gl_program
*p
)
1569 return (const struct brw_program
*) p
;
1573 brw_depth_writes_enabled(const struct brw_context
*brw
)
1575 const struct gl_context
*ctx
= &brw
->ctx
;
1577 /* We consider depth writes disabled if the depth function is GL_EQUAL,
1578 * because it would just overwrite the existing depth value with itself.
1580 * These bonus depth writes not only use bandwidth, but they also can
1581 * prevent early depth processing. For example, if the pixel shader
1582 * discards, the hardware must invoke the to determine whether or not
1583 * to do the depth write. If writes are disabled, we may still be able
1584 * to do the depth test before the shader, and skip the shader execution.
1586 * The Broadwell 3DSTATE_WM_DEPTH_STENCIL documentation also contains
1587 * a programming note saying to disable depth writes for EQUAL.
1589 return ctx
->Depth
.Test
&& ctx
->Depth
.Mask
&& ctx
->Depth
.Func
!= GL_EQUAL
;
1593 brw_emit_depthbuffer(struct brw_context
*brw
);
1596 brw_emit_depth_stencil_hiz(struct brw_context
*brw
,
1597 struct intel_mipmap_tree
*depth_mt
,
1598 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1599 uint32_t depth_surface_type
,
1600 struct intel_mipmap_tree
*stencil_mt
,
1601 bool hiz
, bool separate_stencil
,
1602 uint32_t width
, uint32_t height
,
1603 uint32_t tile_x
, uint32_t tile_y
);
1606 gen6_emit_depth_stencil_hiz(struct brw_context
*brw
,
1607 struct intel_mipmap_tree
*depth_mt
,
1608 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1609 uint32_t depth_surface_type
,
1610 struct intel_mipmap_tree
*stencil_mt
,
1611 bool hiz
, bool separate_stencil
,
1612 uint32_t width
, uint32_t height
,
1613 uint32_t tile_x
, uint32_t tile_y
);
1616 gen7_emit_depth_stencil_hiz(struct brw_context
*brw
,
1617 struct intel_mipmap_tree
*depth_mt
,
1618 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1619 uint32_t depth_surface_type
,
1620 struct intel_mipmap_tree
*stencil_mt
,
1621 bool hiz
, bool separate_stencil
,
1622 uint32_t width
, uint32_t height
,
1623 uint32_t tile_x
, uint32_t tile_y
);
1625 gen8_emit_depth_stencil_hiz(struct brw_context
*brw
,
1626 struct intel_mipmap_tree
*depth_mt
,
1627 uint32_t depth_offset
, uint32_t depthbuffer_format
,
1628 uint32_t depth_surface_type
,
1629 struct intel_mipmap_tree
*stencil_mt
,
1630 bool hiz
, bool separate_stencil
,
1631 uint32_t width
, uint32_t height
,
1632 uint32_t tile_x
, uint32_t tile_y
);
1634 uint32_t get_hw_prim_for_gl_prim(int mode
);
1637 gen6_upload_push_constants(struct brw_context
*brw
,
1638 const struct gl_program
*prog
,
1639 const struct brw_stage_prog_data
*prog_data
,
1640 struct brw_stage_state
*stage_state
);
1643 gen9_use_linear_1d_layout(const struct brw_context
*brw
,
1644 const struct intel_mipmap_tree
*mt
);
1646 /* brw_pipe_control.c */
1647 int brw_init_pipe_control(struct brw_context
*brw
,
1648 const struct gen_device_info
*info
);
1649 void brw_fini_pipe_control(struct brw_context
*brw
);
1651 void brw_emit_pipe_control_flush(struct brw_context
*brw
, uint32_t flags
);
1652 void brw_emit_pipe_control_write(struct brw_context
*brw
, uint32_t flags
,
1653 struct brw_bo
*bo
, uint32_t offset
,
1655 void brw_emit_end_of_pipe_sync(struct brw_context
*brw
, uint32_t flags
);
1656 void brw_emit_mi_flush(struct brw_context
*brw
);
1657 void brw_emit_post_sync_nonzero_flush(struct brw_context
*brw
);
1658 void brw_emit_depth_stall_flushes(struct brw_context
*brw
);
1659 void gen7_emit_vs_workaround_flush(struct brw_context
*brw
);
1660 void gen7_emit_cs_stall_flush(struct brw_context
*brw
);
1662 /* brw_queryformat.c */
1663 void brw_query_internal_format(struct gl_context
*ctx
, GLenum target
,
1664 GLenum internalFormat
, GLenum pname
,