2 * Copyright © 2013 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "brw_device_info.h"
28 static const struct brw_device_info brw_device_info_i965
= {
30 .has_negative_rhw_bug
= true,
34 .max_wm_threads
= 8 * 4,
40 static const struct brw_device_info brw_device_info_g4x
= {
44 .has_surface_tile_offset
= true,
49 .max_wm_threads
= 10 * 5,
55 static const struct brw_device_info brw_device_info_ilk
= {
59 .has_surface_tile_offset
= true,
63 .max_wm_threads
= 12 * 6,
69 static const struct brw_device_info brw_device_info_snb_gt1
= {
72 .has_hiz_and_separate_stencil
= true,
75 .has_surface_tile_offset
= true,
76 .needs_unlit_centroid_workaround
= true,
79 .max_gs_threads
= 21, /* conservative; 24 if rendering disabled. */
84 .max_vs_entries
= 256,
85 .max_gs_entries
= 256,
89 static const struct brw_device_info brw_device_info_snb_gt2
= {
92 .has_hiz_and_separate_stencil
= true,
95 .has_surface_tile_offset
= true,
96 .needs_unlit_centroid_workaround
= true,
100 .max_wm_threads
= 80,
103 .min_vs_entries
= 24,
104 .max_vs_entries
= 256,
105 .max_gs_entries
= 256,
109 #define GEN7_FEATURES \
111 .has_hiz_and_separate_stencil = true, \
112 .must_use_separate_stencil = true, \
115 .has_surface_tile_offset = true
117 static const struct brw_device_info brw_device_info_ivb_gt1
= {
118 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 1,
119 .needs_unlit_centroid_workaround
= true,
121 .max_vs_threads
= 36,
122 .max_hs_threads
= 36,
123 .max_ds_threads
= 36,
124 .max_gs_threads
= 36,
125 .max_wm_threads
= 48,
126 .max_cs_threads
= 36,
129 .min_vs_entries
= 32,
130 .max_vs_entries
= 512,
131 .max_hs_entries
= 32,
132 .min_ds_entries
= 10,
133 .max_ds_entries
= 288,
134 .max_gs_entries
= 192,
138 static const struct brw_device_info brw_device_info_ivb_gt2
= {
139 GEN7_FEATURES
, .is_ivybridge
= true, .gt
= 2,
140 .needs_unlit_centroid_workaround
= true,
142 .max_vs_threads
= 128,
143 .max_hs_threads
= 128,
144 .max_ds_threads
= 128,
145 .max_gs_threads
= 128,
146 .max_wm_threads
= 172,
147 .max_cs_threads
= 64,
150 .min_vs_entries
= 32,
151 .max_vs_entries
= 704,
152 .max_hs_entries
= 64,
153 .min_ds_entries
= 10,
154 .max_ds_entries
= 448,
155 .max_gs_entries
= 320,
159 static const struct brw_device_info brw_device_info_byt
= {
160 GEN7_FEATURES
, .is_baytrail
= true, .gt
= 1,
161 .needs_unlit_centroid_workaround
= true,
164 .max_vs_threads
= 36,
165 .max_hs_threads
= 36,
166 .max_ds_threads
= 36,
167 .max_gs_threads
= 36,
168 .max_wm_threads
= 48,
169 .max_cs_threads
= 32,
172 .min_vs_entries
= 32,
173 .max_vs_entries
= 512,
174 .max_hs_entries
= 32,
175 .min_ds_entries
= 10,
176 .max_ds_entries
= 288,
177 .max_gs_entries
= 192,
181 #define HSW_FEATURES \
183 .is_haswell = true, \
184 .supports_simd16_3src = true, \
185 .has_resource_streamer = true
187 static const struct brw_device_info brw_device_info_hsw_gt1
= {
188 HSW_FEATURES
, .gt
= 1,
190 .max_vs_threads
= 70,
191 .max_hs_threads
= 70,
192 .max_ds_threads
= 70,
193 .max_gs_threads
= 70,
194 .max_wm_threads
= 102,
195 .max_cs_threads
= 70,
198 .min_vs_entries
= 32,
199 .max_vs_entries
= 640,
200 .max_hs_entries
= 64,
201 .min_ds_entries
= 10,
202 .max_ds_entries
= 384,
203 .max_gs_entries
= 256,
207 static const struct brw_device_info brw_device_info_hsw_gt2
= {
208 HSW_FEATURES
, .gt
= 2,
210 .max_vs_threads
= 280,
211 .max_hs_threads
= 256,
212 .max_ds_threads
= 280,
213 .max_gs_threads
= 256,
214 .max_wm_threads
= 204,
215 .max_cs_threads
= 70,
218 .min_vs_entries
= 64,
219 .max_vs_entries
= 1664,
220 .max_hs_entries
= 128,
221 .min_ds_entries
= 10,
222 .max_ds_entries
= 960,
223 .max_gs_entries
= 640,
227 static const struct brw_device_info brw_device_info_hsw_gt3
= {
228 HSW_FEATURES
, .gt
= 3,
230 .max_vs_threads
= 280,
231 .max_hs_threads
= 256,
232 .max_ds_threads
= 280,
233 .max_gs_threads
= 256,
234 .max_wm_threads
= 408,
235 .max_cs_threads
= 70,
238 .min_vs_entries
= 64,
239 .max_vs_entries
= 1664,
240 .max_hs_entries
= 128,
241 .min_ds_entries
= 10,
242 .max_ds_entries
= 960,
243 .max_gs_entries
= 640,
247 #define GEN8_FEATURES \
249 .has_hiz_and_separate_stencil = true, \
250 .has_resource_streamer = true, \
251 .must_use_separate_stencil = true, \
254 .supports_simd16_3src = true, \
255 .max_vs_threads = 504, \
256 .max_hs_threads = 504, \
257 .max_ds_threads = 504, \
258 .max_gs_threads = 504, \
259 .max_wm_threads = 384
261 static const struct brw_device_info brw_device_info_bdw_gt1
= {
262 GEN8_FEATURES
, .gt
= 1,
264 .max_cs_threads
= 42,
267 .min_vs_entries
= 64,
268 .max_vs_entries
= 2560,
269 .max_hs_entries
= 504,
270 .min_ds_entries
= 34,
271 .max_ds_entries
= 1536,
272 .max_gs_entries
= 960,
276 static const struct brw_device_info brw_device_info_bdw_gt2
= {
277 GEN8_FEATURES
, .gt
= 2,
279 .max_cs_threads
= 56,
282 .min_vs_entries
= 64,
283 .max_vs_entries
= 2560,
284 .max_hs_entries
= 504,
285 .min_ds_entries
= 34,
286 .max_ds_entries
= 1536,
287 .max_gs_entries
= 960,
291 static const struct brw_device_info brw_device_info_bdw_gt3
= {
292 GEN8_FEATURES
, .gt
= 3,
294 .max_cs_threads
= 56,
297 .min_vs_entries
= 64,
298 .max_vs_entries
= 2560,
299 .max_hs_entries
= 504,
300 .min_ds_entries
= 34,
301 .max_ds_entries
= 1536,
302 .max_gs_entries
= 960,
306 static const struct brw_device_info brw_device_info_chv
= {
307 GEN8_FEATURES
, .is_cherryview
= 1, .gt
= 1,
310 .max_vs_threads
= 80,
311 .max_hs_threads
= 80,
312 .max_ds_threads
= 80,
313 .max_gs_threads
= 80,
314 .max_wm_threads
= 128,
315 .max_cs_threads
= 6 * 7,
318 .min_vs_entries
= 34,
319 .max_vs_entries
= 640,
320 .max_hs_entries
= 80,
321 .min_ds_entries
= 34,
322 .max_ds_entries
= 384,
323 .max_gs_entries
= 256,
327 #define GEN9_FEATURES \
329 .has_hiz_and_separate_stencil = true, \
330 .has_resource_streamer = true, \
331 .must_use_separate_stencil = true, \
334 .supports_simd16_3src = true, \
335 .max_vs_threads = 336, \
336 .max_gs_threads = 336, \
337 .max_hs_threads = 336, \
338 .max_ds_threads = 336, \
339 .max_wm_threads = 64 * 9, \
340 .max_cs_threads = 56, \
343 .min_vs_entries = 64, \
344 .max_vs_entries = 1856, \
345 .max_hs_entries = 672, \
346 .min_ds_entries = 34, \
347 .max_ds_entries = 1120, \
348 .max_gs_entries = 640, \
351 static const struct brw_device_info brw_device_info_skl_gt1
= {
352 GEN9_FEATURES
, .gt
= 1,
357 static const struct brw_device_info brw_device_info_skl_gt2
= {
358 GEN9_FEATURES
, .gt
= 2,
362 static const struct brw_device_info brw_device_info_skl_gt3
= {
363 GEN9_FEATURES
, .gt
= 3,
367 static const struct brw_device_info brw_device_info_skl_gt4
= {
368 GEN9_FEATURES
, .gt
= 4,
370 /* From the "L3 Allocation and Programming" documentation:
372 * "URB is limited to 1008KB due to programming restrictions. This is not a
373 * restriction of the L3 implementation, but of the FF and other clients.
374 * Therefore, in a GT4 implementation it is possible for the programmed
375 * allocation of the L3 data array to provide 3*384KB=1152KB for URB, but
376 * only 1008KB of this will be used."
378 .urb
.size
= 1008 / 3,
381 static const struct brw_device_info brw_device_info_bxt
= {
388 .max_vs_threads
= 112,
389 .max_hs_threads
= 112,
390 .max_ds_threads
= 112,
391 .max_gs_threads
= 112,
392 .max_wm_threads
= 64 * 3,
393 .max_cs_threads
= 6 * 6,
396 .min_vs_entries
= 34,
397 .max_vs_entries
= 704,
398 .max_hs_entries
= 256,
399 .max_ds_entries
= 416,
400 .max_gs_entries
= 256,
405 * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
406 * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
410 * Both SKL and KBL support a maximum of 64 threads per
411 * Pixel Shader Dispatch (PSD) unit.
413 #define KBL_MAX_THREADS_PER_PSD 64
415 static const struct brw_device_info brw_device_info_kbl_gt1
= {
419 .max_cs_threads
= 7 * 6,
420 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 2,
425 static const struct brw_device_info brw_device_info_kbl_gt1_5
= {
429 .max_cs_threads
= 7 * 6,
430 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 3,
434 static const struct brw_device_info brw_device_info_kbl_gt2
= {
438 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 3,
442 static const struct brw_device_info brw_device_info_kbl_gt3
= {
446 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 6,
450 static const struct brw_device_info brw_device_info_kbl_gt4
= {
454 .max_wm_threads
= KBL_MAX_THREADS_PER_PSD
* 9,
456 * From the "L3 Allocation and Programming" documentation:
458 * "URB is limited to 1008KB due to programming restrictions. This
459 * is not a restriction of the L3 implementation, but of the FF and
460 * other clients. Therefore, in a GT4 implementation it is
461 * possible for the programmed allocation of the L3 data array to
462 * provide 3*384KB=1152KB for URB, but only 1008KB of this
465 .urb
.size
= 1008 / 3,
469 const struct brw_device_info
*
470 brw_get_device_info(int devid
)
472 const struct brw_device_info
*devinfo
;
475 #define CHIPSET(id, family, name) \
476 case id: devinfo = &brw_device_info_##family; break;
477 #include "pci_ids/i965_pci_ids.h"
479 fprintf(stderr
, "i965_dri.so does not support the 0x%x PCI ID.\n", devid
);
487 brw_get_device_name(int devid
)
491 #define CHIPSET(id, family, name) case id: return name;
492 #include "pci_ids/i965_pci_ids.h"