2 * Copyright 2003 VMware, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include <sys/errno.h>
28 #include "main/arrayobj.h"
29 #include "main/blend.h"
30 #include "main/context.h"
31 #include "main/condrender.h"
32 #include "main/samplerobj.h"
33 #include "main/state.h"
34 #include "main/enums.h"
35 #include "main/macros.h"
36 #include "main/transformfeedback.h"
37 #include "main/framebuffer.h"
38 #include "main/varray.h"
41 #include "swrast/swrast.h"
42 #include "swrast_setup/swrast_setup.h"
43 #include "drivers/common/meta.h"
44 #include "util/bitscan.h"
45 #include "util/bitset.h"
47 #include "brw_blorp.h"
49 #include "brw_defines.h"
50 #include "compiler/brw_eu_defines.h"
51 #include "brw_context.h"
52 #include "brw_state.h"
54 #include "intel_batchbuffer.h"
55 #include "intel_buffers.h"
56 #include "intel_fbo.h"
57 #include "intel_mipmap_tree.h"
58 #include "intel_buffer_objects.h"
60 #define FILE_DEBUG_FLAG DEBUG_PRIMS
63 static const GLenum reduced_prim
[GL_POLYGON
+1] = {
64 [GL_POINTS
] = GL_POINTS
,
65 [GL_LINES
] = GL_LINES
,
66 [GL_LINE_LOOP
] = GL_LINES
,
67 [GL_LINE_STRIP
] = GL_LINES
,
68 [GL_TRIANGLES
] = GL_TRIANGLES
,
69 [GL_TRIANGLE_STRIP
] = GL_TRIANGLES
,
70 [GL_TRIANGLE_FAN
] = GL_TRIANGLES
,
71 [GL_QUADS
] = GL_TRIANGLES
,
72 [GL_QUAD_STRIP
] = GL_TRIANGLES
,
73 [GL_POLYGON
] = GL_TRIANGLES
76 /* When the primitive changes, set a state bit and re-validate. Not
77 * the nicest and would rather deal with this by having all the
78 * programs be immune to the active primitive (ie. cope with all
79 * possibilities). That may not be realistic however.
82 brw_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
84 struct gl_context
*ctx
= &brw
->ctx
;
85 uint32_t hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
87 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
89 /* Slight optimization to avoid the GS program when not needed:
91 if (prim
->mode
== GL_QUAD_STRIP
&&
92 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
93 ctx
->Polygon
.FrontMode
== GL_FILL
&&
94 ctx
->Polygon
.BackMode
== GL_FILL
)
95 hw_prim
= _3DPRIM_TRISTRIP
;
97 if (prim
->mode
== GL_QUADS
&& prim
->count
== 4 &&
98 ctx
->Light
.ShadeModel
!= GL_FLAT
&&
99 ctx
->Polygon
.FrontMode
== GL_FILL
&&
100 ctx
->Polygon
.BackMode
== GL_FILL
) {
101 hw_prim
= _3DPRIM_TRIFAN
;
104 if (hw_prim
!= brw
->primitive
) {
105 brw
->primitive
= hw_prim
;
106 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
108 if (reduced_prim
[prim
->mode
] != brw
->reduced_primitive
) {
109 brw
->reduced_primitive
= reduced_prim
[prim
->mode
];
110 brw
->ctx
.NewDriverState
|= BRW_NEW_REDUCED_PRIMITIVE
;
116 gen6_set_prim(struct brw_context
*brw
, const struct _mesa_prim
*prim
)
118 const struct gl_context
*ctx
= &brw
->ctx
;
121 DBG("PRIM: %s\n", _mesa_enum_to_string(prim
->mode
));
123 if (prim
->mode
== GL_PATCHES
) {
124 hw_prim
= _3DPRIM_PATCHLIST(ctx
->TessCtrlProgram
.patch_vertices
);
126 hw_prim
= get_hw_prim_for_gl_prim(prim
->mode
);
129 if (hw_prim
!= brw
->primitive
) {
130 brw
->primitive
= hw_prim
;
131 brw
->ctx
.NewDriverState
|= BRW_NEW_PRIMITIVE
;
132 if (prim
->mode
== GL_PATCHES
)
133 brw
->ctx
.NewDriverState
|= BRW_NEW_PATCH_PRIMITIVE
;
139 * The hardware is capable of removing dangling vertices on its own; however,
140 * prior to Gen6, we sometimes convert quads into trifans (and quad strips
141 * into tristrips), since pre-Gen6 hardware requires a GS to render quads.
142 * This function manually trims dangling vertices from a draw call involving
143 * quads so that those dangling vertices won't get drawn when we convert to
147 trim(GLenum prim
, GLuint length
)
149 if (prim
== GL_QUAD_STRIP
)
150 return length
> 3 ? (length
- length
% 2) : 0;
151 else if (prim
== GL_QUADS
)
152 return length
- length
% 4;
159 brw_emit_prim(struct brw_context
*brw
,
160 const struct _mesa_prim
*prim
,
163 struct brw_transform_feedback_object
*xfb_obj
,
166 GLsizeiptr indirect_offset
)
168 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
169 int verts_per_instance
;
170 int vertex_access_type
;
173 DBG("PRIM: %s %d %d\n", _mesa_enum_to_string(prim
->mode
),
174 prim
->start
, prim
->count
);
176 int start_vertex_location
= prim
->start
;
177 int base_vertex_location
= prim
->basevertex
;
180 vertex_access_type
= devinfo
->gen
>= 7 ?
181 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
:
182 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM
;
183 start_vertex_location
+= brw
->ib
.start_vertex_offset
;
184 base_vertex_location
+= brw
->vb
.start_vertex_bias
;
186 vertex_access_type
= devinfo
->gen
>= 7 ?
187 GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
:
188 GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL
;
189 start_vertex_location
+= brw
->vb
.start_vertex_bias
;
192 /* We only need to trim the primitive count on pre-Gen6. */
193 if (devinfo
->gen
< 6)
194 verts_per_instance
= trim(prim
->mode
, prim
->count
);
196 verts_per_instance
= prim
->count
;
198 /* If nothing to emit, just return. */
199 if (verts_per_instance
== 0 && !is_indirect
&& !xfb_obj
)
202 /* If we're set to always flush, do it before and after the primitive emit.
203 * We want to catch both missed flushes that hurt instruction/state cache
204 * and missed flushes of the render cache as it heads to other parts of
205 * the besides the draw code.
207 if (brw
->always_flush_cache
)
208 brw_emit_mi_flush(brw
);
210 /* If indirect, emit a bunch of loads from the indirect BO. */
212 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
214 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
,
215 xfb_obj
->prim_count_bo
,
216 stream
* sizeof(uint32_t));
218 OUT_BATCH(MI_LOAD_REGISTER_IMM
| (9 - 2));
219 OUT_BATCH(GEN7_3DPRIM_INSTANCE_COUNT
);
220 OUT_BATCH(prim
->num_instances
);
221 OUT_BATCH(GEN7_3DPRIM_START_VERTEX
);
223 OUT_BATCH(GEN7_3DPRIM_BASE_VERTEX
);
225 OUT_BATCH(GEN7_3DPRIM_START_INSTANCE
);
228 } else if (is_indirect
) {
229 struct gl_buffer_object
*indirect_buffer
= brw
->ctx
.DrawIndirectBuffer
;
230 struct brw_bo
*bo
= intel_bufferobj_buffer(brw
,
231 intel_buffer_object(indirect_buffer
),
232 indirect_offset
, 5 * sizeof(GLuint
), false);
234 indirect_flag
= GEN7_3DPRIM_INDIRECT_PARAMETER_ENABLE
;
236 brw_load_register_mem(brw
, GEN7_3DPRIM_VERTEX_COUNT
, bo
,
237 indirect_offset
+ 0);
238 brw_load_register_mem(brw
, GEN7_3DPRIM_INSTANCE_COUNT
, bo
,
239 indirect_offset
+ 4);
241 brw_load_register_mem(brw
, GEN7_3DPRIM_START_VERTEX
, bo
,
242 indirect_offset
+ 8);
244 brw_load_register_mem(brw
, GEN7_3DPRIM_BASE_VERTEX
, bo
,
245 indirect_offset
+ 12);
246 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
247 indirect_offset
+ 16);
249 brw_load_register_mem(brw
, GEN7_3DPRIM_START_INSTANCE
, bo
,
250 indirect_offset
+ 12);
251 brw_load_register_imm32(brw
, GEN7_3DPRIM_BASE_VERTEX
, 0);
257 BEGIN_BATCH(devinfo
->gen
>= 7 ? 7 : 6);
259 if (devinfo
->gen
>= 7) {
260 const int predicate_enable
=
261 (brw
->predicate
.state
== BRW_PREDICATE_STATE_USE_BIT
)
262 ? GEN7_3DPRIM_PREDICATE_ENABLE
: 0;
264 OUT_BATCH(CMD_3D_PRIM
<< 16 | (7 - 2) | indirect_flag
| predicate_enable
);
265 OUT_BATCH(hw_prim
| vertex_access_type
);
267 OUT_BATCH(CMD_3D_PRIM
<< 16 | (6 - 2) |
268 hw_prim
<< GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT
|
271 OUT_BATCH(verts_per_instance
);
272 OUT_BATCH(start_vertex_location
);
273 OUT_BATCH(prim
->num_instances
);
274 OUT_BATCH(prim
->base_instance
);
275 OUT_BATCH(base_vertex_location
);
278 if (brw
->always_flush_cache
)
279 brw_emit_mi_flush(brw
);
284 brw_merge_inputs(struct brw_context
*brw
)
286 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
287 const struct gl_context
*ctx
= &brw
->ctx
;
290 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
291 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
292 brw
->vb
.buffers
[i
].bo
= NULL
;
294 brw
->vb
.nr_buffers
= 0;
296 for (i
= 0; i
< VERT_ATTRIB_MAX
; i
++) {
297 struct brw_vertex_element
*input
= &brw
->vb
.inputs
[i
];
299 _mesa_draw_attrib_and_binding(ctx
, i
,
300 &input
->glattrib
, &input
->glbinding
);
303 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
304 uint64_t mask
= ctx
->VertexProgram
._Current
->info
.inputs_read
;
305 /* Prior to Haswell, the hardware can't natively support GL_FIXED or
306 * 2_10_10_10_REV vertex formats. Set appropriate workaround flags.
309 const struct gl_vertex_format
*glformat
;
310 uint8_t wa_flags
= 0;
312 i
= u_bit_scan64(&mask
);
313 glformat
= &brw
->vb
.inputs
[i
].glattrib
->Format
;
315 switch (glformat
->Type
) {
318 wa_flags
= glformat
->Size
;
321 case GL_INT_2_10_10_10_REV
:
322 wa_flags
|= BRW_ATTRIB_WA_SIGN
;
325 case GL_UNSIGNED_INT_2_10_10_10_REV
:
326 if (glformat
->Format
== GL_BGRA
)
327 wa_flags
|= BRW_ATTRIB_WA_BGRA
;
329 if (glformat
->Normalized
)
330 wa_flags
|= BRW_ATTRIB_WA_NORMALIZE
;
331 else if (!glformat
->Integer
)
332 wa_flags
|= BRW_ATTRIB_WA_SCALE
;
337 if (brw
->vb
.attrib_wa_flags
[i
] != wa_flags
) {
338 brw
->vb
.attrib_wa_flags
[i
] = wa_flags
;
339 brw
->ctx
.NewDriverState
|= BRW_NEW_VS_ATTRIB_WORKAROUNDS
;
345 /* Disable auxiliary buffers if a renderbuffer is also bound as a texture
346 * or shader image. This causes a self-dependency, where both rendering
347 * and sampling may concurrently read or write the CCS buffer, causing
351 intel_disable_rb_aux_buffer(struct brw_context
*brw
,
352 bool *draw_aux_buffer_disabled
,
353 struct intel_mipmap_tree
*tex_mt
,
354 unsigned min_level
, unsigned num_levels
,
357 const struct gl_framebuffer
*fb
= brw
->ctx
.DrawBuffer
;
360 /* We only need to worry about color compression and fast clears. */
361 if (tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_D
&&
362 tex_mt
->aux_usage
!= ISL_AUX_USAGE_CCS_E
)
365 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
366 const struct intel_renderbuffer
*irb
=
367 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
369 if (irb
&& irb
->mt
->bo
== tex_mt
->bo
&&
370 irb
->mt_level
>= min_level
&&
371 irb
->mt_level
< min_level
+ num_levels
) {
372 found
= draw_aux_buffer_disabled
[i
] = true;
377 perf_debug("Disabling CCS because a renderbuffer is also bound %s.\n",
384 /** Implement the ASTC 5x5 sampler workaround
386 * Gen9 sampling hardware has a bug where an ASTC 5x5 compressed surface
387 * cannot live in the sampler cache at the same time as an aux compressed
388 * surface. In order to work around the bug we have to stall rendering with a
389 * CS and pixel scoreboard stall (implicit in the CS stall) and invalidate the
390 * texture cache whenever one of ASTC 5x5 or aux compressed may be in the
391 * sampler cache and we're about to render with something which samples from
394 * In the case of a single shader which textures from both ASTC 5x5 and
395 * a texture which is CCS or HiZ compressed, we have to resolve the aux
396 * compressed texture prior to rendering. This second part is handled in
397 * brw_predraw_resolve_inputs() below.
399 * We have observed this issue to affect CCS and HiZ sampling but whether or
400 * not it also affects MCS is unknown. Because MCS has no concept of a
401 * resolve (and doing one would be stupid expensive), we choose to simply
402 * ignore the possibility and hope for the best.
405 gen9_apply_astc5x5_wa_flush(struct brw_context
*brw
,
406 enum gen9_astc5x5_wa_tex_type curr_mask
)
408 assert(brw
->screen
->devinfo
.gen
== 9);
410 if (((brw
->gen9_astc5x5_wa_tex_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
) &&
411 (curr_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_AUX
)) ||
412 ((brw
->gen9_astc5x5_wa_tex_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_AUX
) &&
413 (curr_mask
& GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
))) {
414 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_CS_STALL
);
415 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE
);
418 brw
->gen9_astc5x5_wa_tex_mask
= curr_mask
;
421 static enum gen9_astc5x5_wa_tex_type
422 gen9_astc5x5_wa_bits(mesa_format format
, enum isl_aux_usage aux_usage
)
424 if (aux_usage
!= ISL_AUX_USAGE_NONE
&&
425 aux_usage
!= ISL_AUX_USAGE_MCS
)
426 return GEN9_ASTC5X5_WA_TEX_TYPE_AUX
;
428 if (format
== MESA_FORMAT_RGBA_ASTC_5x5
||
429 format
== MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5
)
430 return GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5
;
435 /* Helper for the gen9 ASTC 5x5 workaround. This version exists for BLORP's
436 * use-cases where only a single texture is bound.
439 gen9_apply_single_tex_astc5x5_wa(struct brw_context
*brw
,
441 enum isl_aux_usage aux_usage
)
443 gen9_apply_astc5x5_wa_flush(brw
, gen9_astc5x5_wa_bits(format
, aux_usage
));
447 mark_textures_used_for_txf(BITSET_WORD
*used_for_txf
,
448 const struct gl_program
*prog
)
453 uint32_t mask
= prog
->info
.textures_used_by_txf
;
455 int s
= u_bit_scan(&mask
);
456 BITSET_SET(used_for_txf
, prog
->SamplerUnits
[s
]);
461 * \brief Resolve buffers before drawing.
463 * Resolve the depth buffer's HiZ buffer, resolve the depth buffer of each
464 * enabled depth texture, and flush the render cache for any dirty textures.
467 brw_predraw_resolve_inputs(struct brw_context
*brw
, bool rendering
,
468 bool *draw_aux_buffer_disabled
)
470 struct gl_context
*ctx
= &brw
->ctx
;
471 struct intel_texture_object
*tex_obj
;
473 BITSET_DECLARE(used_for_txf
, MAX_COMBINED_TEXTURE_IMAGE_UNITS
);
474 memset(used_for_txf
, 0, sizeof(used_for_txf
));
476 mark_textures_used_for_txf(used_for_txf
, ctx
->VertexProgram
._Current
);
477 mark_textures_used_for_txf(used_for_txf
, ctx
->TessCtrlProgram
._Current
);
478 mark_textures_used_for_txf(used_for_txf
, ctx
->TessEvalProgram
._Current
);
479 mark_textures_used_for_txf(used_for_txf
, ctx
->GeometryProgram
._Current
);
480 mark_textures_used_for_txf(used_for_txf
, ctx
->FragmentProgram
._Current
);
482 mark_textures_used_for_txf(used_for_txf
, ctx
->ComputeProgram
._Current
);
485 int maxEnabledUnit
= ctx
->Texture
._MaxEnabledTexImageUnit
;
487 enum gen9_astc5x5_wa_tex_type astc5x5_wa_bits
= 0;
488 if (brw
->screen
->devinfo
.gen
== 9) {
489 /* In order to properly implement the ASTC 5x5 workaround for an
490 * arbitrary draw or dispatch call, we have to walk the entire list of
491 * textures looking for ASTC 5x5. If there is any ASTC 5x5 in this draw
492 * call, all aux compressed textures must be resolved and have aux
493 * compression disabled while sampling.
495 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
496 if (!ctx
->Texture
.Unit
[i
]._Current
)
498 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
499 if (!tex_obj
|| !tex_obj
->mt
)
502 astc5x5_wa_bits
|= gen9_astc5x5_wa_bits(tex_obj
->_Format
,
503 tex_obj
->mt
->aux_usage
);
505 gen9_apply_astc5x5_wa_flush(brw
, astc5x5_wa_bits
);
508 /* Resolve depth buffer and render cache of each enabled texture. */
509 for (int i
= 0; i
<= maxEnabledUnit
; i
++) {
510 if (!ctx
->Texture
.Unit
[i
]._Current
)
512 tex_obj
= intel_texture_object(ctx
->Texture
.Unit
[i
]._Current
);
513 if (!tex_obj
|| !tex_obj
->mt
)
516 struct gl_sampler_object
*sampler
= _mesa_get_samplerobj(ctx
, i
);
517 enum isl_format view_format
=
518 translate_tex_format(brw
, tex_obj
->_Format
, sampler
->sRGBDecode
);
520 unsigned min_level
, min_layer
, num_levels
, num_layers
;
521 if (tex_obj
->base
.Immutable
) {
522 min_level
= tex_obj
->base
.MinLevel
;
523 num_levels
= MIN2(tex_obj
->base
.NumLevels
, tex_obj
->_MaxLevel
+ 1);
524 min_layer
= tex_obj
->base
.MinLayer
;
525 num_layers
= tex_obj
->base
.Target
!= GL_TEXTURE_3D
?
526 tex_obj
->base
.NumLayers
: INTEL_REMAINING_LAYERS
;
528 min_level
= tex_obj
->base
.BaseLevel
;
529 num_levels
= tex_obj
->_MaxLevel
- tex_obj
->base
.BaseLevel
+ 1;
531 num_layers
= INTEL_REMAINING_LAYERS
;
535 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
536 tex_obj
->mt
, min_level
, num_levels
,
540 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, view_format
,
541 min_level
, num_levels
,
542 min_layer
, num_layers
,
545 /* If any programs are using it with texelFetch, we may need to also do
546 * a prepare with an sRGB format to ensure texelFetch works "properly".
548 if (BITSET_TEST(used_for_txf
, i
)) {
549 enum isl_format txf_format
=
550 translate_tex_format(brw
, tex_obj
->_Format
, GL_DECODE_EXT
);
551 if (txf_format
!= view_format
) {
552 intel_miptree_prepare_texture(brw
, tex_obj
->mt
, txf_format
,
553 min_level
, num_levels
,
554 min_layer
, num_layers
,
559 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
561 if (tex_obj
->base
.StencilSampling
||
562 tex_obj
->mt
->format
== MESA_FORMAT_S_UINT8
) {
563 intel_update_r8stencil(brw
, tex_obj
->mt
);
566 if (intel_miptree_has_etc_shadow(brw
, tex_obj
->mt
) &&
567 tex_obj
->mt
->shadow_needs_update
) {
568 intel_miptree_update_etc_shadow_levels(brw
, tex_obj
->mt
);
572 /* Resolve color for each active shader image. */
573 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
574 const struct gl_program
*prog
= ctx
->_Shader
->CurrentProgram
[i
];
576 if (unlikely(prog
&& prog
->info
.num_images
)) {
577 for (unsigned j
= 0; j
< prog
->info
.num_images
; j
++) {
578 struct gl_image_unit
*u
=
579 &ctx
->ImageUnits
[prog
->sh
.ImageUnits
[j
]];
580 tex_obj
= intel_texture_object(u
->TexObj
);
582 if (tex_obj
&& tex_obj
->mt
) {
584 intel_disable_rb_aux_buffer(brw
, draw_aux_buffer_disabled
,
586 "as a shader image");
589 intel_miptree_prepare_image(brw
, tex_obj
->mt
);
591 brw_cache_flush_for_read(brw
, tex_obj
->mt
->bo
);
599 brw_predraw_resolve_framebuffer(struct brw_context
*brw
,
600 bool *draw_aux_buffer_disabled
)
602 struct gl_context
*ctx
= &brw
->ctx
;
603 struct intel_renderbuffer
*depth_irb
;
605 /* Resolve the depth buffer's HiZ buffer. */
606 depth_irb
= intel_get_renderbuffer(ctx
->DrawBuffer
, BUFFER_DEPTH
);
607 if (depth_irb
&& depth_irb
->mt
) {
608 intel_miptree_prepare_depth(brw
, depth_irb
->mt
,
611 depth_irb
->layer_count
);
614 /* Resolve color buffers for non-coherent framebuffer fetch. */
615 if (!ctx
->Extensions
.EXT_shader_framebuffer_fetch
&&
616 ctx
->FragmentProgram
._Current
&&
617 ctx
->FragmentProgram
._Current
->info
.outputs_read
) {
618 const struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
620 /* This is only used for non-coherent framebuffer fetch, so we don't
621 * need to worry about CCS_E and can simply pass 'false' below.
623 assert(brw
->screen
->devinfo
.gen
< 9);
625 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
626 const struct intel_renderbuffer
*irb
=
627 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
630 intel_miptree_prepare_texture(brw
, irb
->mt
, irb
->mt
->surf
.format
,
632 irb
->mt_layer
, irb
->layer_count
,
633 brw
->gen9_astc5x5_wa_tex_mask
);
638 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
639 for (int i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
640 struct intel_renderbuffer
*irb
=
641 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
643 if (irb
== NULL
|| irb
->mt
== NULL
)
646 mesa_format mesa_format
=
647 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
648 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
649 bool blend_enabled
= ctx
->Color
.BlendEnabled
& (1 << i
);
650 enum isl_aux_usage aux_usage
=
651 intel_miptree_render_aux_usage(brw
, irb
->mt
, isl_format
,
653 draw_aux_buffer_disabled
[i
]);
654 if (brw
->draw_aux_usage
[i
] != aux_usage
) {
655 brw
->ctx
.NewDriverState
|= BRW_NEW_AUX_STATE
;
656 brw
->draw_aux_usage
[i
] = aux_usage
;
659 intel_miptree_prepare_render(brw
, irb
->mt
, irb
->mt_level
,
660 irb
->mt_layer
, irb
->layer_count
,
663 brw_cache_flush_for_render(brw
, irb
->mt
->bo
,
664 isl_format
, aux_usage
);
669 * \brief Call this after drawing to mark which buffers need resolving
671 * If the depth buffer was written to and if it has an accompanying HiZ
672 * buffer, then mark that it needs a depth resolve.
674 * If the stencil buffer was written to then mark that it may need to be
675 * copied to an R8 texture.
677 * If the color buffer is a multisample window system buffer, then
678 * mark that it needs a downsample.
680 * Also mark any render targets which will be textured as needing a render
684 brw_postdraw_set_buffers_need_resolve(struct brw_context
*brw
)
686 struct gl_context
*ctx
= &brw
->ctx
;
687 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
689 struct intel_renderbuffer
*front_irb
= NULL
;
690 struct intel_renderbuffer
*back_irb
= intel_get_renderbuffer(fb
, BUFFER_BACK_LEFT
);
691 struct intel_renderbuffer
*depth_irb
= intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
692 struct intel_renderbuffer
*stencil_irb
= intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
693 struct gl_renderbuffer_attachment
*depth_att
= &fb
->Attachment
[BUFFER_DEPTH
];
695 if (_mesa_is_front_buffer_drawing(fb
))
696 front_irb
= intel_get_renderbuffer(fb
, BUFFER_FRONT_LEFT
);
699 front_irb
->need_downsample
= true;
701 back_irb
->need_downsample
= true;
703 bool depth_written
= brw_depth_writes_enabled(brw
);
704 if (depth_att
->Layered
) {
705 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
708 depth_irb
->layer_count
,
711 intel_miptree_finish_depth(brw
, depth_irb
->mt
,
713 depth_irb
->mt_layer
, 1,
717 brw_depth_cache_add_bo(brw
, depth_irb
->mt
->bo
);
720 if (stencil_irb
&& brw
->stencil_write_enabled
) {
721 struct intel_mipmap_tree
*stencil_mt
=
722 stencil_irb
->mt
->stencil_mt
!= NULL
?
723 stencil_irb
->mt
->stencil_mt
: stencil_irb
->mt
;
724 brw_depth_cache_add_bo(brw
, stencil_mt
->bo
);
725 intel_miptree_finish_write(brw
, stencil_mt
, stencil_irb
->mt_level
,
726 stencil_irb
->mt_layer
,
727 stencil_irb
->layer_count
, ISL_AUX_USAGE_NONE
);
730 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
731 struct intel_renderbuffer
*irb
=
732 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
737 mesa_format mesa_format
=
738 _mesa_get_render_format(ctx
, intel_rb_format(irb
));
739 enum isl_format isl_format
= brw_isl_format_for_mesa_format(mesa_format
);
740 enum isl_aux_usage aux_usage
= brw
->draw_aux_usage
[i
];
742 brw_render_cache_add_bo(brw
, irb
->mt
->bo
, isl_format
, aux_usage
);
744 intel_miptree_finish_render(brw
, irb
->mt
, irb
->mt_level
,
745 irb
->mt_layer
, irb
->layer_count
,
751 intel_renderbuffer_move_temp_back(struct brw_context
*brw
,
752 struct intel_renderbuffer
*irb
)
754 if (irb
->align_wa_mt
== NULL
)
757 brw_cache_flush_for_read(brw
, irb
->align_wa_mt
->bo
);
759 intel_miptree_copy_slice(brw
, irb
->align_wa_mt
, 0, 0,
761 irb
->Base
.Base
.TexImage
->Level
, irb
->mt_layer
);
763 intel_miptree_reference(&irb
->align_wa_mt
, NULL
);
765 /* Finally restore the x,y to correspond to full miptree. */
766 intel_renderbuffer_set_draw_offset(irb
);
768 /* Make sure render surface state gets re-emitted with updated miptree. */
769 brw
->NewGLState
|= _NEW_BUFFERS
;
773 brw_postdraw_reconcile_align_wa_slices(struct brw_context
*brw
)
775 struct gl_context
*ctx
= &brw
->ctx
;
776 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
778 struct intel_renderbuffer
*depth_irb
=
779 intel_get_renderbuffer(fb
, BUFFER_DEPTH
);
780 struct intel_renderbuffer
*stencil_irb
=
781 intel_get_renderbuffer(fb
, BUFFER_STENCIL
);
783 if (depth_irb
&& depth_irb
->align_wa_mt
)
784 intel_renderbuffer_move_temp_back(brw
, depth_irb
);
786 if (stencil_irb
&& stencil_irb
->align_wa_mt
)
787 intel_renderbuffer_move_temp_back(brw
, stencil_irb
);
789 for (unsigned i
= 0; i
< fb
->_NumColorDrawBuffers
; i
++) {
790 struct intel_renderbuffer
*irb
=
791 intel_renderbuffer(fb
->_ColorDrawBuffers
[i
]);
793 if (!irb
|| irb
->align_wa_mt
== NULL
)
796 intel_renderbuffer_move_temp_back(brw
, irb
);
801 brw_prepare_drawing(struct gl_context
*ctx
,
802 const struct _mesa_index_buffer
*ib
,
803 bool index_bounds_valid
,
807 struct brw_context
*brw
= brw_context(ctx
);
810 _mesa_update_state(ctx
);
812 /* We have to validate the textures *before* checking for fallbacks;
813 * otherwise, the software fallback won't be able to rely on the
814 * texture state, the firstLevel and lastLevel fields won't be
815 * set in the intel texture object (they'll both be 0), and the
816 * software fallback will segfault if it attempts to access any
817 * texture level other than level 0.
819 brw_validate_textures(brw
);
821 /* Find the highest sampler unit used by each shader program. A bit-count
822 * won't work since ARB programs use the texture unit number as the sampler
825 brw
->wm
.base
.sampler_count
=
826 util_last_bit(ctx
->FragmentProgram
._Current
->info
.textures_used
);
827 brw
->gs
.base
.sampler_count
= ctx
->GeometryProgram
._Current
?
828 util_last_bit(ctx
->GeometryProgram
._Current
->info
.textures_used
) : 0;
829 brw
->tes
.base
.sampler_count
= ctx
->TessEvalProgram
._Current
?
830 util_last_bit(ctx
->TessEvalProgram
._Current
->info
.textures_used
) : 0;
831 brw
->tcs
.base
.sampler_count
= ctx
->TessCtrlProgram
._Current
?
832 util_last_bit(ctx
->TessCtrlProgram
._Current
->info
.textures_used
) : 0;
833 brw
->vs
.base
.sampler_count
=
834 util_last_bit(ctx
->VertexProgram
._Current
->info
.textures_used
);
836 intel_prepare_render(brw
);
838 /* This workaround has to happen outside of brw_upload_render_state()
839 * because it may flush the batchbuffer for a blit, affecting the state
842 brw_workaround_depthstencil_alignment(brw
, 0);
844 /* Resolves must occur after updating renderbuffers, updating context state,
845 * and finalizing textures but before setting up any hardware state for
848 bool draw_aux_buffer_disabled
[MAX_DRAW_BUFFERS
] = { };
849 brw_predraw_resolve_inputs(brw
, true, draw_aux_buffer_disabled
);
850 brw_predraw_resolve_framebuffer(brw
, draw_aux_buffer_disabled
);
852 /* Bind all inputs, derive varying and size information:
854 brw_merge_inputs(brw
);
857 brw
->ctx
.NewDriverState
|= BRW_NEW_INDICES
;
859 brw
->vb
.index_bounds_valid
= index_bounds_valid
;
860 brw
->vb
.min_index
= min_index
;
861 brw
->vb
.max_index
= max_index
;
862 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
866 brw_finish_drawing(struct gl_context
*ctx
)
868 struct brw_context
*brw
= brw_context(ctx
);
870 if (brw
->always_flush_batch
)
871 intel_batchbuffer_flush(brw
);
873 brw_program_cache_check_size(brw
);
874 brw_postdraw_reconcile_align_wa_slices(brw
);
875 brw_postdraw_set_buffers_need_resolve(brw
);
877 if (brw
->draw
.draw_params_count_bo
) {
878 brw_bo_unreference(brw
->draw
.draw_params_count_bo
);
879 brw
->draw
.draw_params_count_bo
= NULL
;
882 if (brw
->draw
.draw_params_bo
) {
883 brw_bo_unreference(brw
->draw
.draw_params_bo
);
884 brw
->draw
.draw_params_bo
= NULL
;
887 if (brw
->draw
.derived_draw_params_bo
) {
888 brw_bo_unreference(brw
->draw
.derived_draw_params_bo
);
889 brw
->draw
.derived_draw_params_bo
= NULL
;
894 * Implement workarounds for preemption:
895 * - WaDisableMidObjectPreemptionForGSLineStripAdj
896 * - WaDisableMidObjectPreemptionForTrifanOrPolygon
897 * - WaDisableMidObjectPreemptionForLineLoop
901 gen9_emit_preempt_wa(struct brw_context
*brw
,
902 const struct _mesa_prim
*prim
)
904 bool object_preemption
= true;
905 ASSERTED
const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
907 /* Only apply these workarounds for gen9 */
908 assert(devinfo
->gen
== 9);
910 /* WaDisableMidObjectPreemptionForGSLineStripAdj
912 * WA: Disable mid-draw preemption when draw-call is a linestrip_adj and
915 if (brw
->primitive
== _3DPRIM_LINESTRIP_ADJ
&& brw
->gs
.enabled
)
916 object_preemption
= false;
918 /* WaDisableMidObjectPreemptionForTrifanOrPolygon
920 * TriFan miscompare in Execlist Preemption test. Cut index that is on a
921 * previous context. End the previous, the resume another context with a
922 * tri-fan or polygon, and the vertex count is corrupted. If we prempt
923 * again we will cause corruption.
925 * WA: Disable mid-draw preemption when draw-call has a tri-fan.
927 if (brw
->primitive
== _3DPRIM_TRIFAN
)
928 object_preemption
= false;
930 /* WaDisableMidObjectPreemptionForLineLoop
932 * VF Stats Counters Missing a vertex when preemption enabled.
934 * WA: Disable mid-draw preemption when the draw uses a lineloop
937 if (brw
->primitive
== _3DPRIM_LINELOOP
)
938 object_preemption
= false;
942 * VF is corrupting GAFS data when preempted on an instance boundary and
943 * replayed with instancing enabled.
945 * WA: Disable preemption when using instanceing.
947 if (prim
->num_instances
> 1)
948 object_preemption
= false;
950 brw_enable_obj_preemption(brw
, object_preemption
);
953 /* May fail if out of video memory for texture or vbo upload, or on
954 * fallback conditions.
957 brw_draw_single_prim(struct gl_context
*ctx
,
958 const struct _mesa_prim
*prim
,
961 struct brw_transform_feedback_object
*xfb_obj
,
963 GLsizeiptr indirect_offset
)
965 struct brw_context
*brw
= brw_context(ctx
);
966 const struct gen_device_info
*devinfo
= &brw
->screen
->devinfo
;
968 bool is_indirect
= brw
->draw
.draw_indirect_data
!= NULL
;
970 /* Flag BRW_NEW_DRAW_CALL on every draw. This allows us to have
971 * atoms that happen on every draw call.
973 brw
->ctx
.NewDriverState
|= BRW_NEW_DRAW_CALL
;
975 /* Flush the batch if the batch/state buffers are nearly full. We can
976 * grow them if needed, but this is not free, so we'd like to avoid it.
978 intel_batchbuffer_require_space(brw
, 1500);
979 brw_require_statebuffer_space(brw
, 2400);
980 intel_batchbuffer_save_state(brw
);
981 fail_next
= intel_batchbuffer_saved_state_is_empty(brw
);
983 if (brw
->num_instances
!= prim
->num_instances
||
984 brw
->basevertex
!= prim
->basevertex
||
985 brw
->baseinstance
!= prim
->base_instance
) {
986 brw
->num_instances
= prim
->num_instances
;
987 brw
->basevertex
= prim
->basevertex
;
988 brw
->baseinstance
= prim
->base_instance
;
989 if (prim_id
> 0) { /* For i == 0 we just did this before the loop */
990 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
991 brw_merge_inputs(brw
);
995 /* Determine if we need to flag BRW_NEW_VERTICES for updating the
996 * gl_BaseVertexARB or gl_BaseInstanceARB values. For indirect draw, we
997 * always flag if the shader uses one of the values. For direct draws,
998 * we only flag if the values change.
1000 const int new_firstvertex
=
1001 is_indexed
? prim
->basevertex
: prim
->start
;
1002 const int new_baseinstance
= prim
->base_instance
;
1003 const struct brw_vs_prog_data
*vs_prog_data
=
1004 brw_vs_prog_data(brw
->vs
.base
.prog_data
);
1006 const bool uses_draw_parameters
=
1007 vs_prog_data
->uses_firstvertex
||
1008 vs_prog_data
->uses_baseinstance
;
1010 if ((uses_draw_parameters
&& is_indirect
) ||
1011 (vs_prog_data
->uses_firstvertex
&&
1012 brw
->draw
.params
.firstvertex
!= new_firstvertex
) ||
1013 (vs_prog_data
->uses_baseinstance
&&
1014 brw
->draw
.params
.gl_baseinstance
!= new_baseinstance
))
1015 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
1018 brw
->draw
.params
.firstvertex
= new_firstvertex
;
1019 brw
->draw
.params
.gl_baseinstance
= new_baseinstance
;
1020 brw_bo_unreference(brw
->draw
.draw_params_bo
);
1023 /* Point draw_params_bo at the indirect buffer. */
1024 brw
->draw
.draw_params_bo
=
1025 intel_buffer_object(ctx
->DrawIndirectBuffer
)->buffer
;
1026 brw_bo_reference(brw
->draw
.draw_params_bo
);
1027 brw
->draw
.draw_params_offset
=
1028 indirect_offset
+ (is_indexed
? 12 : 8);
1030 /* Set draw_params_bo to NULL so brw_prepare_vertices knows it
1031 * has to upload gl_BaseVertex and such if they're needed.
1033 brw
->draw
.draw_params_bo
= NULL
;
1034 brw
->draw
.draw_params_offset
= 0;
1037 /* gl_DrawID always needs its own vertex buffer since it's not part of
1038 * the indirect parameter buffer. Same for is_indexed_draw, which shares
1039 * the buffer with gl_DrawID. If the program uses gl_DrawID, we need to
1040 * flag BRW_NEW_VERTICES. For the first iteration, we don't have valid
1041 * vs_prog_data, but we always flag BRW_NEW_VERTICES before the loop.
1043 if (prim_id
> 0 && vs_prog_data
->uses_drawid
)
1044 brw
->ctx
.NewDriverState
|= BRW_NEW_VERTICES
;
1046 brw
->draw
.derived_params
.gl_drawid
= prim
->draw_id
;
1047 brw
->draw
.derived_params
.is_indexed_draw
= is_indexed
? ~0 : 0;
1049 brw_bo_unreference(brw
->draw
.derived_draw_params_bo
);
1050 brw
->draw
.derived_draw_params_bo
= NULL
;
1051 brw
->draw
.derived_draw_params_offset
= 0;
1053 if (devinfo
->gen
< 6)
1054 brw_set_prim(brw
, prim
);
1056 gen6_set_prim(brw
, prim
);
1060 /* Note that before the loop, brw->ctx.NewDriverState was set to != 0, and
1061 * that the state updated in the loop outside of this block is that in
1062 * *_set_prim or intel_batchbuffer_flush(), which only impacts
1063 * brw->ctx.NewDriverState.
1065 if (brw
->ctx
.NewDriverState
) {
1066 brw
->batch
.no_wrap
= true;
1067 brw_upload_render_state(brw
);
1070 if (devinfo
->gen
== 9)
1071 gen9_emit_preempt_wa(brw
, prim
);
1073 brw_emit_prim(brw
, prim
, brw
->primitive
, is_indexed
, xfb_obj
, stream
,
1074 is_indirect
, indirect_offset
);
1076 brw
->batch
.no_wrap
= false;
1078 if (!brw_batch_has_aperture_space(brw
, 0)) {
1080 intel_batchbuffer_reset_to_saved(brw
);
1081 intel_batchbuffer_flush(brw
);
1085 int ret
= intel_batchbuffer_flush(brw
);
1086 WARN_ONCE(ret
== -ENOSPC
,
1087 "i965: Single primitive emit exceeded "
1088 "available aperture space\n");
1092 /* Now that we know we haven't run out of aperture space, we can safely
1093 * reset the dirty bits.
1095 if (brw
->ctx
.NewDriverState
)
1096 brw_render_state_finished(brw
);
1104 brw_draw_prims(struct gl_context
*ctx
,
1105 const struct _mesa_prim
*prims
,
1107 const struct _mesa_index_buffer
*ib
,
1108 GLboolean index_bounds_valid
,
1111 struct gl_transform_feedback_object
*gl_xfb_obj
,
1115 struct brw_context
*brw
= brw_context(ctx
);
1116 int predicate_state
= brw
->predicate
.state
;
1117 struct brw_transform_feedback_object
*xfb_obj
=
1118 (struct brw_transform_feedback_object
*) gl_xfb_obj
;
1120 if (!brw_check_conditional_render(brw
))
1123 /* Handle primitive restart if needed */
1124 if (brw_handle_primitive_restart(ctx
, prims
, nr_prims
, ib
)) {
1125 /* The draw was handled, so we can exit now */
1129 /* Do GL_SELECT and GL_FEEDBACK rendering using swrast, even though it
1130 * won't support all the extensions we support.
1132 if (ctx
->RenderMode
!= GL_RENDER
) {
1133 perf_debug("%s render mode not supported in hardware\n",
1134 _mesa_enum_to_string(ctx
->RenderMode
));
1135 _swsetup_Wakeup(ctx
);
1137 _tnl_draw(ctx
, prims
, nr_prims
, ib
,
1138 index_bounds_valid
, min_index
, max_index
, NULL
, 0);
1142 /* If we're going to have to upload any of the user's vertex arrays, then
1143 * get the minimum and maximum of their index buffer so we know what range
1146 if (!index_bounds_valid
&& _mesa_draw_user_array_bits(ctx
) != 0) {
1147 perf_debug("Scanning index buffer to compute index buffer bounds. "
1148 "Use glDrawRangeElements() to avoid this.\n");
1149 vbo_get_minmax_indices(ctx
, prims
, ib
, &min_index
, &max_index
, nr_prims
);
1150 index_bounds_valid
= true;
1153 brw_prepare_drawing(ctx
, ib
, index_bounds_valid
, min_index
, max_index
);
1154 /* Try drawing with the hardware, but don't do anything else if we can't
1155 * manage it. swrast doesn't support our featureset, so we can't fall back
1159 for (i
= 0; i
< nr_prims
; i
++) {
1160 /* Implementation of ARB_indirect_parameters via predicates */
1161 if (brw
->draw
.draw_params_count_bo
) {
1162 brw_emit_pipe_control_flush(brw
, PIPE_CONTROL_FLUSH_ENABLE
);
1164 /* Upload the current draw count from the draw parameters buffer to
1165 * MI_PREDICATE_SRC0.
1167 brw_load_register_mem(brw
, MI_PREDICATE_SRC0
,
1168 brw
->draw
.draw_params_count_bo
,
1169 brw
->draw
.draw_params_count_offset
);
1170 /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
1171 brw_load_register_imm32(brw
, MI_PREDICATE_SRC0
+ 4, 0);
1172 /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
1173 brw_load_register_imm64(brw
, MI_PREDICATE_SRC1
, prims
[i
].draw_id
);
1176 if (i
== 0 && brw
->predicate
.state
!= BRW_PREDICATE_STATE_USE_BIT
) {
1177 OUT_BATCH(GEN7_MI_PREDICATE
| MI_PREDICATE_LOADOP_LOADINV
|
1178 MI_PREDICATE_COMBINEOP_SET
|
1179 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1181 OUT_BATCH(GEN7_MI_PREDICATE
|
1182 MI_PREDICATE_LOADOP_LOAD
| MI_PREDICATE_COMBINEOP_XOR
|
1183 MI_PREDICATE_COMPAREOP_SRCS_EQUAL
);
1187 brw
->predicate
.state
= BRW_PREDICATE_STATE_USE_BIT
;
1190 brw_draw_single_prim(ctx
, &prims
[i
], i
, ib
!= NULL
, xfb_obj
, stream
,
1191 brw
->draw
.draw_indirect_offset
+
1192 brw
->draw
.draw_indirect_stride
* i
);
1195 brw_finish_drawing(ctx
);
1196 brw
->predicate
.state
= predicate_state
;
1200 brw_draw_indirect_prims(struct gl_context
*ctx
,
1202 struct gl_buffer_object
*indirect_data
,
1203 GLsizeiptr indirect_offset
,
1204 unsigned draw_count
,
1206 struct gl_buffer_object
*indirect_params
,
1207 GLsizeiptr indirect_params_offset
,
1208 const struct _mesa_index_buffer
*ib
)
1210 struct brw_context
*brw
= brw_context(ctx
);
1211 struct _mesa_prim
*prim
;
1214 prim
= calloc(draw_count
, sizeof(*prim
));
1216 _mesa_error(ctx
, GL_OUT_OF_MEMORY
, "gl%sDraw%sIndirect%s",
1217 (draw_count
> 1) ? "Multi" : "",
1218 ib
? "Elements" : "Arrays",
1219 indirect_params
? "CountARB" : "");
1223 brw
->draw
.draw_indirect_stride
= stride
;
1224 brw
->draw
.draw_indirect_offset
= indirect_offset
;
1227 prim
[draw_count
- 1].end
= 1;
1228 for (i
= 0; i
< draw_count
; ++i
) {
1229 prim
[i
].mode
= mode
;
1230 prim
[i
].draw_id
= i
;
1233 if (indirect_params
) {
1234 brw
->draw
.draw_params_count_bo
=
1235 intel_buffer_object(indirect_params
)->buffer
;
1236 brw_bo_reference(brw
->draw
.draw_params_count_bo
);
1237 brw
->draw
.draw_params_count_offset
= indirect_params_offset
;
1240 brw
->draw
.draw_indirect_data
= indirect_data
;
1242 brw_draw_prims(ctx
, prim
, draw_count
,
1246 brw
->draw
.draw_indirect_data
= NULL
;
1251 brw_init_draw_functions(struct dd_function_table
*functions
)
1253 /* Register our drawing function:
1255 functions
->Draw
= brw_draw_prims
;
1256 functions
->DrawIndirect
= brw_draw_indirect_prims
;
1260 brw_draw_init(struct brw_context
*brw
)
1262 for (int i
= 0; i
< VERT_ATTRIB_MAX
; i
++)
1263 brw
->vb
.inputs
[i
].buffer
= -1;
1264 brw
->vb
.nr_buffers
= 0;
1265 brw
->vb
.nr_enabled
= 0;
1269 brw_draw_destroy(struct brw_context
*brw
)
1273 for (i
= 0; i
< brw
->vb
.nr_buffers
; i
++) {
1274 brw_bo_unreference(brw
->vb
.buffers
[i
].bo
);
1275 brw
->vb
.buffers
[i
].bo
= NULL
;
1277 brw
->vb
.nr_buffers
= 0;
1279 for (i
= 0; i
< brw
->vb
.nr_enabled
; i
++) {
1280 brw
->vb
.enabled
[i
]->buffer
= -1;
1282 brw
->vb
.nr_enabled
= 0;
1284 brw_bo_unreference(brw
->ib
.bo
);