2 Copyright (C) Intel Corp. 2006. All Rights Reserved.
3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
4 develop this 3D driver.
6 Permission is hereby granted, free of charge, to any person obtaining
7 a copy of this software and associated documentation files (the
8 "Software"), to deal in the Software without restriction, including
9 without limitation the rights to use, copy, modify, merge, publish,
10 distribute, sublicense, and/or sell copies of the Software, and to
11 permit persons to whom the Software is furnished to do so, subject to
12 the following conditions:
14 The above copyright notice and this permission notice (including the
15 next paragraph) shall be included in all copies or substantial
16 portions of the Software.
18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **********************************************************************/
29 * Keith Whitwell <keith@tungstengraphics.com>
33 #include "brw_context.h"
34 #include "brw_defines.h"
40 /***********************************************************************
41 * Internal helper for constructing instructions
44 static void guess_execution_size( struct brw_instruction
*insn
,
47 if (reg
.width
== BRW_WIDTH_8
&&
48 insn
->header
.compression_control
== BRW_COMPRESSION_COMPRESSED
)
49 insn
->header
.execution_size
= BRW_EXECUTE_16
;
51 insn
->header
.execution_size
= reg
.width
; /* note - definitions are compatible */
55 static void brw_set_dest( struct brw_instruction
*insn
,
58 if (dest
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
&&
59 dest
.file
!= BRW_MESSAGE_REGISTER_FILE
)
60 assert(dest
.nr
< 128);
62 insn
->bits1
.da1
.dest_reg_file
= dest
.file
;
63 insn
->bits1
.da1
.dest_reg_type
= dest
.type
;
64 insn
->bits1
.da1
.dest_address_mode
= dest
.address_mode
;
66 if (dest
.address_mode
== BRW_ADDRESS_DIRECT
) {
67 insn
->bits1
.da1
.dest_reg_nr
= dest
.nr
;
69 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
70 insn
->bits1
.da1
.dest_subreg_nr
= dest
.subnr
;
71 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
72 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
73 insn
->bits1
.da1
.dest_horiz_stride
= dest
.hstride
;
76 insn
->bits1
.da16
.dest_subreg_nr
= dest
.subnr
/ 16;
77 insn
->bits1
.da16
.dest_writemask
= dest
.dw1
.bits
.writemask
;
78 /* even ignored in da16, still need to set as '01' */
79 insn
->bits1
.da16
.dest_horiz_stride
= 1;
83 insn
->bits1
.ia1
.dest_subreg_nr
= dest
.subnr
;
85 /* These are different sizes in align1 vs align16:
87 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
88 insn
->bits1
.ia1
.dest_indirect_offset
= dest
.dw1
.bits
.indirect_offset
;
89 if (dest
.hstride
== BRW_HORIZONTAL_STRIDE_0
)
90 dest
.hstride
= BRW_HORIZONTAL_STRIDE_1
;
91 insn
->bits1
.ia1
.dest_horiz_stride
= dest
.hstride
;
94 insn
->bits1
.ia16
.dest_indirect_offset
= dest
.dw1
.bits
.indirect_offset
;
95 /* even ignored in da16, still need to set as '01' */
96 insn
->bits1
.ia16
.dest_horiz_stride
= 1;
100 /* NEW: Set the execution size based on dest.width and
101 * insn->compression_control:
103 guess_execution_size(insn
, dest
);
106 static void brw_set_src0( struct brw_instruction
*insn
,
109 if (reg
.type
!= BRW_ARCHITECTURE_REGISTER_FILE
)
110 assert(reg
.nr
< 128);
112 insn
->bits1
.da1
.src0_reg_file
= reg
.file
;
113 insn
->bits1
.da1
.src0_reg_type
= reg
.type
;
114 insn
->bits2
.da1
.src0_abs
= reg
.abs
;
115 insn
->bits2
.da1
.src0_negate
= reg
.negate
;
116 insn
->bits2
.da1
.src0_address_mode
= reg
.address_mode
;
118 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
119 insn
->bits3
.ud
= reg
.dw1
.ud
;
121 /* Required to set some fields in src1 as well:
123 insn
->bits1
.da1
.src1_reg_file
= 0; /* arf */
124 insn
->bits1
.da1
.src1_reg_type
= reg
.type
;
128 if (reg
.address_mode
== BRW_ADDRESS_DIRECT
) {
129 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
130 insn
->bits2
.da1
.src0_subreg_nr
= reg
.subnr
;
131 insn
->bits2
.da1
.src0_reg_nr
= reg
.nr
;
134 insn
->bits2
.da16
.src0_subreg_nr
= reg
.subnr
/ 16;
135 insn
->bits2
.da16
.src0_reg_nr
= reg
.nr
;
139 insn
->bits2
.ia1
.src0_subreg_nr
= reg
.subnr
;
141 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
142 insn
->bits2
.ia1
.src0_indirect_offset
= reg
.dw1
.bits
.indirect_offset
;
145 insn
->bits2
.ia16
.src0_subreg_nr
= reg
.dw1
.bits
.indirect_offset
;
149 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
150 if (reg
.width
== BRW_WIDTH_1
&&
151 insn
->header
.execution_size
== BRW_EXECUTE_1
) {
152 insn
->bits2
.da1
.src0_horiz_stride
= BRW_HORIZONTAL_STRIDE_0
;
153 insn
->bits2
.da1
.src0_width
= BRW_WIDTH_1
;
154 insn
->bits2
.da1
.src0_vert_stride
= BRW_VERTICAL_STRIDE_0
;
157 insn
->bits2
.da1
.src0_horiz_stride
= reg
.hstride
;
158 insn
->bits2
.da1
.src0_width
= reg
.width
;
159 insn
->bits2
.da1
.src0_vert_stride
= reg
.vstride
;
163 insn
->bits2
.da16
.src0_swz_x
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_X
);
164 insn
->bits2
.da16
.src0_swz_y
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Y
);
165 insn
->bits2
.da16
.src0_swz_z
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Z
);
166 insn
->bits2
.da16
.src0_swz_w
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_W
);
168 /* This is an oddity of the fact we're using the same
169 * descriptions for registers in align_16 as align_1:
171 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
)
172 insn
->bits2
.da16
.src0_vert_stride
= BRW_VERTICAL_STRIDE_4
;
174 insn
->bits2
.da16
.src0_vert_stride
= reg
.vstride
;
180 void brw_set_src1( struct brw_instruction
*insn
,
183 assert(reg
.file
!= BRW_MESSAGE_REGISTER_FILE
);
185 assert(reg
.nr
< 128);
187 insn
->bits1
.da1
.src1_reg_file
= reg
.file
;
188 insn
->bits1
.da1
.src1_reg_type
= reg
.type
;
189 insn
->bits3
.da1
.src1_abs
= reg
.abs
;
190 insn
->bits3
.da1
.src1_negate
= reg
.negate
;
192 /* Only src1 can be immediate in two-argument instructions.
194 assert(insn
->bits1
.da1
.src0_reg_file
!= BRW_IMMEDIATE_VALUE
);
196 if (reg
.file
== BRW_IMMEDIATE_VALUE
) {
197 insn
->bits3
.ud
= reg
.dw1
.ud
;
200 /* This is a hardware restriction, which may or may not be lifted
203 assert (reg
.address_mode
== BRW_ADDRESS_DIRECT
);
204 /* assert (reg.file == BRW_GENERAL_REGISTER_FILE); */
206 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
207 insn
->bits3
.da1
.src1_subreg_nr
= reg
.subnr
;
208 insn
->bits3
.da1
.src1_reg_nr
= reg
.nr
;
211 insn
->bits3
.da16
.src1_subreg_nr
= reg
.subnr
/ 16;
212 insn
->bits3
.da16
.src1_reg_nr
= reg
.nr
;
215 if (insn
->header
.access_mode
== BRW_ALIGN_1
) {
216 if (reg
.width
== BRW_WIDTH_1
&&
217 insn
->header
.execution_size
== BRW_EXECUTE_1
) {
218 insn
->bits3
.da1
.src1_horiz_stride
= BRW_HORIZONTAL_STRIDE_0
;
219 insn
->bits3
.da1
.src1_width
= BRW_WIDTH_1
;
220 insn
->bits3
.da1
.src1_vert_stride
= BRW_VERTICAL_STRIDE_0
;
223 insn
->bits3
.da1
.src1_horiz_stride
= reg
.hstride
;
224 insn
->bits3
.da1
.src1_width
= reg
.width
;
225 insn
->bits3
.da1
.src1_vert_stride
= reg
.vstride
;
229 insn
->bits3
.da16
.src1_swz_x
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_X
);
230 insn
->bits3
.da16
.src1_swz_y
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Y
);
231 insn
->bits3
.da16
.src1_swz_z
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_Z
);
232 insn
->bits3
.da16
.src1_swz_w
= BRW_GET_SWZ(reg
.dw1
.bits
.swizzle
, BRW_CHANNEL_W
);
234 /* This is an oddity of the fact we're using the same
235 * descriptions for registers in align_16 as align_1:
237 if (reg
.vstride
== BRW_VERTICAL_STRIDE_8
)
238 insn
->bits3
.da16
.src1_vert_stride
= BRW_VERTICAL_STRIDE_4
;
240 insn
->bits3
.da16
.src1_vert_stride
= reg
.vstride
;
247 static void brw_set_math_message( struct brw_context
*brw
,
248 struct brw_instruction
*insn
,
250 GLuint response_length
,
253 GLboolean low_precision
,
257 struct intel_context
*intel
= &brw
->intel
;
258 brw_set_src1(insn
, brw_imm_d(0));
260 if (intel
->gen
== 5) {
261 insn
->bits3
.math_gen5
.function
= function
;
262 insn
->bits3
.math_gen5
.int_type
= integer_type
;
263 insn
->bits3
.math_gen5
.precision
= low_precision
;
264 insn
->bits3
.math_gen5
.saturate
= saturate
;
265 insn
->bits3
.math_gen5
.data_type
= dataType
;
266 insn
->bits3
.math_gen5
.snapshot
= 0;
267 insn
->bits3
.math_gen5
.header_present
= 0;
268 insn
->bits3
.math_gen5
.response_length
= response_length
;
269 insn
->bits3
.math_gen5
.msg_length
= msg_length
;
270 insn
->bits3
.math_gen5
.end_of_thread
= 0;
271 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_MATH
;
272 insn
->bits2
.send_gen5
.end_of_thread
= 0;
274 insn
->bits3
.math
.function
= function
;
275 insn
->bits3
.math
.int_type
= integer_type
;
276 insn
->bits3
.math
.precision
= low_precision
;
277 insn
->bits3
.math
.saturate
= saturate
;
278 insn
->bits3
.math
.data_type
= dataType
;
279 insn
->bits3
.math
.response_length
= response_length
;
280 insn
->bits3
.math
.msg_length
= msg_length
;
281 insn
->bits3
.math
.msg_target
= BRW_MESSAGE_TARGET_MATH
;
282 insn
->bits3
.math
.end_of_thread
= 0;
287 static void brw_set_ff_sync_message(struct brw_context
*brw
,
288 struct brw_instruction
*insn
,
290 GLuint response_length
,
291 GLboolean end_of_thread
)
293 struct intel_context
*intel
= &brw
->intel
;
294 brw_set_src1(insn
, brw_imm_d(0));
296 insn
->bits3
.urb_gen5
.opcode
= 1; /* FF_SYNC */
297 insn
->bits3
.urb_gen5
.offset
= 0; /* Not used by FF_SYNC */
298 insn
->bits3
.urb_gen5
.swizzle_control
= 0; /* Not used by FF_SYNC */
299 insn
->bits3
.urb_gen5
.allocate
= allocate
;
300 insn
->bits3
.urb_gen5
.used
= 0; /* Not used by FF_SYNC */
301 insn
->bits3
.urb_gen5
.complete
= 0; /* Not used by FF_SYNC */
302 insn
->bits3
.urb_gen5
.header_present
= 1;
303 insn
->bits3
.urb_gen5
.response_length
= response_length
; /* may be 1 or 0 */
304 insn
->bits3
.urb_gen5
.msg_length
= 1;
305 insn
->bits3
.urb_gen5
.end_of_thread
= end_of_thread
;
306 if (intel
->gen
>= 6) {
307 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_URB
;
309 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_URB
;
310 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
314 static void brw_set_urb_message( struct brw_context
*brw
,
315 struct brw_instruction
*insn
,
319 GLuint response_length
,
320 GLboolean end_of_thread
,
323 GLuint swizzle_control
)
325 struct intel_context
*intel
= &brw
->intel
;
326 brw_set_src1(insn
, brw_imm_d(0));
328 if (intel
->gen
>= 5) {
329 insn
->bits3
.urb_gen5
.opcode
= 0; /* ? */
330 insn
->bits3
.urb_gen5
.offset
= offset
;
331 insn
->bits3
.urb_gen5
.swizzle_control
= swizzle_control
;
332 insn
->bits3
.urb_gen5
.allocate
= allocate
;
333 insn
->bits3
.urb_gen5
.used
= used
; /* ? */
334 insn
->bits3
.urb_gen5
.complete
= complete
;
335 insn
->bits3
.urb_gen5
.header_present
= 1;
336 insn
->bits3
.urb_gen5
.response_length
= response_length
;
337 insn
->bits3
.urb_gen5
.msg_length
= msg_length
;
338 insn
->bits3
.urb_gen5
.end_of_thread
= end_of_thread
;
339 if (intel
->gen
>= 6) {
340 /* For SNB, the SFID bits moved to the condmod bits, and
341 * EOT stayed in bits3 above. Does the EOT bit setting
342 * below on Ironlake even do anything?
344 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_URB
;
346 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_URB
;
347 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
350 insn
->bits3
.urb
.opcode
= 0; /* ? */
351 insn
->bits3
.urb
.offset
= offset
;
352 insn
->bits3
.urb
.swizzle_control
= swizzle_control
;
353 insn
->bits3
.urb
.allocate
= allocate
;
354 insn
->bits3
.urb
.used
= used
; /* ? */
355 insn
->bits3
.urb
.complete
= complete
;
356 insn
->bits3
.urb
.response_length
= response_length
;
357 insn
->bits3
.urb
.msg_length
= msg_length
;
358 insn
->bits3
.urb
.msg_target
= BRW_MESSAGE_TARGET_URB
;
359 insn
->bits3
.urb
.end_of_thread
= end_of_thread
;
363 static void brw_set_dp_write_message( struct brw_context
*brw
,
364 struct brw_instruction
*insn
,
365 GLuint binding_table_index
,
369 GLuint pixel_scoreboard_clear
,
370 GLuint response_length
,
371 GLuint end_of_thread
,
372 GLuint send_commit_msg
)
374 struct intel_context
*intel
= &brw
->intel
;
375 brw_set_src1(insn
, brw_imm_ud(0));
377 if (intel
->gen
>= 6) {
378 insn
->bits3
.dp_render_cache
.binding_table_index
= binding_table_index
;
379 insn
->bits3
.dp_render_cache
.msg_control
= msg_control
;
380 insn
->bits3
.dp_render_cache
.pixel_scoreboard_clear
= pixel_scoreboard_clear
;
381 insn
->bits3
.dp_render_cache
.msg_type
= msg_type
;
382 insn
->bits3
.dp_render_cache
.send_commit_msg
= send_commit_msg
;
383 insn
->bits3
.dp_render_cache
.header_present
= 0; /* XXX */
384 insn
->bits3
.dp_render_cache
.response_length
= response_length
;
385 insn
->bits3
.dp_render_cache
.msg_length
= msg_length
;
386 insn
->bits3
.dp_render_cache
.end_of_thread
= end_of_thread
;
387 insn
->header
.destreg__conditionalmod
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
388 /* XXX really need below? */
389 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
390 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
391 } else if (intel
->gen
== 5) {
392 insn
->bits3
.dp_write_gen5
.binding_table_index
= binding_table_index
;
393 insn
->bits3
.dp_write_gen5
.msg_control
= msg_control
;
394 insn
->bits3
.dp_write_gen5
.pixel_scoreboard_clear
= pixel_scoreboard_clear
;
395 insn
->bits3
.dp_write_gen5
.msg_type
= msg_type
;
396 insn
->bits3
.dp_write_gen5
.send_commit_msg
= send_commit_msg
;
397 insn
->bits3
.dp_write_gen5
.header_present
= 1;
398 insn
->bits3
.dp_write_gen5
.response_length
= response_length
;
399 insn
->bits3
.dp_write_gen5
.msg_length
= msg_length
;
400 insn
->bits3
.dp_write_gen5
.end_of_thread
= end_of_thread
;
401 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
402 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
404 insn
->bits3
.dp_write
.binding_table_index
= binding_table_index
;
405 insn
->bits3
.dp_write
.msg_control
= msg_control
;
406 insn
->bits3
.dp_write
.pixel_scoreboard_clear
= pixel_scoreboard_clear
;
407 insn
->bits3
.dp_write
.msg_type
= msg_type
;
408 insn
->bits3
.dp_write
.send_commit_msg
= send_commit_msg
;
409 insn
->bits3
.dp_write
.response_length
= response_length
;
410 insn
->bits3
.dp_write
.msg_length
= msg_length
;
411 insn
->bits3
.dp_write
.msg_target
= BRW_MESSAGE_TARGET_DATAPORT_WRITE
;
412 insn
->bits3
.dp_write
.end_of_thread
= end_of_thread
;
416 static void brw_set_dp_read_message( struct brw_context
*brw
,
417 struct brw_instruction
*insn
,
418 GLuint binding_table_index
,
423 GLuint response_length
,
424 GLuint end_of_thread
)
426 struct intel_context
*intel
= &brw
->intel
;
427 brw_set_src1(insn
, brw_imm_d(0));
429 if (intel
->gen
== 5) {
430 insn
->bits3
.dp_read_gen5
.binding_table_index
= binding_table_index
;
431 insn
->bits3
.dp_read_gen5
.msg_control
= msg_control
;
432 insn
->bits3
.dp_read_gen5
.msg_type
= msg_type
;
433 insn
->bits3
.dp_read_gen5
.target_cache
= target_cache
;
434 insn
->bits3
.dp_read_gen5
.header_present
= 1;
435 insn
->bits3
.dp_read_gen5
.response_length
= response_length
;
436 insn
->bits3
.dp_read_gen5
.msg_length
= msg_length
;
437 insn
->bits3
.dp_read_gen5
.pad1
= 0;
438 insn
->bits3
.dp_read_gen5
.end_of_thread
= end_of_thread
;
439 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_DATAPORT_READ
;
440 insn
->bits2
.send_gen5
.end_of_thread
= end_of_thread
;
442 insn
->bits3
.dp_read
.binding_table_index
= binding_table_index
; /*0:7*/
443 insn
->bits3
.dp_read
.msg_control
= msg_control
; /*8:11*/
444 insn
->bits3
.dp_read
.msg_type
= msg_type
; /*12:13*/
445 insn
->bits3
.dp_read
.target_cache
= target_cache
; /*14:15*/
446 insn
->bits3
.dp_read
.response_length
= response_length
; /*16:19*/
447 insn
->bits3
.dp_read
.msg_length
= msg_length
; /*20:23*/
448 insn
->bits3
.dp_read
.msg_target
= BRW_MESSAGE_TARGET_DATAPORT_READ
; /*24:27*/
449 insn
->bits3
.dp_read
.pad1
= 0; /*28:30*/
450 insn
->bits3
.dp_read
.end_of_thread
= end_of_thread
; /*31*/
454 static void brw_set_sampler_message(struct brw_context
*brw
,
455 struct brw_instruction
*insn
,
456 GLuint binding_table_index
,
459 GLuint response_length
,
462 GLuint header_present
,
465 struct intel_context
*intel
= &brw
->intel
;
467 brw_set_src1(insn
, brw_imm_d(0));
469 if (intel
->gen
== 5) {
470 insn
->bits3
.sampler_gen5
.binding_table_index
= binding_table_index
;
471 insn
->bits3
.sampler_gen5
.sampler
= sampler
;
472 insn
->bits3
.sampler_gen5
.msg_type
= msg_type
;
473 insn
->bits3
.sampler_gen5
.simd_mode
= simd_mode
;
474 insn
->bits3
.sampler_gen5
.header_present
= header_present
;
475 insn
->bits3
.sampler_gen5
.response_length
= response_length
;
476 insn
->bits3
.sampler_gen5
.msg_length
= msg_length
;
477 insn
->bits3
.sampler_gen5
.end_of_thread
= eot
;
478 insn
->bits2
.send_gen5
.sfid
= BRW_MESSAGE_TARGET_SAMPLER
;
479 insn
->bits2
.send_gen5
.end_of_thread
= eot
;
480 } else if (intel
->is_g4x
) {
481 insn
->bits3
.sampler_g4x
.binding_table_index
= binding_table_index
;
482 insn
->bits3
.sampler_g4x
.sampler
= sampler
;
483 insn
->bits3
.sampler_g4x
.msg_type
= msg_type
;
484 insn
->bits3
.sampler_g4x
.response_length
= response_length
;
485 insn
->bits3
.sampler_g4x
.msg_length
= msg_length
;
486 insn
->bits3
.sampler_g4x
.end_of_thread
= eot
;
487 insn
->bits3
.sampler_g4x
.msg_target
= BRW_MESSAGE_TARGET_SAMPLER
;
489 insn
->bits3
.sampler
.binding_table_index
= binding_table_index
;
490 insn
->bits3
.sampler
.sampler
= sampler
;
491 insn
->bits3
.sampler
.msg_type
= msg_type
;
492 insn
->bits3
.sampler
.return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
493 insn
->bits3
.sampler
.response_length
= response_length
;
494 insn
->bits3
.sampler
.msg_length
= msg_length
;
495 insn
->bits3
.sampler
.end_of_thread
= eot
;
496 insn
->bits3
.sampler
.msg_target
= BRW_MESSAGE_TARGET_SAMPLER
;
502 static struct brw_instruction
*next_insn( struct brw_compile
*p
,
505 struct brw_instruction
*insn
;
507 assert(p
->nr_insn
+ 1 < BRW_EU_MAX_INSN
);
509 insn
= &p
->store
[p
->nr_insn
++];
510 memcpy(insn
, p
->current
, sizeof(*insn
));
512 /* Reset this one-shot flag:
515 if (p
->current
->header
.destreg__conditionalmod
) {
516 p
->current
->header
.destreg__conditionalmod
= 0;
517 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
520 insn
->header
.opcode
= opcode
;
525 static struct brw_instruction
*brw_alu1( struct brw_compile
*p
,
530 struct brw_instruction
*insn
= next_insn(p
, opcode
);
531 brw_set_dest(insn
, dest
);
532 brw_set_src0(insn
, src
);
536 static struct brw_instruction
*brw_alu2(struct brw_compile
*p
,
540 struct brw_reg src1
)
542 struct brw_instruction
*insn
= next_insn(p
, opcode
);
543 brw_set_dest(insn
, dest
);
544 brw_set_src0(insn
, src0
);
545 brw_set_src1(insn
, src1
);
550 /***********************************************************************
551 * Convenience routines.
554 struct brw_instruction *brw_##OP(struct brw_compile *p, \
555 struct brw_reg dest, \
556 struct brw_reg src0) \
558 return brw_alu1(p, BRW_OPCODE_##OP, dest, src0); \
562 struct brw_instruction *brw_##OP(struct brw_compile *p, \
563 struct brw_reg dest, \
564 struct brw_reg src0, \
565 struct brw_reg src1) \
567 return brw_alu2(p, BRW_OPCODE_##OP, dest, src0, src1); \
599 void brw_NOP(struct brw_compile
*p
)
601 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_NOP
);
602 brw_set_dest(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
603 brw_set_src0(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
604 brw_set_src1(insn
, brw_imm_ud(0x0));
611 /***********************************************************************
612 * Comparisons, if/else/endif
615 struct brw_instruction
*brw_JMPI(struct brw_compile
*p
,
620 struct brw_instruction
*insn
= brw_alu2(p
, BRW_OPCODE_JMPI
, dest
, src0
, src1
);
622 insn
->header
.execution_size
= 1;
623 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
624 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
626 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
631 /* EU takes the value from the flag register and pushes it onto some
632 * sort of a stack (presumably merging with any flag value already on
633 * the stack). Within an if block, the flags at the top of the stack
634 * control execution on each channel of the unit, eg. on each of the
635 * 16 pixel values in our wm programs.
637 * When the matching 'else' instruction is reached (presumably by
638 * countdown of the instruction count patched in by our ELSE/ENDIF
639 * functions), the relevent flags are inverted.
641 * When the matching 'endif' instruction is reached, the flags are
642 * popped off. If the stack is now empty, normal execution resumes.
644 * No attempt is made to deal with stack overflow (14 elements?).
646 struct brw_instruction
*brw_IF(struct brw_compile
*p
, GLuint execute_size
)
648 struct brw_instruction
*insn
;
650 if (p
->single_program_flow
) {
651 assert(execute_size
== BRW_EXECUTE_1
);
653 insn
= next_insn(p
, BRW_OPCODE_ADD
);
654 insn
->header
.predicate_inverse
= 1;
656 insn
= next_insn(p
, BRW_OPCODE_IF
);
659 /* Override the defaults for this instruction:
661 brw_set_dest(insn
, brw_ip_reg());
662 brw_set_src0(insn
, brw_ip_reg());
663 brw_set_src1(insn
, brw_imm_d(0x0));
665 insn
->header
.execution_size
= execute_size
;
666 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
667 insn
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
668 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
669 if (!p
->single_program_flow
)
670 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
672 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
678 struct brw_instruction
*brw_ELSE(struct brw_compile
*p
,
679 struct brw_instruction
*if_insn
)
681 struct intel_context
*intel
= &p
->brw
->intel
;
682 struct brw_instruction
*insn
;
688 if (p
->single_program_flow
) {
689 insn
= next_insn(p
, BRW_OPCODE_ADD
);
691 insn
= next_insn(p
, BRW_OPCODE_ELSE
);
694 brw_set_dest(insn
, brw_ip_reg());
695 brw_set_src0(insn
, brw_ip_reg());
696 brw_set_src1(insn
, brw_imm_d(0x0));
698 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
699 insn
->header
.execution_size
= if_insn
->header
.execution_size
;
700 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
701 if (!p
->single_program_flow
)
702 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
704 /* Patch the if instruction to point at this instruction.
706 if (p
->single_program_flow
) {
707 assert(if_insn
->header
.opcode
== BRW_OPCODE_ADD
);
709 if_insn
->bits3
.ud
= (insn
- if_insn
+ 1) * 16;
711 assert(if_insn
->header
.opcode
== BRW_OPCODE_IF
);
713 if_insn
->bits3
.if_else
.jump_count
= br
* (insn
- if_insn
);
714 if_insn
->bits3
.if_else
.pop_count
= 0;
715 if_insn
->bits3
.if_else
.pad0
= 0;
721 void brw_ENDIF(struct brw_compile
*p
,
722 struct brw_instruction
*patch_insn
)
724 struct intel_context
*intel
= &p
->brw
->intel
;
730 if (p
->single_program_flow
) {
731 /* In single program flow mode, there's no need to execute an ENDIF,
732 * since we don't need to do any stack operations, and if we're executing
733 * currently, we want to just continue executing.
735 struct brw_instruction
*next
= &p
->store
[p
->nr_insn
];
737 assert(patch_insn
->header
.opcode
== BRW_OPCODE_ADD
);
739 patch_insn
->bits3
.ud
= (next
- patch_insn
) * 16;
741 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_ENDIF
);
743 brw_set_dest(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
744 brw_set_src0(insn
, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD
));
745 brw_set_src1(insn
, brw_imm_d(0x0));
747 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
748 insn
->header
.execution_size
= patch_insn
->header
.execution_size
;
749 insn
->header
.mask_control
= BRW_MASK_ENABLE
;
750 insn
->header
.thread_control
= BRW_THREAD_SWITCH
;
752 assert(patch_insn
->bits3
.if_else
.jump_count
== 0);
754 /* Patch the if or else instructions to point at this or the next
755 * instruction respectively.
757 if (patch_insn
->header
.opcode
== BRW_OPCODE_IF
) {
758 /* Automagically turn it into an IFF:
760 patch_insn
->header
.opcode
= BRW_OPCODE_IFF
;
761 patch_insn
->bits3
.if_else
.jump_count
= br
* (insn
- patch_insn
+ 1);
762 patch_insn
->bits3
.if_else
.pop_count
= 0;
763 patch_insn
->bits3
.if_else
.pad0
= 0;
764 } else if (patch_insn
->header
.opcode
== BRW_OPCODE_ELSE
) {
765 patch_insn
->bits3
.if_else
.jump_count
= br
* (insn
- patch_insn
+ 1);
766 patch_insn
->bits3
.if_else
.pop_count
= 1;
767 patch_insn
->bits3
.if_else
.pad0
= 0;
772 /* Also pop item off the stack in the endif instruction:
774 insn
->bits3
.if_else
.jump_count
= 0;
775 insn
->bits3
.if_else
.pop_count
= 1;
776 insn
->bits3
.if_else
.pad0
= 0;
780 struct brw_instruction
*brw_BREAK(struct brw_compile
*p
, int pop_count
)
782 struct brw_instruction
*insn
;
783 insn
= next_insn(p
, BRW_OPCODE_BREAK
);
784 brw_set_dest(insn
, brw_ip_reg());
785 brw_set_src0(insn
, brw_ip_reg());
786 brw_set_src1(insn
, brw_imm_d(0x0));
787 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
788 insn
->header
.execution_size
= BRW_EXECUTE_8
;
789 /* insn->header.mask_control = BRW_MASK_DISABLE; */
790 insn
->bits3
.if_else
.pad0
= 0;
791 insn
->bits3
.if_else
.pop_count
= pop_count
;
795 struct brw_instruction
*brw_CONT(struct brw_compile
*p
, int pop_count
)
797 struct brw_instruction
*insn
;
798 insn
= next_insn(p
, BRW_OPCODE_CONTINUE
);
799 brw_set_dest(insn
, brw_ip_reg());
800 brw_set_src0(insn
, brw_ip_reg());
801 brw_set_src1(insn
, brw_imm_d(0x0));
802 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
803 insn
->header
.execution_size
= BRW_EXECUTE_8
;
804 /* insn->header.mask_control = BRW_MASK_DISABLE; */
805 insn
->bits3
.if_else
.pad0
= 0;
806 insn
->bits3
.if_else
.pop_count
= pop_count
;
812 struct brw_instruction
*brw_DO(struct brw_compile
*p
, GLuint execute_size
)
814 if (p
->single_program_flow
) {
815 return &p
->store
[p
->nr_insn
];
817 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_DO
);
819 /* Override the defaults for this instruction:
821 brw_set_dest(insn
, brw_null_reg());
822 brw_set_src0(insn
, brw_null_reg());
823 brw_set_src1(insn
, brw_null_reg());
825 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
826 insn
->header
.execution_size
= execute_size
;
827 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
828 /* insn->header.mask_control = BRW_MASK_ENABLE; */
829 /* insn->header.mask_control = BRW_MASK_DISABLE; */
837 struct brw_instruction
*brw_WHILE(struct brw_compile
*p
,
838 struct brw_instruction
*do_insn
)
840 struct intel_context
*intel
= &p
->brw
->intel
;
841 struct brw_instruction
*insn
;
847 if (p
->single_program_flow
)
848 insn
= next_insn(p
, BRW_OPCODE_ADD
);
850 insn
= next_insn(p
, BRW_OPCODE_WHILE
);
852 brw_set_dest(insn
, brw_ip_reg());
853 brw_set_src0(insn
, brw_ip_reg());
854 brw_set_src1(insn
, brw_imm_d(0x0));
856 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
858 if (p
->single_program_flow
) {
859 insn
->header
.execution_size
= BRW_EXECUTE_1
;
861 insn
->bits3
.d
= (do_insn
- insn
) * 16;
863 insn
->header
.execution_size
= do_insn
->header
.execution_size
;
865 assert(do_insn
->header
.opcode
== BRW_OPCODE_DO
);
866 insn
->bits3
.if_else
.jump_count
= br
* (do_insn
- insn
+ 1);
867 insn
->bits3
.if_else
.pop_count
= 0;
868 insn
->bits3
.if_else
.pad0
= 0;
871 /* insn->header.mask_control = BRW_MASK_ENABLE; */
873 /* insn->header.mask_control = BRW_MASK_DISABLE; */
874 p
->current
->header
.predicate_control
= BRW_PREDICATE_NONE
;
881 void brw_land_fwd_jump(struct brw_compile
*p
,
882 struct brw_instruction
*jmp_insn
)
884 struct intel_context
*intel
= &p
->brw
->intel
;
885 struct brw_instruction
*landing
= &p
->store
[p
->nr_insn
];
891 assert(jmp_insn
->header
.opcode
== BRW_OPCODE_JMPI
);
892 assert(jmp_insn
->bits1
.da1
.src1_reg_file
== BRW_IMMEDIATE_VALUE
);
894 jmp_insn
->bits3
.ud
= jmpi
* ((landing
- jmp_insn
) - 1);
899 /* To integrate with the above, it makes sense that the comparison
900 * instruction should populate the flag register. It might be simpler
901 * just to use the flag reg for most WM tasks?
903 void brw_CMP(struct brw_compile
*p
,
909 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_CMP
);
911 insn
->header
.destreg__conditionalmod
= conditional
;
912 brw_set_dest(insn
, dest
);
913 brw_set_src0(insn
, src0
);
914 brw_set_src1(insn
, src1
);
916 /* guess_execution_size(insn, src0); */
919 /* Make it so that future instructions will use the computed flag
920 * value until brw_set_predicate_control_flag_value() is called
923 if (dest
.file
== BRW_ARCHITECTURE_REGISTER_FILE
&&
925 p
->current
->header
.predicate_control
= BRW_PREDICATE_NORMAL
;
926 p
->flag_value
= 0xff;
930 /* Issue 'wait' instruction for n1, host could program MMIO
931 to wake up thread. */
932 void brw_WAIT (struct brw_compile
*p
)
934 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_WAIT
);
935 struct brw_reg src
= brw_notification_1_reg();
937 brw_set_dest(insn
, src
);
938 brw_set_src0(insn
, src
);
939 brw_set_src1(insn
, brw_null_reg());
940 insn
->header
.execution_size
= 0; /* must */
941 insn
->header
.predicate_control
= 0;
942 insn
->header
.compression_control
= 0;
946 /***********************************************************************
947 * Helpers for the various SEND message types:
950 /** Extended math function, float[8].
952 void brw_math( struct brw_compile
*p
,
961 struct intel_context
*intel
= &p
->brw
->intel
;
963 if (intel
->gen
>= 6) {
964 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_MATH
);
966 /* Math is the same ISA format as other opcodes, except that CondModifier
967 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
969 insn
->header
.destreg__conditionalmod
= function
;
971 brw_set_dest(insn
, dest
);
972 brw_set_src0(insn
, src
);
973 brw_set_src1(insn
, brw_null_reg());
975 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
976 GLuint msg_length
= (function
== BRW_MATH_FUNCTION_POW
) ? 2 : 1;
977 GLuint response_length
= (function
== BRW_MATH_FUNCTION_SINCOS
) ? 2 : 1;
978 /* Example code doesn't set predicate_control for send
981 insn
->header
.predicate_control
= 0;
982 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
984 brw_set_dest(insn
, dest
);
985 brw_set_src0(insn
, src
);
986 brw_set_math_message(p
->brw
,
988 msg_length
, response_length
,
990 BRW_MATH_INTEGER_UNSIGNED
,
998 * Extended math function, float[16].
999 * Use 2 send instructions.
1001 void brw_math_16( struct brw_compile
*p
,
1002 struct brw_reg dest
,
1009 struct intel_context
*intel
= &p
->brw
->intel
;
1010 struct brw_instruction
*insn
;
1011 GLuint msg_length
= (function
== BRW_MATH_FUNCTION_POW
) ? 2 : 1;
1012 GLuint response_length
= (function
== BRW_MATH_FUNCTION_SINCOS
) ? 2 : 1;
1014 if (intel
->gen
>= 6) {
1015 insn
= next_insn(p
, BRW_OPCODE_MATH
);
1017 /* Math is the same ISA format as other opcodes, except that CondModifier
1018 * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
1020 insn
->header
.destreg__conditionalmod
= function
;
1022 brw_set_dest(insn
, dest
);
1023 brw_set_src0(insn
, src
);
1024 brw_set_src1(insn
, brw_null_reg());
1028 /* First instruction:
1030 brw_push_insn_state(p
);
1031 brw_set_predicate_control_flag_value(p
, 0xff);
1032 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1034 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1035 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1037 brw_set_dest(insn
, dest
);
1038 brw_set_src0(insn
, src
);
1039 brw_set_math_message(p
->brw
,
1041 msg_length
, response_length
,
1043 BRW_MATH_INTEGER_UNSIGNED
,
1046 BRW_MATH_DATA_VECTOR
);
1048 /* Second instruction:
1050 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1051 insn
->header
.compression_control
= BRW_COMPRESSION_2NDHALF
;
1052 insn
->header
.destreg__conditionalmod
= msg_reg_nr
+1;
1054 brw_set_dest(insn
, offset(dest
,1));
1055 brw_set_src0(insn
, src
);
1056 brw_set_math_message(p
->brw
,
1058 msg_length
, response_length
,
1060 BRW_MATH_INTEGER_UNSIGNED
,
1063 BRW_MATH_DATA_VECTOR
);
1065 brw_pop_insn_state(p
);
1070 * Write block of 16 dwords/floats to the data port Render Cache scratch buffer.
1071 * Scratch offset should be a multiple of 64.
1072 * Used for register spilling.
1074 void brw_dp_WRITE_16( struct brw_compile
*p
,
1076 GLuint scratch_offset
)
1078 struct intel_context
*intel
= &p
->brw
->intel
;
1079 GLuint msg_reg_nr
= 1;
1081 brw_push_insn_state(p
);
1082 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1083 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1085 /* set message header global offset field (reg 0, element 2) */
1087 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D
),
1088 brw_imm_d(scratch_offset
));
1090 brw_pop_insn_state(p
);
1094 GLuint msg_length
= 3;
1095 struct brw_reg dest
;
1096 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1097 int send_commit_msg
;
1099 insn
->header
.predicate_control
= 0; /* XXX */
1100 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1101 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1103 /* Until gen6, writes followed by reads from the same location
1104 * are not guaranteed to be ordered unless write_commit is set.
1105 * If set, then a no-op write is issued to the destination
1106 * register to set a dependency, and a read from the destination
1107 * can be used to ensure the ordering.
1109 * For gen6, only writes between different threads need ordering
1110 * protection. Our use of DP writes is all about register
1111 * spilling within a thread.
1113 if (intel
->gen
>= 6) {
1114 dest
= retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW
);
1115 send_commit_msg
= 0;
1117 dest
= brw_uw16_grf(0, 0);
1118 send_commit_msg
= 1;
1121 brw_set_dest(insn
, dest
);
1122 brw_set_src0(insn
, src
);
1124 brw_set_dp_write_message(p
->brw
,
1126 255, /* binding table index (255=stateless) */
1127 BRW_DATAPORT_OWORD_BLOCK_4_OWORDS
, /* msg_control */
1128 BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE
, /* msg_type */
1130 0, /* pixel scoreboard */
1131 send_commit_msg
, /* response_length */
1139 * Read block of 16 dwords/floats from the data port Render Cache scratch buffer.
1140 * Scratch offset should be a multiple of 64.
1141 * Used for register spilling.
1143 void brw_dp_READ_16( struct brw_compile
*p
,
1144 struct brw_reg dest
,
1145 GLuint scratch_offset
)
1147 GLuint msg_reg_nr
= 1;
1149 brw_push_insn_state(p
);
1150 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1151 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1153 /* set message header global offset field (reg 0, element 2) */
1155 retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_D
),
1156 brw_imm_d(scratch_offset
));
1158 brw_pop_insn_state(p
);
1162 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1164 insn
->header
.predicate_control
= 0; /* XXX */
1165 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1166 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1168 brw_set_dest(insn
, dest
); /* UW? */
1169 brw_set_src0(insn
, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
));
1171 brw_set_dp_read_message(p
->brw
,
1173 255, /* binding table index (255=stateless) */
1174 BRW_DATAPORT_OWORD_BLOCK_4_OWORDS
,
1175 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1176 1, /* target cache (render/scratch) */
1178 2, /* response_length */
1185 * Read a float[4] vector from the data port Data Cache (const buffer).
1186 * Location (in buffer) should be a multiple of 16.
1187 * Used for fetching shader constants.
1188 * If relAddr is true, we'll do an indirect fetch using the address register.
1190 void brw_dp_READ_4( struct brw_compile
*p
,
1191 struct brw_reg dest
,
1194 GLuint bind_table_index
)
1196 /* XXX: relAddr not implemented */
1197 GLuint msg_reg_nr
= 1;
1200 brw_push_insn_state(p
);
1201 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1202 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1203 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1205 /* Setup MRF[1] with location/offset into const buffer */
1206 b
= brw_message_reg(msg_reg_nr
);
1207 b
= retype(b
, BRW_REGISTER_TYPE_UD
);
1208 /* XXX I think we're setting all the dwords of MRF[1] to 'location'.
1209 * when the docs say only dword[2] should be set. Hmmm. But it works.
1211 brw_MOV(p
, b
, brw_imm_ud(location
));
1212 brw_pop_insn_state(p
);
1216 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1218 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1219 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1220 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1221 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
1223 /* cast dest to a uword[8] vector */
1224 dest
= retype(vec8(dest
), BRW_REGISTER_TYPE_UW
);
1226 brw_set_dest(insn
, dest
);
1227 brw_set_src0(insn
, brw_null_reg());
1229 brw_set_dp_read_message(p
->brw
,
1232 0, /* msg_control (0 means 1 Oword) */
1233 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1234 0, /* source cache = data cache */
1236 1, /* response_length (1 Oword) */
1243 * Read float[4] constant(s) from VS constant buffer.
1244 * For relative addressing, two float[4] constants will be read into 'dest'.
1245 * Otherwise, one float[4] constant will be read into the lower half of 'dest'.
1247 void brw_dp_READ_4_vs(struct brw_compile
*p
,
1248 struct brw_reg dest
,
1250 GLuint bind_table_index
)
1252 struct brw_instruction
*insn
;
1253 GLuint msg_reg_nr
= 1;
1257 printf("vs const read msg, location %u, msg_reg_nr %d\n",
1258 location, msg_reg_nr);
1261 /* Setup MRF[1] with location/offset into const buffer */
1262 brw_push_insn_state(p
);
1263 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1264 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1265 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1267 /* XXX I think we're setting all the dwords of MRF[1] to 'location'.
1268 * when the docs say only dword[2] should be set. Hmmm. But it works.
1270 b
= brw_message_reg(msg_reg_nr
);
1271 b
= retype(b
, BRW_REGISTER_TYPE_UD
);
1272 /*b = get_element_ud(b, 2);*/
1273 brw_MOV(p
, b
, brw_imm_ud(location
));
1275 brw_pop_insn_state(p
);
1277 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1279 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1280 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1281 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1282 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
1284 brw_set_dest(insn
, dest
);
1285 brw_set_src0(insn
, brw_null_reg());
1287 brw_set_dp_read_message(p
->brw
,
1291 BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ
, /* msg_type */
1292 0, /* source cache = data cache */
1294 1, /* response_length (1 Oword) */
1299 * Read a float[4] constant per vertex from VS constant buffer, with
1300 * relative addressing.
1302 void brw_dp_READ_4_vs_relative(struct brw_compile
*p
,
1303 struct brw_reg dest
,
1304 struct brw_reg addr_reg
,
1306 GLuint bind_table_index
)
1308 struct intel_context
*intel
= &p
->brw
->intel
;
1311 /* Setup MRF[1] with offset into const buffer */
1312 brw_push_insn_state(p
);
1313 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1314 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1315 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
1317 /* M1.0 is block offset 0, M1.4 is block offset 1, all other
1320 brw_ADD(p
, retype(brw_message_reg(1), BRW_REGISTER_TYPE_UD
),
1321 addr_reg
, brw_imm_d(offset
));
1322 brw_pop_insn_state(p
);
1324 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1326 insn
->header
.predicate_control
= BRW_PREDICATE_NONE
;
1327 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1328 insn
->header
.destreg__conditionalmod
= 0;
1329 insn
->header
.mask_control
= BRW_MASK_DISABLE
;
1331 brw_set_dest(insn
, dest
);
1332 brw_set_src0(insn
, brw_vec8_grf(0, 0));
1334 if (intel
->gen
== 6)
1335 msg_type
= GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1336 else if (intel
->gen
== 5 || intel
->is_g4x
)
1337 msg_type
= G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1339 msg_type
= BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ
;
1341 brw_set_dp_read_message(p
->brw
,
1344 BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD
,
1346 0, /* source cache = data cache */
1348 1, /* response_length */
1354 void brw_fb_WRITE(struct brw_compile
*p
,
1356 struct brw_reg dest
,
1358 struct brw_reg src0
,
1359 GLuint binding_table_index
,
1361 GLuint response_length
,
1364 struct intel_context
*intel
= &p
->brw
->intel
;
1365 struct brw_instruction
*insn
;
1366 GLuint msg_control
, msg_type
;
1368 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1369 insn
->header
.predicate_control
= 0; /* XXX */
1370 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1372 if (intel
->gen
>= 6) {
1373 /* headerless version, just submit color payload */
1374 src0
= brw_message_reg(msg_reg_nr
);
1376 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6
;
1378 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1380 msg_type
= BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE
;
1383 if (dispatch_width
== 16)
1384 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
1386 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
1388 brw_set_dest(insn
, dest
);
1389 brw_set_src0(insn
, src0
);
1390 brw_set_dp_write_message(p
->brw
,
1392 binding_table_index
,
1396 1, /* pixel scoreboard */
1399 0 /* send_commit_msg */);
1404 * Texture sample instruction.
1405 * Note: the msg_type plus msg_length values determine exactly what kind
1406 * of sampling operation is performed. See volume 4, page 161 of docs.
1408 void brw_SAMPLE(struct brw_compile
*p
,
1409 struct brw_reg dest
,
1411 struct brw_reg src0
,
1412 GLuint binding_table_index
,
1416 GLuint response_length
,
1419 GLuint header_present
,
1422 GLboolean need_stall
= 0;
1424 if (writemask
== 0) {
1425 /*printf("%s: zero writemask??\n", __FUNCTION__); */
1429 /* Hardware doesn't do destination dependency checking on send
1430 * instructions properly. Add a workaround which generates the
1431 * dependency by other means. In practice it seems like this bug
1432 * only crops up for texture samples, and only where registers are
1433 * written by the send and then written again later without being
1434 * read in between. Luckily for us, we already track that
1435 * information and use it to modify the writemask for the
1436 * instruction, so that is a guide for whether a workaround is
1439 if (writemask
!= WRITEMASK_XYZW
) {
1440 GLuint dst_offset
= 0;
1441 GLuint i
, newmask
= 0, len
= 0;
1443 for (i
= 0; i
< 4; i
++) {
1444 if (writemask
& (1<<i
))
1448 for (; i
< 4; i
++) {
1449 if (!(writemask
& (1<<i
)))
1455 if (newmask
!= writemask
) {
1457 /* printf("need stall %x %x\n", newmask , writemask); */
1460 GLboolean dispatch_16
= GL_FALSE
;
1462 struct brw_reg m1
= brw_message_reg(msg_reg_nr
);
1464 guess_execution_size(p
->current
, dest
);
1465 if (p
->current
->header
.execution_size
== BRW_EXECUTE_16
)
1466 dispatch_16
= GL_TRUE
;
1468 newmask
= ~newmask
& WRITEMASK_XYZW
;
1470 brw_push_insn_state(p
);
1472 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1473 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1475 brw_MOV(p
, m1
, brw_vec8_grf(0,0));
1476 brw_MOV(p
, get_element_ud(m1
, 2), brw_imm_ud(newmask
<< 12));
1478 brw_pop_insn_state(p
);
1480 src0
= retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
);
1481 dest
= offset(dest
, dst_offset
);
1483 /* For 16-wide dispatch, masked channels are skipped in the
1484 * response. For 8-wide, masked channels still take up slots,
1485 * and are just not written to.
1488 response_length
= len
* 2;
1493 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1495 insn
->header
.predicate_control
= 0; /* XXX */
1496 insn
->header
.compression_control
= BRW_COMPRESSION_NONE
;
1497 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1499 brw_set_dest(insn
, dest
);
1500 brw_set_src0(insn
, src0
);
1501 brw_set_sampler_message(p
->brw
, insn
,
1502 binding_table_index
,
1513 struct brw_reg reg
= vec8(offset(dest
, response_length
-1));
1515 /* mov (8) r9.0<1>:f r9.0<8;8,1>:f { Align1 }
1517 brw_push_insn_state(p
);
1518 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1519 brw_MOV(p
, reg
, reg
);
1520 brw_pop_insn_state(p
);
1525 /* All these variables are pretty confusing - we might be better off
1526 * using bitmasks and macros for this, in the old style. Or perhaps
1527 * just having the caller instantiate the fields in dword3 itself.
1529 void brw_urb_WRITE(struct brw_compile
*p
,
1530 struct brw_reg dest
,
1532 struct brw_reg src0
,
1536 GLuint response_length
,
1538 GLboolean writes_complete
,
1542 struct intel_context
*intel
= &p
->brw
->intel
;
1543 struct brw_instruction
*insn
;
1545 /* Sandybridge doesn't have the implied move for SENDs,
1546 * and the first message register index comes from src0.
1548 if (intel
->gen
>= 6) {
1549 brw_push_insn_state(p
);
1550 brw_set_mask_control( p
, BRW_MASK_DISABLE
);
1551 brw_MOV(p
, brw_message_reg(msg_reg_nr
), src0
);
1552 brw_pop_insn_state(p
);
1553 src0
= brw_message_reg(msg_reg_nr
);
1556 insn
= next_insn(p
, BRW_OPCODE_SEND
);
1558 assert(msg_length
< BRW_MAX_MRF
);
1560 brw_set_dest(insn
, dest
);
1561 brw_set_src0(insn
, src0
);
1562 brw_set_src1(insn
, brw_imm_d(0));
1565 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1567 brw_set_urb_message(p
->brw
,
1579 void brw_ff_sync(struct brw_compile
*p
,
1580 struct brw_reg dest
,
1582 struct brw_reg src0
,
1584 GLuint response_length
,
1587 struct brw_instruction
*insn
= next_insn(p
, BRW_OPCODE_SEND
);
1589 brw_set_dest(insn
, dest
);
1590 brw_set_src0(insn
, src0
);
1591 brw_set_src1(insn
, brw_imm_d(0));
1593 insn
->header
.destreg__conditionalmod
= msg_reg_nr
;
1595 brw_set_ff_sync_message(p
->brw
,