src/mesa/drivers/dri/i965/brw_eu_validate.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /** @file brw_eu_validate.c
  25  *
  26  * This file implements a pass that validates shader assembly.
  27  */
  28
  29 #include "brw_eu.h"
  30
  31 /* We're going to do lots of string concatenation, so this should help. */
  32 struct string {
  33    char *str;
  34    size_t len;
  35 };
  36
  37 static void
  38 cat(struct string *dest, const struct string src)
  39 {
  40    dest->str = realloc(dest->str, dest->len + src.len + 1);
  41    memcpy(dest->str + dest->len, src.str, src.len);
  42    dest->str[dest->len + src.len] = '\0';
  43    dest->len = dest->len + src.len;
  44 }
  45 #define CAT(dest, src) cat(&dest, (struct string){src, strlen(src)})
  46
  47 #define error(str) "\tERROR: " str "\n"
  48
  49 #define ERROR_IF(cond, msg)          \
  50    do {                              \
  51       if (cond) {                    \
  52          CAT(error_msg, error(msg)); \
  53          valid = false;              \
  54       }                              \
  55    } while(0)
  56
  57 static bool
  58 src0_is_null(const struct brw_device_info *devinfo, const brw_inst *inst)
  59 {
  60    return brw_inst_src0_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
  61           brw_inst_src0_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
  62 }
  63
  64 static bool
  65 src1_is_null(const struct brw_device_info *devinfo, const brw_inst *inst)
  66 {
  67    return brw_inst_src1_reg_file(devinfo, inst) == BRW_ARCHITECTURE_REGISTER_FILE &&
  68           brw_inst_src1_da_reg_nr(devinfo, inst) == BRW_ARF_NULL;
  69 }
  70
  71 enum gen {
  72    GEN4  = (1 << 0),
  73    GEN45 = (1 << 1),
  74    GEN5  = (1 << 2),
  75    GEN6  = (1 << 3),
  76    GEN7  = (1 << 4),
  77    GEN75 = (1 << 5),
  78    GEN8  = (1 << 6),
  79    GEN9  = (1 << 7),
  80    GEN_ALL = ~0
  81 };
  82
  83 #define GEN_GE(gen) (~((gen) - 1) | gen)
  84 #define GEN_LE(gen) (((gen) - 1) | gen)
  85
  86 struct inst_info {
  87    enum gen gen;
  88 };
  89
  90 static const struct inst_info inst_info[128] = {
  91    [BRW_OPCODE_ILLEGAL] = {
  92       .gen = GEN_ALL,
  93    },
  94    [BRW_OPCODE_MOV] = {
  95       .gen = GEN_ALL,
  96    },
  97    [BRW_OPCODE_SEL] = {
  98       .gen = GEN_ALL,
  99    },
 100    [BRW_OPCODE_MOVI] = {
 101       .gen = GEN_GE(GEN45),
 102    },
 103    [BRW_OPCODE_NOT] = {
 104       .gen = GEN_ALL,
 105    },
 106    [BRW_OPCODE_AND] = {
 107       .gen = GEN_ALL,
 108    },
 109    [BRW_OPCODE_OR] = {
 110       .gen = GEN_ALL,
 111    },
 112    [BRW_OPCODE_XOR] = {
 113       .gen = GEN_ALL,
 114    },
 115    [BRW_OPCODE_SHR] = {
 116       .gen = GEN_ALL,
 117    },
 118    [BRW_OPCODE_SHL] = {
 119       .gen = GEN_ALL,
 120    },
 121    /* BRW_OPCODE_DIM / BRW_OPCODE_SMOV */
 122    /* Reserved - 11 */
 123    [BRW_OPCODE_ASR] = {
 124       .gen = GEN_ALL,
 125    },
 126    /* Reserved - 13-15 */
 127    [BRW_OPCODE_CMP] = {
 128       .gen = GEN_ALL,
 129    },
 130    [BRW_OPCODE_CMPN] = {
 131       .gen = GEN_ALL,
 132    },
 133    [BRW_OPCODE_CSEL] = {
 134       .gen = GEN_GE(GEN8),
 135    },
 136    [BRW_OPCODE_F32TO16] = {
 137       .gen = GEN7 | GEN75,
 138    },
 139    [BRW_OPCODE_F16TO32] = {
 140       .gen = GEN7 | GEN75,
 141    },
 142    /* Reserved - 21-22 */
 143    [BRW_OPCODE_BFREV] = {
 144       .gen = GEN_GE(GEN7),
 145    },
 146    [BRW_OPCODE_BFE] = {
 147       .gen = GEN_GE(GEN7),
 148    },
 149    [BRW_OPCODE_BFI1] = {
 150       .gen = GEN_GE(GEN7),
 151    },
 152    [BRW_OPCODE_BFI2] = {
 153       .gen = GEN_GE(GEN7),
 154    },
 155    /* Reserved - 27-31 */
 156    [BRW_OPCODE_JMPI] = {
 157       .gen = GEN_ALL,
 158    },
 159    /* BRW_OPCODE_BRD */
 160    [BRW_OPCODE_IF] = {
 161       .gen = GEN_ALL,
 162    },
 163    [BRW_OPCODE_IFF] = { /* also BRW_OPCODE_BRC */
 164       .gen = GEN_LE(GEN5),
 165    },
 166    [BRW_OPCODE_ELSE] = {
 167       .gen = GEN_ALL,
 168    },
 169    [BRW_OPCODE_ENDIF] = {
 170       .gen = GEN_ALL,
 171    },
 172    [BRW_OPCODE_DO] = { /* also BRW_OPCODE_CASE */
 173       .gen = GEN_LE(GEN5),
 174    },
 175    [BRW_OPCODE_WHILE] = {
 176       .gen = GEN_ALL,
 177    },
 178    [BRW_OPCODE_BREAK] = {
 179       .gen = GEN_ALL,
 180    },
 181    [BRW_OPCODE_CONTINUE] = {
 182       .gen = GEN_ALL,
 183    },
 184    [BRW_OPCODE_HALT] = {
 185       .gen = GEN_ALL,
 186    },
 187    /* BRW_OPCODE_CALLA */
 188    /* BRW_OPCODE_MSAVE / BRW_OPCODE_CALL */
 189    /* BRW_OPCODE_MREST / BRW_OPCODE_RET */
 190    /* BRW_OPCODE_PUSH / BRW_OPCODE_FORK / BRW_OPCODE_GOTO */
 191    /* BRW_OPCODE_POP */
 192    [BRW_OPCODE_WAIT] = {
 193       .gen = GEN_ALL,
 194    },
 195    [BRW_OPCODE_SEND] = {
 196       .gen = GEN_ALL,
 197    },
 198    [BRW_OPCODE_SENDC] = {
 199       .gen = GEN_ALL,
 200    },
 201    [BRW_OPCODE_SENDS] = {
 202       .gen = GEN_GE(GEN9),
 203    },
 204    [BRW_OPCODE_SENDSC] = {
 205       .gen = GEN_GE(GEN9),
 206    },
 207    /* Reserved 53-55 */
 208    [BRW_OPCODE_MATH] = {
 209       .gen = GEN_GE(GEN6),
 210    },
 211    /* Reserved 57-63 */
 212    [BRW_OPCODE_ADD] = {
 213       .gen = GEN_ALL,
 214    },
 215    [BRW_OPCODE_MUL] = {
 216       .gen = GEN_ALL,
 217    },
 218    [BRW_OPCODE_AVG] = {
 219       .gen = GEN_ALL,
 220    },
 221    [BRW_OPCODE_FRC] = {
 222       .gen = GEN_ALL,
 223    },
 224    [BRW_OPCODE_RNDU] = {
 225       .gen = GEN_ALL,
 226    },
 227    [BRW_OPCODE_RNDD] = {
 228       .gen = GEN_ALL,
 229    },
 230    [BRW_OPCODE_RNDE] = {
 231       .gen = GEN_ALL,
 232    },
 233    [BRW_OPCODE_RNDZ] = {
 234       .gen = GEN_ALL,
 235    },
 236    [BRW_OPCODE_MAC] = {
 237       .gen = GEN_ALL,
 238    },
 239    [BRW_OPCODE_MACH] = {
 240       .gen = GEN_ALL,
 241    },
 242    [BRW_OPCODE_LZD] = {
 243       .gen = GEN_ALL,
 244    },
 245    [BRW_OPCODE_FBH] = {
 246       .gen = GEN_GE(GEN7),
 247    },
 248    [BRW_OPCODE_FBL] = {
 249       .gen = GEN_GE(GEN7),
 250    },
 251    [BRW_OPCODE_CBIT] = {
 252       .gen = GEN_GE(GEN7),
 253    },
 254    [BRW_OPCODE_ADDC] = {
 255       .gen = GEN_GE(GEN7),
 256    },
 257    [BRW_OPCODE_SUBB] = {
 258       .gen = GEN_GE(GEN7),
 259    },
 260    [BRW_OPCODE_SAD2] = {
 261       .gen = GEN_ALL,
 262    },
 263    [BRW_OPCODE_SADA2] = {
 264       .gen = GEN_ALL,
 265    },
 266    /* Reserved 82-83 */
 267    [BRW_OPCODE_DP4] = {
 268       .gen = GEN_ALL,
 269    },
 270    [BRW_OPCODE_DPH] = {
 271       .gen = GEN_ALL,
 272    },
 273    [BRW_OPCODE_DP3] = {
 274       .gen = GEN_ALL,
 275    },
 276    [BRW_OPCODE_DP2] = {
 277       .gen = GEN_ALL,
 278    },
 279    /* Reserved 88 */
 280    [BRW_OPCODE_LINE] = {
 281       .gen = GEN_ALL,
 282    },
 283    [BRW_OPCODE_PLN] = {
 284       .gen = GEN_GE(GEN45),
 285    },
 286    [BRW_OPCODE_MAD] = {
 287       .gen = GEN_GE(GEN6),
 288    },
 289    [BRW_OPCODE_LRP] = {
 290       .gen = GEN_GE(GEN6),
 291    },
 292    /* Reserved 93-124 */
 293    /* BRW_OPCODE_NENOP */
 294    [BRW_OPCODE_NOP] = {
 295       .gen = GEN_ALL,
 296    },
 297 };
 298
 299 static unsigned
 300 num_sources_from_inst(const struct brw_device_info *devinfo,
 301                       const brw_inst *inst)
 302 {
 303    unsigned math_function;
 304
 305    if (brw_inst_opcode(devinfo, inst) == BRW_OPCODE_MATH) {
 306       math_function = brw_inst_math_function(devinfo, inst);
 307    } else if (devinfo->gen < 6 &&
 308               brw_inst_opcode(devinfo, inst) == BRW_OPCODE_SEND) {
 309       if (brw_inst_sfid(devinfo, inst) == BRW_SFID_MATH) {
 310          math_function = brw_inst_math_msg_function(devinfo, inst);
 311       } else {
 312          /* Send instructions are allowed to have null sources since they use
 313           * the base_mrf field to specify which message register source.
 314           */
 315          return 0;
 316       }
 317    } else {
 318       return opcode_descs[brw_inst_opcode(devinfo, inst)].nsrc;
 319    }
 320
 321    switch (math_function) {
 322    case BRW_MATH_FUNCTION_INV:
 323    case BRW_MATH_FUNCTION_LOG:
 324    case BRW_MATH_FUNCTION_EXP:
 325    case BRW_MATH_FUNCTION_SQRT:
 326    case BRW_MATH_FUNCTION_RSQ:
 327    case BRW_MATH_FUNCTION_SIN:
 328    case BRW_MATH_FUNCTION_COS:
 329    case BRW_MATH_FUNCTION_SINCOS:
 330    case GEN8_MATH_FUNCTION_INVM:
 331    case GEN8_MATH_FUNCTION_RSQRTM:
 332       return 1;
 333    case BRW_MATH_FUNCTION_FDIV:
 334    case BRW_MATH_FUNCTION_POW:
 335    case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER:
 336    case BRW_MATH_FUNCTION_INT_DIV_QUOTIENT:
 337    case BRW_MATH_FUNCTION_INT_DIV_REMAINDER:
 338       return 2;
 339    default:
 340       unreachable("not reached");
 341    }
 342 }
 343
 344 static enum gen
 345 gen_from_devinfo(const struct brw_device_info *devinfo)
 346 {
 347    switch (devinfo->gen) {
 348    case 4: return devinfo->is_g4x ? GEN45 : GEN4;
 349    case 5: return GEN5;
 350    case 6: return GEN6;
 351    case 7: return devinfo->is_haswell ? GEN75 : GEN7;
 352    case 8: return GEN8;
 353    case 9: return GEN9;
 354    default:
 355       unreachable("not reached");
 356    }
 357 }
 358
 359 static bool
 360 is_unsupported_inst(const struct brw_device_info *devinfo,
 361                     const brw_inst *inst)
 362 {
 363    enum gen gen = gen_from_devinfo(devinfo);
 364    return (inst_info[brw_inst_opcode(devinfo, inst)].gen & gen) == 0;
 365 }
 366
 367 bool
 368 brw_validate_instructions(const struct brw_codegen *p, int start_offset,
 369                           struct annotation_info *annotation)
 370 {
 371    const struct brw_device_info *devinfo = p->devinfo;
 372    const void *store = p->store + start_offset / 16;
 373    bool valid = true;
 374
 375    for (int src_offset = 0; src_offset < p->next_insn_offset - start_offset;
 376         src_offset += sizeof(brw_inst)) {
 377       struct string error_msg = { .str = NULL, .len = 0 };
 378       const brw_inst *inst = store + src_offset;
 379
 380       switch (num_sources_from_inst(devinfo, inst)) {
 381       case 3:
 382          /* Nothing to test. 3-src instructions can only have GRF sources, and
 383           * there's no bit to control the file.
 384           */
 385          break;
 386       case 2:
 387          ERROR_IF(src1_is_null(devinfo, inst), "src1 is null");
 388          /* fallthrough */
 389       case 1:
 390          ERROR_IF(src0_is_null(devinfo, inst), "src0 is null");
 391          break;
 392       case 0:
 393       default:
 394          break;
 395       }
 396
 397       ERROR_IF(is_unsupported_inst(devinfo, inst),
 398                "Instruction not supported on this Gen");
 399
 400       if (error_msg.str && annotation) {
 401          annotation_insert_error(annotation, src_offset, error_msg.str);
 402       }
 403       free(error_msg.str);
 404    }
 405
 406    return valid;
 407 }