2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 struct intel_context
*intel
= intel_context(ctx
);
122 if (using_new_fs
== -1)
123 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
125 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
126 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
128 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
129 void *mem_ctx
= talloc_new(NULL
);
133 talloc_free(shader
->ir
);
134 shader
->ir
= new(shader
) exec_list
;
135 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
137 do_mat_op_to_vec(shader
->ir
);
138 do_mod_to_fract(shader
->ir
);
139 do_div_to_mul_rcp(shader
->ir
);
140 do_sub_to_add_neg(shader
->ir
);
141 do_explog_to_explog2(shader
->ir
);
142 do_lower_texture_projection(shader
->ir
);
147 brw_do_channel_expressions(shader
->ir
);
148 brw_do_vector_splitting(shader
->ir
);
150 progress
= do_lower_jumps(shader
->ir
, true, true,
151 true, /* main return */
152 false, /* continue */
156 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
158 progress
= lower_noise(shader
->ir
) || progress
;
160 lower_variable_index_to_cond_assign(shader
->ir
,
162 GL_TRUE
, /* output */
164 GL_TRUE
/* uniform */
166 if (intel
->gen
== 6) {
167 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
171 validate_ir_tree(shader
->ir
);
173 reparent_ir(shader
->ir
, shader
->ir
);
174 talloc_free(mem_ctx
);
178 if (!_mesa_ir_link_shader(ctx
, prog
))
185 type_size(const struct glsl_type
*type
)
187 unsigned int size
, i
;
189 switch (type
->base_type
) {
192 case GLSL_TYPE_FLOAT
:
194 return type
->components();
195 case GLSL_TYPE_ARRAY
:
196 return type_size(type
->fields
.array
) * type
->length
;
197 case GLSL_TYPE_STRUCT
:
199 for (i
= 0; i
< type
->length
; i
++) {
200 size
+= type_size(type
->fields
.structure
[i
].type
);
203 case GLSL_TYPE_SAMPLER
:
204 /* Samplers take up no register space, since they're baked in at
209 assert(!"not reached");
216 /* Callers of this talloc-based new need not call delete. It's
217 * easier to just talloc_free 'ctx' (or any of its ancestors). */
218 static void* operator new(size_t size
, void *ctx
)
222 node
= talloc_size(ctx
, size
);
223 assert(node
!= NULL
);
231 this->reg_offset
= 0;
237 /** Generic unset register constructor. */
241 this->file
= BAD_FILE
;
244 /** Immediate value constructor. */
249 this->type
= BRW_REGISTER_TYPE_F
;
253 /** Immediate value constructor. */
258 this->type
= BRW_REGISTER_TYPE_D
;
262 /** Immediate value constructor. */
267 this->type
= BRW_REGISTER_TYPE_UD
;
271 /** Fixed brw_reg Immediate value constructor. */
272 fs_reg(struct brw_reg fixed_hw_reg
)
275 this->file
= FIXED_HW_REG
;
276 this->fixed_hw_reg
= fixed_hw_reg
;
277 this->type
= fixed_hw_reg
.type
;
280 fs_reg(enum register_file file
, int hw_reg
);
281 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
283 /** Register file: ARF, GRF, MRF, IMM. */
284 enum register_file file
;
285 /** virtual register number. 0 = fixed hw reg */
287 /** Offset within the virtual register. */
289 /** HW register number. Generally unset until register allocation. */
291 /** Register type. BRW_REGISTER_TYPE_* */
295 struct brw_reg fixed_hw_reg
;
297 /** Value for file == BRW_IMMMEDIATE_FILE */
305 static const fs_reg reg_undef
;
306 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
308 class fs_inst
: public exec_node
{
310 /* Callers of this talloc-based new need not call delete. It's
311 * easier to just talloc_free 'ctx' (or any of its ancestors). */
312 static void* operator new(size_t size
, void *ctx
)
316 node
= talloc_zero_size(ctx
, size
);
317 assert(node
!= NULL
);
324 this->opcode
= BRW_OPCODE_NOP
;
325 this->saturate
= false;
326 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
327 this->predicated
= false;
331 this->header_present
= false;
332 this->shadow_compare
= false;
343 this->opcode
= opcode
;
346 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
349 this->opcode
= opcode
;
354 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
357 this->opcode
= opcode
;
363 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
366 this->opcode
= opcode
;
373 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
378 int conditional_mod
; /**< BRW_CONDITIONAL_* */
380 int mlen
; /**< SEND message length */
382 int target
; /**< MRT target. */
388 * Annotation for the generated IR. One of the two can be set.
391 const char *annotation
;
395 class fs_visitor
: public ir_visitor
399 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
404 this->fp
= brw
->fragment_program
;
405 this->intel
= &brw
->intel
;
406 this->ctx
= &intel
->ctx
;
407 this->mem_ctx
= talloc_new(NULL
);
408 this->shader
= shader
;
410 this->variable_ht
= hash_table_ctor(0,
411 hash_table_pointer_hash
,
412 hash_table_pointer_compare
);
414 this->frag_color
= NULL
;
415 this->frag_data
= NULL
;
416 this->frag_depth
= NULL
;
417 this->first_non_payload_grf
= 0;
419 this->current_annotation
= NULL
;
420 this->annotation_string
= NULL
;
421 this->annotation_ir
= NULL
;
422 this->base_ir
= NULL
;
424 this->virtual_grf_sizes
= NULL
;
425 this->virtual_grf_next
= 1;
426 this->virtual_grf_array_size
= 0;
427 this->virtual_grf_def
= NULL
;
428 this->virtual_grf_use
= NULL
;
430 this->kill_emitted
= false;
435 talloc_free(this->mem_ctx
);
436 hash_table_dtor(this->variable_ht
);
439 fs_reg
*variable_storage(ir_variable
*var
);
440 int virtual_grf_alloc(int size
);
442 void visit(ir_variable
*ir
);
443 void visit(ir_assignment
*ir
);
444 void visit(ir_dereference_variable
*ir
);
445 void visit(ir_dereference_record
*ir
);
446 void visit(ir_dereference_array
*ir
);
447 void visit(ir_expression
*ir
);
448 void visit(ir_texture
*ir
);
449 void visit(ir_if
*ir
);
450 void visit(ir_constant
*ir
);
451 void visit(ir_swizzle
*ir
);
452 void visit(ir_return
*ir
);
453 void visit(ir_loop
*ir
);
454 void visit(ir_loop_jump
*ir
);
455 void visit(ir_discard
*ir
);
456 void visit(ir_call
*ir
);
457 void visit(ir_function
*ir
);
458 void visit(ir_function_signature
*ir
);
460 fs_inst
*emit(fs_inst inst
);
461 void assign_curb_setup();
462 void calculate_urb_setup();
463 void assign_urb_setup();
465 void assign_regs_trivial();
466 void calculate_live_intervals();
467 bool propagate_constants();
468 bool dead_code_eliminate();
469 bool virtual_grf_interferes(int a
, int b
);
470 void generate_code();
471 void generate_fb_write(fs_inst
*inst
);
472 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
473 struct brw_reg
*src
);
474 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
475 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
476 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
477 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
478 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
480 void emit_dummy_fs();
481 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
482 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
483 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
484 void emit_interpolation_setup_gen4();
485 void emit_interpolation_setup_gen6();
486 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
487 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
488 void emit_fb_writes();
489 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
490 const glsl_type
*type
, bool predicated
);
492 struct brw_reg
interp_reg(int location
, int channel
);
493 int setup_uniform_values(int loc
, const glsl_type
*type
);
494 void setup_builtin_uniform_values(ir_variable
*ir
);
496 struct brw_context
*brw
;
497 const struct gl_fragment_program
*fp
;
498 struct intel_context
*intel
;
500 struct brw_wm_compile
*c
;
501 struct brw_compile
*p
;
502 struct brw_shader
*shader
;
504 exec_list instructions
;
506 int *virtual_grf_sizes
;
507 int virtual_grf_next
;
508 int virtual_grf_array_size
;
509 int *virtual_grf_def
;
510 int *virtual_grf_use
;
512 struct hash_table
*variable_ht
;
513 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
514 int first_non_payload_grf
;
515 int urb_setup
[FRAG_ATTRIB_MAX
];
518 /** @{ debug annotation info */
519 const char *current_annotation
;
520 ir_instruction
*base_ir
;
521 const char **annotation_string
;
522 ir_instruction
**annotation_ir
;
527 /* Result of last visit() method. */
542 fs_visitor::virtual_grf_alloc(int size
)
544 if (virtual_grf_array_size
<= virtual_grf_next
) {
545 if (virtual_grf_array_size
== 0)
546 virtual_grf_array_size
= 16;
548 virtual_grf_array_size
*= 2;
549 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
550 int, virtual_grf_array_size
);
552 /* This slot is always unused. */
553 virtual_grf_sizes
[0] = 0;
555 virtual_grf_sizes
[virtual_grf_next
] = size
;
556 return virtual_grf_next
++;
559 /** Fixed HW reg constructor. */
560 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
564 this->hw_reg
= hw_reg
;
565 this->type
= BRW_REGISTER_TYPE_F
;
569 brw_type_for_base_type(const struct glsl_type
*type
)
571 switch (type
->base_type
) {
572 case GLSL_TYPE_FLOAT
:
573 return BRW_REGISTER_TYPE_F
;
576 return BRW_REGISTER_TYPE_D
;
578 return BRW_REGISTER_TYPE_UD
;
579 case GLSL_TYPE_ARRAY
:
580 case GLSL_TYPE_STRUCT
:
581 /* These should be overridden with the type of the member when
582 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
583 * way to trip up if we don't.
585 return BRW_REGISTER_TYPE_UD
;
587 assert(!"not reached");
588 return BRW_REGISTER_TYPE_F
;
592 /** Automatic reg constructor. */
593 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
598 this->reg
= v
->virtual_grf_alloc(type_size(type
));
599 this->reg_offset
= 0;
600 this->type
= brw_type_for_base_type(type
);
604 fs_visitor::variable_storage(ir_variable
*var
)
606 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
609 /* Our support for uniforms is piggy-backed on the struct
610 * gl_fragment_program, because that's where the values actually
611 * get stored, rather than in some global gl_shader_program uniform
615 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
617 unsigned int offset
= 0;
620 if (type
->is_matrix()) {
621 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
622 type
->vector_elements
,
625 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
626 offset
+= setup_uniform_values(loc
+ offset
, column
);
632 switch (type
->base_type
) {
633 case GLSL_TYPE_FLOAT
:
637 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
638 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
639 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
643 case GLSL_TYPE_STRUCT
:
644 for (unsigned int i
= 0; i
< type
->length
; i
++) {
645 offset
+= setup_uniform_values(loc
+ offset
,
646 type
->fields
.structure
[i
].type
);
650 case GLSL_TYPE_ARRAY
:
651 for (unsigned int i
= 0; i
< type
->length
; i
++) {
652 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
656 case GLSL_TYPE_SAMPLER
:
657 /* The sampler takes up a slot, but we don't use any values from it. */
661 assert(!"not reached");
667 /* Our support for builtin uniforms is even scarier than non-builtin.
668 * It sits on top of the PROG_STATE_VAR parameters that are
669 * automatically updated from GL context state.
672 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
674 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
676 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
677 statevar
= &_mesa_builtin_uniform_desc
[i
];
678 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
682 if (!statevar
->name
) {
684 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
689 if (ir
->type
->is_array()) {
690 array_count
= ir
->type
->length
;
695 for (int a
= 0; a
< array_count
; a
++) {
696 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
697 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
698 int tokens
[STATE_LENGTH
];
700 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
701 if (ir
->type
->is_array()) {
705 /* This state reference has already been setup by ir_to_mesa,
706 * but we'll get the same index back here.
708 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
709 (gl_state_index
*)tokens
);
710 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
712 /* Add each of the unique swizzles of the element as a
713 * parameter. This'll end up matching the expected layout of
714 * the array/matrix/structure we're trying to fill in.
717 for (unsigned int i
= 0; i
< 4; i
++) {
718 int swiz
= GET_SWZ(element
->swizzle
, i
);
719 if (swiz
== last_swiz
)
723 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
730 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
732 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
734 fs_reg neg_y
= this->pixel_y
;
738 if (ir
->pixel_center_integer
) {
739 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
741 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
746 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
747 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
749 fs_reg pixel_y
= this->pixel_y
;
750 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
752 if (!ir
->origin_upper_left
) {
753 pixel_y
.negate
= true;
754 offset
+= c
->key
.drawable_height
- 1.0;
757 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
762 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
763 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
766 /* gl_FragCoord.w: Already set up in emit_interpolation */
767 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
773 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
775 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
776 /* Interpolation is always in floating point regs. */
777 reg
->type
= BRW_REGISTER_TYPE_F
;
780 unsigned int array_elements
;
781 const glsl_type
*type
;
783 if (ir
->type
->is_array()) {
784 array_elements
= ir
->type
->length
;
785 if (array_elements
== 0) {
788 type
= ir
->type
->fields
.array
;
794 int location
= ir
->location
;
795 for (unsigned int i
= 0; i
< array_elements
; i
++) {
796 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
797 if (urb_setup
[location
] == -1) {
798 /* If there's no incoming setup data for this slot, don't
799 * emit interpolation for it.
801 attr
.reg_offset
+= type
->vector_elements
;
806 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
807 struct brw_reg interp
= interp_reg(location
, c
);
808 emit(fs_inst(FS_OPCODE_LINTERP
,
815 attr
.reg_offset
-= type
->vector_elements
;
817 if (intel
->gen
< 6) {
818 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
819 emit(fs_inst(BRW_OPCODE_MUL
,
834 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
836 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
838 /* The frontfacing comes in as a bit in the thread payload. */
839 if (intel
->gen
>= 6) {
840 emit(fs_inst(BRW_OPCODE_ASR
,
842 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
844 emit(fs_inst(BRW_OPCODE_NOT
,
847 emit(fs_inst(BRW_OPCODE_AND
,
852 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
853 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
854 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
857 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
861 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
862 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
869 fs_visitor::visit(ir_variable
*ir
)
873 if (variable_storage(ir
))
876 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
877 this->frag_color
= ir
;
878 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
879 this->frag_data
= ir
;
880 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
881 this->frag_depth
= ir
;
884 if (ir
->mode
== ir_var_in
) {
885 if (!strcmp(ir
->name
, "gl_FragCoord")) {
886 reg
= emit_fragcoord_interpolation(ir
);
887 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
888 reg
= emit_frontfacing_interpolation(ir
);
890 reg
= emit_general_interpolation(ir
);
893 hash_table_insert(this->variable_ht
, reg
, ir
);
897 if (ir
->mode
== ir_var_uniform
) {
898 int param_index
= c
->prog_data
.nr_params
;
900 if (!strncmp(ir
->name
, "gl_", 3)) {
901 setup_builtin_uniform_values(ir
);
903 setup_uniform_values(ir
->location
, ir
->type
);
906 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
910 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
912 hash_table_insert(this->variable_ht
, reg
, ir
);
916 fs_visitor::visit(ir_dereference_variable
*ir
)
918 fs_reg
*reg
= variable_storage(ir
->var
);
923 fs_visitor::visit(ir_dereference_record
*ir
)
925 const glsl_type
*struct_type
= ir
->record
->type
;
927 ir
->record
->accept(this);
929 unsigned int offset
= 0;
930 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
931 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
933 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
935 this->result
.reg_offset
+= offset
;
936 this->result
.type
= brw_type_for_base_type(ir
->type
);
940 fs_visitor::visit(ir_dereference_array
*ir
)
945 ir
->array
->accept(this);
946 index
= ir
->array_index
->as_constant();
948 element_size
= type_size(ir
->type
);
949 this->result
.type
= brw_type_for_base_type(ir
->type
);
952 assert(this->result
.file
== UNIFORM
||
953 (this->result
.file
== GRF
&&
954 this->result
.reg
!= 0));
955 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
957 assert(!"FINISHME: non-constant array element");
962 fs_visitor::visit(ir_expression
*ir
)
964 unsigned int operand
;
969 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
970 ir
->operands
[operand
]->accept(this);
971 if (this->result
.file
== BAD_FILE
) {
973 printf("Failed to get tree for expression operand:\n");
974 ir
->operands
[operand
]->accept(&v
);
977 op
[operand
] = this->result
;
979 /* Matrix expression operands should have been broken down to vector
980 * operations already.
982 assert(!ir
->operands
[operand
]->type
->is_matrix());
983 /* And then those vector operands should have been broken down to scalar.
985 assert(!ir
->operands
[operand
]->type
->is_vector());
988 /* Storage for our result. If our result goes into an assignment, it will
989 * just get copy-propagated out, so no worries.
991 this->result
= fs_reg(this, ir
->type
);
993 switch (ir
->operation
) {
994 case ir_unop_logic_not
:
995 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
998 op
[0].negate
= !op
[0].negate
;
999 this->result
= op
[0];
1003 this->result
= op
[0];
1006 temp
= fs_reg(this, ir
->type
);
1008 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
1010 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1011 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1012 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
1013 inst
->predicated
= true;
1015 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1016 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1017 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
1018 inst
->predicated
= true;
1022 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
1026 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
1029 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1033 assert(!"not reached: should be handled by ir_explog_to_explog2");
1036 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1039 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1043 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1046 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1050 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1053 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1057 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1060 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1063 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1067 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1068 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1069 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1071 case ir_binop_greater
:
1072 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1073 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1074 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1076 case ir_binop_lequal
:
1077 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1078 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1079 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1081 case ir_binop_gequal
:
1082 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1083 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1084 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1086 case ir_binop_equal
:
1087 case ir_binop_all_equal
: /* same as nequal for scalars */
1088 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1089 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1090 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1092 case ir_binop_nequal
:
1093 case ir_binop_any_nequal
: /* same as nequal for scalars */
1094 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1095 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1096 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1099 case ir_binop_logic_xor
:
1100 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1103 case ir_binop_logic_or
:
1104 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1107 case ir_binop_logic_and
:
1108 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1112 case ir_binop_cross
:
1114 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1118 assert(!"not reached: should be handled by lower_noise");
1122 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1126 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1132 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1135 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1139 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1140 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1143 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1146 op
[0].negate
= ~op
[0].negate
;
1147 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1148 this->result
.negate
= true;
1151 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1154 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1158 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1159 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1161 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1162 inst
->predicated
= true;
1165 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1166 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1168 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1169 inst
->predicated
= true;
1173 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1176 case ir_unop_bit_not
:
1178 case ir_binop_lshift
:
1179 case ir_binop_rshift
:
1180 case ir_binop_bit_and
:
1181 case ir_binop_bit_xor
:
1182 case ir_binop_bit_or
:
1183 assert(!"GLSL 1.30 features unsupported");
1189 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1190 const glsl_type
*type
, bool predicated
)
1192 switch (type
->base_type
) {
1193 case GLSL_TYPE_FLOAT
:
1194 case GLSL_TYPE_UINT
:
1196 case GLSL_TYPE_BOOL
:
1197 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1198 l
.type
= brw_type_for_base_type(type
);
1199 r
.type
= brw_type_for_base_type(type
);
1201 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1202 inst
->predicated
= predicated
;
1208 case GLSL_TYPE_ARRAY
:
1209 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1210 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1213 case GLSL_TYPE_STRUCT
:
1214 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1215 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1220 case GLSL_TYPE_SAMPLER
:
1224 assert(!"not reached");
1230 fs_visitor::visit(ir_assignment
*ir
)
1235 /* FINISHME: arrays on the lhs */
1236 ir
->lhs
->accept(this);
1239 ir
->rhs
->accept(this);
1242 assert(l
.file
!= BAD_FILE
);
1243 assert(r
.file
!= BAD_FILE
);
1245 if (ir
->condition
) {
1246 /* Get the condition bool into the predicate. */
1247 ir
->condition
->accept(this);
1248 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1249 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1252 if (ir
->lhs
->type
->is_scalar() ||
1253 ir
->lhs
->type
->is_vector()) {
1254 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1255 if (ir
->write_mask
& (1 << i
)) {
1256 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1258 inst
->predicated
= true;
1264 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1269 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1273 bool simd16
= false;
1276 if (ir
->shadow_comparitor
) {
1277 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1278 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1280 coordinate
.reg_offset
++;
1282 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1285 if (ir
->op
== ir_tex
) {
1286 /* There's no plain shadow compare message, so we use shadow
1287 * compare with a bias of 0.0.
1289 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1292 } else if (ir
->op
== ir_txb
) {
1293 ir
->lod_info
.bias
->accept(this);
1294 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1298 assert(ir
->op
== ir_txl
);
1299 ir
->lod_info
.lod
->accept(this);
1300 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1305 ir
->shadow_comparitor
->accept(this);
1306 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1308 } else if (ir
->op
== ir_tex
) {
1309 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1310 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1312 coordinate
.reg_offset
++;
1314 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1317 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1318 * instructions. We'll need to do SIMD16 here.
1320 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1322 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1323 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1325 coordinate
.reg_offset
++;
1328 /* The unused upper half. */
1332 /* lod/bias appears after u/v/r. */
1335 if (ir
->op
== ir_txb
) {
1336 ir
->lod_info
.bias
->accept(this);
1337 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1341 ir
->lod_info
.lod
->accept(this);
1342 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1347 /* The unused upper half. */
1350 /* Now, since we're doing simd16, the return is 2 interleaved
1351 * vec4s where the odd-indexed ones are junk. We'll need to move
1352 * this weirdness around to the expected layout.
1356 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1358 dst
.type
= BRW_REGISTER_TYPE_F
;
1361 fs_inst
*inst
= NULL
;
1364 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1367 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1370 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1374 assert(!"GLSL 1.30 features unsupported");
1380 for (int i
= 0; i
< 4; i
++) {
1381 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1382 orig_dst
.reg_offset
++;
1383 dst
.reg_offset
+= 2;
1391 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1393 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1394 * optional parameters like shadow comparitor or LOD bias. If
1395 * optional parameters aren't present, those base slots are
1396 * optional and don't need to be included in the message.
1398 * We don't fill in the unnecessary slots regardless, which may
1399 * look surprising in the disassembly.
1404 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1405 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1406 coordinate
.reg_offset
++;
1409 if (ir
->shadow_comparitor
) {
1410 mlen
= MAX2(mlen
, 4);
1412 ir
->shadow_comparitor
->accept(this);
1413 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1417 fs_inst
*inst
= NULL
;
1420 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1423 ir
->lod_info
.bias
->accept(this);
1424 mlen
= MAX2(mlen
, 4);
1425 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1428 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1431 ir
->lod_info
.lod
->accept(this);
1432 mlen
= MAX2(mlen
, 4);
1433 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1436 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1440 assert(!"GLSL 1.30 features unsupported");
1449 fs_visitor::visit(ir_texture
*ir
)
1451 fs_inst
*inst
= NULL
;
1453 ir
->coordinate
->accept(this);
1454 fs_reg coordinate
= this->result
;
1456 /* Should be lowered by do_lower_texture_projection */
1457 assert(!ir
->projector
);
1459 /* Writemasking doesn't eliminate channels on SIMD8 texture
1460 * samples, so don't worry about them.
1462 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1464 if (intel
->gen
< 5) {
1465 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1467 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1471 _mesa_get_sampler_uniform_value(ir
->sampler
,
1472 ctx
->Shader
.CurrentProgram
,
1473 &brw
->fragment_program
->Base
);
1474 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1478 if (ir
->shadow_comparitor
)
1479 inst
->shadow_compare
= true;
1481 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1482 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1484 for (int i
= 0; i
< 4; i
++) {
1485 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1486 fs_reg l
= swizzle_dst
;
1489 if (swiz
== SWIZZLE_ZERO
) {
1490 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1491 } else if (swiz
== SWIZZLE_ONE
) {
1492 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1495 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1496 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1499 this->result
= swizzle_dst
;
1504 fs_visitor::visit(ir_swizzle
*ir
)
1506 ir
->val
->accept(this);
1507 fs_reg val
= this->result
;
1509 if (ir
->type
->vector_elements
== 1) {
1510 this->result
.reg_offset
+= ir
->mask
.x
;
1514 fs_reg result
= fs_reg(this, ir
->type
);
1515 this->result
= result
;
1517 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1518 fs_reg channel
= val
;
1536 channel
.reg_offset
+= swiz
;
1537 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1538 result
.reg_offset
++;
1543 fs_visitor::visit(ir_discard
*ir
)
1545 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1547 assert(ir
->condition
== NULL
); /* FINISHME */
1549 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1550 kill_emitted
= true;
1554 fs_visitor::visit(ir_constant
*ir
)
1556 fs_reg
reg(this, ir
->type
);
1559 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1560 switch (ir
->type
->base_type
) {
1561 case GLSL_TYPE_FLOAT
:
1562 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1564 case GLSL_TYPE_UINT
:
1565 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1568 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1570 case GLSL_TYPE_BOOL
:
1571 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1574 assert(!"Non-float/uint/int/bool constant");
1581 fs_visitor::visit(ir_if
*ir
)
1585 /* Don't point the annotation at the if statement, because then it plus
1586 * the then and else blocks get printed.
1588 this->base_ir
= ir
->condition
;
1590 /* Generate the condition into the condition code. */
1591 ir
->condition
->accept(this);
1592 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1593 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1595 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1596 inst
->predicated
= true;
1598 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1599 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1605 if (!ir
->else_instructions
.is_empty()) {
1606 emit(fs_inst(BRW_OPCODE_ELSE
));
1608 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1609 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1616 emit(fs_inst(BRW_OPCODE_ENDIF
));
1620 fs_visitor::visit(ir_loop
*ir
)
1622 fs_reg counter
= reg_undef
;
1625 this->base_ir
= ir
->counter
;
1626 ir
->counter
->accept(this);
1627 counter
= *(variable_storage(ir
->counter
));
1630 this->base_ir
= ir
->from
;
1631 ir
->from
->accept(this);
1633 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1637 emit(fs_inst(BRW_OPCODE_DO
));
1640 this->base_ir
= ir
->to
;
1641 ir
->to
->accept(this);
1643 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1644 counter
, this->result
));
1646 case ir_binop_equal
:
1647 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1649 case ir_binop_nequal
:
1650 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1652 case ir_binop_gequal
:
1653 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1655 case ir_binop_lequal
:
1656 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1658 case ir_binop_greater
:
1659 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1662 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1665 assert(!"not reached: unknown loop condition");
1670 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1671 inst
->predicated
= true;
1674 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1675 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1681 if (ir
->increment
) {
1682 this->base_ir
= ir
->increment
;
1683 ir
->increment
->accept(this);
1684 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1687 emit(fs_inst(BRW_OPCODE_WHILE
));
1691 fs_visitor::visit(ir_loop_jump
*ir
)
1694 case ir_loop_jump::jump_break
:
1695 emit(fs_inst(BRW_OPCODE_BREAK
));
1697 case ir_loop_jump::jump_continue
:
1698 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1704 fs_visitor::visit(ir_call
*ir
)
1706 assert(!"FINISHME");
1710 fs_visitor::visit(ir_return
*ir
)
1712 assert(!"FINISHME");
1716 fs_visitor::visit(ir_function
*ir
)
1718 /* Ignore function bodies other than main() -- we shouldn't see calls to
1719 * them since they should all be inlined before we get to ir_to_mesa.
1721 if (strcmp(ir
->name
, "main") == 0) {
1722 const ir_function_signature
*sig
;
1725 sig
= ir
->matching_signature(&empty
);
1729 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1730 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1739 fs_visitor::visit(ir_function_signature
*ir
)
1741 assert(!"not reached");
1746 fs_visitor::emit(fs_inst inst
)
1748 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1751 list_inst
->annotation
= this->current_annotation
;
1752 list_inst
->ir
= this->base_ir
;
1754 this->instructions
.push_tail(list_inst
);
1759 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1761 fs_visitor::emit_dummy_fs()
1763 /* Everyone's favorite color. */
1764 emit(fs_inst(BRW_OPCODE_MOV
,
1767 emit(fs_inst(BRW_OPCODE_MOV
,
1770 emit(fs_inst(BRW_OPCODE_MOV
,
1773 emit(fs_inst(BRW_OPCODE_MOV
,
1778 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1783 /* The register location here is relative to the start of the URB
1784 * data. It will get adjusted to be a real location before
1785 * generate_code() time.
1788 fs_visitor::interp_reg(int location
, int channel
)
1790 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1791 int stride
= (channel
& 1) * 4;
1793 assert(urb_setup
[location
] != -1);
1795 return brw_vec1_grf(regnr
, stride
);
1798 /** Emits the interpolation for the varying inputs. */
1800 fs_visitor::emit_interpolation_setup_gen4()
1802 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1804 this->current_annotation
= "compute pixel centers";
1805 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1806 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1807 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1808 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1809 emit(fs_inst(BRW_OPCODE_ADD
,
1811 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1812 fs_reg(brw_imm_v(0x10101010))));
1813 emit(fs_inst(BRW_OPCODE_ADD
,
1815 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1816 fs_reg(brw_imm_v(0x11001100))));
1818 this->current_annotation
= "compute pixel deltas from v0";
1820 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1821 this->delta_y
= this->delta_x
;
1822 this->delta_y
.reg_offset
++;
1824 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1825 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1827 emit(fs_inst(BRW_OPCODE_ADD
,
1830 fs_reg(negate(brw_vec1_grf(1, 0)))));
1831 emit(fs_inst(BRW_OPCODE_ADD
,
1834 fs_reg(negate(brw_vec1_grf(1, 1)))));
1836 this->current_annotation
= "compute pos.w and 1/pos.w";
1837 /* Compute wpos.w. It's always in our setup, since it's needed to
1838 * interpolate the other attributes.
1840 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1841 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1842 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1843 /* Compute the pixel 1/W value from wpos.w. */
1844 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1845 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1846 this->current_annotation
= NULL
;
1849 /** Emits the interpolation for the varying inputs. */
1851 fs_visitor::emit_interpolation_setup_gen6()
1853 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1855 /* If the pixel centers end up used, the setup is the same as for gen4. */
1856 this->current_annotation
= "compute pixel centers";
1857 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1858 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1859 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1860 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1861 emit(fs_inst(BRW_OPCODE_ADD
,
1863 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1864 fs_reg(brw_imm_v(0x10101010))));
1865 emit(fs_inst(BRW_OPCODE_ADD
,
1867 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1868 fs_reg(brw_imm_v(0x11001100))));
1870 this->current_annotation
= "compute 1/pos.w";
1871 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1872 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1873 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1875 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1876 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1878 this->current_annotation
= NULL
;
1882 fs_visitor::emit_fb_writes()
1884 this->current_annotation
= "FB write header";
1885 GLboolean header_present
= GL_TRUE
;
1888 if (intel
->gen
>= 6 &&
1889 !this->kill_emitted
&&
1890 c
->key
.nr_color_regions
== 1) {
1891 header_present
= false;
1894 if (header_present
) {
1899 if (c
->key
.aa_dest_stencil_reg
) {
1900 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1901 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1904 /* Reserve space for color. It'll be filled in per MRT below. */
1908 if (c
->key
.source_depth_to_render_target
) {
1909 if (c
->key
.computes_depth
) {
1910 /* Hand over gl_FragDepth. */
1911 assert(this->frag_depth
);
1912 fs_reg depth
= *(variable_storage(this->frag_depth
));
1914 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1916 /* Pass through the payload depth. */
1917 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1918 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1922 if (c
->key
.dest_depth_reg
) {
1923 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1924 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1927 fs_reg color
= reg_undef
;
1928 if (this->frag_color
)
1929 color
= *(variable_storage(this->frag_color
));
1930 else if (this->frag_data
)
1931 color
= *(variable_storage(this->frag_data
));
1933 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1934 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1935 "FB write target %d",
1937 if (this->frag_color
|| this->frag_data
) {
1938 for (int i
= 0; i
< 4; i
++) {
1939 emit(fs_inst(BRW_OPCODE_MOV
,
1940 fs_reg(MRF
, color_mrf
+ i
),
1946 if (this->frag_color
)
1947 color
.reg_offset
-= 4;
1949 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1950 reg_undef
, reg_undef
));
1951 inst
->target
= target
;
1953 if (target
== c
->key
.nr_color_regions
- 1)
1955 inst
->header_present
= header_present
;
1958 if (c
->key
.nr_color_regions
== 0) {
1959 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1960 reg_undef
, reg_undef
));
1963 inst
->header_present
= header_present
;
1966 this->current_annotation
= NULL
;
1970 fs_visitor::generate_fb_write(fs_inst
*inst
)
1972 GLboolean eot
= inst
->eot
;
1973 struct brw_reg implied_header
;
1975 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1978 brw_push_insn_state(p
);
1979 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1980 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1982 if (inst
->header_present
) {
1983 if (intel
->gen
>= 6) {
1986 brw_vec8_grf(0, 0));
1987 implied_header
= brw_null_reg();
1989 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1994 brw_vec8_grf(1, 0));
1996 implied_header
= brw_null_reg();
1999 brw_pop_insn_state(p
);
2002 8, /* dispatch_width */
2003 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2013 fs_visitor::generate_linterp(fs_inst
*inst
,
2014 struct brw_reg dst
, struct brw_reg
*src
)
2016 struct brw_reg delta_x
= src
[0];
2017 struct brw_reg delta_y
= src
[1];
2018 struct brw_reg interp
= src
[2];
2021 delta_y
.nr
== delta_x
.nr
+ 1 &&
2022 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2023 brw_PLN(p
, dst
, interp
, delta_x
);
2025 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2026 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2031 fs_visitor::generate_math(fs_inst
*inst
,
2032 struct brw_reg dst
, struct brw_reg
*src
)
2036 switch (inst
->opcode
) {
2038 op
= BRW_MATH_FUNCTION_INV
;
2041 op
= BRW_MATH_FUNCTION_RSQ
;
2043 case FS_OPCODE_SQRT
:
2044 op
= BRW_MATH_FUNCTION_SQRT
;
2046 case FS_OPCODE_EXP2
:
2047 op
= BRW_MATH_FUNCTION_EXP
;
2049 case FS_OPCODE_LOG2
:
2050 op
= BRW_MATH_FUNCTION_LOG
;
2053 op
= BRW_MATH_FUNCTION_POW
;
2056 op
= BRW_MATH_FUNCTION_SIN
;
2059 op
= BRW_MATH_FUNCTION_COS
;
2062 assert(!"not reached: unknown math function");
2067 if (inst
->opcode
== FS_OPCODE_POW
) {
2068 brw_MOV(p
, brw_message_reg(3), src
[1]);
2073 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2074 BRW_MATH_SATURATE_NONE
,
2076 BRW_MATH_DATA_VECTOR
,
2077 BRW_MATH_PRECISION_FULL
);
2081 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2085 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2087 if (intel
->gen
>= 5) {
2088 switch (inst
->opcode
) {
2090 if (inst
->shadow_compare
) {
2091 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2093 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2097 if (inst
->shadow_compare
) {
2098 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2100 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2105 switch (inst
->opcode
) {
2107 /* Note that G45 and older determines shadow compare and dispatch width
2108 * from message length for most messages.
2110 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2111 if (inst
->shadow_compare
) {
2112 assert(inst
->mlen
== 5);
2114 assert(inst
->mlen
<= 6);
2118 if (inst
->shadow_compare
) {
2119 assert(inst
->mlen
== 5);
2120 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2122 assert(inst
->mlen
== 8);
2123 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2124 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2129 assert(msg_type
!= -1);
2131 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2140 retype(dst
, BRW_REGISTER_TYPE_UW
),
2142 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2143 SURF_INDEX_TEXTURE(inst
->sampler
),
2155 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2158 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2160 * and we're trying to produce:
2163 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2164 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2165 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2166 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2167 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2168 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2169 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2170 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2172 * and add another set of two more subspans if in 16-pixel dispatch mode.
2174 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2175 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2176 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2177 * between each other. We could probably do it like ddx and swizzle the right
2178 * order later, but bail for now and just produce
2179 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2182 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2184 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2185 BRW_REGISTER_TYPE_F
,
2186 BRW_VERTICAL_STRIDE_2
,
2188 BRW_HORIZONTAL_STRIDE_0
,
2189 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2190 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2191 BRW_REGISTER_TYPE_F
,
2192 BRW_VERTICAL_STRIDE_2
,
2194 BRW_HORIZONTAL_STRIDE_0
,
2195 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2196 brw_ADD(p
, dst
, src0
, negate(src1
));
2200 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2202 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2203 BRW_REGISTER_TYPE_F
,
2204 BRW_VERTICAL_STRIDE_4
,
2206 BRW_HORIZONTAL_STRIDE_0
,
2207 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2208 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2209 BRW_REGISTER_TYPE_F
,
2210 BRW_VERTICAL_STRIDE_4
,
2212 BRW_HORIZONTAL_STRIDE_0
,
2213 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2214 brw_ADD(p
, dst
, src0
, negate(src1
));
2218 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2220 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2221 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2223 brw_push_insn_state(p
);
2224 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2225 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2226 brw_AND(p
, g0
, temp
, g0
);
2227 brw_pop_insn_state(p
);
2231 fs_visitor::assign_curb_setup()
2233 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2234 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2236 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2237 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2238 fs_inst
*inst
= (fs_inst
*)iter
.get();
2240 for (unsigned int i
= 0; i
< 3; i
++) {
2241 if (inst
->src
[i
].file
== UNIFORM
) {
2242 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2243 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2247 inst
->src
[i
].file
= FIXED_HW_REG
;
2248 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2255 fs_visitor::calculate_urb_setup()
2257 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2262 /* Figure out where each of the incoming setup attributes lands. */
2263 if (intel
->gen
>= 6) {
2264 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2265 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2266 urb_setup
[i
] = urb_next
++;
2270 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2271 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2272 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2275 if (i
>= VERT_RESULT_VAR0
)
2276 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2277 else if (i
<= VERT_RESULT_TEX7
)
2283 urb_setup
[fp_index
] = urb_next
++;
2288 /* Each attribute is 4 setup channels, each of which is half a reg. */
2289 c
->prog_data
.urb_read_length
= urb_next
* 2;
2293 fs_visitor::assign_urb_setup()
2295 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2297 /* Offset all the urb_setup[] index by the actual position of the
2298 * setup regs, now that the location of the constants has been chosen.
2300 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2301 fs_inst
*inst
= (fs_inst
*)iter
.get();
2303 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2306 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2308 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2311 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2315 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2317 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2318 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2324 fs_visitor::assign_regs_trivial()
2327 int hw_reg_mapping
[this->virtual_grf_next
];
2330 hw_reg_mapping
[0] = 0;
2331 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2332 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2333 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2334 this->virtual_grf_sizes
[i
- 1]);
2336 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2338 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2339 fs_inst
*inst
= (fs_inst
*)iter
.get();
2341 assign_reg(hw_reg_mapping
, &inst
->dst
);
2342 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2343 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2346 this->grf_used
= last_grf
+ 1;
2350 fs_visitor::assign_regs()
2353 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2354 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2355 int class_sizes
[base_reg_count
];
2356 int class_count
= 0;
2357 int aligned_pair_class
= -1;
2359 /* Set up the register classes.
2361 * The base registers store a scalar value. For texture samples,
2362 * we get virtual GRFs composed of 4 contiguous hw register. For
2363 * structures and arrays, we store them as contiguous larger things
2364 * than that, though we should be able to do better most of the
2367 class_sizes
[class_count
++] = 1;
2368 if (brw
->has_pln
&& intel
->gen
< 6) {
2369 /* Always set up the (unaligned) pairs for gen5, so we can find
2370 * them for making the aligned pair class.
2372 class_sizes
[class_count
++] = 2;
2374 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2377 for (i
= 0; i
< class_count
; i
++) {
2378 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2381 if (i
== class_count
) {
2382 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2383 fprintf(stderr
, "Object too large to register allocate.\n");
2387 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2391 int ra_reg_count
= 0;
2392 int class_base_reg
[class_count
];
2393 int class_reg_count
[class_count
];
2394 int classes
[class_count
+ 1];
2396 for (int i
= 0; i
< class_count
; i
++) {
2397 class_base_reg
[i
] = ra_reg_count
;
2398 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2399 ra_reg_count
+= class_reg_count
[i
];
2402 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2403 for (int i
= 0; i
< class_count
; i
++) {
2404 classes
[i
] = ra_alloc_reg_class(regs
);
2406 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2407 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2410 /* Add conflicts between our contiguous registers aliasing
2411 * base regs and other register classes' contiguous registers
2412 * that alias base regs, or the base regs themselves for classes[0].
2414 for (int c
= 0; c
<= i
; c
++) {
2415 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2416 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2417 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2421 printf("%d/%d conflicts %d/%d\n",
2422 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2423 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2426 ra_add_reg_conflict(regs
,
2427 class_base_reg
[i
] + i_r
,
2428 class_base_reg
[c
] + c_r
);
2434 /* Add a special class for aligned pairs, which we'll put delta_x/y
2435 * in on gen5 so that we can do PLN.
2437 if (brw
->has_pln
&& intel
->gen
< 6) {
2438 int reg_count
= (base_reg_count
- 1) / 2;
2439 int unaligned_pair_class
= 1;
2440 assert(class_sizes
[unaligned_pair_class
] == 2);
2442 aligned_pair_class
= class_count
;
2443 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2444 class_base_reg
[aligned_pair_class
] = 0;
2445 class_reg_count
[aligned_pair_class
] = 0;
2446 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2448 for (int i
= 0; i
< reg_count
; i
++) {
2449 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2450 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2455 ra_set_finalize(regs
);
2457 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2458 this->virtual_grf_next
);
2459 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2462 ra_set_node_class(g
, 0, classes
[0]);
2464 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2465 for (int c
= 0; c
< class_count
; c
++) {
2466 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2467 if (aligned_pair_class
>= 0 &&
2468 this->delta_x
.reg
== i
) {
2469 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2471 ra_set_node_class(g
, i
, classes
[c
]);
2477 for (int j
= 1; j
< i
; j
++) {
2478 if (virtual_grf_interferes(i
, j
)) {
2479 ra_add_node_interference(g
, i
, j
);
2484 /* FINISHME: Handle spilling */
2485 if (!ra_allocate_no_spills(g
)) {
2486 fprintf(stderr
, "Failed to allocate registers.\n");
2491 /* Get the chosen virtual registers for each node, and map virtual
2492 * regs in the register classes back down to real hardware reg
2495 hw_reg_mapping
[0] = 0; /* unused */
2496 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2497 int reg
= ra_get_node_reg(g
, i
);
2500 for (int c
= 0; c
< class_count
; c
++) {
2501 if (reg
>= class_base_reg
[c
] &&
2502 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2503 hw_reg
= reg
- class_base_reg
[c
];
2508 assert(hw_reg
!= -1);
2509 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2510 last_grf
= MAX2(last_grf
,
2511 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2514 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2515 fs_inst
*inst
= (fs_inst
*)iter
.get();
2517 assign_reg(hw_reg_mapping
, &inst
->dst
);
2518 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2519 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2522 this->grf_used
= last_grf
+ 1;
2529 fs_visitor::calculate_live_intervals()
2531 int num_vars
= this->virtual_grf_next
;
2532 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2533 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2537 for (int i
= 0; i
< num_vars
; i
++) {
2543 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2544 fs_inst
*inst
= (fs_inst
*)iter
.get();
2546 if (inst
->opcode
== BRW_OPCODE_DO
) {
2547 if (loop_depth
++ == 0)
2549 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2552 if (loop_depth
== 0) {
2555 * Patches up any vars marked for use within the loop as
2556 * live until the end. This is conservative, as there
2557 * will often be variables defined and used inside the
2558 * loop but dead at the end of the loop body.
2560 for (int i
= 0; i
< num_vars
; i
++) {
2561 if (use
[i
] == loop_start
) {
2572 for (unsigned int i
= 0; i
< 3; i
++) {
2573 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2574 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2577 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2578 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2585 talloc_free(this->virtual_grf_def
);
2586 talloc_free(this->virtual_grf_use
);
2587 this->virtual_grf_def
= def
;
2588 this->virtual_grf_use
= use
;
2592 * Attempts to move immediate constants into the immediate
2593 * constant slot of following instructions.
2595 * Immediate constants are a bit tricky -- they have to be in the last
2596 * operand slot, you can't do abs/negate on them,
2600 fs_visitor::propagate_constants()
2602 bool progress
= false;
2604 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2605 fs_inst
*inst
= (fs_inst
*)iter
.get();
2607 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2609 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2610 inst
->dst
.type
!= inst
->src
[0].type
)
2613 /* Don't bother with cases where we should have had the
2614 * operation on the constant folded in GLSL already.
2619 /* Found a move of a constant to a GRF. Find anything else using the GRF
2620 * before it's written, and replace it with the constant if we can.
2622 exec_list_iterator scan_iter
= iter
;
2624 for (; scan_iter
.has_next(); scan_iter
.next()) {
2625 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2627 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2628 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2629 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2630 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2634 for (int i
= 2; i
>= 0; i
--) {
2635 if (scan_inst
->src
[i
].file
!= GRF
||
2636 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2637 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2640 /* Don't bother with cases where we should have had the
2641 * operation on the constant folded in GLSL already.
2643 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2646 switch (scan_inst
->opcode
) {
2647 case BRW_OPCODE_MOV
:
2648 scan_inst
->src
[i
] = inst
->src
[0];
2652 case BRW_OPCODE_MUL
:
2653 case BRW_OPCODE_ADD
:
2655 scan_inst
->src
[i
] = inst
->src
[0];
2657 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2658 /* Fit this constant in by commuting the operands */
2659 scan_inst
->src
[0] = scan_inst
->src
[1];
2660 scan_inst
->src
[1] = inst
->src
[0];
2663 case BRW_OPCODE_CMP
:
2665 scan_inst
->src
[i
] = inst
->src
[0];
2671 if (scan_inst
->dst
.file
== GRF
&&
2672 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2673 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2674 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2683 * Must be called after calculate_live_intervales() to remove unused
2684 * writes to registers -- register allocation will fail otherwise
2685 * because something deffed but not used won't be considered to
2686 * interfere with other regs.
2689 fs_visitor::dead_code_eliminate()
2691 bool progress
= false;
2692 int num_vars
= this->virtual_grf_next
;
2693 bool dead
[num_vars
];
2695 for (int i
= 0; i
< num_vars
; i
++) {
2696 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2697 * it writes dst then reads it as src.
2699 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2702 /* Mark off its interval so it won't interfere with anything. */
2703 this->virtual_grf_def
[i
] = -1;
2704 this->virtual_grf_use
[i
] = -1;
2708 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2709 fs_inst
*inst
= (fs_inst
*)iter
.get();
2711 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2721 fs_visitor::virtual_grf_interferes(int a
, int b
)
2723 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2724 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2726 /* For dead code, just check if the def interferes with the other range. */
2727 if (this->virtual_grf_use
[a
] == -1) {
2728 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2729 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2731 if (this->virtual_grf_use
[b
] == -1) {
2732 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2733 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2736 return start
<= end
;
2739 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2741 struct brw_reg brw_reg
;
2743 switch (reg
->file
) {
2747 brw_reg
= brw_vec8_reg(reg
->file
,
2749 brw_reg
= retype(brw_reg
, reg
->type
);
2752 switch (reg
->type
) {
2753 case BRW_REGISTER_TYPE_F
:
2754 brw_reg
= brw_imm_f(reg
->imm
.f
);
2756 case BRW_REGISTER_TYPE_D
:
2757 brw_reg
= brw_imm_d(reg
->imm
.i
);
2759 case BRW_REGISTER_TYPE_UD
:
2760 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2763 assert(!"not reached");
2768 brw_reg
= reg
->fixed_hw_reg
;
2771 /* Probably unused. */
2772 brw_reg
= brw_null_reg();
2775 assert(!"not reached");
2776 brw_reg
= brw_null_reg();
2780 brw_reg
= brw_abs(brw_reg
);
2782 brw_reg
= negate(brw_reg
);
2788 fs_visitor::generate_code()
2790 unsigned int annotation_len
= 0;
2791 int last_native_inst
= 0;
2792 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2793 int if_stack_depth
= 0, loop_stack_depth
= 0;
2794 int if_depth_in_loop
[16];
2796 if_depth_in_loop
[loop_stack_depth
] = 0;
2798 memset(&if_stack
, 0, sizeof(if_stack
));
2799 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2800 fs_inst
*inst
= (fs_inst
*)iter
.get();
2801 struct brw_reg src
[3], dst
;
2803 for (unsigned int i
= 0; i
< 3; i
++) {
2804 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2806 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2808 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2809 brw_set_predicate_control(p
, inst
->predicated
);
2811 switch (inst
->opcode
) {
2812 case BRW_OPCODE_MOV
:
2813 brw_MOV(p
, dst
, src
[0]);
2815 case BRW_OPCODE_ADD
:
2816 brw_ADD(p
, dst
, src
[0], src
[1]);
2818 case BRW_OPCODE_MUL
:
2819 brw_MUL(p
, dst
, src
[0], src
[1]);
2822 case BRW_OPCODE_FRC
:
2823 brw_FRC(p
, dst
, src
[0]);
2825 case BRW_OPCODE_RNDD
:
2826 brw_RNDD(p
, dst
, src
[0]);
2828 case BRW_OPCODE_RNDZ
:
2829 brw_RNDZ(p
, dst
, src
[0]);
2832 case BRW_OPCODE_AND
:
2833 brw_AND(p
, dst
, src
[0], src
[1]);
2836 brw_OR(p
, dst
, src
[0], src
[1]);
2838 case BRW_OPCODE_XOR
:
2839 brw_XOR(p
, dst
, src
[0], src
[1]);
2841 case BRW_OPCODE_NOT
:
2842 brw_NOT(p
, dst
, src
[0]);
2844 case BRW_OPCODE_ASR
:
2845 brw_ASR(p
, dst
, src
[0], src
[1]);
2847 case BRW_OPCODE_SHR
:
2848 brw_SHR(p
, dst
, src
[0], src
[1]);
2850 case BRW_OPCODE_SHL
:
2851 brw_SHL(p
, dst
, src
[0], src
[1]);
2854 case BRW_OPCODE_CMP
:
2855 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2857 case BRW_OPCODE_SEL
:
2858 brw_SEL(p
, dst
, src
[0], src
[1]);
2862 assert(if_stack_depth
< 16);
2863 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2864 if_depth_in_loop
[loop_stack_depth
]++;
2867 case BRW_OPCODE_ELSE
:
2868 if_stack
[if_stack_depth
- 1] =
2869 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2871 case BRW_OPCODE_ENDIF
:
2873 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2874 if_depth_in_loop
[loop_stack_depth
]--;
2878 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2879 if_depth_in_loop
[loop_stack_depth
] = 0;
2882 case BRW_OPCODE_BREAK
:
2883 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2884 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2886 case BRW_OPCODE_CONTINUE
:
2887 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2888 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2891 case BRW_OPCODE_WHILE
: {
2892 struct brw_instruction
*inst0
, *inst1
;
2895 if (intel
->gen
>= 5)
2898 assert(loop_stack_depth
> 0);
2900 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2901 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2902 while (inst0
> loop_stack
[loop_stack_depth
]) {
2904 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2905 inst0
->bits3
.if_else
.jump_count
== 0) {
2906 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2908 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2909 inst0
->bits3
.if_else
.jump_count
== 0) {
2910 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2918 case FS_OPCODE_SQRT
:
2919 case FS_OPCODE_EXP2
:
2920 case FS_OPCODE_LOG2
:
2924 generate_math(inst
, dst
, src
);
2926 case FS_OPCODE_LINTERP
:
2927 generate_linterp(inst
, dst
, src
);
2932 generate_tex(inst
, dst
, src
[0]);
2934 case FS_OPCODE_DISCARD
:
2935 generate_discard(inst
, dst
/* src0 == dst */);
2938 generate_ddx(inst
, dst
, src
[0]);
2941 generate_ddy(inst
, dst
, src
[0]);
2943 case FS_OPCODE_FB_WRITE
:
2944 generate_fb_write(inst
);
2947 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2948 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2949 brw_opcodes
[inst
->opcode
].name
);
2951 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2956 if (annotation_len
< p
->nr_insn
) {
2957 annotation_len
*= 2;
2958 if (annotation_len
< 16)
2959 annotation_len
= 16;
2961 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2965 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2971 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2972 this->annotation_string
[i
] = inst
->annotation
;
2973 this->annotation_ir
[i
] = inst
->ir
;
2975 last_native_inst
= p
->nr_insn
;
2980 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2982 struct brw_compile
*p
= &c
->func
;
2983 struct intel_context
*intel
= &brw
->intel
;
2984 GLcontext
*ctx
= &intel
->ctx
;
2985 struct brw_shader
*shader
= NULL
;
2986 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2994 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2995 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2996 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
3003 /* We always use 8-wide mode, at least for now. For one, flow
3004 * control only works in 8-wide. Also, when we're fragment shader
3005 * bound, we're almost always under register pressure as well, so
3006 * 8-wide would save us from the performance cliff of spilling
3009 c
->dispatch_width
= 8;
3011 if (INTEL_DEBUG
& DEBUG_WM
) {
3012 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3013 _mesa_print_ir(shader
->ir
, NULL
);
3017 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3019 fs_visitor
v(c
, shader
);
3024 v
.calculate_urb_setup();
3026 v
.emit_interpolation_setup_gen4();
3028 v
.emit_interpolation_setup_gen6();
3030 /* Generate FS IR for main(). (the visitor only descends into
3031 * functions called "main").
3033 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3034 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3040 v
.assign_curb_setup();
3041 v
.assign_urb_setup();
3047 v
.calculate_live_intervals();
3048 progress
= v
.propagate_constants() || progress
;
3049 progress
= v
.dead_code_eliminate() || progress
;
3053 v
.assign_regs_trivial();
3061 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3066 if (INTEL_DEBUG
& DEBUG_WM
) {
3067 const char *last_annotation_string
= NULL
;
3068 ir_instruction
*last_annotation_ir
= NULL
;
3070 printf("Native code for fragment shader %d:\n", prog
->Name
);
3071 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3072 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3073 last_annotation_ir
= v
.annotation_ir
[i
];
3074 if (last_annotation_ir
) {
3076 last_annotation_ir
->print();
3080 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3081 last_annotation_string
= v
.annotation_string
[i
];
3082 if (last_annotation_string
)
3083 printf(" %s\n", last_annotation_string
);
3085 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3090 c
->prog_data
.total_grf
= v
.grf_used
;
3091 c
->prog_data
.total_scratch
= 0;