2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "compiler/glsl_types.h"
42 #include "program/prog_parameter.h"
47 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
48 const fs_reg
*src
, unsigned sources
)
50 memset(this, 0, sizeof(*this));
52 this->src
= new fs_reg
[MAX2(sources
, 3)];
53 for (unsigned i
= 0; i
< sources
; i
++)
54 this->src
[i
] = src
[i
];
56 this->opcode
= opcode
;
58 this->sources
= sources
;
59 this->exec_size
= exec_size
;
62 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
64 assert(this->exec_size
!= 0);
66 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
68 /* This will be the case for almost all instructions. */
75 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
79 this->regs_written
= 0;
83 unreachable("Invalid destination register file");
86 this->writes_accumulator
= false;
91 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
94 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
96 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
99 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
101 init(opcode
, exec_size
, dst
, NULL
, 0);
104 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
107 const fs_reg src
[1] = { src0
};
108 init(opcode
, exec_size
, dst
, src
, 1);
111 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
112 const fs_reg
&src0
, const fs_reg
&src1
)
114 const fs_reg src
[2] = { src0
, src1
};
115 init(opcode
, exec_size
, dst
, src
, 2);
118 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
119 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
121 const fs_reg src
[3] = { src0
, src1
, src2
};
122 init(opcode
, exec_size
, dst
, src
, 3);
125 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
126 const fs_reg src
[], unsigned sources
)
128 init(opcode
, exec_width
, dst
, src
, sources
);
131 fs_inst::fs_inst(const fs_inst
&that
)
133 memcpy(this, &that
, sizeof(that
));
135 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
137 for (unsigned i
= 0; i
< that
.sources
; i
++)
138 this->src
[i
] = that
.src
[i
];
147 fs_inst::resize_sources(uint8_t num_sources
)
149 if (this->sources
!= num_sources
) {
150 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
152 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
153 src
[i
] = this->src
[i
];
157 this->sources
= num_sources
;
162 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
164 const fs_reg
&surf_index
,
165 const fs_reg
&varying_offset
,
166 uint32_t const_offset
)
168 /* We have our constant surface use a pitch of 4 bytes, so our index can
169 * be any component of a vector, and then we load 4 contiguous
170 * components starting from that.
172 * We break down the const_offset to a portion added to the variable
173 * offset and a portion done using reg_offset, which means that if you
174 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
175 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
176 * CSE can later notice that those loads are all the same and eliminate
177 * the redundant ones.
179 fs_reg vec4_offset
= vgrf(glsl_type::uint_type
);
180 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
182 /* The pull load message will load a vec4 (16 bytes). If we are loading
183 * a double this means we are only loading 2 elements worth of data.
184 * We also want to use a 32-bit data type for the dst of the load operation
185 * so other parts of the driver don't get confused about the size of the
188 fs_reg vec4_result
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
189 fs_inst
*inst
= bld
.emit(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
,
190 vec4_result
, surf_index
, vec4_offset
);
191 inst
->regs_written
= 4 * bld
.dispatch_width() / 8;
193 if (type_sz(dst
.type
) == 8) {
194 shuffle_32bit_load_result_to_64bit_data(
195 bld
, retype(vec4_result
, dst
.type
), vec4_result
, 2);
198 vec4_result
.type
= dst
.type
;
199 bld
.MOV(dst
, offset(vec4_result
, bld
,
200 (const_offset
& 0xf) / type_sz(vec4_result
.type
)));
204 * A helper for MOV generation for fixing up broken hardware SEND dependency
208 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
210 /* The caller always wants uncompressed to emit the minimal extra
211 * dependencies, and to avoid having to deal with aligning its regs to 2.
213 const fs_builder ubld
= bld
.annotate("send dependency resolve")
216 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
220 fs_inst::equals(fs_inst
*inst
) const
222 return (opcode
== inst
->opcode
&&
223 dst
.equals(inst
->dst
) &&
224 src
[0].equals(inst
->src
[0]) &&
225 src
[1].equals(inst
->src
[1]) &&
226 src
[2].equals(inst
->src
[2]) &&
227 saturate
== inst
->saturate
&&
228 predicate
== inst
->predicate
&&
229 conditional_mod
== inst
->conditional_mod
&&
230 mlen
== inst
->mlen
&&
231 base_mrf
== inst
->base_mrf
&&
232 target
== inst
->target
&&
234 header_size
== inst
->header_size
&&
235 shadow_compare
== inst
->shadow_compare
&&
236 exec_size
== inst
->exec_size
&&
237 offset
== inst
->offset
);
241 fs_inst::overwrites_reg(const fs_reg
®
) const
243 return reg
.in_range(dst
, regs_written
);
247 fs_inst::is_send_from_grf() const
250 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
251 case SHADER_OPCODE_SHADER_TIME_ADD
:
252 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
253 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
254 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
255 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
256 case SHADER_OPCODE_UNTYPED_ATOMIC
:
257 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
258 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
259 case SHADER_OPCODE_TYPED_ATOMIC
:
260 case SHADER_OPCODE_TYPED_SURFACE_READ
:
261 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
262 case SHADER_OPCODE_URB_WRITE_SIMD8
:
263 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
264 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
265 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
266 case SHADER_OPCODE_URB_READ_SIMD8
:
267 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
269 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
270 return src
[1].file
== VGRF
;
271 case FS_OPCODE_FB_WRITE
:
272 return src
[0].file
== VGRF
;
275 return src
[0].file
== VGRF
;
282 * Returns true if this instruction's sources and destinations cannot
283 * safely be the same register.
285 * In most cases, a register can be written over safely by the same
286 * instruction that is its last use. For a single instruction, the
287 * sources are dereferenced before writing of the destination starts
290 * However, there are a few cases where this can be problematic:
292 * - Virtual opcodes that translate to multiple instructions in the
293 * code generator: if src == dst and one instruction writes the
294 * destination before a later instruction reads the source, then
295 * src will have been clobbered.
297 * - SIMD16 compressed instructions with certain regioning (see below).
299 * The register allocator uses this information to set up conflicts between
300 * GRF sources and the destination.
303 fs_inst::has_source_and_destination_hazard() const
306 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
307 /* Multiple partial writes to the destination */
310 /* The SIMD16 compressed instruction
312 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
314 * is actually decoded in hardware as:
316 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
317 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
319 * Which is safe. However, if we have uniform accesses
320 * happening, we get into trouble:
322 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
323 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
325 * Now our destination for the first instruction overwrote the
326 * second instruction's src0, and we get garbage for those 8
327 * pixels. There's a similar issue for the pre-gen6
328 * pixel_x/pixel_y, which are registers of 16-bit values and thus
329 * would get stomped by the first decode as well.
331 if (exec_size
== 16) {
332 for (int i
= 0; i
< sources
; i
++) {
333 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
334 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
335 src
[i
].type
== BRW_REGISTER_TYPE_W
||
336 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
337 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
347 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
349 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
352 fs_reg reg
= this->src
[0];
353 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
356 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
359 for (int i
= 0; i
< this->sources
; i
++) {
360 reg
.type
= this->src
[i
].type
;
361 if (!this->src
[i
].equals(reg
))
364 if (i
< this->header_size
) {
367 reg
= horiz_offset(reg
, this->exec_size
);
375 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
377 if (devinfo
->gen
== 6 && is_math())
380 if (is_send_from_grf())
383 if (!backend_instruction::can_do_source_mods())
390 fs_inst::can_change_types() const
392 return dst
.type
== src
[0].type
&&
393 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
394 (opcode
== BRW_OPCODE_MOV
||
395 (opcode
== BRW_OPCODE_SEL
&&
396 dst
.type
== src
[1].type
&&
397 predicate
!= BRW_PREDICATE_NONE
&&
398 !src
[1].abs
&& !src
[1].negate
));
402 fs_inst::has_side_effects() const
404 return this->eot
|| backend_instruction::has_side_effects();
410 memset(this, 0, sizeof(*this));
414 /** Generic unset register constructor. */
418 this->file
= BAD_FILE
;
421 fs_reg::fs_reg(struct ::brw_reg reg
) :
424 this->reg_offset
= 0;
425 this->subreg_offset
= 0;
427 if (this->file
== IMM
&&
428 (this->type
!= BRW_REGISTER_TYPE_V
&&
429 this->type
!= BRW_REGISTER_TYPE_UV
&&
430 this->type
!= BRW_REGISTER_TYPE_VF
)) {
436 fs_reg::equals(const fs_reg
&r
) const
438 return (this->backend_reg::equals(r
) &&
439 subreg_offset
== r
.subreg_offset
&&
444 fs_reg::set_smear(unsigned subreg
)
446 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
447 subreg_offset
= subreg
* type_sz(type
);
453 fs_reg::is_contiguous() const
459 fs_reg::component_size(unsigned width
) const
461 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
464 return MAX2(width
* stride
, 1) * type_sz(type
);
468 type_size_scalar(const struct glsl_type
*type
)
470 unsigned int size
, i
;
472 switch (type
->base_type
) {
475 case GLSL_TYPE_FLOAT
:
477 return type
->components();
478 case GLSL_TYPE_DOUBLE
:
479 return type
->components() * 2;
480 case GLSL_TYPE_ARRAY
:
481 return type_size_scalar(type
->fields
.array
) * type
->length
;
482 case GLSL_TYPE_STRUCT
:
484 for (i
= 0; i
< type
->length
; i
++) {
485 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
488 case GLSL_TYPE_SAMPLER
:
489 /* Samplers take up no register space, since they're baked in at
493 case GLSL_TYPE_ATOMIC_UINT
:
495 case GLSL_TYPE_SUBROUTINE
:
497 case GLSL_TYPE_IMAGE
:
498 return BRW_IMAGE_PARAM_SIZE
;
500 case GLSL_TYPE_ERROR
:
501 case GLSL_TYPE_INTERFACE
:
502 case GLSL_TYPE_FUNCTION
:
503 unreachable("not reached");
509 /* Attribute arrays are loaded as one vec4 per element (or matrix column),
510 * except for double-precision types, which are loaded as one dvec4.
513 type_size_vs_input(const struct glsl_type
*type
)
515 if (type
->is_double()) {
516 return type_size_dvec4(type
);
518 return type_size_vec4(type
);
523 * Create a MOV to read the timestamp register.
525 * The caller is responsible for emitting the MOV. The return value is
526 * the destination of the MOV, with extra parameters set.
529 fs_visitor::get_timestamp(const fs_builder
&bld
)
531 assert(devinfo
->gen
>= 7);
533 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
536 BRW_REGISTER_TYPE_UD
));
538 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
540 /* We want to read the 3 fields we care about even if it's not enabled in
543 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
549 fs_visitor::emit_shader_time_begin()
551 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
553 /* We want only the low 32 bits of the timestamp. Since it's running
554 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
555 * which is plenty of time for our purposes. It is identical across the
556 * EUs, but since it's tracking GPU core speed it will increment at a
557 * varying rate as render P-states change.
559 shader_start_time
.set_smear(0);
563 fs_visitor::emit_shader_time_end()
565 /* Insert our code just before the final SEND with EOT. */
566 exec_node
*end
= this->instructions
.get_tail();
567 assert(end
&& ((fs_inst
*) end
)->eot
);
568 const fs_builder ibld
= bld
.annotate("shader time end")
569 .exec_all().at(NULL
, end
);
571 fs_reg shader_end_time
= get_timestamp(ibld
);
573 /* We only use the low 32 bits of the timestamp - see
574 * emit_shader_time_begin()).
576 * We could also check if render P-states have changed (or anything
577 * else that might disrupt timing) by setting smear to 2 and checking if
578 * that field is != 0.
580 shader_end_time
.set_smear(0);
582 /* Check that there weren't any timestamp reset events (assuming these
583 * were the only two timestamp reads that happened).
585 fs_reg reset
= shader_end_time
;
587 set_condmod(BRW_CONDITIONAL_Z
,
588 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
589 ibld
.IF(BRW_PREDICATE_NORMAL
);
591 fs_reg start
= shader_start_time
;
593 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
596 const fs_builder cbld
= ibld
.group(1, 0);
597 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
599 /* If there were no instructions between the two timestamp gets, the diff
600 * is 2 cycles. Remove that overhead, so I can forget about that when
601 * trying to determine the time taken for single instructions.
603 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
604 SHADER_TIME_ADD(cbld
, 0, diff
);
605 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
606 ibld
.emit(BRW_OPCODE_ELSE
);
607 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
608 ibld
.emit(BRW_OPCODE_ENDIF
);
612 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
613 int shader_time_subindex
,
616 int index
= shader_time_index
* 3 + shader_time_subindex
;
617 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
620 if (dispatch_width
== 8)
621 payload
= vgrf(glsl_type::uvec2_type
);
623 payload
= vgrf(glsl_type::uint_type
);
625 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
629 fs_visitor::vfail(const char *format
, va_list va
)
638 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
639 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
641 this->fail_msg
= msg
;
644 fprintf(stderr
, "%s", msg
);
649 fs_visitor::fail(const char *format
, ...)
653 va_start(va
, format
);
659 * Mark this program as impossible to compile with dispatch width greater
662 * During the SIMD8 compile (which happens first), we can detect and flag
663 * things that are unsupported in SIMD16+ mode, so the compiler can skip the
664 * SIMD16+ compile altogether.
666 * During a compile of dispatch width greater than n (if one happens anyway),
667 * this just calls fail().
670 fs_visitor::limit_dispatch_width(unsigned n
, const char *msg
)
672 if (dispatch_width
> n
) {
675 max_dispatch_width
= n
;
676 compiler
->shader_perf_log(log_data
,
677 "Shader dispatch width limited to SIMD%d: %s",
683 * Returns true if the instruction has a flag that means it won't
684 * update an entire destination register.
686 * For example, dead code elimination and live variable analysis want to know
687 * when a write to a variable screens off any preceding values that were in
691 fs_inst::is_partial_write() const
693 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
694 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
695 !this->dst
.is_contiguous() ||
696 this->dst
.subreg_offset
> 0);
700 fs_inst::components_read(unsigned i
) const
703 case FS_OPCODE_LINTERP
:
709 case FS_OPCODE_PIXEL_X
:
710 case FS_OPCODE_PIXEL_Y
:
714 case FS_OPCODE_FB_WRITE_LOGICAL
:
715 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
716 /* First/second FB write color. */
718 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
722 case SHADER_OPCODE_TEX_LOGICAL
:
723 case SHADER_OPCODE_TXD_LOGICAL
:
724 case SHADER_OPCODE_TXF_LOGICAL
:
725 case SHADER_OPCODE_TXL_LOGICAL
:
726 case SHADER_OPCODE_TXS_LOGICAL
:
727 case FS_OPCODE_TXB_LOGICAL
:
728 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
729 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
730 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
731 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
732 case SHADER_OPCODE_LOD_LOGICAL
:
733 case SHADER_OPCODE_TG4_LOGICAL
:
734 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
735 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
736 assert(src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
&&
737 src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
738 /* Texture coordinates. */
739 if (i
== TEX_LOGICAL_SRC_COORDINATE
)
740 return src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
741 /* Texture derivatives. */
742 else if ((i
== TEX_LOGICAL_SRC_LOD
|| i
== TEX_LOGICAL_SRC_LOD2
) &&
743 opcode
== SHADER_OPCODE_TXD_LOGICAL
)
744 return src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
745 /* Texture offset. */
746 else if (i
== TEX_LOGICAL_SRC_OFFSET_VALUE
)
749 else if (i
== TEX_LOGICAL_SRC_MCS
&& opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
754 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
755 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
756 assert(src
[3].file
== IMM
);
757 /* Surface coordinates. */
760 /* Surface operation source (ignored for reads). */
766 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
767 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
768 assert(src
[3].file
== IMM
&&
770 /* Surface coordinates. */
773 /* Surface operation source. */
779 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
780 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
781 assert(src
[3].file
== IMM
&&
783 const unsigned op
= src
[4].ud
;
784 /* Surface coordinates. */
787 /* Surface operation source. */
788 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
790 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
791 op
== BRW_AOP_PREDEC
))
803 fs_inst::regs_read(int arg
) const
806 case FS_OPCODE_FB_WRITE
:
807 case SHADER_OPCODE_URB_WRITE_SIMD8
:
808 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
809 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
810 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
811 case SHADER_OPCODE_URB_READ_SIMD8
:
812 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
813 case SHADER_OPCODE_UNTYPED_ATOMIC
:
814 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
815 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
816 case SHADER_OPCODE_TYPED_ATOMIC
:
817 case SHADER_OPCODE_TYPED_SURFACE_READ
:
818 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
819 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
824 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
825 /* The payload is actually stored in src1 */
830 case FS_OPCODE_LINTERP
:
835 case SHADER_OPCODE_LOAD_PAYLOAD
:
836 if (arg
< this->header_size
)
840 case CS_OPCODE_CS_TERMINATE
:
841 case SHADER_OPCODE_BARRIER
:
844 case SHADER_OPCODE_MOV_INDIRECT
:
846 assert(src
[2].file
== IMM
);
847 unsigned region_length
= src
[2].ud
;
849 if (src
[0].file
== UNIFORM
) {
850 assert(region_length
% 4 == 0);
851 return region_length
/ 4;
852 } else if (src
[0].file
== FIXED_GRF
) {
853 /* If the start of the region is not register aligned, then
854 * there's some portion of the register that's technically
855 * unread at the beginning.
857 * However, the register allocator works in terms of whole
858 * registers, and does not use subnr. It assumes that the
859 * read starts at the beginning of the register, and extends
860 * regs_read() whole registers beyond that.
862 * To compensate, we extend the region length to include this
863 * unread portion at the beginning.
866 region_length
+= src
[0].subnr
;
868 return DIV_ROUND_UP(region_length
, REG_SIZE
);
870 assert(!"Invalid register file");
876 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
881 switch (src
[arg
].file
) {
891 return DIV_ROUND_UP(components_read(arg
) *
892 src
[arg
].component_size(exec_size
),
895 unreachable("MRF registers are not allowed as sources");
901 /* Return the subset of flag registers that an instruction could
902 * potentially read or write based on the execution controls and flag
903 * subregister number of the instruction.
906 flag_mask(const fs_inst
*inst
)
908 const unsigned start
= inst
->flag_subreg
* 16 + inst
->group
;
909 const unsigned end
= start
+ inst
->exec_size
;
910 return ((1 << DIV_ROUND_UP(end
, 8)) - 1) & ~((1 << (start
/ 8)) - 1);
915 fs_inst::flags_read(const brw_device_info
*devinfo
) const
917 /* XXX - This doesn't consider explicit uses of the flag register as source
920 if (predicate
== BRW_PREDICATE_ALIGN1_ANYV
||
921 predicate
== BRW_PREDICATE_ALIGN1_ALLV
) {
922 /* The vertical predication modes combine corresponding bits from
923 * f0.0 and f1.0 on Gen7+, and f0.0 and f0.1 on older hardware.
925 const unsigned shift
= devinfo
->gen
>= 7 ? 4 : 2;
926 return flag_mask(this) << shift
| flag_mask(this);
927 } else if (predicate
) {
928 return flag_mask(this);
935 fs_inst::flags_written() const
937 /* XXX - This doesn't consider explicit uses of the flag register as
938 * destination region.
940 if ((conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
941 opcode
!= BRW_OPCODE_IF
&&
942 opcode
!= BRW_OPCODE_WHILE
)) ||
943 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
944 return flag_mask(this);
951 * Returns how many MRFs an FS opcode will write over.
953 * Note that this is not the 0 or 1 implied writes in an actual gen
954 * instruction -- the FS opcodes often generate MOVs in addition.
957 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
962 if (inst
->base_mrf
== -1)
965 switch (inst
->opcode
) {
966 case SHADER_OPCODE_RCP
:
967 case SHADER_OPCODE_RSQ
:
968 case SHADER_OPCODE_SQRT
:
969 case SHADER_OPCODE_EXP2
:
970 case SHADER_OPCODE_LOG2
:
971 case SHADER_OPCODE_SIN
:
972 case SHADER_OPCODE_COS
:
973 return 1 * dispatch_width
/ 8;
974 case SHADER_OPCODE_POW
:
975 case SHADER_OPCODE_INT_QUOTIENT
:
976 case SHADER_OPCODE_INT_REMAINDER
:
977 return 2 * dispatch_width
/ 8;
978 case SHADER_OPCODE_TEX
:
980 case SHADER_OPCODE_TXD
:
981 case SHADER_OPCODE_TXF
:
982 case SHADER_OPCODE_TXF_CMS
:
983 case SHADER_OPCODE_TXF_MCS
:
984 case SHADER_OPCODE_TG4
:
985 case SHADER_OPCODE_TG4_OFFSET
:
986 case SHADER_OPCODE_TXL
:
987 case SHADER_OPCODE_TXS
:
988 case SHADER_OPCODE_LOD
:
989 case SHADER_OPCODE_SAMPLEINFO
:
991 case FS_OPCODE_FB_WRITE
:
993 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
994 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
996 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
:
998 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1001 unreachable("not reached");
1006 fs_visitor::vgrf(const glsl_type
*const type
)
1008 int reg_width
= dispatch_width
/ 8;
1009 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
1010 brw_type_for_base_type(type
));
1013 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1018 this->type
= BRW_REGISTER_TYPE_F
;
1019 this->stride
= (file
== UNIFORM
? 0 : 1);
1022 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1028 this->stride
= (file
== UNIFORM
? 0 : 1);
1031 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1032 * This brings in those uniform definitions
1035 fs_visitor::import_uniforms(fs_visitor
*v
)
1037 this->push_constant_loc
= v
->push_constant_loc
;
1038 this->pull_constant_loc
= v
->pull_constant_loc
;
1039 this->uniforms
= v
->uniforms
;
1043 fs_visitor::emit_fragcoord_interpolation()
1045 assert(stage
== MESA_SHADER_FRAGMENT
);
1046 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1049 /* gl_FragCoord.x */
1050 bld
.MOV(wpos
, this->pixel_x
);
1051 wpos
= offset(wpos
, bld
, 1);
1053 /* gl_FragCoord.y */
1054 bld
.MOV(wpos
, this->pixel_y
);
1055 wpos
= offset(wpos
, bld
, 1);
1057 /* gl_FragCoord.z */
1058 if (devinfo
->gen
>= 6) {
1059 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1061 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1062 this->delta_xy
[BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
],
1063 interp_reg(VARYING_SLOT_POS
, 2));
1065 wpos
= offset(wpos
, bld
, 1);
1067 /* gl_FragCoord.w: Already set up in emit_interpolation */
1068 bld
.MOV(wpos
, this->wpos_w
);
1073 static enum brw_barycentric_mode
1074 barycentric_mode(enum glsl_interp_mode mode
,
1075 bool is_centroid
, bool is_sample
)
1079 /* Barycentric modes don't make sense for flat inputs. */
1080 assert(mode
!= INTERP_MODE_FLAT
);
1083 bary
= BRW_BARYCENTRIC_PERSPECTIVE_SAMPLE
;
1084 } else if (is_centroid
) {
1085 bary
= BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
;
1087 bary
= BRW_BARYCENTRIC_PERSPECTIVE_PIXEL
;
1090 if (mode
== INTERP_MODE_NOPERSPECTIVE
)
1093 return (enum brw_barycentric_mode
) bary
;
1097 * Turn one of the two CENTROID barycentric modes into PIXEL mode.
1099 static enum brw_barycentric_mode
1100 centroid_to_pixel(enum brw_barycentric_mode bary
)
1102 assert(bary
== BRW_BARYCENTRIC_PERSPECTIVE_CENTROID
||
1103 bary
== BRW_BARYCENTRIC_NONPERSPECTIVE_CENTROID
);
1104 return (enum brw_barycentric_mode
) ((unsigned) bary
- 1);
1108 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1109 const glsl_type
*type
,
1110 glsl_interp_mode interpolation_mode
,
1111 int *location
, bool mod_centroid
,
1114 assert(stage
== MESA_SHADER_FRAGMENT
);
1115 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1117 if (type
->is_array() || type
->is_matrix()) {
1118 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1119 const unsigned length
= glsl_get_length(type
);
1121 for (unsigned i
= 0; i
< length
; i
++) {
1122 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1123 location
, mod_centroid
, mod_sample
);
1125 } else if (type
->is_record()) {
1126 for (unsigned i
= 0; i
< type
->length
; i
++) {
1127 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1128 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1129 location
, mod_centroid
, mod_sample
);
1132 assert(type
->is_scalar() || type
->is_vector());
1134 if (prog_data
->urb_setup
[*location
] == -1) {
1135 /* If there's no incoming setup data for this slot, don't
1136 * emit interpolation for it.
1138 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1143 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1145 if (interpolation_mode
== INTERP_MODE_FLAT
) {
1146 /* Constant interpolation (flat shading) case. The SF has
1147 * handed us defined values in only the constant offset
1148 * field of the setup reg.
1150 unsigned vector_elements
= type
->vector_elements
;
1152 /* Data starts at suboffet 3 in 32-bit units (12 bytes), so it is not
1153 * 64-bit aligned and the current implementation fails to read the
1154 * data properly. Instead, when there is a double input varying,
1155 * read it as vector of floats with twice the number of components.
1157 if (attr
->type
== BRW_REGISTER_TYPE_DF
) {
1158 vector_elements
*= 2;
1159 attr
->type
= BRW_REGISTER_TYPE_F
;
1161 for (unsigned int i
= 0; i
< vector_elements
; i
++) {
1162 struct brw_reg interp
= interp_reg(*location
, i
);
1163 interp
= suboffset(interp
, 3);
1164 interp
.type
= attr
->type
;
1165 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1166 *attr
= offset(*attr
, bld
, 1);
1169 /* Smooth/noperspective interpolation case. */
1170 enum brw_barycentric_mode bary
=
1171 barycentric_mode(interpolation_mode
, mod_centroid
, mod_sample
);
1173 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1174 fs_reg
interp(interp_reg(*location
, i
));
1175 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1176 /* Get the pixel/sample mask into f0 so that we know
1177 * which pixels are lit. Then, for each channel that is
1178 * unlit, replace the centroid data with non-centroid
1181 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1184 inst
= bld
.emit(FS_OPCODE_LINTERP
, *attr
,
1185 delta_xy
[centroid_to_pixel(bary
)], interp
);
1186 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1187 inst
->predicate_inverse
= true;
1188 if (devinfo
->has_pln
)
1189 inst
->no_dd_clear
= true;
1191 inst
= bld
.emit(FS_OPCODE_LINTERP
, *attr
,
1192 delta_xy
[bary
], interp
);
1193 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1194 inst
->predicate_inverse
= false;
1195 if (devinfo
->has_pln
)
1196 inst
->no_dd_check
= true;
1199 bld
.emit(FS_OPCODE_LINTERP
, *attr
, delta_xy
[bary
], interp
);
1201 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_MODE_SMOOTH
) {
1202 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1204 *attr
= offset(*attr
, bld
, 1);
1212 fs_visitor::emit_frontfacing_interpolation()
1214 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1216 if (devinfo
->gen
>= 6) {
1217 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1218 * a boolean result from this (~0/true or 0/false).
1220 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1221 * this task in only one instruction:
1222 * - a negation source modifier will flip the bit; and
1223 * - a W -> D type conversion will sign extend the bit into the high
1224 * word of the destination.
1226 * An ASR 15 fills the low word of the destination.
1228 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1231 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1233 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1234 * a boolean result from this (1/true or 0/false).
1236 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1237 * the negation source modifier to flip it. Unfortunately the SHR
1238 * instruction only operates on UD (or D with an abs source modifier)
1239 * sources without negation.
1241 * Instead, use ASR (which will give ~0/true or 0/false).
1243 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1246 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1253 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1255 assert(stage
== MESA_SHADER_FRAGMENT
);
1256 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1257 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1259 if (wm_prog_data
->persample_dispatch
) {
1260 /* Convert int_sample_pos to floating point */
1261 bld
.MOV(dst
, int_sample_pos
);
1262 /* Scale to the range [0, 1] */
1263 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1266 /* From ARB_sample_shading specification:
1267 * "When rendering to a non-multisample buffer, or if multisample
1268 * rasterization is disabled, gl_SamplePosition will always be
1271 bld
.MOV(dst
, brw_imm_f(0.5f
));
1276 fs_visitor::emit_samplepos_setup()
1278 assert(devinfo
->gen
>= 6);
1280 const fs_builder abld
= bld
.annotate("compute sample position");
1281 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1283 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1284 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1286 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1287 * mode will be enabled.
1289 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1290 * R31.1:0 Position Offset X/Y for Slot[3:0]
1291 * R31.3:2 Position Offset X/Y for Slot[7:4]
1294 * The X, Y sample positions come in as bytes in thread payload. So, read
1295 * the positions using vstride=16, width=8, hstride=2.
1297 struct brw_reg sample_pos_reg
=
1298 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1299 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1301 if (dispatch_width
== 8) {
1302 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1304 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1305 abld
.half(1).MOV(half(int_sample_x
, 1),
1306 fs_reg(suboffset(sample_pos_reg
, 16)));
1308 /* Compute gl_SamplePosition.x */
1309 compute_sample_position(pos
, int_sample_x
);
1310 pos
= offset(pos
, abld
, 1);
1311 if (dispatch_width
== 8) {
1312 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1314 abld
.half(0).MOV(half(int_sample_y
, 0),
1315 fs_reg(suboffset(sample_pos_reg
, 1)));
1316 abld
.half(1).MOV(half(int_sample_y
, 1),
1317 fs_reg(suboffset(sample_pos_reg
, 17)));
1319 /* Compute gl_SamplePosition.y */
1320 compute_sample_position(pos
, int_sample_y
);
1325 fs_visitor::emit_sampleid_setup()
1327 assert(stage
== MESA_SHADER_FRAGMENT
);
1328 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1329 assert(devinfo
->gen
>= 6);
1331 const fs_builder abld
= bld
.annotate("compute sample id");
1332 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1334 if (!key
->multisample_fbo
) {
1335 /* As per GL_ARB_sample_shading specification:
1336 * "When rendering to a non-multisample buffer, or if multisample
1337 * rasterization is disabled, gl_SampleID will always be zero."
1339 abld
.MOV(*reg
, brw_imm_d(0));
1340 } else if (devinfo
->gen
>= 8) {
1341 /* Sample ID comes in as 4-bit numbers in g1.0:
1343 * 15:12 Slot 3 SampleID (only used in SIMD16)
1344 * 11:8 Slot 2 SampleID (only used in SIMD16)
1345 * 7:4 Slot 1 SampleID
1346 * 3:0 Slot 0 SampleID
1348 * Each slot corresponds to four channels, so we want to replicate each
1349 * half-byte value to 4 channels in a row:
1351 * dst+0: .7 .6 .5 .4 .3 .2 .1 .0
1352 * 7:4 7:4 7:4 7:4 3:0 3:0 3:0 3:0
1354 * dst+1: .7 .6 .5 .4 .3 .2 .1 .0 (if SIMD16)
1355 * 15:12 15:12 15:12 15:12 11:8 11:8 11:8 11:8
1357 * First, we read g1.0 with a <1,8,0>UB region, causing the first 8
1358 * channels to read the first byte (7:0), and the second group of 8
1359 * channels to read the second byte (15:8). Then, we shift right by
1360 * a vector immediate of <4, 4, 4, 4, 0, 0, 0, 0>, moving the slot 1 / 3
1361 * values into place. Finally, we AND with 0xf to keep the low nibble.
1363 * shr(16) tmp<1>W g1.0<1,8,0>B 0x44440000:V
1364 * and(16) dst<1>D tmp<8,8,1>W 0xf:W
1366 * TODO: These payload bits exist on Gen7 too, but they appear to always
1367 * be zero, so this code fails to work. We should find out why.
1369 fs_reg
tmp(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1371 abld
.SHR(tmp
, fs_reg(stride(retype(brw_vec1_grf(1, 0),
1372 BRW_REGISTER_TYPE_B
), 1, 8, 0)),
1373 brw_imm_v(0x44440000));
1374 abld
.AND(*reg
, tmp
, brw_imm_w(0xf));
1376 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1378 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1380 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1381 * 8x multisampling, subspan 0 will represent sample N (where N
1382 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1383 * 7. We can find the value of N by looking at R0.0 bits 7:6
1384 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1385 * (since samples are always delivered in pairs). That is, we
1386 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1387 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1388 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1389 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1390 * populating a temporary variable with the sequence (0, 1, 2, 3),
1391 * and then reading from it using vstride=1, width=4, hstride=0.
1392 * These computations hold good for 4x multisampling as well.
1394 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1395 * the first four slots are sample 0 of subspan 0; the next four
1396 * are sample 1 of subspan 0; the third group is sample 0 of
1397 * subspan 1, and finally sample 1 of subspan 1.
1400 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1401 * accomodate 16x MSAA.
1403 abld
.exec_all().group(1, 0)
1404 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1406 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1408 /* This works for both SIMD8 and SIMD16 */
1409 abld
.exec_all().group(4, 0).MOV(t2
, brw_imm_v(0x3210));
1411 /* This special instruction takes care of setting vstride=1,
1412 * width=4, hstride=0 of t2 during an ADD instruction.
1414 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1421 fs_visitor::emit_samplemaskin_setup()
1423 assert(stage
== MESA_SHADER_FRAGMENT
);
1424 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1425 assert(devinfo
->gen
>= 6);
1427 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1429 fs_reg
coverage_mask(retype(brw_vec8_grf(payload
.sample_mask_in_reg
, 0),
1430 BRW_REGISTER_TYPE_D
));
1432 if (wm_prog_data
->persample_dispatch
) {
1433 /* gl_SampleMaskIn[] comes from two sources: the input coverage mask,
1434 * and a mask representing which sample is being processed by the
1435 * current shader invocation.
1437 * From the OES_sample_variables specification:
1438 * "When per-sample shading is active due to the use of a fragment input
1439 * qualified by "sample" or due to the use of the gl_SampleID or
1440 * gl_SamplePosition variables, only the bit for the current sample is
1441 * set in gl_SampleMaskIn."
1443 const fs_builder abld
= bld
.annotate("compute gl_SampleMaskIn");
1445 if (nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
1446 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
1448 fs_reg one
= vgrf(glsl_type::int_type
);
1449 fs_reg enabled_mask
= vgrf(glsl_type::int_type
);
1450 abld
.MOV(one
, brw_imm_d(1));
1451 abld
.SHL(enabled_mask
, one
, nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
]);
1452 abld
.AND(*reg
, enabled_mask
, coverage_mask
);
1454 /* In per-pixel mode, the coverage mask is sufficient. */
1455 *reg
= coverage_mask
;
1461 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1463 if (!src
.abs
&& !src
.negate
)
1466 fs_reg temp
= bld
.vgrf(src
.type
);
1473 fs_visitor::emit_discard_jump()
1475 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1477 /* For performance, after a discard, jump to the end of the
1478 * shader if all relevant channels have been discarded.
1480 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1481 discard_jump
->flag_subreg
= 1;
1483 discard_jump
->predicate
= (dispatch_width
== 8)
1484 ? BRW_PREDICATE_ALIGN1_ANY8H
1485 : BRW_PREDICATE_ALIGN1_ANY16H
;
1486 discard_jump
->predicate_inverse
= true;
1490 fs_visitor::emit_gs_thread_end()
1492 assert(stage
== MESA_SHADER_GEOMETRY
);
1494 struct brw_gs_prog_data
*gs_prog_data
=
1495 (struct brw_gs_prog_data
*) prog_data
;
1497 if (gs_compile
->control_data_header_size_bits
> 0) {
1498 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1501 const fs_builder abld
= bld
.annotate("thread end");
1504 if (gs_prog_data
->static_vertex_count
!= -1) {
1505 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1506 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1507 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1508 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1509 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1512 /* Delete now dead instructions. */
1513 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1519 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1523 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1524 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1525 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1528 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1529 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1530 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1531 sources
[1] = this->final_gs_vertex_count
;
1532 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1533 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1541 fs_visitor::assign_curb_setup()
1543 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1545 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1546 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1547 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1548 if (inst
->src
[i
].file
== UNIFORM
) {
1549 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1551 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1552 constant_nr
= push_constant_loc
[uniform_nr
];
1554 /* Section 5.11 of the OpenGL 4.1 spec says:
1555 * "Out-of-bounds reads return undefined values, which include
1556 * values from other variables of the active program or zero."
1557 * Just return the first push constant.
1562 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1565 brw_reg
.abs
= inst
->src
[i
].abs
;
1566 brw_reg
.negate
= inst
->src
[i
].negate
;
1568 assert(inst
->src
[i
].stride
== 0);
1569 inst
->src
[i
] = byte_offset(
1570 retype(brw_reg
, inst
->src
[i
].type
),
1571 inst
->src
[i
].subreg_offset
);
1576 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1577 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1581 fs_visitor::calculate_urb_setup()
1583 assert(stage
== MESA_SHADER_FRAGMENT
);
1584 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1585 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1587 memset(prog_data
->urb_setup
, -1,
1588 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1591 /* Figure out where each of the incoming setup attributes lands. */
1592 if (devinfo
->gen
>= 6) {
1593 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1594 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1595 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1596 * first 16 varying inputs, so we can put them wherever we want.
1597 * Just put them in order.
1599 * This is useful because it means that (a) inputs not used by the
1600 * fragment shader won't take up valuable register space, and (b) we
1601 * won't have to recompile the fragment shader if it gets paired with
1602 * a different vertex (or geometry) shader.
1604 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1605 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1606 BITFIELD64_BIT(i
)) {
1607 prog_data
->urb_setup
[i
] = urb_next
++;
1611 bool include_vue_header
=
1612 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1614 /* We have enough input varyings that the SF/SBE pipeline stage can't
1615 * arbitrarily rearrange them to suit our whim; we have to put them
1616 * in an order that matches the output of the previous pipeline stage
1617 * (geometry or vertex shader).
1619 struct brw_vue_map prev_stage_vue_map
;
1620 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1621 key
->input_slots_valid
,
1622 nir
->info
.separate_shader
);
1624 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1626 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1627 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1629 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1630 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1631 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1632 BITFIELD64_BIT(varying
))) {
1633 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1636 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1639 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1640 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1641 /* Point size is packed into the header, not as a general attribute */
1642 if (i
== VARYING_SLOT_PSIZ
)
1645 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1646 /* The back color slot is skipped when the front color is
1647 * also written to. In addition, some slots can be
1648 * written in the vertex shader and not read in the
1649 * fragment shader. So the register number must always be
1650 * incremented, mapped or not.
1652 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1653 prog_data
->urb_setup
[i
] = urb_next
;
1659 * It's a FS only attribute, and we did interpolation for this attribute
1660 * in SF thread. So, count it here, too.
1662 * See compile_sf_prog() for more info.
1664 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1665 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1668 prog_data
->num_varying_inputs
= urb_next
;
1672 fs_visitor::assign_urb_setup()
1674 assert(stage
== MESA_SHADER_FRAGMENT
);
1675 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1677 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1679 /* Offset all the urb_setup[] index by the actual position of the
1680 * setup regs, now that the location of the constants has been chosen.
1682 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1683 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1684 assert(inst
->src
[1].file
== FIXED_GRF
);
1685 inst
->src
[1].nr
+= urb_start
;
1688 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1689 assert(inst
->src
[0].file
== FIXED_GRF
);
1690 inst
->src
[0].nr
+= urb_start
;
1694 /* Each attribute is 4 setup channels, each of which is half a reg. */
1695 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1699 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1701 for (int i
= 0; i
< inst
->sources
; i
++) {
1702 if (inst
->src
[i
].file
== ATTR
) {
1703 int grf
= payload
.num_regs
+
1704 prog_data
->curb_read_length
+
1706 inst
->src
[i
].reg_offset
;
1708 /* As explained at brw_reg_from_fs_reg, From the Haswell PRM:
1710 * VertStride must be used to cross GRF register boundaries. This
1711 * rule implies that elements within a 'Width' cannot cross GRF
1714 * So, for registers that are large enough, we have to split the exec
1715 * size in two and trust the compression state to sort it out.
1717 unsigned total_size
= inst
->exec_size
*
1718 inst
->src
[i
].stride
*
1719 type_sz(inst
->src
[i
].type
);
1721 assert(total_size
<= 2 * REG_SIZE
);
1722 const unsigned exec_size
=
1723 (total_size
<= REG_SIZE
) ? inst
->exec_size
: inst
->exec_size
/ 2;
1725 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : exec_size
;
1726 struct brw_reg reg
=
1727 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1728 inst
->src
[i
].subreg_offset
),
1729 exec_size
* inst
->src
[i
].stride
,
1730 width
, inst
->src
[i
].stride
);
1731 reg
.abs
= inst
->src
[i
].abs
;
1732 reg
.negate
= inst
->src
[i
].negate
;
1740 fs_visitor::assign_vs_urb_setup()
1742 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1744 assert(stage
== MESA_SHADER_VERTEX
);
1746 /* Each attribute is 4 regs. */
1747 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attribute_slots
;
1749 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1751 /* Rewrite all ATTR file references to the hw grf that they land in. */
1752 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1753 convert_attr_sources_to_hw_regs(inst
);
1758 fs_visitor::assign_tcs_single_patch_urb_setup()
1760 assert(stage
== MESA_SHADER_TESS_CTRL
);
1762 /* Rewrite all ATTR file references to HW_REGs. */
1763 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1764 convert_attr_sources_to_hw_regs(inst
);
1769 fs_visitor::assign_tes_urb_setup()
1771 assert(stage
== MESA_SHADER_TESS_EVAL
);
1773 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1775 first_non_payload_grf
+= 8 * vue_prog_data
->urb_read_length
;
1777 /* Rewrite all ATTR file references to HW_REGs. */
1778 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1779 convert_attr_sources_to_hw_regs(inst
);
1784 fs_visitor::assign_gs_urb_setup()
1786 assert(stage
== MESA_SHADER_GEOMETRY
);
1788 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1790 first_non_payload_grf
+=
1791 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1793 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1794 /* Rewrite all ATTR file references to GRFs. */
1795 convert_attr_sources_to_hw_regs(inst
);
1801 * Split large virtual GRFs into separate components if we can.
1803 * This is mostly duplicated with what brw_fs_vector_splitting does,
1804 * but that's really conservative because it's afraid of doing
1805 * splitting that doesn't result in real progress after the rest of
1806 * the optimization phases, which would cause infinite looping in
1807 * optimization. We can do it once here, safely. This also has the
1808 * opportunity to split interpolated values, or maybe even uniforms,
1809 * which we don't have at the IR level.
1811 * We want to split, because virtual GRFs are what we register
1812 * allocate and spill (due to contiguousness requirements for some
1813 * instructions), and they're what we naturally generate in the
1814 * codegen process, but most virtual GRFs don't actually need to be
1815 * contiguous sets of GRFs. If we split, we'll end up with reduced
1816 * live intervals and better dead code elimination and coalescing.
1819 fs_visitor::split_virtual_grfs()
1821 int num_vars
= this->alloc
.count
;
1823 /* Count the total number of registers */
1825 int vgrf_to_reg
[num_vars
];
1826 for (int i
= 0; i
< num_vars
; i
++) {
1827 vgrf_to_reg
[i
] = reg_count
;
1828 reg_count
+= alloc
.sizes
[i
];
1831 /* An array of "split points". For each register slot, this indicates
1832 * if this slot can be separated from the previous slot. Every time an
1833 * instruction uses multiple elements of a register (as a source or
1834 * destination), we mark the used slots as inseparable. Then we go
1835 * through and split the registers into the smallest pieces we can.
1837 bool split_points
[reg_count
];
1838 memset(split_points
, 0, sizeof(split_points
));
1840 /* Mark all used registers as fully splittable */
1841 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1842 if (inst
->dst
.file
== VGRF
) {
1843 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1844 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1845 split_points
[reg
+ j
] = true;
1848 for (int i
= 0; i
< inst
->sources
; i
++) {
1849 if (inst
->src
[i
].file
== VGRF
) {
1850 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1851 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1852 split_points
[reg
+ j
] = true;
1857 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1858 if (inst
->dst
.file
== VGRF
) {
1859 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1860 for (int j
= 1; j
< inst
->regs_written
; j
++)
1861 split_points
[reg
+ j
] = false;
1863 for (int i
= 0; i
< inst
->sources
; i
++) {
1864 if (inst
->src
[i
].file
== VGRF
) {
1865 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1866 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1867 split_points
[reg
+ j
] = false;
1872 int new_virtual_grf
[reg_count
];
1873 int new_reg_offset
[reg_count
];
1876 for (int i
= 0; i
< num_vars
; i
++) {
1877 /* The first one should always be 0 as a quick sanity check. */
1878 assert(split_points
[reg
] == false);
1881 new_reg_offset
[reg
] = 0;
1886 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1887 /* If this is a split point, reset the offset to 0 and allocate a
1888 * new virtual GRF for the previous offset many registers
1890 if (split_points
[reg
]) {
1891 assert(offset
<= MAX_VGRF_SIZE
);
1892 int grf
= alloc
.allocate(offset
);
1893 for (int k
= reg
- offset
; k
< reg
; k
++)
1894 new_virtual_grf
[k
] = grf
;
1897 new_reg_offset
[reg
] = offset
;
1902 /* The last one gets the original register number */
1903 assert(offset
<= MAX_VGRF_SIZE
);
1904 alloc
.sizes
[i
] = offset
;
1905 for (int k
= reg
- offset
; k
< reg
; k
++)
1906 new_virtual_grf
[k
] = i
;
1908 assert(reg
== reg_count
);
1910 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1911 if (inst
->dst
.file
== VGRF
) {
1912 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1913 inst
->dst
.nr
= new_virtual_grf
[reg
];
1914 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1915 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1917 for (int i
= 0; i
< inst
->sources
; i
++) {
1918 if (inst
->src
[i
].file
== VGRF
) {
1919 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1920 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1921 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1922 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1926 invalidate_live_intervals();
1930 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1932 * During code generation, we create tons of temporary variables, many of
1933 * which get immediately killed and are never used again. Yet, in later
1934 * optimization and analysis passes, such as compute_live_intervals, we need
1935 * to loop over all the virtual GRFs. Compacting them can save a lot of
1939 fs_visitor::compact_virtual_grfs()
1941 bool progress
= false;
1942 int remap_table
[this->alloc
.count
];
1943 memset(remap_table
, -1, sizeof(remap_table
));
1945 /* Mark which virtual GRFs are used. */
1946 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1947 if (inst
->dst
.file
== VGRF
)
1948 remap_table
[inst
->dst
.nr
] = 0;
1950 for (int i
= 0; i
< inst
->sources
; i
++) {
1951 if (inst
->src
[i
].file
== VGRF
)
1952 remap_table
[inst
->src
[i
].nr
] = 0;
1956 /* Compact the GRF arrays. */
1958 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1959 if (remap_table
[i
] == -1) {
1960 /* We just found an unused register. This means that we are
1961 * actually going to compact something.
1965 remap_table
[i
] = new_index
;
1966 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1967 invalidate_live_intervals();
1972 this->alloc
.count
= new_index
;
1974 /* Patch all the instructions to use the newly renumbered registers */
1975 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1976 if (inst
->dst
.file
== VGRF
)
1977 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1979 for (int i
= 0; i
< inst
->sources
; i
++) {
1980 if (inst
->src
[i
].file
== VGRF
)
1981 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1985 /* Patch all the references to delta_xy, since they're used in register
1986 * allocation. If they're unused, switch them to BAD_FILE so we don't
1987 * think some random VGRF is delta_xy.
1989 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1990 if (delta_xy
[i
].file
== VGRF
) {
1991 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1992 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1994 delta_xy
[i
].file
= BAD_FILE
;
2003 set_push_pull_constant_loc(unsigned uniform
, int *chunk_start
, bool contiguous
,
2004 int *push_constant_loc
, int *pull_constant_loc
,
2005 unsigned *num_push_constants
,
2006 unsigned *num_pull_constants
,
2007 const unsigned max_push_components
,
2008 const unsigned max_chunk_size
,
2009 struct brw_stage_prog_data
*stage_prog_data
)
2011 /* This is the first live uniform in the chunk */
2012 if (*chunk_start
< 0)
2013 *chunk_start
= uniform
;
2015 /* If this element does not need to be contiguous with the next, we
2016 * split at this point and everything between chunk_start and u forms a
2020 unsigned chunk_size
= uniform
- *chunk_start
+ 1;
2022 /* Decide whether we should push or pull this parameter. In the
2023 * Vulkan driver, push constants are explicitly exposed via the API
2024 * so we push everything. In GL, we only push small arrays.
2026 if (stage_prog_data
->pull_param
== NULL
||
2027 (*num_push_constants
+ chunk_size
<= max_push_components
&&
2028 chunk_size
<= max_chunk_size
)) {
2029 assert(*num_push_constants
+ chunk_size
<= max_push_components
);
2030 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2031 push_constant_loc
[j
] = (*num_push_constants
)++;
2033 for (unsigned j
= *chunk_start
; j
<= uniform
; j
++)
2034 pull_constant_loc
[j
] = (*num_pull_constants
)++;
2042 * Assign UNIFORM file registers to either push constants or pull constants.
2044 * We allow a fragment shader to have more than the specified minimum
2045 * maximum number of fragment shader uniform components (64). If
2046 * there are too many of these, they'd fill up all of register space.
2047 * So, this will push some of them out to the pull constant buffer and
2048 * update the program to load them.
2051 fs_visitor::assign_constant_locations()
2053 /* Only the first compile gets to decide on locations. */
2054 if (dispatch_width
!= min_dispatch_width
)
2057 bool is_live
[uniforms
];
2058 memset(is_live
, 0, sizeof(is_live
));
2059 bool is_live_64bit
[uniforms
];
2060 memset(is_live_64bit
, 0, sizeof(is_live_64bit
));
2062 /* For each uniform slot, a value of true indicates that the given slot and
2063 * the next slot must remain contiguous. This is used to keep us from
2064 * splitting arrays apart.
2066 bool contiguous
[uniforms
];
2067 memset(contiguous
, 0, sizeof(contiguous
));
2069 int thread_local_id_index
=
2070 (stage
== MESA_SHADER_COMPUTE
) ?
2071 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
: -1;
2073 /* First, we walk through the instructions and do two things:
2075 * 1) Figure out which uniforms are live.
2077 * 2) Mark any indirectly used ranges of registers as contiguous.
2079 * Note that we don't move constant-indexed accesses to arrays. No
2080 * testing has been done of the performance impact of this choice.
2082 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2083 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2084 if (inst
->src
[i
].file
!= UNIFORM
)
2087 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2089 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0) {
2090 assert(inst
->src
[2].ud
% 4 == 0);
2091 unsigned last
= constant_nr
+ (inst
->src
[2].ud
/ 4) - 1;
2092 assert(last
< uniforms
);
2094 for (unsigned j
= constant_nr
; j
< last
; j
++) {
2096 contiguous
[j
] = true;
2097 if (type_sz(inst
->src
[i
].type
) == 8) {
2098 is_live_64bit
[j
] = true;
2101 is_live
[last
] = true;
2103 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
) {
2104 int regs_read
= inst
->components_read(i
) *
2105 type_sz(inst
->src
[i
].type
) / 4;
2106 for (int j
= 0; j
< regs_read
; j
++) {
2107 is_live
[constant_nr
+ j
] = true;
2108 if (type_sz(inst
->src
[i
].type
) == 8) {
2109 is_live_64bit
[constant_nr
+ j
] = true;
2117 if (thread_local_id_index
>= 0 && !is_live
[thread_local_id_index
])
2118 thread_local_id_index
= -1;
2120 /* Only allow 16 registers (128 uniform components) as push constants.
2122 * Just demote the end of the list. We could probably do better
2123 * here, demoting things that are rarely used in the program first.
2125 * If changing this value, note the limitation about total_regs in
2128 unsigned int max_push_components
= 16 * 8;
2129 if (thread_local_id_index
>= 0)
2130 max_push_components
--; /* Save a slot for the thread ID */
2132 /* We push small arrays, but no bigger than 16 floats. This is big enough
2133 * for a vec4 but hopefully not large enough to push out other stuff. We
2134 * should probably use a better heuristic at some point.
2136 const unsigned int max_chunk_size
= 16;
2138 unsigned int num_push_constants
= 0;
2139 unsigned int num_pull_constants
= 0;
2141 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2142 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2144 /* Default to -1 meaning no location */
2145 memset(push_constant_loc
, -1, uniforms
* sizeof(*push_constant_loc
));
2146 memset(pull_constant_loc
, -1, uniforms
* sizeof(*pull_constant_loc
));
2148 int chunk_start
= -1;
2150 /* First push 64-bit uniforms to ensure they are properly aligned */
2151 for (unsigned u
= 0; u
< uniforms
; u
++) {
2152 if (!is_live
[u
] || !is_live_64bit
[u
])
2155 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2156 push_constant_loc
, pull_constant_loc
,
2157 &num_push_constants
, &num_pull_constants
,
2158 max_push_components
, max_chunk_size
,
2163 /* Then push the rest of uniforms */
2164 for (unsigned u
= 0; u
< uniforms
; u
++) {
2165 if (!is_live
[u
] || is_live_64bit
[u
])
2168 /* Skip thread_local_id_index to put it in the last push register. */
2169 if (thread_local_id_index
== (int)u
)
2172 set_push_pull_constant_loc(u
, &chunk_start
, contiguous
[u
],
2173 push_constant_loc
, pull_constant_loc
,
2174 &num_push_constants
, &num_pull_constants
,
2175 max_push_components
, max_chunk_size
,
2179 /* Add the CS local thread ID uniform at the end of the push constants */
2180 if (thread_local_id_index
>= 0)
2181 push_constant_loc
[thread_local_id_index
] = num_push_constants
++;
2183 /* As the uniforms are going to be reordered, take the data from a temporary
2184 * copy of the original param[].
2186 gl_constant_value
**param
= ralloc_array(NULL
, gl_constant_value
*,
2187 stage_prog_data
->nr_params
);
2188 memcpy(param
, stage_prog_data
->param
,
2189 sizeof(gl_constant_value
*) * stage_prog_data
->nr_params
);
2190 stage_prog_data
->nr_params
= num_push_constants
;
2191 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2193 /* Up until now, the param[] array has been indexed by reg + reg_offset
2194 * of UNIFORM registers. Move pull constants into pull_param[] and
2195 * condense param[] to only contain the uniforms we chose to push.
2197 * NOTE: Because we are condensing the params[] array, we know that
2198 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2199 * having to make a copy.
2201 int new_thread_local_id_index
= -1;
2202 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2203 const gl_constant_value
*value
= param
[i
];
2205 if (pull_constant_loc
[i
] != -1) {
2206 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2207 } else if (push_constant_loc
[i
] != -1) {
2208 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2209 if (thread_local_id_index
== (int)i
)
2210 new_thread_local_id_index
= push_constant_loc
[i
];
2215 if (stage
== MESA_SHADER_COMPUTE
)
2216 ((brw_cs_prog_data
*)stage_prog_data
)->thread_local_id_index
=
2217 new_thread_local_id_index
;
2221 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2222 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2225 fs_visitor::lower_constant_loads()
2227 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2229 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2230 /* Set up the annotation tracking for new generated instructions. */
2231 const fs_builder
ibld(this, block
, inst
);
2233 for (int i
= 0; i
< inst
->sources
; i
++) {
2234 if (inst
->src
[i
].file
!= UNIFORM
)
2237 /* We'll handle this case later */
2238 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&& i
== 0)
2241 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2242 if (location
>= uniforms
)
2243 continue; /* Out of bounds access */
2245 int pull_index
= pull_constant_loc
[location
];
2247 if (pull_index
== -1)
2250 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2253 if (type_sz(inst
->src
[i
].type
) <= 4)
2254 dst
= vgrf(glsl_type::float_type
);
2256 dst
= vgrf(glsl_type::double_type
);
2258 assert(inst
->src
[i
].stride
== 0);
2260 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2261 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2262 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2263 dst
, brw_imm_ud(index
), offset
);
2265 /* Rewrite the instruction to use the temporary VGRF. */
2266 inst
->src
[i
].file
= VGRF
;
2267 inst
->src
[i
].nr
= dst
.nr
;
2268 inst
->src
[i
].reg_offset
= 0;
2269 inst
->src
[i
].set_smear((pull_index
& 3) * 4 /
2270 type_sz(inst
->src
[i
].type
));
2272 brw_mark_surface_used(prog_data
, index
);
2275 if (inst
->opcode
== SHADER_OPCODE_MOV_INDIRECT
&&
2276 inst
->src
[0].file
== UNIFORM
) {
2278 unsigned location
= inst
->src
[0].nr
+ inst
->src
[0].reg_offset
;
2279 if (location
>= uniforms
)
2280 continue; /* Out of bounds access */
2282 int pull_index
= pull_constant_loc
[location
];
2284 if (pull_index
== -1)
2287 VARYING_PULL_CONSTANT_LOAD(ibld
, inst
->dst
,
2291 inst
->remove(block
);
2293 brw_mark_surface_used(prog_data
, index
);
2296 invalidate_live_intervals();
2300 fs_visitor::opt_algebraic()
2302 bool progress
= false;
2304 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2305 switch (inst
->opcode
) {
2306 case BRW_OPCODE_MOV
:
2307 if (inst
->src
[0].file
!= IMM
)
2310 if (inst
->saturate
) {
2311 if (inst
->dst
.type
!= inst
->src
[0].type
)
2312 assert(!"unimplemented: saturate mixed types");
2314 if (brw_saturate_immediate(inst
->dst
.type
,
2315 &inst
->src
[0].as_brw_reg())) {
2316 inst
->saturate
= false;
2322 case BRW_OPCODE_MUL
:
2323 if (inst
->src
[1].file
!= IMM
)
2327 if (inst
->src
[1].is_one()) {
2328 inst
->opcode
= BRW_OPCODE_MOV
;
2329 inst
->src
[1] = reg_undef
;
2335 if (inst
->src
[1].is_negative_one()) {
2336 inst
->opcode
= BRW_OPCODE_MOV
;
2337 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2338 inst
->src
[1] = reg_undef
;
2344 if (inst
->src
[1].is_zero()) {
2345 inst
->opcode
= BRW_OPCODE_MOV
;
2346 inst
->src
[0] = inst
->src
[1];
2347 inst
->src
[1] = reg_undef
;
2352 if (inst
->src
[0].file
== IMM
) {
2353 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2354 inst
->opcode
= BRW_OPCODE_MOV
;
2355 inst
->src
[0].f
*= inst
->src
[1].f
;
2356 inst
->src
[1] = reg_undef
;
2361 case BRW_OPCODE_ADD
:
2362 if (inst
->src
[1].file
!= IMM
)
2366 if (inst
->src
[1].is_zero()) {
2367 inst
->opcode
= BRW_OPCODE_MOV
;
2368 inst
->src
[1] = reg_undef
;
2373 if (inst
->src
[0].file
== IMM
) {
2374 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2375 inst
->opcode
= BRW_OPCODE_MOV
;
2376 inst
->src
[0].f
+= inst
->src
[1].f
;
2377 inst
->src
[1] = reg_undef
;
2383 if (inst
->src
[0].equals(inst
->src
[1])) {
2384 inst
->opcode
= BRW_OPCODE_MOV
;
2385 inst
->src
[1] = reg_undef
;
2390 case BRW_OPCODE_LRP
:
2391 if (inst
->src
[1].equals(inst
->src
[2])) {
2392 inst
->opcode
= BRW_OPCODE_MOV
;
2393 inst
->src
[0] = inst
->src
[1];
2394 inst
->src
[1] = reg_undef
;
2395 inst
->src
[2] = reg_undef
;
2400 case BRW_OPCODE_CMP
:
2401 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2403 inst
->src
[0].negate
&&
2404 inst
->src
[1].is_zero()) {
2405 inst
->src
[0].abs
= false;
2406 inst
->src
[0].negate
= false;
2407 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2412 case BRW_OPCODE_SEL
:
2413 if (inst
->src
[0].equals(inst
->src
[1])) {
2414 inst
->opcode
= BRW_OPCODE_MOV
;
2415 inst
->src
[1] = reg_undef
;
2416 inst
->predicate
= BRW_PREDICATE_NONE
;
2417 inst
->predicate_inverse
= false;
2419 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2420 switch (inst
->conditional_mod
) {
2421 case BRW_CONDITIONAL_LE
:
2422 case BRW_CONDITIONAL_L
:
2423 switch (inst
->src
[1].type
) {
2424 case BRW_REGISTER_TYPE_F
:
2425 if (inst
->src
[1].f
>= 1.0f
) {
2426 inst
->opcode
= BRW_OPCODE_MOV
;
2427 inst
->src
[1] = reg_undef
;
2428 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2436 case BRW_CONDITIONAL_GE
:
2437 case BRW_CONDITIONAL_G
:
2438 switch (inst
->src
[1].type
) {
2439 case BRW_REGISTER_TYPE_F
:
2440 if (inst
->src
[1].f
<= 0.0f
) {
2441 inst
->opcode
= BRW_OPCODE_MOV
;
2442 inst
->src
[1] = reg_undef
;
2443 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2455 case BRW_OPCODE_MAD
:
2456 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2457 inst
->opcode
= BRW_OPCODE_MOV
;
2458 inst
->src
[1] = reg_undef
;
2459 inst
->src
[2] = reg_undef
;
2461 } else if (inst
->src
[0].is_zero()) {
2462 inst
->opcode
= BRW_OPCODE_MUL
;
2463 inst
->src
[0] = inst
->src
[2];
2464 inst
->src
[2] = reg_undef
;
2466 } else if (inst
->src
[1].is_one()) {
2467 inst
->opcode
= BRW_OPCODE_ADD
;
2468 inst
->src
[1] = inst
->src
[2];
2469 inst
->src
[2] = reg_undef
;
2471 } else if (inst
->src
[2].is_one()) {
2472 inst
->opcode
= BRW_OPCODE_ADD
;
2473 inst
->src
[2] = reg_undef
;
2475 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2476 inst
->opcode
= BRW_OPCODE_ADD
;
2477 inst
->src
[1].f
*= inst
->src
[2].f
;
2478 inst
->src
[2] = reg_undef
;
2482 case SHADER_OPCODE_BROADCAST
:
2483 if (is_uniform(inst
->src
[0])) {
2484 inst
->opcode
= BRW_OPCODE_MOV
;
2486 inst
->force_writemask_all
= true;
2488 } else if (inst
->src
[1].file
== IMM
) {
2489 inst
->opcode
= BRW_OPCODE_MOV
;
2490 inst
->src
[0] = component(inst
->src
[0],
2493 inst
->force_writemask_all
= true;
2502 /* Swap if src[0] is immediate. */
2503 if (progress
&& inst
->is_commutative()) {
2504 if (inst
->src
[0].file
== IMM
) {
2505 fs_reg tmp
= inst
->src
[1];
2506 inst
->src
[1] = inst
->src
[0];
2515 * Optimize sample messages that have constant zero values for the trailing
2516 * texture coordinates. We can just reduce the message length for these
2517 * instructions instead of reserving a register for it. Trailing parameters
2518 * that aren't sent default to zero anyway. This will cause the dead code
2519 * eliminator to remove the MOV instruction that would otherwise be emitted to
2520 * set up the zero value.
2523 fs_visitor::opt_zero_samples()
2525 /* Gen4 infers the texturing opcode based on the message length so we can't
2528 if (devinfo
->gen
< 5)
2531 bool progress
= false;
2533 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2534 if (!inst
->is_tex())
2537 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2539 if (load_payload
->is_head_sentinel() ||
2540 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2543 /* We don't want to remove the message header or the first parameter.
2544 * Removing the first parameter is not allowed, see the Haswell PRM
2545 * volume 7, page 149:
2547 * "Parameter 0 is required except for the sampleinfo message, which
2548 * has no parameter 0"
2550 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2551 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2552 (inst
->exec_size
/ 8) +
2553 inst
->header_size
- 1].is_zero()) {
2554 inst
->mlen
-= inst
->exec_size
/ 8;
2560 invalidate_live_intervals();
2566 * Optimize sample messages which are followed by the final RT write.
2568 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2569 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2570 * final texturing results copied to the framebuffer write payload and modify
2571 * them to write to the framebuffer directly.
2574 fs_visitor::opt_sampler_eot()
2576 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2578 if (stage
!= MESA_SHADER_FRAGMENT
)
2581 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2584 /* FINISHME: It should be possible to implement this optimization when there
2585 * are multiple drawbuffers.
2587 if (key
->nr_color_regions
!= 1)
2590 /* Requires emitting a bunch of saturating MOV instructions during logical
2591 * send lowering to clamp the color payload, which the sampler unit isn't
2592 * going to do for us.
2594 if (key
->clamp_fragment_color
)
2597 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2598 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2599 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2600 assert(fb_write
->eot
);
2601 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE_LOGICAL
);
2603 /* There wasn't one; nothing to do. */
2604 if (unlikely(fb_write
->prev
->is_head_sentinel()))
2607 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2609 /* 3D Sampler » Messages » Message Format
2611 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2612 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2614 if (tex_inst
->opcode
!= SHADER_OPCODE_TEX_LOGICAL
&&
2615 tex_inst
->opcode
!= SHADER_OPCODE_TXD_LOGICAL
&&
2616 tex_inst
->opcode
!= SHADER_OPCODE_TXF_LOGICAL
&&
2617 tex_inst
->opcode
!= SHADER_OPCODE_TXL_LOGICAL
&&
2618 tex_inst
->opcode
!= FS_OPCODE_TXB_LOGICAL
&&
2619 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_LOGICAL
&&
2620 tex_inst
->opcode
!= SHADER_OPCODE_TXF_CMS_W_LOGICAL
&&
2621 tex_inst
->opcode
!= SHADER_OPCODE_TXF_UMS_LOGICAL
)
2624 /* XXX - This shouldn't be necessary. */
2625 if (tex_inst
->prev
->is_head_sentinel())
2628 /* Check that the FB write sources are fully initialized by the single
2629 * texturing instruction.
2631 for (unsigned i
= 0; i
< FB_WRITE_LOGICAL_NUM_SRCS
; i
++) {
2632 if (i
== FB_WRITE_LOGICAL_SRC_COLOR0
) {
2633 if (!fb_write
->src
[i
].equals(tex_inst
->dst
) ||
2634 fb_write
->regs_read(i
) != tex_inst
->regs_written
)
2636 } else if (i
!= FB_WRITE_LOGICAL_SRC_COMPONENTS
) {
2637 if (fb_write
->src
[i
].file
!= BAD_FILE
)
2642 assert(!tex_inst
->eot
); /* We can't get here twice */
2643 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2645 const fs_builder
ibld(this, block
, tex_inst
);
2647 tex_inst
->offset
|= fb_write
->target
<< 24;
2648 tex_inst
->eot
= true;
2649 tex_inst
->dst
= ibld
.null_reg_ud();
2650 tex_inst
->regs_written
= 0;
2651 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2653 /* Marking EOT is sufficient, lower_logical_sends() will notice the EOT
2654 * flag and submit a header together with the sampler message as required
2657 invalidate_live_intervals();
2662 fs_visitor::opt_register_renaming()
2664 bool progress
= false;
2667 int remap
[alloc
.count
];
2668 memset(remap
, -1, sizeof(int) * alloc
.count
);
2670 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2671 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2673 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2674 inst
->opcode
== BRW_OPCODE_WHILE
) {
2678 /* Rewrite instruction sources. */
2679 for (int i
= 0; i
< inst
->sources
; i
++) {
2680 if (inst
->src
[i
].file
== VGRF
&&
2681 remap
[inst
->src
[i
].nr
] != -1 &&
2682 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2683 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2688 const int dst
= inst
->dst
.nr
;
2691 inst
->dst
.file
== VGRF
&&
2692 alloc
.sizes
[inst
->dst
.nr
] == inst
->regs_written
&&
2693 !inst
->is_partial_write()) {
2694 if (remap
[dst
] == -1) {
2697 remap
[dst
] = alloc
.allocate(inst
->regs_written
);
2698 inst
->dst
.nr
= remap
[dst
];
2701 } else if (inst
->dst
.file
== VGRF
&&
2703 remap
[dst
] != dst
) {
2704 inst
->dst
.nr
= remap
[dst
];
2710 invalidate_live_intervals();
2712 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2713 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2714 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2723 * Remove redundant or useless discard jumps.
2725 * For example, we can eliminate jumps in the following sequence:
2727 * discard-jump (redundant with the next jump)
2728 * discard-jump (useless; jumps to the next instruction)
2732 fs_visitor::opt_redundant_discard_jumps()
2734 bool progress
= false;
2736 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2738 fs_inst
*placeholder_halt
= NULL
;
2739 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2740 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2741 placeholder_halt
= inst
;
2746 if (!placeholder_halt
)
2749 /* Delete any HALTs immediately before the placeholder halt. */
2750 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2751 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2752 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2753 prev
->remove(last_bblock
);
2758 invalidate_live_intervals();
2764 * Compute a bitmask with GRF granularity with a bit set for each GRF starting
2765 * from \p r which overlaps the region starting at \p r and spanning \p n GRF
2768 static inline unsigned
2769 mask_relative_to(const fs_reg
&r
, const fs_reg
&s
, unsigned n
)
2771 const int rel_offset
= (reg_offset(s
) - reg_offset(r
)) / REG_SIZE
;
2772 assert(reg_space(r
) == reg_space(s
) &&
2773 rel_offset
>= 0 && rel_offset
< int(8 * sizeof(unsigned)));
2774 return ((1 << n
) - 1) << rel_offset
;
2778 fs_visitor::compute_to_mrf()
2780 bool progress
= false;
2783 /* No MRFs on Gen >= 7. */
2784 if (devinfo
->gen
>= 7)
2787 calculate_live_intervals();
2789 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2793 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2794 inst
->is_partial_write() ||
2795 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2796 inst
->dst
.type
!= inst
->src
[0].type
||
2797 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2798 !inst
->src
[0].is_contiguous() ||
2799 inst
->src
[0].subreg_offset
)
2802 /* Can't compute-to-MRF this GRF if someone else was going to
2805 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2808 /* Found a move of a GRF to a MRF. Let's see if we can go rewrite the
2809 * things that computed the value of all GRFs of the source region. The
2810 * regs_left bitset keeps track of the registers we haven't yet found a
2811 * generating instruction for.
2813 unsigned regs_left
= (1 << inst
->regs_read(0)) - 1;
2815 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2816 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2817 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2818 /* Found the last thing to write our reg we want to turn
2819 * into a compute-to-MRF.
2822 /* If this one instruction didn't populate all the
2823 * channels, bail. We might be able to rewrite everything
2824 * that writes that reg, but it would require smarter
2827 if (scan_inst
->is_partial_write())
2830 /* Handling things not fully contained in the source of the copy
2831 * would need us to understand coalescing out more than one MOV at
2834 if (scan_inst
->dst
.reg_offset
< inst
->src
[0].reg_offset
||
2835 scan_inst
->dst
.reg_offset
+ scan_inst
->regs_written
>
2836 inst
->src
[0].reg_offset
+ inst
->regs_read(0))
2839 /* SEND instructions can't have MRF as a destination. */
2840 if (scan_inst
->mlen
)
2843 if (devinfo
->gen
== 6) {
2844 /* gen6 math instructions must have the destination be
2845 * GRF, so no compute-to-MRF for them.
2847 if (scan_inst
->is_math()) {
2852 /* Clear the bits for any registers this instruction overwrites. */
2853 regs_left
&= ~mask_relative_to(
2854 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2859 /* We don't handle control flow here. Most computation of
2860 * values that end up in MRFs are shortly before the MRF
2863 if (block
->start() == scan_inst
)
2866 /* You can't read from an MRF, so if someone else reads our
2867 * MRF's source GRF that we wanted to rewrite, that stops us.
2869 bool interfered
= false;
2870 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2871 if (regions_overlap(scan_inst
->src
[i
], scan_inst
->regs_read(i
) * REG_SIZE
,
2872 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2879 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2880 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2881 /* If somebody else writes our MRF here, we can't
2882 * compute-to-MRF before that.
2887 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1 &&
2888 regions_overlap(fs_reg(MRF
, scan_inst
->base_mrf
), scan_inst
->mlen
* REG_SIZE
,
2889 inst
->dst
, inst
->regs_written
* REG_SIZE
)) {
2890 /* Found a SEND instruction, which means that there are
2891 * live values in MRFs from base_mrf to base_mrf +
2892 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2902 /* Found all generating instructions of our MRF's source value, so it
2903 * should be safe to rewrite them to point to the MRF directly.
2905 regs_left
= (1 << inst
->regs_read(0)) - 1;
2907 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2908 if (regions_overlap(scan_inst
->dst
, scan_inst
->regs_written
* REG_SIZE
,
2909 inst
->src
[0], inst
->regs_read(0) * REG_SIZE
)) {
2910 /* Clear the bits for any registers this instruction overwrites. */
2911 regs_left
&= ~mask_relative_to(
2912 inst
->src
[0], scan_inst
->dst
, scan_inst
->regs_written
);
2914 const unsigned rel_offset
= (reg_offset(scan_inst
->dst
) -
2915 reg_offset(inst
->src
[0])) / REG_SIZE
;
2917 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2918 /* Apply the same address transformation done by the hardware
2919 * for COMPR4 MRF writes.
2921 assert(rel_offset
< 2);
2922 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
* 4;
2924 /* Clear the COMPR4 bit if the generating instruction is not
2927 if (scan_inst
->regs_written
< 2)
2928 scan_inst
->dst
.nr
&= ~BRW_MRF_COMPR4
;
2931 /* Calculate the MRF number the result of this instruction is
2932 * ultimately written to.
2934 scan_inst
->dst
.nr
= inst
->dst
.nr
+ rel_offset
;
2937 scan_inst
->dst
.file
= MRF
;
2938 scan_inst
->dst
.reg_offset
= 0;
2939 scan_inst
->saturate
|= inst
->saturate
;
2946 inst
->remove(block
);
2951 invalidate_live_intervals();
2957 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2958 * flow. We could probably do better here with some form of divergence
2962 fs_visitor::eliminate_find_live_channel()
2964 bool progress
= false;
2967 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2968 switch (inst
->opcode
) {
2974 case BRW_OPCODE_ENDIF
:
2975 case BRW_OPCODE_WHILE
:
2979 case FS_OPCODE_DISCARD_JUMP
:
2980 /* This can potentially make control flow non-uniform until the end
2985 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2987 inst
->opcode
= BRW_OPCODE_MOV
;
2988 inst
->src
[0] = brw_imm_ud(0u);
2990 inst
->force_writemask_all
= true;
3004 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3005 * instructions to FS_OPCODE_REP_FB_WRITE.
3008 fs_visitor::emit_repclear_shader()
3010 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3012 int color_mrf
= base_mrf
+ 2;
3016 mov
= bld
.exec_all().group(4, 0)
3017 .MOV(brw_message_reg(color_mrf
),
3018 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
3020 struct brw_reg reg
=
3021 brw_reg(BRW_GENERAL_REGISTER_FILE
, 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3022 BRW_VERTICAL_STRIDE_8
, BRW_WIDTH_2
, BRW_HORIZONTAL_STRIDE_4
,
3023 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3025 mov
= bld
.exec_all().group(4, 0)
3026 .MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
));
3030 if (key
->nr_color_regions
== 1) {
3031 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3032 write
->saturate
= key
->clamp_fragment_color
;
3033 write
->base_mrf
= color_mrf
;
3035 write
->header_size
= 0;
3038 assume(key
->nr_color_regions
> 0);
3039 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3040 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
3041 write
->saturate
= key
->clamp_fragment_color
;
3042 write
->base_mrf
= base_mrf
;
3044 write
->header_size
= 2;
3052 assign_constant_locations();
3053 assign_curb_setup();
3055 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3057 assert(mov
->src
[0].file
== FIXED_GRF
);
3058 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
3063 * Walks through basic blocks, looking for repeated MRF writes and
3064 * removing the later ones.
3067 fs_visitor::remove_duplicate_mrf_writes()
3069 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
3070 bool progress
= false;
3072 /* Need to update the MRF tracking for compressed instructions. */
3073 if (dispatch_width
>= 16)
3076 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3078 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3079 if (inst
->is_control_flow()) {
3080 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3083 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3084 inst
->dst
.file
== MRF
) {
3085 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
3086 if (prev_inst
&& inst
->equals(prev_inst
)) {
3087 inst
->remove(block
);
3093 /* Clear out the last-write records for MRFs that were overwritten. */
3094 if (inst
->dst
.file
== MRF
) {
3095 last_mrf_move
[inst
->dst
.nr
] = NULL
;
3098 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3099 /* Found a SEND instruction, which will include two or fewer
3100 * implied MRF writes. We could do better here.
3102 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3103 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3107 /* Clear out any MRF move records whose sources got overwritten. */
3108 for (unsigned i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3109 if (last_mrf_move
[i
] &&
3110 regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
3111 last_mrf_move
[i
]->src
[0],
3112 last_mrf_move
[i
]->regs_read(0) * REG_SIZE
)) {
3113 last_mrf_move
[i
] = NULL
;
3117 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3118 inst
->dst
.file
== MRF
&&
3119 inst
->src
[0].file
!= ARF
&&
3120 !inst
->is_partial_write()) {
3121 last_mrf_move
[inst
->dst
.nr
] = inst
;
3126 invalidate_live_intervals();
3132 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3134 /* Clear the flag for registers that actually got read (as expected). */
3135 for (int i
= 0; i
< inst
->sources
; i
++) {
3137 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
3138 grf
= inst
->src
[i
].nr
;
3143 if (grf
>= first_grf
&&
3144 grf
< first_grf
+ grf_len
) {
3145 deps
[grf
- first_grf
] = false;
3146 if (inst
->exec_size
== 16)
3147 deps
[grf
- first_grf
+ 1] = false;
3153 * Implements this workaround for the original 965:
3155 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3156 * check for post destination dependencies on this instruction, software
3157 * must ensure that there is no destination hazard for the case of ‘write
3158 * followed by a posted write’ shown in the following example.
3161 * 2. send r3.xy <rest of send instruction>
3164 * Due to no post-destination dependency check on the ‘send’, the above
3165 * code sequence could have two instructions (1 and 2) in flight at the
3166 * same time that both consider ‘r3’ as the target of their final writes.
3169 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3172 int write_len
= inst
->regs_written
;
3173 int first_write_grf
= inst
->dst
.nr
;
3174 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3175 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3177 memset(needs_dep
, false, sizeof(needs_dep
));
3178 memset(needs_dep
, true, write_len
);
3180 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3182 /* Walk backwards looking for writes to registers we're writing which
3183 * aren't read since being written. If we hit the start of the program,
3184 * we assume that there are no outstanding dependencies on entry to the
3187 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
3188 /* If we hit control flow, assume that there *are* outstanding
3189 * dependencies, and force their cleanup before our instruction.
3191 if (block
->start() == scan_inst
&& block
->num
!= 0) {
3192 for (int i
= 0; i
< write_len
; i
++) {
3194 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
3195 first_write_grf
+ i
);
3200 /* We insert our reads as late as possible on the assumption that any
3201 * instruction but a MOV that might have left us an outstanding
3202 * dependency has more latency than a MOV.
3204 if (scan_inst
->dst
.file
== VGRF
) {
3205 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3206 int reg
= scan_inst
->dst
.nr
+ i
;
3208 if (reg
>= first_write_grf
&&
3209 reg
< first_write_grf
+ write_len
&&
3210 needs_dep
[reg
- first_write_grf
]) {
3211 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
3212 needs_dep
[reg
- first_write_grf
] = false;
3213 if (scan_inst
->exec_size
== 16)
3214 needs_dep
[reg
- first_write_grf
+ 1] = false;
3219 /* Clear the flag for registers that actually got read (as expected). */
3220 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3222 /* Continue the loop only if we haven't resolved all the dependencies */
3224 for (i
= 0; i
< write_len
; i
++) {
3234 * Implements this workaround for the original 965:
3236 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3237 * used as a destination register until after it has been sourced by an
3238 * instruction with a different destination register.
3241 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3243 int write_len
= inst
->regs_written
;
3244 int first_write_grf
= inst
->dst
.nr
;
3245 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3246 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3248 memset(needs_dep
, false, sizeof(needs_dep
));
3249 memset(needs_dep
, true, write_len
);
3250 /* Walk forwards looking for writes to registers we're writing which aren't
3251 * read before being written.
3253 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3254 /* If we hit control flow, force resolve all remaining dependencies. */
3255 if (block
->end() == scan_inst
&& block
->num
!= cfg
->num_blocks
- 1) {
3256 for (int i
= 0; i
< write_len
; i
++) {
3258 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3259 first_write_grf
+ i
);
3264 /* Clear the flag for registers that actually got read (as expected). */
3265 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3267 /* We insert our reads as late as possible since they're reading the
3268 * result of a SEND, which has massive latency.
3270 if (scan_inst
->dst
.file
== VGRF
&&
3271 scan_inst
->dst
.nr
>= first_write_grf
&&
3272 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3273 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3274 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3276 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3279 /* Continue the loop only if we haven't resolved all the dependencies */
3281 for (i
= 0; i
< write_len
; i
++) {
3291 fs_visitor::insert_gen4_send_dependency_workarounds()
3293 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3296 bool progress
= false;
3298 /* Note that we're done with register allocation, so GRF fs_regs always
3299 * have a .reg_offset of 0.
3302 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3303 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3304 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3305 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3311 invalidate_live_intervals();
3315 * Turns the generic expression-style uniform pull constant load instruction
3316 * into a hardware-specific series of instructions for loading a pull
3319 * The expression style allows the CSE pass before this to optimize out
3320 * repeated loads from the same offset, and gives the pre-register-allocation
3321 * scheduling full flexibility, while the conversion to native instructions
3322 * allows the post-register-allocation scheduler the best information
3325 * Note that execution masking for setting up pull constant loads is special:
3326 * the channels that need to be written are unrelated to the current execution
3327 * mask, since a later instruction will use one of the result channels as a
3328 * source operand for all 8 or 16 of its channels.
3331 fs_visitor::lower_uniform_pull_constant_loads()
3333 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3334 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3337 if (devinfo
->gen
>= 7) {
3338 /* The offset arg is a vec4-aligned immediate byte offset. */
3339 fs_reg const_offset_reg
= inst
->src
[1];
3340 assert(const_offset_reg
.file
== IMM
&&
3341 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3342 assert(const_offset_reg
.ud
% 16 == 0);
3344 fs_reg payload
, offset
;
3345 if (devinfo
->gen
>= 9) {
3346 /* We have to use a message header on Skylake to get SIMD4x2
3347 * mode. Reserve space for the register.
3349 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3350 offset
.reg_offset
++;
3353 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3357 /* This is actually going to be a MOV, but since only the first dword
3358 * is accessed, we have a special opcode to do just that one. Note
3359 * that this needs to be an operation that will be considered a def
3360 * by live variable analysis, or register allocation will explode.
3362 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3363 8, offset
, const_offset_reg
);
3364 setup
->force_writemask_all
= true;
3366 setup
->ir
= inst
->ir
;
3367 setup
->annotation
= inst
->annotation
;
3368 inst
->insert_before(block
, setup
);
3370 /* Similarly, this will only populate the first 4 channels of the
3371 * result register (since we only use smear values from 0-3), but we
3372 * don't tell the optimizer.
3374 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3375 inst
->src
[1] = payload
;
3377 invalidate_live_intervals();
3379 /* Before register allocation, we didn't tell the scheduler about the
3380 * MRF we use. We know it's safe to use this MRF because nothing
3381 * else does except for register spill/unspill, which generates and
3382 * uses its MRF within a single IR instruction.
3384 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3391 fs_visitor::lower_load_payload()
3393 bool progress
= false;
3395 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3396 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3399 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3400 assert(inst
->saturate
== false);
3401 fs_reg dst
= inst
->dst
;
3403 /* Get rid of COMPR4. We'll add it back in if we need it */
3404 if (dst
.file
== MRF
)
3405 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3407 const fs_builder
ibld(this, block
, inst
);
3408 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3410 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3411 if (inst
->src
[i
].file
!= BAD_FILE
) {
3412 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3413 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3414 hbld
.MOV(mov_dst
, mov_src
);
3416 dst
= offset(dst
, hbld
, 1);
3419 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3420 inst
->exec_size
> 8) {
3421 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3422 * a straightforward copy. Instead, the result of the
3423 * LOAD_PAYLOAD is treated as interleaved and the first four
3424 * non-header sources are unpacked as:
3435 * This is used for gen <= 5 fb writes.
3437 assert(inst
->exec_size
== 16);
3438 assert(inst
->header_size
+ 4 <= inst
->sources
);
3439 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3440 if (inst
->src
[i
].file
!= BAD_FILE
) {
3441 if (devinfo
->has_compr4
) {
3442 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3443 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3444 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3446 /* Platform doesn't have COMPR4. We have to fake it */
3447 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3448 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3450 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3457 /* The loop above only ever incremented us through the first set
3458 * of 4 registers. However, thanks to the magic of COMPR4, we
3459 * actually wrote to the first 8 registers, so we need to take
3460 * that into account now.
3464 /* The COMPR4 code took care of the first 4 sources. We'll let
3465 * the regular path handle any remaining sources. Yes, we are
3466 * modifying the instruction but we're about to delete it so
3467 * this really doesn't hurt anything.
3469 inst
->header_size
+= 4;
3472 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3473 if (inst
->src
[i
].file
!= BAD_FILE
)
3474 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3475 dst
= offset(dst
, ibld
, 1);
3478 inst
->remove(block
);
3483 invalidate_live_intervals();
3489 fs_visitor::lower_integer_multiplication()
3491 bool progress
= false;
3493 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3494 const fs_builder
ibld(this, block
, inst
);
3496 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3497 if (inst
->dst
.is_accumulator() ||
3498 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3499 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3502 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3503 * operation directly, but CHV/BXT cannot.
3505 if (devinfo
->gen
>= 8 &&
3506 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3509 if (inst
->src
[1].file
== IMM
&&
3510 inst
->src
[1].ud
< (1 << 16)) {
3511 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3512 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3515 * If multiplying by an immediate value that fits in 16-bits, do a
3516 * single MUL instruction with that value in the proper location.
3518 if (devinfo
->gen
< 7) {
3519 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3521 ibld
.MOV(imm
, inst
->src
[1]);
3522 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3524 const bool ud
= (inst
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3525 ibld
.MUL(inst
->dst
, inst
->src
[0],
3526 ud
? brw_imm_uw(inst
->src
[1].ud
)
3527 : brw_imm_w(inst
->src
[1].d
));
3530 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3531 * do 32-bit integer multiplication in one instruction, but instead
3532 * must do a sequence (which actually calculates a 64-bit result):
3534 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3535 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3536 * mov(8) g2<1>D acc0<8,8,1>D
3538 * But on Gen > 6, the ability to use second accumulator register
3539 * (acc1) for non-float data types was removed, preventing a simple
3540 * implementation in SIMD16. A 16-channel result can be calculated by
3541 * executing the three instructions twice in SIMD8, once with quarter
3542 * control of 1Q for the first eight channels and again with 2Q for
3543 * the second eight channels.
3545 * Which accumulator register is implicitly accessed (by AccWrEnable
3546 * for instance) is determined by the quarter control. Unfortunately
3547 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3548 * implicit accumulator access by an instruction with 2Q will access
3549 * acc1 regardless of whether the data type is usable in acc1.
3551 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3552 * integer data types.
3554 * Since we only want the low 32-bits of the result, we can do two
3555 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3556 * adjust the high result and add them (like the mach is doing):
3558 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3559 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3560 * shl(8) g9<1>D g8<8,8,1>D 16D
3561 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3563 * We avoid the shl instruction by realizing that we only want to add
3564 * the low 16-bits of the "high" result to the high 16-bits of the
3565 * "low" result and using proper regioning on the add:
3567 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3568 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3569 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3571 * Since it does not use the (single) accumulator register, we can
3572 * schedule multi-component multiplications much better.
3575 fs_reg orig_dst
= inst
->dst
;
3576 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3577 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3580 fs_reg low
= inst
->dst
;
3581 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3584 if (devinfo
->gen
>= 7) {
3585 fs_reg src1_0_w
= inst
->src
[1];
3586 fs_reg src1_1_w
= inst
->src
[1];
3588 if (inst
->src
[1].file
== IMM
) {
3589 src1_0_w
.ud
&= 0xffff;
3592 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3593 if (src1_0_w
.stride
!= 0) {
3594 assert(src1_0_w
.stride
== 1);
3595 src1_0_w
.stride
= 2;
3598 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3599 if (src1_1_w
.stride
!= 0) {
3600 assert(src1_1_w
.stride
== 1);
3601 src1_1_w
.stride
= 2;
3603 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3605 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3606 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3608 fs_reg src0_0_w
= inst
->src
[0];
3609 fs_reg src0_1_w
= inst
->src
[0];
3611 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3612 if (src0_0_w
.stride
!= 0) {
3613 assert(src0_0_w
.stride
== 1);
3614 src0_0_w
.stride
= 2;
3617 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3618 if (src0_1_w
.stride
!= 0) {
3619 assert(src0_1_w
.stride
== 1);
3620 src0_1_w
.stride
= 2;
3622 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3624 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3625 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3628 fs_reg dst
= inst
->dst
;
3629 dst
.type
= BRW_REGISTER_TYPE_UW
;
3630 dst
.subreg_offset
= 2;
3633 high
.type
= BRW_REGISTER_TYPE_UW
;
3636 low
.type
= BRW_REGISTER_TYPE_UW
;
3637 low
.subreg_offset
= 2;
3640 ibld
.ADD(dst
, low
, high
);
3642 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3643 set_condmod(inst
->conditional_mod
,
3644 ibld
.MOV(orig_dst
, inst
->dst
));
3648 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3649 /* Should have been lowered to 8-wide. */
3650 assert(inst
->exec_size
<= 8);
3651 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3653 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3654 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3656 if (devinfo
->gen
>= 8) {
3657 /* Until Gen8, integer multiplies read 32-bits from one source,
3658 * and 16-bits from the other, and relying on the MACH instruction
3659 * to generate the high bits of the result.
3661 * On Gen8, the multiply instruction does a full 32x32-bit
3662 * multiply, but in order to do a 64-bit multiply we can simulate
3663 * the previous behavior and then use a MACH instruction.
3665 * FINISHME: Don't use source modifiers on src1.
3667 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3668 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3669 mul
->src
[1].type
= BRW_REGISTER_TYPE_UW
;
3670 mul
->src
[1].stride
*= 2;
3672 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3674 /* Among other things the quarter control bits influence which
3675 * accumulator register is used by the hardware for instructions
3676 * that access the accumulator implicitly (e.g. MACH). A
3677 * second-half instruction would normally map to acc1, which
3678 * doesn't exist on Gen7 and up (the hardware does emulate it for
3679 * floating-point instructions *only* by taking advantage of the
3680 * extra precision of acc0 not normally used for floating point
3683 * HSW and up are careful enough not to try to access an
3684 * accumulator register that doesn't exist, but on earlier Gen7
3685 * hardware we need to make sure that the quarter control bits are
3686 * zero to avoid non-deterministic behaviour and emit an extra MOV
3687 * to get the result masked correctly according to the current
3691 mach
->force_writemask_all
= true;
3692 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3693 ibld
.MOV(inst
->dst
, mach
->dst
);
3699 inst
->remove(block
);
3704 invalidate_live_intervals();
3710 fs_visitor::lower_minmax()
3712 assert(devinfo
->gen
< 6);
3714 bool progress
= false;
3716 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3717 const fs_builder
ibld(this, block
, inst
);
3719 if (inst
->opcode
== BRW_OPCODE_SEL
&&
3720 inst
->predicate
== BRW_PREDICATE_NONE
) {
3721 /* FIXME: Using CMP doesn't preserve the NaN propagation semantics of
3722 * the original SEL.L/GE instruction
3724 ibld
.CMP(ibld
.null_reg_d(), inst
->src
[0], inst
->src
[1],
3725 inst
->conditional_mod
);
3726 inst
->predicate
= BRW_PREDICATE_NORMAL
;
3727 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
3734 invalidate_live_intervals();
3740 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3741 fs_reg
*dst
, fs_reg color
, unsigned components
)
3743 if (key
->clamp_fragment_color
) {
3744 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3745 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3747 for (unsigned i
= 0; i
< components
; i
++)
3749 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3754 for (unsigned i
= 0; i
< components
; i
++)
3755 dst
[i
] = offset(color
, bld
, i
);
3759 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3760 const brw_wm_prog_data
*prog_data
,
3761 const brw_wm_prog_key
*key
,
3762 const fs_visitor::thread_payload
&payload
)
3764 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3765 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3766 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3767 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3768 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3769 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3770 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3771 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3772 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3773 const unsigned components
=
3774 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3776 /* We can potentially have a message length of up to 15, so we have to set
3777 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3780 int header_size
= 2, payload_header_size
;
3781 unsigned length
= 0;
3783 /* From the Sandy Bridge PRM, volume 4, page 198:
3785 * "Dispatched Pixel Enables. One bit per pixel indicating
3786 * which pixels were originally enabled when the thread was
3787 * dispatched. This field is only required for the end-of-
3788 * thread message and on all dual-source messages."
3790 if (devinfo
->gen
>= 6 &&
3791 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3792 color1
.file
== BAD_FILE
&&
3793 key
->nr_color_regions
== 1) {
3797 if (header_size
!= 0) {
3798 assert(header_size
== 2);
3799 /* Allocate 2 registers for a header */
3803 if (payload
.aa_dest_stencil_reg
) {
3804 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3805 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3806 .MOV(sources
[length
],
3807 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3811 if (sample_mask
.file
!= BAD_FILE
) {
3812 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3813 BRW_REGISTER_TYPE_UD
);
3815 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3816 * relevant. Since it's unsigned single words one vgrf is always
3817 * 16-wide, but only the lower or higher 8 channels will be used by the
3818 * hardware when doing a SIMD8 write depending on whether we have
3819 * selected the subspans for the first or second half respectively.
3821 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3822 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3823 sample_mask
.stride
*= 2;
3825 bld
.exec_all().annotate("FB write oMask")
3826 .MOV(horiz_offset(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3832 payload_header_size
= length
;
3834 if (src0_alpha
.file
!= BAD_FILE
) {
3835 /* FIXME: This is being passed at the wrong location in the payload and
3836 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3837 * It's supposed to be immediately before oMask but there seems to be no
3838 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3839 * requires header sources to form a contiguous segment at the beginning
3840 * of the message and src0_alpha has per-channel semantics.
3842 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3846 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3849 if (color1
.file
!= BAD_FILE
) {
3850 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3854 if (src_depth
.file
!= BAD_FILE
) {
3855 sources
[length
] = src_depth
;
3859 if (dst_depth
.file
!= BAD_FILE
) {
3860 sources
[length
] = dst_depth
;
3864 if (src_stencil
.file
!= BAD_FILE
) {
3865 assert(devinfo
->gen
>= 9);
3866 assert(bld
.dispatch_width() != 16);
3868 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3869 * available on gen9+. As such it's impossible to have both enabled at the
3870 * same time and therefore length cannot overrun the array.
3872 assert(length
< 15);
3874 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3875 bld
.exec_all().annotate("FB write OS")
3876 .MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UB
),
3877 subscript(src_stencil
, BRW_REGISTER_TYPE_UB
, 0));
3882 if (devinfo
->gen
>= 7) {
3883 /* Send from the GRF */
3884 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3885 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3886 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3887 load
->dst
= payload
;
3889 inst
->src
[0] = payload
;
3890 inst
->resize_sources(1);
3892 /* Send from the MRF */
3893 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3894 sources
, length
, payload_header_size
);
3896 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3897 * will do this for us if we just give it a COMPR4 destination.
3899 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3900 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3902 inst
->resize_sources(0);
3906 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3907 inst
->mlen
= load
->regs_written
;
3908 inst
->header_size
= header_size
;
3912 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3913 const fs_reg
&coordinate
,
3914 const fs_reg
&shadow_c
,
3915 const fs_reg
&lod
, const fs_reg
&lod2
,
3916 const fs_reg
&surface
,
3917 const fs_reg
&sampler
,
3918 unsigned coord_components
,
3919 unsigned grad_components
)
3921 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3922 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3923 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3924 fs_reg msg_end
= msg_begin
;
3927 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3929 for (unsigned i
= 0; i
< coord_components
; i
++)
3930 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3931 offset(coordinate
, bld
, i
));
3933 msg_end
= offset(msg_end
, bld
, coord_components
);
3935 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3936 * require all three components to be present and zero if they are unused.
3938 if (coord_components
> 0 &&
3939 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3940 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3941 for (unsigned i
= coord_components
; i
< 3; i
++)
3942 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3944 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3947 if (op
== SHADER_OPCODE_TXD
) {
3948 /* TXD unsupported in SIMD16 mode. */
3949 assert(bld
.dispatch_width() == 8);
3951 /* the slots for u and v are always present, but r is optional */
3952 if (coord_components
< 2)
3953 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3956 * dPdx = dudx, dvdx, drdx
3957 * dPdy = dudy, dvdy, drdy
3959 * 1-arg: Does not exist.
3961 * 2-arg: dudx dvdx dudy dvdy
3962 * dPdx.x dPdx.y dPdy.x dPdy.y
3965 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3966 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3967 * m5 m6 m7 m8 m9 m10
3969 for (unsigned i
= 0; i
< grad_components
; i
++)
3970 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3972 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3974 for (unsigned i
= 0; i
< grad_components
; i
++)
3975 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3977 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3981 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3982 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3984 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3985 bld
.dispatch_width() == 16);
3987 const brw_reg_type type
=
3988 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3989 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3990 bld
.MOV(retype(msg_end
, type
), lod
);
3991 msg_end
= offset(msg_end
, bld
, 1);
3994 if (shadow_c
.file
!= BAD_FILE
) {
3995 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3996 /* There's no plain shadow compare message, so we use shadow
3997 * compare with a bias of 0.0.
3999 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
4000 msg_end
= offset(msg_end
, bld
, 1);
4003 bld
.MOV(msg_end
, shadow_c
);
4004 msg_end
= offset(msg_end
, bld
, 1);
4008 inst
->src
[0] = reg_undef
;
4009 inst
->src
[1] = surface
;
4010 inst
->src
[2] = sampler
;
4011 inst
->resize_sources(3);
4012 inst
->base_mrf
= msg_begin
.nr
;
4013 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
4014 inst
->header_size
= 1;
4018 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4019 const fs_reg
&coordinate
,
4020 const fs_reg
&shadow_c
,
4021 const fs_reg
&lod
, const fs_reg
&lod2
,
4022 const fs_reg
&sample_index
,
4023 const fs_reg
&surface
,
4024 const fs_reg
&sampler
,
4025 const fs_reg
&offset_value
,
4026 unsigned coord_components
,
4027 unsigned grad_components
)
4029 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
4030 fs_reg msg_coords
= message
;
4031 unsigned header_size
= 0;
4033 if (offset_value
.file
!= BAD_FILE
) {
4034 /* The offsets set up by the visitor are in the m1 header, so we can't
4041 for (unsigned i
= 0; i
< coord_components
; i
++)
4042 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
),
4043 offset(coordinate
, bld
, i
));
4045 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
4046 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
4048 if (shadow_c
.file
!= BAD_FILE
) {
4049 fs_reg msg_shadow
= msg_lod
;
4050 bld
.MOV(msg_shadow
, shadow_c
);
4051 msg_lod
= offset(msg_shadow
, bld
, 1);
4056 case SHADER_OPCODE_TXL
:
4058 bld
.MOV(msg_lod
, lod
);
4059 msg_end
= offset(msg_lod
, bld
, 1);
4061 case SHADER_OPCODE_TXD
:
4064 * dPdx = dudx, dvdx, drdx
4065 * dPdy = dudy, dvdy, drdy
4067 * Load up these values:
4068 * - dudx dudy dvdx dvdy drdx drdy
4069 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
4072 for (unsigned i
= 0; i
< grad_components
; i
++) {
4073 bld
.MOV(msg_end
, offset(lod
, bld
, i
));
4074 msg_end
= offset(msg_end
, bld
, 1);
4076 bld
.MOV(msg_end
, offset(lod2
, bld
, i
));
4077 msg_end
= offset(msg_end
, bld
, 1);
4080 case SHADER_OPCODE_TXS
:
4081 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
4082 bld
.MOV(msg_lod
, lod
);
4083 msg_end
= offset(msg_lod
, bld
, 1);
4085 case SHADER_OPCODE_TXF
:
4086 msg_lod
= offset(msg_coords
, bld
, 3);
4087 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
4088 msg_end
= offset(msg_lod
, bld
, 1);
4090 case SHADER_OPCODE_TXF_CMS
:
4091 msg_lod
= offset(msg_coords
, bld
, 3);
4093 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
4095 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
4096 msg_end
= offset(msg_lod
, bld
, 2);
4103 inst
->src
[0] = reg_undef
;
4104 inst
->src
[1] = surface
;
4105 inst
->src
[2] = sampler
;
4106 inst
->resize_sources(3);
4107 inst
->base_mrf
= message
.nr
;
4108 inst
->mlen
= msg_end
.nr
- message
.nr
;
4109 inst
->header_size
= header_size
;
4111 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4112 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4116 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
4118 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
4121 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
4125 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4126 const fs_reg
&coordinate
,
4127 const fs_reg
&shadow_c
,
4128 fs_reg lod
, const fs_reg
&lod2
,
4129 const fs_reg
&sample_index
,
4131 const fs_reg
&surface
,
4132 const fs_reg
&sampler
,
4133 const fs_reg
&offset_value
,
4134 unsigned coord_components
,
4135 unsigned grad_components
)
4137 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4138 int reg_width
= bld
.dispatch_width() / 8;
4139 unsigned header_size
= 0, length
= 0;
4140 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
4141 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
4142 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
4144 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
4145 offset_value
.file
!= BAD_FILE
|| inst
->eot
||
4146 op
== SHADER_OPCODE_SAMPLEINFO
||
4147 is_high_sampler(devinfo
, sampler
)) {
4148 /* For general texture offsets (no txf workaround), we need a header to
4149 * put them in. Note that we're only reserving space for it in the
4150 * message payload as it will be initialized implicitly by the
4153 * TG4 needs to place its channel select in the header, for interaction
4154 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
4155 * larger sampler numbers we need to offset the Sampler State Pointer in
4159 sources
[0] = fs_reg();
4162 /* If we're requesting fewer than four channels worth of response,
4163 * and we have an explicit header, we need to set up the sampler
4164 * writemask. It's reversed from normal: 1 means "don't write".
4166 if (!inst
->eot
&& inst
->regs_written
!= 4 * reg_width
) {
4167 assert((inst
->regs_written
% reg_width
) == 0);
4168 unsigned mask
= ~((1 << (inst
->regs_written
/ reg_width
)) - 1) & 0xf;
4169 inst
->offset
|= mask
<< 12;
4173 if (shadow_c
.file
!= BAD_FILE
) {
4174 bld
.MOV(sources
[length
], shadow_c
);
4178 bool coordinate_done
= false;
4180 /* The sampler can only meaningfully compute LOD for fragment shader
4181 * messages. For all other stages, we change the opcode to TXL and
4182 * hardcode the LOD to 0.
4184 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
4185 op
== SHADER_OPCODE_TEX
) {
4186 op
= SHADER_OPCODE_TXL
;
4187 lod
= brw_imm_f(0.0f
);
4190 /* Set up the LOD info */
4193 case SHADER_OPCODE_TXL
:
4194 if (devinfo
->gen
>= 9 && op
== SHADER_OPCODE_TXL
&& lod
.is_zero()) {
4195 op
= SHADER_OPCODE_TXL_LZ
;
4198 bld
.MOV(sources
[length
], lod
);
4201 case SHADER_OPCODE_TXD
:
4202 /* TXD should have been lowered in SIMD16 mode. */
4203 assert(bld
.dispatch_width() == 8);
4205 /* Load dPdx and the coordinate together:
4206 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
4208 for (unsigned i
= 0; i
< coord_components
; i
++) {
4209 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4211 /* For cube map array, the coordinate is (u,v,r,ai) but there are
4212 * only derivatives for (u, v, r).
4214 if (i
< grad_components
) {
4215 bld
.MOV(sources
[length
++], offset(lod
, bld
, i
));
4216 bld
.MOV(sources
[length
++], offset(lod2
, bld
, i
));
4220 coordinate_done
= true;
4222 case SHADER_OPCODE_TXS
:
4223 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
4226 case SHADER_OPCODE_TXF
:
4227 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
4228 * On Gen9 they are u, v, lod, r
4230 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
), coordinate
);
4232 if (devinfo
->gen
>= 9) {
4233 if (coord_components
>= 2) {
4234 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
),
4235 offset(coordinate
, bld
, 1));
4237 sources
[length
] = brw_imm_d(0);
4242 if (devinfo
->gen
>= 9 && lod
.is_zero()) {
4243 op
= SHADER_OPCODE_TXF_LZ
;
4245 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
4249 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++)
4250 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4251 offset(coordinate
, bld
, i
));
4253 coordinate_done
= true;
4256 case SHADER_OPCODE_TXF_CMS
:
4257 case SHADER_OPCODE_TXF_CMS_W
:
4258 case SHADER_OPCODE_TXF_UMS
:
4259 case SHADER_OPCODE_TXF_MCS
:
4260 if (op
== SHADER_OPCODE_TXF_UMS
||
4261 op
== SHADER_OPCODE_TXF_CMS
||
4262 op
== SHADER_OPCODE_TXF_CMS_W
) {
4263 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
4267 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
4268 /* Data from the multisample control surface. */
4269 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
4272 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
4275 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
4276 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
4279 offset(mcs
, bld
, 1));
4284 /* There is no offsetting for this message; just copy in the integer
4285 * texture coordinates.
4287 for (unsigned i
= 0; i
< coord_components
; i
++)
4288 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4289 offset(coordinate
, bld
, i
));
4291 coordinate_done
= true;
4293 case SHADER_OPCODE_TG4_OFFSET
:
4294 /* gather4_po_c should have been lowered in SIMD16 mode. */
4295 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4297 /* More crazy intermixing */
4298 for (unsigned i
= 0; i
< 2; i
++) /* u, v */
4299 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4301 for (unsigned i
= 0; i
< 2; i
++) /* offu, offv */
4302 bld
.MOV(retype(sources
[length
++], BRW_REGISTER_TYPE_D
),
4303 offset(offset_value
, bld
, i
));
4305 if (coord_components
== 3) /* r if present */
4306 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, 2));
4308 coordinate_done
= true;
4314 /* Set up the coordinate (except for cases where it was done above) */
4315 if (!coordinate_done
) {
4316 for (unsigned i
= 0; i
< coord_components
; i
++)
4317 bld
.MOV(sources
[length
++], offset(coordinate
, bld
, i
));
4322 mlen
= length
* reg_width
- header_size
;
4324 mlen
= length
* reg_width
;
4326 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4327 BRW_REGISTER_TYPE_F
);
4328 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4330 /* Generate the SEND. */
4332 inst
->src
[0] = src_payload
;
4333 inst
->src
[1] = surface
;
4334 inst
->src
[2] = sampler
;
4335 inst
->resize_sources(3);
4337 inst
->header_size
= header_size
;
4339 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4340 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4344 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4346 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4347 const fs_reg
&coordinate
= inst
->src
[TEX_LOGICAL_SRC_COORDINATE
];
4348 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4349 const fs_reg
&lod
= inst
->src
[TEX_LOGICAL_SRC_LOD
];
4350 const fs_reg
&lod2
= inst
->src
[TEX_LOGICAL_SRC_LOD2
];
4351 const fs_reg
&sample_index
= inst
->src
[TEX_LOGICAL_SRC_SAMPLE_INDEX
];
4352 const fs_reg
&mcs
= inst
->src
[TEX_LOGICAL_SRC_MCS
];
4353 const fs_reg
&surface
= inst
->src
[TEX_LOGICAL_SRC_SURFACE
];
4354 const fs_reg
&sampler
= inst
->src
[TEX_LOGICAL_SRC_SAMPLER
];
4355 const fs_reg
&offset_value
= inst
->src
[TEX_LOGICAL_SRC_OFFSET_VALUE
];
4356 assert(inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].file
== IMM
);
4357 const unsigned coord_components
= inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
4358 assert(inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].file
== IMM
);
4359 const unsigned grad_components
= inst
->src
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
].ud
;
4361 if (devinfo
->gen
>= 7) {
4362 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4363 shadow_c
, lod
, lod2
, sample_index
,
4364 mcs
, surface
, sampler
, offset_value
,
4365 coord_components
, grad_components
);
4366 } else if (devinfo
->gen
>= 5) {
4367 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4368 shadow_c
, lod
, lod2
, sample_index
,
4369 surface
, sampler
, offset_value
,
4370 coord_components
, grad_components
);
4372 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4373 shadow_c
, lod
, lod2
,
4375 coord_components
, grad_components
);
4380 * Initialize the header present in some typed and untyped surface
4384 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4386 fs_builder ubld
= bld
.exec_all().group(8, 0);
4387 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4388 ubld
.MOV(dst
, brw_imm_d(0));
4389 ubld
.MOV(component(dst
, 7), sample_mask
);
4394 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4395 const fs_reg
&sample_mask
)
4397 /* Get the logical send arguments. */
4398 const fs_reg
&addr
= inst
->src
[0];
4399 const fs_reg
&src
= inst
->src
[1];
4400 const fs_reg
&surface
= inst
->src
[2];
4401 const UNUSED fs_reg
&dims
= inst
->src
[3];
4402 const fs_reg
&arg
= inst
->src
[4];
4404 /* Calculate the total number of components of the payload. */
4405 const unsigned addr_sz
= inst
->components_read(0);
4406 const unsigned src_sz
= inst
->components_read(1);
4407 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4408 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4410 /* Allocate space for the payload. */
4411 fs_reg
*const components
= new fs_reg
[sz
];
4412 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4415 /* Construct the payload. */
4417 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4419 for (unsigned i
= 0; i
< addr_sz
; i
++)
4420 components
[n
++] = offset(addr
, bld
, i
);
4422 for (unsigned i
= 0; i
< src_sz
; i
++)
4423 components
[n
++] = offset(src
, bld
, i
);
4425 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4427 /* Update the original instruction. */
4429 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4430 inst
->header_size
= header_sz
;
4432 inst
->src
[0] = payload
;
4433 inst
->src
[1] = surface
;
4435 inst
->resize_sources(3);
4437 delete[] components
;
4441 lower_varying_pull_constant_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4443 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4445 if (devinfo
->gen
>= 7) {
4446 /* We are switching the instruction from an ALU-like instruction to a
4447 * send-from-grf instruction. Since sends can't handle strides or
4448 * source modifiers, we have to make a copy of the offset source.
4450 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
4451 bld
.MOV(tmp
, inst
->src
[1]);
4454 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
4457 const fs_reg
payload(MRF
, FIRST_PULL_LOAD_MRF(devinfo
->gen
),
4458 BRW_REGISTER_TYPE_UD
);
4460 bld
.MOV(byte_offset(payload
, REG_SIZE
), inst
->src
[1]);
4462 inst
->opcode
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4
;
4463 inst
->resize_sources(1);
4464 inst
->base_mrf
= payload
.nr
;
4465 inst
->header_size
= 1;
4466 inst
->mlen
= 1 + inst
->exec_size
/ 8;
4471 lower_math_logical_send(const fs_builder
&bld
, fs_inst
*inst
)
4473 assert(bld
.shader
->devinfo
->gen
< 6);
4476 inst
->mlen
= inst
->sources
* inst
->exec_size
/ 8;
4478 if (inst
->sources
> 1) {
4479 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
4480 * "Message Payload":
4482 * "Operand0[7]. For the INT DIV functions, this operand is the
4485 * "Operand1[7]. For the INT DIV functions, this operand is the
4488 const bool is_int_div
= inst
->opcode
!= SHADER_OPCODE_POW
;
4489 const fs_reg src0
= is_int_div
? inst
->src
[1] : inst
->src
[0];
4490 const fs_reg src1
= is_int_div
? inst
->src
[0] : inst
->src
[1];
4492 inst
->resize_sources(1);
4493 inst
->src
[0] = src0
;
4495 assert(inst
->exec_size
== 8);
4496 bld
.MOV(fs_reg(MRF
, inst
->base_mrf
+ 1, src1
.type
), src1
);
4501 fs_visitor::lower_logical_sends()
4503 bool progress
= false;
4505 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4506 const fs_builder
ibld(this, block
, inst
);
4508 switch (inst
->opcode
) {
4509 case FS_OPCODE_FB_WRITE_LOGICAL
:
4510 assert(stage
== MESA_SHADER_FRAGMENT
);
4511 lower_fb_write_logical_send(ibld
, inst
,
4512 (const brw_wm_prog_data
*)prog_data
,
4513 (const brw_wm_prog_key
*)key
,
4517 case SHADER_OPCODE_TEX_LOGICAL
:
4518 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4521 case SHADER_OPCODE_TXD_LOGICAL
:
4522 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4525 case SHADER_OPCODE_TXF_LOGICAL
:
4526 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4529 case SHADER_OPCODE_TXL_LOGICAL
:
4530 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4533 case SHADER_OPCODE_TXS_LOGICAL
:
4534 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4537 case FS_OPCODE_TXB_LOGICAL
:
4538 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4541 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4542 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4545 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4546 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4549 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4550 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4553 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4554 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4557 case SHADER_OPCODE_LOD_LOGICAL
:
4558 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4561 case SHADER_OPCODE_TG4_LOGICAL
:
4562 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4565 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4566 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4569 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4570 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_SAMPLEINFO
);
4573 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4574 lower_surface_logical_send(ibld
, inst
,
4575 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4579 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4580 lower_surface_logical_send(ibld
, inst
,
4581 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4582 ibld
.sample_mask_reg());
4585 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4586 lower_surface_logical_send(ibld
, inst
,
4587 SHADER_OPCODE_UNTYPED_ATOMIC
,
4588 ibld
.sample_mask_reg());
4591 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4592 lower_surface_logical_send(ibld
, inst
,
4593 SHADER_OPCODE_TYPED_SURFACE_READ
,
4597 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4598 lower_surface_logical_send(ibld
, inst
,
4599 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4600 ibld
.sample_mask_reg());
4603 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4604 lower_surface_logical_send(ibld
, inst
,
4605 SHADER_OPCODE_TYPED_ATOMIC
,
4606 ibld
.sample_mask_reg());
4609 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4610 lower_varying_pull_constant_logical_send(ibld
, inst
);
4613 case SHADER_OPCODE_RCP
:
4614 case SHADER_OPCODE_RSQ
:
4615 case SHADER_OPCODE_SQRT
:
4616 case SHADER_OPCODE_EXP2
:
4617 case SHADER_OPCODE_LOG2
:
4618 case SHADER_OPCODE_SIN
:
4619 case SHADER_OPCODE_COS
:
4620 case SHADER_OPCODE_POW
:
4621 case SHADER_OPCODE_INT_QUOTIENT
:
4622 case SHADER_OPCODE_INT_REMAINDER
:
4623 /* The math opcodes are overloaded for the send-like and
4624 * expression-like instructions which seems kind of icky. Gen6+ has
4625 * a native (but rather quirky) MATH instruction so we don't need to
4626 * do anything here. On Gen4-5 we'll have to lower the Gen6-like
4627 * logical instructions (which we can easily recognize because they
4628 * have mlen = 0) into send-like virtual instructions.
4630 if (devinfo
->gen
< 6 && inst
->mlen
== 0) {
4631 lower_math_logical_send(ibld
, inst
);
4646 invalidate_live_intervals();
4652 * Get the closest allowed SIMD width for instruction \p inst accounting for
4653 * some common regioning and execution control restrictions that apply to FPU
4654 * instructions. These restrictions don't necessarily have any relevance to
4655 * instructions not executed by the FPU pipeline like extended math, control
4656 * flow or send message instructions.
4658 * For virtual opcodes it's really up to the instruction -- In some cases
4659 * (e.g. where a virtual instruction unrolls into a simple sequence of FPU
4660 * instructions) it may simplify virtual instruction lowering if we can
4661 * enforce FPU-like regioning restrictions already on the virtual instruction,
4662 * in other cases (e.g. virtual send-like instructions) this may be
4663 * excessively restrictive.
4666 get_fpu_lowered_simd_width(const struct brw_device_info
*devinfo
,
4667 const fs_inst
*inst
)
4669 /* Maximum execution size representable in the instruction controls. */
4670 unsigned max_width
= MIN2(32, inst
->exec_size
);
4672 /* According to the PRMs:
4673 * "A. In Direct Addressing mode, a source cannot span more than 2
4674 * adjacent GRF registers.
4675 * B. A destination cannot span more than 2 adjacent GRF registers."
4677 * Look for the source or destination with the largest register region
4678 * which is the one that is going to limit the overall execution size of
4679 * the instruction due to this rule.
4681 unsigned reg_count
= inst
->regs_written
;
4683 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4684 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4686 /* Calculate the maximum execution size of the instruction based on the
4687 * factor by which it goes over the hardware limit of 2 GRFs.
4690 max_width
= MIN2(max_width
, inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2));
4692 /* According to the IVB PRMs:
4693 * "When destination spans two registers, the source MUST span two
4694 * registers. The exception to the above rule:
4696 * - When source is scalar, the source registers are not incremented.
4697 * - When source is packed integer Word and destination is packed
4698 * integer DWord, the source register is not incremented but the
4699 * source sub register is incremented."
4701 * The hardware specs from Gen4 to Gen7.5 mention similar regioning
4702 * restrictions. The code below intentionally doesn't check whether the
4703 * destination type is integer because empirically the hardware doesn't
4704 * seem to care what the actual type is as long as it's dword-aligned.
4706 if (devinfo
->gen
< 8) {
4707 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
4708 if (inst
->regs_written
== 2 &&
4709 inst
->regs_read(i
) != 0 && inst
->regs_read(i
) != 2 &&
4710 !is_uniform(inst
->src
[i
]) &&
4711 !(type_sz(inst
->dst
.type
) == 4 && inst
->dst
.stride
== 1 &&
4712 type_sz(inst
->src
[i
].type
) == 2 && inst
->src
[i
].stride
== 1))
4713 max_width
= MIN2(max_width
, inst
->exec_size
/
4714 inst
->regs_written
);
4718 /* From the IVB PRMs:
4719 * "When an instruction is SIMD32, the low 16 bits of the execution mask
4720 * are applied for both halves of the SIMD32 instruction. If different
4721 * execution mask channels are required, split the instruction into two
4722 * SIMD16 instructions."
4724 * There is similar text in the HSW PRMs. Gen4-6 don't even implement
4725 * 32-wide control flow support in hardware and will behave similarly.
4727 if (devinfo
->gen
< 8 && !inst
->force_writemask_all
)
4728 max_width
= MIN2(max_width
, 16);
4730 /* From the IVB PRMs (applies to HSW too):
4731 * "Instructions with condition modifiers must not use SIMD32."
4733 * From the BDW PRMs (applies to later hardware too):
4734 * "Ternary instruction with condition modifiers must not use SIMD32."
4736 if (inst
->conditional_mod
&& (devinfo
->gen
< 8 || inst
->is_3src(devinfo
)))
4737 max_width
= MIN2(max_width
, 16);
4739 /* From the IVB PRMs (applies to other devices that don't have the
4740 * brw_device_info::supports_simd16_3src flag set):
4741 * "In Align16 access mode, SIMD16 is not allowed for DW operations and
4742 * SIMD8 is not allowed for DF operations."
4744 if (inst
->is_3src(devinfo
) && !devinfo
->supports_simd16_3src
)
4745 max_width
= MIN2(max_width
, inst
->exec_size
/ reg_count
);
4747 /* Pre-Gen8 EUs are hardwired to use the QtrCtrl+1 (where QtrCtrl is
4748 * the 8-bit quarter of the execution mask signals specified in the
4749 * instruction control fields) for the second compressed half of any
4750 * single-precision instruction (for double-precision instructions
4751 * it's hardwired to use NibCtrl+1, at least on HSW), which means that
4752 * the EU will apply the wrong execution controls for the second
4753 * sequential GRF write if the number of channels per GRF is not exactly
4754 * eight in single-precision mode (or four in double-float mode).
4756 * In this situation we calculate the maximum size of the split
4757 * instructions so they only ever write to a single register.
4759 if (devinfo
->gen
< 8 && inst
->regs_written
> 1 &&
4760 !inst
->force_writemask_all
) {
4761 const unsigned channels_per_grf
= inst
->exec_size
/ inst
->regs_written
;
4762 unsigned exec_type_size
= 0;
4763 for (int i
= 0; i
< inst
->sources
; i
++) {
4764 if (inst
->src
[i
].file
!= BAD_FILE
)
4765 exec_type_size
= MAX2(exec_type_size
, type_sz(inst
->src
[i
].type
));
4767 assert(exec_type_size
);
4769 /* The hardware shifts exactly 8 channels per compressed half of the
4770 * instruction in single-precision mode and exactly 4 in double-precision.
4772 if (channels_per_grf
!= (exec_type_size
== 8 ? 4 : 8))
4773 max_width
= MIN2(max_width
, channels_per_grf
);
4776 /* Only power-of-two execution sizes are representable in the instruction
4779 return 1 << _mesa_logbase2(max_width
);
4783 * Get the closest native SIMD width supported by the hardware for instruction
4784 * \p inst. The instruction will be left untouched by
4785 * fs_visitor::lower_simd_width() if the returned value is equal to the
4786 * original execution size.
4789 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4790 const fs_inst
*inst
)
4792 switch (inst
->opcode
) {
4793 case BRW_OPCODE_MOV
:
4794 case BRW_OPCODE_SEL
:
4795 case BRW_OPCODE_NOT
:
4796 case BRW_OPCODE_AND
:
4798 case BRW_OPCODE_XOR
:
4799 case BRW_OPCODE_SHR
:
4800 case BRW_OPCODE_SHL
:
4801 case BRW_OPCODE_ASR
:
4802 case BRW_OPCODE_CMPN
:
4803 case BRW_OPCODE_CSEL
:
4804 case BRW_OPCODE_F32TO16
:
4805 case BRW_OPCODE_F16TO32
:
4806 case BRW_OPCODE_BFREV
:
4807 case BRW_OPCODE_BFE
:
4808 case BRW_OPCODE_ADD
:
4809 case BRW_OPCODE_MUL
:
4810 case BRW_OPCODE_AVG
:
4811 case BRW_OPCODE_FRC
:
4812 case BRW_OPCODE_RNDU
:
4813 case BRW_OPCODE_RNDD
:
4814 case BRW_OPCODE_RNDE
:
4815 case BRW_OPCODE_RNDZ
:
4816 case BRW_OPCODE_LZD
:
4817 case BRW_OPCODE_FBH
:
4818 case BRW_OPCODE_FBL
:
4819 case BRW_OPCODE_CBIT
:
4820 case BRW_OPCODE_SAD2
:
4821 case BRW_OPCODE_MAD
:
4822 case BRW_OPCODE_LRP
:
4823 case FS_OPCODE_PACK
:
4824 return get_fpu_lowered_simd_width(devinfo
, inst
);
4826 case BRW_OPCODE_CMP
: {
4827 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that
4828 * when the destination is a GRF the dependency-clear bit on the flag
4829 * register is cleared early.
4831 * Suggested workarounds are to disable coissuing CMP instructions
4832 * or to split CMP(16) instructions into two CMP(8) instructions.
4834 * We choose to split into CMP(8) instructions since disabling
4835 * coissuing would affect CMP instructions not otherwise affected by
4838 const unsigned max_width
= (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
4839 !inst
->dst
.is_null() ? 8 : ~0);
4840 return MIN2(max_width
, get_fpu_lowered_simd_width(devinfo
, inst
));
4842 case BRW_OPCODE_BFI1
:
4843 case BRW_OPCODE_BFI2
:
4844 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
4846 * "Force BFI instructions to be executed always in SIMD8."
4848 return MIN2(devinfo
->is_haswell
? 8 : ~0u,
4849 get_fpu_lowered_simd_width(devinfo
, inst
));
4852 assert(inst
->src
[0].file
== BAD_FILE
|| inst
->exec_size
<= 16);
4853 return inst
->exec_size
;
4855 case SHADER_OPCODE_RCP
:
4856 case SHADER_OPCODE_RSQ
:
4857 case SHADER_OPCODE_SQRT
:
4858 case SHADER_OPCODE_EXP2
:
4859 case SHADER_OPCODE_LOG2
:
4860 case SHADER_OPCODE_SIN
:
4861 case SHADER_OPCODE_COS
:
4862 /* Unary extended math instructions are limited to SIMD8 on Gen4 and
4865 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4866 devinfo
->gen
== 5 || devinfo
->is_g4x
? MIN2(16, inst
->exec_size
) :
4867 MIN2(8, inst
->exec_size
));
4869 case SHADER_OPCODE_POW
:
4870 /* SIMD16 is only allowed on Gen7+. */
4871 return (devinfo
->gen
>= 7 ? MIN2(16, inst
->exec_size
) :
4872 MIN2(8, inst
->exec_size
));
4874 case SHADER_OPCODE_INT_QUOTIENT
:
4875 case SHADER_OPCODE_INT_REMAINDER
:
4876 /* Integer division is limited to SIMD8 on all generations. */
4877 return MIN2(8, inst
->exec_size
);
4879 case FS_OPCODE_LINTERP
:
4880 case FS_OPCODE_GET_BUFFER_SIZE
:
4881 case FS_OPCODE_DDX_COARSE
:
4882 case FS_OPCODE_DDX_FINE
:
4883 case FS_OPCODE_DDY_COARSE
:
4884 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
4885 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
4886 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
4887 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
4888 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
4889 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
4890 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
4891 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
4892 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
4893 return MIN2(16, inst
->exec_size
);
4895 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL
:
4896 /* Pre-ILK hardware doesn't have a SIMD8 variant of the texel fetch
4897 * message used to implement varying pull constant loads, so expand it
4898 * to SIMD16. An alternative with longer message payload length but
4899 * shorter return payload would be to use the SIMD8 sampler message that
4900 * takes (header, u, v, r) as parameters instead of (header, u).
4902 return (devinfo
->gen
== 4 ? 16 : MIN2(16, inst
->exec_size
));
4904 case FS_OPCODE_DDY_FINE
:
4905 /* The implementation of this virtual opcode may require emitting
4906 * compressed Align16 instructions, which are severely limited on some
4909 * From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
4910 * Region Restrictions):
4912 * "In Align16 access mode, SIMD16 is not allowed for DW operations
4913 * and SIMD8 is not allowed for DF operations."
4915 * In this context, "DW operations" means "operations acting on 32-bit
4916 * values", so it includes operations on floats.
4918 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
4919 * (Instruction Compression -> Rules and Restrictions):
4921 * "A compressed instruction must be in Align1 access mode. Align16
4922 * mode instructions cannot be compressed."
4924 * Similar text exists in the g45 PRM.
4926 * Empirically, compressed align16 instructions using odd register
4927 * numbers don't appear to work on Sandybridge either.
4929 return (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
4930 (devinfo
->gen
== 7 && !devinfo
->is_haswell
) ?
4931 MIN2(8, inst
->exec_size
) : MIN2(16, inst
->exec_size
));
4933 case SHADER_OPCODE_MULH
:
4934 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4935 * is 8-wide on Gen7+.
4937 return (devinfo
->gen
>= 7 ? 8 :
4938 get_fpu_lowered_simd_width(devinfo
, inst
));
4940 case FS_OPCODE_FB_WRITE_LOGICAL
:
4941 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4944 assert(devinfo
->gen
!= 6 ||
4945 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4946 inst
->exec_size
== 8);
4947 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4948 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4949 8 : MIN2(16, inst
->exec_size
));
4951 case SHADER_OPCODE_TEX_LOGICAL
:
4952 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4953 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4954 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4955 case SHADER_OPCODE_LOD_LOGICAL
:
4956 case SHADER_OPCODE_TG4_LOGICAL
:
4957 case SHADER_OPCODE_SAMPLEINFO_LOGICAL
:
4958 return MIN2(16, inst
->exec_size
);
4960 case SHADER_OPCODE_TXD_LOGICAL
:
4961 /* TXD is unsupported in SIMD16 mode. */
4964 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4965 /* gather4_po_c is unsupported in SIMD16 mode. */
4966 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4967 return (shadow_c
.file
!= BAD_FILE
? 8 : MIN2(16, inst
->exec_size
));
4969 case SHADER_OPCODE_TXL_LOGICAL
:
4970 case FS_OPCODE_TXB_LOGICAL
: {
4971 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4972 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4973 * mode because the message exceeds the maximum length of 11.
4975 const fs_reg
&shadow_c
= inst
->src
[TEX_LOGICAL_SRC_SHADOW_C
];
4976 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4978 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4981 return MIN2(16, inst
->exec_size
);
4983 case SHADER_OPCODE_TXF_LOGICAL
:
4984 case SHADER_OPCODE_TXS_LOGICAL
:
4985 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4986 * messages. Use SIMD16 instead.
4988 if (devinfo
->gen
== 4)
4991 return MIN2(16, inst
->exec_size
);
4993 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4994 /* This opcode can take up to 6 arguments which means that in some
4995 * circumstances it can end up with a message that is too long in SIMD16
4998 const unsigned coord_components
=
4999 inst
->src
[TEX_LOGICAL_SRC_COORD_COMPONENTS
].ud
;
5000 /* First three arguments are the sample index and the two arguments for
5003 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
5006 return MIN2(16, inst
->exec_size
);
5009 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
5010 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
5011 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
5014 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
5015 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
5016 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
5017 return MIN2(16, inst
->exec_size
);
5019 case SHADER_OPCODE_URB_READ_SIMD8
:
5020 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
5021 case SHADER_OPCODE_URB_WRITE_SIMD8
:
5022 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
5023 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
5024 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
5025 return MIN2(8, inst
->exec_size
);
5027 case SHADER_OPCODE_MOV_INDIRECT
:
5028 /* Prior to Broadwell, we only have 8 address subregisters */
5029 return MIN3(devinfo
->gen
>= 8 ? 16 : 8,
5030 2 * REG_SIZE
/ (inst
->dst
.stride
* type_sz(inst
->dst
.type
)),
5033 case SHADER_OPCODE_LOAD_PAYLOAD
: {
5034 const unsigned reg_count
=
5035 DIV_ROUND_UP(inst
->dst
.component_size(inst
->exec_size
), REG_SIZE
);
5037 if (reg_count
> 2) {
5038 /* Only LOAD_PAYLOAD instructions with per-channel destination region
5039 * can be easily lowered (which excludes headers and heterogeneous
5042 assert(!inst
->header_size
);
5043 for (unsigned i
= 0; i
< inst
->sources
; i
++)
5044 assert(type_sz(inst
->dst
.type
) == type_sz(inst
->src
[i
].type
) ||
5045 inst
->src
[i
].file
== BAD_FILE
);
5047 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
5049 return inst
->exec_size
;
5053 return inst
->exec_size
;
5058 * Return true if splitting out the group of channels of instruction \p inst
5059 * given by lbld.group() requires allocating a temporary for the i-th source
5060 * of the lowered instruction.
5063 needs_src_copy(const fs_builder
&lbld
, const fs_inst
*inst
, unsigned i
)
5065 return !(is_periodic(inst
->src
[i
], lbld
.dispatch_width()) ||
5066 (inst
->components_read(i
) == 1 &&
5067 lbld
.dispatch_width() <= inst
->exec_size
));
5071 * Extract the data that would be consumed by the channel group given by
5072 * lbld.group() from the i-th source region of instruction \p inst and return
5073 * it as result in packed form. If any copy instructions are required they
5074 * will be emitted before the given \p inst in \p block.
5077 emit_unzip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
,
5080 /* Specified channel group from the source region. */
5081 const fs_reg src
= horiz_offset(inst
->src
[i
], lbld
.group());
5083 if (needs_src_copy(lbld
, inst
, i
)) {
5084 /* Builder of the right width to perform the copy avoiding uninitialized
5085 * data if the lowered execution size is greater than the original
5086 * execution size of the instruction.
5088 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5089 inst
->exec_size
), 0);
5090 const fs_reg tmp
= lbld
.vgrf(inst
->src
[i
].type
, inst
->components_read(i
));
5092 for (unsigned k
= 0; k
< inst
->components_read(i
); ++k
)
5093 cbld
.at(block
, inst
)
5094 .MOV(offset(tmp
, lbld
, k
), offset(src
, inst
->exec_size
, k
));
5098 } else if (is_periodic(inst
->src
[i
], lbld
.dispatch_width())) {
5099 /* The source is invariant for all dispatch_width-wide groups of the
5102 return inst
->src
[i
];
5105 /* We can just point the lowered instruction at the right channel group
5106 * from the original region.
5113 * Return true if splitting out the group of channels of instruction \p inst
5114 * given by lbld.group() requires allocating a temporary for the destination
5115 * of the lowered instruction and copying the data back to the original
5116 * destination region.
5119 needs_dst_copy(const fs_builder
&lbld
, const fs_inst
*inst
)
5121 /* If the instruction writes more than one component we'll have to shuffle
5122 * the results of multiple lowered instructions in order to make sure that
5123 * they end up arranged correctly in the original destination region.
5125 if (inst
->regs_written
* REG_SIZE
>
5126 inst
->dst
.component_size(inst
->exec_size
))
5129 /* If the lowered execution size is larger than the original the result of
5130 * the instruction won't fit in the original destination, so we'll have to
5131 * allocate a temporary in any case.
5133 if (lbld
.dispatch_width() > inst
->exec_size
)
5136 for (unsigned i
= 0; i
< inst
->sources
; i
++) {
5137 /* If we already made a copy of the source for other reasons there won't
5138 * be any overlap with the destination.
5140 if (needs_src_copy(lbld
, inst
, i
))
5143 /* In order to keep the logic simple we emit a copy whenever the
5144 * destination region doesn't exactly match an overlapping source, which
5145 * may point at the source and destination not being aligned group by
5146 * group which could cause one of the lowered instructions to overwrite
5147 * the data read from the same source by other lowered instructions.
5149 if (regions_overlap(inst
->dst
, inst
->regs_written
* REG_SIZE
,
5150 inst
->src
[i
], inst
->regs_read(i
) * REG_SIZE
) &&
5151 !inst
->dst
.equals(inst
->src
[i
]))
5159 * Insert data from a packed temporary into the channel group given by
5160 * lbld.group() of the destination region of instruction \p inst and return
5161 * the temporary as result. If any copy instructions are required they will
5162 * be emitted around the given \p inst in \p block.
5165 emit_zip(const fs_builder
&lbld
, bblock_t
*block
, fs_inst
*inst
)
5167 /* Builder of the right width to perform the copy avoiding uninitialized
5168 * data if the lowered execution size is greater than the original
5169 * execution size of the instruction.
5171 const fs_builder cbld
= lbld
.group(MIN2(lbld
.dispatch_width(),
5172 inst
->exec_size
), 0);
5174 /* Specified channel group from the destination region. */
5175 const fs_reg dst
= horiz_offset(inst
->dst
, lbld
.group());
5176 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5177 inst
->dst
.component_size(inst
->exec_size
);
5179 if (needs_dst_copy(lbld
, inst
)) {
5180 const fs_reg tmp
= lbld
.vgrf(inst
->dst
.type
, dst_size
);
5182 if (inst
->predicate
) {
5183 /* Handle predication by copying the original contents of
5184 * the destination into the temporary before emitting the
5185 * lowered instruction.
5187 for (unsigned k
= 0; k
< dst_size
; ++k
)
5188 cbld
.at(block
, inst
)
5189 .MOV(offset(tmp
, lbld
, k
), offset(dst
, inst
->exec_size
, k
));
5192 for (unsigned k
= 0; k
< dst_size
; ++k
)
5193 cbld
.at(block
, inst
->next
)
5194 .MOV(offset(dst
, inst
->exec_size
, k
), offset(tmp
, lbld
, k
));
5199 /* No need to allocate a temporary for the lowered instruction, just
5200 * take the right group of channels from the original region.
5207 fs_visitor::lower_simd_width()
5209 bool progress
= false;
5211 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5212 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
5214 if (lower_width
!= inst
->exec_size
) {
5215 /* Builder matching the original instruction. We may also need to
5216 * emit an instruction of width larger than the original, set the
5217 * execution size of the builder to the highest of both for now so
5218 * we're sure that both cases can be handled.
5220 const unsigned max_width
= MAX2(inst
->exec_size
, lower_width
);
5221 const fs_builder ibld
= bld
.at(block
, inst
)
5222 .exec_all(inst
->force_writemask_all
)
5223 .group(max_width
, inst
->group
/ max_width
);
5225 /* Split the copies in chunks of the execution width of either the
5226 * original or the lowered instruction, whichever is lower.
5228 const unsigned n
= DIV_ROUND_UP(inst
->exec_size
, lower_width
);
5229 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
5230 inst
->dst
.component_size(inst
->exec_size
);
5232 assert(!inst
->writes_accumulator
&& !inst
->mlen
);
5234 for (unsigned i
= 0; i
< n
; i
++) {
5235 /* Emit a copy of the original instruction with the lowered width.
5236 * If the EOT flag was set throw it away except for the last
5237 * instruction to avoid killing the thread prematurely.
5239 fs_inst split_inst
= *inst
;
5240 split_inst
.exec_size
= lower_width
;
5241 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
5243 /* Select the correct channel enables for the i-th group, then
5244 * transform the sources and destination and emit the lowered
5247 const fs_builder lbld
= ibld
.group(lower_width
, i
);
5249 for (unsigned j
= 0; j
< inst
->sources
; j
++)
5250 split_inst
.src
[j
] = emit_unzip(lbld
, block
, inst
, j
);
5252 split_inst
.dst
= emit_zip(lbld
, block
, inst
);
5253 split_inst
.regs_written
= DIV_ROUND_UP(
5254 split_inst
.dst
.component_size(lower_width
) * dst_size
,
5257 lbld
.emit(split_inst
);
5260 inst
->remove(block
);
5266 invalidate_live_intervals();
5272 fs_visitor::dump_instructions()
5274 dump_instructions(NULL
);
5278 fs_visitor::dump_instructions(const char *name
)
5280 FILE *file
= stderr
;
5281 if (name
&& geteuid() != 0) {
5282 file
= fopen(name
, "w");
5288 calculate_register_pressure();
5289 int ip
= 0, max_pressure
= 0;
5290 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
5291 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
5292 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
5293 dump_instruction(inst
, file
);
5296 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
5299 foreach_in_list(backend_instruction
, inst
, &instructions
) {
5300 fprintf(file
, "%4d: ", ip
++);
5301 dump_instruction(inst
, file
);
5305 if (file
!= stderr
) {
5311 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
5313 dump_instruction(be_inst
, stderr
);
5317 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
5319 fs_inst
*inst
= (fs_inst
*)be_inst
;
5321 if (inst
->predicate
) {
5322 fprintf(file
, "(%cf0.%d) ",
5323 inst
->predicate_inverse
? '-' : '+',
5327 fprintf(file
, "%s", brw_instruction_name(devinfo
, inst
->opcode
));
5329 fprintf(file
, ".sat");
5330 if (inst
->conditional_mod
) {
5331 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
5332 if (!inst
->predicate
&&
5333 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
5334 inst
->opcode
!= BRW_OPCODE_IF
&&
5335 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
5336 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
5339 fprintf(file
, "(%d) ", inst
->exec_size
);
5342 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
5346 fprintf(file
, "(EOT) ");
5349 switch (inst
->dst
.file
) {
5351 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
5352 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
5353 inst
->dst
.subreg_offset
)
5354 fprintf(file
, "+%d.%d",
5355 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
5358 fprintf(file
, "g%d", inst
->dst
.nr
);
5361 fprintf(file
, "m%d", inst
->dst
.nr
);
5364 fprintf(file
, "(null)");
5367 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5370 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
5373 switch (inst
->dst
.nr
) {
5375 fprintf(file
, "null");
5377 case BRW_ARF_ADDRESS
:
5378 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
5380 case BRW_ARF_ACCUMULATOR
:
5381 fprintf(file
, "acc%d", inst
->dst
.subnr
);
5384 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5387 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
5390 if (inst
->dst
.subnr
)
5391 fprintf(file
, "+%d", inst
->dst
.subnr
);
5394 unreachable("not reached");
5396 if (inst
->dst
.stride
!= 1)
5397 fprintf(file
, "<%u>", inst
->dst
.stride
);
5398 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
5400 for (int i
= 0; i
< inst
->sources
; i
++) {
5401 if (inst
->src
[i
].negate
)
5403 if (inst
->src
[i
].abs
)
5405 switch (inst
->src
[i
].file
) {
5407 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
5408 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
5409 inst
->src
[i
].subreg_offset
)
5410 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5411 inst
->src
[i
].subreg_offset
);
5414 fprintf(file
, "g%d", inst
->src
[i
].nr
);
5417 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
5420 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
5423 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
5424 if (inst
->src
[i
].subreg_offset
) {
5425 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
5426 inst
->src
[i
].subreg_offset
);
5430 fprintf(file
, "(null)");
5433 switch (inst
->src
[i
].type
) {
5434 case BRW_REGISTER_TYPE_F
:
5435 fprintf(file
, "%-gf", inst
->src
[i
].f
);
5437 case BRW_REGISTER_TYPE_DF
:
5438 fprintf(file
, "%fdf", inst
->src
[i
].df
);
5440 case BRW_REGISTER_TYPE_W
:
5441 case BRW_REGISTER_TYPE_D
:
5442 fprintf(file
, "%dd", inst
->src
[i
].d
);
5444 case BRW_REGISTER_TYPE_UW
:
5445 case BRW_REGISTER_TYPE_UD
:
5446 fprintf(file
, "%uu", inst
->src
[i
].ud
);
5448 case BRW_REGISTER_TYPE_VF
:
5449 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
5450 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
5451 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
5452 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
5453 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
5456 fprintf(file
, "???");
5461 switch (inst
->src
[i
].nr
) {
5463 fprintf(file
, "null");
5465 case BRW_ARF_ADDRESS
:
5466 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
5468 case BRW_ARF_ACCUMULATOR
:
5469 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
5472 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5475 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
5478 if (inst
->src
[i
].subnr
)
5479 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
5482 if (inst
->src
[i
].abs
)
5485 if (inst
->src
[i
].file
!= IMM
) {
5487 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
5488 unsigned hstride
= inst
->src
[i
].hstride
;
5489 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
5491 stride
= inst
->src
[i
].stride
;
5494 fprintf(file
, "<%u>", stride
);
5496 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
5499 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
5500 fprintf(file
, ", ");
5505 if (inst
->force_writemask_all
)
5506 fprintf(file
, "NoMask ");
5508 if (inst
->exec_size
!= dispatch_width
)
5509 fprintf(file
, "group%d ", inst
->group
);
5511 fprintf(file
, "\n");
5515 * Possibly returns an instruction that set up @param reg.
5517 * Sometimes we want to take the result of some expression/variable
5518 * dereference tree and rewrite the instruction generating the result
5519 * of the tree. When processing the tree, we know that the
5520 * instructions generated are all writing temporaries that are dead
5521 * outside of this tree. So, if we have some instructions that write
5522 * a temporary, we're free to point that temp write somewhere else.
5524 * Note that this doesn't guarantee that the instruction generated
5525 * only reg -- it might be the size=4 destination of a texture instruction.
5528 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
5533 end
->is_partial_write() ||
5534 !reg
.equals(end
->dst
)) {
5542 fs_visitor::setup_fs_payload_gen6()
5544 assert(stage
== MESA_SHADER_FRAGMENT
);
5545 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5547 unsigned barycentric_interp_modes
=
5548 (stage
== MESA_SHADER_FRAGMENT
) ?
5549 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
5551 assert(devinfo
->gen
>= 6);
5553 /* R0-1: masks, pixel X/Y coordinates. */
5554 payload
.num_regs
= 2;
5555 /* R2: only for 32-pixel dispatch.*/
5557 /* R3-26: barycentric interpolation coordinates. These appear in the
5558 * same order that they appear in the brw_barycentric_mode
5559 * enum. Each set of coordinates occupies 2 registers if dispatch width
5560 * == 8 and 4 registers if dispatch width == 16. Coordinates only
5561 * appear if they were enabled using the "Barycentric Interpolation
5562 * Mode" bits in WM_STATE.
5564 for (int i
= 0; i
< BRW_BARYCENTRIC_MODE_COUNT
; ++i
) {
5565 if (barycentric_interp_modes
& (1 << i
)) {
5566 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
5567 payload
.num_regs
+= 2;
5568 if (dispatch_width
== 16) {
5569 payload
.num_regs
+= 2;
5574 /* R27: interpolated depth if uses source depth */
5575 prog_data
->uses_src_depth
=
5576 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5577 if (prog_data
->uses_src_depth
) {
5578 payload
.source_depth_reg
= payload
.num_regs
;
5580 if (dispatch_width
== 16) {
5581 /* R28: interpolated depth if not SIMD8. */
5586 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
5587 prog_data
->uses_src_w
=
5588 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
5589 if (prog_data
->uses_src_w
) {
5590 payload
.source_w_reg
= payload
.num_regs
;
5592 if (dispatch_width
== 16) {
5593 /* R30: interpolated W if not SIMD8. */
5598 /* R31: MSAA position offsets. */
5599 if (prog_data
->persample_dispatch
&&
5600 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_POS
)) {
5601 /* From the Ivy Bridge PRM documentation for 3DSTATE_PS:
5603 * "MSDISPMODE_PERSAMPLE is required in order to select
5606 * So we can only really get sample positions if we are doing real
5607 * per-sample dispatch. If we need gl_SamplePosition and we don't have
5608 * persample dispatch, we hard-code it to 0.5.
5610 prog_data
->uses_pos_offset
= true;
5611 payload
.sample_pos_reg
= payload
.num_regs
;
5615 /* R32: MSAA input coverage mask */
5616 prog_data
->uses_sample_mask
=
5617 (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) != 0;
5618 if (prog_data
->uses_sample_mask
) {
5619 assert(devinfo
->gen
>= 7);
5620 payload
.sample_mask_in_reg
= payload
.num_regs
;
5622 if (dispatch_width
== 16) {
5623 /* R33: input coverage mask if not SIMD8. */
5628 /* R34-: bary for 32-pixel. */
5629 /* R58-59: interp W for 32-pixel. */
5631 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5632 source_depth_to_render_target
= true;
5637 fs_visitor::setup_vs_payload()
5639 /* R0: thread header, R1: urb handles */
5640 payload
.num_regs
= 2;
5644 fs_visitor::setup_gs_payload()
5646 assert(stage
== MESA_SHADER_GEOMETRY
);
5648 struct brw_gs_prog_data
*gs_prog_data
=
5649 (struct brw_gs_prog_data
*) prog_data
;
5650 struct brw_vue_prog_data
*vue_prog_data
=
5651 (struct brw_vue_prog_data
*) prog_data
;
5653 /* R0: thread header, R1: output URB handles */
5654 payload
.num_regs
= 2;
5656 if (gs_prog_data
->include_primitive_id
) {
5657 /* R2: Primitive ID 0..7 */
5661 /* Use a maximum of 24 registers for push-model inputs. */
5662 const unsigned max_push_components
= 24;
5664 /* If pushing our inputs would take too many registers, reduce the URB read
5665 * length (which is in HWords, or 8 registers), and resort to pulling.
5667 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
5668 * have to multiply by VerticesIn to obtain the total storage requirement.
5670 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
5671 max_push_components
) {
5672 gs_prog_data
->base
.include_vue_handles
= true;
5674 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
5675 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
5677 vue_prog_data
->urb_read_length
=
5678 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
5683 fs_visitor::setup_cs_payload()
5685 assert(devinfo
->gen
>= 7);
5686 payload
.num_regs
= 1;
5690 fs_visitor::calculate_register_pressure()
5692 invalidate_live_intervals();
5693 calculate_live_intervals();
5695 unsigned num_instructions
= 0;
5696 foreach_block(block
, cfg
)
5697 num_instructions
+= block
->instructions
.length();
5699 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5701 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5702 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5703 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5708 * Look for repeated FS_OPCODE_MOV_DISPATCH_TO_FLAGS and drop the later ones.
5710 * The needs_unlit_centroid_workaround ends up producing one of these per
5711 * channel of centroid input, so it's good to clean them up.
5713 * An assumption here is that nothing ever modifies the dispatched pixels
5714 * value that FS_OPCODE_MOV_DISPATCH_TO_FLAGS reads from, but the hardware
5715 * dictates that anyway.
5718 fs_visitor::opt_drop_redundant_mov_to_flags()
5720 bool flag_mov_found
[2] = {false};
5721 bool progress
= false;
5723 /* Instructions removed by this pass can only be added if this were true */
5724 if (!devinfo
->needs_unlit_centroid_workaround
)
5727 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
5728 if (inst
->is_control_flow()) {
5729 memset(flag_mov_found
, 0, sizeof(flag_mov_found
));
5730 } else if (inst
->opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
) {
5731 if (!flag_mov_found
[inst
->flag_subreg
]) {
5732 flag_mov_found
[inst
->flag_subreg
] = true;
5734 inst
->remove(block
);
5737 } else if (inst
->flags_written()) {
5738 flag_mov_found
[inst
->flag_subreg
] = false;
5746 fs_visitor::optimize()
5748 /* Start by validating the shader we currently have. */
5751 /* bld is the common builder object pointing at the end of the program we
5752 * used to translate it into i965 IR. For the optimization and lowering
5753 * passes coming next, any code added after the end of the program without
5754 * having explicitly called fs_builder::at() clearly points at a mistake.
5755 * Ideally optimization passes wouldn't be part of the visitor so they
5756 * wouldn't have access to bld at all, but they do, so just in case some
5757 * pass forgets to ask for a location explicitly set it to NULL here to
5758 * make it trip. The dispatch width is initialized to a bogus value to
5759 * make sure that optimizations set the execution controls explicitly to
5760 * match the code they are manipulating instead of relying on the defaults.
5762 bld
= fs_builder(this, 64);
5764 assign_constant_locations();
5765 lower_constant_loads();
5769 split_virtual_grfs();
5772 #define OPT(pass, args...) ({ \
5774 bool this_progress = pass(args); \
5776 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5777 char filename[64]; \
5778 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5779 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5781 backend_shader::dump_instructions(filename); \
5786 progress = progress || this_progress; \
5790 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5792 snprintf(filename
, 64, "%s%d-%s-00-00-start",
5793 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5795 backend_shader::dump_instructions(filename
);
5798 bool progress
= false;
5802 OPT(opt_drop_redundant_mov_to_flags
);
5809 OPT(remove_duplicate_mrf_writes
);
5813 OPT(opt_copy_propagate
);
5814 OPT(opt_predicated_break
, this);
5815 OPT(opt_cmod_propagation
);
5816 OPT(dead_code_eliminate
);
5817 OPT(opt_peephole_sel
);
5818 OPT(dead_control_flow_eliminate
, this);
5819 OPT(opt_register_renaming
);
5820 OPT(opt_saturate_propagation
);
5821 OPT(register_coalesce
);
5822 OPT(compute_to_mrf
);
5823 OPT(eliminate_find_live_channel
);
5825 OPT(compact_virtual_grfs
);
5831 if (OPT(lower_pack
)) {
5832 OPT(register_coalesce
);
5833 OPT(dead_code_eliminate
);
5836 if (OPT(lower_d2x
)) {
5837 OPT(opt_copy_propagate
);
5838 OPT(dead_code_eliminate
);
5841 OPT(lower_simd_width
);
5843 /* After SIMD lowering just in case we had to unroll the EOT send. */
5844 OPT(opt_sampler_eot
);
5846 OPT(lower_logical_sends
);
5849 OPT(opt_copy_propagate
);
5850 /* Only run after logical send lowering because it's easier to implement
5851 * in terms of physical sends.
5853 if (OPT(opt_zero_samples
))
5854 OPT(opt_copy_propagate
);
5855 /* Run after logical send lowering to give it a chance to CSE the
5856 * LOAD_PAYLOAD instructions created to construct the payloads of
5857 * e.g. texturing messages in cases where it wasn't possible to CSE the
5858 * whole logical instruction.
5861 OPT(register_coalesce
);
5862 OPT(compute_to_mrf
);
5863 OPT(dead_code_eliminate
);
5864 OPT(remove_duplicate_mrf_writes
);
5865 OPT(opt_peephole_sel
);
5868 OPT(opt_redundant_discard_jumps
);
5870 if (OPT(lower_load_payload
)) {
5871 split_virtual_grfs();
5872 OPT(register_coalesce
);
5873 OPT(compute_to_mrf
);
5874 OPT(dead_code_eliminate
);
5877 OPT(opt_combine_constants
);
5878 OPT(lower_integer_multiplication
);
5880 if (devinfo
->gen
<= 5 && OPT(lower_minmax
)) {
5881 OPT(opt_cmod_propagation
);
5883 OPT(opt_copy_propagate
);
5884 OPT(dead_code_eliminate
);
5887 lower_uniform_pull_constant_loads();
5893 * Three source instruction must have a GRF/MRF destination register.
5894 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5897 fs_visitor::fixup_3src_null_dest()
5899 bool progress
= false;
5901 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5902 if (inst
->is_3src(devinfo
) && inst
->dst
.is_null()) {
5903 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5910 invalidate_live_intervals();
5914 fs_visitor::allocate_registers(bool allow_spilling
)
5916 bool allocated_without_spills
;
5918 static const enum instruction_scheduler_mode pre_modes
[] = {
5920 SCHEDULE_PRE_NON_LIFO
,
5924 bool spill_all
= allow_spilling
&& (INTEL_DEBUG
& DEBUG_SPILL_FS
);
5926 /* Try each scheduling heuristic to see if it can successfully register
5927 * allocate without spilling. They should be ordered by decreasing
5928 * performance but increasing likelihood of allocating.
5930 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5931 schedule_instructions(pre_modes
[i
]);
5934 assign_regs_trivial();
5935 allocated_without_spills
= true;
5937 allocated_without_spills
= assign_regs(false, spill_all
);
5939 if (allocated_without_spills
)
5943 if (!allocated_without_spills
) {
5944 /* We assume that any spilling is worse than just dropping back to
5945 * SIMD8. There's probably actually some intermediate point where
5946 * SIMD16 with a couple of spills is still better.
5948 if (dispatch_width
> min_dispatch_width
) {
5949 fail("Failure to register allocate. Reduce number of "
5950 "live scalar values to avoid this.");
5952 compiler
->shader_perf_log(log_data
,
5953 "%s shader triggered register spilling. "
5954 "Try reducing the number of live scalar "
5955 "values to improve performance.\n",
5959 /* Since we're out of heuristics, just go spill registers until we
5960 * get an allocation.
5962 while (!assign_regs(true, spill_all
)) {
5968 assert(last_scratch
== 0 || allow_spilling
);
5970 /* This must come after all optimization and register allocation, since
5971 * it inserts dead code that happens to have side effects, and it does
5972 * so based on the actual physical registers in use.
5974 insert_gen4_send_dependency_workarounds();
5979 schedule_instructions(SCHEDULE_POST
);
5981 if (last_scratch
> 0) {
5982 unsigned max_scratch_size
= 2 * 1024 * 1024;
5984 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5986 if (stage
== MESA_SHADER_COMPUTE
) {
5987 if (devinfo
->is_haswell
) {
5988 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5989 * field documentation, Haswell supports a minimum of 2kB of
5990 * scratch space for compute shaders, unlike every other stage
5993 prog_data
->total_scratch
= MAX2(prog_data
->total_scratch
, 2048);
5994 } else if (devinfo
->gen
<= 7) {
5995 /* According to the MEDIA_VFE_STATE's "Per Thread Scratch Space"
5996 * field documentation, platforms prior to Haswell measure scratch
5997 * size linearly with a range of [1kB, 12kB] and 1kB granularity.
5999 prog_data
->total_scratch
= ALIGN(last_scratch
, 1024);
6000 max_scratch_size
= 12 * 1024;
6004 /* We currently only support up to 2MB of scratch space. If we
6005 * need to support more eventually, the documentation suggests
6006 * that we could allocate a larger buffer, and partition it out
6007 * ourselves. We'd just have to undo the hardware's address
6008 * calculation by subtracting (FFTID * Per Thread Scratch Space)
6009 * and then add FFTID * (Larger Per Thread Scratch Space).
6011 * See 3D-Media-GPGPU Engine > Media GPGPU Pipeline >
6012 * Thread Group Tracking > Local Memory/Scratch Space.
6014 assert(prog_data
->total_scratch
< max_scratch_size
);
6019 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
6021 assert(stage
== MESA_SHADER_VERTEX
);
6025 if (shader_time_index
>= 0)
6026 emit_shader_time_begin();
6033 compute_clip_distance(clip_planes
);
6037 if (shader_time_index
>= 0)
6038 emit_shader_time_end();
6044 assign_curb_setup();
6045 assign_vs_urb_setup();
6047 fixup_3src_null_dest();
6048 allocate_registers(true);
6054 fs_visitor::run_tcs_single_patch()
6056 assert(stage
== MESA_SHADER_TESS_CTRL
);
6058 struct brw_tcs_prog_data
*tcs_prog_data
=
6059 (struct brw_tcs_prog_data
*) prog_data
;
6061 /* r1-r4 contain the ICP handles. */
6062 payload
.num_regs
= 5;
6064 if (shader_time_index
>= 0)
6065 emit_shader_time_begin();
6067 /* Initialize gl_InvocationID */
6068 fs_reg channels_uw
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
6069 fs_reg channels_ud
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6070 bld
.MOV(channels_uw
, fs_reg(brw_imm_uv(0x76543210)));
6071 bld
.MOV(channels_ud
, channels_uw
);
6073 if (tcs_prog_data
->instances
== 1) {
6074 invocation_id
= channels_ud
;
6076 invocation_id
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6078 /* Get instance number from g0.2 bits 23:17, and multiply it by 8. */
6079 fs_reg t
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6080 fs_reg instance_times_8
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
6081 bld
.AND(t
, fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
)),
6082 brw_imm_ud(INTEL_MASK(23, 17)));
6083 bld
.SHR(instance_times_8
, t
, brw_imm_ud(17 - 3));
6085 bld
.ADD(invocation_id
, instance_times_8
, channels_ud
);
6088 /* Fix the disptach mask */
6089 if (nir
->info
.tcs
.vertices_out
% 8) {
6090 bld
.CMP(bld
.null_reg_ud(), invocation_id
,
6091 brw_imm_ud(nir
->info
.tcs
.vertices_out
), BRW_CONDITIONAL_L
);
6092 bld
.IF(BRW_PREDICATE_NORMAL
);
6097 if (nir
->info
.tcs
.vertices_out
% 8) {
6098 bld
.emit(BRW_OPCODE_ENDIF
);
6101 /* Emit EOT write; set TR DS Cache bit */
6103 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
6104 fs_reg(brw_imm_ud(WRITEMASK_X
<< 16)),
6105 fs_reg(brw_imm_ud(0)),
6107 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
6108 bld
.LOAD_PAYLOAD(payload
, srcs
, 3, 2);
6110 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
,
6111 bld
.null_reg_ud(), payload
);
6115 if (shader_time_index
>= 0)
6116 emit_shader_time_end();
6125 assign_curb_setup();
6126 assign_tcs_single_patch_urb_setup();
6128 fixup_3src_null_dest();
6129 allocate_registers(true);
6135 fs_visitor::run_tes()
6137 assert(stage
== MESA_SHADER_TESS_EVAL
);
6139 /* R0: thread header, R1-3: gl_TessCoord.xyz, R4: URB handles */
6140 payload
.num_regs
= 5;
6142 if (shader_time_index
>= 0)
6143 emit_shader_time_begin();
6152 if (shader_time_index
>= 0)
6153 emit_shader_time_end();
6159 assign_curb_setup();
6160 assign_tes_urb_setup();
6162 fixup_3src_null_dest();
6163 allocate_registers(true);
6169 fs_visitor::run_gs()
6171 assert(stage
== MESA_SHADER_GEOMETRY
);
6175 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
6177 if (gs_compile
->control_data_header_size_bits
> 0) {
6178 /* Create a VGRF to store accumulated control data bits. */
6179 this->control_data_bits
= vgrf(glsl_type::uint_type
);
6181 /* If we're outputting more than 32 control data bits, then EmitVertex()
6182 * will set control_data_bits to 0 after emitting the first vertex.
6183 * Otherwise, we need to initialize it to 0 here.
6185 if (gs_compile
->control_data_header_size_bits
<= 32) {
6186 const fs_builder abld
= bld
.annotate("initialize control data bits");
6187 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
6191 if (shader_time_index
>= 0)
6192 emit_shader_time_begin();
6196 emit_gs_thread_end();
6198 if (shader_time_index
>= 0)
6199 emit_shader_time_end();
6208 assign_curb_setup();
6209 assign_gs_urb_setup();
6211 fixup_3src_null_dest();
6212 allocate_registers(true);
6218 fs_visitor::run_fs(bool allow_spilling
, bool do_rep_send
)
6220 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
6221 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
6223 assert(stage
== MESA_SHADER_FRAGMENT
);
6225 if (devinfo
->gen
>= 6)
6226 setup_fs_payload_gen6();
6228 setup_fs_payload_gen4();
6232 } else if (do_rep_send
) {
6233 assert(dispatch_width
== 16);
6234 emit_repclear_shader();
6236 if (shader_time_index
>= 0)
6237 emit_shader_time_begin();
6239 calculate_urb_setup();
6240 if (nir
->info
.inputs_read
> 0) {
6241 if (devinfo
->gen
< 6)
6242 emit_interpolation_setup_gen4();
6244 emit_interpolation_setup_gen6();
6247 /* We handle discards by keeping track of the still-live pixels in f0.1.
6248 * Initialize it with the dispatched pixels.
6250 if (wm_prog_data
->uses_kill
) {
6251 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
6252 discard_init
->flag_subreg
= 1;
6255 /* Generate FS IR for main(). (the visitor only descends into
6256 * functions called "main").
6263 if (wm_prog_data
->uses_kill
)
6264 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
6266 if (wm_key
->alpha_test_func
)
6271 if (shader_time_index
>= 0)
6272 emit_shader_time_end();
6278 assign_curb_setup();
6281 fixup_3src_null_dest();
6282 allocate_registers(allow_spilling
);
6292 fs_visitor::run_cs()
6294 assert(stage
== MESA_SHADER_COMPUTE
);
6298 if (shader_time_index
>= 0)
6299 emit_shader_time_begin();
6301 if (devinfo
->is_haswell
&& prog_data
->total_shared
> 0) {
6302 /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
6303 const fs_builder abld
= bld
.exec_all().group(1, 0);
6304 abld
.MOV(retype(suboffset(brw_sr0_reg(), 1), BRW_REGISTER_TYPE_UW
),
6305 suboffset(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
), 1));
6313 emit_cs_terminate();
6315 if (shader_time_index
>= 0)
6316 emit_shader_time_end();
6322 assign_curb_setup();
6324 fixup_3src_null_dest();
6325 allocate_registers(true);
6334 * Return a bitfield where bit n is set if barycentric interpolation mode n
6335 * (see enum brw_barycentric_mode) is needed by the fragment shader.
6338 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
6339 const nir_shader
*shader
)
6341 unsigned barycentric_interp_modes
= 0;
6343 nir_foreach_variable(var
, &shader
->inputs
) {
6344 /* Ignore WPOS; it doesn't require interpolation. */
6345 if (var
->data
.location
== VARYING_SLOT_POS
)
6348 /* Flat inputs don't need barycentric modes. */
6349 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6352 /* Determine the set (or sets) of barycentric coordinates needed to
6353 * interpolate this variable. Note that when
6354 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
6355 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
6356 * for lit pixels, so we need both sets of barycentric coordinates.
6358 enum brw_barycentric_mode bary_mode
=
6359 barycentric_mode((glsl_interp_mode
) var
->data
.interpolation
,
6360 var
->data
.centroid
, var
->data
.sample
);
6362 barycentric_interp_modes
|= 1 << bary_mode
;
6364 if (var
->data
.centroid
&& devinfo
->needs_unlit_centroid_workaround
)
6365 barycentric_interp_modes
|= 1 << centroid_to_pixel(bary_mode
);
6368 return barycentric_interp_modes
;
6372 brw_compute_flat_inputs(struct brw_wm_prog_data
*prog_data
,
6373 const nir_shader
*shader
)
6375 prog_data
->flat_inputs
= 0;
6377 nir_foreach_variable(var
, &shader
->inputs
) {
6378 int input_index
= prog_data
->urb_setup
[var
->data
.location
];
6380 if (input_index
< 0)
6384 if (var
->data
.interpolation
== INTERP_MODE_FLAT
)
6385 prog_data
->flat_inputs
|= (1 << input_index
);
6390 computed_depth_mode(const nir_shader
*shader
)
6392 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
6393 switch (shader
->info
.fs
.depth_layout
) {
6394 case FRAG_DEPTH_LAYOUT_NONE
:
6395 case FRAG_DEPTH_LAYOUT_ANY
:
6396 return BRW_PSCDEPTH_ON
;
6397 case FRAG_DEPTH_LAYOUT_GREATER
:
6398 return BRW_PSCDEPTH_ON_GE
;
6399 case FRAG_DEPTH_LAYOUT_LESS
:
6400 return BRW_PSCDEPTH_ON_LE
;
6401 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
6402 return BRW_PSCDEPTH_OFF
;
6405 return BRW_PSCDEPTH_OFF
;
6409 * Apply default interpolation settings to FS inputs which don't specify any.
6412 brw_nir_set_default_interpolation(const struct brw_device_info
*devinfo
,
6413 struct nir_shader
*nir
,
6414 bool api_flat_shade
,
6415 bool per_sample_interpolation
)
6417 assert(nir
->stage
== MESA_SHADER_FRAGMENT
);
6419 nir_foreach_variable(var
, &nir
->inputs
) {
6420 /* Apply default interpolation mode.
6422 * Everything defaults to smooth except for the legacy GL color
6423 * built-in variables, which might be flat depending on API state.
6425 if (var
->data
.interpolation
== INTERP_MODE_NONE
) {
6426 const bool flat
= api_flat_shade
&&
6427 (var
->data
.location
== VARYING_SLOT_COL0
||
6428 var
->data
.location
== VARYING_SLOT_COL1
);
6430 var
->data
.interpolation
= flat
? INTERP_MODE_FLAT
6431 : INTERP_MODE_SMOOTH
;
6434 /* Apply 'sample' if necessary for API state. */
6435 if (per_sample_interpolation
&&
6436 var
->data
.interpolation
!= INTERP_MODE_FLAT
) {
6437 var
->data
.centroid
= false;
6438 var
->data
.sample
= true;
6441 /* On Ironlake and below, there is only one interpolation mode.
6442 * Centroid interpolation doesn't mean anything on this hardware --
6443 * there is no multisampling.
6445 if (devinfo
->gen
< 6) {
6446 var
->data
.centroid
= false;
6447 var
->data
.sample
= false;
6453 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
6455 const struct brw_wm_prog_key
*key
,
6456 struct brw_wm_prog_data
*prog_data
,
6457 const nir_shader
*src_shader
,
6458 struct gl_program
*prog
,
6459 int shader_time_index8
, int shader_time_index16
,
6460 bool allow_spilling
,
6462 unsigned *final_assembly_size
,
6465 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6466 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6468 brw_nir_set_default_interpolation(compiler
->devinfo
, shader
,
6469 key
->flat_shade
, key
->persample_interp
);
6470 brw_nir_lower_fs_inputs(shader
);
6471 brw_nir_lower_fs_outputs(shader
);
6472 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6474 /* key->alpha_test_func means simulating alpha testing via discards,
6475 * so the shader definitely kills pixels.
6477 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
6478 prog_data
->uses_omask
= key
->multisample_fbo
&&
6479 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
6480 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
6481 prog_data
->computed_stencil
=
6482 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
6484 prog_data
->persample_dispatch
=
6485 key
->multisample_fbo
&&
6486 (key
->persample_interp
||
6487 (shader
->info
.system_values_read
& (SYSTEM_BIT_SAMPLE_ID
|
6488 SYSTEM_BIT_SAMPLE_POS
)) ||
6489 shader
->info
.fs
.uses_sample_qualifier
);
6491 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
6493 prog_data
->barycentric_interp_modes
=
6494 brw_compute_barycentric_interp_modes(compiler
->devinfo
, shader
);
6496 cfg_t
*simd8_cfg
= NULL
, *simd16_cfg
= NULL
;
6497 uint8_t simd8_grf_start
= 0, simd16_grf_start
= 0;
6498 unsigned simd8_grf_used
= 0, simd16_grf_used
= 0;
6500 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
,
6501 &prog_data
->base
, prog
, shader
, 8,
6502 shader_time_index8
);
6503 if (!v8
.run_fs(allow_spilling
, false /* do_rep_send */)) {
6505 *error_str
= ralloc_strdup(mem_ctx
, v8
.fail_msg
);
6508 } else if (likely(!(INTEL_DEBUG
& DEBUG_NO8
))) {
6510 simd8_grf_start
= v8
.payload
.num_regs
;
6511 simd8_grf_used
= v8
.grf_used
;
6514 if (v8
.max_dispatch_width
>= 16 &&
6515 likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
6516 /* Try a SIMD16 compile */
6517 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
,
6518 &prog_data
->base
, prog
, shader
, 16,
6519 shader_time_index16
);
6520 v16
.import_uniforms(&v8
);
6521 if (!v16
.run_fs(allow_spilling
, use_rep_send
)) {
6522 compiler
->shader_perf_log(log_data
,
6523 "SIMD16 shader failed to compile: %s",
6526 simd16_cfg
= v16
.cfg
;
6527 simd16_grf_start
= v16
.payload
.num_regs
;
6528 simd16_grf_used
= v16
.grf_used
;
6532 /* When the caller requests a repclear shader, they want SIMD16-only */
6536 /* Prior to Iron Lake, the PS had a single shader offset with a jump table
6537 * at the top to select the shader. We've never implemented that.
6538 * Instead, we just give them exactly one shader and we pick the widest one
6541 if (compiler
->devinfo
->gen
< 5 && simd16_cfg
)
6544 if (prog_data
->persample_dispatch
) {
6545 /* Starting with SandyBridge (where we first get MSAA), the different
6546 * pixel dispatch combinations are grouped into classifications A
6547 * through F (SNB PRM Vol. 2 Part 1 Section 7.7.1). On all hardware
6548 * generations, the only configurations supporting persample dispatch
6549 * are are this in which only one dispatch width is enabled.
6551 * If computed depth is enabled, SNB only allows SIMD8 while IVB+
6552 * allow SIMD8 or SIMD16 so we choose SIMD16 if available.
6554 if (compiler
->devinfo
->gen
== 6 &&
6555 prog_data
->computed_depth_mode
!= BRW_PSCDEPTH_OFF
) {
6557 } else if (simd16_cfg
) {
6562 /* We have to compute the flat inputs after the visitor is finished running
6563 * because it relies on prog_data->urb_setup which is computed in
6564 * fs_visitor::calculate_urb_setup().
6566 brw_compute_flat_inputs(prog_data
, shader
);
6568 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
6569 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6570 MESA_SHADER_FRAGMENT
);
6572 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
6573 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
6574 shader
->info
.label
? shader
->info
.label
:
6576 shader
->info
.name
));
6580 prog_data
->dispatch_8
= true;
6581 g
.generate_code(simd8_cfg
, 8);
6582 prog_data
->base
.dispatch_grf_start_reg
= simd8_grf_start
;
6583 prog_data
->reg_blocks_0
= brw_register_blocks(simd8_grf_used
);
6586 prog_data
->dispatch_16
= true;
6587 prog_data
->prog_offset_2
= g
.generate_code(simd16_cfg
, 16);
6588 prog_data
->dispatch_grf_start_reg_2
= simd16_grf_start
;
6589 prog_data
->reg_blocks_2
= brw_register_blocks(simd16_grf_used
);
6591 } else if (simd16_cfg
) {
6592 prog_data
->dispatch_16
= true;
6593 g
.generate_code(simd16_cfg
, 16);
6594 prog_data
->base
.dispatch_grf_start_reg
= simd16_grf_start
;
6595 prog_data
->reg_blocks_0
= brw_register_blocks(simd16_grf_used
);
6598 return g
.get_assembly(final_assembly_size
);
6602 fs_visitor::emit_cs_work_group_id_setup()
6604 assert(stage
== MESA_SHADER_COMPUTE
);
6606 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
6608 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
6609 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
6610 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
6612 bld
.MOV(*reg
, r0_1
);
6613 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
6614 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
6620 fill_push_const_block_info(struct brw_push_const_block
*block
, unsigned dwords
)
6622 block
->dwords
= dwords
;
6623 block
->regs
= DIV_ROUND_UP(dwords
, 8);
6624 block
->size
= block
->regs
* 32;
6628 cs_fill_push_const_info(const struct brw_device_info
*devinfo
,
6629 struct brw_cs_prog_data
*cs_prog_data
)
6631 const struct brw_stage_prog_data
*prog_data
=
6632 (struct brw_stage_prog_data
*) cs_prog_data
;
6633 bool fill_thread_id
=
6634 cs_prog_data
->thread_local_id_index
>= 0 &&
6635 cs_prog_data
->thread_local_id_index
< (int)prog_data
->nr_params
;
6636 bool cross_thread_supported
= devinfo
->gen
> 7 || devinfo
->is_haswell
;
6638 /* The thread ID should be stored in the last param dword */
6639 assert(prog_data
->nr_params
> 0 || !fill_thread_id
);
6640 assert(!fill_thread_id
||
6641 cs_prog_data
->thread_local_id_index
==
6642 (int)prog_data
->nr_params
- 1);
6644 unsigned cross_thread_dwords
, per_thread_dwords
;
6645 if (!cross_thread_supported
) {
6646 cross_thread_dwords
= 0u;
6647 per_thread_dwords
= prog_data
->nr_params
;
6648 } else if (fill_thread_id
) {
6649 /* Fill all but the last register with cross-thread payload */
6650 cross_thread_dwords
= 8 * (cs_prog_data
->thread_local_id_index
/ 8);
6651 per_thread_dwords
= prog_data
->nr_params
- cross_thread_dwords
;
6652 assert(per_thread_dwords
> 0 && per_thread_dwords
<= 8);
6654 /* Fill all data using cross-thread payload */
6655 cross_thread_dwords
= prog_data
->nr_params
;
6656 per_thread_dwords
= 0u;
6659 fill_push_const_block_info(&cs_prog_data
->push
.cross_thread
, cross_thread_dwords
);
6660 fill_push_const_block_info(&cs_prog_data
->push
.per_thread
, per_thread_dwords
);
6662 unsigned total_dwords
=
6663 (cs_prog_data
->push
.per_thread
.size
* cs_prog_data
->threads
+
6664 cs_prog_data
->push
.cross_thread
.size
) / 4;
6665 fill_push_const_block_info(&cs_prog_data
->push
.total
, total_dwords
);
6667 assert(cs_prog_data
->push
.cross_thread
.dwords
% 8 == 0 ||
6668 cs_prog_data
->push
.per_thread
.size
== 0);
6669 assert(cs_prog_data
->push
.cross_thread
.dwords
+
6670 cs_prog_data
->push
.per_thread
.dwords
==
6671 prog_data
->nr_params
);
6675 cs_set_simd_size(struct brw_cs_prog_data
*cs_prog_data
, unsigned size
)
6677 cs_prog_data
->simd_size
= size
;
6678 unsigned group_size
= cs_prog_data
->local_size
[0] *
6679 cs_prog_data
->local_size
[1] * cs_prog_data
->local_size
[2];
6680 cs_prog_data
->threads
= (group_size
+ size
- 1) / size
;
6684 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
6686 const struct brw_cs_prog_key
*key
,
6687 struct brw_cs_prog_data
*prog_data
,
6688 const nir_shader
*src_shader
,
6689 int shader_time_index
,
6690 unsigned *final_assembly_size
,
6693 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
6694 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
6696 brw_nir_lower_cs_shared(shader
);
6697 prog_data
->base
.total_shared
+= shader
->num_shared
;
6699 /* Now that we cloned the nir_shader, we can update num_uniforms based on
6700 * the thread_local_id_index.
6702 assert(prog_data
->thread_local_id_index
>= 0);
6703 shader
->num_uniforms
=
6704 MAX2(shader
->num_uniforms
,
6705 (unsigned)4 * (prog_data
->thread_local_id_index
+ 1));
6707 brw_nir_lower_intrinsics(shader
, &prog_data
->base
);
6708 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
6710 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
6711 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
6712 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
6713 unsigned local_workgroup_size
=
6714 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
6715 shader
->info
.cs
.local_size
[2];
6717 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
6718 unsigned simd_required
= DIV_ROUND_UP(local_workgroup_size
, max_cs_threads
);
6721 const char *fail_msg
= NULL
;
6723 /* Now the main event: Visit the shader IR and generate our CS IR for it.
6725 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6726 NULL
, /* Never used in core profile */
6727 shader
, 8, shader_time_index
);
6728 if (simd_required
<= 8) {
6730 fail_msg
= v8
.fail_msg
;
6733 cs_set_simd_size(prog_data
, 8);
6734 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6735 prog_data
->base
.dispatch_grf_start_reg
= v8
.payload
.num_regs
;
6739 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6740 NULL
, /* Never used in core profile */
6741 shader
, 16, shader_time_index
);
6742 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
6743 !fail_msg
&& v8
.max_dispatch_width
>= 16 &&
6744 simd_required
<= 16) {
6745 /* Try a SIMD16 compile */
6746 if (simd_required
<= 8)
6747 v16
.import_uniforms(&v8
);
6748 if (!v16
.run_cs()) {
6749 compiler
->shader_perf_log(log_data
,
6750 "SIMD16 shader failed to compile: %s",
6754 "Couldn't generate SIMD16 program and not "
6755 "enough threads for SIMD8";
6759 cs_set_simd_size(prog_data
, 16);
6760 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6761 prog_data
->dispatch_grf_start_reg_16
= v16
.payload
.num_regs
;
6765 fs_visitor
v32(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
6766 NULL
, /* Never used in core profile */
6767 shader
, 32, shader_time_index
);
6768 if (!fail_msg
&& v8
.max_dispatch_width
>= 32 &&
6769 (simd_required
> 16 || (INTEL_DEBUG
& DEBUG_DO32
))) {
6770 /* Try a SIMD32 compile */
6771 if (simd_required
<= 8)
6772 v32
.import_uniforms(&v8
);
6773 else if (simd_required
<= 16)
6774 v32
.import_uniforms(&v16
);
6776 if (!v32
.run_cs()) {
6777 compiler
->shader_perf_log(log_data
,
6778 "SIMD32 shader failed to compile: %s",
6782 "Couldn't generate SIMD32 program and not "
6783 "enough threads for SIMD16";
6787 cs_set_simd_size(prog_data
, 32);
6788 cs_fill_push_const_info(compiler
->devinfo
, prog_data
);
6792 if (unlikely(cfg
== NULL
)) {
6795 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
6800 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
6801 v8
.promoted_constants
, v8
.runtime_check_aads_emit
,
6802 MESA_SHADER_COMPUTE
);
6803 if (INTEL_DEBUG
& DEBUG_CS
) {
6804 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
6805 shader
->info
.label
? shader
->info
.label
:
6808 g
.enable_debug(name
);
6811 g
.generate_code(cfg
, prog_data
->simd_size
);
6813 return g
.get_assembly(final_assembly_size
);