2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "brw_dead_control_flow.h"
47 #include "main/uniforms.h"
48 #include "brw_fs_live_variables.h"
49 #include "glsl/glsl_types.h"
50 #include "program/sampler.h"
53 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
54 const fs_reg
*src
, unsigned sources
)
56 memset(this, 0, sizeof(*this));
58 this->src
= new fs_reg
[MAX2(sources
, 3)];
59 for (unsigned i
= 0; i
< sources
; i
++)
60 this->src
[i
] = src
[i
];
62 this->opcode
= opcode
;
64 this->sources
= sources
;
65 this->exec_size
= exec_size
;
67 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
69 /* If exec_size == 0, try to guess it from the registers. Since all
70 * manner of things may use hardware registers, we first try to guess
71 * based on GRF registers. If this fails, we will go ahead and take the
72 * width from the destination register.
74 if (this->exec_size
== 0) {
75 if (dst
.file
== GRF
) {
76 this->exec_size
= dst
.width
;
78 for (unsigned i
= 0; i
< sources
; ++i
) {
79 if (src
[i
].file
!= GRF
&& src
[i
].file
!= ATTR
)
82 if (this->exec_size
<= 1)
83 this->exec_size
= src
[i
].width
;
84 assert(src
[i
].width
== 1 || src
[i
].width
== this->exec_size
);
88 if (this->exec_size
== 0 && dst
.file
!= BAD_FILE
)
89 this->exec_size
= dst
.width
;
91 assert(this->exec_size
!= 0);
93 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
95 /* This will be the case for almost all instructions. */
102 DIV_ROUND_UP(MAX2(dst
.width
* dst
.stride
, 1) * type_sz(dst
.type
), 32);
105 this->regs_written
= 0;
109 unreachable("Invalid destination register file");
111 unreachable("Invalid register file");
114 this->writes_accumulator
= false;
119 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
122 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
124 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
127 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
)
129 init(opcode
, 0, dst
, NULL
, 0);
132 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
135 const fs_reg src
[1] = { src0
};
136 init(opcode
, exec_size
, dst
, src
, 1);
139 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
141 const fs_reg src
[1] = { src0
};
142 init(opcode
, 0, dst
, src
, 1);
145 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
146 const fs_reg
&src0
, const fs_reg
&src1
)
148 const fs_reg src
[2] = { src0
, src1
};
149 init(opcode
, exec_size
, dst
, src
, 2);
152 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
155 const fs_reg src
[2] = { src0
, src1
};
156 init(opcode
, 0, dst
, src
, 2);
159 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
160 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
162 const fs_reg src
[3] = { src0
, src1
, src2
};
163 init(opcode
, exec_size
, dst
, src
, 3);
166 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
167 const fs_reg
&src1
, const fs_reg
&src2
)
169 const fs_reg src
[3] = { src0
, src1
, src2
};
170 init(opcode
, 0, dst
, src
, 3);
173 fs_inst::fs_inst(enum opcode opcode
, const fs_reg
&dst
,
174 const fs_reg src
[], unsigned sources
)
176 init(opcode
, 0, dst
, src
, sources
);
179 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
180 const fs_reg src
[], unsigned sources
)
182 init(opcode
, exec_width
, dst
, src
, sources
);
185 fs_inst::fs_inst(const fs_inst
&that
)
187 memcpy(this, &that
, sizeof(that
));
189 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
191 for (unsigned i
= 0; i
< that
.sources
; i
++)
192 this->src
[i
] = that
.src
[i
];
201 fs_inst::resize_sources(uint8_t num_sources
)
203 if (this->sources
!= num_sources
) {
204 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
206 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
207 src
[i
] = this->src
[i
];
211 this->sources
= num_sources
;
217 fs_visitor::op(const fs_reg &dst, const fs_reg &src0) \
219 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0); \
224 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
225 const fs_reg &src1) \
227 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1); \
230 #define ALU2_ACC(op) \
232 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
233 const fs_reg &src1) \
235 fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1);\
236 inst->writes_accumulator = true; \
242 fs_visitor::op(const fs_reg &dst, const fs_reg &src0, \
243 const fs_reg &src1, const fs_reg &src2) \
245 return new(mem_ctx) fs_inst(BRW_OPCODE_##op, dst, src0, src1, src2);\
277 /** Gen4 predicated IF. */
279 fs_visitor::IF(enum brw_predicate predicate
)
281 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
);
282 inst
->predicate
= predicate
;
286 /** Gen6 IF with embedded comparison. */
288 fs_visitor::IF(const fs_reg
&src0
, const fs_reg
&src1
,
289 enum brw_conditional_mod condition
)
291 assert(devinfo
->gen
== 6);
292 fs_inst
*inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_IF
, dispatch_width
,
293 reg_null_d
, src0
, src1
);
294 inst
->conditional_mod
= condition
;
299 * CMP: Sets the low bit of the destination channels with the result
300 * of the comparison, while the upper bits are undefined, and updates
301 * the flag register with the packed 16 bits of the result.
304 fs_visitor::CMP(fs_reg dst
, fs_reg src0
, fs_reg src1
,
305 enum brw_conditional_mod condition
)
309 /* Take the instruction:
311 * CMP null<d> src0<f> src1<f>
313 * Original gen4 does type conversion to the destination type before
314 * comparison, producing garbage results for floating point comparisons.
316 * The destination type doesn't matter on newer generations, so we set the
317 * type to match src0 so we can compact the instruction.
319 dst
.type
= src0
.type
;
320 if (dst
.file
== HW_REG
)
321 dst
.fixed_hw_reg
.type
= dst
.type
;
323 resolve_ud_negate(&src0
);
324 resolve_ud_negate(&src1
);
326 inst
= new(mem_ctx
) fs_inst(BRW_OPCODE_CMP
, dst
, src0
, src1
);
327 inst
->conditional_mod
= condition
;
333 fs_visitor::LOAD_PAYLOAD(const fs_reg
&dst
, fs_reg
*src
, int sources
,
336 assert(dst
.width
% 8 == 0);
337 fs_inst
*inst
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
, dst
.width
,
339 inst
->header_size
= header_size
;
341 for (int i
= 0; i
< header_size
; i
++)
342 assert(src
[i
].file
!= GRF
|| src
[i
].width
* type_sz(src
[i
].type
) == 32);
343 inst
->regs_written
= header_size
;
345 for (int i
= header_size
; i
< sources
; ++i
)
346 assert(src
[i
].file
!= GRF
|| src
[i
].width
== dst
.width
);
347 inst
->regs_written
+= (sources
- header_size
) * (dst
.width
/ 8);
353 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_reg
&dst
,
354 const fs_reg
&surf_index
,
355 const fs_reg
&varying_offset
,
356 uint32_t const_offset
)
358 exec_list instructions
;
361 /* We have our constant surface use a pitch of 4 bytes, so our index can
362 * be any component of a vector, and then we load 4 contiguous
363 * components starting from that.
365 * We break down the const_offset to a portion added to the variable
366 * offset and a portion done using reg_offset, which means that if you
367 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
368 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
369 * CSE can later notice that those loads are all the same and eliminate
370 * the redundant ones.
372 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
373 instructions
.push_tail(ADD(vec4_offset
,
374 varying_offset
, fs_reg(const_offset
& ~3)));
377 if (devinfo
->gen
== 4 && dst
.width
== 8) {
378 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
379 * u, v, r) as parameters, or we can just use the SIMD16 message
380 * consisting of (header, u). We choose the second, at the cost of a
381 * longer return length.
387 if (devinfo
->gen
>= 7)
388 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
390 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
392 assert(dst
.width
% 8 == 0);
393 int regs_written
= 4 * (dst
.width
/ 8) * scale
;
394 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
),
395 dst
.type
, dst
.width
);
396 inst
= new(mem_ctx
) fs_inst(op
, vec4_result
, surf_index
, vec4_offset
);
397 inst
->regs_written
= regs_written
;
398 instructions
.push_tail(inst
);
400 if (devinfo
->gen
< 7) {
402 inst
->header_size
= 1;
403 if (devinfo
->gen
== 4)
406 inst
->mlen
= 1 + dispatch_width
/ 8;
409 fs_reg result
= offset(vec4_result
, (const_offset
& 3) * scale
);
410 instructions
.push_tail(MOV(dst
, result
));
416 * A helper for MOV generation for fixing up broken hardware SEND dependency
420 fs_visitor::DEP_RESOLVE_MOV(int grf
)
422 fs_inst
*inst
= MOV(brw_null_reg(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
425 inst
->annotation
= "send dependency resolve";
427 /* The caller always wants uncompressed to emit the minimal extra
428 * dependencies, and to avoid having to deal with aligning its regs to 2.
436 fs_inst::equals(fs_inst
*inst
) const
438 return (opcode
== inst
->opcode
&&
439 dst
.equals(inst
->dst
) &&
440 src
[0].equals(inst
->src
[0]) &&
441 src
[1].equals(inst
->src
[1]) &&
442 src
[2].equals(inst
->src
[2]) &&
443 saturate
== inst
->saturate
&&
444 predicate
== inst
->predicate
&&
445 conditional_mod
== inst
->conditional_mod
&&
446 mlen
== inst
->mlen
&&
447 base_mrf
== inst
->base_mrf
&&
448 target
== inst
->target
&&
450 header_size
== inst
->header_size
&&
451 shadow_compare
== inst
->shadow_compare
&&
452 exec_size
== inst
->exec_size
&&
453 offset
== inst
->offset
);
457 fs_inst::overwrites_reg(const fs_reg
®
) const
459 return reg
.in_range(dst
, regs_written
);
463 fs_inst::is_send_from_grf() const
466 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
467 case SHADER_OPCODE_SHADER_TIME_ADD
:
468 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
469 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
470 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
471 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
472 case SHADER_OPCODE_UNTYPED_ATOMIC
:
473 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
474 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
475 case SHADER_OPCODE_TYPED_ATOMIC
:
476 case SHADER_OPCODE_TYPED_SURFACE_READ
:
477 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
478 case SHADER_OPCODE_URB_WRITE_SIMD8
:
480 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
481 return src
[1].file
== GRF
;
482 case FS_OPCODE_FB_WRITE
:
483 return src
[0].file
== GRF
;
486 return src
[0].file
== GRF
;
493 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
495 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
498 fs_reg reg
= this->src
[0];
499 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
502 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
505 for (int i
= 0; i
< this->sources
; i
++) {
506 reg
.type
= this->src
[i
].type
;
507 reg
.width
= this->src
[i
].width
;
508 if (!this->src
[i
].equals(reg
))
510 reg
= ::offset(reg
, 1);
517 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
519 if (devinfo
->gen
== 6 && is_math())
522 if (is_send_from_grf())
525 if (!backend_instruction::can_do_source_mods())
532 fs_inst::has_side_effects() const
534 return this->eot
|| backend_instruction::has_side_effects();
540 memset(this, 0, sizeof(*this));
544 /** Generic unset register constructor. */
548 this->file
= BAD_FILE
;
551 /** Immediate value constructor. */
552 fs_reg::fs_reg(float f
)
556 this->type
= BRW_REGISTER_TYPE_F
;
557 this->fixed_hw_reg
.dw1
.f
= f
;
561 /** Immediate value constructor. */
562 fs_reg::fs_reg(int32_t i
)
566 this->type
= BRW_REGISTER_TYPE_D
;
567 this->fixed_hw_reg
.dw1
.d
= i
;
571 /** Immediate value constructor. */
572 fs_reg::fs_reg(uint32_t u
)
576 this->type
= BRW_REGISTER_TYPE_UD
;
577 this->fixed_hw_reg
.dw1
.ud
= u
;
581 /** Vector float immediate value constructor. */
582 fs_reg::fs_reg(uint8_t vf
[4])
586 this->type
= BRW_REGISTER_TYPE_VF
;
587 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
590 /** Vector float immediate value constructor. */
591 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
595 this->type
= BRW_REGISTER_TYPE_VF
;
596 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
602 /** Fixed brw_reg. */
603 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
607 this->fixed_hw_reg
= fixed_hw_reg
;
608 this->type
= fixed_hw_reg
.type
;
609 this->width
= 1 << fixed_hw_reg
.width
;
613 fs_reg::equals(const fs_reg
&r
) const
615 return (file
== r
.file
&&
617 reg_offset
== r
.reg_offset
&&
618 subreg_offset
== r
.subreg_offset
&&
620 negate
== r
.negate
&&
622 !reladdr
&& !r
.reladdr
&&
623 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
, sizeof(fixed_hw_reg
)) == 0 &&
629 fs_reg::set_smear(unsigned subreg
)
631 assert(file
!= HW_REG
&& file
!= IMM
);
632 subreg_offset
= subreg
* type_sz(type
);
638 fs_reg::is_contiguous() const
644 fs_visitor::type_size(const struct glsl_type
*type
)
646 unsigned int size
, i
;
648 switch (type
->base_type
) {
651 case GLSL_TYPE_FLOAT
:
653 return type
->components();
654 case GLSL_TYPE_ARRAY
:
655 return type_size(type
->fields
.array
) * type
->length
;
656 case GLSL_TYPE_STRUCT
:
658 for (i
= 0; i
< type
->length
; i
++) {
659 size
+= type_size(type
->fields
.structure
[i
].type
);
662 case GLSL_TYPE_SAMPLER
:
663 /* Samplers take up no register space, since they're baked in at
667 case GLSL_TYPE_ATOMIC_UINT
:
669 case GLSL_TYPE_IMAGE
:
671 case GLSL_TYPE_ERROR
:
672 case GLSL_TYPE_INTERFACE
:
673 case GLSL_TYPE_DOUBLE
:
674 case GLSL_TYPE_FUNCTION
:
675 unreachable("not reached");
682 * Create a MOV to read the timestamp register.
684 * The caller is responsible for emitting the MOV. The return value is
685 * the destination of the MOV, with extra parameters set.
688 fs_visitor::get_timestamp(fs_inst
**out_mov
)
690 assert(devinfo
->gen
>= 7);
692 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
695 BRW_REGISTER_TYPE_UD
));
697 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 4);
699 fs_inst
*mov
= MOV(dst
, ts
);
700 /* We want to read the 3 fields we care about even if it's not enabled in
703 mov
->force_writemask_all
= true;
705 /* The caller wants the low 32 bits of the timestamp. Since it's running
706 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
707 * which is plenty of time for our purposes. It is identical across the
708 * EUs, but since it's tracking GPU core speed it will increment at a
709 * varying rate as render P-states change.
711 * The caller could also check if render P-states have changed (or anything
712 * else that might disrupt timing) by setting smear to 2 and checking if
713 * that field is != 0.
722 fs_visitor::emit_shader_time_begin()
724 current_annotation
= "shader time start";
726 shader_start_time
= get_timestamp(&mov
);
731 fs_visitor::emit_shader_time_end()
733 current_annotation
= "shader time end";
735 enum shader_time_shader_type type
, written_type
, reset_type
;
737 case MESA_SHADER_VERTEX
:
739 written_type
= ST_VS_WRITTEN
;
740 reset_type
= ST_VS_RESET
;
742 case MESA_SHADER_GEOMETRY
:
744 written_type
= ST_GS_WRITTEN
;
745 reset_type
= ST_GS_RESET
;
747 case MESA_SHADER_FRAGMENT
:
748 if (dispatch_width
== 8) {
750 written_type
= ST_FS8_WRITTEN
;
751 reset_type
= ST_FS8_RESET
;
753 assert(dispatch_width
== 16);
755 written_type
= ST_FS16_WRITTEN
;
756 reset_type
= ST_FS16_RESET
;
759 case MESA_SHADER_COMPUTE
:
761 written_type
= ST_CS_WRITTEN
;
762 reset_type
= ST_CS_RESET
;
765 unreachable("fs_visitor::emit_shader_time_end missing code");
768 /* Insert our code just before the final SEND with EOT. */
769 exec_node
*end
= this->instructions
.get_tail();
770 assert(end
&& ((fs_inst
*) end
)->eot
);
773 fs_reg shader_end_time
= get_timestamp(&tm_read
);
774 end
->insert_before(tm_read
);
776 /* Check that there weren't any timestamp reset events (assuming these
777 * were the only two timestamp reads that happened).
779 fs_reg reset
= shader_end_time
;
781 fs_inst
*test
= AND(reg_null_d
, reset
, fs_reg(1u));
782 test
->conditional_mod
= BRW_CONDITIONAL_Z
;
783 test
->force_writemask_all
= true;
784 end
->insert_before(test
);
785 end
->insert_before(IF(BRW_PREDICATE_NORMAL
));
787 fs_reg start
= shader_start_time
;
789 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
, 1);
791 fs_inst
*add
= ADD(diff
, start
, shader_end_time
);
792 add
->force_writemask_all
= true;
793 end
->insert_before(add
);
795 /* If there were no instructions between the two timestamp gets, the diff
796 * is 2 cycles. Remove that overhead, so I can forget about that when
797 * trying to determine the time taken for single instructions.
799 add
= ADD(diff
, diff
, fs_reg(-2u));
800 add
->force_writemask_all
= true;
801 end
->insert_before(add
);
803 end
->insert_before(SHADER_TIME_ADD(type
, diff
));
804 end
->insert_before(SHADER_TIME_ADD(written_type
, fs_reg(1u)));
805 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ELSE
, dispatch_width
));
806 end
->insert_before(SHADER_TIME_ADD(reset_type
, fs_reg(1u)));
807 end
->insert_before(new(mem_ctx
) fs_inst(BRW_OPCODE_ENDIF
, dispatch_width
));
811 fs_visitor::SHADER_TIME_ADD(enum shader_time_shader_type type
, fs_reg value
)
813 int shader_time_index
=
814 brw_get_shader_time_index(brw
, shader_prog
, prog
, type
);
815 fs_reg offset
= fs_reg(shader_time_index
* SHADER_TIME_STRIDE
);
818 if (dispatch_width
== 8)
819 payload
= vgrf(glsl_type::uvec2_type
);
821 payload
= vgrf(glsl_type::uint_type
);
823 return new(mem_ctx
) fs_inst(SHADER_OPCODE_SHADER_TIME_ADD
,
824 fs_reg(), payload
, offset
, value
);
828 fs_visitor::vfail(const char *format
, va_list va
)
837 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
838 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
840 this->fail_msg
= msg
;
843 fprintf(stderr
, "%s", msg
);
848 fs_visitor::fail(const char *format
, ...)
852 va_start(va
, format
);
858 * Mark this program as impossible to compile in SIMD16 mode.
860 * During the SIMD8 compile (which happens first), we can detect and flag
861 * things that are unsupported in SIMD16 mode, so the compiler can skip
862 * the SIMD16 compile altogether.
864 * During a SIMD16 compile (if one happens anyway), this just calls fail().
867 fs_visitor::no16(const char *format
, ...)
871 va_start(va
, format
);
873 if (dispatch_width
== 16) {
876 simd16_unsupported
= true;
878 if (brw
->perf_debug
) {
880 ralloc_vasprintf_append(&no16_msg
, format
, va
);
882 no16_msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
890 fs_visitor::emit(enum opcode opcode
)
892 return emit(new(mem_ctx
) fs_inst(opcode
, dispatch_width
));
896 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
)
898 return emit(new(mem_ctx
) fs_inst(opcode
, dst
));
902 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
)
904 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
));
908 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
911 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
));
915 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
, const fs_reg
&src0
,
916 const fs_reg
&src1
, const fs_reg
&src2
)
918 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src0
, src1
, src2
));
922 fs_visitor::emit(enum opcode opcode
, const fs_reg
&dst
,
923 fs_reg src
[], int sources
)
925 return emit(new(mem_ctx
) fs_inst(opcode
, dst
, src
, sources
));
929 * Returns true if the instruction has a flag that means it won't
930 * update an entire destination register.
932 * For example, dead code elimination and live variable analysis want to know
933 * when a write to a variable screens off any preceding values that were in
937 fs_inst::is_partial_write() const
939 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
940 (this->dst
.width
* type_sz(this->dst
.type
)) < 32 ||
941 !this->dst
.is_contiguous());
945 fs_inst::regs_read(int arg
) const
947 if (is_tex() && arg
== 0 && src
[0].file
== GRF
) {
949 } else if (opcode
== FS_OPCODE_FB_WRITE
&& arg
== 0) {
951 } else if (opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
&& arg
== 0) {
953 } else if (opcode
== SHADER_OPCODE_UNTYPED_ATOMIC
&& arg
== 0) {
955 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_READ
&& arg
== 0) {
957 } else if (opcode
== SHADER_OPCODE_UNTYPED_SURFACE_WRITE
&& arg
== 0) {
959 } else if (opcode
== SHADER_OPCODE_TYPED_ATOMIC
&& arg
== 0) {
961 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_READ
&& arg
== 0) {
963 } else if (opcode
== SHADER_OPCODE_TYPED_SURFACE_WRITE
&& arg
== 0) {
965 } else if (opcode
== FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
&& arg
== 0) {
967 } else if (opcode
== FS_OPCODE_LINTERP
&& arg
== 0) {
968 return exec_size
/ 4;
971 switch (src
[arg
].file
) {
978 if (src
[arg
].stride
== 0) {
981 int size
= src
[arg
].width
* src
[arg
].stride
* type_sz(src
[arg
].type
);
982 return (size
+ 31) / 32;
985 unreachable("MRF registers are not allowed as sources");
987 unreachable("Invalid register file");
992 fs_inst::reads_flag() const
998 fs_inst::writes_flag() const
1000 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
1001 opcode
!= BRW_OPCODE_IF
&&
1002 opcode
!= BRW_OPCODE_WHILE
)) ||
1003 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
1007 * Returns how many MRFs an FS opcode will write over.
1009 * Note that this is not the 0 or 1 implied writes in an actual gen
1010 * instruction -- the FS opcodes often generate MOVs in addition.
1013 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
1015 if (inst
->mlen
== 0)
1018 if (inst
->base_mrf
== -1)
1021 switch (inst
->opcode
) {
1022 case SHADER_OPCODE_RCP
:
1023 case SHADER_OPCODE_RSQ
:
1024 case SHADER_OPCODE_SQRT
:
1025 case SHADER_OPCODE_EXP2
:
1026 case SHADER_OPCODE_LOG2
:
1027 case SHADER_OPCODE_SIN
:
1028 case SHADER_OPCODE_COS
:
1029 return 1 * dispatch_width
/ 8;
1030 case SHADER_OPCODE_POW
:
1031 case SHADER_OPCODE_INT_QUOTIENT
:
1032 case SHADER_OPCODE_INT_REMAINDER
:
1033 return 2 * dispatch_width
/ 8;
1034 case SHADER_OPCODE_TEX
:
1036 case SHADER_OPCODE_TXD
:
1037 case SHADER_OPCODE_TXF
:
1038 case SHADER_OPCODE_TXF_CMS
:
1039 case SHADER_OPCODE_TXF_MCS
:
1040 case SHADER_OPCODE_TG4
:
1041 case SHADER_OPCODE_TG4_OFFSET
:
1042 case SHADER_OPCODE_TXL
:
1043 case SHADER_OPCODE_TXS
:
1044 case SHADER_OPCODE_LOD
:
1046 case FS_OPCODE_FB_WRITE
:
1048 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
1049 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
1051 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
1053 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
1055 case SHADER_OPCODE_UNTYPED_ATOMIC
:
1056 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
1057 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
1058 case SHADER_OPCODE_TYPED_ATOMIC
:
1059 case SHADER_OPCODE_TYPED_SURFACE_READ
:
1060 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
1061 case SHADER_OPCODE_URB_WRITE_SIMD8
:
1062 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
1063 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
1064 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
1065 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
1068 unreachable("not reached");
1073 fs_visitor::vgrf(const glsl_type
*const type
)
1075 int reg_width
= dispatch_width
/ 8;
1076 return fs_reg(GRF
, alloc
.allocate(type_size(type
) * reg_width
),
1077 brw_type_for_base_type(type
), dispatch_width
);
1081 fs_visitor::vgrf(int num_components
)
1083 int reg_width
= dispatch_width
/ 8;
1084 return fs_reg(GRF
, alloc
.allocate(num_components
* reg_width
),
1085 BRW_REGISTER_TYPE_F
, dispatch_width
);
1088 /** Fixed HW reg constructor. */
1089 fs_reg::fs_reg(enum register_file file
, int reg
)
1094 this->type
= BRW_REGISTER_TYPE_F
;
1105 /** Fixed HW reg constructor. */
1106 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
1122 /** Fixed HW reg constructor. */
1123 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
,
1130 this->width
= width
;
1134 fs_visitor::variable_storage(ir_variable
*var
)
1136 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
1140 import_uniforms_callback(const void *key
,
1144 struct hash_table
*dst_ht
= (struct hash_table
*)closure
;
1145 const fs_reg
*reg
= (const fs_reg
*)data
;
1147 if (reg
->file
!= UNIFORM
)
1150 hash_table_insert(dst_ht
, data
, key
);
1153 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1154 * This brings in those uniform definitions
1157 fs_visitor::import_uniforms(fs_visitor
*v
)
1159 hash_table_call_foreach(v
->variable_ht
,
1160 import_uniforms_callback
,
1162 this->push_constant_loc
= v
->push_constant_loc
;
1163 this->pull_constant_loc
= v
->pull_constant_loc
;
1164 this->uniforms
= v
->uniforms
;
1165 this->param_size
= v
->param_size
;
1168 /* Our support for uniforms is piggy-backed on the struct
1169 * gl_fragment_program, because that's where the values actually
1170 * get stored, rather than in some global gl_shader_program uniform
1174 fs_visitor::setup_uniform_values(ir_variable
*ir
)
1176 int namelen
= strlen(ir
->name
);
1178 /* The data for our (non-builtin) uniforms is stored in a series of
1179 * gl_uniform_driver_storage structs for each subcomponent that
1180 * glGetUniformLocation() could name. We know it's been set up in the same
1181 * order we'd walk the type, so walk the list of storage and find anything
1182 * with our name, or the prefix of a component that starts with our name.
1184 unsigned params_before
= uniforms
;
1185 for (unsigned u
= 0; u
< shader_prog
->NumUserUniformStorage
; u
++) {
1186 struct gl_uniform_storage
*storage
= &shader_prog
->UniformStorage
[u
];
1188 if (strncmp(ir
->name
, storage
->name
, namelen
) != 0 ||
1189 (storage
->name
[namelen
] != 0 &&
1190 storage
->name
[namelen
] != '.' &&
1191 storage
->name
[namelen
] != '[')) {
1195 unsigned slots
= storage
->type
->component_slots();
1196 if (storage
->array_elements
)
1197 slots
*= storage
->array_elements
;
1199 for (unsigned i
= 0; i
< slots
; i
++) {
1200 stage_prog_data
->param
[uniforms
++] = &storage
->storage
[i
];
1204 /* Make sure we actually initialized the right amount of stuff here. */
1205 assert(params_before
+ ir
->type
->component_slots() == uniforms
);
1206 (void)params_before
;
1210 /* Our support for builtin uniforms is even scarier than non-builtin.
1211 * It sits on top of the PROG_STATE_VAR parameters that are
1212 * automatically updated from GL context state.
1215 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
1217 const ir_state_slot
*const slots
= ir
->get_state_slots();
1218 assert(slots
!= NULL
);
1220 for (unsigned int i
= 0; i
< ir
->get_num_state_slots(); i
++) {
1221 /* This state reference has already been setup by ir_to_mesa, but we'll
1222 * get the same index back here.
1224 int index
= _mesa_add_state_reference(this->prog
->Parameters
,
1225 (gl_state_index
*)slots
[i
].tokens
);
1227 /* Add each of the unique swizzles of the element as a parameter.
1228 * This'll end up matching the expected layout of the
1229 * array/matrix/structure we're trying to fill in.
1232 for (unsigned int j
= 0; j
< 4; j
++) {
1233 int swiz
= GET_SWZ(slots
[i
].swizzle
, j
);
1234 if (swiz
== last_swiz
)
1238 stage_prog_data
->param
[uniforms
++] =
1239 &prog
->Parameters
->ParameterValues
[index
][swiz
];
1245 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1246 bool origin_upper_left
)
1248 assert(stage
== MESA_SHADER_FRAGMENT
);
1249 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1250 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1252 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1254 /* gl_FragCoord.x */
1255 if (pixel_center_integer
) {
1256 emit(MOV(wpos
, this->pixel_x
));
1258 emit(ADD(wpos
, this->pixel_x
, fs_reg(0.5f
)));
1260 wpos
= offset(wpos
, 1);
1262 /* gl_FragCoord.y */
1263 if (!flip
&& pixel_center_integer
) {
1264 emit(MOV(wpos
, this->pixel_y
));
1266 fs_reg pixel_y
= this->pixel_y
;
1267 float offset
= (pixel_center_integer
? 0.0 : 0.5);
1270 pixel_y
.negate
= true;
1271 offset
+= key
->drawable_height
- 1.0;
1274 emit(ADD(wpos
, pixel_y
, fs_reg(offset
)));
1276 wpos
= offset(wpos
, 1);
1278 /* gl_FragCoord.z */
1279 if (devinfo
->gen
>= 6) {
1280 emit(MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0))));
1282 emit(FS_OPCODE_LINTERP
, wpos
,
1283 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1284 interp_reg(VARYING_SLOT_POS
, 2));
1286 wpos
= offset(wpos
, 1);
1288 /* gl_FragCoord.w: Already set up in emit_interpolation */
1289 emit(BRW_OPCODE_MOV
, wpos
, this->wpos_w
);
1295 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1296 glsl_interp_qualifier interpolation_mode
,
1297 bool is_centroid
, bool is_sample
)
1299 brw_wm_barycentric_interp_mode barycoord_mode
;
1300 if (devinfo
->gen
>= 6) {
1302 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1303 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1305 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1306 } else if (is_sample
) {
1307 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1308 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1310 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1312 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1313 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1315 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1318 /* On Ironlake and below, there is only one interpolation mode.
1319 * Centroid interpolation doesn't mean anything on this hardware --
1320 * there is no multisampling.
1322 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1324 return emit(FS_OPCODE_LINTERP
, attr
,
1325 this->delta_xy
[barycoord_mode
], interp
);
1329 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1330 const glsl_type
*type
,
1331 glsl_interp_qualifier interpolation_mode
,
1332 int location
, bool mod_centroid
,
1335 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1337 assert(stage
== MESA_SHADER_FRAGMENT
);
1338 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1339 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1341 unsigned int array_elements
;
1343 if (type
->is_array()) {
1344 array_elements
= type
->length
;
1345 if (array_elements
== 0) {
1346 fail("dereferenced array '%s' has length 0\n", name
);
1348 type
= type
->fields
.array
;
1353 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1355 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1356 if (key
->flat_shade
&& is_gl_Color
) {
1357 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1359 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1363 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1364 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1365 if (prog_data
->urb_setup
[location
] == -1) {
1366 /* If there's no incoming setup data for this slot, don't
1367 * emit interpolation for it.
1369 attr
= offset(attr
, type
->vector_elements
);
1374 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1375 /* Constant interpolation (flat shading) case. The SF has
1376 * handed us defined values in only the constant offset
1377 * field of the setup reg.
1379 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1380 struct brw_reg interp
= interp_reg(location
, k
);
1381 interp
= suboffset(interp
, 3);
1382 interp
.type
= attr
.type
;
1383 emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1384 attr
= offset(attr
, 1);
1387 /* Smooth/noperspective interpolation case. */
1388 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1389 struct brw_reg interp
= interp_reg(location
, k
);
1390 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1391 /* Get the pixel/sample mask into f0 so that we know
1392 * which pixels are lit. Then, for each channel that is
1393 * unlit, replace the centroid data with non-centroid
1396 emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1399 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1401 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1402 inst
->predicate_inverse
= true;
1403 if (devinfo
->has_pln
)
1404 inst
->no_dd_clear
= true;
1406 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1407 mod_centroid
&& !key
->persample_shading
,
1408 mod_sample
|| key
->persample_shading
);
1409 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1410 inst
->predicate_inverse
= false;
1411 if (devinfo
->has_pln
)
1412 inst
->no_dd_check
= true;
1415 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1416 mod_centroid
&& !key
->persample_shading
,
1417 mod_sample
|| key
->persample_shading
);
1419 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1420 emit(BRW_OPCODE_MUL
, attr
, attr
, this->pixel_w
);
1422 attr
= offset(attr
, 1);
1432 fs_visitor::emit_frontfacing_interpolation()
1434 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1436 if (devinfo
->gen
>= 6) {
1437 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1438 * a boolean result from this (~0/true or 0/false).
1440 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1441 * this task in only one instruction:
1442 * - a negation source modifier will flip the bit; and
1443 * - a W -> D type conversion will sign extend the bit into the high
1444 * word of the destination.
1446 * An ASR 15 fills the low word of the destination.
1448 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1451 emit(ASR(*reg
, g0
, fs_reg(15)));
1453 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1454 * a boolean result from this (1/true or 0/false).
1456 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1457 * the negation source modifier to flip it. Unfortunately the SHR
1458 * instruction only operates on UD (or D with an abs source modifier)
1459 * sources without negation.
1461 * Instead, use ASR (which will give ~0/true or 0/false).
1463 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1466 emit(ASR(*reg
, g1_6
, fs_reg(31)));
1473 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1475 assert(stage
== MESA_SHADER_FRAGMENT
);
1476 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1477 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1479 if (key
->compute_pos_offset
) {
1480 /* Convert int_sample_pos to floating point */
1481 emit(MOV(dst
, int_sample_pos
));
1482 /* Scale to the range [0, 1] */
1483 emit(MUL(dst
, dst
, fs_reg(1 / 16.0f
)));
1486 /* From ARB_sample_shading specification:
1487 * "When rendering to a non-multisample buffer, or if multisample
1488 * rasterization is disabled, gl_SamplePosition will always be
1491 emit(MOV(dst
, fs_reg(0.5f
)));
1496 fs_visitor::emit_samplepos_setup()
1498 assert(devinfo
->gen
>= 6);
1500 this->current_annotation
= "compute sample position";
1501 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1503 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1504 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1506 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1507 * mode will be enabled.
1509 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1510 * R31.1:0 Position Offset X/Y for Slot[3:0]
1511 * R31.3:2 Position Offset X/Y for Slot[7:4]
1514 * The X, Y sample positions come in as bytes in thread payload. So, read
1515 * the positions using vstride=16, width=8, hstride=2.
1517 struct brw_reg sample_pos_reg
=
1518 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1519 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1521 if (dispatch_width
== 8) {
1522 emit(MOV(int_sample_x
, fs_reg(sample_pos_reg
)));
1524 emit(MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
)));
1525 emit(MOV(half(int_sample_x
, 1), fs_reg(suboffset(sample_pos_reg
, 16))))
1526 ->force_sechalf
= true;
1528 /* Compute gl_SamplePosition.x */
1529 compute_sample_position(pos
, int_sample_x
);
1530 pos
= offset(pos
, 1);
1531 if (dispatch_width
== 8) {
1532 emit(MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1))));
1534 emit(MOV(half(int_sample_y
, 0),
1535 fs_reg(suboffset(sample_pos_reg
, 1))));
1536 emit(MOV(half(int_sample_y
, 1), fs_reg(suboffset(sample_pos_reg
, 17))))
1537 ->force_sechalf
= true;
1539 /* Compute gl_SamplePosition.y */
1540 compute_sample_position(pos
, int_sample_y
);
1545 fs_visitor::emit_sampleid_setup()
1547 assert(stage
== MESA_SHADER_FRAGMENT
);
1548 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1549 assert(devinfo
->gen
>= 6);
1551 this->current_annotation
= "compute sample id";
1552 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1554 if (key
->compute_sample_id
) {
1555 fs_reg t1
= vgrf(glsl_type::int_type
);
1556 fs_reg t2
= vgrf(glsl_type::int_type
);
1557 t2
.type
= BRW_REGISTER_TYPE_UW
;
1559 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1560 * 8x multisampling, subspan 0 will represent sample N (where N
1561 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1562 * 7. We can find the value of N by looking at R0.0 bits 7:6
1563 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1564 * (since samples are always delivered in pairs). That is, we
1565 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1566 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1567 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1568 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1569 * populating a temporary variable with the sequence (0, 1, 2, 3),
1570 * and then reading from it using vstride=1, width=4, hstride=0.
1571 * These computations hold good for 4x multisampling as well.
1573 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1574 * the first four slots are sample 0 of subspan 0; the next four
1575 * are sample 1 of subspan 0; the third group is sample 0 of
1576 * subspan 1, and finally sample 1 of subspan 1.
1579 inst
= emit(BRW_OPCODE_AND
, t1
,
1580 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1582 inst
->force_writemask_all
= true;
1583 inst
= emit(BRW_OPCODE_SHR
, t1
, t1
, fs_reg(5));
1584 inst
->force_writemask_all
= true;
1585 /* This works for both SIMD8 and SIMD16 */
1586 inst
= emit(MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210)));
1587 inst
->force_writemask_all
= true;
1588 /* This special instruction takes care of setting vstride=1,
1589 * width=4, hstride=0 of t2 during an ADD instruction.
1591 emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1593 /* As per GL_ARB_sample_shading specification:
1594 * "When rendering to a non-multisample buffer, or if multisample
1595 * rasterization is disabled, gl_SampleID will always be zero."
1597 emit(BRW_OPCODE_MOV
, *reg
, fs_reg(0));
1604 fs_visitor::resolve_source_modifiers(fs_reg
*src
)
1606 if (!src
->abs
&& !src
->negate
)
1609 fs_reg temp
= retype(vgrf(1), src
->type
);
1610 emit(MOV(temp
, *src
));
1615 fs_visitor::fix_math_operand(fs_reg src
)
1617 /* Can't do hstride == 0 args on gen6 math, so expand it out. We
1618 * might be able to do better by doing execsize = 1 math and then
1619 * expanding that result out, but we would need to be careful with
1622 * The hardware ignores source modifiers (negate and abs) on math
1623 * instructions, so we also move to a temp to set those up.
1625 if (devinfo
->gen
== 6 && src
.file
!= UNIFORM
&& src
.file
!= IMM
&&
1626 !src
.abs
&& !src
.negate
)
1629 /* Gen7 relaxes most of the above restrictions, but still can't use IMM
1632 if (devinfo
->gen
>= 7 && src
.file
!= IMM
)
1635 fs_reg expanded
= vgrf(glsl_type::float_type
);
1636 expanded
.type
= src
.type
;
1637 emit(BRW_OPCODE_MOV
, expanded
, src
);
1642 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src
)
1645 case SHADER_OPCODE_RCP
:
1646 case SHADER_OPCODE_RSQ
:
1647 case SHADER_OPCODE_SQRT
:
1648 case SHADER_OPCODE_EXP2
:
1649 case SHADER_OPCODE_LOG2
:
1650 case SHADER_OPCODE_SIN
:
1651 case SHADER_OPCODE_COS
:
1654 unreachable("not reached: bad math opcode");
1657 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
1658 * might be able to do better by doing execsize = 1 math and then
1659 * expanding that result out, but we would need to be careful with
1662 * Gen 6 hardware ignores source modifiers (negate and abs) on math
1663 * instructions, so we also move to a temp to set those up.
1665 if (devinfo
->gen
== 6 || devinfo
->gen
== 7)
1666 src
= fix_math_operand(src
);
1668 fs_inst
*inst
= emit(opcode
, dst
, src
);
1670 if (devinfo
->gen
< 6) {
1672 inst
->mlen
= dispatch_width
/ 8;
1679 fs_visitor::emit_math(enum opcode opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
1684 if (devinfo
->gen
>= 8) {
1685 inst
= emit(opcode
, dst
, src0
, src1
);
1686 } else if (devinfo
->gen
>= 6) {
1687 src0
= fix_math_operand(src0
);
1688 src1
= fix_math_operand(src1
);
1690 inst
= emit(opcode
, dst
, src0
, src1
);
1692 /* From the Ironlake PRM, Volume 4, Part 1, Section 6.1.13
1693 * "Message Payload":
1695 * "Operand0[7]. For the INT DIV functions, this operand is the
1698 * "Operand1[7]. For the INT DIV functions, this operand is the
1701 bool is_int_div
= opcode
!= SHADER_OPCODE_POW
;
1702 fs_reg
&op0
= is_int_div
? src1
: src0
;
1703 fs_reg
&op1
= is_int_div
? src0
: src1
;
1705 emit(MOV(fs_reg(MRF
, base_mrf
+ 1, op1
.type
, dispatch_width
), op1
));
1706 inst
= emit(opcode
, dst
, op0
, reg_null_f
);
1708 inst
->base_mrf
= base_mrf
;
1709 inst
->mlen
= 2 * dispatch_width
/ 8;
1715 fs_visitor::emit_discard_jump()
1717 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1719 /* For performance, after a discard, jump to the end of the
1720 * shader if all relevant channels have been discarded.
1722 fs_inst
*discard_jump
= emit(FS_OPCODE_DISCARD_JUMP
);
1723 discard_jump
->flag_subreg
= 1;
1725 discard_jump
->predicate
= (dispatch_width
== 8)
1726 ? BRW_PREDICATE_ALIGN1_ANY8H
1727 : BRW_PREDICATE_ALIGN1_ANY16H
;
1728 discard_jump
->predicate_inverse
= true;
1732 fs_visitor::assign_curb_setup()
1734 if (dispatch_width
== 8) {
1735 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1737 if (stage
== MESA_SHADER_FRAGMENT
) {
1738 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1739 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1740 } else if (stage
== MESA_SHADER_COMPUTE
) {
1741 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1742 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1744 unreachable("Unsupported shader type!");
1748 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1750 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1751 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1752 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1753 if (inst
->src
[i
].file
== UNIFORM
) {
1754 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1756 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1757 constant_nr
= push_constant_loc
[uniform_nr
];
1759 /* Section 5.11 of the OpenGL 4.1 spec says:
1760 * "Out-of-bounds reads return undefined values, which include
1761 * values from other variables of the active program or zero."
1762 * Just return the first push constant.
1767 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1771 inst
->src
[i
].file
= HW_REG
;
1772 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1773 retype(brw_reg
, inst
->src
[i
].type
),
1774 inst
->src
[i
].subreg_offset
);
1781 fs_visitor::calculate_urb_setup()
1783 assert(stage
== MESA_SHADER_FRAGMENT
);
1784 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1785 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1787 memset(prog_data
->urb_setup
, -1,
1788 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1791 /* Figure out where each of the incoming setup attributes lands. */
1792 if (devinfo
->gen
>= 6) {
1793 if (_mesa_bitcount_64(prog
->InputsRead
&
1794 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1795 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1796 * first 16 varying inputs, so we can put them wherever we want.
1797 * Just put them in order.
1799 * This is useful because it means that (a) inputs not used by the
1800 * fragment shader won't take up valuable register space, and (b) we
1801 * won't have to recompile the fragment shader if it gets paired with
1802 * a different vertex (or geometry) shader.
1804 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1805 if (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1806 BITFIELD64_BIT(i
)) {
1807 prog_data
->urb_setup
[i
] = urb_next
++;
1811 /* We have enough input varyings that the SF/SBE pipeline stage can't
1812 * arbitrarily rearrange them to suit our whim; we have to put them
1813 * in an order that matches the output of the previous pipeline stage
1814 * (geometry or vertex shader).
1816 struct brw_vue_map prev_stage_vue_map
;
1817 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1818 key
->input_slots_valid
);
1819 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1820 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1821 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1823 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1824 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1827 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1828 (prog
->InputsRead
& BRW_FS_VARYING_INPUT_MASK
&
1829 BITFIELD64_BIT(varying
))) {
1830 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1833 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1836 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1837 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1838 /* Point size is packed into the header, not as a general attribute */
1839 if (i
== VARYING_SLOT_PSIZ
)
1842 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1843 /* The back color slot is skipped when the front color is
1844 * also written to. In addition, some slots can be
1845 * written in the vertex shader and not read in the
1846 * fragment shader. So the register number must always be
1847 * incremented, mapped or not.
1849 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1850 prog_data
->urb_setup
[i
] = urb_next
;
1856 * It's a FS only attribute, and we did interpolation for this attribute
1857 * in SF thread. So, count it here, too.
1859 * See compile_sf_prog() for more info.
1861 if (prog
->InputsRead
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1862 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1865 prog_data
->num_varying_inputs
= urb_next
;
1869 fs_visitor::assign_urb_setup()
1871 assert(stage
== MESA_SHADER_FRAGMENT
);
1872 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1874 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1876 /* Offset all the urb_setup[] index by the actual position of the
1877 * setup regs, now that the location of the constants has been chosen.
1879 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1880 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1881 assert(inst
->src
[1].file
== HW_REG
);
1882 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1885 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1886 assert(inst
->src
[0].file
== HW_REG
);
1887 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1891 /* Each attribute is 4 setup channels, each of which is half a reg. */
1892 this->first_non_payload_grf
=
1893 urb_start
+ prog_data
->num_varying_inputs
* 2;
1897 fs_visitor::assign_vs_urb_setup()
1899 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1900 int grf
, count
, slot
, channel
, attr
;
1902 assert(stage
== MESA_SHADER_VERTEX
);
1903 count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1904 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1907 /* Each attribute is 4 regs. */
1908 this->first_non_payload_grf
=
1909 payload
.num_regs
+ prog_data
->curb_read_length
+ count
* 4;
1911 unsigned vue_entries
=
1912 MAX2(count
, vs_prog_data
->base
.vue_map
.num_slots
);
1914 /* URB entry size is counted in units of 64 bytes (for the 3DSTATE_URB_VS
1915 * command). Each attribute is 16 bytes (4 floats/dwords), so each unit
1916 * fits four attributes.
1918 vs_prog_data
->base
.urb_entry_size
= ALIGN(vue_entries
, 4) / 4;
1919 vs_prog_data
->base
.urb_read_length
= (count
+ 1) / 2;
1921 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1923 /* Rewrite all ATTR file references to the hw grf that they land in. */
1924 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1925 for (int i
= 0; i
< inst
->sources
; i
++) {
1926 if (inst
->src
[i
].file
== ATTR
) {
1928 if (inst
->src
[i
].reg
== VERT_ATTRIB_MAX
) {
1931 /* Attributes come in in a contiguous block, ordered by their
1932 * gl_vert_attrib value. That means we can compute the slot
1933 * number for an attribute by masking out the enabled
1934 * attributes before it and counting the bits.
1936 attr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
/ 4;
1937 slot
= _mesa_bitcount_64(vs_prog_data
->inputs_read
&
1938 BITFIELD64_MASK(attr
));
1941 channel
= inst
->src
[i
].reg_offset
& 3;
1943 grf
= payload
.num_regs
+
1944 prog_data
->curb_read_length
+
1947 inst
->src
[i
].file
= HW_REG
;
1948 inst
->src
[i
].fixed_hw_reg
=
1949 retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
);
1956 * Split large virtual GRFs into separate components if we can.
1958 * This is mostly duplicated with what brw_fs_vector_splitting does,
1959 * but that's really conservative because it's afraid of doing
1960 * splitting that doesn't result in real progress after the rest of
1961 * the optimization phases, which would cause infinite looping in
1962 * optimization. We can do it once here, safely. This also has the
1963 * opportunity to split interpolated values, or maybe even uniforms,
1964 * which we don't have at the IR level.
1966 * We want to split, because virtual GRFs are what we register
1967 * allocate and spill (due to contiguousness requirements for some
1968 * instructions), and they're what we naturally generate in the
1969 * codegen process, but most virtual GRFs don't actually need to be
1970 * contiguous sets of GRFs. If we split, we'll end up with reduced
1971 * live intervals and better dead code elimination and coalescing.
1974 fs_visitor::split_virtual_grfs()
1976 int num_vars
= this->alloc
.count
;
1978 /* Count the total number of registers */
1980 int vgrf_to_reg
[num_vars
];
1981 for (int i
= 0; i
< num_vars
; i
++) {
1982 vgrf_to_reg
[i
] = reg_count
;
1983 reg_count
+= alloc
.sizes
[i
];
1986 /* An array of "split points". For each register slot, this indicates
1987 * if this slot can be separated from the previous slot. Every time an
1988 * instruction uses multiple elements of a register (as a source or
1989 * destination), we mark the used slots as inseparable. Then we go
1990 * through and split the registers into the smallest pieces we can.
1992 bool split_points
[reg_count
];
1993 memset(split_points
, 0, sizeof(split_points
));
1995 /* Mark all used registers as fully splittable */
1996 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1997 if (inst
->dst
.file
== GRF
) {
1998 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1999 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
2000 split_points
[reg
+ j
] = true;
2003 for (int i
= 0; i
< inst
->sources
; i
++) {
2004 if (inst
->src
[i
].file
== GRF
) {
2005 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
2006 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
2007 split_points
[reg
+ j
] = true;
2012 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2013 if (inst
->dst
.file
== GRF
) {
2014 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
2015 for (int j
= 1; j
< inst
->regs_written
; j
++)
2016 split_points
[reg
+ j
] = false;
2018 for (int i
= 0; i
< inst
->sources
; i
++) {
2019 if (inst
->src
[i
].file
== GRF
) {
2020 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2021 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
2022 split_points
[reg
+ j
] = false;
2027 int new_virtual_grf
[reg_count
];
2028 int new_reg_offset
[reg_count
];
2031 for (int i
= 0; i
< num_vars
; i
++) {
2032 /* The first one should always be 0 as a quick sanity check. */
2033 assert(split_points
[reg
] == false);
2036 new_reg_offset
[reg
] = 0;
2041 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
2042 /* If this is a split point, reset the offset to 0 and allocate a
2043 * new virtual GRF for the previous offset many registers
2045 if (split_points
[reg
]) {
2046 assert(offset
<= MAX_VGRF_SIZE
);
2047 int grf
= alloc
.allocate(offset
);
2048 for (int k
= reg
- offset
; k
< reg
; k
++)
2049 new_virtual_grf
[k
] = grf
;
2052 new_reg_offset
[reg
] = offset
;
2057 /* The last one gets the original register number */
2058 assert(offset
<= MAX_VGRF_SIZE
);
2059 alloc
.sizes
[i
] = offset
;
2060 for (int k
= reg
- offset
; k
< reg
; k
++)
2061 new_virtual_grf
[k
] = i
;
2063 assert(reg
== reg_count
);
2065 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2066 if (inst
->dst
.file
== GRF
) {
2067 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
2068 inst
->dst
.reg
= new_virtual_grf
[reg
];
2069 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
2070 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2072 for (int i
= 0; i
< inst
->sources
; i
++) {
2073 if (inst
->src
[i
].file
== GRF
) {
2074 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
2075 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
2076 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
2077 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
2081 invalidate_live_intervals();
2085 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
2087 * During code generation, we create tons of temporary variables, many of
2088 * which get immediately killed and are never used again. Yet, in later
2089 * optimization and analysis passes, such as compute_live_intervals, we need
2090 * to loop over all the virtual GRFs. Compacting them can save a lot of
2094 fs_visitor::compact_virtual_grfs()
2096 bool progress
= false;
2097 int remap_table
[this->alloc
.count
];
2098 memset(remap_table
, -1, sizeof(remap_table
));
2100 /* Mark which virtual GRFs are used. */
2101 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
2102 if (inst
->dst
.file
== GRF
)
2103 remap_table
[inst
->dst
.reg
] = 0;
2105 for (int i
= 0; i
< inst
->sources
; i
++) {
2106 if (inst
->src
[i
].file
== GRF
)
2107 remap_table
[inst
->src
[i
].reg
] = 0;
2111 /* Compact the GRF arrays. */
2113 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
2114 if (remap_table
[i
] == -1) {
2115 /* We just found an unused register. This means that we are
2116 * actually going to compact something.
2120 remap_table
[i
] = new_index
;
2121 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
2122 invalidate_live_intervals();
2127 this->alloc
.count
= new_index
;
2129 /* Patch all the instructions to use the newly renumbered registers */
2130 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2131 if (inst
->dst
.file
== GRF
)
2132 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
2134 for (int i
= 0; i
< inst
->sources
; i
++) {
2135 if (inst
->src
[i
].file
== GRF
)
2136 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
2140 /* Patch all the references to delta_xy, since they're used in register
2141 * allocation. If they're unused, switch them to BAD_FILE so we don't
2142 * think some random VGRF is delta_xy.
2144 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2145 if (delta_xy
[i
].file
== GRF
) {
2146 if (remap_table
[delta_xy
[i
].reg
] != -1) {
2147 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
2149 delta_xy
[i
].file
= BAD_FILE
;
2158 * Implements array access of uniforms by inserting a
2159 * PULL_CONSTANT_LOAD instruction.
2161 * Unlike temporary GRF array access (where we don't support it due to
2162 * the difficulty of doing relative addressing on instruction
2163 * destinations), we could potentially do array access of uniforms
2164 * that were loaded in GRF space as push constants. In real-world
2165 * usage we've seen, though, the arrays being used are always larger
2166 * than we could load as push constants, so just always move all
2167 * uniform array access out to a pull constant buffer.
2170 fs_visitor::move_uniform_array_access_to_pull_constants()
2172 if (dispatch_width
!= 8)
2175 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2176 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
2178 /* Walk through and find array access of uniforms. Put a copy of that
2179 * uniform in the pull constant buffer.
2181 * Note that we don't move constant-indexed accesses to arrays. No
2182 * testing has been done of the performance impact of this choice.
2184 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2185 for (int i
= 0 ; i
< inst
->sources
; i
++) {
2186 if (inst
->src
[i
].file
!= UNIFORM
|| !inst
->src
[i
].reladdr
)
2189 int uniform
= inst
->src
[i
].reg
;
2191 /* If this array isn't already present in the pull constant buffer,
2194 if (pull_constant_loc
[uniform
] == -1) {
2195 const gl_constant_value
**values
= &stage_prog_data
->param
[uniform
];
2197 assert(param_size
[uniform
]);
2199 for (int j
= 0; j
< param_size
[uniform
]; j
++) {
2200 pull_constant_loc
[uniform
+ j
] = stage_prog_data
->nr_pull_params
;
2202 stage_prog_data
->pull_param
[stage_prog_data
->nr_pull_params
++] =
2211 * Assign UNIFORM file registers to either push constants or pull constants.
2213 * We allow a fragment shader to have more than the specified minimum
2214 * maximum number of fragment shader uniform components (64). If
2215 * there are too many of these, they'd fill up all of register space.
2216 * So, this will push some of them out to the pull constant buffer and
2217 * update the program to load them.
2220 fs_visitor::assign_constant_locations()
2222 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
2223 if (dispatch_width
!= 8)
2226 /* Find which UNIFORM registers are still in use. */
2227 bool is_live
[uniforms
];
2228 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2232 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2233 for (int i
= 0; i
< inst
->sources
; i
++) {
2234 if (inst
->src
[i
].file
!= UNIFORM
)
2237 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2238 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
2239 is_live
[constant_nr
] = true;
2243 /* Only allow 16 registers (128 uniform components) as push constants.
2245 * Just demote the end of the list. We could probably do better
2246 * here, demoting things that are rarely used in the program first.
2248 * If changing this value, note the limitation about total_regs in
2251 unsigned int max_push_components
= 16 * 8;
2252 unsigned int num_push_constants
= 0;
2254 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
2256 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2257 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
2258 /* This UNIFORM register is either dead, or has already been demoted
2259 * to a pull const. Mark it as no longer living in the param[] array.
2261 push_constant_loc
[i
] = -1;
2265 if (num_push_constants
< max_push_components
) {
2266 /* Retain as a push constant. Record the location in the params[]
2269 push_constant_loc
[i
] = num_push_constants
++;
2271 /* Demote to a pull constant. */
2272 push_constant_loc
[i
] = -1;
2274 int pull_index
= stage_prog_data
->nr_pull_params
++;
2275 stage_prog_data
->pull_param
[pull_index
] = stage_prog_data
->param
[i
];
2276 pull_constant_loc
[i
] = pull_index
;
2280 stage_prog_data
->nr_params
= num_push_constants
;
2282 /* Up until now, the param[] array has been indexed by reg + reg_offset
2283 * of UNIFORM registers. Condense it to only contain the uniforms we
2284 * chose to upload as push constants.
2286 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2287 int remapped
= push_constant_loc
[i
];
2292 assert(remapped
<= (int)i
);
2293 stage_prog_data
->param
[remapped
] = stage_prog_data
->param
[i
];
2298 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2299 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2302 fs_visitor::demote_pull_constants()
2304 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2305 for (int i
= 0; i
< inst
->sources
; i
++) {
2306 if (inst
->src
[i
].file
!= UNIFORM
)
2310 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
2311 if (location
>= uniforms
) /* Out of bounds access */
2314 pull_index
= pull_constant_loc
[location
];
2316 if (pull_index
== -1)
2319 /* Set up the annotation tracking for new generated instructions. */
2321 current_annotation
= inst
->annotation
;
2323 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
2324 fs_reg dst
= vgrf(glsl_type::float_type
);
2326 /* Generate a pull load into dst. */
2327 if (inst
->src
[i
].reladdr
) {
2328 exec_list list
= VARYING_PULL_CONSTANT_LOAD(dst
,
2330 *inst
->src
[i
].reladdr
,
2332 inst
->insert_before(block
, &list
);
2333 inst
->src
[i
].reladdr
= NULL
;
2335 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
2337 new(mem_ctx
) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, 8,
2338 dst
, surf_index
, offset
);
2339 inst
->insert_before(block
, pull
);
2340 inst
->src
[i
].set_smear(pull_index
& 3);
2343 /* Rewrite the instruction to use the temporary VGRF. */
2344 inst
->src
[i
].file
= GRF
;
2345 inst
->src
[i
].reg
= dst
.reg
;
2346 inst
->src
[i
].reg_offset
= 0;
2347 inst
->src
[i
].width
= dispatch_width
;
2350 invalidate_live_intervals();
2354 fs_visitor::opt_algebraic()
2356 bool progress
= false;
2358 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2359 switch (inst
->opcode
) {
2360 case BRW_OPCODE_MOV
:
2361 if (inst
->src
[0].file
!= IMM
)
2364 if (inst
->saturate
) {
2365 if (inst
->dst
.type
!= inst
->src
[0].type
)
2366 assert(!"unimplemented: saturate mixed types");
2368 if (brw_saturate_immediate(inst
->dst
.type
,
2369 &inst
->src
[0].fixed_hw_reg
)) {
2370 inst
->saturate
= false;
2376 case BRW_OPCODE_MUL
:
2377 if (inst
->src
[1].file
!= IMM
)
2381 if (inst
->src
[1].is_one()) {
2382 inst
->opcode
= BRW_OPCODE_MOV
;
2383 inst
->src
[1] = reg_undef
;
2389 if (inst
->src
[1].is_negative_one()) {
2390 inst
->opcode
= BRW_OPCODE_MOV
;
2391 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2392 inst
->src
[1] = reg_undef
;
2398 if (inst
->src
[1].is_zero()) {
2399 inst
->opcode
= BRW_OPCODE_MOV
;
2400 inst
->src
[0] = inst
->src
[1];
2401 inst
->src
[1] = reg_undef
;
2406 if (inst
->src
[0].file
== IMM
) {
2407 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2408 inst
->opcode
= BRW_OPCODE_MOV
;
2409 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2410 inst
->src
[1] = reg_undef
;
2415 case BRW_OPCODE_ADD
:
2416 if (inst
->src
[1].file
!= IMM
)
2420 if (inst
->src
[1].is_zero()) {
2421 inst
->opcode
= BRW_OPCODE_MOV
;
2422 inst
->src
[1] = reg_undef
;
2427 if (inst
->src
[0].file
== IMM
) {
2428 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2429 inst
->opcode
= BRW_OPCODE_MOV
;
2430 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2431 inst
->src
[1] = reg_undef
;
2437 if (inst
->src
[0].equals(inst
->src
[1])) {
2438 inst
->opcode
= BRW_OPCODE_MOV
;
2439 inst
->src
[1] = reg_undef
;
2444 case BRW_OPCODE_LRP
:
2445 if (inst
->src
[1].equals(inst
->src
[2])) {
2446 inst
->opcode
= BRW_OPCODE_MOV
;
2447 inst
->src
[0] = inst
->src
[1];
2448 inst
->src
[1] = reg_undef
;
2449 inst
->src
[2] = reg_undef
;
2454 case BRW_OPCODE_CMP
:
2455 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2457 inst
->src
[0].negate
&&
2458 inst
->src
[1].is_zero()) {
2459 inst
->src
[0].abs
= false;
2460 inst
->src
[0].negate
= false;
2461 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2466 case BRW_OPCODE_SEL
:
2467 if (inst
->src
[0].equals(inst
->src
[1])) {
2468 inst
->opcode
= BRW_OPCODE_MOV
;
2469 inst
->src
[1] = reg_undef
;
2470 inst
->predicate
= BRW_PREDICATE_NONE
;
2471 inst
->predicate_inverse
= false;
2473 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2474 switch (inst
->conditional_mod
) {
2475 case BRW_CONDITIONAL_LE
:
2476 case BRW_CONDITIONAL_L
:
2477 switch (inst
->src
[1].type
) {
2478 case BRW_REGISTER_TYPE_F
:
2479 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2480 inst
->opcode
= BRW_OPCODE_MOV
;
2481 inst
->src
[1] = reg_undef
;
2482 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2490 case BRW_CONDITIONAL_GE
:
2491 case BRW_CONDITIONAL_G
:
2492 switch (inst
->src
[1].type
) {
2493 case BRW_REGISTER_TYPE_F
:
2494 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2495 inst
->opcode
= BRW_OPCODE_MOV
;
2496 inst
->src
[1] = reg_undef
;
2497 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2509 case BRW_OPCODE_MAD
:
2510 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2511 inst
->opcode
= BRW_OPCODE_MOV
;
2512 inst
->src
[1] = reg_undef
;
2513 inst
->src
[2] = reg_undef
;
2515 } else if (inst
->src
[0].is_zero()) {
2516 inst
->opcode
= BRW_OPCODE_MUL
;
2517 inst
->src
[0] = inst
->src
[2];
2518 inst
->src
[2] = reg_undef
;
2520 } else if (inst
->src
[1].is_one()) {
2521 inst
->opcode
= BRW_OPCODE_ADD
;
2522 inst
->src
[1] = inst
->src
[2];
2523 inst
->src
[2] = reg_undef
;
2525 } else if (inst
->src
[2].is_one()) {
2526 inst
->opcode
= BRW_OPCODE_ADD
;
2527 inst
->src
[2] = reg_undef
;
2529 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2530 inst
->opcode
= BRW_OPCODE_ADD
;
2531 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2532 inst
->src
[2] = reg_undef
;
2536 case SHADER_OPCODE_RCP
: {
2537 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2538 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2539 if (inst
->src
[0].equals(prev
->dst
)) {
2540 inst
->opcode
= SHADER_OPCODE_RSQ
;
2541 inst
->src
[0] = prev
->src
[0];
2547 case SHADER_OPCODE_BROADCAST
:
2548 if (is_uniform(inst
->src
[0])) {
2549 inst
->opcode
= BRW_OPCODE_MOV
;
2551 inst
->force_writemask_all
= true;
2553 } else if (inst
->src
[1].file
== IMM
) {
2554 inst
->opcode
= BRW_OPCODE_MOV
;
2555 inst
->src
[0] = component(inst
->src
[0],
2556 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2558 inst
->force_writemask_all
= true;
2567 /* Swap if src[0] is immediate. */
2568 if (progress
&& inst
->is_commutative()) {
2569 if (inst
->src
[0].file
== IMM
) {
2570 fs_reg tmp
= inst
->src
[1];
2571 inst
->src
[1] = inst
->src
[0];
2580 * Optimize sample messages that have constant zero values for the trailing
2581 * texture coordinates. We can just reduce the message length for these
2582 * instructions instead of reserving a register for it. Trailing parameters
2583 * that aren't sent default to zero anyway. This will cause the dead code
2584 * eliminator to remove the MOV instruction that would otherwise be emitted to
2585 * set up the zero value.
2588 fs_visitor::opt_zero_samples()
2590 /* Gen4 infers the texturing opcode based on the message length so we can't
2593 if (devinfo
->gen
< 5)
2596 bool progress
= false;
2598 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2599 if (!inst
->is_tex())
2602 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2604 if (load_payload
->is_head_sentinel() ||
2605 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2608 /* We don't want to remove the message header or the first parameter.
2609 * Removing the first parameter is not allowed, see the Haswell PRM
2610 * volume 7, page 149:
2612 * "Parameter 0 is required except for the sampleinfo message, which
2613 * has no parameter 0"
2615 while (inst
->mlen
> inst
->header_size
+ dispatch_width
/ 8 &&
2616 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2617 (dispatch_width
/ 8) +
2618 inst
->header_size
- 1].is_zero()) {
2619 inst
->mlen
-= dispatch_width
/ 8;
2625 invalidate_live_intervals();
2631 * Optimize sample messages which are followed by the final RT write.
2633 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2634 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2635 * final texturing results copied to the framebuffer write payload and modify
2636 * them to write to the framebuffer directly.
2639 fs_visitor::opt_sampler_eot()
2641 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2643 if (stage
!= MESA_SHADER_FRAGMENT
)
2646 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2649 /* FINISHME: It should be possible to implement this optimization when there
2650 * are multiple drawbuffers.
2652 if (key
->nr_color_regions
!= 1)
2655 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2656 fs_inst
*fb_write
= (fs_inst
*) cfg
->blocks
[cfg
->num_blocks
- 1]->end();
2657 assert(fb_write
->eot
);
2658 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2660 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2662 /* There wasn't one; nothing to do. */
2663 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2666 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2667 * It's very likely to be the previous instruction.
2669 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2670 if (load_payload
->is_head_sentinel() ||
2671 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2674 assert(!tex_inst
->eot
); /* We can't get here twice */
2675 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2677 tex_inst
->offset
|= fb_write
->target
<< 24;
2678 tex_inst
->eot
= true;
2679 tex_inst
->dst
= reg_null_ud
;
2680 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2682 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2683 * to create a new LOAD_PAYLOAD command with the same sources and a space
2684 * saved for the header. Using a new destination register not only makes sure
2685 * we have enough space, but it will make sure the dead code eliminator kills
2686 * the instruction that this will replace.
2688 if (tex_inst
->header_size
!= 0)
2691 fs_reg send_header
= vgrf(load_payload
->sources
+ 1);
2692 fs_reg
*new_sources
=
2693 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2695 new_sources
[0] = fs_reg();
2696 for (int i
= 0; i
< load_payload
->sources
; i
++)
2697 new_sources
[i
+1] = load_payload
->src
[i
];
2699 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2700 * requires a lot of information about the sources to appropriately figure
2701 * out the number of registers needed to be used. Given this stage in our
2702 * optimization, we may not have the appropriate GRFs required by
2703 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2704 * manually emit the instruction.
2706 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2707 load_payload
->exec_size
,
2710 load_payload
->sources
+ 1);
2712 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2713 new_load_payload
->header_size
= 1;
2715 tex_inst
->header_size
= 1;
2716 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2717 tex_inst
->src
[0] = send_header
;
2723 fs_visitor::opt_register_renaming()
2725 bool progress
= false;
2728 int remap
[alloc
.count
];
2729 memset(remap
, -1, sizeof(int) * alloc
.count
);
2731 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2732 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2734 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2735 inst
->opcode
== BRW_OPCODE_WHILE
) {
2739 /* Rewrite instruction sources. */
2740 for (int i
= 0; i
< inst
->sources
; i
++) {
2741 if (inst
->src
[i
].file
== GRF
&&
2742 remap
[inst
->src
[i
].reg
] != -1 &&
2743 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2744 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2749 const int dst
= inst
->dst
.reg
;
2752 inst
->dst
.file
== GRF
&&
2753 alloc
.sizes
[inst
->dst
.reg
] == inst
->dst
.width
/ 8 &&
2754 !inst
->is_partial_write()) {
2755 if (remap
[dst
] == -1) {
2758 remap
[dst
] = alloc
.allocate(inst
->dst
.width
/ 8);
2759 inst
->dst
.reg
= remap
[dst
];
2762 } else if (inst
->dst
.file
== GRF
&&
2764 remap
[dst
] != dst
) {
2765 inst
->dst
.reg
= remap
[dst
];
2771 invalidate_live_intervals();
2773 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2774 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2775 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2784 * Remove redundant or useless discard jumps.
2786 * For example, we can eliminate jumps in the following sequence:
2788 * discard-jump (redundant with the next jump)
2789 * discard-jump (useless; jumps to the next instruction)
2793 fs_visitor::opt_redundant_discard_jumps()
2795 bool progress
= false;
2797 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2799 fs_inst
*placeholder_halt
= NULL
;
2800 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2801 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2802 placeholder_halt
= inst
;
2807 if (!placeholder_halt
)
2810 /* Delete any HALTs immediately before the placeholder halt. */
2811 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2812 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2813 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2814 prev
->remove(last_bblock
);
2819 invalidate_live_intervals();
2825 fs_visitor::compute_to_mrf()
2827 bool progress
= false;
2830 /* No MRFs on Gen >= 7. */
2831 if (devinfo
->gen
>= 7)
2834 calculate_live_intervals();
2836 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2840 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2841 inst
->is_partial_write() ||
2842 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2843 inst
->dst
.type
!= inst
->src
[0].type
||
2844 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2845 !inst
->src
[0].is_contiguous() ||
2846 inst
->src
[0].subreg_offset
)
2849 /* Work out which hardware MRF registers are written by this
2852 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2854 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2855 mrf_high
= mrf_low
+ 4;
2856 } else if (inst
->exec_size
== 16) {
2857 mrf_high
= mrf_low
+ 1;
2862 /* Can't compute-to-MRF this GRF if someone else was going to
2865 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2868 /* Found a move of a GRF to a MRF. Let's see if we can go
2869 * rewrite the thing that made this GRF to write into the MRF.
2871 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
2872 if (scan_inst
->dst
.file
== GRF
&&
2873 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2874 /* Found the last thing to write our reg we want to turn
2875 * into a compute-to-MRF.
2878 /* If this one instruction didn't populate all the
2879 * channels, bail. We might be able to rewrite everything
2880 * that writes that reg, but it would require smarter
2881 * tracking to delay the rewriting until complete success.
2883 if (scan_inst
->is_partial_write())
2886 /* Things returning more than one register would need us to
2887 * understand coalescing out more than one MOV at a time.
2889 if (scan_inst
->regs_written
> scan_inst
->dst
.width
/ 8)
2892 /* SEND instructions can't have MRF as a destination. */
2893 if (scan_inst
->mlen
)
2896 if (devinfo
->gen
== 6) {
2897 /* gen6 math instructions must have the destination be
2898 * GRF, so no compute-to-MRF for them.
2900 if (scan_inst
->is_math()) {
2905 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2906 /* Found the creator of our MRF's source value. */
2907 scan_inst
->dst
.file
= MRF
;
2908 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2909 scan_inst
->saturate
|= inst
->saturate
;
2910 inst
->remove(block
);
2916 /* We don't handle control flow here. Most computation of
2917 * values that end up in MRFs are shortly before the MRF
2920 if (block
->start() == scan_inst
)
2923 /* You can't read from an MRF, so if someone else reads our
2924 * MRF's source GRF that we wanted to rewrite, that stops us.
2926 bool interfered
= false;
2927 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2928 if (scan_inst
->src
[i
].file
== GRF
&&
2929 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2930 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2937 if (scan_inst
->dst
.file
== MRF
) {
2938 /* If somebody else writes our MRF here, we can't
2939 * compute-to-MRF before that.
2941 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2944 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2945 scan_mrf_high
= scan_mrf_low
+ 4;
2946 } else if (scan_inst
->exec_size
== 16) {
2947 scan_mrf_high
= scan_mrf_low
+ 1;
2949 scan_mrf_high
= scan_mrf_low
;
2952 if (mrf_low
== scan_mrf_low
||
2953 mrf_low
== scan_mrf_high
||
2954 mrf_high
== scan_mrf_low
||
2955 mrf_high
== scan_mrf_high
) {
2960 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2961 /* Found a SEND instruction, which means that there are
2962 * live values in MRFs from base_mrf to base_mrf +
2963 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2966 if (mrf_low
>= scan_inst
->base_mrf
&&
2967 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2970 if (mrf_high
>= scan_inst
->base_mrf
&&
2971 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2979 invalidate_live_intervals();
2985 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2986 * flow. We could probably do better here with some form of divergence
2990 fs_visitor::eliminate_find_live_channel()
2992 bool progress
= false;
2995 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2996 switch (inst
->opcode
) {
3002 case BRW_OPCODE_ENDIF
:
3003 case BRW_OPCODE_WHILE
:
3007 case FS_OPCODE_DISCARD_JUMP
:
3008 /* This can potentially make control flow non-uniform until the end
3013 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
3015 inst
->opcode
= BRW_OPCODE_MOV
;
3016 inst
->src
[0] = fs_reg(0);
3018 inst
->force_writemask_all
= true;
3032 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
3033 * instructions to FS_OPCODE_REP_FB_WRITE.
3036 fs_visitor::emit_repclear_shader()
3038 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3040 int color_mrf
= base_mrf
+ 2;
3043 if (uniforms
== 1) {
3044 mov
= emit(MOV(vec4(brw_message_reg(color_mrf
)),
3045 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
)));
3047 struct brw_reg reg
=
3048 brw_reg(BRW_GENERAL_REGISTER_FILE
,
3049 2, 3, 0, 0, BRW_REGISTER_TYPE_F
,
3050 BRW_VERTICAL_STRIDE_8
,
3052 BRW_HORIZONTAL_STRIDE_4
, BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
3054 mov
= emit(MOV(vec4(brw_message_reg(color_mrf
)), fs_reg(reg
)));
3057 mov
->force_writemask_all
= true;
3060 if (key
->nr_color_regions
== 1) {
3061 write
= emit(FS_OPCODE_REP_FB_WRITE
);
3062 write
->saturate
= key
->clamp_fragment_color
;
3063 write
->base_mrf
= color_mrf
;
3065 write
->header_size
= 0;
3068 assume(key
->nr_color_regions
> 0);
3069 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
3070 write
= emit(FS_OPCODE_REP_FB_WRITE
);
3071 write
->saturate
= key
->clamp_fragment_color
;
3072 write
->base_mrf
= base_mrf
;
3074 write
->header_size
= 2;
3082 assign_constant_locations();
3083 assign_curb_setup();
3085 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
3086 if (uniforms
== 1) {
3087 assert(mov
->src
[0].file
== HW_REG
);
3088 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
3093 * Walks through basic blocks, looking for repeated MRF writes and
3094 * removing the later ones.
3097 fs_visitor::remove_duplicate_mrf_writes()
3099 fs_inst
*last_mrf_move
[16];
3100 bool progress
= false;
3102 /* Need to update the MRF tracking for compressed instructions. */
3103 if (dispatch_width
== 16)
3106 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3108 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3109 if (inst
->is_control_flow()) {
3110 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
3113 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3114 inst
->dst
.file
== MRF
) {
3115 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
3116 if (prev_inst
&& inst
->equals(prev_inst
)) {
3117 inst
->remove(block
);
3123 /* Clear out the last-write records for MRFs that were overwritten. */
3124 if (inst
->dst
.file
== MRF
) {
3125 last_mrf_move
[inst
->dst
.reg
] = NULL
;
3128 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
3129 /* Found a SEND instruction, which will include two or fewer
3130 * implied MRF writes. We could do better here.
3132 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
3133 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
3137 /* Clear out any MRF move records whose sources got overwritten. */
3138 if (inst
->dst
.file
== GRF
) {
3139 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
3140 if (last_mrf_move
[i
] &&
3141 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
3142 last_mrf_move
[i
] = NULL
;
3147 if (inst
->opcode
== BRW_OPCODE_MOV
&&
3148 inst
->dst
.file
== MRF
&&
3149 inst
->src
[0].file
== GRF
&&
3150 !inst
->is_partial_write()) {
3151 last_mrf_move
[inst
->dst
.reg
] = inst
;
3156 invalidate_live_intervals();
3162 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
3164 /* Clear the flag for registers that actually got read (as expected). */
3165 for (int i
= 0; i
< inst
->sources
; i
++) {
3167 if (inst
->src
[i
].file
== GRF
) {
3168 grf
= inst
->src
[i
].reg
;
3169 } else if (inst
->src
[i
].file
== HW_REG
&&
3170 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
3171 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
3176 if (grf
>= first_grf
&&
3177 grf
< first_grf
+ grf_len
) {
3178 deps
[grf
- first_grf
] = false;
3179 if (inst
->exec_size
== 16)
3180 deps
[grf
- first_grf
+ 1] = false;
3186 * Implements this workaround for the original 965:
3188 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
3189 * check for post destination dependencies on this instruction, software
3190 * must ensure that there is no destination hazard for the case of ‘write
3191 * followed by a posted write’ shown in the following example.
3194 * 2. send r3.xy <rest of send instruction>
3197 * Due to no post-destination dependency check on the ‘send’, the above
3198 * code sequence could have two instructions (1 and 2) in flight at the
3199 * same time that both consider ‘r3’ as the target of their final writes.
3202 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
3205 int write_len
= inst
->regs_written
;
3206 int first_write_grf
= inst
->dst
.reg
;
3207 bool needs_dep
[BRW_MAX_MRF
];
3208 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3210 memset(needs_dep
, false, sizeof(needs_dep
));
3211 memset(needs_dep
, true, write_len
);
3213 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
3215 /* Walk backwards looking for writes to registers we're writing which
3216 * aren't read since being written. If we hit the start of the program,
3217 * we assume that there are no outstanding dependencies on entry to the
3220 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3221 /* If we hit control flow, assume that there *are* outstanding
3222 * dependencies, and force their cleanup before our instruction.
3224 if (block
->start() == scan_inst
) {
3225 for (int i
= 0; i
< write_len
; i
++) {
3227 inst
->insert_before(block
, DEP_RESOLVE_MOV(first_write_grf
+ i
));
3233 /* We insert our reads as late as possible on the assumption that any
3234 * instruction but a MOV that might have left us an outstanding
3235 * dependency has more latency than a MOV.
3237 if (scan_inst
->dst
.file
== GRF
) {
3238 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
3239 int reg
= scan_inst
->dst
.reg
+ i
;
3241 if (reg
>= first_write_grf
&&
3242 reg
< first_write_grf
+ write_len
&&
3243 needs_dep
[reg
- first_write_grf
]) {
3244 inst
->insert_before(block
, DEP_RESOLVE_MOV(reg
));
3245 needs_dep
[reg
- first_write_grf
] = false;
3246 if (scan_inst
->exec_size
== 16)
3247 needs_dep
[reg
- first_write_grf
+ 1] = false;
3252 /* Clear the flag for registers that actually got read (as expected). */
3253 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3255 /* Continue the loop only if we haven't resolved all the dependencies */
3257 for (i
= 0; i
< write_len
; i
++) {
3267 * Implements this workaround for the original 965:
3269 * "[DevBW, DevCL] Errata: A destination register from a send can not be
3270 * used as a destination register until after it has been sourced by an
3271 * instruction with a different destination register.
3274 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3276 int write_len
= inst
->regs_written
;
3277 int first_write_grf
= inst
->dst
.reg
;
3278 bool needs_dep
[BRW_MAX_MRF
];
3279 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3281 memset(needs_dep
, false, sizeof(needs_dep
));
3282 memset(needs_dep
, true, write_len
);
3283 /* Walk forwards looking for writes to registers we're writing which aren't
3284 * read before being written.
3286 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
, block
) {
3287 /* If we hit control flow, force resolve all remaining dependencies. */
3288 if (block
->end() == scan_inst
) {
3289 for (int i
= 0; i
< write_len
; i
++) {
3291 scan_inst
->insert_before(block
,
3292 DEP_RESOLVE_MOV(first_write_grf
+ i
));
3297 /* Clear the flag for registers that actually got read (as expected). */
3298 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3300 /* We insert our reads as late as possible since they're reading the
3301 * result of a SEND, which has massive latency.
3303 if (scan_inst
->dst
.file
== GRF
&&
3304 scan_inst
->dst
.reg
>= first_write_grf
&&
3305 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
3306 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
3307 scan_inst
->insert_before(block
, DEP_RESOLVE_MOV(scan_inst
->dst
.reg
));
3308 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
3311 /* Continue the loop only if we haven't resolved all the dependencies */
3313 for (i
= 0; i
< write_len
; i
++) {
3323 fs_visitor::insert_gen4_send_dependency_workarounds()
3325 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3328 bool progress
= false;
3330 /* Note that we're done with register allocation, so GRF fs_regs always
3331 * have a .reg_offset of 0.
3334 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3335 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
3336 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3337 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3343 invalidate_live_intervals();
3347 * Turns the generic expression-style uniform pull constant load instruction
3348 * into a hardware-specific series of instructions for loading a pull
3351 * The expression style allows the CSE pass before this to optimize out
3352 * repeated loads from the same offset, and gives the pre-register-allocation
3353 * scheduling full flexibility, while the conversion to native instructions
3354 * allows the post-register-allocation scheduler the best information
3357 * Note that execution masking for setting up pull constant loads is special:
3358 * the channels that need to be written are unrelated to the current execution
3359 * mask, since a later instruction will use one of the result channels as a
3360 * source operand for all 8 or 16 of its channels.
3363 fs_visitor::lower_uniform_pull_constant_loads()
3365 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3366 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3369 if (devinfo
->gen
>= 7) {
3370 /* The offset arg before was a vec4-aligned byte offset. We need to
3371 * turn it into a dword offset.
3373 fs_reg const_offset_reg
= inst
->src
[1];
3374 assert(const_offset_reg
.file
== IMM
&&
3375 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3376 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
3377 fs_reg payload
= fs_reg(GRF
, alloc
.allocate(1));
3379 /* We have to use a message header on Skylake to get SIMD4x2 mode.
3380 * Reserve space for the register.
3382 if (devinfo
->gen
>= 9) {
3383 payload
.reg_offset
++;
3384 alloc
.sizes
[payload
.reg
] = 2;
3387 /* This is actually going to be a MOV, but since only the first dword
3388 * is accessed, we have a special opcode to do just that one. Note
3389 * that this needs to be an operation that will be considered a def
3390 * by live variable analysis, or register allocation will explode.
3392 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3393 8, payload
, const_offset_reg
);
3394 setup
->force_writemask_all
= true;
3396 setup
->ir
= inst
->ir
;
3397 setup
->annotation
= inst
->annotation
;
3398 inst
->insert_before(block
, setup
);
3400 /* Similarly, this will only populate the first 4 channels of the
3401 * result register (since we only use smear values from 0-3), but we
3402 * don't tell the optimizer.
3404 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3405 inst
->src
[1] = payload
;
3407 invalidate_live_intervals();
3409 /* Before register allocation, we didn't tell the scheduler about the
3410 * MRF we use. We know it's safe to use this MRF because nothing
3411 * else does except for register spill/unspill, which generates and
3412 * uses its MRF within a single IR instruction.
3414 inst
->base_mrf
= 14;
3421 fs_visitor::lower_load_payload()
3423 bool progress
= false;
3425 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3426 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3429 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3430 assert(inst
->saturate
== false);
3432 fs_reg dst
= inst
->dst
;
3434 /* Get rid of COMPR4. We'll add it back in if we need it */
3435 if (dst
.file
== MRF
)
3436 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3439 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3440 if (inst
->src
[i
].file
!= BAD_FILE
) {
3441 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3442 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3444 fs_inst
*mov
= MOV(mov_dst
, mov_src
);
3445 mov
->force_writemask_all
= true;
3446 inst
->insert_before(block
, mov
);
3448 dst
= offset(dst
, 1);
3451 dst
.width
= inst
->exec_size
;
3452 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3453 inst
->exec_size
> 8) {
3454 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3455 * a straightforward copy. Instead, the result of the
3456 * LOAD_PAYLOAD is treated as interleaved and the first four
3457 * non-header sources are unpacked as:
3468 * This is used for gen <= 5 fb writes.
3470 assert(inst
->exec_size
== 16);
3471 assert(inst
->header_size
+ 4 <= inst
->sources
);
3472 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3473 if (inst
->src
[i
].file
!= BAD_FILE
) {
3474 if (devinfo
->has_compr4
) {
3475 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3476 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3478 fs_inst
*mov
= MOV(compr4_dst
, inst
->src
[i
]);
3479 mov
->force_writemask_all
= inst
->force_writemask_all
;
3480 inst
->insert_before(block
, mov
);
3482 /* Platform doesn't have COMPR4. We have to fake it */
3483 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3486 fs_inst
*mov
= MOV(mov_dst
, half(inst
->src
[i
], 0));
3487 mov
->force_writemask_all
= inst
->force_writemask_all
;
3488 inst
->insert_before(block
, mov
);
3490 mov
= MOV(offset(mov_dst
, 4), half(inst
->src
[i
], 1));
3491 mov
->force_writemask_all
= inst
->force_writemask_all
;
3492 mov
->force_sechalf
= true;
3493 inst
->insert_before(block
, mov
);
3500 /* The loop above only ever incremented us through the first set
3501 * of 4 registers. However, thanks to the magic of COMPR4, we
3502 * actually wrote to the first 8 registers, so we need to take
3503 * that into account now.
3507 /* The COMPR4 code took care of the first 4 sources. We'll let
3508 * the regular path handle any remaining sources. Yes, we are
3509 * modifying the instruction but we're about to delete it so
3510 * this really doesn't hurt anything.
3512 inst
->header_size
+= 4;
3515 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3516 if (inst
->src
[i
].file
!= BAD_FILE
) {
3517 fs_inst
*mov
= MOV(retype(dst
, inst
->src
[i
].type
),
3519 mov
->force_writemask_all
= inst
->force_writemask_all
;
3520 inst
->insert_before(block
, mov
);
3522 dst
= offset(dst
, 1);
3525 inst
->remove(block
);
3530 invalidate_live_intervals();
3536 fs_visitor::dump_instructions()
3538 dump_instructions(NULL
);
3542 fs_visitor::dump_instructions(const char *name
)
3544 FILE *file
= stderr
;
3545 if (name
&& geteuid() != 0) {
3546 file
= fopen(name
, "w");
3552 calculate_register_pressure();
3553 int ip
= 0, max_pressure
= 0;
3554 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
3555 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
3556 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
3557 dump_instruction(inst
, file
);
3560 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
3563 foreach_in_list(backend_instruction
, inst
, &instructions
) {
3564 fprintf(file
, "%4d: ", ip
++);
3565 dump_instruction(inst
, file
);
3569 if (file
!= stderr
) {
3575 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
3577 dump_instruction(be_inst
, stderr
);
3581 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
3583 fs_inst
*inst
= (fs_inst
*)be_inst
;
3585 if (inst
->predicate
) {
3586 fprintf(file
, "(%cf0.%d) ",
3587 inst
->predicate_inverse
? '-' : '+',
3591 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
3593 fprintf(file
, ".sat");
3594 if (inst
->conditional_mod
) {
3595 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
3596 if (!inst
->predicate
&&
3597 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
3598 inst
->opcode
!= BRW_OPCODE_IF
&&
3599 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
3600 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
3603 fprintf(file
, "(%d) ", inst
->exec_size
);
3606 switch (inst
->dst
.file
) {
3608 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
3609 if (inst
->dst
.width
!= dispatch_width
)
3610 fprintf(file
, "@%d", inst
->dst
.width
);
3611 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->dst
.width
/ 8 ||
3612 inst
->dst
.subreg_offset
)
3613 fprintf(file
, "+%d.%d",
3614 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
3617 fprintf(file
, "m%d", inst
->dst
.reg
);
3620 fprintf(file
, "(null)");
3623 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3626 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
3629 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3630 switch (inst
->dst
.fixed_hw_reg
.nr
) {
3632 fprintf(file
, "null");
3634 case BRW_ARF_ADDRESS
:
3635 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
3637 case BRW_ARF_ACCUMULATOR
:
3638 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
3641 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3642 inst
->dst
.fixed_hw_reg
.subnr
);
3645 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
3646 inst
->dst
.fixed_hw_reg
.subnr
);
3650 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
3652 if (inst
->dst
.fixed_hw_reg
.subnr
)
3653 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
3656 fprintf(file
, "???");
3659 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
3661 for (int i
= 0; i
< inst
->sources
; i
++) {
3662 if (inst
->src
[i
].negate
)
3664 if (inst
->src
[i
].abs
)
3666 switch (inst
->src
[i
].file
) {
3668 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
3669 if (inst
->src
[i
].width
!= dispatch_width
)
3670 fprintf(file
, "@%d", inst
->src
[i
].width
);
3671 if (alloc
.sizes
[inst
->src
[i
].reg
] != inst
->src
[i
].width
/ 8 ||
3672 inst
->src
[i
].subreg_offset
)
3673 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3674 inst
->src
[i
].subreg_offset
);
3677 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
3680 fprintf(file
, "attr%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3683 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
3684 if (inst
->src
[i
].reladdr
) {
3685 fprintf(file
, "+reladdr");
3686 } else if (inst
->src
[i
].subreg_offset
) {
3687 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
3688 inst
->src
[i
].subreg_offset
);
3692 fprintf(file
, "(null)");
3695 switch (inst
->src
[i
].type
) {
3696 case BRW_REGISTER_TYPE_F
:
3697 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
3699 case BRW_REGISTER_TYPE_W
:
3700 case BRW_REGISTER_TYPE_D
:
3701 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
3703 case BRW_REGISTER_TYPE_UW
:
3704 case BRW_REGISTER_TYPE_UD
:
3705 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
3707 case BRW_REGISTER_TYPE_VF
:
3708 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
3709 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
3710 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
3711 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
3712 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
3715 fprintf(file
, "???");
3720 if (inst
->src
[i
].fixed_hw_reg
.negate
)
3722 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3724 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
3725 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
3727 fprintf(file
, "null");
3729 case BRW_ARF_ADDRESS
:
3730 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3732 case BRW_ARF_ACCUMULATOR
:
3733 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3736 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3737 inst
->src
[i
].fixed_hw_reg
.subnr
);
3740 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
3741 inst
->src
[i
].fixed_hw_reg
.subnr
);
3745 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
3747 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
3748 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
3749 if (inst
->src
[i
].fixed_hw_reg
.abs
)
3753 fprintf(file
, "???");
3756 if (inst
->src
[i
].abs
)
3759 if (inst
->src
[i
].file
!= IMM
) {
3760 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
3763 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
3764 fprintf(file
, ", ");
3769 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
3770 if (inst
->force_sechalf
)
3771 fprintf(file
, "2ndhalf ");
3773 fprintf(file
, "1sthalf ");
3776 fprintf(file
, "\n");
3780 * Possibly returns an instruction that set up @param reg.
3782 * Sometimes we want to take the result of some expression/variable
3783 * dereference tree and rewrite the instruction generating the result
3784 * of the tree. When processing the tree, we know that the
3785 * instructions generated are all writing temporaries that are dead
3786 * outside of this tree. So, if we have some instructions that write
3787 * a temporary, we're free to point that temp write somewhere else.
3789 * Note that this doesn't guarantee that the instruction generated
3790 * only reg -- it might be the size=4 destination of a texture instruction.
3793 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
3798 end
->is_partial_write() ||
3800 !reg
.equals(end
->dst
)) {
3808 fs_visitor::setup_payload_gen6()
3811 (prog
->InputsRead
& (1 << VARYING_SLOT_POS
)) != 0;
3812 unsigned barycentric_interp_modes
=
3813 (stage
== MESA_SHADER_FRAGMENT
) ?
3814 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
3816 assert(devinfo
->gen
>= 6);
3818 /* R0-1: masks, pixel X/Y coordinates. */
3819 payload
.num_regs
= 2;
3820 /* R2: only for 32-pixel dispatch.*/
3822 /* R3-26: barycentric interpolation coordinates. These appear in the
3823 * same order that they appear in the brw_wm_barycentric_interp_mode
3824 * enum. Each set of coordinates occupies 2 registers if dispatch width
3825 * == 8 and 4 registers if dispatch width == 16. Coordinates only
3826 * appear if they were enabled using the "Barycentric Interpolation
3827 * Mode" bits in WM_STATE.
3829 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
3830 if (barycentric_interp_modes
& (1 << i
)) {
3831 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
3832 payload
.num_regs
+= 2;
3833 if (dispatch_width
== 16) {
3834 payload
.num_regs
+= 2;
3839 /* R27: interpolated depth if uses source depth */
3841 payload
.source_depth_reg
= payload
.num_regs
;
3843 if (dispatch_width
== 16) {
3844 /* R28: interpolated depth if not SIMD8. */
3848 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
3850 payload
.source_w_reg
= payload
.num_regs
;
3852 if (dispatch_width
== 16) {
3853 /* R30: interpolated W if not SIMD8. */
3858 if (stage
== MESA_SHADER_FRAGMENT
) {
3859 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3860 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3861 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
3862 /* R31: MSAA position offsets. */
3863 if (prog_data
->uses_pos_offset
) {
3864 payload
.sample_pos_reg
= payload
.num_regs
;
3869 /* R32: MSAA input coverage mask */
3870 if (prog
->SystemValuesRead
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
3871 assert(devinfo
->gen
>= 7);
3872 payload
.sample_mask_in_reg
= payload
.num_regs
;
3874 if (dispatch_width
== 16) {
3875 /* R33: input coverage mask if not SIMD8. */
3880 /* R34-: bary for 32-pixel. */
3881 /* R58-59: interp W for 32-pixel. */
3883 if (prog
->OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
3884 source_depth_to_render_target
= true;
3889 fs_visitor::setup_vs_payload()
3891 /* R0: thread header, R1: urb handles */
3892 payload
.num_regs
= 2;
3896 fs_visitor::setup_cs_payload()
3898 assert(brw
->gen
>= 7);
3900 payload
.num_regs
= 1;
3904 fs_visitor::assign_binding_table_offsets()
3906 assert(stage
== MESA_SHADER_FRAGMENT
);
3907 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
3908 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
3909 uint32_t next_binding_table_offset
= 0;
3911 /* If there are no color regions, we still perform an FB write to a null
3912 * renderbuffer, which we place at surface index 0.
3914 prog_data
->binding_table
.render_target_start
= next_binding_table_offset
;
3915 next_binding_table_offset
+= MAX2(key
->nr_color_regions
, 1);
3917 assign_common_binding_table_offsets(next_binding_table_offset
);
3921 fs_visitor::calculate_register_pressure()
3923 invalidate_live_intervals();
3924 calculate_live_intervals();
3926 unsigned num_instructions
= 0;
3927 foreach_block(block
, cfg
)
3928 num_instructions
+= block
->instructions
.length();
3930 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
3932 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
3933 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
3934 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
3939 fs_visitor::optimize()
3941 split_virtual_grfs();
3943 move_uniform_array_access_to_pull_constants();
3944 assign_constant_locations();
3945 demote_pull_constants();
3947 #define OPT(pass, args...) ({ \
3949 bool this_progress = pass(args); \
3951 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
3952 char filename[64]; \
3953 snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
3954 stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
3956 backend_visitor::dump_instructions(filename); \
3959 progress = progress || this_progress; \
3963 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
3965 snprintf(filename
, 64, "%s%d-%04d-00-start",
3966 stage_abbrev
, dispatch_width
,
3967 shader_prog
? shader_prog
->Name
: 0);
3969 backend_visitor::dump_instructions(filename
);
3980 OPT(remove_duplicate_mrf_writes
);
3984 OPT(opt_copy_propagate
);
3985 OPT(opt_peephole_predicated_break
);
3986 OPT(opt_cmod_propagation
);
3987 OPT(dead_code_eliminate
);
3988 OPT(opt_peephole_sel
);
3989 OPT(dead_control_flow_eliminate
, this);
3990 OPT(opt_register_renaming
);
3991 OPT(opt_redundant_discard_jumps
);
3992 OPT(opt_saturate_propagation
);
3993 OPT(opt_zero_samples
);
3994 OPT(register_coalesce
);
3995 OPT(compute_to_mrf
);
3996 OPT(eliminate_find_live_channel
);
3998 OPT(compact_virtual_grfs
);
4003 OPT(opt_sampler_eot
);
4005 if (OPT(lower_load_payload
)) {
4006 split_virtual_grfs();
4007 OPT(register_coalesce
);
4008 OPT(compute_to_mrf
);
4009 OPT(dead_code_eliminate
);
4012 OPT(opt_combine_constants
);
4014 lower_uniform_pull_constant_loads();
4018 * Three source instruction must have a GRF/MRF destination register.
4019 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4022 fs_visitor::fixup_3src_null_dest()
4024 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4025 if (inst
->is_3src() && inst
->dst
.is_null()) {
4026 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4033 fs_visitor::allocate_registers()
4035 bool allocated_without_spills
;
4037 static const enum instruction_scheduler_mode pre_modes
[] = {
4039 SCHEDULE_PRE_NON_LIFO
,
4043 /* Try each scheduling heuristic to see if it can successfully register
4044 * allocate without spilling. They should be ordered by decreasing
4045 * performance but increasing likelihood of allocating.
4047 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4048 schedule_instructions(pre_modes
[i
]);
4051 assign_regs_trivial();
4052 allocated_without_spills
= true;
4054 allocated_without_spills
= assign_regs(false);
4056 if (allocated_without_spills
)
4060 if (!allocated_without_spills
) {
4061 /* We assume that any spilling is worse than just dropping back to
4062 * SIMD8. There's probably actually some intermediate point where
4063 * SIMD16 with a couple of spills is still better.
4065 if (dispatch_width
== 16) {
4066 fail("Failure to register allocate. Reduce number of "
4067 "live scalar values to avoid this.");
4069 perf_debug("%s shader triggered register spilling. "
4070 "Try reducing the number of live scalar values to "
4071 "improve performance.\n", stage_name
);
4074 /* Since we're out of heuristics, just go spill registers until we
4075 * get an allocation.
4077 while (!assign_regs(true)) {
4083 /* This must come after all optimization and register allocation, since
4084 * it inserts dead code that happens to have side effects, and it does
4085 * so based on the actual physical registers in use.
4087 insert_gen4_send_dependency_workarounds();
4092 if (!allocated_without_spills
)
4093 schedule_instructions(SCHEDULE_POST
);
4095 if (last_scratch
> 0)
4096 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4100 fs_visitor::run_vs()
4102 assert(stage
== MESA_SHADER_VERTEX
);
4104 if (prog_data
->map_entries
== NULL
)
4105 assign_common_binding_table_offsets(0);
4108 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4109 emit_shader_time_begin();
4111 if (brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_VERTEX
].NirOptions
) {
4114 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
4116 this->result
= reg_undef
;
4127 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4128 emit_shader_time_end();
4134 assign_curb_setup();
4135 assign_vs_urb_setup();
4137 fixup_3src_null_dest();
4138 allocate_registers();
4144 fs_visitor::run_fs()
4146 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4147 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
4149 assert(stage
== MESA_SHADER_FRAGMENT
);
4151 sanity_param_count
= prog
->Parameters
->NumParameters
;
4153 if (prog_data
->map_entries
== NULL
)
4154 assign_binding_table_offsets();
4156 if (devinfo
->gen
>= 6)
4157 setup_payload_gen6();
4159 setup_payload_gen4();
4163 } else if (brw
->use_rep_send
&& dispatch_width
== 16) {
4164 emit_repclear_shader();
4166 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4167 emit_shader_time_begin();
4169 calculate_urb_setup();
4170 if (prog
->InputsRead
> 0) {
4171 if (devinfo
->gen
< 6)
4172 emit_interpolation_setup_gen4();
4174 emit_interpolation_setup_gen6();
4177 /* We handle discards by keeping track of the still-live pixels in f0.1.
4178 * Initialize it with the dispatched pixels.
4180 if (wm_prog_data
->uses_kill
) {
4181 fs_inst
*discard_init
= emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
4182 discard_init
->flag_subreg
= 1;
4185 /* Generate FS IR for main(). (the visitor only descends into
4186 * functions called "main").
4188 if (brw
->ctx
.Const
.ShaderCompilerOptions
[MESA_SHADER_FRAGMENT
].NirOptions
) {
4190 } else if (shader
) {
4191 foreach_in_list(ir_instruction
, ir
, shader
->base
.ir
) {
4193 this->result
= reg_undef
;
4197 emit_fragment_program_code();
4203 if (wm_prog_data
->uses_kill
)
4204 emit(FS_OPCODE_PLACEHOLDER_HALT
);
4206 if (wm_key
->alpha_test_func
)
4211 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4212 emit_shader_time_end();
4218 assign_curb_setup();
4221 fixup_3src_null_dest();
4222 allocate_registers();
4228 if (dispatch_width
== 8)
4229 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
4231 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
4233 /* If any state parameters were appended, then ParameterValues could have
4234 * been realloced, in which case the driver uniform storage set up by
4235 * _mesa_associate_uniform_storage() would point to freed memory. Make
4236 * sure that didn't happen.
4238 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4244 fs_visitor::run_cs()
4246 assert(stage
== MESA_SHADER_COMPUTE
);
4249 sanity_param_count
= prog
->Parameters
->NumParameters
;
4251 assign_common_binding_table_offsets(0);
4255 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4256 emit_shader_time_begin();
4263 emit_cs_terminate();
4265 if (INTEL_DEBUG
& DEBUG_SHADER_TIME
)
4266 emit_shader_time_end();
4272 assign_curb_setup();
4274 fixup_3src_null_dest();
4275 allocate_registers();
4280 /* If any state parameters were appended, then ParameterValues could have
4281 * been realloced, in which case the driver uniform storage set up by
4282 * _mesa_associate_uniform_storage() would point to freed memory. Make
4283 * sure that didn't happen.
4285 assert(sanity_param_count
== prog
->Parameters
->NumParameters
);
4291 brw_wm_fs_emit(struct brw_context
*brw
,
4293 const struct brw_wm_prog_key
*key
,
4294 struct brw_wm_prog_data
*prog_data
,
4295 struct gl_fragment_program
*fp
,
4296 struct gl_shader_program
*prog
,
4297 unsigned *final_assembly_size
)
4299 bool start_busy
= false;
4300 double start_time
= 0;
4302 if (unlikely(brw
->perf_debug
)) {
4303 start_busy
= (brw
->batch
.last_bo
&&
4304 drm_intel_bo_busy(brw
->batch
.last_bo
));
4305 start_time
= get_time();
4308 struct brw_shader
*shader
= NULL
;
4310 shader
= (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
4312 if (unlikely(INTEL_DEBUG
& DEBUG_WM
))
4313 brw_dump_ir("fragment", prog
, &shader
->base
, &fp
->Base
);
4315 /* Now the main event: Visit the shader IR and generate our FS IR for it.
4317 fs_visitor
v(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 8);
4320 prog
->LinkStatus
= false;
4321 ralloc_strcat(&prog
->InfoLog
, v
.fail_msg
);
4324 _mesa_problem(NULL
, "Failed to compile fragment shader: %s\n",
4330 cfg_t
*simd16_cfg
= NULL
;
4331 fs_visitor
v2(brw
, mem_ctx
, key
, prog_data
, prog
, fp
, 16);
4332 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || brw
->use_rep_send
)) {
4333 if (!v
.simd16_unsupported
) {
4334 /* Try a SIMD16 compile */
4335 v2
.import_uniforms(&v
);
4337 perf_debug("SIMD16 shader failed to compile, falling back to "
4338 "SIMD8 at a 10-20%% performance cost: %s", v2
.fail_msg
);
4340 simd16_cfg
= v2
.cfg
;
4343 perf_debug("SIMD16 shader unsupported, falling back to "
4344 "SIMD8 at a 10-20%% performance cost: %s", v
.no16_msg
);
4349 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || brw
->no_simd8
;
4350 if ((no_simd8
|| brw
->gen
< 5) && simd16_cfg
) {
4352 prog_data
->no_8
= true;
4355 prog_data
->no_8
= false;
4358 fs_generator
g(brw
, mem_ctx
, (void *) key
, &prog_data
->base
,
4359 &fp
->Base
, v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
4361 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
4364 name
= ralloc_asprintf(mem_ctx
, "%s fragment shader %d",
4365 prog
->Label
? prog
->Label
: "unnamed",
4368 name
= ralloc_asprintf(mem_ctx
, "fragment program %d", fp
->Base
.Id
);
4370 g
.enable_debug(name
);
4374 g
.generate_code(simd8_cfg
, 8);
4376 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
4378 if (unlikely(brw
->perf_debug
) && shader
) {
4379 if (shader
->compiled_once
)
4380 brw_wm_debug_recompile(brw
, prog
, key
);
4381 shader
->compiled_once
= true;
4383 if (start_busy
&& !drm_intel_bo_busy(brw
->batch
.last_bo
)) {
4384 perf_debug("FS compile took %.03f ms and stalled the GPU\n",
4385 (get_time() - start_time
) * 1000);
4389 return g
.get_assembly(final_assembly_size
);
4393 brw_fs_precompile(struct gl_context
*ctx
,
4394 struct gl_shader_program
*shader_prog
,
4395 struct gl_program
*prog
)
4397 struct brw_context
*brw
= brw_context(ctx
);
4398 struct brw_wm_prog_key key
;
4400 struct gl_fragment_program
*fp
= (struct gl_fragment_program
*) prog
;
4401 struct brw_fragment_program
*bfp
= brw_fragment_program(fp
);
4402 bool program_uses_dfdy
= fp
->UsesDFdy
;
4404 memset(&key
, 0, sizeof(key
));
4408 key
.iz_lookup
|= IZ_PS_KILL_ALPHATEST_BIT
;
4410 if (fp
->Base
.OutputsWritten
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
))
4411 key
.iz_lookup
|= IZ_PS_COMPUTES_DEPTH_BIT
;
4413 /* Just assume depth testing. */
4414 key
.iz_lookup
|= IZ_DEPTH_TEST_ENABLE_BIT
;
4415 key
.iz_lookup
|= IZ_DEPTH_WRITE_ENABLE_BIT
;
4418 if (brw
->gen
< 6 || _mesa_bitcount_64(fp
->Base
.InputsRead
&
4419 BRW_FS_VARYING_INPUT_MASK
) > 16)
4420 key
.input_slots_valid
= fp
->Base
.InputsRead
| VARYING_BIT_POS
;
4422 brw_setup_tex_for_precompile(brw
, &key
.tex
, &fp
->Base
);
4424 if (fp
->Base
.InputsRead
& VARYING_BIT_POS
) {
4425 key
.drawable_height
= ctx
->DrawBuffer
->Height
;
4428 key
.nr_color_regions
= _mesa_bitcount_64(fp
->Base
.OutputsWritten
&
4429 ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH
) |
4430 BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
)));
4432 if ((fp
->Base
.InputsRead
& VARYING_BIT_POS
) || program_uses_dfdy
) {
4433 key
.render_to_fbo
= _mesa_is_user_fbo(ctx
->DrawBuffer
) ||
4434 key
.nr_color_regions
> 1;
4437 key
.program_string_id
= bfp
->id
;
4439 uint32_t old_prog_offset
= brw
->wm
.base
.prog_offset
;
4440 struct brw_wm_prog_data
*old_prog_data
= brw
->wm
.prog_data
;
4442 bool success
= brw_codegen_wm_prog(brw
, shader_prog
, bfp
, &key
);
4444 brw
->wm
.base
.prog_offset
= old_prog_offset
;
4445 brw
->wm
.prog_data
= old_prog_data
;
4451 brw_setup_tex_for_precompile(struct brw_context
*brw
,
4452 struct brw_sampler_prog_key_data
*tex
,
4453 struct gl_program
*prog
)
4455 const bool has_shader_channel_select
= brw
->is_haswell
|| brw
->gen
>= 8;
4456 unsigned sampler_count
= _mesa_fls(prog
->SamplersUsed
);
4457 for (unsigned i
= 0; i
< sampler_count
; i
++) {
4458 if (!has_shader_channel_select
&& (prog
->ShadowSamplers
& (1 << i
))) {
4459 /* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
4461 MAKE_SWIZZLE4(SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_X
, SWIZZLE_ONE
);
4463 /* Color sampler: assume no swizzling. */
4464 tex
->swizzles
[i
] = SWIZZLE_XYZW
;