2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "brw_dead_control_flow.h"
48 #include "main/uniforms.h"
49 #include "brw_fs_live_variables.h"
50 #include "glsl/nir/glsl_types.h"
51 #include "program/sampler.h"
56 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
57 const fs_reg
*src
, unsigned sources
)
59 memset(this, 0, sizeof(*this));
61 this->src
= new fs_reg
[MAX2(sources
, 3)];
62 for (unsigned i
= 0; i
< sources
; i
++)
63 this->src
[i
] = src
[i
];
65 this->opcode
= opcode
;
67 this->sources
= sources
;
68 this->exec_size
= exec_size
;
70 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
72 assert(this->exec_size
!= 0);
74 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
76 /* This will be the case for almost all instructions. */
82 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
86 this->regs_written
= 0;
90 unreachable("Invalid destination register file");
92 unreachable("Invalid register file");
95 this->writes_accumulator
= false;
100 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
103 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
105 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
108 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
110 init(opcode
, exec_size
, dst
, NULL
, 0);
113 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
116 const fs_reg src
[1] = { src0
};
117 init(opcode
, exec_size
, dst
, src
, 1);
120 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
121 const fs_reg
&src0
, const fs_reg
&src1
)
123 const fs_reg src
[2] = { src0
, src1
};
124 init(opcode
, exec_size
, dst
, src
, 2);
127 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
128 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
130 const fs_reg src
[3] = { src0
, src1
, src2
};
131 init(opcode
, exec_size
, dst
, src
, 3);
134 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
135 const fs_reg src
[], unsigned sources
)
137 init(opcode
, exec_width
, dst
, src
, sources
);
140 fs_inst::fs_inst(const fs_inst
&that
)
142 memcpy(this, &that
, sizeof(that
));
144 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
146 for (unsigned i
= 0; i
< that
.sources
; i
++)
147 this->src
[i
] = that
.src
[i
];
156 fs_inst::resize_sources(uint8_t num_sources
)
158 if (this->sources
!= num_sources
) {
159 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
161 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
162 src
[i
] = this->src
[i
];
166 this->sources
= num_sources
;
171 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
173 const fs_reg
&surf_index
,
174 const fs_reg
&varying_offset
,
175 uint32_t const_offset
)
177 /* We have our constant surface use a pitch of 4 bytes, so our index can
178 * be any component of a vector, and then we load 4 contiguous
179 * components starting from that.
181 * We break down the const_offset to a portion added to the variable
182 * offset and a portion done using reg_offset, which means that if you
183 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
184 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
185 * CSE can later notice that those loads are all the same and eliminate
186 * the redundant ones.
188 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
189 bld
.ADD(vec4_offset
, varying_offset
, fs_reg(const_offset
& ~3));
192 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
193 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
194 * u, v, r) as parameters, or we can just use the SIMD16 message
195 * consisting of (header, u). We choose the second, at the cost of a
196 * longer return length.
202 if (devinfo
->gen
>= 7)
203 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
207 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
208 fs_reg vec4_result
= fs_reg(GRF
, alloc
.allocate(regs_written
), dst
.type
);
209 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
210 inst
->regs_written
= regs_written
;
212 if (devinfo
->gen
< 7) {
213 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
214 inst
->header_size
= 1;
215 if (devinfo
->gen
== 4)
218 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
221 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
225 * A helper for MOV generation for fixing up broken hardware SEND dependency
229 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
231 /* The caller always wants uncompressed to emit the minimal extra
232 * dependencies, and to avoid having to deal with aligning its regs to 2.
234 const fs_builder ubld
= bld
.annotate("send dependency resolve")
237 ubld
.MOV(ubld
.null_reg_f(), fs_reg(GRF
, grf
, BRW_REGISTER_TYPE_F
));
241 fs_inst::equals(fs_inst
*inst
) const
243 return (opcode
== inst
->opcode
&&
244 dst
.equals(inst
->dst
) &&
245 src
[0].equals(inst
->src
[0]) &&
246 src
[1].equals(inst
->src
[1]) &&
247 src
[2].equals(inst
->src
[2]) &&
248 saturate
== inst
->saturate
&&
249 predicate
== inst
->predicate
&&
250 conditional_mod
== inst
->conditional_mod
&&
251 mlen
== inst
->mlen
&&
252 base_mrf
== inst
->base_mrf
&&
253 target
== inst
->target
&&
255 header_size
== inst
->header_size
&&
256 shadow_compare
== inst
->shadow_compare
&&
257 exec_size
== inst
->exec_size
&&
258 offset
== inst
->offset
);
262 fs_inst::overwrites_reg(const fs_reg
®
) const
264 return reg
.in_range(dst
, regs_written
);
268 fs_inst::is_send_from_grf() const
271 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
272 case SHADER_OPCODE_SHADER_TIME_ADD
:
273 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
274 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
275 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
276 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
277 case SHADER_OPCODE_UNTYPED_ATOMIC
:
278 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
279 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
280 case SHADER_OPCODE_TYPED_ATOMIC
:
281 case SHADER_OPCODE_TYPED_SURFACE_READ
:
282 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
283 case SHADER_OPCODE_URB_WRITE_SIMD8
:
285 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
286 return src
[1].file
== GRF
;
287 case FS_OPCODE_FB_WRITE
:
288 return src
[0].file
== GRF
;
291 return src
[0].file
== GRF
;
298 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
300 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
303 fs_reg reg
= this->src
[0];
304 if (reg
.file
!= GRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
307 if (grf_alloc
.sizes
[reg
.reg
] != this->regs_written
)
310 for (int i
= 0; i
< this->sources
; i
++) {
311 reg
.type
= this->src
[i
].type
;
312 if (!this->src
[i
].equals(reg
))
315 if (i
< this->header_size
) {
318 reg
.reg_offset
+= this->exec_size
/ 8;
326 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
328 if (devinfo
->gen
== 6 && is_math())
331 if (is_send_from_grf())
334 if (!backend_instruction::can_do_source_mods())
341 fs_inst::can_change_types() const
343 return dst
.type
== src
[0].type
&&
344 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
345 (opcode
== BRW_OPCODE_MOV
||
346 (opcode
== BRW_OPCODE_SEL
&&
347 dst
.type
== src
[1].type
&&
348 predicate
!= BRW_PREDICATE_NONE
&&
349 !src
[1].abs
&& !src
[1].negate
));
353 fs_inst::has_side_effects() const
355 return this->eot
|| backend_instruction::has_side_effects();
361 memset(this, 0, sizeof(*this));
365 /** Generic unset register constructor. */
369 this->file
= BAD_FILE
;
372 /** Immediate value constructor. */
373 fs_reg::fs_reg(float f
)
377 this->type
= BRW_REGISTER_TYPE_F
;
379 this->fixed_hw_reg
.dw1
.f
= f
;
382 /** Immediate value constructor. */
383 fs_reg::fs_reg(int32_t i
)
387 this->type
= BRW_REGISTER_TYPE_D
;
389 this->fixed_hw_reg
.dw1
.d
= i
;
392 /** Immediate value constructor. */
393 fs_reg::fs_reg(uint32_t u
)
397 this->type
= BRW_REGISTER_TYPE_UD
;
399 this->fixed_hw_reg
.dw1
.ud
= u
;
402 /** Vector float immediate value constructor. */
403 fs_reg::fs_reg(uint8_t vf
[4])
407 this->type
= BRW_REGISTER_TYPE_VF
;
408 memcpy(&this->fixed_hw_reg
.dw1
.ud
, vf
, sizeof(unsigned));
411 /** Vector float immediate value constructor. */
412 fs_reg::fs_reg(uint8_t vf0
, uint8_t vf1
, uint8_t vf2
, uint8_t vf3
)
416 this->type
= BRW_REGISTER_TYPE_VF
;
417 this->fixed_hw_reg
.dw1
.ud
= (vf0
<< 0) |
423 /** Fixed brw_reg. */
424 fs_reg::fs_reg(struct brw_reg fixed_hw_reg
)
428 this->fixed_hw_reg
= fixed_hw_reg
;
429 this->type
= fixed_hw_reg
.type
;
433 fs_reg::equals(const fs_reg
&r
) const
435 return (file
== r
.file
&&
437 reg_offset
== r
.reg_offset
&&
438 subreg_offset
== r
.subreg_offset
&&
440 negate
== r
.negate
&&
442 !reladdr
&& !r
.reladdr
&&
443 ((file
!= HW_REG
&& file
!= IMM
) ||
444 memcmp(&fixed_hw_reg
, &r
.fixed_hw_reg
,
445 sizeof(fixed_hw_reg
)) == 0) &&
450 fs_reg::set_smear(unsigned subreg
)
452 assert(file
!= HW_REG
&& file
!= IMM
);
453 subreg_offset
= subreg
* type_sz(type
);
459 fs_reg::is_contiguous() const
465 fs_reg::component_size(unsigned width
) const
467 const unsigned stride
= (file
!= HW_REG
? this->stride
:
468 fixed_hw_reg
.hstride
== 0 ? 0 :
469 1 << (fixed_hw_reg
.hstride
- 1));
470 return MAX2(width
* stride
, 1) * type_sz(type
);
474 type_size_scalar(const struct glsl_type
*type
)
476 unsigned int size
, i
;
478 switch (type
->base_type
) {
481 case GLSL_TYPE_FLOAT
:
483 return type
->components();
484 case GLSL_TYPE_ARRAY
:
485 return type_size_scalar(type
->fields
.array
) * type
->length
;
486 case GLSL_TYPE_STRUCT
:
488 for (i
= 0; i
< type
->length
; i
++) {
489 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
492 case GLSL_TYPE_SAMPLER
:
493 /* Samplers take up no register space, since they're baked in at
497 case GLSL_TYPE_ATOMIC_UINT
:
499 case GLSL_TYPE_SUBROUTINE
:
501 case GLSL_TYPE_IMAGE
:
502 return BRW_IMAGE_PARAM_SIZE
;
504 case GLSL_TYPE_ERROR
:
505 case GLSL_TYPE_INTERFACE
:
506 case GLSL_TYPE_DOUBLE
:
507 unreachable("not reached");
514 * Create a MOV to read the timestamp register.
516 * The caller is responsible for emitting the MOV. The return value is
517 * the destination of the MOV, with extra parameters set.
520 fs_visitor::get_timestamp(const fs_builder
&bld
)
522 assert(devinfo
->gen
>= 7);
524 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
527 BRW_REGISTER_TYPE_UD
));
529 fs_reg dst
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
531 /* We want to read the 3 fields we care about even if it's not enabled in
534 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
536 /* The caller wants the low 32 bits of the timestamp. Since it's running
537 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
538 * which is plenty of time for our purposes. It is identical across the
539 * EUs, but since it's tracking GPU core speed it will increment at a
540 * varying rate as render P-states change.
542 * The caller could also check if render P-states have changed (or anything
543 * else that might disrupt timing) by setting smear to 2 and checking if
544 * that field is != 0.
552 fs_visitor::emit_shader_time_begin()
554 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
558 fs_visitor::emit_shader_time_end()
560 /* Insert our code just before the final SEND with EOT. */
561 exec_node
*end
= this->instructions
.get_tail();
562 assert(end
&& ((fs_inst
*) end
)->eot
);
563 const fs_builder ibld
= bld
.annotate("shader time end")
564 .exec_all().at(NULL
, end
);
566 fs_reg shader_end_time
= get_timestamp(ibld
);
568 /* Check that there weren't any timestamp reset events (assuming these
569 * were the only two timestamp reads that happened).
571 fs_reg reset
= shader_end_time
;
573 set_condmod(BRW_CONDITIONAL_Z
,
574 ibld
.AND(ibld
.null_reg_ud(), reset
, fs_reg(1u)));
575 ibld
.IF(BRW_PREDICATE_NORMAL
);
577 fs_reg start
= shader_start_time
;
579 fs_reg diff
= fs_reg(GRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
582 const fs_builder cbld
= ibld
.group(1, 0);
583 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
585 /* If there were no instructions between the two timestamp gets, the diff
586 * is 2 cycles. Remove that overhead, so I can forget about that when
587 * trying to determine the time taken for single instructions.
589 cbld
.ADD(diff
, diff
, fs_reg(-2u));
590 SHADER_TIME_ADD(cbld
, 0, diff
);
591 SHADER_TIME_ADD(cbld
, 1, fs_reg(1u));
592 ibld
.emit(BRW_OPCODE_ELSE
);
593 SHADER_TIME_ADD(cbld
, 2, fs_reg(1u));
594 ibld
.emit(BRW_OPCODE_ENDIF
);
598 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
599 int shader_time_subindex
,
602 int index
= shader_time_index
* 3 + shader_time_subindex
;
603 fs_reg offset
= fs_reg(index
* SHADER_TIME_STRIDE
);
606 if (dispatch_width
== 8)
607 payload
= vgrf(glsl_type::uvec2_type
);
609 payload
= vgrf(glsl_type::uint_type
);
611 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
615 fs_visitor::vfail(const char *format
, va_list va
)
624 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
625 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
627 this->fail_msg
= msg
;
630 fprintf(stderr
, "%s", msg
);
635 fs_visitor::fail(const char *format
, ...)
639 va_start(va
, format
);
645 * Mark this program as impossible to compile in SIMD16 mode.
647 * During the SIMD8 compile (which happens first), we can detect and flag
648 * things that are unsupported in SIMD16 mode, so the compiler can skip
649 * the SIMD16 compile altogether.
651 * During a SIMD16 compile (if one happens anyway), this just calls fail().
654 fs_visitor::no16(const char *msg
)
656 if (dispatch_width
== 16) {
659 simd16_unsupported
= true;
661 compiler
->shader_perf_log(log_data
,
662 "SIMD16 shader failed to compile: %s", msg
);
667 * Returns true if the instruction has a flag that means it won't
668 * update an entire destination register.
670 * For example, dead code elimination and live variable analysis want to know
671 * when a write to a variable screens off any preceding values that were in
675 fs_inst::is_partial_write() const
677 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
678 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
679 !this->dst
.is_contiguous());
683 fs_inst::components_read(unsigned i
) const
686 case FS_OPCODE_LINTERP
:
692 case FS_OPCODE_PIXEL_X
:
693 case FS_OPCODE_PIXEL_Y
:
697 case FS_OPCODE_FB_WRITE_LOGICAL
:
698 assert(src
[6].file
== IMM
);
699 /* First/second FB write color. */
701 return src
[6].fixed_hw_reg
.dw1
.ud
;
705 case SHADER_OPCODE_TEX_LOGICAL
:
706 case SHADER_OPCODE_TXD_LOGICAL
:
707 case SHADER_OPCODE_TXF_LOGICAL
:
708 case SHADER_OPCODE_TXL_LOGICAL
:
709 case SHADER_OPCODE_TXS_LOGICAL
:
710 case FS_OPCODE_TXB_LOGICAL
:
711 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
712 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
713 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
714 case SHADER_OPCODE_LOD_LOGICAL
:
715 case SHADER_OPCODE_TG4_LOGICAL
:
716 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
717 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
718 /* Texture coordinates. */
720 return src
[8].fixed_hw_reg
.dw1
.ud
;
721 /* Texture derivatives. */
722 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
723 return src
[9].fixed_hw_reg
.dw1
.ud
;
724 /* Texture offset. */
730 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
731 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
732 assert(src
[3].file
== IMM
);
733 /* Surface coordinates. */
735 return src
[3].fixed_hw_reg
.dw1
.ud
;
736 /* Surface operation source (ignored for reads). */
742 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
743 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
744 assert(src
[3].file
== IMM
&&
746 /* Surface coordinates. */
748 return src
[3].fixed_hw_reg
.dw1
.ud
;
749 /* Surface operation source. */
751 return src
[4].fixed_hw_reg
.dw1
.ud
;
755 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
756 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
757 assert(src
[3].file
== IMM
&&
759 const unsigned op
= src
[4].fixed_hw_reg
.dw1
.ud
;
760 /* Surface coordinates. */
762 return src
[3].fixed_hw_reg
.dw1
.ud
;
763 /* Surface operation source. */
764 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
766 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
767 op
== BRW_AOP_PREDEC
))
779 fs_inst::regs_read(int arg
) const
782 case FS_OPCODE_FB_WRITE
:
783 case SHADER_OPCODE_URB_WRITE_SIMD8
:
784 case SHADER_OPCODE_UNTYPED_ATOMIC
:
785 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
786 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
787 case SHADER_OPCODE_TYPED_ATOMIC
:
788 case SHADER_OPCODE_TYPED_SURFACE_READ
:
789 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
790 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
795 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
796 /* The payload is actually stored in src1 */
801 case FS_OPCODE_LINTERP
:
806 case SHADER_OPCODE_LOAD_PAYLOAD
:
807 if (arg
< this->header_size
)
811 case CS_OPCODE_CS_TERMINATE
:
812 case SHADER_OPCODE_BARRIER
:
816 if (is_tex() && arg
== 0 && src
[0].file
== GRF
)
821 switch (src
[arg
].file
) {
830 return DIV_ROUND_UP(components_read(arg
) *
831 src
[arg
].component_size(exec_size
),
834 unreachable("MRF registers are not allowed as sources");
836 unreachable("Invalid register file");
841 fs_inst::reads_flag() const
847 fs_inst::writes_flag() const
849 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
850 opcode
!= BRW_OPCODE_IF
&&
851 opcode
!= BRW_OPCODE_WHILE
)) ||
852 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
856 * Returns how many MRFs an FS opcode will write over.
858 * Note that this is not the 0 or 1 implied writes in an actual gen
859 * instruction -- the FS opcodes often generate MOVs in addition.
862 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
867 if (inst
->base_mrf
== -1)
870 switch (inst
->opcode
) {
871 case SHADER_OPCODE_RCP
:
872 case SHADER_OPCODE_RSQ
:
873 case SHADER_OPCODE_SQRT
:
874 case SHADER_OPCODE_EXP2
:
875 case SHADER_OPCODE_LOG2
:
876 case SHADER_OPCODE_SIN
:
877 case SHADER_OPCODE_COS
:
878 return 1 * dispatch_width
/ 8;
879 case SHADER_OPCODE_POW
:
880 case SHADER_OPCODE_INT_QUOTIENT
:
881 case SHADER_OPCODE_INT_REMAINDER
:
882 return 2 * dispatch_width
/ 8;
883 case SHADER_OPCODE_TEX
:
885 case SHADER_OPCODE_TXD
:
886 case SHADER_OPCODE_TXF
:
887 case SHADER_OPCODE_TXF_CMS
:
888 case SHADER_OPCODE_TXF_MCS
:
889 case SHADER_OPCODE_TG4
:
890 case SHADER_OPCODE_TG4_OFFSET
:
891 case SHADER_OPCODE_TXL
:
892 case SHADER_OPCODE_TXS
:
893 case SHADER_OPCODE_LOD
:
894 case SHADER_OPCODE_SAMPLEINFO
:
896 case FS_OPCODE_FB_WRITE
:
898 case FS_OPCODE_GET_BUFFER_SIZE
:
899 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
900 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
902 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
904 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
906 case SHADER_OPCODE_UNTYPED_ATOMIC
:
907 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
908 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
909 case SHADER_OPCODE_TYPED_ATOMIC
:
910 case SHADER_OPCODE_TYPED_SURFACE_READ
:
911 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
912 case SHADER_OPCODE_URB_WRITE_SIMD8
:
913 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
914 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
915 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
916 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
919 unreachable("not reached");
924 fs_visitor::vgrf(const glsl_type
*const type
)
926 int reg_width
= dispatch_width
/ 8;
927 return fs_reg(GRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
928 brw_type_for_base_type(type
));
931 /** Fixed HW reg constructor. */
932 fs_reg::fs_reg(enum register_file file
, int reg
)
937 this->type
= BRW_REGISTER_TYPE_F
;
938 this->stride
= (file
== UNIFORM
? 0 : 1);
941 /** Fixed HW reg constructor. */
942 fs_reg::fs_reg(enum register_file file
, int reg
, enum brw_reg_type type
)
948 this->stride
= (file
== UNIFORM
? 0 : 1);
951 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
952 * This brings in those uniform definitions
955 fs_visitor::import_uniforms(fs_visitor
*v
)
957 this->push_constant_loc
= v
->push_constant_loc
;
958 this->pull_constant_loc
= v
->pull_constant_loc
;
959 this->uniforms
= v
->uniforms
;
960 this->param_size
= v
->param_size
;
964 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
965 bool origin_upper_left
)
967 assert(stage
== MESA_SHADER_FRAGMENT
);
968 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
969 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
971 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
974 if (pixel_center_integer
) {
975 bld
.MOV(wpos
, this->pixel_x
);
977 bld
.ADD(wpos
, this->pixel_x
, fs_reg(0.5f
));
979 wpos
= offset(wpos
, bld
, 1);
982 if (!flip
&& pixel_center_integer
) {
983 bld
.MOV(wpos
, this->pixel_y
);
985 fs_reg pixel_y
= this->pixel_y
;
986 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
989 pixel_y
.negate
= true;
990 offset
+= key
->drawable_height
- 1.0f
;
993 bld
.ADD(wpos
, pixel_y
, fs_reg(offset
));
995 wpos
= offset(wpos
, bld
, 1);
998 if (devinfo
->gen
>= 6) {
999 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1001 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1002 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1003 interp_reg(VARYING_SLOT_POS
, 2));
1005 wpos
= offset(wpos
, bld
, 1);
1007 /* gl_FragCoord.w: Already set up in emit_interpolation */
1008 bld
.MOV(wpos
, this->wpos_w
);
1014 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1015 glsl_interp_qualifier interpolation_mode
,
1016 bool is_centroid
, bool is_sample
)
1018 brw_wm_barycentric_interp_mode barycoord_mode
;
1019 if (devinfo
->gen
>= 6) {
1021 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1022 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1024 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1025 } else if (is_sample
) {
1026 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1027 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1029 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1031 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1032 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1034 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1037 /* On Ironlake and below, there is only one interpolation mode.
1038 * Centroid interpolation doesn't mean anything on this hardware --
1039 * there is no multisampling.
1041 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1043 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1044 this->delta_xy
[barycoord_mode
], interp
);
1048 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1049 const glsl_type
*type
,
1050 glsl_interp_qualifier interpolation_mode
,
1051 int location
, bool mod_centroid
,
1054 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1056 assert(stage
== MESA_SHADER_FRAGMENT
);
1057 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1058 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1060 unsigned int array_elements
;
1062 if (type
->is_array()) {
1063 array_elements
= type
->arrays_of_arrays_size();
1064 if (array_elements
== 0) {
1065 fail("dereferenced array '%s' has length 0\n", name
);
1067 type
= type
->without_array();
1072 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1074 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1075 if (key
->flat_shade
&& is_gl_Color
) {
1076 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1078 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1082 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1083 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1084 if (prog_data
->urb_setup
[location
] == -1) {
1085 /* If there's no incoming setup data for this slot, don't
1086 * emit interpolation for it.
1088 attr
= offset(attr
, bld
, type
->vector_elements
);
1093 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1094 /* Constant interpolation (flat shading) case. The SF has
1095 * handed us defined values in only the constant offset
1096 * field of the setup reg.
1098 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1099 struct brw_reg interp
= interp_reg(location
, k
);
1100 interp
= suboffset(interp
, 3);
1101 interp
.type
= attr
.type
;
1102 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1103 attr
= offset(attr
, bld
, 1);
1106 /* Smooth/noperspective interpolation case. */
1107 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1108 struct brw_reg interp
= interp_reg(location
, k
);
1109 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1110 /* Get the pixel/sample mask into f0 so that we know
1111 * which pixels are lit. Then, for each channel that is
1112 * unlit, replace the centroid data with non-centroid
1115 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1118 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1120 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1121 inst
->predicate_inverse
= true;
1122 if (devinfo
->has_pln
)
1123 inst
->no_dd_clear
= true;
1125 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1126 mod_centroid
&& !key
->persample_shading
,
1127 mod_sample
|| key
->persample_shading
);
1128 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1129 inst
->predicate_inverse
= false;
1130 if (devinfo
->has_pln
)
1131 inst
->no_dd_check
= true;
1134 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1135 mod_centroid
&& !key
->persample_shading
,
1136 mod_sample
|| key
->persample_shading
);
1138 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1139 bld
.MUL(attr
, attr
, this->pixel_w
);
1141 attr
= offset(attr
, bld
, 1);
1151 fs_visitor::emit_frontfacing_interpolation()
1153 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1155 if (devinfo
->gen
>= 6) {
1156 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1157 * a boolean result from this (~0/true or 0/false).
1159 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1160 * this task in only one instruction:
1161 * - a negation source modifier will flip the bit; and
1162 * - a W -> D type conversion will sign extend the bit into the high
1163 * word of the destination.
1165 * An ASR 15 fills the low word of the destination.
1167 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1170 bld
.ASR(*reg
, g0
, fs_reg(15));
1172 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1173 * a boolean result from this (1/true or 0/false).
1175 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1176 * the negation source modifier to flip it. Unfortunately the SHR
1177 * instruction only operates on UD (or D with an abs source modifier)
1178 * sources without negation.
1180 * Instead, use ASR (which will give ~0/true or 0/false).
1182 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1185 bld
.ASR(*reg
, g1_6
, fs_reg(31));
1192 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1194 assert(stage
== MESA_SHADER_FRAGMENT
);
1195 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1196 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1198 if (key
->compute_pos_offset
) {
1199 /* Convert int_sample_pos to floating point */
1200 bld
.MOV(dst
, int_sample_pos
);
1201 /* Scale to the range [0, 1] */
1202 bld
.MUL(dst
, dst
, fs_reg(1 / 16.0f
));
1205 /* From ARB_sample_shading specification:
1206 * "When rendering to a non-multisample buffer, or if multisample
1207 * rasterization is disabled, gl_SamplePosition will always be
1210 bld
.MOV(dst
, fs_reg(0.5f
));
1215 fs_visitor::emit_samplepos_setup()
1217 assert(devinfo
->gen
>= 6);
1219 const fs_builder abld
= bld
.annotate("compute sample position");
1220 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1222 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1223 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1225 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1226 * mode will be enabled.
1228 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1229 * R31.1:0 Position Offset X/Y for Slot[3:0]
1230 * R31.3:2 Position Offset X/Y for Slot[7:4]
1233 * The X, Y sample positions come in as bytes in thread payload. So, read
1234 * the positions using vstride=16, width=8, hstride=2.
1236 struct brw_reg sample_pos_reg
=
1237 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1238 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1240 if (dispatch_width
== 8) {
1241 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1243 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1244 abld
.half(1).MOV(half(int_sample_x
, 1),
1245 fs_reg(suboffset(sample_pos_reg
, 16)));
1247 /* Compute gl_SamplePosition.x */
1248 compute_sample_position(pos
, int_sample_x
);
1249 pos
= offset(pos
, abld
, 1);
1250 if (dispatch_width
== 8) {
1251 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1253 abld
.half(0).MOV(half(int_sample_y
, 0),
1254 fs_reg(suboffset(sample_pos_reg
, 1)));
1255 abld
.half(1).MOV(half(int_sample_y
, 1),
1256 fs_reg(suboffset(sample_pos_reg
, 17)));
1258 /* Compute gl_SamplePosition.y */
1259 compute_sample_position(pos
, int_sample_y
);
1264 fs_visitor::emit_sampleid_setup()
1266 assert(stage
== MESA_SHADER_FRAGMENT
);
1267 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1268 assert(devinfo
->gen
>= 6);
1270 const fs_builder abld
= bld
.annotate("compute sample id");
1271 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1273 if (key
->compute_sample_id
) {
1274 fs_reg t1
= vgrf(glsl_type::int_type
);
1275 fs_reg t2
= vgrf(glsl_type::int_type
);
1276 t2
.type
= BRW_REGISTER_TYPE_UW
;
1278 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1279 * 8x multisampling, subspan 0 will represent sample N (where N
1280 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1281 * 7. We can find the value of N by looking at R0.0 bits 7:6
1282 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1283 * (since samples are always delivered in pairs). That is, we
1284 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1285 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1286 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1287 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1288 * populating a temporary variable with the sequence (0, 1, 2, 3),
1289 * and then reading from it using vstride=1, width=4, hstride=0.
1290 * These computations hold good for 4x multisampling as well.
1292 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1293 * the first four slots are sample 0 of subspan 0; the next four
1294 * are sample 1 of subspan 0; the third group is sample 0 of
1295 * subspan 1, and finally sample 1 of subspan 1.
1298 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
1300 abld
.exec_all().SHR(t1
, t1
, fs_reg(5));
1302 /* This works for both SIMD8 and SIMD16 */
1304 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1306 /* This special instruction takes care of setting vstride=1,
1307 * width=4, hstride=0 of t2 during an ADD instruction.
1309 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1311 /* As per GL_ARB_sample_shading specification:
1312 * "When rendering to a non-multisample buffer, or if multisample
1313 * rasterization is disabled, gl_SampleID will always be zero."
1315 abld
.MOV(*reg
, fs_reg(0));
1322 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1324 if (!src
.abs
&& !src
.negate
)
1327 fs_reg temp
= bld
.vgrf(src
.type
);
1334 fs_visitor::emit_discard_jump()
1336 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1338 /* For performance, after a discard, jump to the end of the
1339 * shader if all relevant channels have been discarded.
1341 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1342 discard_jump
->flag_subreg
= 1;
1344 discard_jump
->predicate
= (dispatch_width
== 8)
1345 ? BRW_PREDICATE_ALIGN1_ANY8H
1346 : BRW_PREDICATE_ALIGN1_ANY16H
;
1347 discard_jump
->predicate_inverse
= true;
1351 fs_visitor::assign_curb_setup()
1353 if (dispatch_width
== 8) {
1354 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1356 if (stage
== MESA_SHADER_FRAGMENT
) {
1357 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1358 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1359 } else if (stage
== MESA_SHADER_COMPUTE
) {
1360 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1361 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1363 unreachable("Unsupported shader type!");
1367 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1369 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1370 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1371 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1372 if (inst
->src
[i
].file
== UNIFORM
) {
1373 int uniform_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1375 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1376 constant_nr
= push_constant_loc
[uniform_nr
];
1378 /* Section 5.11 of the OpenGL 4.1 spec says:
1379 * "Out-of-bounds reads return undefined values, which include
1380 * values from other variables of the active program or zero."
1381 * Just return the first push constant.
1386 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1390 assert(inst
->src
[i
].stride
== 0);
1391 inst
->src
[i
].file
= HW_REG
;
1392 inst
->src
[i
].fixed_hw_reg
= byte_offset(
1393 retype(brw_reg
, inst
->src
[i
].type
),
1394 inst
->src
[i
].subreg_offset
);
1399 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1400 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1404 fs_visitor::calculate_urb_setup()
1406 assert(stage
== MESA_SHADER_FRAGMENT
);
1407 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1408 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1410 memset(prog_data
->urb_setup
, -1,
1411 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1414 /* Figure out where each of the incoming setup attributes lands. */
1415 if (devinfo
->gen
>= 6) {
1416 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1417 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1418 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1419 * first 16 varying inputs, so we can put them wherever we want.
1420 * Just put them in order.
1422 * This is useful because it means that (a) inputs not used by the
1423 * fragment shader won't take up valuable register space, and (b) we
1424 * won't have to recompile the fragment shader if it gets paired with
1425 * a different vertex (or geometry) shader.
1427 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1428 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1429 BITFIELD64_BIT(i
)) {
1430 prog_data
->urb_setup
[i
] = urb_next
++;
1434 /* We have enough input varyings that the SF/SBE pipeline stage can't
1435 * arbitrarily rearrange them to suit our whim; we have to put them
1436 * in an order that matches the output of the previous pipeline stage
1437 * (geometry or vertex shader).
1439 struct brw_vue_map prev_stage_vue_map
;
1440 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1441 key
->input_slots_valid
,
1442 nir
->info
.separate_shader
);
1443 int first_slot
= 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1444 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1445 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1447 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1448 /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
1451 if (varying
!= BRW_VARYING_SLOT_COUNT
&&
1452 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1453 BITFIELD64_BIT(varying
))) {
1454 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1457 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1460 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1461 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1462 /* Point size is packed into the header, not as a general attribute */
1463 if (i
== VARYING_SLOT_PSIZ
)
1466 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1467 /* The back color slot is skipped when the front color is
1468 * also written to. In addition, some slots can be
1469 * written in the vertex shader and not read in the
1470 * fragment shader. So the register number must always be
1471 * incremented, mapped or not.
1473 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1474 prog_data
->urb_setup
[i
] = urb_next
;
1480 * It's a FS only attribute, and we did interpolation for this attribute
1481 * in SF thread. So, count it here, too.
1483 * See compile_sf_prog() for more info.
1485 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1486 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1489 prog_data
->num_varying_inputs
= urb_next
;
1493 fs_visitor::assign_urb_setup()
1495 assert(stage
== MESA_SHADER_FRAGMENT
);
1496 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1498 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1500 /* Offset all the urb_setup[] index by the actual position of the
1501 * setup regs, now that the location of the constants has been chosen.
1503 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1504 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1505 assert(inst
->src
[1].file
== HW_REG
);
1506 inst
->src
[1].fixed_hw_reg
.nr
+= urb_start
;
1509 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1510 assert(inst
->src
[0].file
== HW_REG
);
1511 inst
->src
[0].fixed_hw_reg
.nr
+= urb_start
;
1515 /* Each attribute is 4 setup channels, each of which is half a reg. */
1516 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1520 fs_visitor::assign_vs_urb_setup()
1522 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1524 assert(stage
== MESA_SHADER_VERTEX
);
1525 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1526 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1529 /* Each attribute is 4 regs. */
1530 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1532 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1534 /* Rewrite all ATTR file references to the hw grf that they land in. */
1535 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1536 for (int i
= 0; i
< inst
->sources
; i
++) {
1537 if (inst
->src
[i
].file
== ATTR
) {
1538 int grf
= payload
.num_regs
+
1539 prog_data
->curb_read_length
+
1541 inst
->src
[i
].reg_offset
;
1543 inst
->src
[i
].file
= HW_REG
;
1544 inst
->src
[i
].fixed_hw_reg
=
1545 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1546 inst
->src
[i
].subreg_offset
),
1547 inst
->exec_size
* inst
->src
[i
].stride
,
1548 inst
->exec_size
, inst
->src
[i
].stride
);
1555 * Split large virtual GRFs into separate components if we can.
1557 * This is mostly duplicated with what brw_fs_vector_splitting does,
1558 * but that's really conservative because it's afraid of doing
1559 * splitting that doesn't result in real progress after the rest of
1560 * the optimization phases, which would cause infinite looping in
1561 * optimization. We can do it once here, safely. This also has the
1562 * opportunity to split interpolated values, or maybe even uniforms,
1563 * which we don't have at the IR level.
1565 * We want to split, because virtual GRFs are what we register
1566 * allocate and spill (due to contiguousness requirements for some
1567 * instructions), and they're what we naturally generate in the
1568 * codegen process, but most virtual GRFs don't actually need to be
1569 * contiguous sets of GRFs. If we split, we'll end up with reduced
1570 * live intervals and better dead code elimination and coalescing.
1573 fs_visitor::split_virtual_grfs()
1575 int num_vars
= this->alloc
.count
;
1577 /* Count the total number of registers */
1579 int vgrf_to_reg
[num_vars
];
1580 for (int i
= 0; i
< num_vars
; i
++) {
1581 vgrf_to_reg
[i
] = reg_count
;
1582 reg_count
+= alloc
.sizes
[i
];
1585 /* An array of "split points". For each register slot, this indicates
1586 * if this slot can be separated from the previous slot. Every time an
1587 * instruction uses multiple elements of a register (as a source or
1588 * destination), we mark the used slots as inseparable. Then we go
1589 * through and split the registers into the smallest pieces we can.
1591 bool split_points
[reg_count
];
1592 memset(split_points
, 0, sizeof(split_points
));
1594 /* Mark all used registers as fully splittable */
1595 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1596 if (inst
->dst
.file
== GRF
) {
1597 int reg
= vgrf_to_reg
[inst
->dst
.reg
];
1598 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.reg
]; j
++)
1599 split_points
[reg
+ j
] = true;
1602 for (int i
= 0; i
< inst
->sources
; i
++) {
1603 if (inst
->src
[i
].file
== GRF
) {
1604 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
];
1605 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].reg
]; j
++)
1606 split_points
[reg
+ j
] = true;
1611 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1612 if (inst
->dst
.file
== GRF
) {
1613 int reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1614 for (int j
= 1; j
< inst
->regs_written
; j
++)
1615 split_points
[reg
+ j
] = false;
1617 for (int i
= 0; i
< inst
->sources
; i
++) {
1618 if (inst
->src
[i
].file
== GRF
) {
1619 int reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1620 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1621 split_points
[reg
+ j
] = false;
1626 int new_virtual_grf
[reg_count
];
1627 int new_reg_offset
[reg_count
];
1630 for (int i
= 0; i
< num_vars
; i
++) {
1631 /* The first one should always be 0 as a quick sanity check. */
1632 assert(split_points
[reg
] == false);
1635 new_reg_offset
[reg
] = 0;
1640 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1641 /* If this is a split point, reset the offset to 0 and allocate a
1642 * new virtual GRF for the previous offset many registers
1644 if (split_points
[reg
]) {
1645 assert(offset
<= MAX_VGRF_SIZE
);
1646 int grf
= alloc
.allocate(offset
);
1647 for (int k
= reg
- offset
; k
< reg
; k
++)
1648 new_virtual_grf
[k
] = grf
;
1651 new_reg_offset
[reg
] = offset
;
1656 /* The last one gets the original register number */
1657 assert(offset
<= MAX_VGRF_SIZE
);
1658 alloc
.sizes
[i
] = offset
;
1659 for (int k
= reg
- offset
; k
< reg
; k
++)
1660 new_virtual_grf
[k
] = i
;
1662 assert(reg
== reg_count
);
1664 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1665 if (inst
->dst
.file
== GRF
) {
1666 reg
= vgrf_to_reg
[inst
->dst
.reg
] + inst
->dst
.reg_offset
;
1667 inst
->dst
.reg
= new_virtual_grf
[reg
];
1668 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1669 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1671 for (int i
= 0; i
< inst
->sources
; i
++) {
1672 if (inst
->src
[i
].file
== GRF
) {
1673 reg
= vgrf_to_reg
[inst
->src
[i
].reg
] + inst
->src
[i
].reg_offset
;
1674 inst
->src
[i
].reg
= new_virtual_grf
[reg
];
1675 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1676 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1680 invalidate_live_intervals();
1684 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1686 * During code generation, we create tons of temporary variables, many of
1687 * which get immediately killed and are never used again. Yet, in later
1688 * optimization and analysis passes, such as compute_live_intervals, we need
1689 * to loop over all the virtual GRFs. Compacting them can save a lot of
1693 fs_visitor::compact_virtual_grfs()
1695 bool progress
= false;
1696 int remap_table
[this->alloc
.count
];
1697 memset(remap_table
, -1, sizeof(remap_table
));
1699 /* Mark which virtual GRFs are used. */
1700 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1701 if (inst
->dst
.file
== GRF
)
1702 remap_table
[inst
->dst
.reg
] = 0;
1704 for (int i
= 0; i
< inst
->sources
; i
++) {
1705 if (inst
->src
[i
].file
== GRF
)
1706 remap_table
[inst
->src
[i
].reg
] = 0;
1710 /* Compact the GRF arrays. */
1712 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1713 if (remap_table
[i
] == -1) {
1714 /* We just found an unused register. This means that we are
1715 * actually going to compact something.
1719 remap_table
[i
] = new_index
;
1720 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1721 invalidate_live_intervals();
1726 this->alloc
.count
= new_index
;
1728 /* Patch all the instructions to use the newly renumbered registers */
1729 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1730 if (inst
->dst
.file
== GRF
)
1731 inst
->dst
.reg
= remap_table
[inst
->dst
.reg
];
1733 for (int i
= 0; i
< inst
->sources
; i
++) {
1734 if (inst
->src
[i
].file
== GRF
)
1735 inst
->src
[i
].reg
= remap_table
[inst
->src
[i
].reg
];
1739 /* Patch all the references to delta_xy, since they're used in register
1740 * allocation. If they're unused, switch them to BAD_FILE so we don't
1741 * think some random VGRF is delta_xy.
1743 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1744 if (delta_xy
[i
].file
== GRF
) {
1745 if (remap_table
[delta_xy
[i
].reg
] != -1) {
1746 delta_xy
[i
].reg
= remap_table
[delta_xy
[i
].reg
];
1748 delta_xy
[i
].file
= BAD_FILE
;
1757 * Assign UNIFORM file registers to either push constants or pull constants.
1759 * We allow a fragment shader to have more than the specified minimum
1760 * maximum number of fragment shader uniform components (64). If
1761 * there are too many of these, they'd fill up all of register space.
1762 * So, this will push some of them out to the pull constant buffer and
1763 * update the program to load them. We also use pull constants for all
1764 * indirect constant loads because we don't support indirect accesses in
1768 fs_visitor::assign_constant_locations()
1770 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1771 if (dispatch_width
!= 8)
1774 unsigned int num_pull_constants
= 0;
1776 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1777 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1779 bool is_live
[uniforms
];
1780 memset(is_live
, 0, sizeof(is_live
));
1782 /* First, we walk through the instructions and do two things:
1784 * 1) Figure out which uniforms are live.
1786 * 2) Find all indirect access of uniform arrays and flag them as needing
1787 * to go into the pull constant buffer.
1789 * Note that we don't move constant-indexed accesses to arrays. No
1790 * testing has been done of the performance impact of this choice.
1792 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1793 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1794 if (inst
->src
[i
].file
!= UNIFORM
)
1797 if (inst
->src
[i
].reladdr
) {
1798 int uniform
= inst
->src
[i
].reg
;
1800 /* If this array isn't already present in the pull constant buffer,
1803 if (pull_constant_loc
[uniform
] == -1) {
1804 assert(param_size
[uniform
]);
1805 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1806 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1809 /* Mark the the one accessed uniform as live */
1810 int constant_nr
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1811 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1812 is_live
[constant_nr
] = true;
1817 /* Only allow 16 registers (128 uniform components) as push constants.
1819 * Just demote the end of the list. We could probably do better
1820 * here, demoting things that are rarely used in the program first.
1822 * If changing this value, note the limitation about total_regs in
1825 unsigned int max_push_components
= 16 * 8;
1826 unsigned int num_push_constants
= 0;
1828 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1830 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1831 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1832 /* This UNIFORM register is either dead, or has already been demoted
1833 * to a pull const. Mark it as no longer living in the param[] array.
1835 push_constant_loc
[i
] = -1;
1839 if (num_push_constants
< max_push_components
) {
1840 /* Retain as a push constant. Record the location in the params[]
1843 push_constant_loc
[i
] = num_push_constants
++;
1845 /* Demote to a pull constant. */
1846 push_constant_loc
[i
] = -1;
1847 pull_constant_loc
[i
] = num_pull_constants
++;
1851 stage_prog_data
->nr_params
= num_push_constants
;
1852 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1854 /* Up until now, the param[] array has been indexed by reg + reg_offset
1855 * of UNIFORM registers. Move pull constants into pull_param[] and
1856 * condense param[] to only contain the uniforms we chose to push.
1858 * NOTE: Because we are condensing the params[] array, we know that
1859 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1860 * having to make a copy.
1862 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1863 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1865 if (pull_constant_loc
[i
] != -1) {
1866 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1867 } else if (push_constant_loc
[i
] != -1) {
1868 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1874 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1875 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1878 fs_visitor::demote_pull_constants()
1880 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1881 for (int i
= 0; i
< inst
->sources
; i
++) {
1882 if (inst
->src
[i
].file
!= UNIFORM
)
1886 unsigned location
= inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
;
1887 if (location
>= uniforms
) /* Out of bounds access */
1890 pull_index
= pull_constant_loc
[location
];
1892 if (pull_index
== -1)
1895 /* Set up the annotation tracking for new generated instructions. */
1896 const fs_builder
ibld(this, block
, inst
);
1897 fs_reg
surf_index(stage_prog_data
->binding_table
.pull_constants_start
);
1898 fs_reg dst
= vgrf(glsl_type::float_type
);
1900 assert(inst
->src
[i
].stride
== 0);
1902 /* Generate a pull load into dst. */
1903 if (inst
->src
[i
].reladdr
) {
1904 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
1906 *inst
->src
[i
].reladdr
,
1908 inst
->src
[i
].reladdr
= NULL
;
1909 inst
->src
[i
].stride
= 1;
1911 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
1912 fs_reg offset
= fs_reg((unsigned)(pull_index
* 4) & ~15);
1913 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
1914 dst
, surf_index
, offset
);
1915 inst
->src
[i
].set_smear(pull_index
& 3);
1918 /* Rewrite the instruction to use the temporary VGRF. */
1919 inst
->src
[i
].file
= GRF
;
1920 inst
->src
[i
].reg
= dst
.reg
;
1921 inst
->src
[i
].reg_offset
= 0;
1924 invalidate_live_intervals();
1928 fs_visitor::opt_algebraic()
1930 bool progress
= false;
1932 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1933 switch (inst
->opcode
) {
1934 case BRW_OPCODE_MOV
:
1935 if (inst
->src
[0].file
!= IMM
)
1938 if (inst
->saturate
) {
1939 if (inst
->dst
.type
!= inst
->src
[0].type
)
1940 assert(!"unimplemented: saturate mixed types");
1942 if (brw_saturate_immediate(inst
->dst
.type
,
1943 &inst
->src
[0].fixed_hw_reg
)) {
1944 inst
->saturate
= false;
1950 case BRW_OPCODE_MUL
:
1951 if (inst
->src
[1].file
!= IMM
)
1955 if (inst
->src
[1].is_one()) {
1956 inst
->opcode
= BRW_OPCODE_MOV
;
1957 inst
->src
[1] = reg_undef
;
1963 if (inst
->src
[1].is_negative_one()) {
1964 inst
->opcode
= BRW_OPCODE_MOV
;
1965 inst
->src
[0].negate
= !inst
->src
[0].negate
;
1966 inst
->src
[1] = reg_undef
;
1972 if (inst
->src
[1].is_zero()) {
1973 inst
->opcode
= BRW_OPCODE_MOV
;
1974 inst
->src
[0] = inst
->src
[1];
1975 inst
->src
[1] = reg_undef
;
1980 if (inst
->src
[0].file
== IMM
) {
1981 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
1982 inst
->opcode
= BRW_OPCODE_MOV
;
1983 inst
->src
[0].fixed_hw_reg
.dw1
.f
*= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
1984 inst
->src
[1] = reg_undef
;
1989 case BRW_OPCODE_ADD
:
1990 if (inst
->src
[1].file
!= IMM
)
1994 if (inst
->src
[1].is_zero()) {
1995 inst
->opcode
= BRW_OPCODE_MOV
;
1996 inst
->src
[1] = reg_undef
;
2001 if (inst
->src
[0].file
== IMM
) {
2002 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2003 inst
->opcode
= BRW_OPCODE_MOV
;
2004 inst
->src
[0].fixed_hw_reg
.dw1
.f
+= inst
->src
[1].fixed_hw_reg
.dw1
.f
;
2005 inst
->src
[1] = reg_undef
;
2011 if (inst
->src
[0].equals(inst
->src
[1])) {
2012 inst
->opcode
= BRW_OPCODE_MOV
;
2013 inst
->src
[1] = reg_undef
;
2018 case BRW_OPCODE_LRP
:
2019 if (inst
->src
[1].equals(inst
->src
[2])) {
2020 inst
->opcode
= BRW_OPCODE_MOV
;
2021 inst
->src
[0] = inst
->src
[1];
2022 inst
->src
[1] = reg_undef
;
2023 inst
->src
[2] = reg_undef
;
2028 case BRW_OPCODE_CMP
:
2029 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2031 inst
->src
[0].negate
&&
2032 inst
->src
[1].is_zero()) {
2033 inst
->src
[0].abs
= false;
2034 inst
->src
[0].negate
= false;
2035 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2040 case BRW_OPCODE_SEL
:
2041 if (inst
->src
[0].equals(inst
->src
[1])) {
2042 inst
->opcode
= BRW_OPCODE_MOV
;
2043 inst
->src
[1] = reg_undef
;
2044 inst
->predicate
= BRW_PREDICATE_NONE
;
2045 inst
->predicate_inverse
= false;
2047 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2048 switch (inst
->conditional_mod
) {
2049 case BRW_CONDITIONAL_LE
:
2050 case BRW_CONDITIONAL_L
:
2051 switch (inst
->src
[1].type
) {
2052 case BRW_REGISTER_TYPE_F
:
2053 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
>= 1.0f
) {
2054 inst
->opcode
= BRW_OPCODE_MOV
;
2055 inst
->src
[1] = reg_undef
;
2056 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2064 case BRW_CONDITIONAL_GE
:
2065 case BRW_CONDITIONAL_G
:
2066 switch (inst
->src
[1].type
) {
2067 case BRW_REGISTER_TYPE_F
:
2068 if (inst
->src
[1].fixed_hw_reg
.dw1
.f
<= 0.0f
) {
2069 inst
->opcode
= BRW_OPCODE_MOV
;
2070 inst
->src
[1] = reg_undef
;
2071 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2083 case BRW_OPCODE_MAD
:
2084 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2085 inst
->opcode
= BRW_OPCODE_MOV
;
2086 inst
->src
[1] = reg_undef
;
2087 inst
->src
[2] = reg_undef
;
2089 } else if (inst
->src
[0].is_zero()) {
2090 inst
->opcode
= BRW_OPCODE_MUL
;
2091 inst
->src
[0] = inst
->src
[2];
2092 inst
->src
[2] = reg_undef
;
2094 } else if (inst
->src
[1].is_one()) {
2095 inst
->opcode
= BRW_OPCODE_ADD
;
2096 inst
->src
[1] = inst
->src
[2];
2097 inst
->src
[2] = reg_undef
;
2099 } else if (inst
->src
[2].is_one()) {
2100 inst
->opcode
= BRW_OPCODE_ADD
;
2101 inst
->src
[2] = reg_undef
;
2103 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2104 inst
->opcode
= BRW_OPCODE_ADD
;
2105 inst
->src
[1].fixed_hw_reg
.dw1
.f
*= inst
->src
[2].fixed_hw_reg
.dw1
.f
;
2106 inst
->src
[2] = reg_undef
;
2110 case SHADER_OPCODE_RCP
: {
2111 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2112 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2113 if (inst
->src
[0].equals(prev
->dst
)) {
2114 inst
->opcode
= SHADER_OPCODE_RSQ
;
2115 inst
->src
[0] = prev
->src
[0];
2121 case SHADER_OPCODE_BROADCAST
:
2122 if (is_uniform(inst
->src
[0])) {
2123 inst
->opcode
= BRW_OPCODE_MOV
;
2125 inst
->force_writemask_all
= true;
2127 } else if (inst
->src
[1].file
== IMM
) {
2128 inst
->opcode
= BRW_OPCODE_MOV
;
2129 inst
->src
[0] = component(inst
->src
[0],
2130 inst
->src
[1].fixed_hw_reg
.dw1
.ud
);
2132 inst
->force_writemask_all
= true;
2141 /* Swap if src[0] is immediate. */
2142 if (progress
&& inst
->is_commutative()) {
2143 if (inst
->src
[0].file
== IMM
) {
2144 fs_reg tmp
= inst
->src
[1];
2145 inst
->src
[1] = inst
->src
[0];
2154 * Optimize sample messages that have constant zero values for the trailing
2155 * texture coordinates. We can just reduce the message length for these
2156 * instructions instead of reserving a register for it. Trailing parameters
2157 * that aren't sent default to zero anyway. This will cause the dead code
2158 * eliminator to remove the MOV instruction that would otherwise be emitted to
2159 * set up the zero value.
2162 fs_visitor::opt_zero_samples()
2164 /* Gen4 infers the texturing opcode based on the message length so we can't
2167 if (devinfo
->gen
< 5)
2170 bool progress
= false;
2172 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2173 if (!inst
->is_tex())
2176 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2178 if (load_payload
->is_head_sentinel() ||
2179 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2182 /* We don't want to remove the message header or the first parameter.
2183 * Removing the first parameter is not allowed, see the Haswell PRM
2184 * volume 7, page 149:
2186 * "Parameter 0 is required except for the sampleinfo message, which
2187 * has no parameter 0"
2189 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2190 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2191 (inst
->exec_size
/ 8) +
2192 inst
->header_size
- 1].is_zero()) {
2193 inst
->mlen
-= inst
->exec_size
/ 8;
2199 invalidate_live_intervals();
2205 * Optimize sample messages which are followed by the final RT write.
2207 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2208 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2209 * final texturing results copied to the framebuffer write payload and modify
2210 * them to write to the framebuffer directly.
2213 fs_visitor::opt_sampler_eot()
2215 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2217 if (stage
!= MESA_SHADER_FRAGMENT
)
2220 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2223 /* FINISHME: It should be possible to implement this optimization when there
2224 * are multiple drawbuffers.
2226 if (key
->nr_color_regions
!= 1)
2229 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2230 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2231 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2232 assert(fb_write
->eot
);
2233 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2235 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2237 /* There wasn't one; nothing to do. */
2238 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2241 /* This optimisation doesn't seem to work for textureGather for some
2242 * reason. I can't find any documentation or known workarounds to indicate
2243 * that this is expected, but considering that it is probably pretty
2244 * unlikely that a shader would directly write out the results from
2245 * textureGather we might as well just disable it.
2247 if (tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2248 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2251 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2252 * It's very likely to be the previous instruction.
2254 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2255 if (load_payload
->is_head_sentinel() ||
2256 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2259 assert(!tex_inst
->eot
); /* We can't get here twice */
2260 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2262 const fs_builder
ibld(this, block
, tex_inst
);
2264 tex_inst
->offset
|= fb_write
->target
<< 24;
2265 tex_inst
->eot
= true;
2266 tex_inst
->dst
= ibld
.null_reg_ud();
2267 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2269 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2270 * to create a new LOAD_PAYLOAD command with the same sources and a space
2271 * saved for the header. Using a new destination register not only makes sure
2272 * we have enough space, but it will make sure the dead code eliminator kills
2273 * the instruction that this will replace.
2275 if (tex_inst
->header_size
!= 0)
2278 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2279 load_payload
->sources
+ 1);
2280 fs_reg
*new_sources
=
2281 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2283 new_sources
[0] = fs_reg();
2284 for (int i
= 0; i
< load_payload
->sources
; i
++)
2285 new_sources
[i
+1] = load_payload
->src
[i
];
2287 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2288 * requires a lot of information about the sources to appropriately figure
2289 * out the number of registers needed to be used. Given this stage in our
2290 * optimization, we may not have the appropriate GRFs required by
2291 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2292 * manually emit the instruction.
2294 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2295 load_payload
->exec_size
,
2298 load_payload
->sources
+ 1);
2300 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2301 new_load_payload
->header_size
= 1;
2303 tex_inst
->header_size
= 1;
2304 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2305 tex_inst
->src
[0] = send_header
;
2311 fs_visitor::opt_register_renaming()
2313 bool progress
= false;
2316 int remap
[alloc
.count
];
2317 memset(remap
, -1, sizeof(int) * alloc
.count
);
2319 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2320 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2322 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2323 inst
->opcode
== BRW_OPCODE_WHILE
) {
2327 /* Rewrite instruction sources. */
2328 for (int i
= 0; i
< inst
->sources
; i
++) {
2329 if (inst
->src
[i
].file
== GRF
&&
2330 remap
[inst
->src
[i
].reg
] != -1 &&
2331 remap
[inst
->src
[i
].reg
] != inst
->src
[i
].reg
) {
2332 inst
->src
[i
].reg
= remap
[inst
->src
[i
].reg
];
2337 const int dst
= inst
->dst
.reg
;
2340 inst
->dst
.file
== GRF
&&
2341 alloc
.sizes
[inst
->dst
.reg
] == inst
->exec_size
/ 8 &&
2342 !inst
->is_partial_write()) {
2343 if (remap
[dst
] == -1) {
2346 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2347 inst
->dst
.reg
= remap
[dst
];
2350 } else if (inst
->dst
.file
== GRF
&&
2352 remap
[dst
] != dst
) {
2353 inst
->dst
.reg
= remap
[dst
];
2359 invalidate_live_intervals();
2361 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2362 if (delta_xy
[i
].file
== GRF
&& remap
[delta_xy
[i
].reg
] != -1) {
2363 delta_xy
[i
].reg
= remap
[delta_xy
[i
].reg
];
2372 * Remove redundant or useless discard jumps.
2374 * For example, we can eliminate jumps in the following sequence:
2376 * discard-jump (redundant with the next jump)
2377 * discard-jump (useless; jumps to the next instruction)
2381 fs_visitor::opt_redundant_discard_jumps()
2383 bool progress
= false;
2385 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2387 fs_inst
*placeholder_halt
= NULL
;
2388 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2389 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2390 placeholder_halt
= inst
;
2395 if (!placeholder_halt
)
2398 /* Delete any HALTs immediately before the placeholder halt. */
2399 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2400 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2401 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2402 prev
->remove(last_bblock
);
2407 invalidate_live_intervals();
2413 fs_visitor::compute_to_mrf()
2415 bool progress
= false;
2418 /* No MRFs on Gen >= 7. */
2419 if (devinfo
->gen
>= 7)
2422 calculate_live_intervals();
2424 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2428 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2429 inst
->is_partial_write() ||
2430 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2431 inst
->dst
.type
!= inst
->src
[0].type
||
2432 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2433 !inst
->src
[0].is_contiguous() ||
2434 inst
->src
[0].subreg_offset
)
2437 /* Work out which hardware MRF registers are written by this
2440 int mrf_low
= inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2442 if (inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2443 mrf_high
= mrf_low
+ 4;
2444 } else if (inst
->exec_size
== 16) {
2445 mrf_high
= mrf_low
+ 1;
2450 /* Can't compute-to-MRF this GRF if someone else was going to
2453 if (this->virtual_grf_end
[inst
->src
[0].reg
] > ip
)
2456 /* Found a move of a GRF to a MRF. Let's see if we can go
2457 * rewrite the thing that made this GRF to write into the MRF.
2459 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2460 if (scan_inst
->dst
.file
== GRF
&&
2461 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2462 /* Found the last thing to write our reg we want to turn
2463 * into a compute-to-MRF.
2466 /* If this one instruction didn't populate all the
2467 * channels, bail. We might be able to rewrite everything
2468 * that writes that reg, but it would require smarter
2469 * tracking to delay the rewriting until complete success.
2471 if (scan_inst
->is_partial_write())
2474 /* Things returning more than one register would need us to
2475 * understand coalescing out more than one MOV at a time.
2477 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2480 /* SEND instructions can't have MRF as a destination. */
2481 if (scan_inst
->mlen
)
2484 if (devinfo
->gen
== 6) {
2485 /* gen6 math instructions must have the destination be
2486 * GRF, so no compute-to-MRF for them.
2488 if (scan_inst
->is_math()) {
2493 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2494 /* Found the creator of our MRF's source value. */
2495 scan_inst
->dst
.file
= MRF
;
2496 scan_inst
->dst
.reg
= inst
->dst
.reg
;
2497 scan_inst
->saturate
|= inst
->saturate
;
2498 inst
->remove(block
);
2504 /* We don't handle control flow here. Most computation of
2505 * values that end up in MRFs are shortly before the MRF
2508 if (block
->start() == scan_inst
)
2511 /* You can't read from an MRF, so if someone else reads our
2512 * MRF's source GRF that we wanted to rewrite, that stops us.
2514 bool interfered
= false;
2515 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2516 if (scan_inst
->src
[i
].file
== GRF
&&
2517 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2518 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2525 if (scan_inst
->dst
.file
== MRF
) {
2526 /* If somebody else writes our MRF here, we can't
2527 * compute-to-MRF before that.
2529 int scan_mrf_low
= scan_inst
->dst
.reg
& ~BRW_MRF_COMPR4
;
2532 if (scan_inst
->dst
.reg
& BRW_MRF_COMPR4
) {
2533 scan_mrf_high
= scan_mrf_low
+ 4;
2534 } else if (scan_inst
->exec_size
== 16) {
2535 scan_mrf_high
= scan_mrf_low
+ 1;
2537 scan_mrf_high
= scan_mrf_low
;
2540 if (mrf_low
== scan_mrf_low
||
2541 mrf_low
== scan_mrf_high
||
2542 mrf_high
== scan_mrf_low
||
2543 mrf_high
== scan_mrf_high
) {
2548 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2549 /* Found a SEND instruction, which means that there are
2550 * live values in MRFs from base_mrf to base_mrf +
2551 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2554 if (mrf_low
>= scan_inst
->base_mrf
&&
2555 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2558 if (mrf_high
>= scan_inst
->base_mrf
&&
2559 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2567 invalidate_live_intervals();
2573 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2574 * flow. We could probably do better here with some form of divergence
2578 fs_visitor::eliminate_find_live_channel()
2580 bool progress
= false;
2583 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2584 switch (inst
->opcode
) {
2590 case BRW_OPCODE_ENDIF
:
2591 case BRW_OPCODE_WHILE
:
2595 case FS_OPCODE_DISCARD_JUMP
:
2596 /* This can potentially make control flow non-uniform until the end
2601 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2603 inst
->opcode
= BRW_OPCODE_MOV
;
2604 inst
->src
[0] = fs_reg(0);
2606 inst
->force_writemask_all
= true;
2620 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2621 * instructions to FS_OPCODE_REP_FB_WRITE.
2624 fs_visitor::emit_repclear_shader()
2626 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2628 int color_mrf
= base_mrf
+ 2;
2630 fs_inst
*mov
= bld
.exec_all().MOV(vec4(brw_message_reg(color_mrf
)),
2631 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2634 if (key
->nr_color_regions
== 1) {
2635 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2636 write
->saturate
= key
->clamp_fragment_color
;
2637 write
->base_mrf
= color_mrf
;
2639 write
->header_size
= 0;
2642 assume(key
->nr_color_regions
> 0);
2643 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2644 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2645 write
->saturate
= key
->clamp_fragment_color
;
2646 write
->base_mrf
= base_mrf
;
2648 write
->header_size
= 2;
2656 assign_constant_locations();
2657 assign_curb_setup();
2659 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2660 assert(mov
->src
[0].file
== HW_REG
);
2661 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].fixed_hw_reg
.nr
, 0);
2665 * Walks through basic blocks, looking for repeated MRF writes and
2666 * removing the later ones.
2669 fs_visitor::remove_duplicate_mrf_writes()
2671 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2672 bool progress
= false;
2674 /* Need to update the MRF tracking for compressed instructions. */
2675 if (dispatch_width
== 16)
2678 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2680 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2681 if (inst
->is_control_flow()) {
2682 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2685 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2686 inst
->dst
.file
== MRF
) {
2687 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.reg
];
2688 if (prev_inst
&& inst
->equals(prev_inst
)) {
2689 inst
->remove(block
);
2695 /* Clear out the last-write records for MRFs that were overwritten. */
2696 if (inst
->dst
.file
== MRF
) {
2697 last_mrf_move
[inst
->dst
.reg
] = NULL
;
2700 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2701 /* Found a SEND instruction, which will include two or fewer
2702 * implied MRF writes. We could do better here.
2704 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2705 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2709 /* Clear out any MRF move records whose sources got overwritten. */
2710 if (inst
->dst
.file
== GRF
) {
2711 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2712 if (last_mrf_move
[i
] &&
2713 last_mrf_move
[i
]->src
[0].reg
== inst
->dst
.reg
) {
2714 last_mrf_move
[i
] = NULL
;
2719 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2720 inst
->dst
.file
== MRF
&&
2721 inst
->src
[0].file
== GRF
&&
2722 !inst
->is_partial_write()) {
2723 last_mrf_move
[inst
->dst
.reg
] = inst
;
2728 invalidate_live_intervals();
2734 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2736 /* Clear the flag for registers that actually got read (as expected). */
2737 for (int i
= 0; i
< inst
->sources
; i
++) {
2739 if (inst
->src
[i
].file
== GRF
) {
2740 grf
= inst
->src
[i
].reg
;
2741 } else if (inst
->src
[i
].file
== HW_REG
&&
2742 inst
->src
[i
].fixed_hw_reg
.file
== BRW_GENERAL_REGISTER_FILE
) {
2743 grf
= inst
->src
[i
].fixed_hw_reg
.nr
;
2748 if (grf
>= first_grf
&&
2749 grf
< first_grf
+ grf_len
) {
2750 deps
[grf
- first_grf
] = false;
2751 if (inst
->exec_size
== 16)
2752 deps
[grf
- first_grf
+ 1] = false;
2758 * Implements this workaround for the original 965:
2760 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2761 * check for post destination dependencies on this instruction, software
2762 * must ensure that there is no destination hazard for the case of ‘write
2763 * followed by a posted write’ shown in the following example.
2766 * 2. send r3.xy <rest of send instruction>
2769 * Due to no post-destination dependency check on the ‘send’, the above
2770 * code sequence could have two instructions (1 and 2) in flight at the
2771 * same time that both consider ‘r3’ as the target of their final writes.
2774 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2777 int write_len
= inst
->regs_written
;
2778 int first_write_grf
= inst
->dst
.reg
;
2779 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2780 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2782 memset(needs_dep
, false, sizeof(needs_dep
));
2783 memset(needs_dep
, true, write_len
);
2785 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2787 /* Walk backwards looking for writes to registers we're writing which
2788 * aren't read since being written. If we hit the start of the program,
2789 * we assume that there are no outstanding dependencies on entry to the
2792 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2793 /* If we hit control flow, assume that there *are* outstanding
2794 * dependencies, and force their cleanup before our instruction.
2796 if (block
->start() == scan_inst
) {
2797 for (int i
= 0; i
< write_len
; i
++) {
2799 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2800 first_write_grf
+ i
);
2805 /* We insert our reads as late as possible on the assumption that any
2806 * instruction but a MOV that might have left us an outstanding
2807 * dependency has more latency than a MOV.
2809 if (scan_inst
->dst
.file
== GRF
) {
2810 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2811 int reg
= scan_inst
->dst
.reg
+ i
;
2813 if (reg
>= first_write_grf
&&
2814 reg
< first_write_grf
+ write_len
&&
2815 needs_dep
[reg
- first_write_grf
]) {
2816 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2817 needs_dep
[reg
- first_write_grf
] = false;
2818 if (scan_inst
->exec_size
== 16)
2819 needs_dep
[reg
- first_write_grf
+ 1] = false;
2824 /* Clear the flag for registers that actually got read (as expected). */
2825 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2827 /* Continue the loop only if we haven't resolved all the dependencies */
2829 for (i
= 0; i
< write_len
; i
++) {
2839 * Implements this workaround for the original 965:
2841 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2842 * used as a destination register until after it has been sourced by an
2843 * instruction with a different destination register.
2846 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2848 int write_len
= inst
->regs_written
;
2849 int first_write_grf
= inst
->dst
.reg
;
2850 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2851 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2853 memset(needs_dep
, false, sizeof(needs_dep
));
2854 memset(needs_dep
, true, write_len
);
2855 /* Walk forwards looking for writes to registers we're writing which aren't
2856 * read before being written.
2858 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2859 /* If we hit control flow, force resolve all remaining dependencies. */
2860 if (block
->end() == scan_inst
) {
2861 for (int i
= 0; i
< write_len
; i
++) {
2863 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2864 first_write_grf
+ i
);
2869 /* Clear the flag for registers that actually got read (as expected). */
2870 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2872 /* We insert our reads as late as possible since they're reading the
2873 * result of a SEND, which has massive latency.
2875 if (scan_inst
->dst
.file
== GRF
&&
2876 scan_inst
->dst
.reg
>= first_write_grf
&&
2877 scan_inst
->dst
.reg
< first_write_grf
+ write_len
&&
2878 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
]) {
2879 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2880 scan_inst
->dst
.reg
);
2881 needs_dep
[scan_inst
->dst
.reg
- first_write_grf
] = false;
2884 /* Continue the loop only if we haven't resolved all the dependencies */
2886 for (i
= 0; i
< write_len
; i
++) {
2896 fs_visitor::insert_gen4_send_dependency_workarounds()
2898 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
2901 bool progress
= false;
2903 /* Note that we're done with register allocation, so GRF fs_regs always
2904 * have a .reg_offset of 0.
2907 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2908 if (inst
->mlen
!= 0 && inst
->dst
.file
== GRF
) {
2909 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
2910 insert_gen4_post_send_dependency_workarounds(block
, inst
);
2916 invalidate_live_intervals();
2920 * Turns the generic expression-style uniform pull constant load instruction
2921 * into a hardware-specific series of instructions for loading a pull
2924 * The expression style allows the CSE pass before this to optimize out
2925 * repeated loads from the same offset, and gives the pre-register-allocation
2926 * scheduling full flexibility, while the conversion to native instructions
2927 * allows the post-register-allocation scheduler the best information
2930 * Note that execution masking for setting up pull constant loads is special:
2931 * the channels that need to be written are unrelated to the current execution
2932 * mask, since a later instruction will use one of the result channels as a
2933 * source operand for all 8 or 16 of its channels.
2936 fs_visitor::lower_uniform_pull_constant_loads()
2938 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2939 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
2942 if (devinfo
->gen
>= 7) {
2943 /* The offset arg before was a vec4-aligned byte offset. We need to
2944 * turn it into a dword offset.
2946 fs_reg const_offset_reg
= inst
->src
[1];
2947 assert(const_offset_reg
.file
== IMM
&&
2948 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
2949 const_offset_reg
.fixed_hw_reg
.dw1
.ud
/= 4;
2951 fs_reg payload
, offset
;
2952 if (devinfo
->gen
>= 9) {
2953 /* We have to use a message header on Skylake to get SIMD4x2
2954 * mode. Reserve space for the register.
2956 offset
= payload
= fs_reg(GRF
, alloc
.allocate(2));
2957 offset
.reg_offset
++;
2960 offset
= payload
= fs_reg(GRF
, alloc
.allocate(1));
2964 /* This is actually going to be a MOV, but since only the first dword
2965 * is accessed, we have a special opcode to do just that one. Note
2966 * that this needs to be an operation that will be considered a def
2967 * by live variable analysis, or register allocation will explode.
2969 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
2970 8, offset
, const_offset_reg
);
2971 setup
->force_writemask_all
= true;
2973 setup
->ir
= inst
->ir
;
2974 setup
->annotation
= inst
->annotation
;
2975 inst
->insert_before(block
, setup
);
2977 /* Similarly, this will only populate the first 4 channels of the
2978 * result register (since we only use smear values from 0-3), but we
2979 * don't tell the optimizer.
2981 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
2982 inst
->src
[1] = payload
;
2983 inst
->base_mrf
= -1;
2985 invalidate_live_intervals();
2987 /* Before register allocation, we didn't tell the scheduler about the
2988 * MRF we use. We know it's safe to use this MRF because nothing
2989 * else does except for register spill/unspill, which generates and
2990 * uses its MRF within a single IR instruction.
2992 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
2999 fs_visitor::lower_load_payload()
3001 bool progress
= false;
3003 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3004 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3007 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== GRF
);
3008 assert(inst
->saturate
== false);
3009 fs_reg dst
= inst
->dst
;
3011 /* Get rid of COMPR4. We'll add it back in if we need it */
3012 if (dst
.file
== MRF
)
3013 dst
.reg
= dst
.reg
& ~BRW_MRF_COMPR4
;
3015 const fs_builder
ibld(this, block
, inst
);
3016 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3018 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3019 if (inst
->src
[i
].file
!= BAD_FILE
) {
3020 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3021 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3022 hbld
.MOV(mov_dst
, mov_src
);
3024 dst
= offset(dst
, hbld
, 1);
3027 if (inst
->dst
.file
== MRF
&& (inst
->dst
.reg
& BRW_MRF_COMPR4
) &&
3028 inst
->exec_size
> 8) {
3029 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3030 * a straightforward copy. Instead, the result of the
3031 * LOAD_PAYLOAD is treated as interleaved and the first four
3032 * non-header sources are unpacked as:
3043 * This is used for gen <= 5 fb writes.
3045 assert(inst
->exec_size
== 16);
3046 assert(inst
->header_size
+ 4 <= inst
->sources
);
3047 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3048 if (inst
->src
[i
].file
!= BAD_FILE
) {
3049 if (devinfo
->has_compr4
) {
3050 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3051 compr4_dst
.reg
|= BRW_MRF_COMPR4
;
3052 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3054 /* Platform doesn't have COMPR4. We have to fake it */
3055 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3056 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3058 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3065 /* The loop above only ever incremented us through the first set
3066 * of 4 registers. However, thanks to the magic of COMPR4, we
3067 * actually wrote to the first 8 registers, so we need to take
3068 * that into account now.
3072 /* The COMPR4 code took care of the first 4 sources. We'll let
3073 * the regular path handle any remaining sources. Yes, we are
3074 * modifying the instruction but we're about to delete it so
3075 * this really doesn't hurt anything.
3077 inst
->header_size
+= 4;
3080 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3081 if (inst
->src
[i
].file
!= BAD_FILE
)
3082 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3083 dst
= offset(dst
, ibld
, 1);
3086 inst
->remove(block
);
3091 invalidate_live_intervals();
3097 fs_visitor::lower_integer_multiplication()
3099 bool progress
= false;
3101 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3102 const fs_builder
ibld(this, block
, inst
);
3104 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3105 if (inst
->dst
.is_accumulator() ||
3106 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3107 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3110 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3111 * operation directly, but CHV/BXT cannot.
3113 if (devinfo
->gen
>= 8 &&
3114 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3117 if (inst
->src
[1].file
== IMM
&&
3118 inst
->src
[1].fixed_hw_reg
.dw1
.ud
< (1 << 16)) {
3119 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3120 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3123 * If multiplying by an immediate value that fits in 16-bits, do a
3124 * single MUL instruction with that value in the proper location.
3126 if (devinfo
->gen
< 7) {
3127 fs_reg
imm(GRF
, alloc
.allocate(dispatch_width
/ 8),
3129 ibld
.MOV(imm
, inst
->src
[1]);
3130 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3132 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3135 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3136 * do 32-bit integer multiplication in one instruction, but instead
3137 * must do a sequence (which actually calculates a 64-bit result):
3139 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3140 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3141 * mov(8) g2<1>D acc0<8,8,1>D
3143 * But on Gen > 6, the ability to use second accumulator register
3144 * (acc1) for non-float data types was removed, preventing a simple
3145 * implementation in SIMD16. A 16-channel result can be calculated by
3146 * executing the three instructions twice in SIMD8, once with quarter
3147 * control of 1Q for the first eight channels and again with 2Q for
3148 * the second eight channels.
3150 * Which accumulator register is implicitly accessed (by AccWrEnable
3151 * for instance) is determined by the quarter control. Unfortunately
3152 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3153 * implicit accumulator access by an instruction with 2Q will access
3154 * acc1 regardless of whether the data type is usable in acc1.
3156 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3157 * integer data types.
3159 * Since we only want the low 32-bits of the result, we can do two
3160 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3161 * adjust the high result and add them (like the mach is doing):
3163 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3164 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3165 * shl(8) g9<1>D g8<8,8,1>D 16D
3166 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3168 * We avoid the shl instruction by realizing that we only want to add
3169 * the low 16-bits of the "high" result to the high 16-bits of the
3170 * "low" result and using proper regioning on the add:
3172 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3173 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3174 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3176 * Since it does not use the (single) accumulator register, we can
3177 * schedule multi-component multiplications much better.
3180 fs_reg orig_dst
= inst
->dst
;
3181 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3182 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
3185 fs_reg low
= inst
->dst
;
3186 fs_reg
high(GRF
, alloc
.allocate(dispatch_width
/ 8),
3189 if (devinfo
->gen
>= 7) {
3190 fs_reg src1_0_w
= inst
->src
[1];
3191 fs_reg src1_1_w
= inst
->src
[1];
3193 if (inst
->src
[1].file
== IMM
) {
3194 src1_0_w
.fixed_hw_reg
.dw1
.ud
&= 0xffff;
3195 src1_1_w
.fixed_hw_reg
.dw1
.ud
>>= 16;
3197 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3198 if (src1_0_w
.stride
!= 0) {
3199 assert(src1_0_w
.stride
== 1);
3200 src1_0_w
.stride
= 2;
3203 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3204 if (src1_1_w
.stride
!= 0) {
3205 assert(src1_1_w
.stride
== 1);
3206 src1_1_w
.stride
= 2;
3208 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3210 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3211 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3213 fs_reg src0_0_w
= inst
->src
[0];
3214 fs_reg src0_1_w
= inst
->src
[0];
3216 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3217 if (src0_0_w
.stride
!= 0) {
3218 assert(src0_0_w
.stride
== 1);
3219 src0_0_w
.stride
= 2;
3222 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3223 if (src0_1_w
.stride
!= 0) {
3224 assert(src0_1_w
.stride
== 1);
3225 src0_1_w
.stride
= 2;
3227 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3229 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3230 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3233 fs_reg dst
= inst
->dst
;
3234 dst
.type
= BRW_REGISTER_TYPE_UW
;
3235 dst
.subreg_offset
= 2;
3238 high
.type
= BRW_REGISTER_TYPE_UW
;
3241 low
.type
= BRW_REGISTER_TYPE_UW
;
3242 low
.subreg_offset
= 2;
3245 ibld
.ADD(dst
, low
, high
);
3247 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3248 set_condmod(inst
->conditional_mod
,
3249 ibld
.MOV(orig_dst
, inst
->dst
));
3253 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3254 /* Should have been lowered to 8-wide. */
3255 assert(inst
->exec_size
<= 8);
3256 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3258 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3259 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3261 if (devinfo
->gen
>= 8) {
3262 /* Until Gen8, integer multiplies read 32-bits from one source,
3263 * and 16-bits from the other, and relying on the MACH instruction
3264 * to generate the high bits of the result.
3266 * On Gen8, the multiply instruction does a full 32x32-bit
3267 * multiply, but in order to do a 64-bit multiply we can simulate
3268 * the previous behavior and then use a MACH instruction.
3270 * FINISHME: Don't use source modifiers on src1.
3272 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3273 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3274 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3275 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3276 mul
->src
[1].stride
*= 2;
3278 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3279 inst
->force_sechalf
) {
3280 /* Among other things the quarter control bits influence which
3281 * accumulator register is used by the hardware for instructions
3282 * that access the accumulator implicitly (e.g. MACH). A
3283 * second-half instruction would normally map to acc1, which
3284 * doesn't exist on Gen7 and up (the hardware does emulate it for
3285 * floating-point instructions *only* by taking advantage of the
3286 * extra precision of acc0 not normally used for floating point
3289 * HSW and up are careful enough not to try to access an
3290 * accumulator register that doesn't exist, but on earlier Gen7
3291 * hardware we need to make sure that the quarter control bits are
3292 * zero to avoid non-deterministic behaviour and emit an extra MOV
3293 * to get the result masked correctly according to the current
3296 mach
->force_sechalf
= false;
3297 mach
->force_writemask_all
= true;
3298 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3299 ibld
.MOV(inst
->dst
, mach
->dst
);
3305 inst
->remove(block
);
3310 invalidate_live_intervals();
3316 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3317 fs_reg
*dst
, fs_reg color
, unsigned components
)
3319 if (key
->clamp_fragment_color
) {
3320 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3321 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3323 for (unsigned i
= 0; i
< components
; i
++)
3325 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3330 for (unsigned i
= 0; i
< components
; i
++)
3331 dst
[i
] = offset(color
, bld
, i
);
3335 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3336 const brw_wm_prog_data
*prog_data
,
3337 const brw_wm_prog_key
*key
,
3338 const fs_visitor::thread_payload
&payload
)
3340 assert(inst
->src
[6].file
== IMM
);
3341 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3342 const fs_reg
&color0
= inst
->src
[0];
3343 const fs_reg
&color1
= inst
->src
[1];
3344 const fs_reg
&src0_alpha
= inst
->src
[2];
3345 const fs_reg
&src_depth
= inst
->src
[3];
3346 const fs_reg
&dst_depth
= inst
->src
[4];
3347 fs_reg sample_mask
= inst
->src
[5];
3348 const unsigned components
= inst
->src
[6].fixed_hw_reg
.dw1
.ud
;
3350 /* We can potentially have a message length of up to 15, so we have to set
3351 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3354 int header_size
= 2, payload_header_size
;
3355 unsigned length
= 0;
3357 /* From the Sandy Bridge PRM, volume 4, page 198:
3359 * "Dispatched Pixel Enables. One bit per pixel indicating
3360 * which pixels were originally enabled when the thread was
3361 * dispatched. This field is only required for the end-of-
3362 * thread message and on all dual-source messages."
3364 if (devinfo
->gen
>= 6 &&
3365 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3366 color1
.file
== BAD_FILE
&&
3367 key
->nr_color_regions
== 1) {
3371 if (header_size
!= 0) {
3372 assert(header_size
== 2);
3373 /* Allocate 2 registers for a header */
3377 if (payload
.aa_dest_stencil_reg
) {
3378 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1));
3379 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3380 .MOV(sources
[length
],
3381 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3385 if (prog_data
->uses_omask
) {
3386 sources
[length
] = fs_reg(GRF
, bld
.shader
->alloc
.allocate(1),
3387 BRW_REGISTER_TYPE_UD
);
3389 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3390 * relevant. Since it's unsigned single words one vgrf is always
3391 * 16-wide, but only the lower or higher 8 channels will be used by the
3392 * hardware when doing a SIMD8 write depending on whether we have
3393 * selected the subspans for the first or second half respectively.
3395 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3396 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3397 sample_mask
.stride
*= 2;
3399 bld
.exec_all().annotate("FB write oMask")
3400 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3401 inst
->force_sechalf
),
3406 payload_header_size
= length
;
3408 if (src0_alpha
.file
!= BAD_FILE
) {
3409 /* FIXME: This is being passed at the wrong location in the payload and
3410 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3411 * It's supposed to be immediately before oMask but there seems to be no
3412 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3413 * requires header sources to form a contiguous segment at the beginning
3414 * of the message and src0_alpha has per-channel semantics.
3416 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3420 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3423 if (color1
.file
!= BAD_FILE
) {
3424 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3428 if (src_depth
.file
!= BAD_FILE
) {
3429 sources
[length
] = src_depth
;
3433 if (dst_depth
.file
!= BAD_FILE
) {
3434 sources
[length
] = dst_depth
;
3439 if (devinfo
->gen
>= 7) {
3440 /* Send from the GRF */
3441 fs_reg payload
= fs_reg(GRF
, -1, BRW_REGISTER_TYPE_F
);
3442 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3443 payload
.reg
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3444 load
->dst
= payload
;
3446 inst
->src
[0] = payload
;
3447 inst
->resize_sources(1);
3448 inst
->base_mrf
= -1;
3450 /* Send from the MRF */
3451 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3452 sources
, length
, payload_header_size
);
3454 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3455 * will do this for us if we just give it a COMPR4 destination.
3457 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3458 load
->dst
.reg
|= BRW_MRF_COMPR4
;
3460 inst
->resize_sources(0);
3464 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3465 inst
->mlen
= load
->regs_written
;
3466 inst
->header_size
= header_size
;
3470 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3471 const fs_reg
&coordinate
,
3472 const fs_reg
&shadow_c
,
3473 const fs_reg
&lod
, const fs_reg
&lod2
,
3474 const fs_reg
&sampler
,
3475 unsigned coord_components
,
3476 unsigned grad_components
)
3478 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3479 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3480 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3481 fs_reg msg_end
= msg_begin
;
3484 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3486 for (unsigned i
= 0; i
< coord_components
; i
++)
3487 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3488 offset(coordinate
, bld
, i
));
3490 msg_end
= offset(msg_end
, bld
, coord_components
);
3492 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3493 * require all three components to be present and zero if they are unused.
3495 if (coord_components
> 0 &&
3496 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3497 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3498 for (unsigned i
= coord_components
; i
< 3; i
++)
3499 bld
.MOV(offset(msg_end
, bld
, i
), fs_reg(0.0f
));
3501 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3504 if (op
== SHADER_OPCODE_TXD
) {
3505 /* TXD unsupported in SIMD16 mode. */
3506 assert(bld
.dispatch_width() == 8);
3508 /* the slots for u and v are always present, but r is optional */
3509 if (coord_components
< 2)
3510 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3513 * dPdx = dudx, dvdx, drdx
3514 * dPdy = dudy, dvdy, drdy
3516 * 1-arg: Does not exist.
3518 * 2-arg: dudx dvdx dudy dvdy
3519 * dPdx.x dPdx.y dPdy.x dPdy.y
3522 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3523 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3524 * m5 m6 m7 m8 m9 m10
3526 for (unsigned i
= 0; i
< grad_components
; i
++)
3527 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3529 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3531 for (unsigned i
= 0; i
< grad_components
; i
++)
3532 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3534 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3538 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3539 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3541 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3542 bld
.dispatch_width() == 16);
3544 const brw_reg_type type
=
3545 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3546 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3547 bld
.MOV(retype(msg_end
, type
), lod
);
3548 msg_end
= offset(msg_end
, bld
, 1);
3551 if (shadow_c
.file
!= BAD_FILE
) {
3552 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3553 /* There's no plain shadow compare message, so we use shadow
3554 * compare with a bias of 0.0.
3556 bld
.MOV(msg_end
, fs_reg(0.0f
));
3557 msg_end
= offset(msg_end
, bld
, 1);
3560 bld
.MOV(msg_end
, shadow_c
);
3561 msg_end
= offset(msg_end
, bld
, 1);
3565 inst
->src
[0] = reg_undef
;
3566 inst
->src
[1] = sampler
;
3567 inst
->resize_sources(2);
3568 inst
->base_mrf
= msg_begin
.reg
;
3569 inst
->mlen
= msg_end
.reg
- msg_begin
.reg
;
3570 inst
->header_size
= 1;
3574 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3576 const fs_reg
&shadow_c
,
3577 fs_reg lod
, fs_reg lod2
,
3578 const fs_reg
&sample_index
,
3579 const fs_reg
&sampler
,
3580 const fs_reg
&offset_value
,
3581 unsigned coord_components
,
3582 unsigned grad_components
)
3584 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3585 fs_reg msg_coords
= message
;
3586 unsigned header_size
= 0;
3588 if (offset_value
.file
!= BAD_FILE
) {
3589 /* The offsets set up by the visitor are in the m1 header, so we can't
3596 for (unsigned i
= 0; i
< coord_components
; i
++) {
3597 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3598 coordinate
= offset(coordinate
, bld
, 1);
3600 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3601 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3603 if (shadow_c
.file
!= BAD_FILE
) {
3604 fs_reg msg_shadow
= msg_lod
;
3605 bld
.MOV(msg_shadow
, shadow_c
);
3606 msg_lod
= offset(msg_shadow
, bld
, 1);
3611 case SHADER_OPCODE_TXL
:
3613 bld
.MOV(msg_lod
, lod
);
3614 msg_end
= offset(msg_lod
, bld
, 1);
3616 case SHADER_OPCODE_TXD
:
3619 * dPdx = dudx, dvdx, drdx
3620 * dPdy = dudy, dvdy, drdy
3622 * Load up these values:
3623 * - dudx dudy dvdx dvdy drdx drdy
3624 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3627 for (unsigned i
= 0; i
< grad_components
; i
++) {
3628 bld
.MOV(msg_end
, lod
);
3629 lod
= offset(lod
, bld
, 1);
3630 msg_end
= offset(msg_end
, bld
, 1);
3632 bld
.MOV(msg_end
, lod2
);
3633 lod2
= offset(lod2
, bld
, 1);
3634 msg_end
= offset(msg_end
, bld
, 1);
3637 case SHADER_OPCODE_TXS
:
3638 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3639 bld
.MOV(msg_lod
, lod
);
3640 msg_end
= offset(msg_lod
, bld
, 1);
3642 case SHADER_OPCODE_TXF
:
3643 msg_lod
= offset(msg_coords
, bld
, 3);
3644 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3645 msg_end
= offset(msg_lod
, bld
, 1);
3647 case SHADER_OPCODE_TXF_CMS
:
3648 msg_lod
= offset(msg_coords
, bld
, 3);
3650 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), fs_reg(0u));
3652 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3653 msg_end
= offset(msg_lod
, bld
, 2);
3660 inst
->src
[0] = reg_undef
;
3661 inst
->src
[1] = sampler
;
3662 inst
->resize_sources(2);
3663 inst
->base_mrf
= message
.reg
;
3664 inst
->mlen
= msg_end
.reg
- message
.reg
;
3665 inst
->header_size
= header_size
;
3667 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3668 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3672 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3674 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3677 return sampler
.file
!= IMM
|| sampler
.fixed_hw_reg
.dw1
.ud
>= 16;
3681 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3683 const fs_reg
&shadow_c
,
3684 fs_reg lod
, fs_reg lod2
,
3685 const fs_reg
&sample_index
,
3686 const fs_reg
&mcs
, const fs_reg
&sampler
,
3687 fs_reg offset_value
,
3688 unsigned coord_components
,
3689 unsigned grad_components
)
3691 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3692 int reg_width
= bld
.dispatch_width() / 8;
3693 unsigned header_size
= 0, length
= 0;
3694 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3695 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3696 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3698 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3699 offset_value
.file
!= BAD_FILE
||
3700 is_high_sampler(devinfo
, sampler
)) {
3701 /* For general texture offsets (no txf workaround), we need a header to
3702 * put them in. Note that we're only reserving space for it in the
3703 * message payload as it will be initialized implicitly by the
3706 * TG4 needs to place its channel select in the header, for interaction
3707 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3708 * larger sampler numbers we need to offset the Sampler State Pointer in
3712 sources
[0] = fs_reg();
3716 if (shadow_c
.file
!= BAD_FILE
) {
3717 bld
.MOV(sources
[length
], shadow_c
);
3721 bool coordinate_done
= false;
3723 /* The sampler can only meaningfully compute LOD for fragment shader
3724 * messages. For all other stages, we change the opcode to TXL and
3725 * hardcode the LOD to 0.
3727 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3728 op
== SHADER_OPCODE_TEX
) {
3729 op
= SHADER_OPCODE_TXL
;
3733 /* Set up the LOD info */
3736 case SHADER_OPCODE_TXL
:
3737 bld
.MOV(sources
[length
], lod
);
3740 case SHADER_OPCODE_TXD
:
3741 /* TXD should have been lowered in SIMD16 mode. */
3742 assert(bld
.dispatch_width() == 8);
3744 /* Load dPdx and the coordinate together:
3745 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3747 for (unsigned i
= 0; i
< coord_components
; i
++) {
3748 bld
.MOV(sources
[length
], coordinate
);
3749 coordinate
= offset(coordinate
, bld
, 1);
3752 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3753 * only derivatives for (u, v, r).
3755 if (i
< grad_components
) {
3756 bld
.MOV(sources
[length
], lod
);
3757 lod
= offset(lod
, bld
, 1);
3760 bld
.MOV(sources
[length
], lod2
);
3761 lod2
= offset(lod2
, bld
, 1);
3766 coordinate_done
= true;
3768 case SHADER_OPCODE_TXS
:
3769 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3772 case SHADER_OPCODE_TXF
:
3773 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3774 * On Gen9 they are u, v, lod, r
3776 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3777 coordinate
= offset(coordinate
, bld
, 1);
3780 if (devinfo
->gen
>= 9) {
3781 if (coord_components
>= 2) {
3782 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3783 coordinate
= offset(coordinate
, bld
, 1);
3788 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3791 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3792 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3793 coordinate
= offset(coordinate
, bld
, 1);
3797 coordinate_done
= true;
3799 case SHADER_OPCODE_TXF_CMS
:
3800 case SHADER_OPCODE_TXF_UMS
:
3801 case SHADER_OPCODE_TXF_MCS
:
3802 if (op
== SHADER_OPCODE_TXF_UMS
|| op
== SHADER_OPCODE_TXF_CMS
) {
3803 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3807 if (op
== SHADER_OPCODE_TXF_CMS
) {
3808 /* Data from the multisample control surface. */
3809 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3813 /* There is no offsetting for this message; just copy in the integer
3814 * texture coordinates.
3816 for (unsigned i
= 0; i
< coord_components
; i
++) {
3817 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3818 coordinate
= offset(coordinate
, bld
, 1);
3822 coordinate_done
= true;
3824 case SHADER_OPCODE_TG4_OFFSET
:
3825 /* gather4_po_c should have been lowered in SIMD16 mode. */
3826 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3828 /* More crazy intermixing */
3829 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3830 bld
.MOV(sources
[length
], coordinate
);
3831 coordinate
= offset(coordinate
, bld
, 1);
3835 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3836 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3837 offset_value
= offset(offset_value
, bld
, 1);
3841 if (coord_components
== 3) { /* r if present */
3842 bld
.MOV(sources
[length
], coordinate
);
3843 coordinate
= offset(coordinate
, bld
, 1);
3847 coordinate_done
= true;
3853 /* Set up the coordinate (except for cases where it was done above) */
3854 if (!coordinate_done
) {
3855 for (unsigned i
= 0; i
< coord_components
; i
++) {
3856 bld
.MOV(sources
[length
], coordinate
);
3857 coordinate
= offset(coordinate
, bld
, 1);
3864 mlen
= length
* reg_width
- header_size
;
3866 mlen
= length
* reg_width
;
3868 const fs_reg src_payload
= fs_reg(GRF
, bld
.shader
->alloc
.allocate(mlen
),
3869 BRW_REGISTER_TYPE_F
);
3870 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
3872 /* Generate the SEND. */
3874 inst
->src
[0] = src_payload
;
3875 inst
->src
[1] = sampler
;
3876 inst
->resize_sources(2);
3877 inst
->base_mrf
= -1;
3879 inst
->header_size
= header_size
;
3881 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3882 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3886 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
3888 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3889 const fs_reg
&coordinate
= inst
->src
[0];
3890 const fs_reg
&shadow_c
= inst
->src
[1];
3891 const fs_reg
&lod
= inst
->src
[2];
3892 const fs_reg
&lod2
= inst
->src
[3];
3893 const fs_reg
&sample_index
= inst
->src
[4];
3894 const fs_reg
&mcs
= inst
->src
[5];
3895 const fs_reg
&sampler
= inst
->src
[6];
3896 const fs_reg
&offset_value
= inst
->src
[7];
3897 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
3898 const unsigned coord_components
= inst
->src
[8].fixed_hw_reg
.dw1
.ud
;
3899 const unsigned grad_components
= inst
->src
[9].fixed_hw_reg
.dw1
.ud
;
3901 if (devinfo
->gen
>= 7) {
3902 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
3903 shadow_c
, lod
, lod2
, sample_index
,
3904 mcs
, sampler
, offset_value
,
3905 coord_components
, grad_components
);
3906 } else if (devinfo
->gen
>= 5) {
3907 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
3908 shadow_c
, lod
, lod2
, sample_index
,
3909 sampler
, offset_value
,
3910 coord_components
, grad_components
);
3912 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
3913 shadow_c
, lod
, lod2
, sampler
,
3914 coord_components
, grad_components
);
3919 * Initialize the header present in some typed and untyped surface
3923 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
3925 fs_builder ubld
= bld
.exec_all().group(8, 0);
3926 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
3927 ubld
.MOV(dst
, fs_reg(0));
3928 ubld
.MOV(component(dst
, 7), sample_mask
);
3933 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3934 const fs_reg
&sample_mask
)
3936 /* Get the logical send arguments. */
3937 const fs_reg
&addr
= inst
->src
[0];
3938 const fs_reg
&src
= inst
->src
[1];
3939 const fs_reg
&surface
= inst
->src
[2];
3940 const UNUSED fs_reg
&dims
= inst
->src
[3];
3941 const fs_reg
&arg
= inst
->src
[4];
3943 /* Calculate the total number of components of the payload. */
3944 const unsigned addr_sz
= inst
->components_read(0);
3945 const unsigned src_sz
= inst
->components_read(1);
3946 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
3947 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
3949 /* Allocate space for the payload. */
3950 fs_reg
*const components
= new fs_reg
[sz
];
3951 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
3954 /* Construct the payload. */
3956 components
[n
++] = emit_surface_header(bld
, sample_mask
);
3958 for (unsigned i
= 0; i
< addr_sz
; i
++)
3959 components
[n
++] = offset(addr
, bld
, i
);
3961 for (unsigned i
= 0; i
< src_sz
; i
++)
3962 components
[n
++] = offset(src
, bld
, i
);
3964 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
3966 /* Update the original instruction. */
3968 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
3969 inst
->header_size
= header_sz
;
3971 inst
->src
[0] = payload
;
3972 inst
->src
[1] = surface
;
3974 inst
->resize_sources(3);
3976 delete[] components
;
3980 fs_visitor::lower_logical_sends()
3982 bool progress
= false;
3984 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3985 const fs_builder
ibld(this, block
, inst
);
3987 switch (inst
->opcode
) {
3988 case FS_OPCODE_FB_WRITE_LOGICAL
:
3989 assert(stage
== MESA_SHADER_FRAGMENT
);
3990 lower_fb_write_logical_send(ibld
, inst
,
3991 (const brw_wm_prog_data
*)prog_data
,
3992 (const brw_wm_prog_key
*)key
,
3996 case SHADER_OPCODE_TEX_LOGICAL
:
3997 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4000 case SHADER_OPCODE_TXD_LOGICAL
:
4001 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4004 case SHADER_OPCODE_TXF_LOGICAL
:
4005 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4008 case SHADER_OPCODE_TXL_LOGICAL
:
4009 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4012 case SHADER_OPCODE_TXS_LOGICAL
:
4013 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4016 case FS_OPCODE_TXB_LOGICAL
:
4017 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4020 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4021 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4024 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4025 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4028 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4029 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4032 case SHADER_OPCODE_LOD_LOGICAL
:
4033 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4036 case SHADER_OPCODE_TG4_LOGICAL
:
4037 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4040 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4041 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4044 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4045 lower_surface_logical_send(ibld
, inst
,
4046 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4050 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4051 lower_surface_logical_send(ibld
, inst
,
4052 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4053 ibld
.sample_mask_reg());
4056 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4057 lower_surface_logical_send(ibld
, inst
,
4058 SHADER_OPCODE_UNTYPED_ATOMIC
,
4059 ibld
.sample_mask_reg());
4062 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4063 lower_surface_logical_send(ibld
, inst
,
4064 SHADER_OPCODE_TYPED_SURFACE_READ
,
4068 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4069 lower_surface_logical_send(ibld
, inst
,
4070 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4071 ibld
.sample_mask_reg());
4074 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4075 lower_surface_logical_send(ibld
, inst
,
4076 SHADER_OPCODE_TYPED_ATOMIC
,
4077 ibld
.sample_mask_reg());
4088 invalidate_live_intervals();
4094 * Get the closest native SIMD width supported by the hardware for instruction
4095 * \p inst. The instruction will be left untouched by
4096 * fs_visitor::lower_simd_width() if the returned value is equal to the
4097 * original execution size.
4100 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4101 const fs_inst
*inst
)
4103 switch (inst
->opcode
) {
4104 case BRW_OPCODE_MOV
:
4105 case BRW_OPCODE_SEL
:
4106 case BRW_OPCODE_NOT
:
4107 case BRW_OPCODE_AND
:
4109 case BRW_OPCODE_XOR
:
4110 case BRW_OPCODE_SHR
:
4111 case BRW_OPCODE_SHL
:
4112 case BRW_OPCODE_ASR
:
4113 case BRW_OPCODE_CMP
:
4114 case BRW_OPCODE_CMPN
:
4115 case BRW_OPCODE_CSEL
:
4116 case BRW_OPCODE_F32TO16
:
4117 case BRW_OPCODE_F16TO32
:
4118 case BRW_OPCODE_BFREV
:
4119 case BRW_OPCODE_BFE
:
4120 case BRW_OPCODE_BFI1
:
4121 case BRW_OPCODE_BFI2
:
4122 case BRW_OPCODE_ADD
:
4123 case BRW_OPCODE_MUL
:
4124 case BRW_OPCODE_AVG
:
4125 case BRW_OPCODE_FRC
:
4126 case BRW_OPCODE_RNDU
:
4127 case BRW_OPCODE_RNDD
:
4128 case BRW_OPCODE_RNDE
:
4129 case BRW_OPCODE_RNDZ
:
4130 case BRW_OPCODE_LZD
:
4131 case BRW_OPCODE_FBH
:
4132 case BRW_OPCODE_FBL
:
4133 case BRW_OPCODE_CBIT
:
4134 case BRW_OPCODE_SAD2
:
4135 case BRW_OPCODE_MAD
:
4136 case BRW_OPCODE_LRP
:
4137 case SHADER_OPCODE_RCP
:
4138 case SHADER_OPCODE_RSQ
:
4139 case SHADER_OPCODE_SQRT
:
4140 case SHADER_OPCODE_EXP2
:
4141 case SHADER_OPCODE_LOG2
:
4142 case SHADER_OPCODE_POW
:
4143 case SHADER_OPCODE_INT_QUOTIENT
:
4144 case SHADER_OPCODE_INT_REMAINDER
:
4145 case SHADER_OPCODE_SIN
:
4146 case SHADER_OPCODE_COS
: {
4147 /* According to the PRMs:
4148 * "A. In Direct Addressing mode, a source cannot span more than 2
4149 * adjacent GRF registers.
4150 * B. A destination cannot span more than 2 adjacent GRF registers."
4152 * Look for the source or destination with the largest register region
4153 * which is the one that is going to limit the overal execution size of
4154 * the instruction due to this rule.
4156 unsigned reg_count
= inst
->regs_written
;
4158 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4159 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4161 /* Calculate the maximum execution size of the instruction based on the
4162 * factor by which it goes over the hardware limit of 2 GRFs.
4164 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4166 case SHADER_OPCODE_MULH
:
4167 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4168 * is 8-wide on Gen7+.
4170 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4172 case FS_OPCODE_FB_WRITE_LOGICAL
:
4173 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4176 assert(devinfo
->gen
!= 6 || inst
->src
[3].file
== BAD_FILE
||
4177 inst
->exec_size
== 8);
4178 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4179 return (inst
->src
[1].file
!= BAD_FILE
? 8 : inst
->exec_size
);
4181 case SHADER_OPCODE_TXD_LOGICAL
:
4182 /* TXD is unsupported in SIMD16 mode. */
4185 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4186 /* gather4_po_c is unsupported in SIMD16 mode. */
4187 const fs_reg
&shadow_c
= inst
->src
[1];
4188 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4190 case SHADER_OPCODE_TXL_LOGICAL
:
4191 case FS_OPCODE_TXB_LOGICAL
: {
4192 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4193 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4194 * mode because the message exceeds the maximum length of 11.
4196 const fs_reg
&shadow_c
= inst
->src
[1];
4197 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4199 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4202 return inst
->exec_size
;
4204 case SHADER_OPCODE_TXF_LOGICAL
:
4205 case SHADER_OPCODE_TXS_LOGICAL
:
4206 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4207 * messages. Use SIMD16 instead.
4209 if (devinfo
->gen
== 4)
4212 return inst
->exec_size
;
4214 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4215 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4216 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4220 return inst
->exec_size
;
4225 * The \p rows array of registers represents a \p num_rows by \p num_columns
4226 * matrix in row-major order, write it in column-major order into the register
4227 * passed as destination. \p stride gives the separation between matrix
4228 * elements in the input in fs_builder::dispatch_width() units.
4231 emit_transpose(const fs_builder
&bld
,
4232 const fs_reg
&dst
, const fs_reg
*rows
,
4233 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4235 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4237 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4238 for (unsigned j
= 0; j
< num_rows
; ++j
)
4239 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4242 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4244 delete[] components
;
4248 fs_visitor::lower_simd_width()
4250 bool progress
= false;
4252 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4253 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4255 if (lower_width
!= inst
->exec_size
) {
4256 /* Builder matching the original instruction. We may also need to
4257 * emit an instruction of width larger than the original, set the
4258 * execution size of the builder to the highest of both for now so
4259 * we're sure that both cases can be handled.
4261 const fs_builder ibld
= bld
.at(block
, inst
)
4262 .exec_all(inst
->force_writemask_all
)
4263 .group(MAX2(inst
->exec_size
, lower_width
),
4264 inst
->force_sechalf
);
4266 /* Split the copies in chunks of the execution width of either the
4267 * original or the lowered instruction, whichever is lower.
4269 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4270 const unsigned n
= inst
->exec_size
/ copy_width
;
4271 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4272 inst
->dst
.component_size(inst
->exec_size
);
4275 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4276 !inst
->writes_accumulator
&& !inst
->mlen
);
4278 for (unsigned i
= 0; i
< n
; i
++) {
4279 /* Emit a copy of the original instruction with the lowered width.
4280 * If the EOT flag was set throw it away except for the last
4281 * instruction to avoid killing the thread prematurely.
4283 fs_inst split_inst
= *inst
;
4284 split_inst
.exec_size
= lower_width
;
4285 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4287 /* Select the correct channel enables for the i-th group, then
4288 * transform the sources and destination and emit the lowered
4291 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4293 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4294 if (inst
->src
[j
].file
!= BAD_FILE
&&
4295 !is_uniform(inst
->src
[j
])) {
4296 /* Get the i-th copy_width-wide chunk of the source. */
4297 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4298 const unsigned src_size
= inst
->components_read(j
);
4300 /* Use a trivial transposition to copy one every n
4301 * copy_width-wide components of the register into a
4302 * temporary passed as source to the lowered instruction.
4304 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4305 emit_transpose(lbld
.group(copy_width
, 0),
4306 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4310 if (inst
->regs_written
) {
4311 /* Allocate enough space to hold the result of the lowered
4312 * instruction and fix up the number of registers written.
4314 split_inst
.dst
= dsts
[i
] =
4315 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4316 split_inst
.regs_written
=
4317 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4321 lbld
.emit(split_inst
);
4324 if (inst
->regs_written
) {
4325 /* Distance between useful channels in the temporaries, skipping
4326 * garbage if the lowered instruction is wider than the original.
4328 const unsigned m
= lower_width
/ copy_width
;
4330 /* Interleave the components of the result from the lowered
4331 * instructions. We need to set exec_all() when copying more than
4332 * one half per component, because LOAD_PAYLOAD (in terms of which
4333 * emit_transpose is implemented) can only use the same channel
4334 * enable signals for all of its non-header sources.
4336 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4337 .group(copy_width
, 0),
4338 inst
->dst
, dsts
, n
, dst_size
, m
);
4341 inst
->remove(block
);
4347 invalidate_live_intervals();
4353 fs_visitor::dump_instructions()
4355 dump_instructions(NULL
);
4359 fs_visitor::dump_instructions(const char *name
)
4361 FILE *file
= stderr
;
4362 if (name
&& geteuid() != 0) {
4363 file
= fopen(name
, "w");
4369 calculate_register_pressure();
4370 int ip
= 0, max_pressure
= 0;
4371 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4372 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4373 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4374 dump_instruction(inst
, file
);
4377 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4380 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4381 fprintf(file
, "%4d: ", ip
++);
4382 dump_instruction(inst
, file
);
4386 if (file
!= stderr
) {
4392 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4394 dump_instruction(be_inst
, stderr
);
4398 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4400 fs_inst
*inst
= (fs_inst
*)be_inst
;
4402 if (inst
->predicate
) {
4403 fprintf(file
, "(%cf0.%d) ",
4404 inst
->predicate_inverse
? '-' : '+',
4408 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4410 fprintf(file
, ".sat");
4411 if (inst
->conditional_mod
) {
4412 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4413 if (!inst
->predicate
&&
4414 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4415 inst
->opcode
!= BRW_OPCODE_IF
&&
4416 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4417 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4420 fprintf(file
, "(%d) ", inst
->exec_size
);
4423 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4426 switch (inst
->dst
.file
) {
4428 fprintf(file
, "vgrf%d", inst
->dst
.reg
);
4429 if (alloc
.sizes
[inst
->dst
.reg
] != inst
->regs_written
||
4430 inst
->dst
.subreg_offset
)
4431 fprintf(file
, "+%d.%d",
4432 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4435 fprintf(file
, "m%d", inst
->dst
.reg
);
4438 fprintf(file
, "(null)");
4441 fprintf(file
, "***u%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4444 fprintf(file
, "***attr%d***", inst
->dst
.reg
+ inst
->dst
.reg_offset
);
4447 if (inst
->dst
.fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4448 switch (inst
->dst
.fixed_hw_reg
.nr
) {
4450 fprintf(file
, "null");
4452 case BRW_ARF_ADDRESS
:
4453 fprintf(file
, "a0.%d", inst
->dst
.fixed_hw_reg
.subnr
);
4455 case BRW_ARF_ACCUMULATOR
:
4456 fprintf(file
, "acc%d", inst
->dst
.fixed_hw_reg
.subnr
);
4459 fprintf(file
, "f%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4460 inst
->dst
.fixed_hw_reg
.subnr
);
4463 fprintf(file
, "arf%d.%d", inst
->dst
.fixed_hw_reg
.nr
& 0xf,
4464 inst
->dst
.fixed_hw_reg
.subnr
);
4468 fprintf(file
, "hw_reg%d", inst
->dst
.fixed_hw_reg
.nr
);
4470 if (inst
->dst
.fixed_hw_reg
.subnr
)
4471 fprintf(file
, "+%d", inst
->dst
.fixed_hw_reg
.subnr
);
4474 fprintf(file
, "???");
4477 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4479 for (int i
= 0; i
< inst
->sources
; i
++) {
4480 if (inst
->src
[i
].negate
)
4482 if (inst
->src
[i
].abs
)
4484 switch (inst
->src
[i
].file
) {
4486 fprintf(file
, "vgrf%d", inst
->src
[i
].reg
);
4487 if (alloc
.sizes
[inst
->src
[i
].reg
] != (unsigned)inst
->regs_read(i
) ||
4488 inst
->src
[i
].subreg_offset
)
4489 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4490 inst
->src
[i
].subreg_offset
);
4493 fprintf(file
, "***m%d***", inst
->src
[i
].reg
);
4496 fprintf(file
, "attr%d+%d", inst
->src
[i
].reg
, inst
->src
[i
].reg_offset
);
4499 fprintf(file
, "u%d", inst
->src
[i
].reg
+ inst
->src
[i
].reg_offset
);
4500 if (inst
->src
[i
].reladdr
) {
4501 fprintf(file
, "+reladdr");
4502 } else if (inst
->src
[i
].subreg_offset
) {
4503 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4504 inst
->src
[i
].subreg_offset
);
4508 fprintf(file
, "(null)");
4511 switch (inst
->src
[i
].type
) {
4512 case BRW_REGISTER_TYPE_F
:
4513 fprintf(file
, "%ff", inst
->src
[i
].fixed_hw_reg
.dw1
.f
);
4515 case BRW_REGISTER_TYPE_W
:
4516 case BRW_REGISTER_TYPE_D
:
4517 fprintf(file
, "%dd", inst
->src
[i
].fixed_hw_reg
.dw1
.d
);
4519 case BRW_REGISTER_TYPE_UW
:
4520 case BRW_REGISTER_TYPE_UD
:
4521 fprintf(file
, "%uu", inst
->src
[i
].fixed_hw_reg
.dw1
.ud
);
4523 case BRW_REGISTER_TYPE_VF
:
4524 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4525 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 0) & 0xff),
4526 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 8) & 0xff),
4527 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 16) & 0xff),
4528 brw_vf_to_float((inst
->src
[i
].fixed_hw_reg
.dw1
.ud
>> 24) & 0xff));
4531 fprintf(file
, "???");
4536 if (inst
->src
[i
].fixed_hw_reg
.negate
)
4538 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4540 if (inst
->src
[i
].fixed_hw_reg
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
4541 switch (inst
->src
[i
].fixed_hw_reg
.nr
) {
4543 fprintf(file
, "null");
4545 case BRW_ARF_ADDRESS
:
4546 fprintf(file
, "a0.%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4548 case BRW_ARF_ACCUMULATOR
:
4549 fprintf(file
, "acc%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4552 fprintf(file
, "f%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4553 inst
->src
[i
].fixed_hw_reg
.subnr
);
4556 fprintf(file
, "arf%d.%d", inst
->src
[i
].fixed_hw_reg
.nr
& 0xf,
4557 inst
->src
[i
].fixed_hw_reg
.subnr
);
4561 fprintf(file
, "hw_reg%d", inst
->src
[i
].fixed_hw_reg
.nr
);
4563 if (inst
->src
[i
].fixed_hw_reg
.subnr
)
4564 fprintf(file
, "+%d", inst
->src
[i
].fixed_hw_reg
.subnr
);
4565 if (inst
->src
[i
].fixed_hw_reg
.abs
)
4569 fprintf(file
, "???");
4572 if (inst
->src
[i
].abs
)
4575 if (inst
->src
[i
].file
!= IMM
) {
4576 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4579 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4580 fprintf(file
, ", ");
4585 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4586 if (inst
->force_sechalf
)
4587 fprintf(file
, "2ndhalf ");
4589 fprintf(file
, "1sthalf ");
4592 fprintf(file
, "\n");
4596 * Possibly returns an instruction that set up @param reg.
4598 * Sometimes we want to take the result of some expression/variable
4599 * dereference tree and rewrite the instruction generating the result
4600 * of the tree. When processing the tree, we know that the
4601 * instructions generated are all writing temporaries that are dead
4602 * outside of this tree. So, if we have some instructions that write
4603 * a temporary, we're free to point that temp write somewhere else.
4605 * Note that this doesn't guarantee that the instruction generated
4606 * only reg -- it might be the size=4 destination of a texture instruction.
4609 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4614 end
->is_partial_write() ||
4616 !reg
.equals(end
->dst
)) {
4624 fs_visitor::setup_payload_gen6()
4627 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4628 unsigned barycentric_interp_modes
=
4629 (stage
== MESA_SHADER_FRAGMENT
) ?
4630 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4632 assert(devinfo
->gen
>= 6);
4634 /* R0-1: masks, pixel X/Y coordinates. */
4635 payload
.num_regs
= 2;
4636 /* R2: only for 32-pixel dispatch.*/
4638 /* R3-26: barycentric interpolation coordinates. These appear in the
4639 * same order that they appear in the brw_wm_barycentric_interp_mode
4640 * enum. Each set of coordinates occupies 2 registers if dispatch width
4641 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4642 * appear if they were enabled using the "Barycentric Interpolation
4643 * Mode" bits in WM_STATE.
4645 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4646 if (barycentric_interp_modes
& (1 << i
)) {
4647 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4648 payload
.num_regs
+= 2;
4649 if (dispatch_width
== 16) {
4650 payload
.num_regs
+= 2;
4655 /* R27: interpolated depth if uses source depth */
4657 payload
.source_depth_reg
= payload
.num_regs
;
4659 if (dispatch_width
== 16) {
4660 /* R28: interpolated depth if not SIMD8. */
4664 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4666 payload
.source_w_reg
= payload
.num_regs
;
4668 if (dispatch_width
== 16) {
4669 /* R30: interpolated W if not SIMD8. */
4674 if (stage
== MESA_SHADER_FRAGMENT
) {
4675 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4676 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4677 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4678 /* R31: MSAA position offsets. */
4679 if (prog_data
->uses_pos_offset
) {
4680 payload
.sample_pos_reg
= payload
.num_regs
;
4685 /* R32: MSAA input coverage mask */
4686 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4687 assert(devinfo
->gen
>= 7);
4688 payload
.sample_mask_in_reg
= payload
.num_regs
;
4690 if (dispatch_width
== 16) {
4691 /* R33: input coverage mask if not SIMD8. */
4696 /* R34-: bary for 32-pixel. */
4697 /* R58-59: interp W for 32-pixel. */
4699 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4700 source_depth_to_render_target
= true;
4705 fs_visitor::setup_vs_payload()
4707 /* R0: thread header, R1: urb handles */
4708 payload
.num_regs
= 2;
4712 * We are building the local ID push constant data using the simplest possible
4713 * method. We simply push the local IDs directly as they should appear in the
4714 * registers for the uvec3 gl_LocalInvocationID variable.
4716 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4717 * registers worth of push constant space.
4719 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4720 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4723 * FINISHME: There are a few easy optimizations to consider.
4725 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4726 * no need for using push constant space for that dimension.
4728 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4729 * easily use 16-bit words rather than 32-bit dwords in the push constant
4732 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4733 * conveying the data, and thereby reduce push constant usage.
4737 fs_visitor::setup_cs_payload()
4739 assert(devinfo
->gen
>= 7);
4740 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4742 payload
.num_regs
= 1;
4744 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4745 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4746 payload
.local_invocation_id_reg
= payload
.num_regs
;
4747 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4752 fs_visitor::calculate_register_pressure()
4754 invalidate_live_intervals();
4755 calculate_live_intervals();
4757 unsigned num_instructions
= 0;
4758 foreach_block(block
, cfg
)
4759 num_instructions
+= block
->instructions
.length();
4761 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4763 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4764 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4765 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4770 fs_visitor::optimize()
4772 /* Start by validating the shader we currently have. */
4775 /* bld is the common builder object pointing at the end of the program we
4776 * used to translate it into i965 IR. For the optimization and lowering
4777 * passes coming next, any code added after the end of the program without
4778 * having explicitly called fs_builder::at() clearly points at a mistake.
4779 * Ideally optimization passes wouldn't be part of the visitor so they
4780 * wouldn't have access to bld at all, but they do, so just in case some
4781 * pass forgets to ask for a location explicitly set it to NULL here to
4782 * make it trip. The dispatch width is initialized to a bogus value to
4783 * make sure that optimizations set the execution controls explicitly to
4784 * match the code they are manipulating instead of relying on the defaults.
4786 bld
= fs_builder(this, 64);
4788 assign_constant_locations();
4789 demote_pull_constants();
4793 split_virtual_grfs();
4796 #define OPT(pass, args...) ({ \
4798 bool this_progress = pass(args); \
4800 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4801 char filename[64]; \
4802 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
4803 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
4805 backend_shader::dump_instructions(filename); \
4810 progress = progress || this_progress; \
4814 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
4816 snprintf(filename
, 64, "%s%d-%s-00-start",
4817 stage_abbrev
, dispatch_width
, nir
->info
.name
);
4819 backend_shader::dump_instructions(filename
);
4822 bool progress
= false;
4826 OPT(lower_simd_width
);
4827 OPT(lower_logical_sends
);
4834 OPT(remove_duplicate_mrf_writes
);
4838 OPT(opt_copy_propagate
);
4839 OPT(opt_predicated_break
, this);
4840 OPT(opt_cmod_propagation
);
4841 OPT(dead_code_eliminate
);
4842 OPT(opt_peephole_sel
);
4843 OPT(dead_control_flow_eliminate
, this);
4844 OPT(opt_register_renaming
);
4845 OPT(opt_redundant_discard_jumps
);
4846 OPT(opt_saturate_propagation
);
4847 OPT(opt_zero_samples
);
4848 OPT(register_coalesce
);
4849 OPT(compute_to_mrf
);
4850 OPT(eliminate_find_live_channel
);
4852 OPT(compact_virtual_grfs
);
4857 OPT(opt_sampler_eot
);
4859 if (OPT(lower_load_payload
)) {
4860 split_virtual_grfs();
4861 OPT(register_coalesce
);
4862 OPT(compute_to_mrf
);
4863 OPT(dead_code_eliminate
);
4866 OPT(opt_combine_constants
);
4867 OPT(lower_integer_multiplication
);
4869 lower_uniform_pull_constant_loads();
4875 * Three source instruction must have a GRF/MRF destination register.
4876 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
4879 fs_visitor::fixup_3src_null_dest()
4881 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
4882 if (inst
->is_3src() && inst
->dst
.is_null()) {
4883 inst
->dst
= fs_reg(GRF
, alloc
.allocate(dispatch_width
/ 8),
4890 fs_visitor::allocate_registers()
4892 bool allocated_without_spills
;
4894 static const enum instruction_scheduler_mode pre_modes
[] = {
4896 SCHEDULE_PRE_NON_LIFO
,
4900 /* Try each scheduling heuristic to see if it can successfully register
4901 * allocate without spilling. They should be ordered by decreasing
4902 * performance but increasing likelihood of allocating.
4904 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
4905 schedule_instructions(pre_modes
[i
]);
4908 assign_regs_trivial();
4909 allocated_without_spills
= true;
4911 allocated_without_spills
= assign_regs(false);
4913 if (allocated_without_spills
)
4917 if (!allocated_without_spills
) {
4918 /* We assume that any spilling is worse than just dropping back to
4919 * SIMD8. There's probably actually some intermediate point where
4920 * SIMD16 with a couple of spills is still better.
4922 if (dispatch_width
== 16) {
4923 fail("Failure to register allocate. Reduce number of "
4924 "live scalar values to avoid this.");
4926 compiler
->shader_perf_log(log_data
,
4927 "%s shader triggered register spilling. "
4928 "Try reducing the number of live scalar "
4929 "values to improve performance.\n",
4933 /* Since we're out of heuristics, just go spill registers until we
4934 * get an allocation.
4936 while (!assign_regs(true)) {
4942 /* This must come after all optimization and register allocation, since
4943 * it inserts dead code that happens to have side effects, and it does
4944 * so based on the actual physical registers in use.
4946 insert_gen4_send_dependency_workarounds();
4951 if (!allocated_without_spills
)
4952 schedule_instructions(SCHEDULE_POST
);
4954 if (last_scratch
> 0)
4955 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
4959 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
4961 assert(stage
== MESA_SHADER_VERTEX
);
4965 if (shader_time_index
>= 0)
4966 emit_shader_time_begin();
4973 compute_clip_distance(clip_planes
);
4977 if (shader_time_index
>= 0)
4978 emit_shader_time_end();
4984 assign_curb_setup();
4985 assign_vs_urb_setup();
4987 fixup_3src_null_dest();
4988 allocate_registers();
4994 fs_visitor::run_fs(bool do_rep_send
)
4996 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4997 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
4999 assert(stage
== MESA_SHADER_FRAGMENT
);
5001 if (devinfo
->gen
>= 6)
5002 setup_payload_gen6();
5004 setup_payload_gen4();
5008 } else if (do_rep_send
) {
5009 assert(dispatch_width
== 16);
5010 emit_repclear_shader();
5012 if (shader_time_index
>= 0)
5013 emit_shader_time_begin();
5015 calculate_urb_setup();
5016 if (nir
->info
.inputs_read
> 0) {
5017 if (devinfo
->gen
< 6)
5018 emit_interpolation_setup_gen4();
5020 emit_interpolation_setup_gen6();
5023 /* We handle discards by keeping track of the still-live pixels in f0.1.
5024 * Initialize it with the dispatched pixels.
5026 if (wm_prog_data
->uses_kill
) {
5027 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5028 discard_init
->flag_subreg
= 1;
5031 /* Generate FS IR for main(). (the visitor only descends into
5032 * functions called "main").
5039 if (wm_prog_data
->uses_kill
)
5040 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5042 if (wm_key
->alpha_test_func
)
5047 if (shader_time_index
>= 0)
5048 emit_shader_time_end();
5054 assign_curb_setup();
5057 fixup_3src_null_dest();
5058 allocate_registers();
5064 if (dispatch_width
== 8)
5065 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5067 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5073 fs_visitor::run_cs()
5075 assert(stage
== MESA_SHADER_COMPUTE
);
5079 if (shader_time_index
>= 0)
5080 emit_shader_time_begin();
5087 emit_cs_terminate();
5089 if (shader_time_index
>= 0)
5090 emit_shader_time_end();
5096 assign_curb_setup();
5098 fixup_3src_null_dest();
5099 allocate_registers();
5108 * Return a bitfield where bit n is set if barycentric interpolation mode n
5109 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5112 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5113 bool shade_model_flat
,
5114 bool persample_shading
,
5115 const nir_shader
*shader
)
5117 unsigned barycentric_interp_modes
= 0;
5119 nir_foreach_variable(var
, &shader
->inputs
) {
5120 enum glsl_interp_qualifier interp_qualifier
=
5121 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5122 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5123 bool is_sample
= var
->data
.sample
|| persample_shading
;
5124 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5125 (var
->data
.location
== VARYING_SLOT_COL1
);
5127 /* Ignore WPOS and FACE, because they don't require interpolation. */
5128 if (var
->data
.location
== VARYING_SLOT_POS
||
5129 var
->data
.location
== VARYING_SLOT_FACE
)
5132 /* Determine the set (or sets) of barycentric coordinates needed to
5133 * interpolate this variable. Note that when
5134 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5135 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5136 * for lit pixels, so we need both sets of barycentric coordinates.
5138 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5140 barycentric_interp_modes
|=
5141 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5142 } else if (is_sample
) {
5143 barycentric_interp_modes
|=
5144 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5146 if ((!is_centroid
&& !is_sample
) ||
5147 devinfo
->needs_unlit_centroid_workaround
) {
5148 barycentric_interp_modes
|=
5149 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5151 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5152 (!(shade_model_flat
&& is_gl_Color
) &&
5153 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5155 barycentric_interp_modes
|=
5156 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5157 } else if (is_sample
) {
5158 barycentric_interp_modes
|=
5159 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5161 if ((!is_centroid
&& !is_sample
) ||
5162 devinfo
->needs_unlit_centroid_workaround
) {
5163 barycentric_interp_modes
|=
5164 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5169 return barycentric_interp_modes
;
5173 computed_depth_mode(const nir_shader
*shader
)
5175 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5176 switch (shader
->info
.fs
.depth_layout
) {
5177 case FRAG_DEPTH_LAYOUT_NONE
:
5178 case FRAG_DEPTH_LAYOUT_ANY
:
5179 return BRW_PSCDEPTH_ON
;
5180 case FRAG_DEPTH_LAYOUT_GREATER
:
5181 return BRW_PSCDEPTH_ON_GE
;
5182 case FRAG_DEPTH_LAYOUT_LESS
:
5183 return BRW_PSCDEPTH_ON_LE
;
5184 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5185 return BRW_PSCDEPTH_OFF
;
5188 return BRW_PSCDEPTH_OFF
;
5192 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5194 const struct brw_wm_prog_key
*key
,
5195 struct brw_wm_prog_data
*prog_data
,
5196 const nir_shader
*shader
,
5197 struct gl_program
*prog
,
5198 int shader_time_index8
, int shader_time_index16
,
5200 unsigned *final_assembly_size
,
5203 /* key->alpha_test_func means simulating alpha testing via discards,
5204 * so the shader definitely kills pixels.
5206 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5207 prog_data
->uses_omask
=
5208 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5209 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5211 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5213 prog_data
->barycentric_interp_modes
=
5214 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5216 key
->persample_shading
,
5219 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5220 &prog_data
->base
, prog
, shader
, 8,
5221 shader_time_index8
);
5222 if (!v
.run_fs(false /* do_rep_send */)) {
5224 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5229 cfg_t
*simd16_cfg
= NULL
;
5230 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5231 &prog_data
->base
, prog
, shader
, 16,
5232 shader_time_index16
);
5233 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5234 if (!v
.simd16_unsupported
) {
5235 /* Try a SIMD16 compile */
5236 v2
.import_uniforms(&v
);
5237 if (!v2
.run_fs(use_rep_send
)) {
5238 compiler
->shader_perf_log(log_data
,
5239 "SIMD16 shader failed to compile: %s",
5242 simd16_cfg
= v2
.cfg
;
5248 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5249 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5251 prog_data
->no_8
= true;
5254 prog_data
->no_8
= false;
5257 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5258 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5260 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5261 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5262 shader
->info
.label
? shader
->info
.label
:
5264 shader
->info
.name
));
5268 g
.generate_code(simd8_cfg
, 8);
5270 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5272 return g
.get_assembly(final_assembly_size
);
5276 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5277 void *buffer
, uint32_t threads
, uint32_t stride
)
5279 if (prog_data
->local_invocation_id_regs
== 0)
5282 /* 'stride' should be an integer number of registers, that is, a multiple
5285 assert(stride
% 32 == 0);
5287 unsigned x
= 0, y
= 0, z
= 0;
5288 for (unsigned t
= 0; t
< threads
; t
++) {
5289 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5291 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5292 param
[0 * prog_data
->simd_size
+ i
] = x
;
5293 param
[1 * prog_data
->simd_size
+ i
] = y
;
5294 param
[2 * prog_data
->simd_size
+ i
] = z
;
5297 if (x
== prog_data
->local_size
[0]) {
5300 if (y
== prog_data
->local_size
[1]) {
5303 if (z
== prog_data
->local_size
[2])
5312 fs_visitor::emit_cs_local_invocation_id_setup()
5314 assert(stage
== MESA_SHADER_COMPUTE
);
5316 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5318 struct brw_reg src
=
5319 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5320 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5322 src
.nr
+= dispatch_width
/ 8;
5323 bld
.MOV(offset(*reg
, bld
, 1), src
);
5324 src
.nr
+= dispatch_width
/ 8;
5325 bld
.MOV(offset(*reg
, bld
, 2), src
);
5331 fs_visitor::emit_cs_work_group_id_setup()
5333 assert(stage
== MESA_SHADER_COMPUTE
);
5335 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5337 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5338 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5339 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5341 bld
.MOV(*reg
, r0_1
);
5342 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5343 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5349 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5351 const struct brw_cs_prog_key
*key
,
5352 struct brw_cs_prog_data
*prog_data
,
5353 const nir_shader
*shader
,
5354 int shader_time_index
,
5355 unsigned *final_assembly_size
,
5358 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5359 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5360 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5361 unsigned local_workgroup_size
=
5362 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5363 shader
->info
.cs
.local_size
[2];
5365 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5368 const char *fail_msg
= NULL
;
5370 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5372 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5373 NULL
, /* Never used in core profile */
5374 shader
, 8, shader_time_index
);
5376 fail_msg
= v8
.fail_msg
;
5377 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5379 prog_data
->simd_size
= 8;
5382 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5383 NULL
, /* Never used in core profile */
5384 shader
, 16, shader_time_index
);
5385 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5386 !fail_msg
&& !v8
.simd16_unsupported
&&
5387 local_workgroup_size
<= 16 * max_cs_threads
) {
5388 /* Try a SIMD16 compile */
5389 v16
.import_uniforms(&v8
);
5390 if (!v16
.run_cs()) {
5391 compiler
->shader_perf_log(log_data
,
5392 "SIMD16 shader failed to compile: %s",
5396 "Couldn't generate SIMD16 program and not "
5397 "enough threads for SIMD8";
5401 prog_data
->simd_size
= 16;
5405 if (unlikely(cfg
== NULL
)) {
5408 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5413 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5414 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5415 if (INTEL_DEBUG
& DEBUG_CS
) {
5416 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5417 shader
->info
.label
? shader
->info
.label
:
5420 g
.enable_debug(name
);
5423 g
.generate_code(cfg
, prog_data
->simd_size
);
5425 return g
.get_assembly(final_assembly_size
);