2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include <sys/types.h>
33 #include "util/hash_table.h"
34 #include "main/macros.h"
35 #include "main/shaderobj.h"
36 #include "main/fbobject.h"
37 #include "program/prog_parameter.h"
38 #include "program/prog_print.h"
39 #include "util/register_allocate.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "brw_vec4_gs_visitor.h"
49 #include "brw_program.h"
50 #include "brw_dead_control_flow.h"
51 #include "main/uniforms.h"
52 #include "brw_fs_live_variables.h"
53 #include "glsl/nir/glsl_types.h"
54 #include "program/sampler.h"
59 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
60 const fs_reg
*src
, unsigned sources
)
62 memset(this, 0, sizeof(*this));
64 this->src
= new fs_reg
[MAX2(sources
, 3)];
65 for (unsigned i
= 0; i
< sources
; i
++)
66 this->src
[i
] = src
[i
];
68 this->opcode
= opcode
;
70 this->sources
= sources
;
71 this->exec_size
= exec_size
;
73 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
75 assert(this->exec_size
!= 0);
77 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
79 /* This will be the case for almost all instructions. */
86 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
90 this->regs_written
= 0;
94 unreachable("Invalid destination register file");
97 this->writes_accumulator
= false;
102 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
105 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
107 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
110 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
112 init(opcode
, exec_size
, dst
, NULL
, 0);
115 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
118 const fs_reg src
[1] = { src0
};
119 init(opcode
, exec_size
, dst
, src
, 1);
122 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
123 const fs_reg
&src0
, const fs_reg
&src1
)
125 const fs_reg src
[2] = { src0
, src1
};
126 init(opcode
, exec_size
, dst
, src
, 2);
129 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
130 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
132 const fs_reg src
[3] = { src0
, src1
, src2
};
133 init(opcode
, exec_size
, dst
, src
, 3);
136 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
137 const fs_reg src
[], unsigned sources
)
139 init(opcode
, exec_width
, dst
, src
, sources
);
142 fs_inst::fs_inst(const fs_inst
&that
)
144 memcpy(this, &that
, sizeof(that
));
146 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
148 for (unsigned i
= 0; i
< that
.sources
; i
++)
149 this->src
[i
] = that
.src
[i
];
158 fs_inst::resize_sources(uint8_t num_sources
)
160 if (this->sources
!= num_sources
) {
161 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
163 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
164 src
[i
] = this->src
[i
];
168 this->sources
= num_sources
;
173 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
175 const fs_reg
&surf_index
,
176 const fs_reg
&varying_offset
,
177 uint32_t const_offset
)
179 /* We have our constant surface use a pitch of 4 bytes, so our index can
180 * be any component of a vector, and then we load 4 contiguous
181 * components starting from that.
183 * We break down the const_offset to a portion added to the variable
184 * offset and a portion done using reg_offset, which means that if you
185 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
186 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
187 * CSE can later notice that those loads are all the same and eliminate
188 * the redundant ones.
190 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
191 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~3));
194 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
195 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
196 * u, v, r) as parameters, or we can just use the SIMD16 message
197 * consisting of (header, u). We choose the second, at the cost of a
198 * longer return length.
204 if (devinfo
->gen
>= 7)
205 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
207 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
209 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
210 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
211 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
212 inst
->regs_written
= regs_written
;
214 if (devinfo
->gen
< 7) {
215 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
216 inst
->header_size
= 1;
217 if (devinfo
->gen
== 4)
220 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
223 bld
.MOV(dst
, offset(vec4_result
, bld
, (const_offset
& 3) * scale
));
227 * A helper for MOV generation for fixing up broken hardware SEND dependency
231 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
233 /* The caller always wants uncompressed to emit the minimal extra
234 * dependencies, and to avoid having to deal with aligning its regs to 2.
236 const fs_builder ubld
= bld
.annotate("send dependency resolve")
239 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
243 fs_inst::equals(fs_inst
*inst
) const
245 return (opcode
== inst
->opcode
&&
246 dst
.equals(inst
->dst
) &&
247 src
[0].equals(inst
->src
[0]) &&
248 src
[1].equals(inst
->src
[1]) &&
249 src
[2].equals(inst
->src
[2]) &&
250 saturate
== inst
->saturate
&&
251 predicate
== inst
->predicate
&&
252 conditional_mod
== inst
->conditional_mod
&&
253 mlen
== inst
->mlen
&&
254 base_mrf
== inst
->base_mrf
&&
255 target
== inst
->target
&&
257 header_size
== inst
->header_size
&&
258 shadow_compare
== inst
->shadow_compare
&&
259 exec_size
== inst
->exec_size
&&
260 offset
== inst
->offset
);
264 fs_inst::overwrites_reg(const fs_reg
®
) const
266 return reg
.in_range(dst
, regs_written
);
270 fs_inst::is_send_from_grf() const
273 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
274 case SHADER_OPCODE_SHADER_TIME_ADD
:
275 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
276 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
277 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
278 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
279 case SHADER_OPCODE_UNTYPED_ATOMIC
:
280 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
281 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
282 case SHADER_OPCODE_TYPED_ATOMIC
:
283 case SHADER_OPCODE_TYPED_SURFACE_READ
:
284 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
285 case SHADER_OPCODE_URB_WRITE_SIMD8
:
286 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
287 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
288 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
289 case SHADER_OPCODE_URB_READ_SIMD8
:
290 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
292 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
293 return src
[1].file
== VGRF
;
294 case FS_OPCODE_FB_WRITE
:
295 return src
[0].file
== VGRF
;
298 return src
[0].file
== VGRF
;
305 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
307 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
310 fs_reg reg
= this->src
[0];
311 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
314 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
317 for (int i
= 0; i
< this->sources
; i
++) {
318 reg
.type
= this->src
[i
].type
;
319 if (!this->src
[i
].equals(reg
))
322 if (i
< this->header_size
) {
325 reg
.reg_offset
+= this->exec_size
/ 8;
333 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
335 if (devinfo
->gen
== 6 && is_math())
338 if (is_send_from_grf())
341 if (!backend_instruction::can_do_source_mods())
348 fs_inst::can_change_types() const
350 return dst
.type
== src
[0].type
&&
351 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
352 (opcode
== BRW_OPCODE_MOV
||
353 (opcode
== BRW_OPCODE_SEL
&&
354 dst
.type
== src
[1].type
&&
355 predicate
!= BRW_PREDICATE_NONE
&&
356 !src
[1].abs
&& !src
[1].negate
));
360 fs_inst::has_side_effects() const
362 return this->eot
|| backend_instruction::has_side_effects();
368 memset(this, 0, sizeof(*this));
372 /** Generic unset register constructor. */
376 this->file
= BAD_FILE
;
379 fs_reg::fs_reg(struct ::brw_reg reg
) :
382 this->reg_offset
= 0;
383 this->subreg_offset
= 0;
384 this->reladdr
= NULL
;
386 if (this->file
== IMM
&&
387 (this->type
!= BRW_REGISTER_TYPE_V
&&
388 this->type
!= BRW_REGISTER_TYPE_UV
&&
389 this->type
!= BRW_REGISTER_TYPE_VF
)) {
395 fs_reg::equals(const fs_reg
&r
) const
397 return (this->backend_reg::equals(r
) &&
398 subreg_offset
== r
.subreg_offset
&&
399 !reladdr
&& !r
.reladdr
&&
404 fs_reg::set_smear(unsigned subreg
)
406 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
407 subreg_offset
= subreg
* type_sz(type
);
413 fs_reg::is_contiguous() const
419 fs_reg::component_size(unsigned width
) const
421 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
424 return MAX2(width
* stride
, 1) * type_sz(type
);
428 type_size_scalar(const struct glsl_type
*type
)
430 unsigned int size
, i
;
432 switch (type
->base_type
) {
435 case GLSL_TYPE_FLOAT
:
437 return type
->components();
438 case GLSL_TYPE_ARRAY
:
439 return type_size_scalar(type
->fields
.array
) * type
->length
;
440 case GLSL_TYPE_STRUCT
:
442 for (i
= 0; i
< type
->length
; i
++) {
443 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
446 case GLSL_TYPE_SAMPLER
:
447 /* Samplers take up no register space, since they're baked in at
451 case GLSL_TYPE_ATOMIC_UINT
:
453 case GLSL_TYPE_SUBROUTINE
:
455 case GLSL_TYPE_IMAGE
:
456 return BRW_IMAGE_PARAM_SIZE
;
458 case GLSL_TYPE_ERROR
:
459 case GLSL_TYPE_INTERFACE
:
460 case GLSL_TYPE_DOUBLE
:
461 unreachable("not reached");
468 * Returns the number of scalar components needed to store type, assuming
469 * that vectors are padded out to vec4.
471 * This has the packing rules of type_size_vec4(), but counts components
472 * similar to type_size_scalar().
475 type_size_vec4_times_4(const struct glsl_type
*type
)
477 return 4 * type_size_vec4(type
);
481 * Create a MOV to read the timestamp register.
483 * The caller is responsible for emitting the MOV. The return value is
484 * the destination of the MOV, with extra parameters set.
487 fs_visitor::get_timestamp(const fs_builder
&bld
)
489 assert(devinfo
->gen
>= 7);
491 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
494 BRW_REGISTER_TYPE_UD
));
496 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
498 /* We want to read the 3 fields we care about even if it's not enabled in
501 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
507 fs_visitor::emit_shader_time_begin()
509 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
511 /* We want only the low 32 bits of the timestamp. Since it's running
512 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
513 * which is plenty of time for our purposes. It is identical across the
514 * EUs, but since it's tracking GPU core speed it will increment at a
515 * varying rate as render P-states change.
517 shader_start_time
.set_smear(0);
521 fs_visitor::emit_shader_time_end()
523 /* Insert our code just before the final SEND with EOT. */
524 exec_node
*end
= this->instructions
.get_tail();
525 assert(end
&& ((fs_inst
*) end
)->eot
);
526 const fs_builder ibld
= bld
.annotate("shader time end")
527 .exec_all().at(NULL
, end
);
529 fs_reg shader_end_time
= get_timestamp(ibld
);
531 /* We only use the low 32 bits of the timestamp - see
532 * emit_shader_time_begin()).
534 * We could also check if render P-states have changed (or anything
535 * else that might disrupt timing) by setting smear to 2 and checking if
536 * that field is != 0.
538 shader_end_time
.set_smear(0);
540 /* Check that there weren't any timestamp reset events (assuming these
541 * were the only two timestamp reads that happened).
543 fs_reg reset
= shader_end_time
;
545 set_condmod(BRW_CONDITIONAL_Z
,
546 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
547 ibld
.IF(BRW_PREDICATE_NORMAL
);
549 fs_reg start
= shader_start_time
;
551 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
554 const fs_builder cbld
= ibld
.group(1, 0);
555 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
557 /* If there were no instructions between the two timestamp gets, the diff
558 * is 2 cycles. Remove that overhead, so I can forget about that when
559 * trying to determine the time taken for single instructions.
561 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
562 SHADER_TIME_ADD(cbld
, 0, diff
);
563 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
564 ibld
.emit(BRW_OPCODE_ELSE
);
565 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
566 ibld
.emit(BRW_OPCODE_ENDIF
);
570 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
571 int shader_time_subindex
,
574 int index
= shader_time_index
* 3 + shader_time_subindex
;
575 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
578 if (dispatch_width
== 8)
579 payload
= vgrf(glsl_type::uvec2_type
);
581 payload
= vgrf(glsl_type::uint_type
);
583 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
587 fs_visitor::vfail(const char *format
, va_list va
)
596 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
597 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
599 this->fail_msg
= msg
;
602 fprintf(stderr
, "%s", msg
);
607 fs_visitor::fail(const char *format
, ...)
611 va_start(va
, format
);
617 * Mark this program as impossible to compile in SIMD16 mode.
619 * During the SIMD8 compile (which happens first), we can detect and flag
620 * things that are unsupported in SIMD16 mode, so the compiler can skip
621 * the SIMD16 compile altogether.
623 * During a SIMD16 compile (if one happens anyway), this just calls fail().
626 fs_visitor::no16(const char *msg
)
628 if (dispatch_width
== 16) {
631 simd16_unsupported
= true;
633 compiler
->shader_perf_log(log_data
,
634 "SIMD16 shader failed to compile: %s", msg
);
639 * Returns true if the instruction has a flag that means it won't
640 * update an entire destination register.
642 * For example, dead code elimination and live variable analysis want to know
643 * when a write to a variable screens off any preceding values that were in
647 fs_inst::is_partial_write() const
649 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
650 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
651 !this->dst
.is_contiguous());
655 fs_inst::components_read(unsigned i
) const
658 case FS_OPCODE_LINTERP
:
664 case FS_OPCODE_PIXEL_X
:
665 case FS_OPCODE_PIXEL_Y
:
669 case FS_OPCODE_FB_WRITE_LOGICAL
:
670 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
671 /* First/second FB write color. */
673 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
677 case SHADER_OPCODE_TEX_LOGICAL
:
678 case SHADER_OPCODE_TXD_LOGICAL
:
679 case SHADER_OPCODE_TXF_LOGICAL
:
680 case SHADER_OPCODE_TXL_LOGICAL
:
681 case SHADER_OPCODE_TXS_LOGICAL
:
682 case FS_OPCODE_TXB_LOGICAL
:
683 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
684 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
685 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
686 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
687 case SHADER_OPCODE_LOD_LOGICAL
:
688 case SHADER_OPCODE_TG4_LOGICAL
:
689 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
690 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
691 /* Texture coordinates. */
694 /* Texture derivatives. */
695 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
697 /* Texture offset. */
701 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
706 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
707 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
708 assert(src
[3].file
== IMM
);
709 /* Surface coordinates. */
712 /* Surface operation source (ignored for reads). */
718 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
719 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
720 assert(src
[3].file
== IMM
&&
722 /* Surface coordinates. */
725 /* Surface operation source. */
731 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
732 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
733 assert(src
[3].file
== IMM
&&
735 const unsigned op
= src
[4].ud
;
736 /* Surface coordinates. */
739 /* Surface operation source. */
740 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
742 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
743 op
== BRW_AOP_PREDEC
))
755 fs_inst::regs_read(int arg
) const
758 case FS_OPCODE_FB_WRITE
:
759 case SHADER_OPCODE_URB_WRITE_SIMD8
:
760 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
761 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
762 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
763 case SHADER_OPCODE_URB_READ_SIMD8
:
764 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
765 case SHADER_OPCODE_UNTYPED_ATOMIC
:
766 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
767 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
768 case SHADER_OPCODE_TYPED_ATOMIC
:
769 case SHADER_OPCODE_TYPED_SURFACE_READ
:
770 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
771 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
776 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
777 /* The payload is actually stored in src1 */
782 case FS_OPCODE_LINTERP
:
787 case SHADER_OPCODE_LOAD_PAYLOAD
:
788 if (arg
< this->header_size
)
792 case CS_OPCODE_CS_TERMINATE
:
793 case SHADER_OPCODE_BARRIER
:
796 case SHADER_OPCODE_MOV_INDIRECT
:
798 assert(src
[2].file
== IMM
);
799 unsigned region_length
= src
[2].ud
;
801 if (src
[0].file
== FIXED_GRF
) {
802 /* If the start of the region is not register aligned, then
803 * there's some portion of the register that's technically
804 * unread at the beginning.
806 * However, the register allocator works in terms of whole
807 * registers, and does not use subnr. It assumes that the
808 * read starts at the beginning of the register, and extends
809 * regs_read() whole registers beyond that.
811 * To compensate, we extend the region length to include this
812 * unread portion at the beginning.
815 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
817 return DIV_ROUND_UP(region_length
, REG_SIZE
);
819 assert(!"Invalid register file");
825 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
830 switch (src
[arg
].file
) {
840 return DIV_ROUND_UP(components_read(arg
) *
841 src
[arg
].component_size(exec_size
),
844 unreachable("MRF registers are not allowed as sources");
850 fs_inst::reads_flag() const
856 fs_inst::writes_flag() const
858 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
859 opcode
!= BRW_OPCODE_IF
&&
860 opcode
!= BRW_OPCODE_WHILE
)) ||
861 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
865 * Returns how many MRFs an FS opcode will write over.
867 * Note that this is not the 0 or 1 implied writes in an actual gen
868 * instruction -- the FS opcodes often generate MOVs in addition.
871 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
876 if (inst
->base_mrf
== -1)
879 switch (inst
->opcode
) {
880 case SHADER_OPCODE_RCP
:
881 case SHADER_OPCODE_RSQ
:
882 case SHADER_OPCODE_SQRT
:
883 case SHADER_OPCODE_EXP2
:
884 case SHADER_OPCODE_LOG2
:
885 case SHADER_OPCODE_SIN
:
886 case SHADER_OPCODE_COS
:
887 return 1 * dispatch_width
/ 8;
888 case SHADER_OPCODE_POW
:
889 case SHADER_OPCODE_INT_QUOTIENT
:
890 case SHADER_OPCODE_INT_REMAINDER
:
891 return 2 * dispatch_width
/ 8;
892 case SHADER_OPCODE_TEX
:
894 case SHADER_OPCODE_TXD
:
895 case SHADER_OPCODE_TXF
:
896 case SHADER_OPCODE_TXF_CMS
:
897 case SHADER_OPCODE_TXF_CMS_W
:
898 case SHADER_OPCODE_TXF_MCS
:
899 case SHADER_OPCODE_TG4
:
900 case SHADER_OPCODE_TG4_OFFSET
:
901 case SHADER_OPCODE_TXL
:
902 case SHADER_OPCODE_TXS
:
903 case SHADER_OPCODE_LOD
:
904 case SHADER_OPCODE_SAMPLEINFO
:
906 case FS_OPCODE_FB_WRITE
:
908 case FS_OPCODE_GET_BUFFER_SIZE
:
909 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
910 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
912 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
914 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
916 case SHADER_OPCODE_UNTYPED_ATOMIC
:
917 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
918 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
919 case SHADER_OPCODE_TYPED_ATOMIC
:
920 case SHADER_OPCODE_TYPED_SURFACE_READ
:
921 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
922 case SHADER_OPCODE_URB_WRITE_SIMD8
:
923 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
924 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
925 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
926 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
927 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
928 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
929 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
932 unreachable("not reached");
937 fs_visitor::vgrf(const glsl_type
*const type
)
939 int reg_width
= dispatch_width
/ 8;
940 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
941 brw_type_for_base_type(type
));
944 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
949 this->type
= BRW_REGISTER_TYPE_F
;
950 this->stride
= (file
== UNIFORM
? 0 : 1);
953 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
959 this->stride
= (file
== UNIFORM
? 0 : 1);
962 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
963 * This brings in those uniform definitions
966 fs_visitor::import_uniforms(fs_visitor
*v
)
968 this->push_constant_loc
= v
->push_constant_loc
;
969 this->pull_constant_loc
= v
->pull_constant_loc
;
970 this->uniforms
= v
->uniforms
;
971 this->param_size
= v
->param_size
;
975 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
976 bool origin_upper_left
)
978 assert(stage
== MESA_SHADER_FRAGMENT
);
979 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
980 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
982 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
985 if (pixel_center_integer
) {
986 bld
.MOV(wpos
, this->pixel_x
);
988 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
990 wpos
= offset(wpos
, bld
, 1);
993 if (!flip
&& pixel_center_integer
) {
994 bld
.MOV(wpos
, this->pixel_y
);
996 fs_reg pixel_y
= this->pixel_y
;
997 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1000 pixel_y
.negate
= true;
1001 offset
+= key
->drawable_height
- 1.0f
;
1004 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1006 wpos
= offset(wpos
, bld
, 1);
1008 /* gl_FragCoord.z */
1009 if (devinfo
->gen
>= 6) {
1010 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1012 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1013 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1014 interp_reg(VARYING_SLOT_POS
, 2));
1016 wpos
= offset(wpos
, bld
, 1);
1018 /* gl_FragCoord.w: Already set up in emit_interpolation */
1019 bld
.MOV(wpos
, this->wpos_w
);
1025 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1026 glsl_interp_qualifier interpolation_mode
,
1027 bool is_centroid
, bool is_sample
)
1029 brw_wm_barycentric_interp_mode barycoord_mode
;
1030 if (devinfo
->gen
>= 6) {
1032 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1033 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1035 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1036 } else if (is_sample
) {
1037 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1038 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1040 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1042 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1043 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1045 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1048 /* On Ironlake and below, there is only one interpolation mode.
1049 * Centroid interpolation doesn't mean anything on this hardware --
1050 * there is no multisampling.
1052 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1054 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1055 this->delta_xy
[barycoord_mode
], interp
);
1059 fs_visitor::emit_general_interpolation(fs_reg attr
, const char *name
,
1060 const glsl_type
*type
,
1061 glsl_interp_qualifier interpolation_mode
,
1062 int location
, bool mod_centroid
,
1065 attr
.type
= brw_type_for_base_type(type
->get_scalar_type());
1067 assert(stage
== MESA_SHADER_FRAGMENT
);
1068 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1069 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1071 unsigned int array_elements
;
1073 if (type
->is_array()) {
1074 array_elements
= type
->arrays_of_arrays_size();
1075 if (array_elements
== 0) {
1076 fail("dereferenced array '%s' has length 0\n", name
);
1078 type
= type
->without_array();
1083 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1085 location
== VARYING_SLOT_COL0
|| location
== VARYING_SLOT_COL1
;
1086 if (key
->flat_shade
&& is_gl_Color
) {
1087 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1089 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1093 for (unsigned int i
= 0; i
< array_elements
; i
++) {
1094 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
1095 if (prog_data
->urb_setup
[location
] == -1) {
1096 /* If there's no incoming setup data for this slot, don't
1097 * emit interpolation for it.
1099 attr
= offset(attr
, bld
, type
->vector_elements
);
1104 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1105 /* Constant interpolation (flat shading) case. The SF has
1106 * handed us defined values in only the constant offset
1107 * field of the setup reg.
1109 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1110 struct brw_reg interp
= interp_reg(location
, k
);
1111 interp
= suboffset(interp
, 3);
1112 interp
.type
= attr
.type
;
1113 bld
.emit(FS_OPCODE_CINTERP
, attr
, fs_reg(interp
));
1114 attr
= offset(attr
, bld
, 1);
1117 /* Smooth/noperspective interpolation case. */
1118 for (unsigned int k
= 0; k
< type
->vector_elements
; k
++) {
1119 struct brw_reg interp
= interp_reg(location
, k
);
1120 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1121 /* Get the pixel/sample mask into f0 so that we know
1122 * which pixels are lit. Then, for each channel that is
1123 * unlit, replace the centroid data with non-centroid
1126 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1129 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1131 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1132 inst
->predicate_inverse
= true;
1133 if (devinfo
->has_pln
)
1134 inst
->no_dd_clear
= true;
1136 inst
= emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1137 mod_centroid
&& !key
->persample_shading
,
1138 mod_sample
|| key
->persample_shading
);
1139 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1140 inst
->predicate_inverse
= false;
1141 if (devinfo
->has_pln
)
1142 inst
->no_dd_check
= true;
1145 emit_linterp(attr
, fs_reg(interp
), interpolation_mode
,
1146 mod_centroid
&& !key
->persample_shading
,
1147 mod_sample
|| key
->persample_shading
);
1149 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1150 bld
.MUL(attr
, attr
, this->pixel_w
);
1152 attr
= offset(attr
, bld
, 1);
1162 fs_visitor::emit_frontfacing_interpolation()
1164 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1166 if (devinfo
->gen
>= 6) {
1167 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1168 * a boolean result from this (~0/true or 0/false).
1170 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1171 * this task in only one instruction:
1172 * - a negation source modifier will flip the bit; and
1173 * - a W -> D type conversion will sign extend the bit into the high
1174 * word of the destination.
1176 * An ASR 15 fills the low word of the destination.
1178 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1181 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1183 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1184 * a boolean result from this (1/true or 0/false).
1186 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1187 * the negation source modifier to flip it. Unfortunately the SHR
1188 * instruction only operates on UD (or D with an abs source modifier)
1189 * sources without negation.
1191 * Instead, use ASR (which will give ~0/true or 0/false).
1193 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1196 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1203 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1205 assert(stage
== MESA_SHADER_FRAGMENT
);
1206 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1207 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1209 if (key
->compute_pos_offset
) {
1210 /* Convert int_sample_pos to floating point */
1211 bld
.MOV(dst
, int_sample_pos
);
1212 /* Scale to the range [0, 1] */
1213 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1216 /* From ARB_sample_shading specification:
1217 * "When rendering to a non-multisample buffer, or if multisample
1218 * rasterization is disabled, gl_SamplePosition will always be
1221 bld
.MOV(dst
, brw_imm_f(0.5f
));
1226 fs_visitor::emit_samplepos_setup()
1228 assert(devinfo
->gen
>= 6);
1230 const fs_builder abld
= bld
.annotate("compute sample position");
1231 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1233 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1234 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1236 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1237 * mode will be enabled.
1239 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1240 * R31.1:0 Position Offset X/Y for Slot[3:0]
1241 * R31.3:2 Position Offset X/Y for Slot[7:4]
1244 * The X, Y sample positions come in as bytes in thread payload. So, read
1245 * the positions using vstride=16, width=8, hstride=2.
1247 struct brw_reg sample_pos_reg
=
1248 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1249 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1251 if (dispatch_width
== 8) {
1252 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1254 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1255 abld
.half(1).MOV(half(int_sample_x
, 1),
1256 fs_reg(suboffset(sample_pos_reg
, 16)));
1258 /* Compute gl_SamplePosition.x */
1259 compute_sample_position(pos
, int_sample_x
);
1260 pos
= offset(pos
, abld
, 1);
1261 if (dispatch_width
== 8) {
1262 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1264 abld
.half(0).MOV(half(int_sample_y
, 0),
1265 fs_reg(suboffset(sample_pos_reg
, 1)));
1266 abld
.half(1).MOV(half(int_sample_y
, 1),
1267 fs_reg(suboffset(sample_pos_reg
, 17)));
1269 /* Compute gl_SamplePosition.y */
1270 compute_sample_position(pos
, int_sample_y
);
1275 fs_visitor::emit_sampleid_setup()
1277 assert(stage
== MESA_SHADER_FRAGMENT
);
1278 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1279 assert(devinfo
->gen
>= 6);
1281 const fs_builder abld
= bld
.annotate("compute sample id");
1282 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1284 if (key
->compute_sample_id
) {
1285 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1287 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1289 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1290 * 8x multisampling, subspan 0 will represent sample N (where N
1291 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1292 * 7. We can find the value of N by looking at R0.0 bits 7:6
1293 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1294 * (since samples are always delivered in pairs). That is, we
1295 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1296 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1297 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1298 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1299 * populating a temporary variable with the sequence (0, 1, 2, 3),
1300 * and then reading from it using vstride=1, width=4, hstride=0.
1301 * These computations hold good for 4x multisampling as well.
1303 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1304 * the first four slots are sample 0 of subspan 0; the next four
1305 * are sample 1 of subspan 0; the third group is sample 0 of
1306 * subspan 1, and finally sample 1 of subspan 1.
1309 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1310 * accomodate 16x MSAA.
1312 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1314 abld
.exec_all().group(1, 0)
1315 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1316 brw_imm_ud(sspi_mask
));
1317 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1319 /* This works for both SIMD8 and SIMD16 */
1320 abld
.exec_all().group(4, 0)
1321 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1323 /* This special instruction takes care of setting vstride=1,
1324 * width=4, hstride=0 of t2 during an ADD instruction.
1326 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1328 /* As per GL_ARB_sample_shading specification:
1329 * "When rendering to a non-multisample buffer, or if multisample
1330 * rasterization is disabled, gl_SampleID will always be zero."
1332 abld
.MOV(*reg
, brw_imm_d(0));
1339 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1341 if (!src
.abs
&& !src
.negate
)
1344 fs_reg temp
= bld
.vgrf(src
.type
);
1351 fs_visitor::emit_discard_jump()
1353 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1355 /* For performance, after a discard, jump to the end of the
1356 * shader if all relevant channels have been discarded.
1358 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1359 discard_jump
->flag_subreg
= 1;
1361 discard_jump
->predicate
= (dispatch_width
== 8)
1362 ? BRW_PREDICATE_ALIGN1_ANY8H
1363 : BRW_PREDICATE_ALIGN1_ANY16H
;
1364 discard_jump
->predicate_inverse
= true;
1368 fs_visitor::emit_gs_thread_end()
1370 assert(stage
== MESA_SHADER_GEOMETRY
);
1372 struct brw_gs_prog_data
*gs_prog_data
=
1373 (struct brw_gs_prog_data
*) prog_data
;
1375 if (gs_compile
->control_data_header_size_bits
> 0) {
1376 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1379 const fs_builder abld
= bld
.annotate("thread end");
1382 if (gs_prog_data
->static_vertex_count
!= -1) {
1383 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1384 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1385 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1386 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1387 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1390 /* Delete now dead instructions. */
1391 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1397 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1401 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1402 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1403 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1406 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1407 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1408 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1409 sources
[1] = this->final_gs_vertex_count
;
1410 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1411 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1419 fs_visitor::assign_curb_setup()
1421 if (dispatch_width
== 8) {
1422 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1424 if (stage
== MESA_SHADER_FRAGMENT
) {
1425 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1426 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1427 } else if (stage
== MESA_SHADER_COMPUTE
) {
1428 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1429 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1431 unreachable("Unsupported shader type!");
1435 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1437 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1438 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1439 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1440 if (inst
->src
[i
].file
== UNIFORM
) {
1441 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1443 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1444 constant_nr
= push_constant_loc
[uniform_nr
];
1446 /* Section 5.11 of the OpenGL 4.1 spec says:
1447 * "Out-of-bounds reads return undefined values, which include
1448 * values from other variables of the active program or zero."
1449 * Just return the first push constant.
1454 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1457 brw_reg
.abs
= inst
->src
[i
].abs
;
1458 brw_reg
.negate
= inst
->src
[i
].negate
;
1460 assert(inst
->src
[i
].stride
== 0);
1461 inst
->src
[i
] = byte_offset(
1462 retype(brw_reg
, inst
->src
[i
].type
),
1463 inst
->src
[i
].subreg_offset
);
1468 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1469 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1473 fs_visitor::calculate_urb_setup()
1475 assert(stage
== MESA_SHADER_FRAGMENT
);
1476 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1477 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1479 memset(prog_data
->urb_setup
, -1,
1480 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1483 /* Figure out where each of the incoming setup attributes lands. */
1484 if (devinfo
->gen
>= 6) {
1485 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1486 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1487 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1488 * first 16 varying inputs, so we can put them wherever we want.
1489 * Just put them in order.
1491 * This is useful because it means that (a) inputs not used by the
1492 * fragment shader won't take up valuable register space, and (b) we
1493 * won't have to recompile the fragment shader if it gets paired with
1494 * a different vertex (or geometry) shader.
1496 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1497 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1498 BITFIELD64_BIT(i
)) {
1499 prog_data
->urb_setup
[i
] = urb_next
++;
1503 bool include_vue_header
=
1504 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1506 /* We have enough input varyings that the SF/SBE pipeline stage can't
1507 * arbitrarily rearrange them to suit our whim; we have to put them
1508 * in an order that matches the output of the previous pipeline stage
1509 * (geometry or vertex shader).
1511 struct brw_vue_map prev_stage_vue_map
;
1512 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1513 key
->input_slots_valid
,
1514 nir
->info
.separate_shader
);
1516 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1518 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1519 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1521 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1522 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1523 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1524 BITFIELD64_BIT(varying
))) {
1525 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1528 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1531 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1532 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1533 /* Point size is packed into the header, not as a general attribute */
1534 if (i
== VARYING_SLOT_PSIZ
)
1537 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1538 /* The back color slot is skipped when the front color is
1539 * also written to. In addition, some slots can be
1540 * written in the vertex shader and not read in the
1541 * fragment shader. So the register number must always be
1542 * incremented, mapped or not.
1544 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1545 prog_data
->urb_setup
[i
] = urb_next
;
1551 * It's a FS only attribute, and we did interpolation for this attribute
1552 * in SF thread. So, count it here, too.
1554 * See compile_sf_prog() for more info.
1556 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1557 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1560 prog_data
->num_varying_inputs
= urb_next
;
1564 fs_visitor::assign_urb_setup()
1566 assert(stage
== MESA_SHADER_FRAGMENT
);
1567 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1569 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1571 /* Offset all the urb_setup[] index by the actual position of the
1572 * setup regs, now that the location of the constants has been chosen.
1574 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1575 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1576 assert(inst
->src
[1].file
== FIXED_GRF
);
1577 inst
->src
[1].nr
+= urb_start
;
1580 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1581 assert(inst
->src
[0].file
== FIXED_GRF
);
1582 inst
->src
[0].nr
+= urb_start
;
1586 /* Each attribute is 4 setup channels, each of which is half a reg. */
1587 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1591 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1593 for (int i
= 0; i
< inst
->sources
; i
++) {
1594 if (inst
->src
[i
].file
== ATTR
) {
1595 int grf
= payload
.num_regs
+
1596 prog_data
->curb_read_length
+
1598 inst
->src
[i
].reg_offset
;
1600 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1601 struct brw_reg reg
=
1602 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1603 inst
->src
[i
].subreg_offset
),
1604 inst
->exec_size
* inst
->src
[i
].stride
,
1605 width
, inst
->src
[i
].stride
);
1606 reg
.abs
= inst
->src
[i
].abs
;
1607 reg
.negate
= inst
->src
[i
].negate
;
1615 fs_visitor::assign_vs_urb_setup()
1617 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1619 assert(stage
== MESA_SHADER_VERTEX
);
1620 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1621 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1624 /* Each attribute is 4 regs. */
1625 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1627 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1629 /* Rewrite all ATTR file references to the hw grf that they land in. */
1630 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1631 convert_attr_sources_to_hw_regs(inst
);
1636 fs_visitor::assign_gs_urb_setup()
1638 assert(stage
== MESA_SHADER_GEOMETRY
);
1640 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1642 first_non_payload_grf
+=
1643 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1645 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1646 /* Rewrite all ATTR file references to GRFs. */
1647 convert_attr_sources_to_hw_regs(inst
);
1653 * Split large virtual GRFs into separate components if we can.
1655 * This is mostly duplicated with what brw_fs_vector_splitting does,
1656 * but that's really conservative because it's afraid of doing
1657 * splitting that doesn't result in real progress after the rest of
1658 * the optimization phases, which would cause infinite looping in
1659 * optimization. We can do it once here, safely. This also has the
1660 * opportunity to split interpolated values, or maybe even uniforms,
1661 * which we don't have at the IR level.
1663 * We want to split, because virtual GRFs are what we register
1664 * allocate and spill (due to contiguousness requirements for some
1665 * instructions), and they're what we naturally generate in the
1666 * codegen process, but most virtual GRFs don't actually need to be
1667 * contiguous sets of GRFs. If we split, we'll end up with reduced
1668 * live intervals and better dead code elimination and coalescing.
1671 fs_visitor::split_virtual_grfs()
1673 int num_vars
= this->alloc
.count
;
1675 /* Count the total number of registers */
1677 int vgrf_to_reg
[num_vars
];
1678 for (int i
= 0; i
< num_vars
; i
++) {
1679 vgrf_to_reg
[i
] = reg_count
;
1680 reg_count
+= alloc
.sizes
[i
];
1683 /* An array of "split points". For each register slot, this indicates
1684 * if this slot can be separated from the previous slot. Every time an
1685 * instruction uses multiple elements of a register (as a source or
1686 * destination), we mark the used slots as inseparable. Then we go
1687 * through and split the registers into the smallest pieces we can.
1689 bool split_points
[reg_count
];
1690 memset(split_points
, 0, sizeof(split_points
));
1692 /* Mark all used registers as fully splittable */
1693 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1694 if (inst
->dst
.file
== VGRF
) {
1695 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1696 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1697 split_points
[reg
+ j
] = true;
1700 for (int i
= 0; i
< inst
->sources
; i
++) {
1701 if (inst
->src
[i
].file
== VGRF
) {
1702 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1703 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1704 split_points
[reg
+ j
] = true;
1709 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1710 if (inst
->dst
.file
== VGRF
) {
1711 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1712 for (int j
= 1; j
< inst
->regs_written
; j
++)
1713 split_points
[reg
+ j
] = false;
1715 for (int i
= 0; i
< inst
->sources
; i
++) {
1716 if (inst
->src
[i
].file
== VGRF
) {
1717 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1718 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1719 split_points
[reg
+ j
] = false;
1724 int new_virtual_grf
[reg_count
];
1725 int new_reg_offset
[reg_count
];
1728 for (int i
= 0; i
< num_vars
; i
++) {
1729 /* The first one should always be 0 as a quick sanity check. */
1730 assert(split_points
[reg
] == false);
1733 new_reg_offset
[reg
] = 0;
1738 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1739 /* If this is a split point, reset the offset to 0 and allocate a
1740 * new virtual GRF for the previous offset many registers
1742 if (split_points
[reg
]) {
1743 assert(offset
<= MAX_VGRF_SIZE
);
1744 int grf
= alloc
.allocate(offset
);
1745 for (int k
= reg
- offset
; k
< reg
; k
++)
1746 new_virtual_grf
[k
] = grf
;
1749 new_reg_offset
[reg
] = offset
;
1754 /* The last one gets the original register number */
1755 assert(offset
<= MAX_VGRF_SIZE
);
1756 alloc
.sizes
[i
] = offset
;
1757 for (int k
= reg
- offset
; k
< reg
; k
++)
1758 new_virtual_grf
[k
] = i
;
1760 assert(reg
== reg_count
);
1762 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1763 if (inst
->dst
.file
== VGRF
) {
1764 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1765 inst
->dst
.nr
= new_virtual_grf
[reg
];
1766 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1767 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1769 for (int i
= 0; i
< inst
->sources
; i
++) {
1770 if (inst
->src
[i
].file
== VGRF
) {
1771 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1772 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1773 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1774 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1778 invalidate_live_intervals();
1782 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1784 * During code generation, we create tons of temporary variables, many of
1785 * which get immediately killed and are never used again. Yet, in later
1786 * optimization and analysis passes, such as compute_live_intervals, we need
1787 * to loop over all the virtual GRFs. Compacting them can save a lot of
1791 fs_visitor::compact_virtual_grfs()
1793 bool progress
= false;
1794 int remap_table
[this->alloc
.count
];
1795 memset(remap_table
, -1, sizeof(remap_table
));
1797 /* Mark which virtual GRFs are used. */
1798 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1799 if (inst
->dst
.file
== VGRF
)
1800 remap_table
[inst
->dst
.nr
] = 0;
1802 for (int i
= 0; i
< inst
->sources
; i
++) {
1803 if (inst
->src
[i
].file
== VGRF
)
1804 remap_table
[inst
->src
[i
].nr
] = 0;
1808 /* Compact the GRF arrays. */
1810 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1811 if (remap_table
[i
] == -1) {
1812 /* We just found an unused register. This means that we are
1813 * actually going to compact something.
1817 remap_table
[i
] = new_index
;
1818 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1819 invalidate_live_intervals();
1824 this->alloc
.count
= new_index
;
1826 /* Patch all the instructions to use the newly renumbered registers */
1827 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1828 if (inst
->dst
.file
== VGRF
)
1829 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1831 for (int i
= 0; i
< inst
->sources
; i
++) {
1832 if (inst
->src
[i
].file
== VGRF
)
1833 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1837 /* Patch all the references to delta_xy, since they're used in register
1838 * allocation. If they're unused, switch them to BAD_FILE so we don't
1839 * think some random VGRF is delta_xy.
1841 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1842 if (delta_xy
[i
].file
== VGRF
) {
1843 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1844 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1846 delta_xy
[i
].file
= BAD_FILE
;
1855 * Assign UNIFORM file registers to either push constants or pull constants.
1857 * We allow a fragment shader to have more than the specified minimum
1858 * maximum number of fragment shader uniform components (64). If
1859 * there are too many of these, they'd fill up all of register space.
1860 * So, this will push some of them out to the pull constant buffer and
1861 * update the program to load them. We also use pull constants for all
1862 * indirect constant loads because we don't support indirect accesses in
1866 fs_visitor::assign_constant_locations()
1868 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1869 if (dispatch_width
!= 8)
1872 unsigned int num_pull_constants
= 0;
1874 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1875 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1877 bool is_live
[uniforms
];
1878 memset(is_live
, 0, sizeof(is_live
));
1880 /* First, we walk through the instructions and do two things:
1882 * 1) Figure out which uniforms are live.
1884 * 2) Find all indirect access of uniform arrays and flag them as needing
1885 * to go into the pull constant buffer.
1887 * Note that we don't move constant-indexed accesses to arrays. No
1888 * testing has been done of the performance impact of this choice.
1890 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1891 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1892 if (inst
->src
[i
].file
!= UNIFORM
)
1895 if (inst
->src
[i
].reladdr
) {
1896 int uniform
= inst
->src
[i
].nr
;
1898 /* If this array isn't already present in the pull constant buffer,
1901 if (pull_constant_loc
[uniform
] == -1) {
1902 assert(param_size
[uniform
]);
1903 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1904 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1907 /* Mark the the one accessed uniform as live */
1908 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1909 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1910 is_live
[constant_nr
] = true;
1915 /* Only allow 16 registers (128 uniform components) as push constants.
1917 * Just demote the end of the list. We could probably do better
1918 * here, demoting things that are rarely used in the program first.
1920 * If changing this value, note the limitation about total_regs in
1923 unsigned int max_push_components
= 16 * 8;
1924 unsigned int num_push_constants
= 0;
1926 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1928 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1929 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1930 /* This UNIFORM register is either dead, or has already been demoted
1931 * to a pull const. Mark it as no longer living in the param[] array.
1933 push_constant_loc
[i
] = -1;
1937 if (num_push_constants
< max_push_components
) {
1938 /* Retain as a push constant. Record the location in the params[]
1941 push_constant_loc
[i
] = num_push_constants
++;
1943 /* Demote to a pull constant. */
1944 push_constant_loc
[i
] = -1;
1945 pull_constant_loc
[i
] = num_pull_constants
++;
1949 stage_prog_data
->nr_params
= num_push_constants
;
1950 stage_prog_data
->nr_pull_params
= num_pull_constants
;
1952 /* Up until now, the param[] array has been indexed by reg + reg_offset
1953 * of UNIFORM registers. Move pull constants into pull_param[] and
1954 * condense param[] to only contain the uniforms we chose to push.
1956 * NOTE: Because we are condensing the params[] array, we know that
1957 * push_constant_loc[i] <= i and we can do it in one smooth loop without
1958 * having to make a copy.
1960 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1961 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
1963 if (pull_constant_loc
[i
] != -1) {
1964 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
1965 } else if (push_constant_loc
[i
] != -1) {
1966 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
1972 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
1973 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
1976 fs_visitor::demote_pull_constants()
1978 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1979 for (int i
= 0; i
< inst
->sources
; i
++) {
1980 if (inst
->src
[i
].file
!= UNIFORM
)
1984 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1985 if (location
>= uniforms
) /* Out of bounds access */
1988 pull_index
= pull_constant_loc
[location
];
1990 if (pull_index
== -1)
1993 /* Set up the annotation tracking for new generated instructions. */
1994 const fs_builder
ibld(this, block
, inst
);
1995 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
1996 fs_reg dst
= vgrf(glsl_type::float_type
);
1998 assert(inst
->src
[i
].stride
== 0);
2000 /* Generate a pull load into dst. */
2001 if (inst
->src
[i
].reladdr
) {
2002 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2004 *inst
->src
[i
].reladdr
,
2006 inst
->src
[i
].reladdr
= NULL
;
2007 inst
->src
[i
].stride
= 1;
2009 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2010 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2011 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2012 dst
, brw_imm_ud(index
), offset
);
2013 inst
->src
[i
].set_smear(pull_index
& 3);
2015 brw_mark_surface_used(prog_data
, index
);
2017 /* Rewrite the instruction to use the temporary VGRF. */
2018 inst
->src
[i
].file
= VGRF
;
2019 inst
->src
[i
].nr
= dst
.nr
;
2020 inst
->src
[i
].reg_offset
= 0;
2023 invalidate_live_intervals();
2027 fs_visitor::opt_algebraic()
2029 bool progress
= false;
2031 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2032 switch (inst
->opcode
) {
2033 case BRW_OPCODE_MOV
:
2034 if (inst
->src
[0].file
!= IMM
)
2037 if (inst
->saturate
) {
2038 if (inst
->dst
.type
!= inst
->src
[0].type
)
2039 assert(!"unimplemented: saturate mixed types");
2041 if (brw_saturate_immediate(inst
->dst
.type
,
2042 &inst
->src
[0].as_brw_reg())) {
2043 inst
->saturate
= false;
2049 case BRW_OPCODE_MUL
:
2050 if (inst
->src
[1].file
!= IMM
)
2054 if (inst
->src
[1].is_one()) {
2055 inst
->opcode
= BRW_OPCODE_MOV
;
2056 inst
->src
[1] = reg_undef
;
2062 if (inst
->src
[1].is_negative_one()) {
2063 inst
->opcode
= BRW_OPCODE_MOV
;
2064 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2065 inst
->src
[1] = reg_undef
;
2071 if (inst
->src
[1].is_zero()) {
2072 inst
->opcode
= BRW_OPCODE_MOV
;
2073 inst
->src
[0] = inst
->src
[1];
2074 inst
->src
[1] = reg_undef
;
2079 if (inst
->src
[0].file
== IMM
) {
2080 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2081 inst
->opcode
= BRW_OPCODE_MOV
;
2082 inst
->src
[0].f
*= inst
->src
[1].f
;
2083 inst
->src
[1] = reg_undef
;
2088 case BRW_OPCODE_ADD
:
2089 if (inst
->src
[1].file
!= IMM
)
2093 if (inst
->src
[1].is_zero()) {
2094 inst
->opcode
= BRW_OPCODE_MOV
;
2095 inst
->src
[1] = reg_undef
;
2100 if (inst
->src
[0].file
== IMM
) {
2101 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2102 inst
->opcode
= BRW_OPCODE_MOV
;
2103 inst
->src
[0].f
+= inst
->src
[1].f
;
2104 inst
->src
[1] = reg_undef
;
2110 if (inst
->src
[0].equals(inst
->src
[1])) {
2111 inst
->opcode
= BRW_OPCODE_MOV
;
2112 inst
->src
[1] = reg_undef
;
2117 case BRW_OPCODE_LRP
:
2118 if (inst
->src
[1].equals(inst
->src
[2])) {
2119 inst
->opcode
= BRW_OPCODE_MOV
;
2120 inst
->src
[0] = inst
->src
[1];
2121 inst
->src
[1] = reg_undef
;
2122 inst
->src
[2] = reg_undef
;
2127 case BRW_OPCODE_CMP
:
2128 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2130 inst
->src
[0].negate
&&
2131 inst
->src
[1].is_zero()) {
2132 inst
->src
[0].abs
= false;
2133 inst
->src
[0].negate
= false;
2134 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2139 case BRW_OPCODE_SEL
:
2140 if (inst
->src
[0].equals(inst
->src
[1])) {
2141 inst
->opcode
= BRW_OPCODE_MOV
;
2142 inst
->src
[1] = reg_undef
;
2143 inst
->predicate
= BRW_PREDICATE_NONE
;
2144 inst
->predicate_inverse
= false;
2146 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2147 switch (inst
->conditional_mod
) {
2148 case BRW_CONDITIONAL_LE
:
2149 case BRW_CONDITIONAL_L
:
2150 switch (inst
->src
[1].type
) {
2151 case BRW_REGISTER_TYPE_F
:
2152 if (inst
->src
[1].f
>= 1.0f
) {
2153 inst
->opcode
= BRW_OPCODE_MOV
;
2154 inst
->src
[1] = reg_undef
;
2155 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2163 case BRW_CONDITIONAL_GE
:
2164 case BRW_CONDITIONAL_G
:
2165 switch (inst
->src
[1].type
) {
2166 case BRW_REGISTER_TYPE_F
:
2167 if (inst
->src
[1].f
<= 0.0f
) {
2168 inst
->opcode
= BRW_OPCODE_MOV
;
2169 inst
->src
[1] = reg_undef
;
2170 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2182 case BRW_OPCODE_MAD
:
2183 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2184 inst
->opcode
= BRW_OPCODE_MOV
;
2185 inst
->src
[1] = reg_undef
;
2186 inst
->src
[2] = reg_undef
;
2188 } else if (inst
->src
[0].is_zero()) {
2189 inst
->opcode
= BRW_OPCODE_MUL
;
2190 inst
->src
[0] = inst
->src
[2];
2191 inst
->src
[2] = reg_undef
;
2193 } else if (inst
->src
[1].is_one()) {
2194 inst
->opcode
= BRW_OPCODE_ADD
;
2195 inst
->src
[1] = inst
->src
[2];
2196 inst
->src
[2] = reg_undef
;
2198 } else if (inst
->src
[2].is_one()) {
2199 inst
->opcode
= BRW_OPCODE_ADD
;
2200 inst
->src
[2] = reg_undef
;
2202 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2203 inst
->opcode
= BRW_OPCODE_ADD
;
2204 inst
->src
[1].f
*= inst
->src
[2].f
;
2205 inst
->src
[2] = reg_undef
;
2209 case SHADER_OPCODE_RCP
: {
2210 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2211 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2212 if (inst
->src
[0].equals(prev
->dst
)) {
2213 inst
->opcode
= SHADER_OPCODE_RSQ
;
2214 inst
->src
[0] = prev
->src
[0];
2220 case SHADER_OPCODE_BROADCAST
:
2221 if (is_uniform(inst
->src
[0])) {
2222 inst
->opcode
= BRW_OPCODE_MOV
;
2224 inst
->force_writemask_all
= true;
2226 } else if (inst
->src
[1].file
== IMM
) {
2227 inst
->opcode
= BRW_OPCODE_MOV
;
2228 inst
->src
[0] = component(inst
->src
[0],
2231 inst
->force_writemask_all
= true;
2240 /* Swap if src[0] is immediate. */
2241 if (progress
&& inst
->is_commutative()) {
2242 if (inst
->src
[0].file
== IMM
) {
2243 fs_reg tmp
= inst
->src
[1];
2244 inst
->src
[1] = inst
->src
[0];
2253 * Optimize sample messages that have constant zero values for the trailing
2254 * texture coordinates. We can just reduce the message length for these
2255 * instructions instead of reserving a register for it. Trailing parameters
2256 * that aren't sent default to zero anyway. This will cause the dead code
2257 * eliminator to remove the MOV instruction that would otherwise be emitted to
2258 * set up the zero value.
2261 fs_visitor::opt_zero_samples()
2263 /* Gen4 infers the texturing opcode based on the message length so we can't
2266 if (devinfo
->gen
< 5)
2269 bool progress
= false;
2271 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2272 if (!inst
->is_tex())
2275 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2277 if (load_payload
->is_head_sentinel() ||
2278 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2281 /* We don't want to remove the message header or the first parameter.
2282 * Removing the first parameter is not allowed, see the Haswell PRM
2283 * volume 7, page 149:
2285 * "Parameter 0 is required except for the sampleinfo message, which
2286 * has no parameter 0"
2288 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2289 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2290 (inst
->exec_size
/ 8) +
2291 inst
->header_size
- 1].is_zero()) {
2292 inst
->mlen
-= inst
->exec_size
/ 8;
2298 invalidate_live_intervals();
2304 * Optimize sample messages which are followed by the final RT write.
2306 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2307 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2308 * final texturing results copied to the framebuffer write payload and modify
2309 * them to write to the framebuffer directly.
2312 fs_visitor::opt_sampler_eot()
2314 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2316 if (stage
!= MESA_SHADER_FRAGMENT
)
2319 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2322 /* FINISHME: It should be possible to implement this optimization when there
2323 * are multiple drawbuffers.
2325 if (key
->nr_color_regions
!= 1)
2328 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2329 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2330 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2331 assert(fb_write
->eot
);
2332 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2334 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2336 /* There wasn't one; nothing to do. */
2337 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2340 /* 3D Sampler » Messages » Message Format
2342 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2343 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2345 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2346 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2347 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2348 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2349 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2352 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2353 * It's very likely to be the previous instruction.
2355 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2356 if (load_payload
->is_head_sentinel() ||
2357 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2360 assert(!tex_inst
->eot
); /* We can't get here twice */
2361 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2363 const fs_builder
ibld(this, block
, tex_inst
);
2365 tex_inst
->offset
|= fb_write
->target
<< 24;
2366 tex_inst
->eot
= true;
2367 tex_inst
->dst
= ibld
.null_reg_ud();
2368 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2370 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2371 * to create a new LOAD_PAYLOAD command with the same sources and a space
2372 * saved for the header. Using a new destination register not only makes sure
2373 * we have enough space, but it will make sure the dead code eliminator kills
2374 * the instruction that this will replace.
2376 if (tex_inst
->header_size
!= 0)
2379 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2380 load_payload
->sources
+ 1);
2381 fs_reg
*new_sources
=
2382 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2384 new_sources
[0] = fs_reg();
2385 for (int i
= 0; i
< load_payload
->sources
; i
++)
2386 new_sources
[i
+1] = load_payload
->src
[i
];
2388 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2389 * requires a lot of information about the sources to appropriately figure
2390 * out the number of registers needed to be used. Given this stage in our
2391 * optimization, we may not have the appropriate GRFs required by
2392 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2393 * manually emit the instruction.
2395 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2396 load_payload
->exec_size
,
2399 load_payload
->sources
+ 1);
2401 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2402 new_load_payload
->header_size
= 1;
2404 tex_inst
->header_size
= 1;
2405 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2406 tex_inst
->src
[0] = send_header
;
2412 fs_visitor::opt_register_renaming()
2414 bool progress
= false;
2417 int remap
[alloc
.count
];
2418 memset(remap
, -1, sizeof(int) * alloc
.count
);
2420 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2421 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2423 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2424 inst
->opcode
== BRW_OPCODE_WHILE
) {
2428 /* Rewrite instruction sources. */
2429 for (int i
= 0; i
< inst
->sources
; i
++) {
2430 if (inst
->src
[i
].file
== VGRF
&&
2431 remap
[inst
->src
[i
].nr
] != -1 &&
2432 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2433 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2438 const int dst
= inst
->dst
.nr
;
2441 inst
->dst
.file
== VGRF
&&
2442 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2443 !inst
->is_partial_write()) {
2444 if (remap
[dst
] == -1) {
2447 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2448 inst
->dst
.nr
= remap
[dst
];
2451 } else if (inst
->dst
.file
== VGRF
&&
2453 remap
[dst
] != dst
) {
2454 inst
->dst
.nr
= remap
[dst
];
2460 invalidate_live_intervals();
2462 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2463 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2464 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2473 * Remove redundant or useless discard jumps.
2475 * For example, we can eliminate jumps in the following sequence:
2477 * discard-jump (redundant with the next jump)
2478 * discard-jump (useless; jumps to the next instruction)
2482 fs_visitor::opt_redundant_discard_jumps()
2484 bool progress
= false;
2486 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2488 fs_inst
*placeholder_halt
= NULL
;
2489 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2490 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2491 placeholder_halt
= inst
;
2496 if (!placeholder_halt
)
2499 /* Delete any HALTs immediately before the placeholder halt. */
2500 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2501 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2502 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2503 prev
->remove(last_bblock
);
2508 invalidate_live_intervals();
2514 fs_visitor::compute_to_mrf()
2516 bool progress
= false;
2519 /* No MRFs on Gen >= 7. */
2520 if (devinfo
->gen
>= 7)
2523 calculate_live_intervals();
2525 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2529 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2530 inst
->is_partial_write() ||
2531 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2532 inst
->dst
.type
!= inst
->src
[0].type
||
2533 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2534 !inst
->src
[0].is_contiguous() ||
2535 inst
->src
[0].subreg_offset
)
2538 /* Work out which hardware MRF registers are written by this
2541 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2543 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2544 mrf_high
= mrf_low
+ 4;
2545 } else if (inst
->exec_size
== 16) {
2546 mrf_high
= mrf_low
+ 1;
2551 /* Can't compute-to-MRF this GRF if someone else was going to
2554 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2557 /* Found a move of a GRF to a MRF. Let's see if we can go
2558 * rewrite the thing that made this GRF to write into the MRF.
2560 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2561 if (scan_inst
->dst
.file
== VGRF
&&
2562 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2563 /* Found the last thing to write our reg we want to turn
2564 * into a compute-to-MRF.
2567 /* If this one instruction didn't populate all the
2568 * channels, bail. We might be able to rewrite everything
2569 * that writes that reg, but it would require smarter
2570 * tracking to delay the rewriting until complete success.
2572 if (scan_inst
->is_partial_write())
2575 /* Things returning more than one register would need us to
2576 * understand coalescing out more than one MOV at a time.
2578 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2581 /* SEND instructions can't have MRF as a destination. */
2582 if (scan_inst
->mlen
)
2585 if (devinfo
->gen
== 6) {
2586 /* gen6 math instructions must have the destination be
2587 * GRF, so no compute-to-MRF for them.
2589 if (scan_inst
->is_math()) {
2594 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2595 /* Found the creator of our MRF's source value. */
2596 scan_inst
->dst
.file
= MRF
;
2597 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2598 scan_inst
->saturate
|= inst
->saturate
;
2599 inst
->remove(block
);
2605 /* We don't handle control flow here. Most computation of
2606 * values that end up in MRFs are shortly before the MRF
2609 if (block
->start() == scan_inst
)
2612 /* You can't read from an MRF, so if someone else reads our
2613 * MRF's source GRF that we wanted to rewrite, that stops us.
2615 bool interfered
= false;
2616 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2617 if (scan_inst
->src
[i
].file
== VGRF
&&
2618 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2619 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2626 if (scan_inst
->dst
.file
== MRF
) {
2627 /* If somebody else writes our MRF here, we can't
2628 * compute-to-MRF before that.
2630 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2633 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2634 scan_mrf_high
= scan_mrf_low
+ 4;
2635 } else if (scan_inst
->exec_size
== 16) {
2636 scan_mrf_high
= scan_mrf_low
+ 1;
2638 scan_mrf_high
= scan_mrf_low
;
2641 if (mrf_low
== scan_mrf_low
||
2642 mrf_low
== scan_mrf_high
||
2643 mrf_high
== scan_mrf_low
||
2644 mrf_high
== scan_mrf_high
) {
2649 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2650 /* Found a SEND instruction, which means that there are
2651 * live values in MRFs from base_mrf to base_mrf +
2652 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2655 if (mrf_low
>= scan_inst
->base_mrf
&&
2656 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2659 if (mrf_high
>= scan_inst
->base_mrf
&&
2660 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2668 invalidate_live_intervals();
2674 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2675 * flow. We could probably do better here with some form of divergence
2679 fs_visitor::eliminate_find_live_channel()
2681 bool progress
= false;
2684 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2685 switch (inst
->opcode
) {
2691 case BRW_OPCODE_ENDIF
:
2692 case BRW_OPCODE_WHILE
:
2696 case FS_OPCODE_DISCARD_JUMP
:
2697 /* This can potentially make control flow non-uniform until the end
2702 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2704 inst
->opcode
= BRW_OPCODE_MOV
;
2705 inst
->src
[0] = brw_imm_ud(0u);
2707 inst
->force_writemask_all
= true;
2721 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2722 * instructions to FS_OPCODE_REP_FB_WRITE.
2725 fs_visitor::emit_repclear_shader()
2727 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2729 int color_mrf
= base_mrf
+ 2;
2731 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2732 .MOV(brw_message_reg(color_mrf
),
2733 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2736 if (key
->nr_color_regions
== 1) {
2737 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2738 write
->saturate
= key
->clamp_fragment_color
;
2739 write
->base_mrf
= color_mrf
;
2741 write
->header_size
= 0;
2744 assume(key
->nr_color_regions
> 0);
2745 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2746 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2747 write
->saturate
= key
->clamp_fragment_color
;
2748 write
->base_mrf
= base_mrf
;
2750 write
->header_size
= 2;
2758 assign_constant_locations();
2759 assign_curb_setup();
2761 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2762 assert(mov
->src
[0].file
== FIXED_GRF
);
2763 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2767 * Walks through basic blocks, looking for repeated MRF writes and
2768 * removing the later ones.
2771 fs_visitor::remove_duplicate_mrf_writes()
2773 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2774 bool progress
= false;
2776 /* Need to update the MRF tracking for compressed instructions. */
2777 if (dispatch_width
== 16)
2780 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2782 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2783 if (inst
->is_control_flow()) {
2784 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2787 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2788 inst
->dst
.file
== MRF
) {
2789 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2790 if (prev_inst
&& inst
->equals(prev_inst
)) {
2791 inst
->remove(block
);
2797 /* Clear out the last-write records for MRFs that were overwritten. */
2798 if (inst
->dst
.file
== MRF
) {
2799 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2802 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2803 /* Found a SEND instruction, which will include two or fewer
2804 * implied MRF writes. We could do better here.
2806 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2807 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2811 /* Clear out any MRF move records whose sources got overwritten. */
2812 if (inst
->dst
.file
== VGRF
) {
2813 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2814 if (last_mrf_move
[i
] &&
2815 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2816 last_mrf_move
[i
] = NULL
;
2821 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2822 inst
->dst
.file
== MRF
&&
2823 inst
->src
[0].file
== VGRF
&&
2824 !inst
->is_partial_write()) {
2825 last_mrf_move
[inst
->dst
.nr
] = inst
;
2830 invalidate_live_intervals();
2836 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2838 /* Clear the flag for registers that actually got read (as expected). */
2839 for (int i
= 0; i
< inst
->sources
; i
++) {
2841 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2842 grf
= inst
->src
[i
].nr
;
2847 if (grf
>= first_grf
&&
2848 grf
< first_grf
+ grf_len
) {
2849 deps
[grf
- first_grf
] = false;
2850 if (inst
->exec_size
== 16)
2851 deps
[grf
- first_grf
+ 1] = false;
2857 * Implements this workaround for the original 965:
2859 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2860 * check for post destination dependencies on this instruction, software
2861 * must ensure that there is no destination hazard for the case of ‘write
2862 * followed by a posted write’ shown in the following example.
2865 * 2. send r3.xy <rest of send instruction>
2868 * Due to no post-destination dependency check on the ‘send’, the above
2869 * code sequence could have two instructions (1 and 2) in flight at the
2870 * same time that both consider ‘r3’ as the target of their final writes.
2873 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2876 int write_len
= inst
->regs_written
;
2877 int first_write_grf
= inst
->dst
.nr
;
2878 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2879 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2881 memset(needs_dep
, false, sizeof(needs_dep
));
2882 memset(needs_dep
, true, write_len
);
2884 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2886 /* Walk backwards looking for writes to registers we're writing which
2887 * aren't read since being written. If we hit the start of the program,
2888 * we assume that there are no outstanding dependencies on entry to the
2891 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2892 /* If we hit control flow, assume that there *are* outstanding
2893 * dependencies, and force their cleanup before our instruction.
2895 if (block
->start() == scan_inst
) {
2896 for (int i
= 0; i
< write_len
; i
++) {
2898 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2899 first_write_grf
+ i
);
2904 /* We insert our reads as late as possible on the assumption that any
2905 * instruction but a MOV that might have left us an outstanding
2906 * dependency has more latency than a MOV.
2908 if (scan_inst
->dst
.file
== VGRF
) {
2909 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2910 int reg
= scan_inst
->dst
.nr
+ i
;
2912 if (reg
>= first_write_grf
&&
2913 reg
< first_write_grf
+ write_len
&&
2914 needs_dep
[reg
- first_write_grf
]) {
2915 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2916 needs_dep
[reg
- first_write_grf
] = false;
2917 if (scan_inst
->exec_size
== 16)
2918 needs_dep
[reg
- first_write_grf
+ 1] = false;
2923 /* Clear the flag for registers that actually got read (as expected). */
2924 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2926 /* Continue the loop only if we haven't resolved all the dependencies */
2928 for (i
= 0; i
< write_len
; i
++) {
2938 * Implements this workaround for the original 965:
2940 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2941 * used as a destination register until after it has been sourced by an
2942 * instruction with a different destination register.
2945 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
2947 int write_len
= inst
->regs_written
;
2948 int first_write_grf
= inst
->dst
.nr
;
2949 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2950 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2952 memset(needs_dep
, false, sizeof(needs_dep
));
2953 memset(needs_dep
, true, write_len
);
2954 /* Walk forwards looking for writes to registers we're writing which aren't
2955 * read before being written.
2957 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
2958 /* If we hit control flow, force resolve all remaining dependencies. */
2959 if (block
->end() == scan_inst
) {
2960 for (int i
= 0; i
< write_len
; i
++) {
2962 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2963 first_write_grf
+ i
);
2968 /* Clear the flag for registers that actually got read (as expected). */
2969 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2971 /* We insert our reads as late as possible since they're reading the
2972 * result of a SEND, which has massive latency.
2974 if (scan_inst
->dst
.file
== VGRF
&&
2975 scan_inst
->dst
.nr
>= first_write_grf
&&
2976 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
2977 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
2978 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
2980 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
2983 /* Continue the loop only if we haven't resolved all the dependencies */
2985 for (i
= 0; i
< write_len
; i
++) {
2995 fs_visitor::insert_gen4_send_dependency_workarounds()
2997 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3000 bool progress
= false;
3002 /* Note that we're done with register allocation, so GRF fs_regs always
3003 * have a .reg_offset of 0.
3006 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3007 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3008 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3009 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3015 invalidate_live_intervals();
3019 * Turns the generic expression-style uniform pull constant load instruction
3020 * into a hardware-specific series of instructions for loading a pull
3023 * The expression style allows the CSE pass before this to optimize out
3024 * repeated loads from the same offset, and gives the pre-register-allocation
3025 * scheduling full flexibility, while the conversion to native instructions
3026 * allows the post-register-allocation scheduler the best information
3029 * Note that execution masking for setting up pull constant loads is special:
3030 * the channels that need to be written are unrelated to the current execution
3031 * mask, since a later instruction will use one of the result channels as a
3032 * source operand for all 8 or 16 of its channels.
3035 fs_visitor::lower_uniform_pull_constant_loads()
3037 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3038 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3041 if (devinfo
->gen
>= 7) {
3042 /* The offset arg before was a vec4-aligned byte offset. We need to
3043 * turn it into a dword offset.
3045 fs_reg const_offset_reg
= inst
->src
[1];
3046 assert(const_offset_reg
.file
== IMM
&&
3047 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3048 const_offset_reg
.ud
/= 4;
3050 fs_reg payload
, offset
;
3051 if (devinfo
->gen
>= 9) {
3052 /* We have to use a message header on Skylake to get SIMD4x2
3053 * mode. Reserve space for the register.
3055 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3056 offset
.reg_offset
++;
3059 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3063 /* This is actually going to be a MOV, but since only the first dword
3064 * is accessed, we have a special opcode to do just that one. Note
3065 * that this needs to be an operation that will be considered a def
3066 * by live variable analysis, or register allocation will explode.
3068 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3069 8, offset
, const_offset_reg
);
3070 setup
->force_writemask_all
= true;
3072 setup
->ir
= inst
->ir
;
3073 setup
->annotation
= inst
->annotation
;
3074 inst
->insert_before(block
, setup
);
3076 /* Similarly, this will only populate the first 4 channels of the
3077 * result register (since we only use smear values from 0-3), but we
3078 * don't tell the optimizer.
3080 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3081 inst
->src
[1] = payload
;
3082 inst
->base_mrf
= -1;
3084 invalidate_live_intervals();
3086 /* Before register allocation, we didn't tell the scheduler about the
3087 * MRF we use. We know it's safe to use this MRF because nothing
3088 * else does except for register spill/unspill, which generates and
3089 * uses its MRF within a single IR instruction.
3091 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3098 fs_visitor::lower_load_payload()
3100 bool progress
= false;
3102 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3103 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3106 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3107 assert(inst
->saturate
== false);
3108 fs_reg dst
= inst
->dst
;
3110 /* Get rid of COMPR4. We'll add it back in if we need it */
3111 if (dst
.file
== MRF
)
3112 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3114 const fs_builder
ibld(this, block
, inst
);
3115 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3117 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3118 if (inst
->src
[i
].file
!= BAD_FILE
) {
3119 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3120 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3121 hbld
.MOV(mov_dst
, mov_src
);
3123 dst
= offset(dst
, hbld
, 1);
3126 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3127 inst
->exec_size
> 8) {
3128 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3129 * a straightforward copy. Instead, the result of the
3130 * LOAD_PAYLOAD is treated as interleaved and the first four
3131 * non-header sources are unpacked as:
3142 * This is used for gen <= 5 fb writes.
3144 assert(inst
->exec_size
== 16);
3145 assert(inst
->header_size
+ 4 <= inst
->sources
);
3146 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3147 if (inst
->src
[i
].file
!= BAD_FILE
) {
3148 if (devinfo
->has_compr4
) {
3149 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3150 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3151 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3153 /* Platform doesn't have COMPR4. We have to fake it */
3154 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3155 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3157 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3164 /* The loop above only ever incremented us through the first set
3165 * of 4 registers. However, thanks to the magic of COMPR4, we
3166 * actually wrote to the first 8 registers, so we need to take
3167 * that into account now.
3171 /* The COMPR4 code took care of the first 4 sources. We'll let
3172 * the regular path handle any remaining sources. Yes, we are
3173 * modifying the instruction but we're about to delete it so
3174 * this really doesn't hurt anything.
3176 inst
->header_size
+= 4;
3179 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3180 if (inst
->src
[i
].file
!= BAD_FILE
)
3181 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3182 dst
= offset(dst
, ibld
, 1);
3185 inst
->remove(block
);
3190 invalidate_live_intervals();
3196 fs_visitor::lower_integer_multiplication()
3198 bool progress
= false;
3200 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3201 const fs_builder
ibld(this, block
, inst
);
3203 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3204 if (inst
->dst
.is_accumulator() ||
3205 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3206 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3209 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3210 * operation directly, but CHV/BXT cannot.
3212 if (devinfo
->gen
>= 8 &&
3213 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3216 if (inst
->src
[1].file
== IMM
&&
3217 inst
->src
[1].ud
< (1 << 16)) {
3218 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3219 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3222 * If multiplying by an immediate value that fits in 16-bits, do a
3223 * single MUL instruction with that value in the proper location.
3225 if (devinfo
->gen
< 7) {
3226 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3228 ibld
.MOV(imm
, inst
->src
[1]);
3229 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3231 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3234 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3235 * do 32-bit integer multiplication in one instruction, but instead
3236 * must do a sequence (which actually calculates a 64-bit result):
3238 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3239 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3240 * mov(8) g2<1>D acc0<8,8,1>D
3242 * But on Gen > 6, the ability to use second accumulator register
3243 * (acc1) for non-float data types was removed, preventing a simple
3244 * implementation in SIMD16. A 16-channel result can be calculated by
3245 * executing the three instructions twice in SIMD8, once with quarter
3246 * control of 1Q for the first eight channels and again with 2Q for
3247 * the second eight channels.
3249 * Which accumulator register is implicitly accessed (by AccWrEnable
3250 * for instance) is determined by the quarter control. Unfortunately
3251 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3252 * implicit accumulator access by an instruction with 2Q will access
3253 * acc1 regardless of whether the data type is usable in acc1.
3255 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3256 * integer data types.
3258 * Since we only want the low 32-bits of the result, we can do two
3259 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3260 * adjust the high result and add them (like the mach is doing):
3262 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3263 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3264 * shl(8) g9<1>D g8<8,8,1>D 16D
3265 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3267 * We avoid the shl instruction by realizing that we only want to add
3268 * the low 16-bits of the "high" result to the high 16-bits of the
3269 * "low" result and using proper regioning on the add:
3271 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3272 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3273 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3275 * Since it does not use the (single) accumulator register, we can
3276 * schedule multi-component multiplications much better.
3279 fs_reg orig_dst
= inst
->dst
;
3280 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3281 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3284 fs_reg low
= inst
->dst
;
3285 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3288 if (devinfo
->gen
>= 7) {
3289 fs_reg src1_0_w
= inst
->src
[1];
3290 fs_reg src1_1_w
= inst
->src
[1];
3292 if (inst
->src
[1].file
== IMM
) {
3293 src1_0_w
.ud
&= 0xffff;
3296 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3297 if (src1_0_w
.stride
!= 0) {
3298 assert(src1_0_w
.stride
== 1);
3299 src1_0_w
.stride
= 2;
3302 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3303 if (src1_1_w
.stride
!= 0) {
3304 assert(src1_1_w
.stride
== 1);
3305 src1_1_w
.stride
= 2;
3307 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3309 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3310 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3312 fs_reg src0_0_w
= inst
->src
[0];
3313 fs_reg src0_1_w
= inst
->src
[0];
3315 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3316 if (src0_0_w
.stride
!= 0) {
3317 assert(src0_0_w
.stride
== 1);
3318 src0_0_w
.stride
= 2;
3321 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3322 if (src0_1_w
.stride
!= 0) {
3323 assert(src0_1_w
.stride
== 1);
3324 src0_1_w
.stride
= 2;
3326 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3328 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3329 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3332 fs_reg dst
= inst
->dst
;
3333 dst
.type
= BRW_REGISTER_TYPE_UW
;
3334 dst
.subreg_offset
= 2;
3337 high
.type
= BRW_REGISTER_TYPE_UW
;
3340 low
.type
= BRW_REGISTER_TYPE_UW
;
3341 low
.subreg_offset
= 2;
3344 ibld
.ADD(dst
, low
, high
);
3346 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3347 set_condmod(inst
->conditional_mod
,
3348 ibld
.MOV(orig_dst
, inst
->dst
));
3352 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3353 /* Should have been lowered to 8-wide. */
3354 assert(inst
->exec_size
<= 8);
3355 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3357 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3358 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3360 if (devinfo
->gen
>= 8) {
3361 /* Until Gen8, integer multiplies read 32-bits from one source,
3362 * and 16-bits from the other, and relying on the MACH instruction
3363 * to generate the high bits of the result.
3365 * On Gen8, the multiply instruction does a full 32x32-bit
3366 * multiply, but in order to do a 64-bit multiply we can simulate
3367 * the previous behavior and then use a MACH instruction.
3369 * FINISHME: Don't use source modifiers on src1.
3371 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3372 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3373 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3374 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3375 mul
->src
[1].stride
*= 2;
3377 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3378 inst
->force_sechalf
) {
3379 /* Among other things the quarter control bits influence which
3380 * accumulator register is used by the hardware for instructions
3381 * that access the accumulator implicitly (e.g. MACH). A
3382 * second-half instruction would normally map to acc1, which
3383 * doesn't exist on Gen7 and up (the hardware does emulate it for
3384 * floating-point instructions *only* by taking advantage of the
3385 * extra precision of acc0 not normally used for floating point
3388 * HSW and up are careful enough not to try to access an
3389 * accumulator register that doesn't exist, but on earlier Gen7
3390 * hardware we need to make sure that the quarter control bits are
3391 * zero to avoid non-deterministic behaviour and emit an extra MOV
3392 * to get the result masked correctly according to the current
3395 mach
->force_sechalf
= false;
3396 mach
->force_writemask_all
= true;
3397 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3398 ibld
.MOV(inst
->dst
, mach
->dst
);
3404 inst
->remove(block
);
3409 invalidate_live_intervals();
3415 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3416 fs_reg
*dst
, fs_reg color
, unsigned components
)
3418 if (key
->clamp_fragment_color
) {
3419 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3420 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3422 for (unsigned i
= 0; i
< components
; i
++)
3424 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3429 for (unsigned i
= 0; i
< components
; i
++)
3430 dst
[i
] = offset(color
, bld
, i
);
3434 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3435 const brw_wm_prog_data
*prog_data
,
3436 const brw_wm_prog_key
*key
,
3437 const fs_visitor::thread_payload
&payload
)
3439 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3440 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3441 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3442 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3443 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3444 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3445 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3446 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3447 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3448 const unsigned components
=
3449 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3451 /* We can potentially have a message length of up to 15, so we have to set
3452 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3455 int header_size
= 2, payload_header_size
;
3456 unsigned length
= 0;
3458 /* From the Sandy Bridge PRM, volume 4, page 198:
3460 * "Dispatched Pixel Enables. One bit per pixel indicating
3461 * which pixels were originally enabled when the thread was
3462 * dispatched. This field is only required for the end-of-
3463 * thread message and on all dual-source messages."
3465 if (devinfo
->gen
>= 6 &&
3466 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3467 color1
.file
== BAD_FILE
&&
3468 key
->nr_color_regions
== 1) {
3472 if (header_size
!= 0) {
3473 assert(header_size
== 2);
3474 /* Allocate 2 registers for a header */
3478 if (payload
.aa_dest_stencil_reg
) {
3479 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3480 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3481 .MOV(sources
[length
],
3482 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3486 if (prog_data
->uses_omask
) {
3487 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3488 BRW_REGISTER_TYPE_UD
);
3490 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3491 * relevant. Since it's unsigned single words one vgrf is always
3492 * 16-wide, but only the lower or higher 8 channels will be used by the
3493 * hardware when doing a SIMD8 write depending on whether we have
3494 * selected the subspans for the first or second half respectively.
3496 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3497 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3498 sample_mask
.stride
*= 2;
3500 bld
.exec_all().annotate("FB write oMask")
3501 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3502 inst
->force_sechalf
),
3507 payload_header_size
= length
;
3509 if (src0_alpha
.file
!= BAD_FILE
) {
3510 /* FIXME: This is being passed at the wrong location in the payload and
3511 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3512 * It's supposed to be immediately before oMask but there seems to be no
3513 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3514 * requires header sources to form a contiguous segment at the beginning
3515 * of the message and src0_alpha has per-channel semantics.
3517 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3521 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3524 if (color1
.file
!= BAD_FILE
) {
3525 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3529 if (src_depth
.file
!= BAD_FILE
) {
3530 sources
[length
] = src_depth
;
3534 if (dst_depth
.file
!= BAD_FILE
) {
3535 sources
[length
] = dst_depth
;
3539 if (src_stencil
.file
!= BAD_FILE
) {
3540 assert(devinfo
->gen
>= 9);
3541 assert(bld
.dispatch_width() != 16);
3543 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3544 * available on gen9+. As such it's impossible to have both enabled at the
3545 * same time and therefore length cannot overrun the array.
3547 assert(length
< 15);
3549 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3550 bld
.exec_all().annotate("FB write OS")
3551 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3552 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3557 if (devinfo
->gen
>= 7) {
3558 /* Send from the GRF */
3559 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3560 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3561 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3562 load
->dst
= payload
;
3564 inst
->src
[0] = payload
;
3565 inst
->resize_sources(1);
3566 inst
->base_mrf
= -1;
3568 /* Send from the MRF */
3569 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3570 sources
, length
, payload_header_size
);
3572 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3573 * will do this for us if we just give it a COMPR4 destination.
3575 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3576 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3578 inst
->resize_sources(0);
3582 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3583 inst
->mlen
= load
->regs_written
;
3584 inst
->header_size
= header_size
;
3588 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3589 const fs_reg
&coordinate
,
3590 const fs_reg
&shadow_c
,
3591 const fs_reg
&lod
, const fs_reg
&lod2
,
3592 const fs_reg
&sampler
,
3593 unsigned coord_components
,
3594 unsigned grad_components
)
3596 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3597 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3598 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3599 fs_reg msg_end
= msg_begin
;
3602 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3604 for (unsigned i
= 0; i
< coord_components
; i
++)
3605 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3606 offset(coordinate
, bld
, i
));
3608 msg_end
= offset(msg_end
, bld
, coord_components
);
3610 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3611 * require all three components to be present and zero if they are unused.
3613 if (coord_components
> 0 &&
3614 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3615 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3616 for (unsigned i
= coord_components
; i
< 3; i
++)
3617 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3619 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3622 if (op
== SHADER_OPCODE_TXD
) {
3623 /* TXD unsupported in SIMD16 mode. */
3624 assert(bld
.dispatch_width() == 8);
3626 /* the slots for u and v are always present, but r is optional */
3627 if (coord_components
< 2)
3628 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3631 * dPdx = dudx, dvdx, drdx
3632 * dPdy = dudy, dvdy, drdy
3634 * 1-arg: Does not exist.
3636 * 2-arg: dudx dvdx dudy dvdy
3637 * dPdx.x dPdx.y dPdy.x dPdy.y
3640 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3641 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3642 * m5 m6 m7 m8 m9 m10
3644 for (unsigned i
= 0; i
< grad_components
; i
++)
3645 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3647 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3649 for (unsigned i
= 0; i
< grad_components
; i
++)
3650 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3652 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3656 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3657 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3659 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3660 bld
.dispatch_width() == 16);
3662 const brw_reg_type type
=
3663 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3664 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3665 bld
.MOV(retype(msg_end
, type
), lod
);
3666 msg_end
= offset(msg_end
, bld
, 1);
3669 if (shadow_c
.file
!= BAD_FILE
) {
3670 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3671 /* There's no plain shadow compare message, so we use shadow
3672 * compare with a bias of 0.0.
3674 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3675 msg_end
= offset(msg_end
, bld
, 1);
3678 bld
.MOV(msg_end
, shadow_c
);
3679 msg_end
= offset(msg_end
, bld
, 1);
3683 inst
->src
[0] = reg_undef
;
3684 inst
->src
[1] = sampler
;
3685 inst
->resize_sources(2);
3686 inst
->base_mrf
= msg_begin
.nr
;
3687 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3688 inst
->header_size
= 1;
3692 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3694 const fs_reg
&shadow_c
,
3695 fs_reg lod
, fs_reg lod2
,
3696 const fs_reg
&sample_index
,
3697 const fs_reg
&sampler
,
3698 const fs_reg
&offset_value
,
3699 unsigned coord_components
,
3700 unsigned grad_components
)
3702 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3703 fs_reg msg_coords
= message
;
3704 unsigned header_size
= 0;
3706 if (offset_value
.file
!= BAD_FILE
) {
3707 /* The offsets set up by the visitor are in the m1 header, so we can't
3714 for (unsigned i
= 0; i
< coord_components
; i
++) {
3715 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3716 coordinate
= offset(coordinate
, bld
, 1);
3718 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3719 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3721 if (shadow_c
.file
!= BAD_FILE
) {
3722 fs_reg msg_shadow
= msg_lod
;
3723 bld
.MOV(msg_shadow
, shadow_c
);
3724 msg_lod
= offset(msg_shadow
, bld
, 1);
3729 case SHADER_OPCODE_TXL
:
3731 bld
.MOV(msg_lod
, lod
);
3732 msg_end
= offset(msg_lod
, bld
, 1);
3734 case SHADER_OPCODE_TXD
:
3737 * dPdx = dudx, dvdx, drdx
3738 * dPdy = dudy, dvdy, drdy
3740 * Load up these values:
3741 * - dudx dudy dvdx dvdy drdx drdy
3742 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3745 for (unsigned i
= 0; i
< grad_components
; i
++) {
3746 bld
.MOV(msg_end
, lod
);
3747 lod
= offset(lod
, bld
, 1);
3748 msg_end
= offset(msg_end
, bld
, 1);
3750 bld
.MOV(msg_end
, lod2
);
3751 lod2
= offset(lod2
, bld
, 1);
3752 msg_end
= offset(msg_end
, bld
, 1);
3755 case SHADER_OPCODE_TXS
:
3756 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3757 bld
.MOV(msg_lod
, lod
);
3758 msg_end
= offset(msg_lod
, bld
, 1);
3760 case SHADER_OPCODE_TXF
:
3761 msg_lod
= offset(msg_coords
, bld
, 3);
3762 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3763 msg_end
= offset(msg_lod
, bld
, 1);
3765 case SHADER_OPCODE_TXF_CMS
:
3766 msg_lod
= offset(msg_coords
, bld
, 3);
3768 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3770 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3771 msg_end
= offset(msg_lod
, bld
, 2);
3778 inst
->src
[0] = reg_undef
;
3779 inst
->src
[1] = sampler
;
3780 inst
->resize_sources(2);
3781 inst
->base_mrf
= message
.nr
;
3782 inst
->mlen
= msg_end
.nr
- message
.nr
;
3783 inst
->header_size
= header_size
;
3785 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3786 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3790 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3792 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3795 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3799 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3801 const fs_reg
&shadow_c
,
3802 fs_reg lod
, fs_reg lod2
,
3803 const fs_reg
&sample_index
,
3804 const fs_reg
&mcs
, const fs_reg
&sampler
,
3805 fs_reg offset_value
,
3806 unsigned coord_components
,
3807 unsigned grad_components
)
3809 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3810 int reg_width
= bld
.dispatch_width() / 8;
3811 unsigned header_size
= 0, length
= 0;
3812 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3813 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3814 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3816 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3817 offset_value
.file
!= BAD_FILE
||
3818 is_high_sampler(devinfo
, sampler
)) {
3819 /* For general texture offsets (no txf workaround), we need a header to
3820 * put them in. Note that we're only reserving space for it in the
3821 * message payload as it will be initialized implicitly by the
3824 * TG4 needs to place its channel select in the header, for interaction
3825 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3826 * larger sampler numbers we need to offset the Sampler State Pointer in
3830 sources
[0] = fs_reg();
3834 if (shadow_c
.file
!= BAD_FILE
) {
3835 bld
.MOV(sources
[length
], shadow_c
);
3839 bool coordinate_done
= false;
3841 /* The sampler can only meaningfully compute LOD for fragment shader
3842 * messages. For all other stages, we change the opcode to TXL and
3843 * hardcode the LOD to 0.
3845 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3846 op
== SHADER_OPCODE_TEX
) {
3847 op
= SHADER_OPCODE_TXL
;
3848 lod
= brw_imm_f(0.0f
);
3851 /* Set up the LOD info */
3854 case SHADER_OPCODE_TXL
:
3855 bld
.MOV(sources
[length
], lod
);
3858 case SHADER_OPCODE_TXD
:
3859 /* TXD should have been lowered in SIMD16 mode. */
3860 assert(bld
.dispatch_width() == 8);
3862 /* Load dPdx and the coordinate together:
3863 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3865 for (unsigned i
= 0; i
< coord_components
; i
++) {
3866 bld
.MOV(sources
[length
], coordinate
);
3867 coordinate
= offset(coordinate
, bld
, 1);
3870 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3871 * only derivatives for (u, v, r).
3873 if (i
< grad_components
) {
3874 bld
.MOV(sources
[length
], lod
);
3875 lod
= offset(lod
, bld
, 1);
3878 bld
.MOV(sources
[length
], lod2
);
3879 lod2
= offset(lod2
, bld
, 1);
3884 coordinate_done
= true;
3886 case SHADER_OPCODE_TXS
:
3887 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3890 case SHADER_OPCODE_TXF
:
3891 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3892 * On Gen9 they are u, v, lod, r
3894 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3895 coordinate
= offset(coordinate
, bld
, 1);
3898 if (devinfo
->gen
>= 9) {
3899 if (coord_components
>= 2) {
3900 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3901 coordinate
= offset(coordinate
, bld
, 1);
3906 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3909 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3910 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3911 coordinate
= offset(coordinate
, bld
, 1);
3915 coordinate_done
= true;
3917 case SHADER_OPCODE_TXF_CMS
:
3918 case SHADER_OPCODE_TXF_CMS_W
:
3919 case SHADER_OPCODE_TXF_UMS
:
3920 case SHADER_OPCODE_TXF_MCS
:
3921 if (op
== SHADER_OPCODE_TXF_UMS
||
3922 op
== SHADER_OPCODE_TXF_CMS
||
3923 op
== SHADER_OPCODE_TXF_CMS_W
) {
3924 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3928 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3929 /* Data from the multisample control surface. */
3930 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3933 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3936 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3937 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3940 offset(mcs
, bld
, 1));
3945 /* There is no offsetting for this message; just copy in the integer
3946 * texture coordinates.
3948 for (unsigned i
= 0; i
< coord_components
; i
++) {
3949 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3950 coordinate
= offset(coordinate
, bld
, 1);
3954 coordinate_done
= true;
3956 case SHADER_OPCODE_TG4_OFFSET
:
3957 /* gather4_po_c should have been lowered in SIMD16 mode. */
3958 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
3960 /* More crazy intermixing */
3961 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
3962 bld
.MOV(sources
[length
], coordinate
);
3963 coordinate
= offset(coordinate
, bld
, 1);
3967 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
3968 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
3969 offset_value
= offset(offset_value
, bld
, 1);
3973 if (coord_components
== 3) { /* r if present */
3974 bld
.MOV(sources
[length
], coordinate
);
3975 coordinate
= offset(coordinate
, bld
, 1);
3979 coordinate_done
= true;
3985 /* Set up the coordinate (except for cases where it was done above) */
3986 if (!coordinate_done
) {
3987 for (unsigned i
= 0; i
< coord_components
; i
++) {
3988 bld
.MOV(sources
[length
], coordinate
);
3989 coordinate
= offset(coordinate
, bld
, 1);
3996 mlen
= length
* reg_width
- header_size
;
3998 mlen
= length
* reg_width
;
4000 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4001 BRW_REGISTER_TYPE_F
);
4002 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4004 /* Generate the SEND. */
4006 inst
->src
[0] = src_payload
;
4007 inst
->src
[1] = sampler
;
4008 inst
->resize_sources(2);
4009 inst
->base_mrf
= -1;
4011 inst
->header_size
= header_size
;
4013 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4014 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4018 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4020 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4021 const fs_reg
&coordinate
= inst
->src
[0];
4022 const fs_reg
&shadow_c
= inst
->src
[1];
4023 const fs_reg
&lod
= inst
->src
[2];
4024 const fs_reg
&lod2
= inst
->src
[3];
4025 const fs_reg
&sample_index
= inst
->src
[4];
4026 const fs_reg
&mcs
= inst
->src
[5];
4027 const fs_reg
&sampler
= inst
->src
[6];
4028 const fs_reg
&offset_value
= inst
->src
[7];
4029 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4030 const unsigned coord_components
= inst
->src
[8].ud
;
4031 const unsigned grad_components
= inst
->src
[9].ud
;
4033 if (devinfo
->gen
>= 7) {
4034 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4035 shadow_c
, lod
, lod2
, sample_index
,
4036 mcs
, sampler
, offset_value
,
4037 coord_components
, grad_components
);
4038 } else if (devinfo
->gen
>= 5) {
4039 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4040 shadow_c
, lod
, lod2
, sample_index
,
4041 sampler
, offset_value
,
4042 coord_components
, grad_components
);
4044 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4045 shadow_c
, lod
, lod2
, sampler
,
4046 coord_components
, grad_components
);
4051 * Initialize the header present in some typed and untyped surface
4055 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4057 fs_builder ubld
= bld
.exec_all().group(8, 0);
4058 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4059 ubld
.MOV(dst
, brw_imm_d(0));
4060 ubld
.MOV(component(dst
, 7), sample_mask
);
4065 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4066 const fs_reg
&sample_mask
)
4068 /* Get the logical send arguments. */
4069 const fs_reg
&addr
= inst
->src
[0];
4070 const fs_reg
&src
= inst
->src
[1];
4071 const fs_reg
&surface
= inst
->src
[2];
4072 const UNUSED fs_reg
&dims
= inst
->src
[3];
4073 const fs_reg
&arg
= inst
->src
[4];
4075 /* Calculate the total number of components of the payload. */
4076 const unsigned addr_sz
= inst
->components_read(0);
4077 const unsigned src_sz
= inst
->components_read(1);
4078 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4079 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4081 /* Allocate space for the payload. */
4082 fs_reg
*const components
= new fs_reg
[sz
];
4083 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4086 /* Construct the payload. */
4088 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4090 for (unsigned i
= 0; i
< addr_sz
; i
++)
4091 components
[n
++] = offset(addr
, bld
, i
);
4093 for (unsigned i
= 0; i
< src_sz
; i
++)
4094 components
[n
++] = offset(src
, bld
, i
);
4096 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4098 /* Update the original instruction. */
4100 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4101 inst
->header_size
= header_sz
;
4103 inst
->src
[0] = payload
;
4104 inst
->src
[1] = surface
;
4106 inst
->resize_sources(3);
4108 delete[] components
;
4112 fs_visitor::lower_logical_sends()
4114 bool progress
= false;
4116 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4117 const fs_builder
ibld(this, block
, inst
);
4119 switch (inst
->opcode
) {
4120 case FS_OPCODE_FB_WRITE_LOGICAL
:
4121 assert(stage
== MESA_SHADER_FRAGMENT
);
4122 lower_fb_write_logical_send(ibld
, inst
,
4123 (const brw_wm_prog_data
*)prog_data
,
4124 (const brw_wm_prog_key
*)key
,
4128 case SHADER_OPCODE_TEX_LOGICAL
:
4129 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4132 case SHADER_OPCODE_TXD_LOGICAL
:
4133 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4136 case SHADER_OPCODE_TXF_LOGICAL
:
4137 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4140 case SHADER_OPCODE_TXL_LOGICAL
:
4141 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4144 case SHADER_OPCODE_TXS_LOGICAL
:
4145 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4148 case FS_OPCODE_TXB_LOGICAL
:
4149 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4152 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4153 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4156 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4157 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4160 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4161 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4164 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4165 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4168 case SHADER_OPCODE_LOD_LOGICAL
:
4169 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4172 case SHADER_OPCODE_TG4_LOGICAL
:
4173 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4176 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4177 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4180 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4181 lower_surface_logical_send(ibld
, inst
,
4182 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4186 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4187 lower_surface_logical_send(ibld
, inst
,
4188 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4189 ibld
.sample_mask_reg());
4192 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4193 lower_surface_logical_send(ibld
, inst
,
4194 SHADER_OPCODE_UNTYPED_ATOMIC
,
4195 ibld
.sample_mask_reg());
4198 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4199 lower_surface_logical_send(ibld
, inst
,
4200 SHADER_OPCODE_TYPED_SURFACE_READ
,
4204 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4205 lower_surface_logical_send(ibld
, inst
,
4206 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4207 ibld
.sample_mask_reg());
4210 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4211 lower_surface_logical_send(ibld
, inst
,
4212 SHADER_OPCODE_TYPED_ATOMIC
,
4213 ibld
.sample_mask_reg());
4224 invalidate_live_intervals();
4230 * Get the closest native SIMD width supported by the hardware for instruction
4231 * \p inst. The instruction will be left untouched by
4232 * fs_visitor::lower_simd_width() if the returned value is equal to the
4233 * original execution size.
4236 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4237 const fs_inst
*inst
)
4239 switch (inst
->opcode
) {
4240 case BRW_OPCODE_MOV
:
4241 case BRW_OPCODE_SEL
:
4242 case BRW_OPCODE_NOT
:
4243 case BRW_OPCODE_AND
:
4245 case BRW_OPCODE_XOR
:
4246 case BRW_OPCODE_SHR
:
4247 case BRW_OPCODE_SHL
:
4248 case BRW_OPCODE_ASR
:
4249 case BRW_OPCODE_CMP
:
4250 case BRW_OPCODE_CMPN
:
4251 case BRW_OPCODE_CSEL
:
4252 case BRW_OPCODE_F32TO16
:
4253 case BRW_OPCODE_F16TO32
:
4254 case BRW_OPCODE_BFREV
:
4255 case BRW_OPCODE_BFE
:
4256 case BRW_OPCODE_BFI1
:
4257 case BRW_OPCODE_BFI2
:
4258 case BRW_OPCODE_ADD
:
4259 case BRW_OPCODE_MUL
:
4260 case BRW_OPCODE_AVG
:
4261 case BRW_OPCODE_FRC
:
4262 case BRW_OPCODE_RNDU
:
4263 case BRW_OPCODE_RNDD
:
4264 case BRW_OPCODE_RNDE
:
4265 case BRW_OPCODE_RNDZ
:
4266 case BRW_OPCODE_LZD
:
4267 case BRW_OPCODE_FBH
:
4268 case BRW_OPCODE_FBL
:
4269 case BRW_OPCODE_CBIT
:
4270 case BRW_OPCODE_SAD2
:
4271 case BRW_OPCODE_MAD
:
4272 case BRW_OPCODE_LRP
:
4273 case SHADER_OPCODE_RCP
:
4274 case SHADER_OPCODE_RSQ
:
4275 case SHADER_OPCODE_SQRT
:
4276 case SHADER_OPCODE_EXP2
:
4277 case SHADER_OPCODE_LOG2
:
4278 case SHADER_OPCODE_POW
:
4279 case SHADER_OPCODE_INT_QUOTIENT
:
4280 case SHADER_OPCODE_INT_REMAINDER
:
4281 case SHADER_OPCODE_SIN
:
4282 case SHADER_OPCODE_COS
: {
4283 /* According to the PRMs:
4284 * "A. In Direct Addressing mode, a source cannot span more than 2
4285 * adjacent GRF registers.
4286 * B. A destination cannot span more than 2 adjacent GRF registers."
4288 * Look for the source or destination with the largest register region
4289 * which is the one that is going to limit the overal execution size of
4290 * the instruction due to this rule.
4292 unsigned reg_count
= inst
->regs_written
;
4294 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4295 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4297 /* Calculate the maximum execution size of the instruction based on the
4298 * factor by which it goes over the hardware limit of 2 GRFs.
4300 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4302 case SHADER_OPCODE_MULH
:
4303 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4304 * is 8-wide on Gen7+.
4306 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4308 case FS_OPCODE_FB_WRITE_LOGICAL
:
4309 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4312 assert(devinfo
->gen
!= 6 ||
4313 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4314 inst
->exec_size
== 8);
4315 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4316 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4317 8 : inst
->exec_size
);
4319 case SHADER_OPCODE_TXD_LOGICAL
:
4320 /* TXD is unsupported in SIMD16 mode. */
4323 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4324 /* gather4_po_c is unsupported in SIMD16 mode. */
4325 const fs_reg
&shadow_c
= inst
->src
[1];
4326 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4328 case SHADER_OPCODE_TXL_LOGICAL
:
4329 case FS_OPCODE_TXB_LOGICAL
: {
4330 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4331 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4332 * mode because the message exceeds the maximum length of 11.
4334 const fs_reg
&shadow_c
= inst
->src
[1];
4335 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4337 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4340 return inst
->exec_size
;
4342 case SHADER_OPCODE_TXF_LOGICAL
:
4343 case SHADER_OPCODE_TXS_LOGICAL
:
4344 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4345 * messages. Use SIMD16 instead.
4347 if (devinfo
->gen
== 4)
4350 return inst
->exec_size
;
4352 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4353 /* This opcode can take up to 6 arguments which means that in some
4354 * circumstances it can end up with a message that is too long in SIMD16
4357 const unsigned coord_components
= inst
->src
[8].ud
;
4358 /* First three arguments are the sample index and the two arguments for
4361 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4364 return inst
->exec_size
;
4367 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4368 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4369 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4373 return inst
->exec_size
;
4378 * The \p rows array of registers represents a \p num_rows by \p num_columns
4379 * matrix in row-major order, write it in column-major order into the register
4380 * passed as destination. \p stride gives the separation between matrix
4381 * elements in the input in fs_builder::dispatch_width() units.
4384 emit_transpose(const fs_builder
&bld
,
4385 const fs_reg
&dst
, const fs_reg
*rows
,
4386 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4388 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4390 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4391 for (unsigned j
= 0; j
< num_rows
; ++j
)
4392 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4395 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4397 delete[] components
;
4401 fs_visitor::lower_simd_width()
4403 bool progress
= false;
4405 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4406 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4408 if (lower_width
!= inst
->exec_size
) {
4409 /* Builder matching the original instruction. We may also need to
4410 * emit an instruction of width larger than the original, set the
4411 * execution size of the builder to the highest of both for now so
4412 * we're sure that both cases can be handled.
4414 const fs_builder ibld
= bld
.at(block
, inst
)
4415 .exec_all(inst
->force_writemask_all
)
4416 .group(MAX2(inst
->exec_size
, lower_width
),
4417 inst
->force_sechalf
);
4419 /* Split the copies in chunks of the execution width of either the
4420 * original or the lowered instruction, whichever is lower.
4422 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4423 const unsigned n
= inst
->exec_size
/ copy_width
;
4424 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4425 inst
->dst
.component_size(inst
->exec_size
);
4428 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4429 !inst
->writes_accumulator
&& !inst
->mlen
);
4431 for (unsigned i
= 0; i
< n
; i
++) {
4432 /* Emit a copy of the original instruction with the lowered width.
4433 * If the EOT flag was set throw it away except for the last
4434 * instruction to avoid killing the thread prematurely.
4436 fs_inst split_inst
= *inst
;
4437 split_inst
.exec_size
= lower_width
;
4438 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4440 /* Select the correct channel enables for the i-th group, then
4441 * transform the sources and destination and emit the lowered
4444 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4446 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4447 if (inst
->src
[j
].file
!= BAD_FILE
&&
4448 !is_uniform(inst
->src
[j
])) {
4449 /* Get the i-th copy_width-wide chunk of the source. */
4450 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4451 const unsigned src_size
= inst
->components_read(j
);
4453 /* Use a trivial transposition to copy one every n
4454 * copy_width-wide components of the register into a
4455 * temporary passed as source to the lowered instruction.
4457 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4458 emit_transpose(lbld
.group(copy_width
, 0),
4459 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4463 if (inst
->regs_written
) {
4464 /* Allocate enough space to hold the result of the lowered
4465 * instruction and fix up the number of registers written.
4467 split_inst
.dst
= dsts
[i
] =
4468 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4469 split_inst
.regs_written
=
4470 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4474 lbld
.emit(split_inst
);
4477 if (inst
->regs_written
) {
4478 /* Distance between useful channels in the temporaries, skipping
4479 * garbage if the lowered instruction is wider than the original.
4481 const unsigned m
= lower_width
/ copy_width
;
4483 /* Interleave the components of the result from the lowered
4484 * instructions. We need to set exec_all() when copying more than
4485 * one half per component, because LOAD_PAYLOAD (in terms of which
4486 * emit_transpose is implemented) can only use the same channel
4487 * enable signals for all of its non-header sources.
4489 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4490 .group(copy_width
, 0),
4491 inst
->dst
, dsts
, n
, dst_size
, m
);
4494 inst
->remove(block
);
4500 invalidate_live_intervals();
4506 fs_visitor::dump_instructions()
4508 dump_instructions(NULL
);
4512 fs_visitor::dump_instructions(const char *name
)
4514 FILE *file
= stderr
;
4515 if (name
&& geteuid() != 0) {
4516 file
= fopen(name
, "w");
4522 calculate_register_pressure();
4523 int ip
= 0, max_pressure
= 0;
4524 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4525 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4526 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4527 dump_instruction(inst
, file
);
4530 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4533 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4534 fprintf(file
, "%4d: ", ip
++);
4535 dump_instruction(inst
, file
);
4539 if (file
!= stderr
) {
4545 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4547 dump_instruction(be_inst
, stderr
);
4551 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4553 fs_inst
*inst
= (fs_inst
*)be_inst
;
4555 if (inst
->predicate
) {
4556 fprintf(file
, "(%cf0.%d) ",
4557 inst
->predicate_inverse
? '-' : '+',
4561 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4563 fprintf(file
, ".sat");
4564 if (inst
->conditional_mod
) {
4565 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4566 if (!inst
->predicate
&&
4567 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4568 inst
->opcode
!= BRW_OPCODE_IF
&&
4569 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4570 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4573 fprintf(file
, "(%d) ", inst
->exec_size
);
4576 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4579 switch (inst
->dst
.file
) {
4581 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4582 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4583 inst
->dst
.subreg_offset
)
4584 fprintf(file
, "+%d.%d",
4585 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4588 fprintf(file
, "g%d", inst
->dst
.nr
);
4591 fprintf(file
, "m%d", inst
->dst
.nr
);
4594 fprintf(file
, "(null)");
4597 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4600 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4603 switch (inst
->dst
.nr
) {
4605 fprintf(file
, "null");
4607 case BRW_ARF_ADDRESS
:
4608 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4610 case BRW_ARF_ACCUMULATOR
:
4611 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4614 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4617 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4620 if (inst
->dst
.subnr
)
4621 fprintf(file
, "+%d", inst
->dst
.subnr
);
4624 unreachable("not reached");
4626 if (inst
->dst
.stride
!= 1)
4627 fprintf(file
, "<%u>", inst
->dst
.stride
);
4628 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4630 for (int i
= 0; i
< inst
->sources
; i
++) {
4631 if (inst
->src
[i
].negate
)
4633 if (inst
->src
[i
].abs
)
4635 switch (inst
->src
[i
].file
) {
4637 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4638 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4639 inst
->src
[i
].subreg_offset
)
4640 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4641 inst
->src
[i
].subreg_offset
);
4644 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4647 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4650 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4653 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4654 if (inst
->src
[i
].reladdr
) {
4655 fprintf(file
, "+reladdr");
4656 } else if (inst
->src
[i
].subreg_offset
) {
4657 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4658 inst
->src
[i
].subreg_offset
);
4662 fprintf(file
, "(null)");
4665 switch (inst
->src
[i
].type
) {
4666 case BRW_REGISTER_TYPE_F
:
4667 fprintf(file
, "%ff", inst
->src
[i
].f
);
4669 case BRW_REGISTER_TYPE_W
:
4670 case BRW_REGISTER_TYPE_D
:
4671 fprintf(file
, "%dd", inst
->src
[i
].d
);
4673 case BRW_REGISTER_TYPE_UW
:
4674 case BRW_REGISTER_TYPE_UD
:
4675 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4677 case BRW_REGISTER_TYPE_VF
:
4678 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4679 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4680 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4681 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4682 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4685 fprintf(file
, "???");
4690 switch (inst
->src
[i
].nr
) {
4692 fprintf(file
, "null");
4694 case BRW_ARF_ADDRESS
:
4695 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4697 case BRW_ARF_ACCUMULATOR
:
4698 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4701 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4704 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4707 if (inst
->src
[i
].subnr
)
4708 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4711 if (inst
->src
[i
].abs
)
4714 if (inst
->src
[i
].file
!= IMM
) {
4716 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4717 unsigned hstride
= inst
->src
[i
].hstride
;
4718 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4720 stride
= inst
->src
[i
].stride
;
4723 fprintf(file
, "<%u>", stride
);
4725 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4728 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4729 fprintf(file
, ", ");
4734 if (inst
->force_writemask_all
)
4735 fprintf(file
, "NoMask ");
4737 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4738 if (inst
->force_sechalf
)
4739 fprintf(file
, "2ndhalf ");
4741 fprintf(file
, "1sthalf ");
4744 fprintf(file
, "\n");
4748 * Possibly returns an instruction that set up @param reg.
4750 * Sometimes we want to take the result of some expression/variable
4751 * dereference tree and rewrite the instruction generating the result
4752 * of the tree. When processing the tree, we know that the
4753 * instructions generated are all writing temporaries that are dead
4754 * outside of this tree. So, if we have some instructions that write
4755 * a temporary, we're free to point that temp write somewhere else.
4757 * Note that this doesn't guarantee that the instruction generated
4758 * only reg -- it might be the size=4 destination of a texture instruction.
4761 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4766 end
->is_partial_write() ||
4768 !reg
.equals(end
->dst
)) {
4776 fs_visitor::setup_payload_gen6()
4779 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4780 unsigned barycentric_interp_modes
=
4781 (stage
== MESA_SHADER_FRAGMENT
) ?
4782 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4784 assert(devinfo
->gen
>= 6);
4786 /* R0-1: masks, pixel X/Y coordinates. */
4787 payload
.num_regs
= 2;
4788 /* R2: only for 32-pixel dispatch.*/
4790 /* R3-26: barycentric interpolation coordinates. These appear in the
4791 * same order that they appear in the brw_wm_barycentric_interp_mode
4792 * enum. Each set of coordinates occupies 2 registers if dispatch width
4793 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4794 * appear if they were enabled using the "Barycentric Interpolation
4795 * Mode" bits in WM_STATE.
4797 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4798 if (barycentric_interp_modes
& (1 << i
)) {
4799 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4800 payload
.num_regs
+= 2;
4801 if (dispatch_width
== 16) {
4802 payload
.num_regs
+= 2;
4807 /* R27: interpolated depth if uses source depth */
4809 payload
.source_depth_reg
= payload
.num_regs
;
4811 if (dispatch_width
== 16) {
4812 /* R28: interpolated depth if not SIMD8. */
4816 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4818 payload
.source_w_reg
= payload
.num_regs
;
4820 if (dispatch_width
== 16) {
4821 /* R30: interpolated W if not SIMD8. */
4826 if (stage
== MESA_SHADER_FRAGMENT
) {
4827 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4828 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4829 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4830 /* R31: MSAA position offsets. */
4831 if (prog_data
->uses_pos_offset
) {
4832 payload
.sample_pos_reg
= payload
.num_regs
;
4837 /* R32: MSAA input coverage mask */
4838 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4839 assert(devinfo
->gen
>= 7);
4840 payload
.sample_mask_in_reg
= payload
.num_regs
;
4842 if (dispatch_width
== 16) {
4843 /* R33: input coverage mask if not SIMD8. */
4848 /* R34-: bary for 32-pixel. */
4849 /* R58-59: interp W for 32-pixel. */
4851 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4852 source_depth_to_render_target
= true;
4857 fs_visitor::setup_vs_payload()
4859 /* R0: thread header, R1: urb handles */
4860 payload
.num_regs
= 2;
4864 * We are building the local ID push constant data using the simplest possible
4865 * method. We simply push the local IDs directly as they should appear in the
4866 * registers for the uvec3 gl_LocalInvocationID variable.
4868 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4869 * registers worth of push constant space.
4871 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4872 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4875 * FINISHME: There are a few easy optimizations to consider.
4877 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4878 * no need for using push constant space for that dimension.
4880 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4881 * easily use 16-bit words rather than 32-bit dwords in the push constant
4884 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4885 * conveying the data, and thereby reduce push constant usage.
4889 fs_visitor::setup_gs_payload()
4891 assert(stage
== MESA_SHADER_GEOMETRY
);
4893 struct brw_gs_prog_data
*gs_prog_data
=
4894 (struct brw_gs_prog_data
*) prog_data
;
4895 struct brw_vue_prog_data
*vue_prog_data
=
4896 (struct brw_vue_prog_data
*) prog_data
;
4898 /* R0: thread header, R1: output URB handles */
4899 payload
.num_regs
= 2;
4901 if (gs_prog_data
->include_primitive_id
) {
4902 /* R2: Primitive ID 0..7 */
4906 /* Use a maximum of 32 registers for push-model inputs. */
4907 const unsigned max_push_components
= 32;
4909 /* If pushing our inputs would take too many registers, reduce the URB read
4910 * length (which is in HWords, or 8 registers), and resort to pulling.
4912 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4913 * have to multiply by VerticesIn to obtain the total storage requirement.
4915 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4916 max_push_components
) {
4917 gs_prog_data
->base
.include_vue_handles
= true;
4919 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4920 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4922 vue_prog_data
->urb_read_length
=
4923 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4928 fs_visitor::setup_cs_payload()
4930 assert(devinfo
->gen
>= 7);
4931 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4933 payload
.num_regs
= 1;
4935 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4936 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4937 payload
.local_invocation_id_reg
= payload
.num_regs
;
4938 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4943 fs_visitor::calculate_register_pressure()
4945 invalidate_live_intervals();
4946 calculate_live_intervals();
4948 unsigned num_instructions
= 0;
4949 foreach_block(block
, cfg
)
4950 num_instructions
+= block
->instructions
.length();
4952 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
4954 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
4955 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
4956 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
4961 fs_visitor::optimize()
4963 /* Start by validating the shader we currently have. */
4966 /* bld is the common builder object pointing at the end of the program we
4967 * used to translate it into i965 IR. For the optimization and lowering
4968 * passes coming next, any code added after the end of the program without
4969 * having explicitly called fs_builder::at() clearly points at a mistake.
4970 * Ideally optimization passes wouldn't be part of the visitor so they
4971 * wouldn't have access to bld at all, but they do, so just in case some
4972 * pass forgets to ask for a location explicitly set it to NULL here to
4973 * make it trip. The dispatch width is initialized to a bogus value to
4974 * make sure that optimizations set the execution controls explicitly to
4975 * match the code they are manipulating instead of relying on the defaults.
4977 bld
= fs_builder(this, 64);
4979 assign_constant_locations();
4980 demote_pull_constants();
4984 split_virtual_grfs();
4987 #define OPT(pass, args...) ({ \
4989 bool this_progress = pass(args); \
4991 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
4992 char filename[64]; \
4993 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
4994 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
4996 backend_shader::dump_instructions(filename); \
5001 progress = progress || this_progress; \
5005 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5007 snprintf(filename
, 64, "%s%d-%s-00-start",
5008 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5010 backend_shader::dump_instructions(filename
);
5013 bool progress
= false;
5017 OPT(lower_simd_width
);
5018 OPT(lower_logical_sends
);
5025 OPT(remove_duplicate_mrf_writes
);
5029 OPT(opt_copy_propagate
);
5030 OPT(opt_predicated_break
, this);
5031 OPT(opt_cmod_propagation
);
5032 OPT(dead_code_eliminate
);
5033 OPT(opt_peephole_sel
);
5034 OPT(dead_control_flow_eliminate
, this);
5035 OPT(opt_register_renaming
);
5036 OPT(opt_redundant_discard_jumps
);
5037 OPT(opt_saturate_propagation
);
5038 OPT(opt_zero_samples
);
5039 OPT(register_coalesce
);
5040 OPT(compute_to_mrf
);
5041 OPT(eliminate_find_live_channel
);
5043 OPT(compact_virtual_grfs
);
5048 OPT(opt_sampler_eot
);
5050 if (OPT(lower_load_payload
)) {
5051 split_virtual_grfs();
5052 OPT(register_coalesce
);
5053 OPT(compute_to_mrf
);
5054 OPT(dead_code_eliminate
);
5057 OPT(opt_combine_constants
);
5058 OPT(lower_integer_multiplication
);
5060 lower_uniform_pull_constant_loads();
5066 * Three source instruction must have a GRF/MRF destination register.
5067 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5070 fs_visitor::fixup_3src_null_dest()
5072 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5073 if (inst
->is_3src() && inst
->dst
.is_null()) {
5074 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5081 fs_visitor::allocate_registers()
5083 bool allocated_without_spills
;
5085 static const enum instruction_scheduler_mode pre_modes
[] = {
5087 SCHEDULE_PRE_NON_LIFO
,
5091 /* Try each scheduling heuristic to see if it can successfully register
5092 * allocate without spilling. They should be ordered by decreasing
5093 * performance but increasing likelihood of allocating.
5095 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5096 schedule_instructions(pre_modes
[i
]);
5099 assign_regs_trivial();
5100 allocated_without_spills
= true;
5102 allocated_without_spills
= assign_regs(false);
5104 if (allocated_without_spills
)
5108 if (!allocated_without_spills
) {
5109 /* We assume that any spilling is worse than just dropping back to
5110 * SIMD8. There's probably actually some intermediate point where
5111 * SIMD16 with a couple of spills is still better.
5113 if (dispatch_width
== 16) {
5114 fail("Failure to register allocate. Reduce number of "
5115 "live scalar values to avoid this.");
5117 compiler
->shader_perf_log(log_data
,
5118 "%s shader triggered register spilling. "
5119 "Try reducing the number of live scalar "
5120 "values to improve performance.\n",
5124 /* Since we're out of heuristics, just go spill registers until we
5125 * get an allocation.
5127 while (!assign_regs(true)) {
5133 /* This must come after all optimization and register allocation, since
5134 * it inserts dead code that happens to have side effects, and it does
5135 * so based on the actual physical registers in use.
5137 insert_gen4_send_dependency_workarounds();
5142 schedule_instructions(SCHEDULE_POST
);
5144 if (last_scratch
> 0)
5145 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5149 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5151 assert(stage
== MESA_SHADER_VERTEX
);
5155 if (shader_time_index
>= 0)
5156 emit_shader_time_begin();
5163 compute_clip_distance(clip_planes
);
5167 if (shader_time_index
>= 0)
5168 emit_shader_time_end();
5174 assign_curb_setup();
5175 assign_vs_urb_setup();
5177 fixup_3src_null_dest();
5178 allocate_registers();
5184 fs_visitor::run_gs()
5186 assert(stage
== MESA_SHADER_GEOMETRY
);
5190 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5192 if (gs_compile
->control_data_header_size_bits
> 0) {
5193 /* Create a VGRF to store accumulated control data bits. */
5194 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5196 /* If we're outputting more than 32 control data bits, then EmitVertex()
5197 * will set control_data_bits to 0 after emitting the first vertex.
5198 * Otherwise, we need to initialize it to 0 here.
5200 if (gs_compile
->control_data_header_size_bits
<= 32) {
5201 const fs_builder abld
= bld
.annotate("initialize control data bits");
5202 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5206 if (shader_time_index
>= 0)
5207 emit_shader_time_begin();
5211 emit_gs_thread_end();
5213 if (shader_time_index
>= 0)
5214 emit_shader_time_end();
5223 assign_curb_setup();
5224 assign_gs_urb_setup();
5226 fixup_3src_null_dest();
5227 allocate_registers();
5233 fs_visitor::run_fs(bool do_rep_send
)
5235 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5236 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5238 assert(stage
== MESA_SHADER_FRAGMENT
);
5240 if (devinfo
->gen
>= 6)
5241 setup_payload_gen6();
5243 setup_payload_gen4();
5247 } else if (do_rep_send
) {
5248 assert(dispatch_width
== 16);
5249 emit_repclear_shader();
5251 if (shader_time_index
>= 0)
5252 emit_shader_time_begin();
5254 calculate_urb_setup();
5255 if (nir
->info
.inputs_read
> 0) {
5256 if (devinfo
->gen
< 6)
5257 emit_interpolation_setup_gen4();
5259 emit_interpolation_setup_gen6();
5262 /* We handle discards by keeping track of the still-live pixels in f0.1.
5263 * Initialize it with the dispatched pixels.
5265 if (wm_prog_data
->uses_kill
) {
5266 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5267 discard_init
->flag_subreg
= 1;
5270 /* Generate FS IR for main(). (the visitor only descends into
5271 * functions called "main").
5278 if (wm_prog_data
->uses_kill
)
5279 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5281 if (wm_key
->alpha_test_func
)
5286 if (shader_time_index
>= 0)
5287 emit_shader_time_end();
5293 assign_curb_setup();
5296 fixup_3src_null_dest();
5297 allocate_registers();
5303 if (dispatch_width
== 8)
5304 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5306 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5312 fs_visitor::run_cs()
5314 assert(stage
== MESA_SHADER_COMPUTE
);
5318 if (shader_time_index
>= 0)
5319 emit_shader_time_begin();
5326 emit_cs_terminate();
5328 if (shader_time_index
>= 0)
5329 emit_shader_time_end();
5335 assign_curb_setup();
5337 fixup_3src_null_dest();
5338 allocate_registers();
5347 * Return a bitfield where bit n is set if barycentric interpolation mode n
5348 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5351 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5352 bool shade_model_flat
,
5353 bool persample_shading
,
5354 const nir_shader
*shader
)
5356 unsigned barycentric_interp_modes
= 0;
5358 nir_foreach_variable(var
, &shader
->inputs
) {
5359 enum glsl_interp_qualifier interp_qualifier
=
5360 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5361 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5362 bool is_sample
= var
->data
.sample
|| persample_shading
;
5363 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5364 (var
->data
.location
== VARYING_SLOT_COL1
);
5366 /* Ignore WPOS and FACE, because they don't require interpolation. */
5367 if (var
->data
.location
== VARYING_SLOT_POS
||
5368 var
->data
.location
== VARYING_SLOT_FACE
)
5371 /* Determine the set (or sets) of barycentric coordinates needed to
5372 * interpolate this variable. Note that when
5373 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5374 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5375 * for lit pixels, so we need both sets of barycentric coordinates.
5377 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5379 barycentric_interp_modes
|=
5380 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5381 } else if (is_sample
) {
5382 barycentric_interp_modes
|=
5383 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5385 if ((!is_centroid
&& !is_sample
) ||
5386 devinfo
->needs_unlit_centroid_workaround
) {
5387 barycentric_interp_modes
|=
5388 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5390 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5391 (!(shade_model_flat
&& is_gl_Color
) &&
5392 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5394 barycentric_interp_modes
|=
5395 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5396 } else if (is_sample
) {
5397 barycentric_interp_modes
|=
5398 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5400 if ((!is_centroid
&& !is_sample
) ||
5401 devinfo
->needs_unlit_centroid_workaround
) {
5402 barycentric_interp_modes
|=
5403 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5408 return barycentric_interp_modes
;
5412 computed_depth_mode(const nir_shader
*shader
)
5414 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5415 switch (shader
->info
.fs
.depth_layout
) {
5416 case FRAG_DEPTH_LAYOUT_NONE
:
5417 case FRAG_DEPTH_LAYOUT_ANY
:
5418 return BRW_PSCDEPTH_ON
;
5419 case FRAG_DEPTH_LAYOUT_GREATER
:
5420 return BRW_PSCDEPTH_ON_GE
;
5421 case FRAG_DEPTH_LAYOUT_LESS
:
5422 return BRW_PSCDEPTH_ON_LE
;
5423 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5424 return BRW_PSCDEPTH_OFF
;
5427 return BRW_PSCDEPTH_OFF
;
5431 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5433 const struct brw_wm_prog_key
*key
,
5434 struct brw_wm_prog_data
*prog_data
,
5435 const nir_shader
*src_shader
,
5436 struct gl_program
*prog
,
5437 int shader_time_index8
, int shader_time_index16
,
5439 unsigned *final_assembly_size
,
5442 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5443 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5445 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5447 /* key->alpha_test_func means simulating alpha testing via discards,
5448 * so the shader definitely kills pixels.
5450 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5451 prog_data
->uses_omask
=
5452 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5453 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5454 prog_data
->computed_stencil
=
5455 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5457 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5459 prog_data
->barycentric_interp_modes
=
5460 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5462 key
->persample_shading
,
5465 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5466 &prog_data
->base
, prog
, shader
, 8,
5467 shader_time_index8
);
5468 if (!v
.run_fs(false /* do_rep_send */)) {
5470 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5475 cfg_t
*simd16_cfg
= NULL
;
5476 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5477 &prog_data
->base
, prog
, shader
, 16,
5478 shader_time_index16
);
5479 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5480 if (!v
.simd16_unsupported
) {
5481 /* Try a SIMD16 compile */
5482 v2
.import_uniforms(&v
);
5483 if (!v2
.run_fs(use_rep_send
)) {
5484 compiler
->shader_perf_log(log_data
,
5485 "SIMD16 shader failed to compile: %s",
5488 simd16_cfg
= v2
.cfg
;
5494 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5495 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5497 prog_data
->no_8
= true;
5500 prog_data
->no_8
= false;
5503 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5504 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5506 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5507 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5508 shader
->info
.label
? shader
->info
.label
:
5510 shader
->info
.name
));
5514 g
.generate_code(simd8_cfg
, 8);
5516 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5518 return g
.get_assembly(final_assembly_size
);
5522 brw_cs_fill_local_id_payload(const struct brw_cs_prog_data
*prog_data
,
5523 void *buffer
, uint32_t threads
, uint32_t stride
)
5525 if (prog_data
->local_invocation_id_regs
== 0)
5528 /* 'stride' should be an integer number of registers, that is, a multiple
5531 assert(stride
% 32 == 0);
5533 unsigned x
= 0, y
= 0, z
= 0;
5534 for (unsigned t
= 0; t
< threads
; t
++) {
5535 uint32_t *param
= (uint32_t *) buffer
+ stride
* t
/ 4;
5537 for (unsigned i
= 0; i
< prog_data
->simd_size
; i
++) {
5538 param
[0 * prog_data
->simd_size
+ i
] = x
;
5539 param
[1 * prog_data
->simd_size
+ i
] = y
;
5540 param
[2 * prog_data
->simd_size
+ i
] = z
;
5543 if (x
== prog_data
->local_size
[0]) {
5546 if (y
== prog_data
->local_size
[1]) {
5549 if (z
== prog_data
->local_size
[2])
5558 fs_visitor::emit_cs_local_invocation_id_setup()
5560 assert(stage
== MESA_SHADER_COMPUTE
);
5562 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5564 struct brw_reg src
=
5565 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5566 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5568 src
.nr
+= dispatch_width
/ 8;
5569 bld
.MOV(offset(*reg
, bld
, 1), src
);
5570 src
.nr
+= dispatch_width
/ 8;
5571 bld
.MOV(offset(*reg
, bld
, 2), src
);
5577 fs_visitor::emit_cs_work_group_id_setup()
5579 assert(stage
== MESA_SHADER_COMPUTE
);
5581 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5583 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5584 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5585 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5587 bld
.MOV(*reg
, r0_1
);
5588 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5589 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5595 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5597 const struct brw_cs_prog_key
*key
,
5598 struct brw_cs_prog_data
*prog_data
,
5599 const nir_shader
*src_shader
,
5600 int shader_time_index
,
5601 unsigned *final_assembly_size
,
5604 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5605 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5607 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5609 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5610 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5611 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5612 unsigned local_workgroup_size
=
5613 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5614 shader
->info
.cs
.local_size
[2];
5616 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5619 const char *fail_msg
= NULL
;
5621 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5623 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5624 NULL
, /* Never used in core profile */
5625 shader
, 8, shader_time_index
);
5627 fail_msg
= v8
.fail_msg
;
5628 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5630 prog_data
->simd_size
= 8;
5633 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5634 NULL
, /* Never used in core profile */
5635 shader
, 16, shader_time_index
);
5636 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5637 !fail_msg
&& !v8
.simd16_unsupported
&&
5638 local_workgroup_size
<= 16 * max_cs_threads
) {
5639 /* Try a SIMD16 compile */
5640 v16
.import_uniforms(&v8
);
5641 if (!v16
.run_cs()) {
5642 compiler
->shader_perf_log(log_data
,
5643 "SIMD16 shader failed to compile: %s",
5647 "Couldn't generate SIMD16 program and not "
5648 "enough threads for SIMD8";
5652 prog_data
->simd_size
= 16;
5656 if (unlikely(cfg
== NULL
)) {
5659 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5664 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5665 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5666 if (INTEL_DEBUG
& DEBUG_CS
) {
5667 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5668 shader
->info
.label
? shader
->info
.label
:
5671 g
.enable_debug(name
);
5674 g
.generate_code(cfg
, prog_data
->simd_size
);
5676 return g
.get_assembly(final_assembly_size
);