2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * This file drives the GLSL IR -> LIR translation, contains the
27 * optimizations on the LIR, and drives the generation of native code
31 #include "main/macros.h"
32 #include "brw_context.h"
37 #include "brw_vec4_gs_visitor.h"
39 #include "brw_program.h"
40 #include "brw_dead_control_flow.h"
41 #include "glsl/nir/glsl_types.h"
46 fs_inst::init(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
47 const fs_reg
*src
, unsigned sources
)
49 memset(this, 0, sizeof(*this));
51 this->src
= new fs_reg
[MAX2(sources
, 3)];
52 for (unsigned i
= 0; i
< sources
; i
++)
53 this->src
[i
] = src
[i
];
55 this->opcode
= opcode
;
57 this->sources
= sources
;
58 this->exec_size
= exec_size
;
60 assert(dst
.file
!= IMM
&& dst
.file
!= UNIFORM
);
62 assert(this->exec_size
!= 0);
64 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
66 /* This will be the case for almost all instructions. */
73 this->regs_written
= DIV_ROUND_UP(dst
.component_size(exec_size
),
77 this->regs_written
= 0;
81 unreachable("Invalid destination register file");
84 this->writes_accumulator
= false;
89 init(BRW_OPCODE_NOP
, 8, dst
, NULL
, 0);
92 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
)
94 init(opcode
, exec_size
, reg_undef
, NULL
, 0);
97 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
)
99 init(opcode
, exec_size
, dst
, NULL
, 0);
102 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
105 const fs_reg src
[1] = { src0
};
106 init(opcode
, exec_size
, dst
, src
, 1);
109 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
110 const fs_reg
&src0
, const fs_reg
&src1
)
112 const fs_reg src
[2] = { src0
, src1
};
113 init(opcode
, exec_size
, dst
, src
, 2);
116 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_size
, const fs_reg
&dst
,
117 const fs_reg
&src0
, const fs_reg
&src1
, const fs_reg
&src2
)
119 const fs_reg src
[3] = { src0
, src1
, src2
};
120 init(opcode
, exec_size
, dst
, src
, 3);
123 fs_inst::fs_inst(enum opcode opcode
, uint8_t exec_width
, const fs_reg
&dst
,
124 const fs_reg src
[], unsigned sources
)
126 init(opcode
, exec_width
, dst
, src
, sources
);
129 fs_inst::fs_inst(const fs_inst
&that
)
131 memcpy(this, &that
, sizeof(that
));
133 this->src
= new fs_reg
[MAX2(that
.sources
, 3)];
135 for (unsigned i
= 0; i
< that
.sources
; i
++)
136 this->src
[i
] = that
.src
[i
];
145 fs_inst::resize_sources(uint8_t num_sources
)
147 if (this->sources
!= num_sources
) {
148 fs_reg
*src
= new fs_reg
[MAX2(num_sources
, 3)];
150 for (unsigned i
= 0; i
< MIN2(this->sources
, num_sources
); ++i
)
151 src
[i
] = this->src
[i
];
155 this->sources
= num_sources
;
160 fs_visitor::VARYING_PULL_CONSTANT_LOAD(const fs_builder
&bld
,
162 const fs_reg
&surf_index
,
163 const fs_reg
&varying_offset
,
164 uint32_t const_offset
)
166 /* We have our constant surface use a pitch of 4 bytes, so our index can
167 * be any component of a vector, and then we load 4 contiguous
168 * components starting from that.
170 * We break down the const_offset to a portion added to the variable
171 * offset and a portion done using reg_offset, which means that if you
172 * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
173 * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
174 * CSE can later notice that those loads are all the same and eliminate
175 * the redundant ones.
177 fs_reg vec4_offset
= vgrf(glsl_type::int_type
);
178 bld
.ADD(vec4_offset
, varying_offset
, brw_imm_ud(const_offset
& ~0xf));
181 if (devinfo
->gen
== 4 && bld
.dispatch_width() == 8) {
182 /* Pre-gen5, we can either use a SIMD8 message that requires (header,
183 * u, v, r) as parameters, or we can just use the SIMD16 message
184 * consisting of (header, u). We choose the second, at the cost of a
185 * longer return length.
191 if (devinfo
->gen
>= 7)
192 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
;
194 op
= FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
;
196 int regs_written
= 4 * (bld
.dispatch_width() / 8) * scale
;
197 fs_reg vec4_result
= fs_reg(VGRF
, alloc
.allocate(regs_written
), dst
.type
);
198 fs_inst
*inst
= bld
.emit(op
, vec4_result
, surf_index
, vec4_offset
);
199 inst
->regs_written
= regs_written
;
201 if (devinfo
->gen
< 7) {
202 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
);
203 inst
->header_size
= 1;
204 if (devinfo
->gen
== 4)
207 inst
->mlen
= 1 + bld
.dispatch_width() / 8;
210 bld
.MOV(dst
, offset(vec4_result
, bld
, ((const_offset
& 0xf) / 4) * scale
));
214 * A helper for MOV generation for fixing up broken hardware SEND dependency
218 fs_visitor::DEP_RESOLVE_MOV(const fs_builder
&bld
, int grf
)
220 /* The caller always wants uncompressed to emit the minimal extra
221 * dependencies, and to avoid having to deal with aligning its regs to 2.
223 const fs_builder ubld
= bld
.annotate("send dependency resolve")
226 ubld
.MOV(ubld
.null_reg_f(), fs_reg(VGRF
, grf
, BRW_REGISTER_TYPE_F
));
230 fs_inst::equals(fs_inst
*inst
) const
232 return (opcode
== inst
->opcode
&&
233 dst
.equals(inst
->dst
) &&
234 src
[0].equals(inst
->src
[0]) &&
235 src
[1].equals(inst
->src
[1]) &&
236 src
[2].equals(inst
->src
[2]) &&
237 saturate
== inst
->saturate
&&
238 predicate
== inst
->predicate
&&
239 conditional_mod
== inst
->conditional_mod
&&
240 mlen
== inst
->mlen
&&
241 base_mrf
== inst
->base_mrf
&&
242 target
== inst
->target
&&
244 header_size
== inst
->header_size
&&
245 shadow_compare
== inst
->shadow_compare
&&
246 exec_size
== inst
->exec_size
&&
247 offset
== inst
->offset
);
251 fs_inst::overwrites_reg(const fs_reg
®
) const
253 return reg
.in_range(dst
, regs_written
);
257 fs_inst::is_send_from_grf() const
260 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
261 case SHADER_OPCODE_SHADER_TIME_ADD
:
262 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
264 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
265 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
266 case SHADER_OPCODE_UNTYPED_ATOMIC
:
267 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
268 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
269 case SHADER_OPCODE_TYPED_ATOMIC
:
270 case SHADER_OPCODE_TYPED_SURFACE_READ
:
271 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
272 case SHADER_OPCODE_URB_WRITE_SIMD8
:
273 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
274 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
275 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
276 case SHADER_OPCODE_URB_READ_SIMD8
:
277 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
279 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
280 return src
[1].file
== VGRF
;
281 case FS_OPCODE_FB_WRITE
:
282 return src
[0].file
== VGRF
;
285 return src
[0].file
== VGRF
;
292 * Returns true if this instruction's sources and destinations cannot
293 * safely be the same register.
295 * In most cases, a register can be written over safely by the same
296 * instruction that is its last use. For a single instruction, the
297 * sources are dereferenced before writing of the destination starts
300 * However, there are a few cases where this can be problematic:
302 * - Virtual opcodes that translate to multiple instructions in the
303 * code generator: if src == dst and one instruction writes the
304 * destination before a later instruction reads the source, then
305 * src will have been clobbered.
307 * - SIMD16 compressed instructions with certain regioning (see below).
309 * The register allocator uses this information to set up conflicts between
310 * GRF sources and the destination.
313 fs_inst::has_source_and_destination_hazard() const
316 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
317 /* Multiple partial writes to the destination */
320 /* The SIMD16 compressed instruction
322 * add(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
324 * is actually decoded in hardware as:
326 * add(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
327 * add(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
329 * Which is safe. However, if we have uniform accesses
330 * happening, we get into trouble:
332 * add(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
333 * add(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
335 * Now our destination for the first instruction overwrote the
336 * second instruction's src0, and we get garbage for those 8
337 * pixels. There's a similar issue for the pre-gen6
338 * pixel_x/pixel_y, which are registers of 16-bit values and thus
339 * would get stomped by the first decode as well.
341 if (exec_size
== 16) {
342 for (int i
= 0; i
< sources
; i
++) {
343 if (src
[i
].file
== VGRF
&& (src
[i
].stride
== 0 ||
344 src
[i
].type
== BRW_REGISTER_TYPE_UW
||
345 src
[i
].type
== BRW_REGISTER_TYPE_W
||
346 src
[i
].type
== BRW_REGISTER_TYPE_UB
||
347 src
[i
].type
== BRW_REGISTER_TYPE_B
)) {
357 fs_inst::is_copy_payload(const brw::simple_allocator
&grf_alloc
) const
359 if (this->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
362 fs_reg reg
= this->src
[0];
363 if (reg
.file
!= VGRF
|| reg
.reg_offset
!= 0 || reg
.stride
== 0)
366 if (grf_alloc
.sizes
[reg
.nr
] != this->regs_written
)
369 for (int i
= 0; i
< this->sources
; i
++) {
370 reg
.type
= this->src
[i
].type
;
371 if (!this->src
[i
].equals(reg
))
374 if (i
< this->header_size
) {
377 reg
.reg_offset
+= this->exec_size
/ 8;
385 fs_inst::can_do_source_mods(const struct brw_device_info
*devinfo
)
387 if (devinfo
->gen
== 6 && is_math())
390 if (is_send_from_grf())
393 if (!backend_instruction::can_do_source_mods())
400 fs_inst::can_change_types() const
402 return dst
.type
== src
[0].type
&&
403 !src
[0].abs
&& !src
[0].negate
&& !saturate
&&
404 (opcode
== BRW_OPCODE_MOV
||
405 (opcode
== BRW_OPCODE_SEL
&&
406 dst
.type
== src
[1].type
&&
407 predicate
!= BRW_PREDICATE_NONE
&&
408 !src
[1].abs
&& !src
[1].negate
));
412 fs_inst::has_side_effects() const
414 return this->eot
|| backend_instruction::has_side_effects();
420 memset(this, 0, sizeof(*this));
424 /** Generic unset register constructor. */
428 this->file
= BAD_FILE
;
431 fs_reg::fs_reg(struct ::brw_reg reg
) :
434 this->reg_offset
= 0;
435 this->subreg_offset
= 0;
436 this->reladdr
= NULL
;
438 if (this->file
== IMM
&&
439 (this->type
!= BRW_REGISTER_TYPE_V
&&
440 this->type
!= BRW_REGISTER_TYPE_UV
&&
441 this->type
!= BRW_REGISTER_TYPE_VF
)) {
447 fs_reg::equals(const fs_reg
&r
) const
449 return (this->backend_reg::equals(r
) &&
450 subreg_offset
== r
.subreg_offset
&&
451 !reladdr
&& !r
.reladdr
&&
456 fs_reg::set_smear(unsigned subreg
)
458 assert(file
!= ARF
&& file
!= FIXED_GRF
&& file
!= IMM
);
459 subreg_offset
= subreg
* type_sz(type
);
465 fs_reg::is_contiguous() const
471 fs_reg::component_size(unsigned width
) const
473 const unsigned stride
= ((file
!= ARF
&& file
!= FIXED_GRF
) ? this->stride
:
476 return MAX2(width
* stride
, 1) * type_sz(type
);
480 type_size_scalar(const struct glsl_type
*type
)
482 unsigned int size
, i
;
484 switch (type
->base_type
) {
487 case GLSL_TYPE_FLOAT
:
489 return type
->components();
490 case GLSL_TYPE_ARRAY
:
491 return type_size_scalar(type
->fields
.array
) * type
->length
;
492 case GLSL_TYPE_STRUCT
:
494 for (i
= 0; i
< type
->length
; i
++) {
495 size
+= type_size_scalar(type
->fields
.structure
[i
].type
);
498 case GLSL_TYPE_SAMPLER
:
499 /* Samplers take up no register space, since they're baked in at
503 case GLSL_TYPE_ATOMIC_UINT
:
505 case GLSL_TYPE_SUBROUTINE
:
507 case GLSL_TYPE_IMAGE
:
508 return BRW_IMAGE_PARAM_SIZE
;
510 case GLSL_TYPE_ERROR
:
511 case GLSL_TYPE_INTERFACE
:
512 case GLSL_TYPE_DOUBLE
:
513 unreachable("not reached");
520 * Returns the number of scalar components needed to store type, assuming
521 * that vectors are padded out to vec4.
523 * This has the packing rules of type_size_vec4(), but counts components
524 * similar to type_size_scalar().
527 type_size_vec4_times_4(const struct glsl_type
*type
)
529 return 4 * type_size_vec4(type
);
533 * Create a MOV to read the timestamp register.
535 * The caller is responsible for emitting the MOV. The return value is
536 * the destination of the MOV, with extra parameters set.
539 fs_visitor::get_timestamp(const fs_builder
&bld
)
541 assert(devinfo
->gen
>= 7);
543 fs_reg ts
= fs_reg(retype(brw_vec4_reg(BRW_ARCHITECTURE_REGISTER_FILE
,
546 BRW_REGISTER_TYPE_UD
));
548 fs_reg dst
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
550 /* We want to read the 3 fields we care about even if it's not enabled in
553 bld
.group(4, 0).exec_all().MOV(dst
, ts
);
559 fs_visitor::emit_shader_time_begin()
561 shader_start_time
= get_timestamp(bld
.annotate("shader time start"));
563 /* We want only the low 32 bits of the timestamp. Since it's running
564 * at the GPU clock rate of ~1.2ghz, it will roll over every ~3 seconds,
565 * which is plenty of time for our purposes. It is identical across the
566 * EUs, but since it's tracking GPU core speed it will increment at a
567 * varying rate as render P-states change.
569 shader_start_time
.set_smear(0);
573 fs_visitor::emit_shader_time_end()
575 /* Insert our code just before the final SEND with EOT. */
576 exec_node
*end
= this->instructions
.get_tail();
577 assert(end
&& ((fs_inst
*) end
)->eot
);
578 const fs_builder ibld
= bld
.annotate("shader time end")
579 .exec_all().at(NULL
, end
);
581 fs_reg shader_end_time
= get_timestamp(ibld
);
583 /* We only use the low 32 bits of the timestamp - see
584 * emit_shader_time_begin()).
586 * We could also check if render P-states have changed (or anything
587 * else that might disrupt timing) by setting smear to 2 and checking if
588 * that field is != 0.
590 shader_end_time
.set_smear(0);
592 /* Check that there weren't any timestamp reset events (assuming these
593 * were the only two timestamp reads that happened).
595 fs_reg reset
= shader_end_time
;
597 set_condmod(BRW_CONDITIONAL_Z
,
598 ibld
.AND(ibld
.null_reg_ud(), reset
, brw_imm_ud(1u)));
599 ibld
.IF(BRW_PREDICATE_NORMAL
);
601 fs_reg start
= shader_start_time
;
603 fs_reg diff
= fs_reg(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_UD
);
606 const fs_builder cbld
= ibld
.group(1, 0);
607 cbld
.group(1, 0).ADD(diff
, start
, shader_end_time
);
609 /* If there were no instructions between the two timestamp gets, the diff
610 * is 2 cycles. Remove that overhead, so I can forget about that when
611 * trying to determine the time taken for single instructions.
613 cbld
.ADD(diff
, diff
, brw_imm_ud(-2u));
614 SHADER_TIME_ADD(cbld
, 0, diff
);
615 SHADER_TIME_ADD(cbld
, 1, brw_imm_ud(1u));
616 ibld
.emit(BRW_OPCODE_ELSE
);
617 SHADER_TIME_ADD(cbld
, 2, brw_imm_ud(1u));
618 ibld
.emit(BRW_OPCODE_ENDIF
);
622 fs_visitor::SHADER_TIME_ADD(const fs_builder
&bld
,
623 int shader_time_subindex
,
626 int index
= shader_time_index
* 3 + shader_time_subindex
;
627 struct brw_reg offset
= brw_imm_d(index
* SHADER_TIME_STRIDE
);
630 if (dispatch_width
== 8)
631 payload
= vgrf(glsl_type::uvec2_type
);
633 payload
= vgrf(glsl_type::uint_type
);
635 bld
.emit(SHADER_OPCODE_SHADER_TIME_ADD
, fs_reg(), payload
, offset
, value
);
639 fs_visitor::vfail(const char *format
, va_list va
)
648 msg
= ralloc_vasprintf(mem_ctx
, format
, va
);
649 msg
= ralloc_asprintf(mem_ctx
, "%s compile failed: %s\n", stage_abbrev
, msg
);
651 this->fail_msg
= msg
;
654 fprintf(stderr
, "%s", msg
);
659 fs_visitor::fail(const char *format
, ...)
663 va_start(va
, format
);
669 * Mark this program as impossible to compile in SIMD16 mode.
671 * During the SIMD8 compile (which happens first), we can detect and flag
672 * things that are unsupported in SIMD16 mode, so the compiler can skip
673 * the SIMD16 compile altogether.
675 * During a SIMD16 compile (if one happens anyway), this just calls fail().
678 fs_visitor::no16(const char *msg
)
680 if (dispatch_width
== 16) {
683 simd16_unsupported
= true;
685 compiler
->shader_perf_log(log_data
,
686 "SIMD16 shader failed to compile: %s", msg
);
691 * Returns true if the instruction has a flag that means it won't
692 * update an entire destination register.
694 * For example, dead code elimination and live variable analysis want to know
695 * when a write to a variable screens off any preceding values that were in
699 fs_inst::is_partial_write() const
701 return ((this->predicate
&& this->opcode
!= BRW_OPCODE_SEL
) ||
702 (this->exec_size
* type_sz(this->dst
.type
)) < 32 ||
703 !this->dst
.is_contiguous());
707 fs_inst::components_read(unsigned i
) const
710 case FS_OPCODE_LINTERP
:
716 case FS_OPCODE_PIXEL_X
:
717 case FS_OPCODE_PIXEL_Y
:
721 case FS_OPCODE_FB_WRITE_LOGICAL
:
722 assert(src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
723 /* First/second FB write color. */
725 return src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
729 case SHADER_OPCODE_TEX_LOGICAL
:
730 case SHADER_OPCODE_TXD_LOGICAL
:
731 case SHADER_OPCODE_TXF_LOGICAL
:
732 case SHADER_OPCODE_TXL_LOGICAL
:
733 case SHADER_OPCODE_TXS_LOGICAL
:
734 case FS_OPCODE_TXB_LOGICAL
:
735 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
736 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
737 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
738 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
739 case SHADER_OPCODE_LOD_LOGICAL
:
740 case SHADER_OPCODE_TG4_LOGICAL
:
741 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
742 assert(src
[8].file
== IMM
&& src
[9].file
== IMM
);
743 /* Texture coordinates. */
746 /* Texture derivatives. */
747 else if ((i
== 2 || i
== 3) && opcode
== SHADER_OPCODE_TXD_LOGICAL
)
749 /* Texture offset. */
753 else if (i
== 5 && opcode
== SHADER_OPCODE_TXF_CMS_W_LOGICAL
)
758 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
759 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
760 assert(src
[3].file
== IMM
);
761 /* Surface coordinates. */
764 /* Surface operation source (ignored for reads). */
770 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
771 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
772 assert(src
[3].file
== IMM
&&
774 /* Surface coordinates. */
777 /* Surface operation source. */
783 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
784 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
: {
785 assert(src
[3].file
== IMM
&&
787 const unsigned op
= src
[4].ud
;
788 /* Surface coordinates. */
791 /* Surface operation source. */
792 else if (i
== 1 && op
== BRW_AOP_CMPWR
)
794 else if (i
== 1 && (op
== BRW_AOP_INC
|| op
== BRW_AOP_DEC
||
795 op
== BRW_AOP_PREDEC
))
807 fs_inst::regs_read(int arg
) const
810 case FS_OPCODE_FB_WRITE
:
811 case SHADER_OPCODE_URB_WRITE_SIMD8
:
812 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
813 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
814 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
815 case SHADER_OPCODE_URB_READ_SIMD8
:
816 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
817 case SHADER_OPCODE_UNTYPED_ATOMIC
:
818 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
819 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
820 case SHADER_OPCODE_TYPED_ATOMIC
:
821 case SHADER_OPCODE_TYPED_SURFACE_READ
:
822 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
823 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
828 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
829 /* The payload is actually stored in src1 */
834 case FS_OPCODE_LINTERP
:
839 case SHADER_OPCODE_LOAD_PAYLOAD
:
840 if (arg
< this->header_size
)
844 case CS_OPCODE_CS_TERMINATE
:
845 case SHADER_OPCODE_BARRIER
:
848 case SHADER_OPCODE_MOV_INDIRECT
:
850 assert(src
[2].file
== IMM
);
851 unsigned region_length
= src
[2].ud
;
853 if (src
[0].file
== FIXED_GRF
) {
854 /* If the start of the region is not register aligned, then
855 * there's some portion of the register that's technically
856 * unread at the beginning.
858 * However, the register allocator works in terms of whole
859 * registers, and does not use subnr. It assumes that the
860 * read starts at the beginning of the register, and extends
861 * regs_read() whole registers beyond that.
863 * To compensate, we extend the region length to include this
864 * unread portion at the beginning.
867 region_length
+= src
[0].subnr
* type_sz(src
[0].type
);
869 return DIV_ROUND_UP(region_length
, REG_SIZE
);
871 assert(!"Invalid register file");
877 if (is_tex() && arg
== 0 && src
[0].file
== VGRF
)
882 switch (src
[arg
].file
) {
892 return DIV_ROUND_UP(components_read(arg
) *
893 src
[arg
].component_size(exec_size
),
896 unreachable("MRF registers are not allowed as sources");
902 fs_inst::reads_flag() const
908 fs_inst::writes_flag() const
910 return (conditional_mod
&& (opcode
!= BRW_OPCODE_SEL
&&
911 opcode
!= BRW_OPCODE_IF
&&
912 opcode
!= BRW_OPCODE_WHILE
)) ||
913 opcode
== FS_OPCODE_MOV_DISPATCH_TO_FLAGS
;
917 * Returns how many MRFs an FS opcode will write over.
919 * Note that this is not the 0 or 1 implied writes in an actual gen
920 * instruction -- the FS opcodes often generate MOVs in addition.
923 fs_visitor::implied_mrf_writes(fs_inst
*inst
)
928 if (inst
->base_mrf
== -1)
931 switch (inst
->opcode
) {
932 case SHADER_OPCODE_RCP
:
933 case SHADER_OPCODE_RSQ
:
934 case SHADER_OPCODE_SQRT
:
935 case SHADER_OPCODE_EXP2
:
936 case SHADER_OPCODE_LOG2
:
937 case SHADER_OPCODE_SIN
:
938 case SHADER_OPCODE_COS
:
939 return 1 * dispatch_width
/ 8;
940 case SHADER_OPCODE_POW
:
941 case SHADER_OPCODE_INT_QUOTIENT
:
942 case SHADER_OPCODE_INT_REMAINDER
:
943 return 2 * dispatch_width
/ 8;
944 case SHADER_OPCODE_TEX
:
946 case SHADER_OPCODE_TXD
:
947 case SHADER_OPCODE_TXF
:
948 case SHADER_OPCODE_TXF_CMS
:
949 case SHADER_OPCODE_TXF_CMS_W
:
950 case SHADER_OPCODE_TXF_MCS
:
951 case SHADER_OPCODE_TG4
:
952 case SHADER_OPCODE_TG4_OFFSET
:
953 case SHADER_OPCODE_TXL
:
954 case SHADER_OPCODE_TXS
:
955 case SHADER_OPCODE_LOD
:
956 case SHADER_OPCODE_SAMPLEINFO
:
958 case FS_OPCODE_FB_WRITE
:
960 case FS_OPCODE_GET_BUFFER_SIZE
:
961 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
962 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
964 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
966 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
968 case SHADER_OPCODE_UNTYPED_ATOMIC
:
969 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
970 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
971 case SHADER_OPCODE_TYPED_ATOMIC
:
972 case SHADER_OPCODE_TYPED_SURFACE_READ
:
973 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
974 case SHADER_OPCODE_URB_WRITE_SIMD8
:
975 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
976 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
977 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
978 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
979 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
980 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
981 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
984 unreachable("not reached");
989 fs_visitor::vgrf(const glsl_type
*const type
)
991 int reg_width
= dispatch_width
/ 8;
992 return fs_reg(VGRF
, alloc
.allocate(type_size_scalar(type
) * reg_width
),
993 brw_type_for_base_type(type
));
996 fs_reg::fs_reg(enum brw_reg_file file
, int nr
)
1001 this->type
= BRW_REGISTER_TYPE_F
;
1002 this->stride
= (file
== UNIFORM
? 0 : 1);
1005 fs_reg::fs_reg(enum brw_reg_file file
, int nr
, enum brw_reg_type type
)
1011 this->stride
= (file
== UNIFORM
? 0 : 1);
1014 /* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
1015 * This brings in those uniform definitions
1018 fs_visitor::import_uniforms(fs_visitor
*v
)
1020 this->push_constant_loc
= v
->push_constant_loc
;
1021 this->pull_constant_loc
= v
->pull_constant_loc
;
1022 this->uniforms
= v
->uniforms
;
1023 this->param_size
= v
->param_size
;
1027 fs_visitor::emit_fragcoord_interpolation(bool pixel_center_integer
,
1028 bool origin_upper_left
)
1030 assert(stage
== MESA_SHADER_FRAGMENT
);
1031 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1032 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec4_type
));
1034 bool flip
= !origin_upper_left
^ key
->render_to_fbo
;
1036 /* gl_FragCoord.x */
1037 if (pixel_center_integer
) {
1038 bld
.MOV(wpos
, this->pixel_x
);
1040 bld
.ADD(wpos
, this->pixel_x
, brw_imm_f(0.5f
));
1042 wpos
= offset(wpos
, bld
, 1);
1044 /* gl_FragCoord.y */
1045 if (!flip
&& pixel_center_integer
) {
1046 bld
.MOV(wpos
, this->pixel_y
);
1048 fs_reg pixel_y
= this->pixel_y
;
1049 float offset
= (pixel_center_integer
? 0.0f
: 0.5f
);
1052 pixel_y
.negate
= true;
1053 offset
+= key
->drawable_height
- 1.0f
;
1056 bld
.ADD(wpos
, pixel_y
, brw_imm_f(offset
));
1058 wpos
= offset(wpos
, bld
, 1);
1060 /* gl_FragCoord.z */
1061 if (devinfo
->gen
>= 6) {
1062 bld
.MOV(wpos
, fs_reg(brw_vec8_grf(payload
.source_depth_reg
, 0)));
1064 bld
.emit(FS_OPCODE_LINTERP
, wpos
,
1065 this->delta_xy
[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
],
1066 interp_reg(VARYING_SLOT_POS
, 2));
1068 wpos
= offset(wpos
, bld
, 1);
1070 /* gl_FragCoord.w: Already set up in emit_interpolation */
1071 bld
.MOV(wpos
, this->wpos_w
);
1077 fs_visitor::emit_linterp(const fs_reg
&attr
, const fs_reg
&interp
,
1078 glsl_interp_qualifier interpolation_mode
,
1079 bool is_centroid
, bool is_sample
)
1081 brw_wm_barycentric_interp_mode barycoord_mode
;
1082 if (devinfo
->gen
>= 6) {
1084 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1085 barycoord_mode
= BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
1087 barycoord_mode
= BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
1088 } else if (is_sample
) {
1089 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1090 barycoord_mode
= BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
1092 barycoord_mode
= BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
1094 if (interpolation_mode
== INTERP_QUALIFIER_SMOOTH
)
1095 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1097 barycoord_mode
= BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
1100 /* On Ironlake and below, there is only one interpolation mode.
1101 * Centroid interpolation doesn't mean anything on this hardware --
1102 * there is no multisampling.
1104 barycoord_mode
= BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
1106 return bld
.emit(FS_OPCODE_LINTERP
, attr
,
1107 this->delta_xy
[barycoord_mode
], interp
);
1111 fs_visitor::emit_general_interpolation(fs_reg
*attr
, const char *name
,
1112 const glsl_type
*type
,
1113 glsl_interp_qualifier interpolation_mode
,
1114 int *location
, bool mod_centroid
,
1117 assert(stage
== MESA_SHADER_FRAGMENT
);
1118 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1119 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1121 if (interpolation_mode
== INTERP_QUALIFIER_NONE
) {
1123 *location
== VARYING_SLOT_COL0
|| *location
== VARYING_SLOT_COL1
;
1124 if (key
->flat_shade
&& is_gl_Color
) {
1125 interpolation_mode
= INTERP_QUALIFIER_FLAT
;
1127 interpolation_mode
= INTERP_QUALIFIER_SMOOTH
;
1131 if (type
->is_array() || type
->is_matrix()) {
1132 const glsl_type
*elem_type
= glsl_get_array_element(type
);
1133 const unsigned length
= glsl_get_length(type
);
1135 for (unsigned i
= 0; i
< length
; i
++) {
1136 emit_general_interpolation(attr
, name
, elem_type
, interpolation_mode
,
1137 location
, mod_centroid
, mod_sample
);
1139 } else if (type
->is_record()) {
1140 for (unsigned i
= 0; i
< type
->length
; i
++) {
1141 const glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
1142 emit_general_interpolation(attr
, name
, field_type
, interpolation_mode
,
1143 location
, mod_centroid
, mod_sample
);
1146 assert(type
->is_scalar() || type
->is_vector());
1148 if (prog_data
->urb_setup
[*location
] == -1) {
1149 /* If there's no incoming setup data for this slot, don't
1150 * emit interpolation for it.
1152 *attr
= offset(*attr
, bld
, type
->vector_elements
);
1157 attr
->type
= brw_type_for_base_type(type
->get_scalar_type());
1159 if (interpolation_mode
== INTERP_QUALIFIER_FLAT
) {
1160 /* Constant interpolation (flat shading) case. The SF has
1161 * handed us defined values in only the constant offset
1162 * field of the setup reg.
1164 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1165 struct brw_reg interp
= interp_reg(*location
, i
);
1166 interp
= suboffset(interp
, 3);
1167 interp
.type
= attr
->type
;
1168 bld
.emit(FS_OPCODE_CINTERP
, *attr
, fs_reg(interp
));
1169 *attr
= offset(*attr
, bld
, 1);
1172 /* Smooth/noperspective interpolation case. */
1173 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
1174 struct brw_reg interp
= interp_reg(*location
, i
);
1175 if (devinfo
->needs_unlit_centroid_workaround
&& mod_centroid
) {
1176 /* Get the pixel/sample mask into f0 so that we know
1177 * which pixels are lit. Then, for each channel that is
1178 * unlit, replace the centroid data with non-centroid
1181 bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
1184 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1186 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1187 inst
->predicate_inverse
= true;
1188 if (devinfo
->has_pln
)
1189 inst
->no_dd_clear
= true;
1191 inst
= emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1192 mod_centroid
&& !key
->persample_shading
,
1193 mod_sample
|| key
->persample_shading
);
1194 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1195 inst
->predicate_inverse
= false;
1196 if (devinfo
->has_pln
)
1197 inst
->no_dd_check
= true;
1200 emit_linterp(*attr
, fs_reg(interp
), interpolation_mode
,
1201 mod_centroid
&& !key
->persample_shading
,
1202 mod_sample
|| key
->persample_shading
);
1204 if (devinfo
->gen
< 6 && interpolation_mode
== INTERP_QUALIFIER_SMOOTH
) {
1205 bld
.MUL(*attr
, *attr
, this->pixel_w
);
1207 *attr
= offset(*attr
, bld
, 1);
1215 fs_visitor::emit_frontfacing_interpolation()
1217 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::bool_type
));
1219 if (devinfo
->gen
>= 6) {
1220 /* Bit 15 of g0.0 is 0 if the polygon is front facing. We want to create
1221 * a boolean result from this (~0/true or 0/false).
1223 * We can use the fact that bit 15 is the MSB of g0.0:W to accomplish
1224 * this task in only one instruction:
1225 * - a negation source modifier will flip the bit; and
1226 * - a W -> D type conversion will sign extend the bit into the high
1227 * word of the destination.
1229 * An ASR 15 fills the low word of the destination.
1231 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
1234 bld
.ASR(*reg
, g0
, brw_imm_d(15));
1236 /* Bit 31 of g1.6 is 0 if the polygon is front facing. We want to create
1237 * a boolean result from this (1/true or 0/false).
1239 * Like in the above case, since the bit is the MSB of g1.6:UD we can use
1240 * the negation source modifier to flip it. Unfortunately the SHR
1241 * instruction only operates on UD (or D with an abs source modifier)
1242 * sources without negation.
1244 * Instead, use ASR (which will give ~0/true or 0/false).
1246 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
1249 bld
.ASR(*reg
, g1_6
, brw_imm_d(31));
1256 fs_visitor::compute_sample_position(fs_reg dst
, fs_reg int_sample_pos
)
1258 assert(stage
== MESA_SHADER_FRAGMENT
);
1259 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1260 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1262 if (key
->compute_pos_offset
) {
1263 /* Convert int_sample_pos to floating point */
1264 bld
.MOV(dst
, int_sample_pos
);
1265 /* Scale to the range [0, 1] */
1266 bld
.MUL(dst
, dst
, brw_imm_f(1 / 16.0f
));
1269 /* From ARB_sample_shading specification:
1270 * "When rendering to a non-multisample buffer, or if multisample
1271 * rasterization is disabled, gl_SamplePosition will always be
1274 bld
.MOV(dst
, brw_imm_f(0.5f
));
1279 fs_visitor::emit_samplepos_setup()
1281 assert(devinfo
->gen
>= 6);
1283 const fs_builder abld
= bld
.annotate("compute sample position");
1284 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::vec2_type
));
1286 fs_reg int_sample_x
= vgrf(glsl_type::int_type
);
1287 fs_reg int_sample_y
= vgrf(glsl_type::int_type
);
1289 /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
1290 * mode will be enabled.
1292 * From the Ivy Bridge PRM, volume 2 part 1, page 344:
1293 * R31.1:0 Position Offset X/Y for Slot[3:0]
1294 * R31.3:2 Position Offset X/Y for Slot[7:4]
1297 * The X, Y sample positions come in as bytes in thread payload. So, read
1298 * the positions using vstride=16, width=8, hstride=2.
1300 struct brw_reg sample_pos_reg
=
1301 stride(retype(brw_vec1_grf(payload
.sample_pos_reg
, 0),
1302 BRW_REGISTER_TYPE_B
), 16, 8, 2);
1304 if (dispatch_width
== 8) {
1305 abld
.MOV(int_sample_x
, fs_reg(sample_pos_reg
));
1307 abld
.half(0).MOV(half(int_sample_x
, 0), fs_reg(sample_pos_reg
));
1308 abld
.half(1).MOV(half(int_sample_x
, 1),
1309 fs_reg(suboffset(sample_pos_reg
, 16)));
1311 /* Compute gl_SamplePosition.x */
1312 compute_sample_position(pos
, int_sample_x
);
1313 pos
= offset(pos
, abld
, 1);
1314 if (dispatch_width
== 8) {
1315 abld
.MOV(int_sample_y
, fs_reg(suboffset(sample_pos_reg
, 1)));
1317 abld
.half(0).MOV(half(int_sample_y
, 0),
1318 fs_reg(suboffset(sample_pos_reg
, 1)));
1319 abld
.half(1).MOV(half(int_sample_y
, 1),
1320 fs_reg(suboffset(sample_pos_reg
, 17)));
1322 /* Compute gl_SamplePosition.y */
1323 compute_sample_position(pos
, int_sample_y
);
1328 fs_visitor::emit_sampleid_setup()
1330 assert(stage
== MESA_SHADER_FRAGMENT
);
1331 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1332 assert(devinfo
->gen
>= 6);
1334 const fs_builder abld
= bld
.annotate("compute sample id");
1335 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::int_type
));
1337 if (key
->compute_sample_id
) {
1338 fs_reg
t1(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_D
);
1340 fs_reg
t2(VGRF
, alloc
.allocate(1), BRW_REGISTER_TYPE_W
);
1342 /* The PS will be run in MSDISPMODE_PERSAMPLE. For example with
1343 * 8x multisampling, subspan 0 will represent sample N (where N
1344 * is 0, 2, 4 or 6), subspan 1 will represent sample 1, 3, 5 or
1345 * 7. We can find the value of N by looking at R0.0 bits 7:6
1346 * ("Starting Sample Pair Index (SSPI)") and multiplying by two
1347 * (since samples are always delivered in pairs). That is, we
1348 * compute 2*((R0.0 & 0xc0) >> 6) == (R0.0 & 0xc0) >> 5. Then
1349 * we need to add N to the sequence (0, 0, 0, 0, 1, 1, 1, 1) in
1350 * case of SIMD8 and sequence (0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2,
1351 * 2, 3, 3, 3, 3) in case of SIMD16. We compute this sequence by
1352 * populating a temporary variable with the sequence (0, 1, 2, 3),
1353 * and then reading from it using vstride=1, width=4, hstride=0.
1354 * These computations hold good for 4x multisampling as well.
1356 * For 2x MSAA and SIMD16, we want to use the sequence (0, 1, 0, 1):
1357 * the first four slots are sample 0 of subspan 0; the next four
1358 * are sample 1 of subspan 0; the third group is sample 0 of
1359 * subspan 1, and finally sample 1 of subspan 1.
1362 /* SKL+ has an extra bit for the Starting Sample Pair Index to
1363 * accomodate 16x MSAA.
1365 unsigned sspi_mask
= devinfo
->gen
>= 9 ? 0x1c0 : 0xc0;
1367 abld
.exec_all().group(1, 0)
1368 .AND(t1
, fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
1369 brw_imm_ud(sspi_mask
));
1370 abld
.exec_all().group(1, 0).SHR(t1
, t1
, brw_imm_d(5));
1372 /* This works for both SIMD8 and SIMD16 */
1373 abld
.exec_all().group(4, 0)
1374 .MOV(t2
, brw_imm_v(key
->persample_2x
? 0x1010 : 0x3210));
1376 /* This special instruction takes care of setting vstride=1,
1377 * width=4, hstride=0 of t2 during an ADD instruction.
1379 abld
.emit(FS_OPCODE_SET_SAMPLE_ID
, *reg
, t1
, t2
);
1381 /* As per GL_ARB_sample_shading specification:
1382 * "When rendering to a non-multisample buffer, or if multisample
1383 * rasterization is disabled, gl_SampleID will always be zero."
1385 abld
.MOV(*reg
, brw_imm_d(0));
1392 fs_visitor::resolve_source_modifiers(const fs_reg
&src
)
1394 if (!src
.abs
&& !src
.negate
)
1397 fs_reg temp
= bld
.vgrf(src
.type
);
1404 fs_visitor::emit_discard_jump()
1406 assert(((brw_wm_prog_data
*) this->prog_data
)->uses_kill
);
1408 /* For performance, after a discard, jump to the end of the
1409 * shader if all relevant channels have been discarded.
1411 fs_inst
*discard_jump
= bld
.emit(FS_OPCODE_DISCARD_JUMP
);
1412 discard_jump
->flag_subreg
= 1;
1414 discard_jump
->predicate
= (dispatch_width
== 8)
1415 ? BRW_PREDICATE_ALIGN1_ANY8H
1416 : BRW_PREDICATE_ALIGN1_ANY16H
;
1417 discard_jump
->predicate_inverse
= true;
1421 fs_visitor::emit_gs_thread_end()
1423 assert(stage
== MESA_SHADER_GEOMETRY
);
1425 struct brw_gs_prog_data
*gs_prog_data
=
1426 (struct brw_gs_prog_data
*) prog_data
;
1428 if (gs_compile
->control_data_header_size_bits
> 0) {
1429 emit_gs_control_data_bits(this->final_gs_vertex_count
);
1432 const fs_builder abld
= bld
.annotate("thread end");
1435 if (gs_prog_data
->static_vertex_count
!= -1) {
1436 foreach_in_list_reverse(fs_inst
, prev
, &this->instructions
) {
1437 if (prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8
||
1438 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
1439 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
1440 prev
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
) {
1443 /* Delete now dead instructions. */
1444 foreach_in_list_reverse_safe(exec_node
, dead
, &this->instructions
) {
1450 } else if (prev
->is_control_flow() || prev
->has_side_effects()) {
1454 fs_reg hdr
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1455 abld
.MOV(hdr
, fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
)));
1456 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, hdr
);
1459 fs_reg payload
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1460 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, 2);
1461 sources
[0] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1462 sources
[1] = this->final_gs_vertex_count
;
1463 abld
.LOAD_PAYLOAD(payload
, sources
, 2, 2);
1464 inst
= abld
.emit(SHADER_OPCODE_URB_WRITE_SIMD8
, reg_undef
, payload
);
1472 fs_visitor::assign_curb_setup()
1474 if (dispatch_width
== 8) {
1475 prog_data
->dispatch_grf_start_reg
= payload
.num_regs
;
1477 if (stage
== MESA_SHADER_FRAGMENT
) {
1478 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1479 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1480 } else if (stage
== MESA_SHADER_COMPUTE
) {
1481 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
1482 prog_data
->dispatch_grf_start_reg_16
= payload
.num_regs
;
1484 unreachable("Unsupported shader type!");
1488 prog_data
->curb_read_length
= ALIGN(stage_prog_data
->nr_params
, 8) / 8;
1490 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1491 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1492 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1493 if (inst
->src
[i
].file
== UNIFORM
) {
1494 int uniform_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1496 if (uniform_nr
>= 0 && uniform_nr
< (int) uniforms
) {
1497 constant_nr
= push_constant_loc
[uniform_nr
];
1499 /* Section 5.11 of the OpenGL 4.1 spec says:
1500 * "Out-of-bounds reads return undefined values, which include
1501 * values from other variables of the active program or zero."
1502 * Just return the first push constant.
1507 struct brw_reg brw_reg
= brw_vec1_grf(payload
.num_regs
+
1510 brw_reg
.abs
= inst
->src
[i
].abs
;
1511 brw_reg
.negate
= inst
->src
[i
].negate
;
1513 assert(inst
->src
[i
].stride
== 0);
1514 inst
->src
[i
] = byte_offset(
1515 retype(brw_reg
, inst
->src
[i
].type
),
1516 inst
->src
[i
].subreg_offset
);
1521 /* This may be updated in assign_urb_setup or assign_vs_urb_setup. */
1522 this->first_non_payload_grf
= payload
.num_regs
+ prog_data
->curb_read_length
;
1526 fs_visitor::calculate_urb_setup()
1528 assert(stage
== MESA_SHADER_FRAGMENT
);
1529 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1530 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
1532 memset(prog_data
->urb_setup
, -1,
1533 sizeof(prog_data
->urb_setup
[0]) * VARYING_SLOT_MAX
);
1536 /* Figure out where each of the incoming setup attributes lands. */
1537 if (devinfo
->gen
>= 6) {
1538 if (_mesa_bitcount_64(nir
->info
.inputs_read
&
1539 BRW_FS_VARYING_INPUT_MASK
) <= 16) {
1540 /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
1541 * first 16 varying inputs, so we can put them wherever we want.
1542 * Just put them in order.
1544 * This is useful because it means that (a) inputs not used by the
1545 * fragment shader won't take up valuable register space, and (b) we
1546 * won't have to recompile the fragment shader if it gets paired with
1547 * a different vertex (or geometry) shader.
1549 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1550 if (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1551 BITFIELD64_BIT(i
)) {
1552 prog_data
->urb_setup
[i
] = urb_next
++;
1556 bool include_vue_header
=
1557 nir
->info
.inputs_read
& (VARYING_BIT_LAYER
| VARYING_BIT_VIEWPORT
);
1559 /* We have enough input varyings that the SF/SBE pipeline stage can't
1560 * arbitrarily rearrange them to suit our whim; we have to put them
1561 * in an order that matches the output of the previous pipeline stage
1562 * (geometry or vertex shader).
1564 struct brw_vue_map prev_stage_vue_map
;
1565 brw_compute_vue_map(devinfo
, &prev_stage_vue_map
,
1566 key
->input_slots_valid
,
1567 nir
->info
.separate_shader
);
1569 include_vue_header
? 0 : 2 * BRW_SF_URB_ENTRY_READ_OFFSET
;
1571 assert(prev_stage_vue_map
.num_slots
<= first_slot
+ 32);
1572 for (int slot
= first_slot
; slot
< prev_stage_vue_map
.num_slots
;
1574 int varying
= prev_stage_vue_map
.slot_to_varying
[slot
];
1575 if (varying
!= BRW_VARYING_SLOT_PAD
&&
1576 (nir
->info
.inputs_read
& BRW_FS_VARYING_INPUT_MASK
&
1577 BITFIELD64_BIT(varying
))) {
1578 prog_data
->urb_setup
[varying
] = slot
- first_slot
;
1581 urb_next
= prev_stage_vue_map
.num_slots
- first_slot
;
1584 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
1585 for (unsigned int i
= 0; i
< VARYING_SLOT_MAX
; i
++) {
1586 /* Point size is packed into the header, not as a general attribute */
1587 if (i
== VARYING_SLOT_PSIZ
)
1590 if (key
->input_slots_valid
& BITFIELD64_BIT(i
)) {
1591 /* The back color slot is skipped when the front color is
1592 * also written to. In addition, some slots can be
1593 * written in the vertex shader and not read in the
1594 * fragment shader. So the register number must always be
1595 * incremented, mapped or not.
1597 if (_mesa_varying_slot_in_fs((gl_varying_slot
) i
))
1598 prog_data
->urb_setup
[i
] = urb_next
;
1604 * It's a FS only attribute, and we did interpolation for this attribute
1605 * in SF thread. So, count it here, too.
1607 * See compile_sf_prog() for more info.
1609 if (nir
->info
.inputs_read
& BITFIELD64_BIT(VARYING_SLOT_PNTC
))
1610 prog_data
->urb_setup
[VARYING_SLOT_PNTC
] = urb_next
++;
1613 prog_data
->num_varying_inputs
= urb_next
;
1617 fs_visitor::assign_urb_setup()
1619 assert(stage
== MESA_SHADER_FRAGMENT
);
1620 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
1622 int urb_start
= payload
.num_regs
+ prog_data
->base
.curb_read_length
;
1624 /* Offset all the urb_setup[] index by the actual position of the
1625 * setup regs, now that the location of the constants has been chosen.
1627 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1628 if (inst
->opcode
== FS_OPCODE_LINTERP
) {
1629 assert(inst
->src
[1].file
== FIXED_GRF
);
1630 inst
->src
[1].nr
+= urb_start
;
1633 if (inst
->opcode
== FS_OPCODE_CINTERP
) {
1634 assert(inst
->src
[0].file
== FIXED_GRF
);
1635 inst
->src
[0].nr
+= urb_start
;
1639 /* Each attribute is 4 setup channels, each of which is half a reg. */
1640 this->first_non_payload_grf
+= prog_data
->num_varying_inputs
* 2;
1644 fs_visitor::convert_attr_sources_to_hw_regs(fs_inst
*inst
)
1646 for (int i
= 0; i
< inst
->sources
; i
++) {
1647 if (inst
->src
[i
].file
== ATTR
) {
1648 int grf
= payload
.num_regs
+
1649 prog_data
->curb_read_length
+
1651 inst
->src
[i
].reg_offset
;
1653 unsigned width
= inst
->src
[i
].stride
== 0 ? 1 : inst
->exec_size
;
1654 struct brw_reg reg
=
1655 stride(byte_offset(retype(brw_vec8_grf(grf
, 0), inst
->src
[i
].type
),
1656 inst
->src
[i
].subreg_offset
),
1657 inst
->exec_size
* inst
->src
[i
].stride
,
1658 width
, inst
->src
[i
].stride
);
1659 reg
.abs
= inst
->src
[i
].abs
;
1660 reg
.negate
= inst
->src
[i
].negate
;
1668 fs_visitor::assign_vs_urb_setup()
1670 brw_vs_prog_data
*vs_prog_data
= (brw_vs_prog_data
*) prog_data
;
1672 assert(stage
== MESA_SHADER_VERTEX
);
1673 int count
= _mesa_bitcount_64(vs_prog_data
->inputs_read
);
1674 if (vs_prog_data
->uses_vertexid
|| vs_prog_data
->uses_instanceid
)
1677 /* Each attribute is 4 regs. */
1678 this->first_non_payload_grf
+= 4 * vs_prog_data
->nr_attributes
;
1680 assert(vs_prog_data
->base
.urb_read_length
<= 15);
1682 /* Rewrite all ATTR file references to the hw grf that they land in. */
1683 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1684 convert_attr_sources_to_hw_regs(inst
);
1689 fs_visitor::assign_gs_urb_setup()
1691 assert(stage
== MESA_SHADER_GEOMETRY
);
1693 brw_vue_prog_data
*vue_prog_data
= (brw_vue_prog_data
*) prog_data
;
1695 first_non_payload_grf
+=
1696 8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
;
1698 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1699 /* Rewrite all ATTR file references to GRFs. */
1700 convert_attr_sources_to_hw_regs(inst
);
1706 * Split large virtual GRFs into separate components if we can.
1708 * This is mostly duplicated with what brw_fs_vector_splitting does,
1709 * but that's really conservative because it's afraid of doing
1710 * splitting that doesn't result in real progress after the rest of
1711 * the optimization phases, which would cause infinite looping in
1712 * optimization. We can do it once here, safely. This also has the
1713 * opportunity to split interpolated values, or maybe even uniforms,
1714 * which we don't have at the IR level.
1716 * We want to split, because virtual GRFs are what we register
1717 * allocate and spill (due to contiguousness requirements for some
1718 * instructions), and they're what we naturally generate in the
1719 * codegen process, but most virtual GRFs don't actually need to be
1720 * contiguous sets of GRFs. If we split, we'll end up with reduced
1721 * live intervals and better dead code elimination and coalescing.
1724 fs_visitor::split_virtual_grfs()
1726 int num_vars
= this->alloc
.count
;
1728 /* Count the total number of registers */
1730 int vgrf_to_reg
[num_vars
];
1731 for (int i
= 0; i
< num_vars
; i
++) {
1732 vgrf_to_reg
[i
] = reg_count
;
1733 reg_count
+= alloc
.sizes
[i
];
1736 /* An array of "split points". For each register slot, this indicates
1737 * if this slot can be separated from the previous slot. Every time an
1738 * instruction uses multiple elements of a register (as a source or
1739 * destination), we mark the used slots as inseparable. Then we go
1740 * through and split the registers into the smallest pieces we can.
1742 bool split_points
[reg_count
];
1743 memset(split_points
, 0, sizeof(split_points
));
1745 /* Mark all used registers as fully splittable */
1746 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1747 if (inst
->dst
.file
== VGRF
) {
1748 int reg
= vgrf_to_reg
[inst
->dst
.nr
];
1749 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->dst
.nr
]; j
++)
1750 split_points
[reg
+ j
] = true;
1753 for (int i
= 0; i
< inst
->sources
; i
++) {
1754 if (inst
->src
[i
].file
== VGRF
) {
1755 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
];
1756 for (unsigned j
= 1; j
< this->alloc
.sizes
[inst
->src
[i
].nr
]; j
++)
1757 split_points
[reg
+ j
] = true;
1762 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1763 if (inst
->dst
.file
== VGRF
) {
1764 int reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1765 for (int j
= 1; j
< inst
->regs_written
; j
++)
1766 split_points
[reg
+ j
] = false;
1768 for (int i
= 0; i
< inst
->sources
; i
++) {
1769 if (inst
->src
[i
].file
== VGRF
) {
1770 int reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1771 for (int j
= 1; j
< inst
->regs_read(i
); j
++)
1772 split_points
[reg
+ j
] = false;
1777 int new_virtual_grf
[reg_count
];
1778 int new_reg_offset
[reg_count
];
1781 for (int i
= 0; i
< num_vars
; i
++) {
1782 /* The first one should always be 0 as a quick sanity check. */
1783 assert(split_points
[reg
] == false);
1786 new_reg_offset
[reg
] = 0;
1791 for (unsigned j
= 1; j
< alloc
.sizes
[i
]; j
++) {
1792 /* If this is a split point, reset the offset to 0 and allocate a
1793 * new virtual GRF for the previous offset many registers
1795 if (split_points
[reg
]) {
1796 assert(offset
<= MAX_VGRF_SIZE
);
1797 int grf
= alloc
.allocate(offset
);
1798 for (int k
= reg
- offset
; k
< reg
; k
++)
1799 new_virtual_grf
[k
] = grf
;
1802 new_reg_offset
[reg
] = offset
;
1807 /* The last one gets the original register number */
1808 assert(offset
<= MAX_VGRF_SIZE
);
1809 alloc
.sizes
[i
] = offset
;
1810 for (int k
= reg
- offset
; k
< reg
; k
++)
1811 new_virtual_grf
[k
] = i
;
1813 assert(reg
== reg_count
);
1815 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1816 if (inst
->dst
.file
== VGRF
) {
1817 reg
= vgrf_to_reg
[inst
->dst
.nr
] + inst
->dst
.reg_offset
;
1818 inst
->dst
.nr
= new_virtual_grf
[reg
];
1819 inst
->dst
.reg_offset
= new_reg_offset
[reg
];
1820 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1822 for (int i
= 0; i
< inst
->sources
; i
++) {
1823 if (inst
->src
[i
].file
== VGRF
) {
1824 reg
= vgrf_to_reg
[inst
->src
[i
].nr
] + inst
->src
[i
].reg_offset
;
1825 inst
->src
[i
].nr
= new_virtual_grf
[reg
];
1826 inst
->src
[i
].reg_offset
= new_reg_offset
[reg
];
1827 assert((unsigned)new_reg_offset
[reg
] < alloc
.sizes
[new_virtual_grf
[reg
]]);
1831 invalidate_live_intervals();
1835 * Remove unused virtual GRFs and compact the virtual_grf_* arrays.
1837 * During code generation, we create tons of temporary variables, many of
1838 * which get immediately killed and are never used again. Yet, in later
1839 * optimization and analysis passes, such as compute_live_intervals, we need
1840 * to loop over all the virtual GRFs. Compacting them can save a lot of
1844 fs_visitor::compact_virtual_grfs()
1846 bool progress
= false;
1847 int remap_table
[this->alloc
.count
];
1848 memset(remap_table
, -1, sizeof(remap_table
));
1850 /* Mark which virtual GRFs are used. */
1851 foreach_block_and_inst(block
, const fs_inst
, inst
, cfg
) {
1852 if (inst
->dst
.file
== VGRF
)
1853 remap_table
[inst
->dst
.nr
] = 0;
1855 for (int i
= 0; i
< inst
->sources
; i
++) {
1856 if (inst
->src
[i
].file
== VGRF
)
1857 remap_table
[inst
->src
[i
].nr
] = 0;
1861 /* Compact the GRF arrays. */
1863 for (unsigned i
= 0; i
< this->alloc
.count
; i
++) {
1864 if (remap_table
[i
] == -1) {
1865 /* We just found an unused register. This means that we are
1866 * actually going to compact something.
1870 remap_table
[i
] = new_index
;
1871 alloc
.sizes
[new_index
] = alloc
.sizes
[i
];
1872 invalidate_live_intervals();
1877 this->alloc
.count
= new_index
;
1879 /* Patch all the instructions to use the newly renumbered registers */
1880 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
1881 if (inst
->dst
.file
== VGRF
)
1882 inst
->dst
.nr
= remap_table
[inst
->dst
.nr
];
1884 for (int i
= 0; i
< inst
->sources
; i
++) {
1885 if (inst
->src
[i
].file
== VGRF
)
1886 inst
->src
[i
].nr
= remap_table
[inst
->src
[i
].nr
];
1890 /* Patch all the references to delta_xy, since they're used in register
1891 * allocation. If they're unused, switch them to BAD_FILE so we don't
1892 * think some random VGRF is delta_xy.
1894 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
1895 if (delta_xy
[i
].file
== VGRF
) {
1896 if (remap_table
[delta_xy
[i
].nr
] != -1) {
1897 delta_xy
[i
].nr
= remap_table
[delta_xy
[i
].nr
];
1899 delta_xy
[i
].file
= BAD_FILE
;
1908 * Assign UNIFORM file registers to either push constants or pull constants.
1910 * We allow a fragment shader to have more than the specified minimum
1911 * maximum number of fragment shader uniform components (64). If
1912 * there are too many of these, they'd fill up all of register space.
1913 * So, this will push some of them out to the pull constant buffer and
1914 * update the program to load them. We also use pull constants for all
1915 * indirect constant loads because we don't support indirect accesses in
1919 fs_visitor::assign_constant_locations()
1921 /* Only the first compile (SIMD8 mode) gets to decide on locations. */
1922 if (dispatch_width
!= 8)
1925 unsigned int num_pull_constants
= 0;
1927 pull_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1928 memset(pull_constant_loc
, -1, sizeof(pull_constant_loc
[0]) * uniforms
);
1930 bool is_live
[uniforms
];
1931 memset(is_live
, 0, sizeof(is_live
));
1933 /* First, we walk through the instructions and do two things:
1935 * 1) Figure out which uniforms are live.
1937 * 2) Find all indirect access of uniform arrays and flag them as needing
1938 * to go into the pull constant buffer.
1940 * Note that we don't move constant-indexed accesses to arrays. No
1941 * testing has been done of the performance impact of this choice.
1943 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
1944 for (int i
= 0 ; i
< inst
->sources
; i
++) {
1945 if (inst
->src
[i
].file
!= UNIFORM
)
1948 if (inst
->src
[i
].reladdr
) {
1949 int uniform
= inst
->src
[i
].nr
;
1951 /* If this array isn't already present in the pull constant buffer,
1954 if (pull_constant_loc
[uniform
] == -1) {
1955 assert(param_size
[uniform
]);
1956 for (int j
= 0; j
< param_size
[uniform
]; j
++)
1957 pull_constant_loc
[uniform
+ j
] = num_pull_constants
++;
1960 /* Mark the the one accessed uniform as live */
1961 int constant_nr
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
1962 if (constant_nr
>= 0 && constant_nr
< (int) uniforms
)
1963 is_live
[constant_nr
] = true;
1968 /* Only allow 16 registers (128 uniform components) as push constants.
1970 * Just demote the end of the list. We could probably do better
1971 * here, demoting things that are rarely used in the program first.
1973 * If changing this value, note the limitation about total_regs in
1976 unsigned int max_push_components
= 16 * 8;
1977 unsigned int num_push_constants
= 0;
1979 push_constant_loc
= ralloc_array(mem_ctx
, int, uniforms
);
1981 for (unsigned int i
= 0; i
< uniforms
; i
++) {
1982 if (!is_live
[i
] || pull_constant_loc
[i
] != -1) {
1983 /* This UNIFORM register is either dead, or has already been demoted
1984 * to a pull const. Mark it as no longer living in the param[] array.
1986 push_constant_loc
[i
] = -1;
1990 if (num_push_constants
< max_push_components
) {
1991 /* Retain as a push constant. Record the location in the params[]
1994 push_constant_loc
[i
] = num_push_constants
++;
1996 /* Demote to a pull constant. */
1997 push_constant_loc
[i
] = -1;
1998 pull_constant_loc
[i
] = num_pull_constants
++;
2002 stage_prog_data
->nr_params
= num_push_constants
;
2003 stage_prog_data
->nr_pull_params
= num_pull_constants
;
2005 /* Up until now, the param[] array has been indexed by reg + reg_offset
2006 * of UNIFORM registers. Move pull constants into pull_param[] and
2007 * condense param[] to only contain the uniforms we chose to push.
2009 * NOTE: Because we are condensing the params[] array, we know that
2010 * push_constant_loc[i] <= i and we can do it in one smooth loop without
2011 * having to make a copy.
2013 for (unsigned int i
= 0; i
< uniforms
; i
++) {
2014 const gl_constant_value
*value
= stage_prog_data
->param
[i
];
2016 if (pull_constant_loc
[i
] != -1) {
2017 stage_prog_data
->pull_param
[pull_constant_loc
[i
]] = value
;
2018 } else if (push_constant_loc
[i
] != -1) {
2019 stage_prog_data
->param
[push_constant_loc
[i
]] = value
;
2025 * Replace UNIFORM register file access with either UNIFORM_PULL_CONSTANT_LOAD
2026 * or VARYING_PULL_CONSTANT_LOAD instructions which load values into VGRFs.
2029 fs_visitor::demote_pull_constants()
2031 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
2032 for (int i
= 0; i
< inst
->sources
; i
++) {
2033 if (inst
->src
[i
].file
!= UNIFORM
)
2037 unsigned location
= inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
;
2038 if (location
>= uniforms
) /* Out of bounds access */
2041 pull_index
= pull_constant_loc
[location
];
2043 if (pull_index
== -1)
2046 /* Set up the annotation tracking for new generated instructions. */
2047 const fs_builder
ibld(this, block
, inst
);
2048 const unsigned index
= stage_prog_data
->binding_table
.pull_constants_start
;
2049 fs_reg dst
= vgrf(glsl_type::float_type
);
2051 assert(inst
->src
[i
].stride
== 0);
2053 /* Generate a pull load into dst. */
2054 if (inst
->src
[i
].reladdr
) {
2055 fs_reg indirect
= ibld
.vgrf(BRW_REGISTER_TYPE_D
);
2056 ibld
.MUL(indirect
, *inst
->src
[i
].reladdr
, brw_imm_d(4));
2057 VARYING_PULL_CONSTANT_LOAD(ibld
, dst
,
2061 inst
->src
[i
].reladdr
= NULL
;
2062 inst
->src
[i
].stride
= 1;
2064 const fs_builder ubld
= ibld
.exec_all().group(8, 0);
2065 struct brw_reg offset
= brw_imm_ud((unsigned)(pull_index
* 4) & ~15);
2066 ubld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
2067 dst
, brw_imm_ud(index
), offset
);
2068 inst
->src
[i
].set_smear(pull_index
& 3);
2070 brw_mark_surface_used(prog_data
, index
);
2072 /* Rewrite the instruction to use the temporary VGRF. */
2073 inst
->src
[i
].file
= VGRF
;
2074 inst
->src
[i
].nr
= dst
.nr
;
2075 inst
->src
[i
].reg_offset
= 0;
2078 invalidate_live_intervals();
2082 fs_visitor::opt_algebraic()
2084 bool progress
= false;
2086 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2087 switch (inst
->opcode
) {
2088 case BRW_OPCODE_MOV
:
2089 if (inst
->src
[0].file
!= IMM
)
2092 if (inst
->saturate
) {
2093 if (inst
->dst
.type
!= inst
->src
[0].type
)
2094 assert(!"unimplemented: saturate mixed types");
2096 if (brw_saturate_immediate(inst
->dst
.type
,
2097 &inst
->src
[0].as_brw_reg())) {
2098 inst
->saturate
= false;
2104 case BRW_OPCODE_MUL
:
2105 if (inst
->src
[1].file
!= IMM
)
2109 if (inst
->src
[1].is_one()) {
2110 inst
->opcode
= BRW_OPCODE_MOV
;
2111 inst
->src
[1] = reg_undef
;
2117 if (inst
->src
[1].is_negative_one()) {
2118 inst
->opcode
= BRW_OPCODE_MOV
;
2119 inst
->src
[0].negate
= !inst
->src
[0].negate
;
2120 inst
->src
[1] = reg_undef
;
2126 if (inst
->src
[1].is_zero()) {
2127 inst
->opcode
= BRW_OPCODE_MOV
;
2128 inst
->src
[0] = inst
->src
[1];
2129 inst
->src
[1] = reg_undef
;
2134 if (inst
->src
[0].file
== IMM
) {
2135 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2136 inst
->opcode
= BRW_OPCODE_MOV
;
2137 inst
->src
[0].f
*= inst
->src
[1].f
;
2138 inst
->src
[1] = reg_undef
;
2143 case BRW_OPCODE_ADD
:
2144 if (inst
->src
[1].file
!= IMM
)
2148 if (inst
->src
[1].is_zero()) {
2149 inst
->opcode
= BRW_OPCODE_MOV
;
2150 inst
->src
[1] = reg_undef
;
2155 if (inst
->src
[0].file
== IMM
) {
2156 assert(inst
->src
[0].type
== BRW_REGISTER_TYPE_F
);
2157 inst
->opcode
= BRW_OPCODE_MOV
;
2158 inst
->src
[0].f
+= inst
->src
[1].f
;
2159 inst
->src
[1] = reg_undef
;
2165 if (inst
->src
[0].equals(inst
->src
[1])) {
2166 inst
->opcode
= BRW_OPCODE_MOV
;
2167 inst
->src
[1] = reg_undef
;
2172 case BRW_OPCODE_LRP
:
2173 if (inst
->src
[1].equals(inst
->src
[2])) {
2174 inst
->opcode
= BRW_OPCODE_MOV
;
2175 inst
->src
[0] = inst
->src
[1];
2176 inst
->src
[1] = reg_undef
;
2177 inst
->src
[2] = reg_undef
;
2182 case BRW_OPCODE_CMP
:
2183 if (inst
->conditional_mod
== BRW_CONDITIONAL_GE
&&
2185 inst
->src
[0].negate
&&
2186 inst
->src
[1].is_zero()) {
2187 inst
->src
[0].abs
= false;
2188 inst
->src
[0].negate
= false;
2189 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
2194 case BRW_OPCODE_SEL
:
2195 if (inst
->src
[0].equals(inst
->src
[1])) {
2196 inst
->opcode
= BRW_OPCODE_MOV
;
2197 inst
->src
[1] = reg_undef
;
2198 inst
->predicate
= BRW_PREDICATE_NONE
;
2199 inst
->predicate_inverse
= false;
2201 } else if (inst
->saturate
&& inst
->src
[1].file
== IMM
) {
2202 switch (inst
->conditional_mod
) {
2203 case BRW_CONDITIONAL_LE
:
2204 case BRW_CONDITIONAL_L
:
2205 switch (inst
->src
[1].type
) {
2206 case BRW_REGISTER_TYPE_F
:
2207 if (inst
->src
[1].f
>= 1.0f
) {
2208 inst
->opcode
= BRW_OPCODE_MOV
;
2209 inst
->src
[1] = reg_undef
;
2210 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2218 case BRW_CONDITIONAL_GE
:
2219 case BRW_CONDITIONAL_G
:
2220 switch (inst
->src
[1].type
) {
2221 case BRW_REGISTER_TYPE_F
:
2222 if (inst
->src
[1].f
<= 0.0f
) {
2223 inst
->opcode
= BRW_OPCODE_MOV
;
2224 inst
->src
[1] = reg_undef
;
2225 inst
->conditional_mod
= BRW_CONDITIONAL_NONE
;
2237 case BRW_OPCODE_MAD
:
2238 if (inst
->src
[1].is_zero() || inst
->src
[2].is_zero()) {
2239 inst
->opcode
= BRW_OPCODE_MOV
;
2240 inst
->src
[1] = reg_undef
;
2241 inst
->src
[2] = reg_undef
;
2243 } else if (inst
->src
[0].is_zero()) {
2244 inst
->opcode
= BRW_OPCODE_MUL
;
2245 inst
->src
[0] = inst
->src
[2];
2246 inst
->src
[2] = reg_undef
;
2248 } else if (inst
->src
[1].is_one()) {
2249 inst
->opcode
= BRW_OPCODE_ADD
;
2250 inst
->src
[1] = inst
->src
[2];
2251 inst
->src
[2] = reg_undef
;
2253 } else if (inst
->src
[2].is_one()) {
2254 inst
->opcode
= BRW_OPCODE_ADD
;
2255 inst
->src
[2] = reg_undef
;
2257 } else if (inst
->src
[1].file
== IMM
&& inst
->src
[2].file
== IMM
) {
2258 inst
->opcode
= BRW_OPCODE_ADD
;
2259 inst
->src
[1].f
*= inst
->src
[2].f
;
2260 inst
->src
[2] = reg_undef
;
2264 case SHADER_OPCODE_RCP
: {
2265 fs_inst
*prev
= (fs_inst
*)inst
->prev
;
2266 if (prev
->opcode
== SHADER_OPCODE_SQRT
) {
2267 if (inst
->src
[0].equals(prev
->dst
)) {
2268 inst
->opcode
= SHADER_OPCODE_RSQ
;
2269 inst
->src
[0] = prev
->src
[0];
2275 case SHADER_OPCODE_BROADCAST
:
2276 if (is_uniform(inst
->src
[0])) {
2277 inst
->opcode
= BRW_OPCODE_MOV
;
2279 inst
->force_writemask_all
= true;
2281 } else if (inst
->src
[1].file
== IMM
) {
2282 inst
->opcode
= BRW_OPCODE_MOV
;
2283 inst
->src
[0] = component(inst
->src
[0],
2286 inst
->force_writemask_all
= true;
2295 /* Swap if src[0] is immediate. */
2296 if (progress
&& inst
->is_commutative()) {
2297 if (inst
->src
[0].file
== IMM
) {
2298 fs_reg tmp
= inst
->src
[1];
2299 inst
->src
[1] = inst
->src
[0];
2308 * Optimize sample messages that have constant zero values for the trailing
2309 * texture coordinates. We can just reduce the message length for these
2310 * instructions instead of reserving a register for it. Trailing parameters
2311 * that aren't sent default to zero anyway. This will cause the dead code
2312 * eliminator to remove the MOV instruction that would otherwise be emitted to
2313 * set up the zero value.
2316 fs_visitor::opt_zero_samples()
2318 /* Gen4 infers the texturing opcode based on the message length so we can't
2321 if (devinfo
->gen
< 5)
2324 bool progress
= false;
2326 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2327 if (!inst
->is_tex())
2330 fs_inst
*load_payload
= (fs_inst
*) inst
->prev
;
2332 if (load_payload
->is_head_sentinel() ||
2333 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2336 /* We don't want to remove the message header or the first parameter.
2337 * Removing the first parameter is not allowed, see the Haswell PRM
2338 * volume 7, page 149:
2340 * "Parameter 0 is required except for the sampleinfo message, which
2341 * has no parameter 0"
2343 while (inst
->mlen
> inst
->header_size
+ inst
->exec_size
/ 8 &&
2344 load_payload
->src
[(inst
->mlen
- inst
->header_size
) /
2345 (inst
->exec_size
/ 8) +
2346 inst
->header_size
- 1].is_zero()) {
2347 inst
->mlen
-= inst
->exec_size
/ 8;
2353 invalidate_live_intervals();
2359 * Optimize sample messages which are followed by the final RT write.
2361 * CHV, and GEN9+ can mark a texturing SEND instruction with EOT to have its
2362 * results sent directly to the framebuffer, bypassing the EU. Recognize the
2363 * final texturing results copied to the framebuffer write payload and modify
2364 * them to write to the framebuffer directly.
2367 fs_visitor::opt_sampler_eot()
2369 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2371 if (stage
!= MESA_SHADER_FRAGMENT
)
2374 if (devinfo
->gen
< 9 && !devinfo
->is_cherryview
)
2377 /* FINISHME: It should be possible to implement this optimization when there
2378 * are multiple drawbuffers.
2380 if (key
->nr_color_regions
!= 1)
2383 /* Look for a texturing instruction immediately before the final FB_WRITE. */
2384 bblock_t
*block
= cfg
->blocks
[cfg
->num_blocks
- 1];
2385 fs_inst
*fb_write
= (fs_inst
*)block
->end();
2386 assert(fb_write
->eot
);
2387 assert(fb_write
->opcode
== FS_OPCODE_FB_WRITE
);
2389 fs_inst
*tex_inst
= (fs_inst
*) fb_write
->prev
;
2391 /* There wasn't one; nothing to do. */
2392 if (unlikely(tex_inst
->is_head_sentinel()) || !tex_inst
->is_tex())
2395 /* 3D Sampler » Messages » Message Format
2397 * “Response Length of zero is allowed on all SIMD8* and SIMD16* sampler
2398 * messages except sample+killpix, resinfo, sampleinfo, LOD, and gather4*”
2400 if (tex_inst
->opcode
== SHADER_OPCODE_TXS
||
2401 tex_inst
->opcode
== SHADER_OPCODE_SAMPLEINFO
||
2402 tex_inst
->opcode
== SHADER_OPCODE_LOD
||
2403 tex_inst
->opcode
== SHADER_OPCODE_TG4
||
2404 tex_inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
2407 /* If there's no header present, we need to munge the LOAD_PAYLOAD as well.
2408 * It's very likely to be the previous instruction.
2410 fs_inst
*load_payload
= (fs_inst
*) tex_inst
->prev
;
2411 if (load_payload
->is_head_sentinel() ||
2412 load_payload
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
2415 assert(!tex_inst
->eot
); /* We can't get here twice */
2416 assert((tex_inst
->offset
& (0xff << 24)) == 0);
2418 const fs_builder
ibld(this, block
, tex_inst
);
2420 tex_inst
->offset
|= fb_write
->target
<< 24;
2421 tex_inst
->eot
= true;
2422 tex_inst
->dst
= ibld
.null_reg_ud();
2423 fb_write
->remove(cfg
->blocks
[cfg
->num_blocks
- 1]);
2425 /* If a header is present, marking the eot is sufficient. Otherwise, we need
2426 * to create a new LOAD_PAYLOAD command with the same sources and a space
2427 * saved for the header. Using a new destination register not only makes sure
2428 * we have enough space, but it will make sure the dead code eliminator kills
2429 * the instruction that this will replace.
2431 if (tex_inst
->header_size
!= 0)
2434 fs_reg send_header
= ibld
.vgrf(BRW_REGISTER_TYPE_F
,
2435 load_payload
->sources
+ 1);
2436 fs_reg
*new_sources
=
2437 ralloc_array(mem_ctx
, fs_reg
, load_payload
->sources
+ 1);
2439 new_sources
[0] = fs_reg();
2440 for (int i
= 0; i
< load_payload
->sources
; i
++)
2441 new_sources
[i
+1] = load_payload
->src
[i
];
2443 /* The LOAD_PAYLOAD helper seems like the obvious choice here. However, it
2444 * requires a lot of information about the sources to appropriately figure
2445 * out the number of registers needed to be used. Given this stage in our
2446 * optimization, we may not have the appropriate GRFs required by
2447 * LOAD_PAYLOAD at this point (copy propagation). Therefore, we need to
2448 * manually emit the instruction.
2450 fs_inst
*new_load_payload
= new(mem_ctx
) fs_inst(SHADER_OPCODE_LOAD_PAYLOAD
,
2451 load_payload
->exec_size
,
2454 load_payload
->sources
+ 1);
2456 new_load_payload
->regs_written
= load_payload
->regs_written
+ 1;
2457 new_load_payload
->header_size
= 1;
2459 tex_inst
->header_size
= 1;
2460 tex_inst
->insert_before(cfg
->blocks
[cfg
->num_blocks
- 1], new_load_payload
);
2461 tex_inst
->src
[0] = send_header
;
2467 fs_visitor::opt_register_renaming()
2469 bool progress
= false;
2472 int remap
[alloc
.count
];
2473 memset(remap
, -1, sizeof(int) * alloc
.count
);
2475 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
2476 if (inst
->opcode
== BRW_OPCODE_IF
|| inst
->opcode
== BRW_OPCODE_DO
) {
2478 } else if (inst
->opcode
== BRW_OPCODE_ENDIF
||
2479 inst
->opcode
== BRW_OPCODE_WHILE
) {
2483 /* Rewrite instruction sources. */
2484 for (int i
= 0; i
< inst
->sources
; i
++) {
2485 if (inst
->src
[i
].file
== VGRF
&&
2486 remap
[inst
->src
[i
].nr
] != -1 &&
2487 remap
[inst
->src
[i
].nr
] != inst
->src
[i
].nr
) {
2488 inst
->src
[i
].nr
= remap
[inst
->src
[i
].nr
];
2493 const int dst
= inst
->dst
.nr
;
2496 inst
->dst
.file
== VGRF
&&
2497 alloc
.sizes
[inst
->dst
.nr
] == inst
->exec_size
/ 8 &&
2498 !inst
->is_partial_write()) {
2499 if (remap
[dst
] == -1) {
2502 remap
[dst
] = alloc
.allocate(inst
->exec_size
/ 8);
2503 inst
->dst
.nr
= remap
[dst
];
2506 } else if (inst
->dst
.file
== VGRF
&&
2508 remap
[dst
] != dst
) {
2509 inst
->dst
.nr
= remap
[dst
];
2515 invalidate_live_intervals();
2517 for (unsigned i
= 0; i
< ARRAY_SIZE(delta_xy
); i
++) {
2518 if (delta_xy
[i
].file
== VGRF
&& remap
[delta_xy
[i
].nr
] != -1) {
2519 delta_xy
[i
].nr
= remap
[delta_xy
[i
].nr
];
2528 * Remove redundant or useless discard jumps.
2530 * For example, we can eliminate jumps in the following sequence:
2532 * discard-jump (redundant with the next jump)
2533 * discard-jump (useless; jumps to the next instruction)
2537 fs_visitor::opt_redundant_discard_jumps()
2539 bool progress
= false;
2541 bblock_t
*last_bblock
= cfg
->blocks
[cfg
->num_blocks
- 1];
2543 fs_inst
*placeholder_halt
= NULL
;
2544 foreach_inst_in_block_reverse(fs_inst
, inst
, last_bblock
) {
2545 if (inst
->opcode
== FS_OPCODE_PLACEHOLDER_HALT
) {
2546 placeholder_halt
= inst
;
2551 if (!placeholder_halt
)
2554 /* Delete any HALTs immediately before the placeholder halt. */
2555 for (fs_inst
*prev
= (fs_inst
*) placeholder_halt
->prev
;
2556 !prev
->is_head_sentinel() && prev
->opcode
== FS_OPCODE_DISCARD_JUMP
;
2557 prev
= (fs_inst
*) placeholder_halt
->prev
) {
2558 prev
->remove(last_bblock
);
2563 invalidate_live_intervals();
2569 fs_visitor::compute_to_mrf()
2571 bool progress
= false;
2574 /* No MRFs on Gen >= 7. */
2575 if (devinfo
->gen
>= 7)
2578 calculate_live_intervals();
2580 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2584 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2585 inst
->is_partial_write() ||
2586 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= VGRF
||
2587 inst
->dst
.type
!= inst
->src
[0].type
||
2588 inst
->src
[0].abs
|| inst
->src
[0].negate
||
2589 !inst
->src
[0].is_contiguous() ||
2590 inst
->src
[0].subreg_offset
)
2593 /* Work out which hardware MRF registers are written by this
2596 int mrf_low
= inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2598 if (inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2599 mrf_high
= mrf_low
+ 4;
2600 } else if (inst
->exec_size
== 16) {
2601 mrf_high
= mrf_low
+ 1;
2606 /* Can't compute-to-MRF this GRF if someone else was going to
2609 if (this->virtual_grf_end
[inst
->src
[0].nr
] > ip
)
2612 /* Found a move of a GRF to a MRF. Let's see if we can go
2613 * rewrite the thing that made this GRF to write into the MRF.
2615 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2616 if (scan_inst
->dst
.file
== VGRF
&&
2617 scan_inst
->dst
.nr
== inst
->src
[0].nr
) {
2618 /* Found the last thing to write our reg we want to turn
2619 * into a compute-to-MRF.
2622 /* If this one instruction didn't populate all the
2623 * channels, bail. We might be able to rewrite everything
2624 * that writes that reg, but it would require smarter
2625 * tracking to delay the rewriting until complete success.
2627 if (scan_inst
->is_partial_write())
2630 /* Things returning more than one register would need us to
2631 * understand coalescing out more than one MOV at a time.
2633 if (scan_inst
->regs_written
> scan_inst
->exec_size
/ 8)
2636 /* SEND instructions can't have MRF as a destination. */
2637 if (scan_inst
->mlen
)
2640 if (devinfo
->gen
== 6) {
2641 /* gen6 math instructions must have the destination be
2642 * GRF, so no compute-to-MRF for them.
2644 if (scan_inst
->is_math()) {
2649 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2650 /* Found the creator of our MRF's source value. */
2651 scan_inst
->dst
.file
= MRF
;
2652 scan_inst
->dst
.nr
= inst
->dst
.nr
;
2653 scan_inst
->saturate
|= inst
->saturate
;
2654 inst
->remove(block
);
2660 /* We don't handle control flow here. Most computation of
2661 * values that end up in MRFs are shortly before the MRF
2664 if (block
->start() == scan_inst
)
2667 /* You can't read from an MRF, so if someone else reads our
2668 * MRF's source GRF that we wanted to rewrite, that stops us.
2670 bool interfered
= false;
2671 for (int i
= 0; i
< scan_inst
->sources
; i
++) {
2672 if (scan_inst
->src
[i
].file
== VGRF
&&
2673 scan_inst
->src
[i
].nr
== inst
->src
[0].nr
&&
2674 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2681 if (scan_inst
->dst
.file
== MRF
) {
2682 /* If somebody else writes our MRF here, we can't
2683 * compute-to-MRF before that.
2685 int scan_mrf_low
= scan_inst
->dst
.nr
& ~BRW_MRF_COMPR4
;
2688 if (scan_inst
->dst
.nr
& BRW_MRF_COMPR4
) {
2689 scan_mrf_high
= scan_mrf_low
+ 4;
2690 } else if (scan_inst
->exec_size
== 16) {
2691 scan_mrf_high
= scan_mrf_low
+ 1;
2693 scan_mrf_high
= scan_mrf_low
;
2696 if (mrf_low
== scan_mrf_low
||
2697 mrf_low
== scan_mrf_high
||
2698 mrf_high
== scan_mrf_low
||
2699 mrf_high
== scan_mrf_high
) {
2704 if (scan_inst
->mlen
> 0 && scan_inst
->base_mrf
!= -1) {
2705 /* Found a SEND instruction, which means that there are
2706 * live values in MRFs from base_mrf to base_mrf +
2707 * scan_inst->mlen - 1. Don't go pushing our MRF write up
2710 if (mrf_low
>= scan_inst
->base_mrf
&&
2711 mrf_low
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2714 if (mrf_high
>= scan_inst
->base_mrf
&&
2715 mrf_high
< scan_inst
->base_mrf
+ scan_inst
->mlen
) {
2723 invalidate_live_intervals();
2729 * Eliminate FIND_LIVE_CHANNEL instructions occurring outside any control
2730 * flow. We could probably do better here with some form of divergence
2734 fs_visitor::eliminate_find_live_channel()
2736 bool progress
= false;
2739 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
2740 switch (inst
->opcode
) {
2746 case BRW_OPCODE_ENDIF
:
2747 case BRW_OPCODE_WHILE
:
2751 case FS_OPCODE_DISCARD_JUMP
:
2752 /* This can potentially make control flow non-uniform until the end
2757 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2759 inst
->opcode
= BRW_OPCODE_MOV
;
2760 inst
->src
[0] = brw_imm_ud(0u);
2762 inst
->force_writemask_all
= true;
2776 * Once we've generated code, try to convert normal FS_OPCODE_FB_WRITE
2777 * instructions to FS_OPCODE_REP_FB_WRITE.
2780 fs_visitor::emit_repclear_shader()
2782 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
2784 int color_mrf
= base_mrf
+ 2;
2786 fs_inst
*mov
= bld
.exec_all().group(4, 0)
2787 .MOV(brw_message_reg(color_mrf
),
2788 fs_reg(UNIFORM
, 0, BRW_REGISTER_TYPE_F
));
2791 if (key
->nr_color_regions
== 1) {
2792 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2793 write
->saturate
= key
->clamp_fragment_color
;
2794 write
->base_mrf
= color_mrf
;
2796 write
->header_size
= 0;
2799 assume(key
->nr_color_regions
> 0);
2800 for (int i
= 0; i
< key
->nr_color_regions
; ++i
) {
2801 write
= bld
.emit(FS_OPCODE_REP_FB_WRITE
);
2802 write
->saturate
= key
->clamp_fragment_color
;
2803 write
->base_mrf
= base_mrf
;
2805 write
->header_size
= 2;
2813 assign_constant_locations();
2814 assign_curb_setup();
2816 /* Now that we have the uniform assigned, go ahead and force it to a vec4. */
2817 assert(mov
->src
[0].file
== FIXED_GRF
);
2818 mov
->src
[0] = brw_vec4_grf(mov
->src
[0].nr
, 0);
2822 * Walks through basic blocks, looking for repeated MRF writes and
2823 * removing the later ones.
2826 fs_visitor::remove_duplicate_mrf_writes()
2828 fs_inst
*last_mrf_move
[BRW_MAX_MRF(devinfo
->gen
)];
2829 bool progress
= false;
2831 /* Need to update the MRF tracking for compressed instructions. */
2832 if (dispatch_width
== 16)
2835 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2837 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
2838 if (inst
->is_control_flow()) {
2839 memset(last_mrf_move
, 0, sizeof(last_mrf_move
));
2842 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2843 inst
->dst
.file
== MRF
) {
2844 fs_inst
*prev_inst
= last_mrf_move
[inst
->dst
.nr
];
2845 if (prev_inst
&& inst
->equals(prev_inst
)) {
2846 inst
->remove(block
);
2852 /* Clear out the last-write records for MRFs that were overwritten. */
2853 if (inst
->dst
.file
== MRF
) {
2854 last_mrf_move
[inst
->dst
.nr
] = NULL
;
2857 if (inst
->mlen
> 0 && inst
->base_mrf
!= -1) {
2858 /* Found a SEND instruction, which will include two or fewer
2859 * implied MRF writes. We could do better here.
2861 for (int i
= 0; i
< implied_mrf_writes(inst
); i
++) {
2862 last_mrf_move
[inst
->base_mrf
+ i
] = NULL
;
2866 /* Clear out any MRF move records whose sources got overwritten. */
2867 if (inst
->dst
.file
== VGRF
) {
2868 for (unsigned int i
= 0; i
< ARRAY_SIZE(last_mrf_move
); i
++) {
2869 if (last_mrf_move
[i
] &&
2870 last_mrf_move
[i
]->src
[0].nr
== inst
->dst
.nr
) {
2871 last_mrf_move
[i
] = NULL
;
2876 if (inst
->opcode
== BRW_OPCODE_MOV
&&
2877 inst
->dst
.file
== MRF
&&
2878 inst
->src
[0].file
== VGRF
&&
2879 !inst
->is_partial_write()) {
2880 last_mrf_move
[inst
->dst
.nr
] = inst
;
2885 invalidate_live_intervals();
2891 clear_deps_for_inst_src(fs_inst
*inst
, bool *deps
, int first_grf
, int grf_len
)
2893 /* Clear the flag for registers that actually got read (as expected). */
2894 for (int i
= 0; i
< inst
->sources
; i
++) {
2896 if (inst
->src
[i
].file
== VGRF
|| inst
->src
[i
].file
== FIXED_GRF
) {
2897 grf
= inst
->src
[i
].nr
;
2902 if (grf
>= first_grf
&&
2903 grf
< first_grf
+ grf_len
) {
2904 deps
[grf
- first_grf
] = false;
2905 if (inst
->exec_size
== 16)
2906 deps
[grf
- first_grf
+ 1] = false;
2912 * Implements this workaround for the original 965:
2914 * "[DevBW, DevCL] Implementation Restrictions: As the hardware does not
2915 * check for post destination dependencies on this instruction, software
2916 * must ensure that there is no destination hazard for the case of ‘write
2917 * followed by a posted write’ shown in the following example.
2920 * 2. send r3.xy <rest of send instruction>
2923 * Due to no post-destination dependency check on the ‘send’, the above
2924 * code sequence could have two instructions (1 and 2) in flight at the
2925 * same time that both consider ‘r3’ as the target of their final writes.
2928 fs_visitor::insert_gen4_pre_send_dependency_workarounds(bblock_t
*block
,
2931 int write_len
= inst
->regs_written
;
2932 int first_write_grf
= inst
->dst
.nr
;
2933 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
2934 assert(write_len
< (int)sizeof(needs_dep
) - 1);
2936 memset(needs_dep
, false, sizeof(needs_dep
));
2937 memset(needs_dep
, true, write_len
);
2939 clear_deps_for_inst_src(inst
, needs_dep
, first_write_grf
, write_len
);
2941 /* Walk backwards looking for writes to registers we're writing which
2942 * aren't read since being written. If we hit the start of the program,
2943 * we assume that there are no outstanding dependencies on entry to the
2946 foreach_inst_in_block_reverse_starting_from(fs_inst
, scan_inst
, inst
) {
2947 /* If we hit control flow, assume that there *are* outstanding
2948 * dependencies, and force their cleanup before our instruction.
2950 if (block
->start() == scan_inst
) {
2951 for (int i
= 0; i
< write_len
; i
++) {
2953 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
),
2954 first_write_grf
+ i
);
2959 /* We insert our reads as late as possible on the assumption that any
2960 * instruction but a MOV that might have left us an outstanding
2961 * dependency has more latency than a MOV.
2963 if (scan_inst
->dst
.file
== VGRF
) {
2964 for (int i
= 0; i
< scan_inst
->regs_written
; i
++) {
2965 int reg
= scan_inst
->dst
.nr
+ i
;
2967 if (reg
>= first_write_grf
&&
2968 reg
< first_write_grf
+ write_len
&&
2969 needs_dep
[reg
- first_write_grf
]) {
2970 DEP_RESOLVE_MOV(fs_builder(this, block
, inst
), reg
);
2971 needs_dep
[reg
- first_write_grf
] = false;
2972 if (scan_inst
->exec_size
== 16)
2973 needs_dep
[reg
- first_write_grf
+ 1] = false;
2978 /* Clear the flag for registers that actually got read (as expected). */
2979 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
2981 /* Continue the loop only if we haven't resolved all the dependencies */
2983 for (i
= 0; i
< write_len
; i
++) {
2993 * Implements this workaround for the original 965:
2995 * "[DevBW, DevCL] Errata: A destination register from a send can not be
2996 * used as a destination register until after it has been sourced by an
2997 * instruction with a different destination register.
3000 fs_visitor::insert_gen4_post_send_dependency_workarounds(bblock_t
*block
, fs_inst
*inst
)
3002 int write_len
= inst
->regs_written
;
3003 int first_write_grf
= inst
->dst
.nr
;
3004 bool needs_dep
[BRW_MAX_MRF(devinfo
->gen
)];
3005 assert(write_len
< (int)sizeof(needs_dep
) - 1);
3007 memset(needs_dep
, false, sizeof(needs_dep
));
3008 memset(needs_dep
, true, write_len
);
3009 /* Walk forwards looking for writes to registers we're writing which aren't
3010 * read before being written.
3012 foreach_inst_in_block_starting_from(fs_inst
, scan_inst
, inst
) {
3013 /* If we hit control flow, force resolve all remaining dependencies. */
3014 if (block
->end() == scan_inst
) {
3015 for (int i
= 0; i
< write_len
; i
++) {
3017 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3018 first_write_grf
+ i
);
3023 /* Clear the flag for registers that actually got read (as expected). */
3024 clear_deps_for_inst_src(scan_inst
, needs_dep
, first_write_grf
, write_len
);
3026 /* We insert our reads as late as possible since they're reading the
3027 * result of a SEND, which has massive latency.
3029 if (scan_inst
->dst
.file
== VGRF
&&
3030 scan_inst
->dst
.nr
>= first_write_grf
&&
3031 scan_inst
->dst
.nr
< first_write_grf
+ write_len
&&
3032 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
]) {
3033 DEP_RESOLVE_MOV(fs_builder(this, block
, scan_inst
),
3035 needs_dep
[scan_inst
->dst
.nr
- first_write_grf
] = false;
3038 /* Continue the loop only if we haven't resolved all the dependencies */
3040 for (i
= 0; i
< write_len
; i
++) {
3050 fs_visitor::insert_gen4_send_dependency_workarounds()
3052 if (devinfo
->gen
!= 4 || devinfo
->is_g4x
)
3055 bool progress
= false;
3057 /* Note that we're done with register allocation, so GRF fs_regs always
3058 * have a .reg_offset of 0.
3061 foreach_block_and_inst(block
, fs_inst
, inst
, cfg
) {
3062 if (inst
->mlen
!= 0 && inst
->dst
.file
== VGRF
) {
3063 insert_gen4_pre_send_dependency_workarounds(block
, inst
);
3064 insert_gen4_post_send_dependency_workarounds(block
, inst
);
3070 invalidate_live_intervals();
3074 * Turns the generic expression-style uniform pull constant load instruction
3075 * into a hardware-specific series of instructions for loading a pull
3078 * The expression style allows the CSE pass before this to optimize out
3079 * repeated loads from the same offset, and gives the pre-register-allocation
3080 * scheduling full flexibility, while the conversion to native instructions
3081 * allows the post-register-allocation scheduler the best information
3084 * Note that execution masking for setting up pull constant loads is special:
3085 * the channels that need to be written are unrelated to the current execution
3086 * mask, since a later instruction will use one of the result channels as a
3087 * source operand for all 8 or 16 of its channels.
3090 fs_visitor::lower_uniform_pull_constant_loads()
3092 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
3093 if (inst
->opcode
!= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
)
3096 if (devinfo
->gen
>= 7) {
3097 /* The offset arg is a vec4-aligned immediate byte offset. */
3098 fs_reg const_offset_reg
= inst
->src
[1];
3099 assert(const_offset_reg
.file
== IMM
&&
3100 const_offset_reg
.type
== BRW_REGISTER_TYPE_UD
);
3101 assert(const_offset_reg
.ud
% 16 == 0);
3103 fs_reg payload
, offset
;
3104 if (devinfo
->gen
>= 9) {
3105 /* We have to use a message header on Skylake to get SIMD4x2
3106 * mode. Reserve space for the register.
3108 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(2));
3109 offset
.reg_offset
++;
3112 offset
= payload
= fs_reg(VGRF
, alloc
.allocate(1));
3116 /* This is actually going to be a MOV, but since only the first dword
3117 * is accessed, we have a special opcode to do just that one. Note
3118 * that this needs to be an operation that will be considered a def
3119 * by live variable analysis, or register allocation will explode.
3121 fs_inst
*setup
= new(mem_ctx
) fs_inst(FS_OPCODE_SET_SIMD4X2_OFFSET
,
3122 8, offset
, const_offset_reg
);
3123 setup
->force_writemask_all
= true;
3125 setup
->ir
= inst
->ir
;
3126 setup
->annotation
= inst
->annotation
;
3127 inst
->insert_before(block
, setup
);
3129 /* Similarly, this will only populate the first 4 channels of the
3130 * result register (since we only use smear values from 0-3), but we
3131 * don't tell the optimizer.
3133 inst
->opcode
= FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
;
3134 inst
->src
[1] = payload
;
3135 inst
->base_mrf
= -1;
3137 invalidate_live_intervals();
3139 /* Before register allocation, we didn't tell the scheduler about the
3140 * MRF we use. We know it's safe to use this MRF because nothing
3141 * else does except for register spill/unspill, which generates and
3142 * uses its MRF within a single IR instruction.
3144 inst
->base_mrf
= FIRST_PULL_LOAD_MRF(devinfo
->gen
) + 1;
3151 fs_visitor::lower_load_payload()
3153 bool progress
= false;
3155 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
3156 if (inst
->opcode
!= SHADER_OPCODE_LOAD_PAYLOAD
)
3159 assert(inst
->dst
.file
== MRF
|| inst
->dst
.file
== VGRF
);
3160 assert(inst
->saturate
== false);
3161 fs_reg dst
= inst
->dst
;
3163 /* Get rid of COMPR4. We'll add it back in if we need it */
3164 if (dst
.file
== MRF
)
3165 dst
.nr
= dst
.nr
& ~BRW_MRF_COMPR4
;
3167 const fs_builder
ibld(this, block
, inst
);
3168 const fs_builder hbld
= ibld
.exec_all().group(8, 0);
3170 for (uint8_t i
= 0; i
< inst
->header_size
; i
++) {
3171 if (inst
->src
[i
].file
!= BAD_FILE
) {
3172 fs_reg mov_dst
= retype(dst
, BRW_REGISTER_TYPE_UD
);
3173 fs_reg mov_src
= retype(inst
->src
[i
], BRW_REGISTER_TYPE_UD
);
3174 hbld
.MOV(mov_dst
, mov_src
);
3176 dst
= offset(dst
, hbld
, 1);
3179 if (inst
->dst
.file
== MRF
&& (inst
->dst
.nr
& BRW_MRF_COMPR4
) &&
3180 inst
->exec_size
> 8) {
3181 /* In this case, the payload portion of the LOAD_PAYLOAD isn't
3182 * a straightforward copy. Instead, the result of the
3183 * LOAD_PAYLOAD is treated as interleaved and the first four
3184 * non-header sources are unpacked as:
3195 * This is used for gen <= 5 fb writes.
3197 assert(inst
->exec_size
== 16);
3198 assert(inst
->header_size
+ 4 <= inst
->sources
);
3199 for (uint8_t i
= inst
->header_size
; i
< inst
->header_size
+ 4; i
++) {
3200 if (inst
->src
[i
].file
!= BAD_FILE
) {
3201 if (devinfo
->has_compr4
) {
3202 fs_reg compr4_dst
= retype(dst
, inst
->src
[i
].type
);
3203 compr4_dst
.nr
|= BRW_MRF_COMPR4
;
3204 ibld
.MOV(compr4_dst
, inst
->src
[i
]);
3206 /* Platform doesn't have COMPR4. We have to fake it */
3207 fs_reg mov_dst
= retype(dst
, inst
->src
[i
].type
);
3208 ibld
.half(0).MOV(mov_dst
, half(inst
->src
[i
], 0));
3210 ibld
.half(1).MOV(mov_dst
, half(inst
->src
[i
], 1));
3217 /* The loop above only ever incremented us through the first set
3218 * of 4 registers. However, thanks to the magic of COMPR4, we
3219 * actually wrote to the first 8 registers, so we need to take
3220 * that into account now.
3224 /* The COMPR4 code took care of the first 4 sources. We'll let
3225 * the regular path handle any remaining sources. Yes, we are
3226 * modifying the instruction but we're about to delete it so
3227 * this really doesn't hurt anything.
3229 inst
->header_size
+= 4;
3232 for (uint8_t i
= inst
->header_size
; i
< inst
->sources
; i
++) {
3233 if (inst
->src
[i
].file
!= BAD_FILE
)
3234 ibld
.MOV(retype(dst
, inst
->src
[i
].type
), inst
->src
[i
]);
3235 dst
= offset(dst
, ibld
, 1);
3238 inst
->remove(block
);
3243 invalidate_live_intervals();
3249 fs_visitor::lower_integer_multiplication()
3251 bool progress
= false;
3253 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
3254 const fs_builder
ibld(this, block
, inst
);
3256 if (inst
->opcode
== BRW_OPCODE_MUL
) {
3257 if (inst
->dst
.is_accumulator() ||
3258 (inst
->dst
.type
!= BRW_REGISTER_TYPE_D
&&
3259 inst
->dst
.type
!= BRW_REGISTER_TYPE_UD
))
3262 /* Gen8's MUL instruction can do a 32-bit x 32-bit -> 32-bit
3263 * operation directly, but CHV/BXT cannot.
3265 if (devinfo
->gen
>= 8 &&
3266 !devinfo
->is_cherryview
&& !devinfo
->is_broxton
)
3269 if (inst
->src
[1].file
== IMM
&&
3270 inst
->src
[1].ud
< (1 << 16)) {
3271 /* The MUL instruction isn't commutative. On Gen <= 6, only the low
3272 * 16-bits of src0 are read, and on Gen >= 7 only the low 16-bits of
3275 * If multiplying by an immediate value that fits in 16-bits, do a
3276 * single MUL instruction with that value in the proper location.
3278 if (devinfo
->gen
< 7) {
3279 fs_reg
imm(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3281 ibld
.MOV(imm
, inst
->src
[1]);
3282 ibld
.MUL(inst
->dst
, imm
, inst
->src
[0]);
3284 ibld
.MUL(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3287 /* Gen < 8 (and some Gen8+ low-power parts like Cherryview) cannot
3288 * do 32-bit integer multiplication in one instruction, but instead
3289 * must do a sequence (which actually calculates a 64-bit result):
3291 * mul(8) acc0<1>D g3<8,8,1>D g4<8,8,1>D
3292 * mach(8) null g3<8,8,1>D g4<8,8,1>D
3293 * mov(8) g2<1>D acc0<8,8,1>D
3295 * But on Gen > 6, the ability to use second accumulator register
3296 * (acc1) for non-float data types was removed, preventing a simple
3297 * implementation in SIMD16. A 16-channel result can be calculated by
3298 * executing the three instructions twice in SIMD8, once with quarter
3299 * control of 1Q for the first eight channels and again with 2Q for
3300 * the second eight channels.
3302 * Which accumulator register is implicitly accessed (by AccWrEnable
3303 * for instance) is determined by the quarter control. Unfortunately
3304 * Ivybridge (and presumably Baytrail) has a hardware bug in which an
3305 * implicit accumulator access by an instruction with 2Q will access
3306 * acc1 regardless of whether the data type is usable in acc1.
3308 * Specifically, the 2Q mach(8) writes acc1 which does not exist for
3309 * integer data types.
3311 * Since we only want the low 32-bits of the result, we can do two
3312 * 32-bit x 16-bit multiplies (like the mul and mach are doing), and
3313 * adjust the high result and add them (like the mach is doing):
3315 * mul(8) g7<1>D g3<8,8,1>D g4.0<8,8,1>UW
3316 * mul(8) g8<1>D g3<8,8,1>D g4.1<8,8,1>UW
3317 * shl(8) g9<1>D g8<8,8,1>D 16D
3318 * add(8) g2<1>D g7<8,8,1>D g8<8,8,1>D
3320 * We avoid the shl instruction by realizing that we only want to add
3321 * the low 16-bits of the "high" result to the high 16-bits of the
3322 * "low" result and using proper regioning on the add:
3324 * mul(8) g7<1>D g3<8,8,1>D g4.0<16,8,2>UW
3325 * mul(8) g8<1>D g3<8,8,1>D g4.1<16,8,2>UW
3326 * add(8) g7.1<2>UW g7.1<16,8,2>UW g8<16,8,2>UW
3328 * Since it does not use the (single) accumulator register, we can
3329 * schedule multi-component multiplications much better.
3332 fs_reg orig_dst
= inst
->dst
;
3333 if (orig_dst
.is_null() || orig_dst
.file
== MRF
) {
3334 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3337 fs_reg low
= inst
->dst
;
3338 fs_reg
high(VGRF
, alloc
.allocate(dispatch_width
/ 8),
3341 if (devinfo
->gen
>= 7) {
3342 fs_reg src1_0_w
= inst
->src
[1];
3343 fs_reg src1_1_w
= inst
->src
[1];
3345 if (inst
->src
[1].file
== IMM
) {
3346 src1_0_w
.ud
&= 0xffff;
3349 src1_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3350 if (src1_0_w
.stride
!= 0) {
3351 assert(src1_0_w
.stride
== 1);
3352 src1_0_w
.stride
= 2;
3355 src1_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3356 if (src1_1_w
.stride
!= 0) {
3357 assert(src1_1_w
.stride
== 1);
3358 src1_1_w
.stride
= 2;
3360 src1_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3362 ibld
.MUL(low
, inst
->src
[0], src1_0_w
);
3363 ibld
.MUL(high
, inst
->src
[0], src1_1_w
);
3365 fs_reg src0_0_w
= inst
->src
[0];
3366 fs_reg src0_1_w
= inst
->src
[0];
3368 src0_0_w
.type
= BRW_REGISTER_TYPE_UW
;
3369 if (src0_0_w
.stride
!= 0) {
3370 assert(src0_0_w
.stride
== 1);
3371 src0_0_w
.stride
= 2;
3374 src0_1_w
.type
= BRW_REGISTER_TYPE_UW
;
3375 if (src0_1_w
.stride
!= 0) {
3376 assert(src0_1_w
.stride
== 1);
3377 src0_1_w
.stride
= 2;
3379 src0_1_w
.subreg_offset
+= type_sz(BRW_REGISTER_TYPE_UW
);
3381 ibld
.MUL(low
, src0_0_w
, inst
->src
[1]);
3382 ibld
.MUL(high
, src0_1_w
, inst
->src
[1]);
3385 fs_reg dst
= inst
->dst
;
3386 dst
.type
= BRW_REGISTER_TYPE_UW
;
3387 dst
.subreg_offset
= 2;
3390 high
.type
= BRW_REGISTER_TYPE_UW
;
3393 low
.type
= BRW_REGISTER_TYPE_UW
;
3394 low
.subreg_offset
= 2;
3397 ibld
.ADD(dst
, low
, high
);
3399 if (inst
->conditional_mod
|| orig_dst
.file
== MRF
) {
3400 set_condmod(inst
->conditional_mod
,
3401 ibld
.MOV(orig_dst
, inst
->dst
));
3405 } else if (inst
->opcode
== SHADER_OPCODE_MULH
) {
3406 /* Should have been lowered to 8-wide. */
3407 assert(inst
->exec_size
<= 8);
3408 const fs_reg acc
= retype(brw_acc_reg(inst
->exec_size
),
3410 fs_inst
*mul
= ibld
.MUL(acc
, inst
->src
[0], inst
->src
[1]);
3411 fs_inst
*mach
= ibld
.MACH(inst
->dst
, inst
->src
[0], inst
->src
[1]);
3413 if (devinfo
->gen
>= 8) {
3414 /* Until Gen8, integer multiplies read 32-bits from one source,
3415 * and 16-bits from the other, and relying on the MACH instruction
3416 * to generate the high bits of the result.
3418 * On Gen8, the multiply instruction does a full 32x32-bit
3419 * multiply, but in order to do a 64-bit multiply we can simulate
3420 * the previous behavior and then use a MACH instruction.
3422 * FINISHME: Don't use source modifiers on src1.
3424 assert(mul
->src
[1].type
== BRW_REGISTER_TYPE_D
||
3425 mul
->src
[1].type
== BRW_REGISTER_TYPE_UD
);
3426 mul
->src
[1].type
= (type_is_signed(mul
->src
[1].type
) ?
3427 BRW_REGISTER_TYPE_W
: BRW_REGISTER_TYPE_UW
);
3428 mul
->src
[1].stride
*= 2;
3430 } else if (devinfo
->gen
== 7 && !devinfo
->is_haswell
&&
3431 inst
->force_sechalf
) {
3432 /* Among other things the quarter control bits influence which
3433 * accumulator register is used by the hardware for instructions
3434 * that access the accumulator implicitly (e.g. MACH). A
3435 * second-half instruction would normally map to acc1, which
3436 * doesn't exist on Gen7 and up (the hardware does emulate it for
3437 * floating-point instructions *only* by taking advantage of the
3438 * extra precision of acc0 not normally used for floating point
3441 * HSW and up are careful enough not to try to access an
3442 * accumulator register that doesn't exist, but on earlier Gen7
3443 * hardware we need to make sure that the quarter control bits are
3444 * zero to avoid non-deterministic behaviour and emit an extra MOV
3445 * to get the result masked correctly according to the current
3448 mach
->force_sechalf
= false;
3449 mach
->force_writemask_all
= true;
3450 mach
->dst
= ibld
.vgrf(inst
->dst
.type
);
3451 ibld
.MOV(inst
->dst
, mach
->dst
);
3457 inst
->remove(block
);
3462 invalidate_live_intervals();
3468 setup_color_payload(const fs_builder
&bld
, const brw_wm_prog_key
*key
,
3469 fs_reg
*dst
, fs_reg color
, unsigned components
)
3471 if (key
->clamp_fragment_color
) {
3472 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
3473 assert(color
.type
== BRW_REGISTER_TYPE_F
);
3475 for (unsigned i
= 0; i
< components
; i
++)
3477 bld
.MOV(offset(tmp
, bld
, i
), offset(color
, bld
, i
)));
3482 for (unsigned i
= 0; i
< components
; i
++)
3483 dst
[i
] = offset(color
, bld
, i
);
3487 lower_fb_write_logical_send(const fs_builder
&bld
, fs_inst
*inst
,
3488 const brw_wm_prog_data
*prog_data
,
3489 const brw_wm_prog_key
*key
,
3490 const fs_visitor::thread_payload
&payload
)
3492 assert(inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].file
== IMM
);
3493 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3494 const fs_reg
&color0
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR0
];
3495 const fs_reg
&color1
= inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
];
3496 const fs_reg
&src0_alpha
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC0_ALPHA
];
3497 const fs_reg
&src_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
];
3498 const fs_reg
&dst_depth
= inst
->src
[FB_WRITE_LOGICAL_SRC_DST_DEPTH
];
3499 const fs_reg
&src_stencil
= inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_STENCIL
];
3500 fs_reg sample_mask
= inst
->src
[FB_WRITE_LOGICAL_SRC_OMASK
];
3501 const unsigned components
=
3502 inst
->src
[FB_WRITE_LOGICAL_SRC_COMPONENTS
].ud
;
3504 /* We can potentially have a message length of up to 15, so we have to set
3505 * base_mrf to either 0 or 1 in order to fit in m0..m15.
3508 int header_size
= 2, payload_header_size
;
3509 unsigned length
= 0;
3511 /* From the Sandy Bridge PRM, volume 4, page 198:
3513 * "Dispatched Pixel Enables. One bit per pixel indicating
3514 * which pixels were originally enabled when the thread was
3515 * dispatched. This field is only required for the end-of-
3516 * thread message and on all dual-source messages."
3518 if (devinfo
->gen
>= 6 &&
3519 (devinfo
->is_haswell
|| devinfo
->gen
>= 8 || !prog_data
->uses_kill
) &&
3520 color1
.file
== BAD_FILE
&&
3521 key
->nr_color_regions
== 1) {
3525 if (header_size
!= 0) {
3526 assert(header_size
== 2);
3527 /* Allocate 2 registers for a header */
3531 if (payload
.aa_dest_stencil_reg
) {
3532 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1));
3533 bld
.group(8, 0).exec_all().annotate("FB write stencil/AA alpha")
3534 .MOV(sources
[length
],
3535 fs_reg(brw_vec8_grf(payload
.aa_dest_stencil_reg
, 0)));
3539 if (prog_data
->uses_omask
) {
3540 sources
[length
] = fs_reg(VGRF
, bld
.shader
->alloc
.allocate(1),
3541 BRW_REGISTER_TYPE_UD
);
3543 /* Hand over gl_SampleMask. Only the lower 16 bits of each channel are
3544 * relevant. Since it's unsigned single words one vgrf is always
3545 * 16-wide, but only the lower or higher 8 channels will be used by the
3546 * hardware when doing a SIMD8 write depending on whether we have
3547 * selected the subspans for the first or second half respectively.
3549 assert(sample_mask
.file
!= BAD_FILE
&& type_sz(sample_mask
.type
) == 4);
3550 sample_mask
.type
= BRW_REGISTER_TYPE_UW
;
3551 sample_mask
.stride
*= 2;
3553 bld
.exec_all().annotate("FB write oMask")
3554 .MOV(half(retype(sources
[length
], BRW_REGISTER_TYPE_UW
),
3555 inst
->force_sechalf
),
3560 payload_header_size
= length
;
3562 if (src0_alpha
.file
!= BAD_FILE
) {
3563 /* FIXME: This is being passed at the wrong location in the payload and
3564 * doesn't work when gl_SampleMask and MRTs are used simultaneously.
3565 * It's supposed to be immediately before oMask but there seems to be no
3566 * reasonable way to pass them in the correct order because LOAD_PAYLOAD
3567 * requires header sources to form a contiguous segment at the beginning
3568 * of the message and src0_alpha has per-channel semantics.
3570 setup_color_payload(bld
, key
, &sources
[length
], src0_alpha
, 1);
3574 setup_color_payload(bld
, key
, &sources
[length
], color0
, components
);
3577 if (color1
.file
!= BAD_FILE
) {
3578 setup_color_payload(bld
, key
, &sources
[length
], color1
, components
);
3582 if (src_depth
.file
!= BAD_FILE
) {
3583 sources
[length
] = src_depth
;
3587 if (dst_depth
.file
!= BAD_FILE
) {
3588 sources
[length
] = dst_depth
;
3592 if (src_stencil
.file
!= BAD_FILE
) {
3593 assert(devinfo
->gen
>= 9);
3594 assert(bld
.dispatch_width() != 16);
3596 /* XXX: src_stencil is only available on gen9+. dst_depth is never
3597 * available on gen9+. As such it's impossible to have both enabled at the
3598 * same time and therefore length cannot overrun the array.
3600 assert(length
< 15);
3602 sources
[length
] = bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3603 bld
.exec_all().annotate("FB write OS")
3604 .emit(FS_OPCODE_PACK_STENCIL_REF
, sources
[length
],
3605 retype(src_stencil
, BRW_REGISTER_TYPE_UB
));
3610 if (devinfo
->gen
>= 7) {
3611 /* Send from the GRF */
3612 fs_reg payload
= fs_reg(VGRF
, -1, BRW_REGISTER_TYPE_F
);
3613 load
= bld
.LOAD_PAYLOAD(payload
, sources
, length
, payload_header_size
);
3614 payload
.nr
= bld
.shader
->alloc
.allocate(load
->regs_written
);
3615 load
->dst
= payload
;
3617 inst
->src
[0] = payload
;
3618 inst
->resize_sources(1);
3619 inst
->base_mrf
= -1;
3621 /* Send from the MRF */
3622 load
= bld
.LOAD_PAYLOAD(fs_reg(MRF
, 1, BRW_REGISTER_TYPE_F
),
3623 sources
, length
, payload_header_size
);
3625 /* On pre-SNB, we have to interlace the color values. LOAD_PAYLOAD
3626 * will do this for us if we just give it a COMPR4 destination.
3628 if (devinfo
->gen
< 6 && bld
.dispatch_width() == 16)
3629 load
->dst
.nr
|= BRW_MRF_COMPR4
;
3631 inst
->resize_sources(0);
3635 inst
->opcode
= FS_OPCODE_FB_WRITE
;
3636 inst
->mlen
= load
->regs_written
;
3637 inst
->header_size
= header_size
;
3641 lower_sampler_logical_send_gen4(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3642 const fs_reg
&coordinate
,
3643 const fs_reg
&shadow_c
,
3644 const fs_reg
&lod
, const fs_reg
&lod2
,
3645 const fs_reg
&sampler
,
3646 unsigned coord_components
,
3647 unsigned grad_components
)
3649 const bool has_lod
= (op
== SHADER_OPCODE_TXL
|| op
== FS_OPCODE_TXB
||
3650 op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
);
3651 fs_reg
msg_begin(MRF
, 1, BRW_REGISTER_TYPE_F
);
3652 fs_reg msg_end
= msg_begin
;
3655 msg_end
= offset(msg_end
, bld
.group(8, 0), 1);
3657 for (unsigned i
= 0; i
< coord_components
; i
++)
3658 bld
.MOV(retype(offset(msg_end
, bld
, i
), coordinate
.type
),
3659 offset(coordinate
, bld
, i
));
3661 msg_end
= offset(msg_end
, bld
, coord_components
);
3663 /* Messages other than SAMPLE and RESINFO in SIMD16 and TXD in SIMD8
3664 * require all three components to be present and zero if they are unused.
3666 if (coord_components
> 0 &&
3667 (has_lod
|| shadow_c
.file
!= BAD_FILE
||
3668 (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8))) {
3669 for (unsigned i
= coord_components
; i
< 3; i
++)
3670 bld
.MOV(offset(msg_end
, bld
, i
), brw_imm_f(0.0f
));
3672 msg_end
= offset(msg_end
, bld
, 3 - coord_components
);
3675 if (op
== SHADER_OPCODE_TXD
) {
3676 /* TXD unsupported in SIMD16 mode. */
3677 assert(bld
.dispatch_width() == 8);
3679 /* the slots for u and v are always present, but r is optional */
3680 if (coord_components
< 2)
3681 msg_end
= offset(msg_end
, bld
, 2 - coord_components
);
3684 * dPdx = dudx, dvdx, drdx
3685 * dPdy = dudy, dvdy, drdy
3687 * 1-arg: Does not exist.
3689 * 2-arg: dudx dvdx dudy dvdy
3690 * dPdx.x dPdx.y dPdy.x dPdy.y
3693 * 3-arg: dudx dvdx drdx dudy dvdy drdy
3694 * dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
3695 * m5 m6 m7 m8 m9 m10
3697 for (unsigned i
= 0; i
< grad_components
; i
++)
3698 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod
, bld
, i
));
3700 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3702 for (unsigned i
= 0; i
< grad_components
; i
++)
3703 bld
.MOV(offset(msg_end
, bld
, i
), offset(lod2
, bld
, i
));
3705 msg_end
= offset(msg_end
, bld
, MAX2(grad_components
, 2));
3709 /* Bias/LOD with shadow comparitor is unsupported in SIMD16 -- *Without*
3710 * shadow comparitor (including RESINFO) it's unsupported in SIMD8 mode.
3712 assert(shadow_c
.file
!= BAD_FILE
? bld
.dispatch_width() == 8 :
3713 bld
.dispatch_width() == 16);
3715 const brw_reg_type type
=
3716 (op
== SHADER_OPCODE_TXF
|| op
== SHADER_OPCODE_TXS
?
3717 BRW_REGISTER_TYPE_UD
: BRW_REGISTER_TYPE_F
);
3718 bld
.MOV(retype(msg_end
, type
), lod
);
3719 msg_end
= offset(msg_end
, bld
, 1);
3722 if (shadow_c
.file
!= BAD_FILE
) {
3723 if (op
== SHADER_OPCODE_TEX
&& bld
.dispatch_width() == 8) {
3724 /* There's no plain shadow compare message, so we use shadow
3725 * compare with a bias of 0.0.
3727 bld
.MOV(msg_end
, brw_imm_f(0.0f
));
3728 msg_end
= offset(msg_end
, bld
, 1);
3731 bld
.MOV(msg_end
, shadow_c
);
3732 msg_end
= offset(msg_end
, bld
, 1);
3736 inst
->src
[0] = reg_undef
;
3737 inst
->src
[1] = sampler
;
3738 inst
->resize_sources(2);
3739 inst
->base_mrf
= msg_begin
.nr
;
3740 inst
->mlen
= msg_end
.nr
- msg_begin
.nr
;
3741 inst
->header_size
= 1;
3745 lower_sampler_logical_send_gen5(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3747 const fs_reg
&shadow_c
,
3748 fs_reg lod
, fs_reg lod2
,
3749 const fs_reg
&sample_index
,
3750 const fs_reg
&sampler
,
3751 const fs_reg
&offset_value
,
3752 unsigned coord_components
,
3753 unsigned grad_components
)
3755 fs_reg
message(MRF
, 2, BRW_REGISTER_TYPE_F
);
3756 fs_reg msg_coords
= message
;
3757 unsigned header_size
= 0;
3759 if (offset_value
.file
!= BAD_FILE
) {
3760 /* The offsets set up by the visitor are in the m1 header, so we can't
3767 for (unsigned i
= 0; i
< coord_components
; i
++) {
3768 bld
.MOV(retype(offset(msg_coords
, bld
, i
), coordinate
.type
), coordinate
);
3769 coordinate
= offset(coordinate
, bld
, 1);
3771 fs_reg msg_end
= offset(msg_coords
, bld
, coord_components
);
3772 fs_reg msg_lod
= offset(msg_coords
, bld
, 4);
3774 if (shadow_c
.file
!= BAD_FILE
) {
3775 fs_reg msg_shadow
= msg_lod
;
3776 bld
.MOV(msg_shadow
, shadow_c
);
3777 msg_lod
= offset(msg_shadow
, bld
, 1);
3782 case SHADER_OPCODE_TXL
:
3784 bld
.MOV(msg_lod
, lod
);
3785 msg_end
= offset(msg_lod
, bld
, 1);
3787 case SHADER_OPCODE_TXD
:
3790 * dPdx = dudx, dvdx, drdx
3791 * dPdy = dudy, dvdy, drdy
3793 * Load up these values:
3794 * - dudx dudy dvdx dvdy drdx drdy
3795 * - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
3798 for (unsigned i
= 0; i
< grad_components
; i
++) {
3799 bld
.MOV(msg_end
, lod
);
3800 lod
= offset(lod
, bld
, 1);
3801 msg_end
= offset(msg_end
, bld
, 1);
3803 bld
.MOV(msg_end
, lod2
);
3804 lod2
= offset(lod2
, bld
, 1);
3805 msg_end
= offset(msg_end
, bld
, 1);
3808 case SHADER_OPCODE_TXS
:
3809 msg_lod
= retype(msg_end
, BRW_REGISTER_TYPE_UD
);
3810 bld
.MOV(msg_lod
, lod
);
3811 msg_end
= offset(msg_lod
, bld
, 1);
3813 case SHADER_OPCODE_TXF
:
3814 msg_lod
= offset(msg_coords
, bld
, 3);
3815 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), lod
);
3816 msg_end
= offset(msg_lod
, bld
, 1);
3818 case SHADER_OPCODE_TXF_CMS
:
3819 msg_lod
= offset(msg_coords
, bld
, 3);
3821 bld
.MOV(retype(msg_lod
, BRW_REGISTER_TYPE_UD
), brw_imm_ud(0u));
3823 bld
.MOV(retype(offset(msg_lod
, bld
, 1), BRW_REGISTER_TYPE_UD
), sample_index
);
3824 msg_end
= offset(msg_lod
, bld
, 2);
3831 inst
->src
[0] = reg_undef
;
3832 inst
->src
[1] = sampler
;
3833 inst
->resize_sources(2);
3834 inst
->base_mrf
= message
.nr
;
3835 inst
->mlen
= msg_end
.nr
- message
.nr
;
3836 inst
->header_size
= header_size
;
3838 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
3839 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
3843 is_high_sampler(const struct brw_device_info
*devinfo
, const fs_reg
&sampler
)
3845 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
)
3848 return sampler
.file
!= IMM
|| sampler
.ud
>= 16;
3852 lower_sampler_logical_send_gen7(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
3854 const fs_reg
&shadow_c
,
3855 fs_reg lod
, fs_reg lod2
,
3856 const fs_reg
&sample_index
,
3857 const fs_reg
&mcs
, const fs_reg
&sampler
,
3858 fs_reg offset_value
,
3859 unsigned coord_components
,
3860 unsigned grad_components
)
3862 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
3863 int reg_width
= bld
.dispatch_width() / 8;
3864 unsigned header_size
= 0, length
= 0;
3865 fs_reg sources
[MAX_SAMPLER_MESSAGE_SIZE
];
3866 for (unsigned i
= 0; i
< ARRAY_SIZE(sources
); i
++)
3867 sources
[i
] = bld
.vgrf(BRW_REGISTER_TYPE_F
);
3869 if (op
== SHADER_OPCODE_TG4
|| op
== SHADER_OPCODE_TG4_OFFSET
||
3870 offset_value
.file
!= BAD_FILE
||
3871 is_high_sampler(devinfo
, sampler
)) {
3872 /* For general texture offsets (no txf workaround), we need a header to
3873 * put them in. Note that we're only reserving space for it in the
3874 * message payload as it will be initialized implicitly by the
3877 * TG4 needs to place its channel select in the header, for interaction
3878 * with ARB_texture_swizzle. The sampler index is only 4-bits, so for
3879 * larger sampler numbers we need to offset the Sampler State Pointer in
3883 sources
[0] = fs_reg();
3887 if (shadow_c
.file
!= BAD_FILE
) {
3888 bld
.MOV(sources
[length
], shadow_c
);
3892 bool coordinate_done
= false;
3894 /* The sampler can only meaningfully compute LOD for fragment shader
3895 * messages. For all other stages, we change the opcode to TXL and
3896 * hardcode the LOD to 0.
3898 if (bld
.shader
->stage
!= MESA_SHADER_FRAGMENT
&&
3899 op
== SHADER_OPCODE_TEX
) {
3900 op
= SHADER_OPCODE_TXL
;
3901 lod
= brw_imm_f(0.0f
);
3904 /* Set up the LOD info */
3907 case SHADER_OPCODE_TXL
:
3908 bld
.MOV(sources
[length
], lod
);
3911 case SHADER_OPCODE_TXD
:
3912 /* TXD should have been lowered in SIMD16 mode. */
3913 assert(bld
.dispatch_width() == 8);
3915 /* Load dPdx and the coordinate together:
3916 * [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
3918 for (unsigned i
= 0; i
< coord_components
; i
++) {
3919 bld
.MOV(sources
[length
], coordinate
);
3920 coordinate
= offset(coordinate
, bld
, 1);
3923 /* For cube map array, the coordinate is (u,v,r,ai) but there are
3924 * only derivatives for (u, v, r).
3926 if (i
< grad_components
) {
3927 bld
.MOV(sources
[length
], lod
);
3928 lod
= offset(lod
, bld
, 1);
3931 bld
.MOV(sources
[length
], lod2
);
3932 lod2
= offset(lod2
, bld
, 1);
3937 coordinate_done
= true;
3939 case SHADER_OPCODE_TXS
:
3940 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), lod
);
3943 case SHADER_OPCODE_TXF
:
3944 /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
3945 * On Gen9 they are u, v, lod, r
3947 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3948 coordinate
= offset(coordinate
, bld
, 1);
3951 if (devinfo
->gen
>= 9) {
3952 if (coord_components
>= 2) {
3953 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3954 coordinate
= offset(coordinate
, bld
, 1);
3959 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), lod
);
3962 for (unsigned i
= devinfo
->gen
>= 9 ? 2 : 1; i
< coord_components
; i
++) {
3963 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
3964 coordinate
= offset(coordinate
, bld
, 1);
3968 coordinate_done
= true;
3970 case SHADER_OPCODE_TXF_CMS
:
3971 case SHADER_OPCODE_TXF_CMS_W
:
3972 case SHADER_OPCODE_TXF_UMS
:
3973 case SHADER_OPCODE_TXF_MCS
:
3974 if (op
== SHADER_OPCODE_TXF_UMS
||
3975 op
== SHADER_OPCODE_TXF_CMS
||
3976 op
== SHADER_OPCODE_TXF_CMS_W
) {
3977 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), sample_index
);
3981 if (op
== SHADER_OPCODE_TXF_CMS
|| op
== SHADER_OPCODE_TXF_CMS_W
) {
3982 /* Data from the multisample control surface. */
3983 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
), mcs
);
3986 /* On Gen9+ we'll use ld2dms_w instead which has two registers for
3989 if (op
== SHADER_OPCODE_TXF_CMS_W
) {
3990 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_UD
),
3993 offset(mcs
, bld
, 1));
3998 /* There is no offsetting for this message; just copy in the integer
3999 * texture coordinates.
4001 for (unsigned i
= 0; i
< coord_components
; i
++) {
4002 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), coordinate
);
4003 coordinate
= offset(coordinate
, bld
, 1);
4007 coordinate_done
= true;
4009 case SHADER_OPCODE_TG4_OFFSET
:
4010 /* gather4_po_c should have been lowered in SIMD16 mode. */
4011 assert(bld
.dispatch_width() == 8 || shadow_c
.file
== BAD_FILE
);
4013 /* More crazy intermixing */
4014 for (unsigned i
= 0; i
< 2; i
++) { /* u, v */
4015 bld
.MOV(sources
[length
], coordinate
);
4016 coordinate
= offset(coordinate
, bld
, 1);
4020 for (unsigned i
= 0; i
< 2; i
++) { /* offu, offv */
4021 bld
.MOV(retype(sources
[length
], BRW_REGISTER_TYPE_D
), offset_value
);
4022 offset_value
= offset(offset_value
, bld
, 1);
4026 if (coord_components
== 3) { /* r if present */
4027 bld
.MOV(sources
[length
], coordinate
);
4028 coordinate
= offset(coordinate
, bld
, 1);
4032 coordinate_done
= true;
4038 /* Set up the coordinate (except for cases where it was done above) */
4039 if (!coordinate_done
) {
4040 for (unsigned i
= 0; i
< coord_components
; i
++) {
4041 bld
.MOV(sources
[length
], coordinate
);
4042 coordinate
= offset(coordinate
, bld
, 1);
4049 mlen
= length
* reg_width
- header_size
;
4051 mlen
= length
* reg_width
;
4053 const fs_reg src_payload
= fs_reg(VGRF
, bld
.shader
->alloc
.allocate(mlen
),
4054 BRW_REGISTER_TYPE_F
);
4055 bld
.LOAD_PAYLOAD(src_payload
, sources
, length
, header_size
);
4057 /* Generate the SEND. */
4059 inst
->src
[0] = src_payload
;
4060 inst
->src
[1] = sampler
;
4061 inst
->resize_sources(2);
4062 inst
->base_mrf
= -1;
4064 inst
->header_size
= header_size
;
4066 /* Message length > MAX_SAMPLER_MESSAGE_SIZE disallowed by hardware. */
4067 assert(inst
->mlen
<= MAX_SAMPLER_MESSAGE_SIZE
);
4071 lower_sampler_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
)
4073 const brw_device_info
*devinfo
= bld
.shader
->devinfo
;
4074 const fs_reg
&coordinate
= inst
->src
[0];
4075 const fs_reg
&shadow_c
= inst
->src
[1];
4076 const fs_reg
&lod
= inst
->src
[2];
4077 const fs_reg
&lod2
= inst
->src
[3];
4078 const fs_reg
&sample_index
= inst
->src
[4];
4079 const fs_reg
&mcs
= inst
->src
[5];
4080 const fs_reg
&sampler
= inst
->src
[6];
4081 const fs_reg
&offset_value
= inst
->src
[7];
4082 assert(inst
->src
[8].file
== IMM
&& inst
->src
[9].file
== IMM
);
4083 const unsigned coord_components
= inst
->src
[8].ud
;
4084 const unsigned grad_components
= inst
->src
[9].ud
;
4086 if (devinfo
->gen
>= 7) {
4087 lower_sampler_logical_send_gen7(bld
, inst
, op
, coordinate
,
4088 shadow_c
, lod
, lod2
, sample_index
,
4089 mcs
, sampler
, offset_value
,
4090 coord_components
, grad_components
);
4091 } else if (devinfo
->gen
>= 5) {
4092 lower_sampler_logical_send_gen5(bld
, inst
, op
, coordinate
,
4093 shadow_c
, lod
, lod2
, sample_index
,
4094 sampler
, offset_value
,
4095 coord_components
, grad_components
);
4097 lower_sampler_logical_send_gen4(bld
, inst
, op
, coordinate
,
4098 shadow_c
, lod
, lod2
, sampler
,
4099 coord_components
, grad_components
);
4104 * Initialize the header present in some typed and untyped surface
4108 emit_surface_header(const fs_builder
&bld
, const fs_reg
&sample_mask
)
4110 fs_builder ubld
= bld
.exec_all().group(8, 0);
4111 const fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4112 ubld
.MOV(dst
, brw_imm_d(0));
4113 ubld
.MOV(component(dst
, 7), sample_mask
);
4118 lower_surface_logical_send(const fs_builder
&bld
, fs_inst
*inst
, opcode op
,
4119 const fs_reg
&sample_mask
)
4121 /* Get the logical send arguments. */
4122 const fs_reg
&addr
= inst
->src
[0];
4123 const fs_reg
&src
= inst
->src
[1];
4124 const fs_reg
&surface
= inst
->src
[2];
4125 const UNUSED fs_reg
&dims
= inst
->src
[3];
4126 const fs_reg
&arg
= inst
->src
[4];
4128 /* Calculate the total number of components of the payload. */
4129 const unsigned addr_sz
= inst
->components_read(0);
4130 const unsigned src_sz
= inst
->components_read(1);
4131 const unsigned header_sz
= (sample_mask
.file
== BAD_FILE
? 0 : 1);
4132 const unsigned sz
= header_sz
+ addr_sz
+ src_sz
;
4134 /* Allocate space for the payload. */
4135 fs_reg
*const components
= new fs_reg
[sz
];
4136 const fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, sz
);
4139 /* Construct the payload. */
4141 components
[n
++] = emit_surface_header(bld
, sample_mask
);
4143 for (unsigned i
= 0; i
< addr_sz
; i
++)
4144 components
[n
++] = offset(addr
, bld
, i
);
4146 for (unsigned i
= 0; i
< src_sz
; i
++)
4147 components
[n
++] = offset(src
, bld
, i
);
4149 bld
.LOAD_PAYLOAD(payload
, components
, sz
, header_sz
);
4151 /* Update the original instruction. */
4153 inst
->mlen
= header_sz
+ (addr_sz
+ src_sz
) * inst
->exec_size
/ 8;
4154 inst
->header_size
= header_sz
;
4156 inst
->src
[0] = payload
;
4157 inst
->src
[1] = surface
;
4159 inst
->resize_sources(3);
4161 delete[] components
;
4165 fs_visitor::lower_logical_sends()
4167 bool progress
= false;
4169 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4170 const fs_builder
ibld(this, block
, inst
);
4172 switch (inst
->opcode
) {
4173 case FS_OPCODE_FB_WRITE_LOGICAL
:
4174 assert(stage
== MESA_SHADER_FRAGMENT
);
4175 lower_fb_write_logical_send(ibld
, inst
,
4176 (const brw_wm_prog_data
*)prog_data
,
4177 (const brw_wm_prog_key
*)key
,
4181 case SHADER_OPCODE_TEX_LOGICAL
:
4182 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TEX
);
4185 case SHADER_OPCODE_TXD_LOGICAL
:
4186 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXD
);
4189 case SHADER_OPCODE_TXF_LOGICAL
:
4190 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF
);
4193 case SHADER_OPCODE_TXL_LOGICAL
:
4194 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXL
);
4197 case SHADER_OPCODE_TXS_LOGICAL
:
4198 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXS
);
4201 case FS_OPCODE_TXB_LOGICAL
:
4202 lower_sampler_logical_send(ibld
, inst
, FS_OPCODE_TXB
);
4205 case SHADER_OPCODE_TXF_CMS_LOGICAL
:
4206 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS
);
4209 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
4210 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_CMS_W
);
4213 case SHADER_OPCODE_TXF_UMS_LOGICAL
:
4214 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_UMS
);
4217 case SHADER_OPCODE_TXF_MCS_LOGICAL
:
4218 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TXF_MCS
);
4221 case SHADER_OPCODE_LOD_LOGICAL
:
4222 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_LOD
);
4225 case SHADER_OPCODE_TG4_LOGICAL
:
4226 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4
);
4229 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
:
4230 lower_sampler_logical_send(ibld
, inst
, SHADER_OPCODE_TG4_OFFSET
);
4233 case SHADER_OPCODE_UNTYPED_SURFACE_READ_LOGICAL
:
4234 lower_surface_logical_send(ibld
, inst
,
4235 SHADER_OPCODE_UNTYPED_SURFACE_READ
,
4239 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE_LOGICAL
:
4240 lower_surface_logical_send(ibld
, inst
,
4241 SHADER_OPCODE_UNTYPED_SURFACE_WRITE
,
4242 ibld
.sample_mask_reg());
4245 case SHADER_OPCODE_UNTYPED_ATOMIC_LOGICAL
:
4246 lower_surface_logical_send(ibld
, inst
,
4247 SHADER_OPCODE_UNTYPED_ATOMIC
,
4248 ibld
.sample_mask_reg());
4251 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4252 lower_surface_logical_send(ibld
, inst
,
4253 SHADER_OPCODE_TYPED_SURFACE_READ
,
4257 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4258 lower_surface_logical_send(ibld
, inst
,
4259 SHADER_OPCODE_TYPED_SURFACE_WRITE
,
4260 ibld
.sample_mask_reg());
4263 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4264 lower_surface_logical_send(ibld
, inst
,
4265 SHADER_OPCODE_TYPED_ATOMIC
,
4266 ibld
.sample_mask_reg());
4277 invalidate_live_intervals();
4283 * Get the closest native SIMD width supported by the hardware for instruction
4284 * \p inst. The instruction will be left untouched by
4285 * fs_visitor::lower_simd_width() if the returned value is equal to the
4286 * original execution size.
4289 get_lowered_simd_width(const struct brw_device_info
*devinfo
,
4290 const fs_inst
*inst
)
4292 switch (inst
->opcode
) {
4293 case BRW_OPCODE_MOV
:
4294 case BRW_OPCODE_SEL
:
4295 case BRW_OPCODE_NOT
:
4296 case BRW_OPCODE_AND
:
4298 case BRW_OPCODE_XOR
:
4299 case BRW_OPCODE_SHR
:
4300 case BRW_OPCODE_SHL
:
4301 case BRW_OPCODE_ASR
:
4302 case BRW_OPCODE_CMP
:
4303 case BRW_OPCODE_CMPN
:
4304 case BRW_OPCODE_CSEL
:
4305 case BRW_OPCODE_F32TO16
:
4306 case BRW_OPCODE_F16TO32
:
4307 case BRW_OPCODE_BFREV
:
4308 case BRW_OPCODE_BFE
:
4309 case BRW_OPCODE_BFI1
:
4310 case BRW_OPCODE_BFI2
:
4311 case BRW_OPCODE_ADD
:
4312 case BRW_OPCODE_MUL
:
4313 case BRW_OPCODE_AVG
:
4314 case BRW_OPCODE_FRC
:
4315 case BRW_OPCODE_RNDU
:
4316 case BRW_OPCODE_RNDD
:
4317 case BRW_OPCODE_RNDE
:
4318 case BRW_OPCODE_RNDZ
:
4319 case BRW_OPCODE_LZD
:
4320 case BRW_OPCODE_FBH
:
4321 case BRW_OPCODE_FBL
:
4322 case BRW_OPCODE_CBIT
:
4323 case BRW_OPCODE_SAD2
:
4324 case BRW_OPCODE_MAD
:
4325 case BRW_OPCODE_LRP
:
4326 case SHADER_OPCODE_RCP
:
4327 case SHADER_OPCODE_RSQ
:
4328 case SHADER_OPCODE_SQRT
:
4329 case SHADER_OPCODE_EXP2
:
4330 case SHADER_OPCODE_LOG2
:
4331 case SHADER_OPCODE_POW
:
4332 case SHADER_OPCODE_INT_QUOTIENT
:
4333 case SHADER_OPCODE_INT_REMAINDER
:
4334 case SHADER_OPCODE_SIN
:
4335 case SHADER_OPCODE_COS
: {
4336 /* According to the PRMs:
4337 * "A. In Direct Addressing mode, a source cannot span more than 2
4338 * adjacent GRF registers.
4339 * B. A destination cannot span more than 2 adjacent GRF registers."
4341 * Look for the source or destination with the largest register region
4342 * which is the one that is going to limit the overal execution size of
4343 * the instruction due to this rule.
4345 unsigned reg_count
= inst
->regs_written
;
4347 for (unsigned i
= 0; i
< inst
->sources
; i
++)
4348 reg_count
= MAX2(reg_count
, (unsigned)inst
->regs_read(i
));
4350 /* Calculate the maximum execution size of the instruction based on the
4351 * factor by which it goes over the hardware limit of 2 GRFs.
4353 return inst
->exec_size
/ DIV_ROUND_UP(reg_count
, 2);
4355 case SHADER_OPCODE_MULH
:
4356 /* MULH is lowered to the MUL/MACH sequence using the accumulator, which
4357 * is 8-wide on Gen7+.
4359 return (devinfo
->gen
>= 7 ? 8 : inst
->exec_size
);
4361 case FS_OPCODE_FB_WRITE_LOGICAL
:
4362 /* Gen6 doesn't support SIMD16 depth writes but we cannot handle them
4365 assert(devinfo
->gen
!= 6 ||
4366 inst
->src
[FB_WRITE_LOGICAL_SRC_SRC_DEPTH
].file
== BAD_FILE
||
4367 inst
->exec_size
== 8);
4368 /* Dual-source FB writes are unsupported in SIMD16 mode. */
4369 return (inst
->src
[FB_WRITE_LOGICAL_SRC_COLOR1
].file
!= BAD_FILE
?
4370 8 : inst
->exec_size
);
4372 case SHADER_OPCODE_TXD_LOGICAL
:
4373 /* TXD is unsupported in SIMD16 mode. */
4376 case SHADER_OPCODE_TG4_OFFSET_LOGICAL
: {
4377 /* gather4_po_c is unsupported in SIMD16 mode. */
4378 const fs_reg
&shadow_c
= inst
->src
[1];
4379 return (shadow_c
.file
!= BAD_FILE
? 8 : inst
->exec_size
);
4381 case SHADER_OPCODE_TXL_LOGICAL
:
4382 case FS_OPCODE_TXB_LOGICAL
: {
4383 /* Gen4 doesn't have SIMD8 non-shadow-compare bias/LOD instructions, and
4384 * Gen4-6 can't support TXL and TXB with shadow comparison in SIMD16
4385 * mode because the message exceeds the maximum length of 11.
4387 const fs_reg
&shadow_c
= inst
->src
[1];
4388 if (devinfo
->gen
== 4 && shadow_c
.file
== BAD_FILE
)
4390 else if (devinfo
->gen
< 7 && shadow_c
.file
!= BAD_FILE
)
4393 return inst
->exec_size
;
4395 case SHADER_OPCODE_TXF_LOGICAL
:
4396 case SHADER_OPCODE_TXS_LOGICAL
:
4397 /* Gen4 doesn't have SIMD8 variants for the RESINFO and LD-with-LOD
4398 * messages. Use SIMD16 instead.
4400 if (devinfo
->gen
== 4)
4403 return inst
->exec_size
;
4405 case SHADER_OPCODE_TXF_CMS_W_LOGICAL
: {
4406 /* This opcode can take up to 6 arguments which means that in some
4407 * circumstances it can end up with a message that is too long in SIMD16
4410 const unsigned coord_components
= inst
->src
[8].ud
;
4411 /* First three arguments are the sample index and the two arguments for
4414 if ((coord_components
+ 3) * 2 > MAX_SAMPLER_MESSAGE_SIZE
)
4417 return inst
->exec_size
;
4420 case SHADER_OPCODE_TYPED_ATOMIC_LOGICAL
:
4421 case SHADER_OPCODE_TYPED_SURFACE_READ_LOGICAL
:
4422 case SHADER_OPCODE_TYPED_SURFACE_WRITE_LOGICAL
:
4426 return inst
->exec_size
;
4431 * The \p rows array of registers represents a \p num_rows by \p num_columns
4432 * matrix in row-major order, write it in column-major order into the register
4433 * passed as destination. \p stride gives the separation between matrix
4434 * elements in the input in fs_builder::dispatch_width() units.
4437 emit_transpose(const fs_builder
&bld
,
4438 const fs_reg
&dst
, const fs_reg
*rows
,
4439 unsigned num_rows
, unsigned num_columns
, unsigned stride
)
4441 fs_reg
*const components
= new fs_reg
[num_rows
* num_columns
];
4443 for (unsigned i
= 0; i
< num_columns
; ++i
) {
4444 for (unsigned j
= 0; j
< num_rows
; ++j
)
4445 components
[num_rows
* i
+ j
] = offset(rows
[j
], bld
, stride
* i
);
4448 bld
.LOAD_PAYLOAD(dst
, components
, num_rows
* num_columns
, 0);
4450 delete[] components
;
4454 fs_visitor::lower_simd_width()
4456 bool progress
= false;
4458 foreach_block_and_inst_safe(block
, fs_inst
, inst
, cfg
) {
4459 const unsigned lower_width
= get_lowered_simd_width(devinfo
, inst
);
4461 if (lower_width
!= inst
->exec_size
) {
4462 /* Builder matching the original instruction. We may also need to
4463 * emit an instruction of width larger than the original, set the
4464 * execution size of the builder to the highest of both for now so
4465 * we're sure that both cases can be handled.
4467 const fs_builder ibld
= bld
.at(block
, inst
)
4468 .exec_all(inst
->force_writemask_all
)
4469 .group(MAX2(inst
->exec_size
, lower_width
),
4470 inst
->force_sechalf
);
4472 /* Split the copies in chunks of the execution width of either the
4473 * original or the lowered instruction, whichever is lower.
4475 const unsigned copy_width
= MIN2(lower_width
, inst
->exec_size
);
4476 const unsigned n
= inst
->exec_size
/ copy_width
;
4477 const unsigned dst_size
= inst
->regs_written
* REG_SIZE
/
4478 inst
->dst
.component_size(inst
->exec_size
);
4481 assert(n
> 0 && n
<= ARRAY_SIZE(dsts
) &&
4482 !inst
->writes_accumulator
&& !inst
->mlen
);
4484 for (unsigned i
= 0; i
< n
; i
++) {
4485 /* Emit a copy of the original instruction with the lowered width.
4486 * If the EOT flag was set throw it away except for the last
4487 * instruction to avoid killing the thread prematurely.
4489 fs_inst split_inst
= *inst
;
4490 split_inst
.exec_size
= lower_width
;
4491 split_inst
.eot
= inst
->eot
&& i
== n
- 1;
4493 /* Select the correct channel enables for the i-th group, then
4494 * transform the sources and destination and emit the lowered
4497 const fs_builder lbld
= ibld
.group(lower_width
, i
);
4499 for (unsigned j
= 0; j
< inst
->sources
; j
++) {
4500 if (inst
->src
[j
].file
!= BAD_FILE
&&
4501 !is_uniform(inst
->src
[j
])) {
4502 /* Get the i-th copy_width-wide chunk of the source. */
4503 const fs_reg src
= horiz_offset(inst
->src
[j
], copy_width
* i
);
4504 const unsigned src_size
= inst
->components_read(j
);
4506 /* Use a trivial transposition to copy one every n
4507 * copy_width-wide components of the register into a
4508 * temporary passed as source to the lowered instruction.
4510 split_inst
.src
[j
] = lbld
.vgrf(inst
->src
[j
].type
, src_size
);
4511 emit_transpose(lbld
.group(copy_width
, 0),
4512 split_inst
.src
[j
], &src
, 1, src_size
, n
);
4516 if (inst
->regs_written
) {
4517 /* Allocate enough space to hold the result of the lowered
4518 * instruction and fix up the number of registers written.
4520 split_inst
.dst
= dsts
[i
] =
4521 lbld
.vgrf(inst
->dst
.type
, dst_size
);
4522 split_inst
.regs_written
=
4523 DIV_ROUND_UP(inst
->regs_written
* lower_width
,
4527 lbld
.emit(split_inst
);
4530 if (inst
->regs_written
) {
4531 /* Distance between useful channels in the temporaries, skipping
4532 * garbage if the lowered instruction is wider than the original.
4534 const unsigned m
= lower_width
/ copy_width
;
4536 /* Interleave the components of the result from the lowered
4537 * instructions. We need to set exec_all() when copying more than
4538 * one half per component, because LOAD_PAYLOAD (in terms of which
4539 * emit_transpose is implemented) can only use the same channel
4540 * enable signals for all of its non-header sources.
4542 emit_transpose(ibld
.exec_all(inst
->exec_size
> copy_width
)
4543 .group(copy_width
, 0),
4544 inst
->dst
, dsts
, n
, dst_size
, m
);
4547 inst
->remove(block
);
4553 invalidate_live_intervals();
4559 fs_visitor::dump_instructions()
4561 dump_instructions(NULL
);
4565 fs_visitor::dump_instructions(const char *name
)
4567 FILE *file
= stderr
;
4568 if (name
&& geteuid() != 0) {
4569 file
= fopen(name
, "w");
4575 calculate_register_pressure();
4576 int ip
= 0, max_pressure
= 0;
4577 foreach_block_and_inst(block
, backend_instruction
, inst
, cfg
) {
4578 max_pressure
= MAX2(max_pressure
, regs_live_at_ip
[ip
]);
4579 fprintf(file
, "{%3d} %4d: ", regs_live_at_ip
[ip
], ip
);
4580 dump_instruction(inst
, file
);
4583 fprintf(file
, "Maximum %3d registers live at once.\n", max_pressure
);
4586 foreach_in_list(backend_instruction
, inst
, &instructions
) {
4587 fprintf(file
, "%4d: ", ip
++);
4588 dump_instruction(inst
, file
);
4592 if (file
!= stderr
) {
4598 fs_visitor::dump_instruction(backend_instruction
*be_inst
)
4600 dump_instruction(be_inst
, stderr
);
4604 fs_visitor::dump_instruction(backend_instruction
*be_inst
, FILE *file
)
4606 fs_inst
*inst
= (fs_inst
*)be_inst
;
4608 if (inst
->predicate
) {
4609 fprintf(file
, "(%cf0.%d) ",
4610 inst
->predicate_inverse
? '-' : '+',
4614 fprintf(file
, "%s", brw_instruction_name(inst
->opcode
));
4616 fprintf(file
, ".sat");
4617 if (inst
->conditional_mod
) {
4618 fprintf(file
, "%s", conditional_modifier
[inst
->conditional_mod
]);
4619 if (!inst
->predicate
&&
4620 (devinfo
->gen
< 5 || (inst
->opcode
!= BRW_OPCODE_SEL
&&
4621 inst
->opcode
!= BRW_OPCODE_IF
&&
4622 inst
->opcode
!= BRW_OPCODE_WHILE
))) {
4623 fprintf(file
, ".f0.%d", inst
->flag_subreg
);
4626 fprintf(file
, "(%d) ", inst
->exec_size
);
4629 fprintf(file
, "(mlen: %d) ", inst
->mlen
);
4632 switch (inst
->dst
.file
) {
4634 fprintf(file
, "vgrf%d", inst
->dst
.nr
);
4635 if (alloc
.sizes
[inst
->dst
.nr
] != inst
->regs_written
||
4636 inst
->dst
.subreg_offset
)
4637 fprintf(file
, "+%d.%d",
4638 inst
->dst
.reg_offset
, inst
->dst
.subreg_offset
);
4641 fprintf(file
, "g%d", inst
->dst
.nr
);
4644 fprintf(file
, "m%d", inst
->dst
.nr
);
4647 fprintf(file
, "(null)");
4650 fprintf(file
, "***u%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4653 fprintf(file
, "***attr%d***", inst
->dst
.nr
+ inst
->dst
.reg_offset
);
4656 switch (inst
->dst
.nr
) {
4658 fprintf(file
, "null");
4660 case BRW_ARF_ADDRESS
:
4661 fprintf(file
, "a0.%d", inst
->dst
.subnr
);
4663 case BRW_ARF_ACCUMULATOR
:
4664 fprintf(file
, "acc%d", inst
->dst
.subnr
);
4667 fprintf(file
, "f%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4670 fprintf(file
, "arf%d.%d", inst
->dst
.nr
& 0xf, inst
->dst
.subnr
);
4673 if (inst
->dst
.subnr
)
4674 fprintf(file
, "+%d", inst
->dst
.subnr
);
4677 unreachable("not reached");
4679 if (inst
->dst
.stride
!= 1)
4680 fprintf(file
, "<%u>", inst
->dst
.stride
);
4681 fprintf(file
, ":%s, ", brw_reg_type_letters(inst
->dst
.type
));
4683 for (int i
= 0; i
< inst
->sources
; i
++) {
4684 if (inst
->src
[i
].negate
)
4686 if (inst
->src
[i
].abs
)
4688 switch (inst
->src
[i
].file
) {
4690 fprintf(file
, "vgrf%d", inst
->src
[i
].nr
);
4691 if (alloc
.sizes
[inst
->src
[i
].nr
] != (unsigned)inst
->regs_read(i
) ||
4692 inst
->src
[i
].subreg_offset
)
4693 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4694 inst
->src
[i
].subreg_offset
);
4697 fprintf(file
, "g%d", inst
->src
[i
].nr
);
4700 fprintf(file
, "***m%d***", inst
->src
[i
].nr
);
4703 fprintf(file
, "attr%d+%d", inst
->src
[i
].nr
, inst
->src
[i
].reg_offset
);
4706 fprintf(file
, "u%d", inst
->src
[i
].nr
+ inst
->src
[i
].reg_offset
);
4707 if (inst
->src
[i
].reladdr
) {
4708 fprintf(file
, "+reladdr");
4709 } else if (inst
->src
[i
].subreg_offset
) {
4710 fprintf(file
, "+%d.%d", inst
->src
[i
].reg_offset
,
4711 inst
->src
[i
].subreg_offset
);
4715 fprintf(file
, "(null)");
4718 switch (inst
->src
[i
].type
) {
4719 case BRW_REGISTER_TYPE_F
:
4720 fprintf(file
, "%ff", inst
->src
[i
].f
);
4722 case BRW_REGISTER_TYPE_W
:
4723 case BRW_REGISTER_TYPE_D
:
4724 fprintf(file
, "%dd", inst
->src
[i
].d
);
4726 case BRW_REGISTER_TYPE_UW
:
4727 case BRW_REGISTER_TYPE_UD
:
4728 fprintf(file
, "%uu", inst
->src
[i
].ud
);
4730 case BRW_REGISTER_TYPE_VF
:
4731 fprintf(file
, "[%-gF, %-gF, %-gF, %-gF]",
4732 brw_vf_to_float((inst
->src
[i
].ud
>> 0) & 0xff),
4733 brw_vf_to_float((inst
->src
[i
].ud
>> 8) & 0xff),
4734 brw_vf_to_float((inst
->src
[i
].ud
>> 16) & 0xff),
4735 brw_vf_to_float((inst
->src
[i
].ud
>> 24) & 0xff));
4738 fprintf(file
, "???");
4743 switch (inst
->src
[i
].nr
) {
4745 fprintf(file
, "null");
4747 case BRW_ARF_ADDRESS
:
4748 fprintf(file
, "a0.%d", inst
->src
[i
].subnr
);
4750 case BRW_ARF_ACCUMULATOR
:
4751 fprintf(file
, "acc%d", inst
->src
[i
].subnr
);
4754 fprintf(file
, "f%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4757 fprintf(file
, "arf%d.%d", inst
->src
[i
].nr
& 0xf, inst
->src
[i
].subnr
);
4760 if (inst
->src
[i
].subnr
)
4761 fprintf(file
, "+%d", inst
->src
[i
].subnr
);
4764 if (inst
->src
[i
].abs
)
4767 if (inst
->src
[i
].file
!= IMM
) {
4769 if (inst
->src
[i
].file
== ARF
|| inst
->src
[i
].file
== FIXED_GRF
) {
4770 unsigned hstride
= inst
->src
[i
].hstride
;
4771 stride
= (hstride
== 0 ? 0 : (1 << (hstride
- 1)));
4773 stride
= inst
->src
[i
].stride
;
4776 fprintf(file
, "<%u>", stride
);
4778 fprintf(file
, ":%s", brw_reg_type_letters(inst
->src
[i
].type
));
4781 if (i
< inst
->sources
- 1 && inst
->src
[i
+ 1].file
!= BAD_FILE
)
4782 fprintf(file
, ", ");
4787 if (inst
->force_writemask_all
)
4788 fprintf(file
, "NoMask ");
4790 if (dispatch_width
== 16 && inst
->exec_size
== 8) {
4791 if (inst
->force_sechalf
)
4792 fprintf(file
, "2ndhalf ");
4794 fprintf(file
, "1sthalf ");
4797 fprintf(file
, "\n");
4801 * Possibly returns an instruction that set up @param reg.
4803 * Sometimes we want to take the result of some expression/variable
4804 * dereference tree and rewrite the instruction generating the result
4805 * of the tree. When processing the tree, we know that the
4806 * instructions generated are all writing temporaries that are dead
4807 * outside of this tree. So, if we have some instructions that write
4808 * a temporary, we're free to point that temp write somewhere else.
4810 * Note that this doesn't guarantee that the instruction generated
4811 * only reg -- it might be the size=4 destination of a texture instruction.
4814 fs_visitor::get_instruction_generating_reg(fs_inst
*start
,
4819 end
->is_partial_write() ||
4821 !reg
.equals(end
->dst
)) {
4829 fs_visitor::setup_payload_gen6()
4832 (nir
->info
.inputs_read
& (1 << VARYING_SLOT_POS
)) != 0;
4833 unsigned barycentric_interp_modes
=
4834 (stage
== MESA_SHADER_FRAGMENT
) ?
4835 ((brw_wm_prog_data
*) this->prog_data
)->barycentric_interp_modes
: 0;
4837 assert(devinfo
->gen
>= 6);
4839 /* R0-1: masks, pixel X/Y coordinates. */
4840 payload
.num_regs
= 2;
4841 /* R2: only for 32-pixel dispatch.*/
4843 /* R3-26: barycentric interpolation coordinates. These appear in the
4844 * same order that they appear in the brw_wm_barycentric_interp_mode
4845 * enum. Each set of coordinates occupies 2 registers if dispatch width
4846 * == 8 and 4 registers if dispatch width == 16. Coordinates only
4847 * appear if they were enabled using the "Barycentric Interpolation
4848 * Mode" bits in WM_STATE.
4850 for (int i
= 0; i
< BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT
; ++i
) {
4851 if (barycentric_interp_modes
& (1 << i
)) {
4852 payload
.barycentric_coord_reg
[i
] = payload
.num_regs
;
4853 payload
.num_regs
+= 2;
4854 if (dispatch_width
== 16) {
4855 payload
.num_regs
+= 2;
4860 /* R27: interpolated depth if uses source depth */
4862 payload
.source_depth_reg
= payload
.num_regs
;
4864 if (dispatch_width
== 16) {
4865 /* R28: interpolated depth if not SIMD8. */
4869 /* R29: interpolated W set if GEN6_WM_USES_SOURCE_W. */
4871 payload
.source_w_reg
= payload
.num_regs
;
4873 if (dispatch_width
== 16) {
4874 /* R30: interpolated W if not SIMD8. */
4879 if (stage
== MESA_SHADER_FRAGMENT
) {
4880 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
4881 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
4882 prog_data
->uses_pos_offset
= key
->compute_pos_offset
;
4883 /* R31: MSAA position offsets. */
4884 if (prog_data
->uses_pos_offset
) {
4885 payload
.sample_pos_reg
= payload
.num_regs
;
4890 /* R32: MSAA input coverage mask */
4891 if (nir
->info
.system_values_read
& SYSTEM_BIT_SAMPLE_MASK_IN
) {
4892 assert(devinfo
->gen
>= 7);
4893 payload
.sample_mask_in_reg
= payload
.num_regs
;
4895 if (dispatch_width
== 16) {
4896 /* R33: input coverage mask if not SIMD8. */
4901 /* R34-: bary for 32-pixel. */
4902 /* R58-59: interp W for 32-pixel. */
4904 if (nir
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
4905 source_depth_to_render_target
= true;
4910 fs_visitor::setup_vs_payload()
4912 /* R0: thread header, R1: urb handles */
4913 payload
.num_regs
= 2;
4917 * We are building the local ID push constant data using the simplest possible
4918 * method. We simply push the local IDs directly as they should appear in the
4919 * registers for the uvec3 gl_LocalInvocationID variable.
4921 * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
4922 * registers worth of push constant space.
4924 * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
4925 * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
4928 * FINISHME: There are a few easy optimizations to consider.
4930 * 1. If gl_WorkGroupSize x, y or z is 1, we can just use zero, and there is
4931 * no need for using push constant space for that dimension.
4933 * 2. Since GL_MAX_COMPUTE_WORK_GROUP_SIZE is currently 1024 or less, we can
4934 * easily use 16-bit words rather than 32-bit dwords in the push constant
4937 * 3. If gl_WorkGroupSize x, y or z is small, then we can use bytes for
4938 * conveying the data, and thereby reduce push constant usage.
4942 fs_visitor::setup_gs_payload()
4944 assert(stage
== MESA_SHADER_GEOMETRY
);
4946 struct brw_gs_prog_data
*gs_prog_data
=
4947 (struct brw_gs_prog_data
*) prog_data
;
4948 struct brw_vue_prog_data
*vue_prog_data
=
4949 (struct brw_vue_prog_data
*) prog_data
;
4951 /* R0: thread header, R1: output URB handles */
4952 payload
.num_regs
= 2;
4954 if (gs_prog_data
->include_primitive_id
) {
4955 /* R2: Primitive ID 0..7 */
4959 /* Use a maximum of 32 registers for push-model inputs. */
4960 const unsigned max_push_components
= 32;
4962 /* If pushing our inputs would take too many registers, reduce the URB read
4963 * length (which is in HWords, or 8 registers), and resort to pulling.
4965 * Note that the GS reads <URB Read Length> HWords for every vertex - so we
4966 * have to multiply by VerticesIn to obtain the total storage requirement.
4968 if (8 * vue_prog_data
->urb_read_length
* nir
->info
.gs
.vertices_in
>
4969 max_push_components
) {
4970 gs_prog_data
->base
.include_vue_handles
= true;
4972 /* R3..RN: ICP Handles for each incoming vertex (when using pull model) */
4973 payload
.num_regs
+= nir
->info
.gs
.vertices_in
;
4975 vue_prog_data
->urb_read_length
=
4976 ROUND_DOWN_TO(max_push_components
/ nir
->info
.gs
.vertices_in
, 8) / 8;
4981 fs_visitor::setup_cs_payload()
4983 assert(devinfo
->gen
>= 7);
4984 brw_cs_prog_data
*prog_data
= (brw_cs_prog_data
*) this->prog_data
;
4986 payload
.num_regs
= 1;
4988 if (nir
->info
.system_values_read
& SYSTEM_BIT_LOCAL_INVOCATION_ID
) {
4989 prog_data
->local_invocation_id_regs
= dispatch_width
* 3 / 8;
4990 payload
.local_invocation_id_reg
= payload
.num_regs
;
4991 payload
.num_regs
+= prog_data
->local_invocation_id_regs
;
4996 fs_visitor::calculate_register_pressure()
4998 invalidate_live_intervals();
4999 calculate_live_intervals();
5001 unsigned num_instructions
= 0;
5002 foreach_block(block
, cfg
)
5003 num_instructions
+= block
->instructions
.length();
5005 regs_live_at_ip
= rzalloc_array(mem_ctx
, int, num_instructions
);
5007 for (unsigned reg
= 0; reg
< alloc
.count
; reg
++) {
5008 for (int ip
= virtual_grf_start
[reg
]; ip
<= virtual_grf_end
[reg
]; ip
++)
5009 regs_live_at_ip
[ip
] += alloc
.sizes
[reg
];
5014 fs_visitor::optimize()
5016 /* Start by validating the shader we currently have. */
5019 /* bld is the common builder object pointing at the end of the program we
5020 * used to translate it into i965 IR. For the optimization and lowering
5021 * passes coming next, any code added after the end of the program without
5022 * having explicitly called fs_builder::at() clearly points at a mistake.
5023 * Ideally optimization passes wouldn't be part of the visitor so they
5024 * wouldn't have access to bld at all, but they do, so just in case some
5025 * pass forgets to ask for a location explicitly set it to NULL here to
5026 * make it trip. The dispatch width is initialized to a bogus value to
5027 * make sure that optimizations set the execution controls explicitly to
5028 * match the code they are manipulating instead of relying on the defaults.
5030 bld
= fs_builder(this, 64);
5032 assign_constant_locations();
5033 demote_pull_constants();
5037 split_virtual_grfs();
5040 #define OPT(pass, args...) ({ \
5042 bool this_progress = pass(args); \
5044 if (unlikely(INTEL_DEBUG & DEBUG_OPTIMIZER) && this_progress) { \
5045 char filename[64]; \
5046 snprintf(filename, 64, "%s%d-%s-%02d-%02d-" #pass, \
5047 stage_abbrev, dispatch_width, nir->info.name, iteration, pass_num); \
5049 backend_shader::dump_instructions(filename); \
5054 progress = progress || this_progress; \
5058 if (unlikely(INTEL_DEBUG
& DEBUG_OPTIMIZER
)) {
5060 snprintf(filename
, 64, "%s%d-%s-00-start",
5061 stage_abbrev
, dispatch_width
, nir
->info
.name
);
5063 backend_shader::dump_instructions(filename
);
5066 bool progress
= false;
5070 OPT(lower_simd_width
);
5071 OPT(lower_logical_sends
);
5078 OPT(remove_duplicate_mrf_writes
);
5082 OPT(opt_copy_propagate
);
5083 OPT(opt_predicated_break
, this);
5084 OPT(opt_cmod_propagation
);
5085 OPT(dead_code_eliminate
);
5086 OPT(opt_peephole_sel
);
5087 OPT(dead_control_flow_eliminate
, this);
5088 OPT(opt_register_renaming
);
5089 OPT(opt_redundant_discard_jumps
);
5090 OPT(opt_saturate_propagation
);
5091 OPT(opt_zero_samples
);
5092 OPT(register_coalesce
);
5093 OPT(compute_to_mrf
);
5094 OPT(eliminate_find_live_channel
);
5096 OPT(compact_virtual_grfs
);
5101 OPT(opt_sampler_eot
);
5103 if (OPT(lower_load_payload
)) {
5104 split_virtual_grfs();
5105 OPT(register_coalesce
);
5106 OPT(compute_to_mrf
);
5107 OPT(dead_code_eliminate
);
5110 OPT(opt_combine_constants
);
5111 OPT(lower_integer_multiplication
);
5113 lower_uniform_pull_constant_loads();
5119 * Three source instruction must have a GRF/MRF destination register.
5120 * ARF NULL is not allowed. Fix that up by allocating a temporary GRF.
5123 fs_visitor::fixup_3src_null_dest()
5125 foreach_block_and_inst_safe (block
, fs_inst
, inst
, cfg
) {
5126 if (inst
->is_3src() && inst
->dst
.is_null()) {
5127 inst
->dst
= fs_reg(VGRF
, alloc
.allocate(dispatch_width
/ 8),
5134 fs_visitor::allocate_registers()
5136 bool allocated_without_spills
;
5138 static const enum instruction_scheduler_mode pre_modes
[] = {
5140 SCHEDULE_PRE_NON_LIFO
,
5144 /* Try each scheduling heuristic to see if it can successfully register
5145 * allocate without spilling. They should be ordered by decreasing
5146 * performance but increasing likelihood of allocating.
5148 for (unsigned i
= 0; i
< ARRAY_SIZE(pre_modes
); i
++) {
5149 schedule_instructions(pre_modes
[i
]);
5152 assign_regs_trivial();
5153 allocated_without_spills
= true;
5155 allocated_without_spills
= assign_regs(false);
5157 if (allocated_without_spills
)
5161 if (!allocated_without_spills
) {
5162 /* We assume that any spilling is worse than just dropping back to
5163 * SIMD8. There's probably actually some intermediate point where
5164 * SIMD16 with a couple of spills is still better.
5166 if (dispatch_width
== 16) {
5167 fail("Failure to register allocate. Reduce number of "
5168 "live scalar values to avoid this.");
5170 compiler
->shader_perf_log(log_data
,
5171 "%s shader triggered register spilling. "
5172 "Try reducing the number of live scalar "
5173 "values to improve performance.\n",
5177 /* Since we're out of heuristics, just go spill registers until we
5178 * get an allocation.
5180 while (!assign_regs(true)) {
5186 /* This must come after all optimization and register allocation, since
5187 * it inserts dead code that happens to have side effects, and it does
5188 * so based on the actual physical registers in use.
5190 insert_gen4_send_dependency_workarounds();
5195 schedule_instructions(SCHEDULE_POST
);
5197 if (last_scratch
> 0)
5198 prog_data
->total_scratch
= brw_get_scratch_size(last_scratch
);
5202 fs_visitor::run_vs(gl_clip_plane
*clip_planes
)
5204 assert(stage
== MESA_SHADER_VERTEX
);
5208 if (shader_time_index
>= 0)
5209 emit_shader_time_begin();
5216 compute_clip_distance(clip_planes
);
5220 if (shader_time_index
>= 0)
5221 emit_shader_time_end();
5227 assign_curb_setup();
5228 assign_vs_urb_setup();
5230 fixup_3src_null_dest();
5231 allocate_registers();
5237 fs_visitor::run_gs()
5239 assert(stage
== MESA_SHADER_GEOMETRY
);
5243 this->final_gs_vertex_count
= vgrf(glsl_type::uint_type
);
5245 if (gs_compile
->control_data_header_size_bits
> 0) {
5246 /* Create a VGRF to store accumulated control data bits. */
5247 this->control_data_bits
= vgrf(glsl_type::uint_type
);
5249 /* If we're outputting more than 32 control data bits, then EmitVertex()
5250 * will set control_data_bits to 0 after emitting the first vertex.
5251 * Otherwise, we need to initialize it to 0 here.
5253 if (gs_compile
->control_data_header_size_bits
<= 32) {
5254 const fs_builder abld
= bld
.annotate("initialize control data bits");
5255 abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
5259 if (shader_time_index
>= 0)
5260 emit_shader_time_begin();
5264 emit_gs_thread_end();
5266 if (shader_time_index
>= 0)
5267 emit_shader_time_end();
5276 assign_curb_setup();
5277 assign_gs_urb_setup();
5279 fixup_3src_null_dest();
5280 allocate_registers();
5286 fs_visitor::run_fs(bool do_rep_send
)
5288 brw_wm_prog_data
*wm_prog_data
= (brw_wm_prog_data
*) this->prog_data
;
5289 brw_wm_prog_key
*wm_key
= (brw_wm_prog_key
*) this->key
;
5291 assert(stage
== MESA_SHADER_FRAGMENT
);
5293 if (devinfo
->gen
>= 6)
5294 setup_payload_gen6();
5296 setup_payload_gen4();
5300 } else if (do_rep_send
) {
5301 assert(dispatch_width
== 16);
5302 emit_repclear_shader();
5304 if (shader_time_index
>= 0)
5305 emit_shader_time_begin();
5307 calculate_urb_setup();
5308 if (nir
->info
.inputs_read
> 0) {
5309 if (devinfo
->gen
< 6)
5310 emit_interpolation_setup_gen4();
5312 emit_interpolation_setup_gen6();
5315 /* We handle discards by keeping track of the still-live pixels in f0.1.
5316 * Initialize it with the dispatched pixels.
5318 if (wm_prog_data
->uses_kill
) {
5319 fs_inst
*discard_init
= bld
.emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS
);
5320 discard_init
->flag_subreg
= 1;
5323 /* Generate FS IR for main(). (the visitor only descends into
5324 * functions called "main").
5331 if (wm_prog_data
->uses_kill
)
5332 bld
.emit(FS_OPCODE_PLACEHOLDER_HALT
);
5334 if (wm_key
->alpha_test_func
)
5339 if (shader_time_index
>= 0)
5340 emit_shader_time_end();
5346 assign_curb_setup();
5349 fixup_3src_null_dest();
5350 allocate_registers();
5356 if (dispatch_width
== 8)
5357 wm_prog_data
->reg_blocks
= brw_register_blocks(grf_used
);
5359 wm_prog_data
->reg_blocks_16
= brw_register_blocks(grf_used
);
5365 fs_visitor::run_cs()
5367 assert(stage
== MESA_SHADER_COMPUTE
);
5371 if (shader_time_index
>= 0)
5372 emit_shader_time_begin();
5379 emit_cs_terminate();
5381 if (shader_time_index
>= 0)
5382 emit_shader_time_end();
5388 assign_curb_setup();
5390 fixup_3src_null_dest();
5391 allocate_registers();
5400 * Return a bitfield where bit n is set if barycentric interpolation mode n
5401 * (see enum brw_wm_barycentric_interp_mode) is needed by the fragment shader.
5404 brw_compute_barycentric_interp_modes(const struct brw_device_info
*devinfo
,
5405 bool shade_model_flat
,
5406 bool persample_shading
,
5407 const nir_shader
*shader
)
5409 unsigned barycentric_interp_modes
= 0;
5411 nir_foreach_variable(var
, &shader
->inputs
) {
5412 enum glsl_interp_qualifier interp_qualifier
=
5413 (enum glsl_interp_qualifier
)var
->data
.interpolation
;
5414 bool is_centroid
= var
->data
.centroid
&& !persample_shading
;
5415 bool is_sample
= var
->data
.sample
|| persample_shading
;
5416 bool is_gl_Color
= (var
->data
.location
== VARYING_SLOT_COL0
) ||
5417 (var
->data
.location
== VARYING_SLOT_COL1
);
5419 /* Ignore WPOS and FACE, because they don't require interpolation. */
5420 if (var
->data
.location
== VARYING_SLOT_POS
||
5421 var
->data
.location
== VARYING_SLOT_FACE
)
5424 /* Determine the set (or sets) of barycentric coordinates needed to
5425 * interpolate this variable. Note that when
5426 * brw->needs_unlit_centroid_workaround is set, centroid interpolation
5427 * uses PIXEL interpolation for unlit pixels and CENTROID interpolation
5428 * for lit pixels, so we need both sets of barycentric coordinates.
5430 if (interp_qualifier
== INTERP_QUALIFIER_NOPERSPECTIVE
) {
5432 barycentric_interp_modes
|=
5433 1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC
;
5434 } else if (is_sample
) {
5435 barycentric_interp_modes
|=
5436 1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC
;
5438 if ((!is_centroid
&& !is_sample
) ||
5439 devinfo
->needs_unlit_centroid_workaround
) {
5440 barycentric_interp_modes
|=
5441 1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC
;
5443 } else if (interp_qualifier
== INTERP_QUALIFIER_SMOOTH
||
5444 (!(shade_model_flat
&& is_gl_Color
) &&
5445 interp_qualifier
== INTERP_QUALIFIER_NONE
)) {
5447 barycentric_interp_modes
|=
5448 1 << BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC
;
5449 } else if (is_sample
) {
5450 barycentric_interp_modes
|=
5451 1 << BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC
;
5453 if ((!is_centroid
&& !is_sample
) ||
5454 devinfo
->needs_unlit_centroid_workaround
) {
5455 barycentric_interp_modes
|=
5456 1 << BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC
;
5461 return barycentric_interp_modes
;
5465 computed_depth_mode(const nir_shader
*shader
)
5467 if (shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_DEPTH
)) {
5468 switch (shader
->info
.fs
.depth_layout
) {
5469 case FRAG_DEPTH_LAYOUT_NONE
:
5470 case FRAG_DEPTH_LAYOUT_ANY
:
5471 return BRW_PSCDEPTH_ON
;
5472 case FRAG_DEPTH_LAYOUT_GREATER
:
5473 return BRW_PSCDEPTH_ON_GE
;
5474 case FRAG_DEPTH_LAYOUT_LESS
:
5475 return BRW_PSCDEPTH_ON_LE
;
5476 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
5477 return BRW_PSCDEPTH_OFF
;
5480 return BRW_PSCDEPTH_OFF
;
5484 brw_compile_fs(const struct brw_compiler
*compiler
, void *log_data
,
5486 const struct brw_wm_prog_key
*key
,
5487 struct brw_wm_prog_data
*prog_data
,
5488 const nir_shader
*src_shader
,
5489 struct gl_program
*prog
,
5490 int shader_time_index8
, int shader_time_index16
,
5492 unsigned *final_assembly_size
,
5495 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5496 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5498 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5500 /* key->alpha_test_func means simulating alpha testing via discards,
5501 * so the shader definitely kills pixels.
5503 prog_data
->uses_kill
= shader
->info
.fs
.uses_discard
|| key
->alpha_test_func
;
5504 prog_data
->uses_omask
=
5505 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK
);
5506 prog_data
->computed_depth_mode
= computed_depth_mode(shader
);
5507 prog_data
->computed_stencil
=
5508 shader
->info
.outputs_written
& BITFIELD64_BIT(FRAG_RESULT_STENCIL
);
5510 prog_data
->early_fragment_tests
= shader
->info
.fs
.early_fragment_tests
;
5512 prog_data
->barycentric_interp_modes
=
5513 brw_compute_barycentric_interp_modes(compiler
->devinfo
,
5515 key
->persample_shading
,
5518 fs_visitor
v(compiler
, log_data
, mem_ctx
, key
,
5519 &prog_data
->base
, prog
, shader
, 8,
5520 shader_time_index8
);
5521 if (!v
.run_fs(false /* do_rep_send */)) {
5523 *error_str
= ralloc_strdup(mem_ctx
, v
.fail_msg
);
5528 cfg_t
*simd16_cfg
= NULL
;
5529 fs_visitor
v2(compiler
, log_data
, mem_ctx
, key
,
5530 &prog_data
->base
, prog
, shader
, 16,
5531 shader_time_index16
);
5532 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
) || use_rep_send
)) {
5533 if (!v
.simd16_unsupported
) {
5534 /* Try a SIMD16 compile */
5535 v2
.import_uniforms(&v
);
5536 if (!v2
.run_fs(use_rep_send
)) {
5537 compiler
->shader_perf_log(log_data
,
5538 "SIMD16 shader failed to compile: %s",
5541 simd16_cfg
= v2
.cfg
;
5547 int no_simd8
= (INTEL_DEBUG
& DEBUG_NO8
) || use_rep_send
;
5548 if ((no_simd8
|| compiler
->devinfo
->gen
< 5) && simd16_cfg
) {
5550 prog_data
->no_8
= true;
5553 prog_data
->no_8
= false;
5556 fs_generator
g(compiler
, log_data
, mem_ctx
, (void *) key
, &prog_data
->base
,
5557 v
.promoted_constants
, v
.runtime_check_aads_emit
, "FS");
5559 if (unlikely(INTEL_DEBUG
& DEBUG_WM
)) {
5560 g
.enable_debug(ralloc_asprintf(mem_ctx
, "%s fragment shader %s",
5561 shader
->info
.label
? shader
->info
.label
:
5563 shader
->info
.name
));
5567 g
.generate_code(simd8_cfg
, 8);
5569 prog_data
->prog_offset_16
= g
.generate_code(simd16_cfg
, 16);
5571 return g
.get_assembly(final_assembly_size
);
5575 fs_visitor::emit_cs_local_invocation_id_setup()
5577 assert(stage
== MESA_SHADER_COMPUTE
);
5579 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5581 struct brw_reg src
=
5582 brw_vec8_grf(payload
.local_invocation_id_reg
, 0);
5583 src
= retype(src
, BRW_REGISTER_TYPE_UD
);
5585 src
.nr
+= dispatch_width
/ 8;
5586 bld
.MOV(offset(*reg
, bld
, 1), src
);
5587 src
.nr
+= dispatch_width
/ 8;
5588 bld
.MOV(offset(*reg
, bld
, 2), src
);
5594 fs_visitor::emit_cs_work_group_id_setup()
5596 assert(stage
== MESA_SHADER_COMPUTE
);
5598 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(vgrf(glsl_type::uvec3_type
));
5600 struct brw_reg
r0_1(retype(brw_vec1_grf(0, 1), BRW_REGISTER_TYPE_UD
));
5601 struct brw_reg
r0_6(retype(brw_vec1_grf(0, 6), BRW_REGISTER_TYPE_UD
));
5602 struct brw_reg
r0_7(retype(brw_vec1_grf(0, 7), BRW_REGISTER_TYPE_UD
));
5604 bld
.MOV(*reg
, r0_1
);
5605 bld
.MOV(offset(*reg
, bld
, 1), r0_6
);
5606 bld
.MOV(offset(*reg
, bld
, 2), r0_7
);
5612 brw_compile_cs(const struct brw_compiler
*compiler
, void *log_data
,
5614 const struct brw_cs_prog_key
*key
,
5615 struct brw_cs_prog_data
*prog_data
,
5616 const nir_shader
*src_shader
,
5617 int shader_time_index
,
5618 unsigned *final_assembly_size
,
5621 nir_shader
*shader
= nir_shader_clone(mem_ctx
, src_shader
);
5622 shader
= brw_nir_apply_sampler_key(shader
, compiler
->devinfo
, &key
->tex
,
5624 shader
= brw_postprocess_nir(shader
, compiler
->devinfo
, true);
5626 prog_data
->local_size
[0] = shader
->info
.cs
.local_size
[0];
5627 prog_data
->local_size
[1] = shader
->info
.cs
.local_size
[1];
5628 prog_data
->local_size
[2] = shader
->info
.cs
.local_size
[2];
5629 unsigned local_workgroup_size
=
5630 shader
->info
.cs
.local_size
[0] * shader
->info
.cs
.local_size
[1] *
5631 shader
->info
.cs
.local_size
[2];
5633 unsigned max_cs_threads
= compiler
->devinfo
->max_cs_threads
;
5636 const char *fail_msg
= NULL
;
5638 /* Now the main event: Visit the shader IR and generate our CS IR for it.
5640 fs_visitor
v8(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5641 NULL
, /* Never used in core profile */
5642 shader
, 8, shader_time_index
);
5644 fail_msg
= v8
.fail_msg
;
5645 } else if (local_workgroup_size
<= 8 * max_cs_threads
) {
5647 prog_data
->simd_size
= 8;
5650 fs_visitor
v16(compiler
, log_data
, mem_ctx
, key
, &prog_data
->base
,
5651 NULL
, /* Never used in core profile */
5652 shader
, 16, shader_time_index
);
5653 if (likely(!(INTEL_DEBUG
& DEBUG_NO16
)) &&
5654 !fail_msg
&& !v8
.simd16_unsupported
&&
5655 local_workgroup_size
<= 16 * max_cs_threads
) {
5656 /* Try a SIMD16 compile */
5657 v16
.import_uniforms(&v8
);
5658 if (!v16
.run_cs()) {
5659 compiler
->shader_perf_log(log_data
,
5660 "SIMD16 shader failed to compile: %s",
5664 "Couldn't generate SIMD16 program and not "
5665 "enough threads for SIMD8";
5669 prog_data
->simd_size
= 16;
5673 if (unlikely(cfg
== NULL
)) {
5676 *error_str
= ralloc_strdup(mem_ctx
, fail_msg
);
5681 fs_generator
g(compiler
, log_data
, mem_ctx
, (void*) key
, &prog_data
->base
,
5682 v8
.promoted_constants
, v8
.runtime_check_aads_emit
, "CS");
5683 if (INTEL_DEBUG
& DEBUG_CS
) {
5684 char *name
= ralloc_asprintf(mem_ctx
, "%s compute shader %s",
5685 shader
->info
.label
? shader
->info
.label
:
5688 g
.enable_debug(name
);
5691 g
.generate_code(cfg
, prog_data
->simd_size
);
5693 return g
.get_assembly(final_assembly_size
);