2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
31 /* Evil hack for using libdrm in a c++ compiler. */
34 #include "intel_bufmgr.h"
37 #include "main/macros.h"
38 #include "main/shaderobj.h"
39 #include "program/prog_parameter.h"
40 #include "program/prog_print.h"
41 #include "program/prog_optimize.h"
42 #include "program/hash_table.h"
43 #include "brw_context.h"
48 #include "../glsl/glsl_types.h"
49 #include "../glsl/ir_optimization.h"
50 #include "../glsl/ir_print_visitor.h"
53 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
54 GRF
= BRW_GENERAL_REGISTER_FILE
,
55 MRF
= BRW_MESSAGE_REGISTER_FILE
,
56 IMM
= BRW_IMMEDIATE_VALUE
,
57 FIXED_HW_REG
, /* a struct brw_reg */
58 UNIFORM
, /* prog_data->params[hw_reg] */
63 FS_OPCODE_FB_WRITE
= 256,
77 static int using_new_fs
= -1;
80 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
82 struct brw_shader
*shader
;
84 shader
= talloc_zero(NULL
, struct brw_shader
);
86 shader
->base
.Type
= type
;
87 shader
->base
.Name
= name
;
88 _mesa_init_shader(ctx
, &shader
->base
);
94 struct gl_shader_program
*
95 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
97 struct brw_shader_program
*prog
;
98 prog
= talloc_zero(NULL
, struct brw_shader_program
);
100 prog
->base
.Name
= name
;
101 _mesa_init_shader_program(ctx
, &prog
->base
);
107 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
109 if (!_mesa_ir_compile_shader(ctx
, shader
))
116 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
118 if (using_new_fs
== -1)
119 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
121 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
122 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
124 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
125 void *mem_ctx
= talloc_new(NULL
);
129 talloc_free(shader
->ir
);
130 shader
->ir
= new(shader
) exec_list
;
131 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
133 do_mat_op_to_vec(shader
->ir
);
134 do_div_to_mul_rcp(shader
->ir
);
135 do_sub_to_add_neg(shader
->ir
);
136 do_explog_to_explog2(shader
->ir
);
138 brw_do_channel_expressions(shader
->ir
);
139 brw_do_vector_splitting(shader
->ir
);
144 progress
= do_common_optimization(shader
->ir
, true) || progress
;
147 validate_ir_tree(shader
->ir
);
149 reparent_ir(shader
->ir
, shader
->ir
);
150 talloc_free(mem_ctx
);
154 if (!_mesa_ir_link_shader(ctx
, prog
))
161 type_size(const struct glsl_type
*type
)
163 unsigned int size
, i
;
165 switch (type
->base_type
) {
168 case GLSL_TYPE_FLOAT
:
170 return type
->components();
171 case GLSL_TYPE_ARRAY
:
172 /* FINISHME: uniform/varying arrays. */
173 return type_size(type
->fields
.array
) * type
->length
;
174 case GLSL_TYPE_STRUCT
:
176 for (i
= 0; i
< type
->length
; i
++) {
177 size
+= type_size(type
->fields
.structure
[i
].type
);
180 case GLSL_TYPE_SAMPLER
:
181 /* Samplers take up no register space, since they're baked in at
186 assert(!"not reached");
193 /* Callers of this talloc-based new need not call delete. It's
194 * easier to just talloc_free 'ctx' (or any of its ancestors). */
195 static void* operator new(size_t size
, void *ctx
)
199 node
= talloc_size(ctx
, size
);
200 assert(node
!= NULL
);
205 /** Generic unset register constructor. */
208 this->file
= BAD_FILE
;
210 this->reg_offset
= 0;
216 /** Immediate value constructor. */
222 this->type
= BRW_REGISTER_TYPE_F
;
228 /** Immediate value constructor. */
234 this->type
= BRW_REGISTER_TYPE_D
;
240 /** Immediate value constructor. */
246 this->type
= BRW_REGISTER_TYPE_UD
;
252 /** Fixed brw_reg Immediate value constructor. */
253 fs_reg(struct brw_reg fixed_hw_reg
)
255 this->file
= FIXED_HW_REG
;
256 this->fixed_hw_reg
= fixed_hw_reg
;
259 this->type
= fixed_hw_reg
.type
;
264 fs_reg(enum register_file file
, int hw_reg
);
265 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
267 /** Register file: ARF, GRF, MRF, IMM. */
268 enum register_file file
;
269 /** Abstract register number. 0 = fixed hw reg */
271 /** Offset within the abstract register. */
273 /** HW register number. Generally unset until register allocation. */
275 /** Register type. BRW_REGISTER_TYPE_* */
279 struct brw_reg fixed_hw_reg
;
281 /** Value for file == BRW_IMMMEDIATE_FILE */
289 static const fs_reg reg_undef
;
290 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
292 class fs_inst
: public exec_node
{
294 /* Callers of this talloc-based new need not call delete. It's
295 * easier to just talloc_free 'ctx' (or any of its ancestors). */
296 static void* operator new(size_t size
, void *ctx
)
300 node
= talloc_zero_size(ctx
, size
);
301 assert(node
!= NULL
);
308 this->opcode
= BRW_OPCODE_NOP
;
309 this->saturate
= false;
310 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
311 this->predicated
= false;
314 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
316 this->opcode
= opcode
;
319 this->saturate
= false;
320 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
321 this->predicated
= false;
324 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
326 this->opcode
= opcode
;
330 this->saturate
= false;
331 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
332 this->predicated
= false;
335 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
337 this->opcode
= opcode
;
342 this->saturate
= false;
343 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
344 this->predicated
= false;
347 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
352 int conditional_mod
; /**< BRW_CONDITIONAL_* */
355 * Annotation for the generated IR. One of the two can be set.
358 const char *annotation
;
362 class fs_visitor
: public ir_visitor
366 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
371 this->intel
= &brw
->intel
;
372 this->mem_ctx
= talloc_new(NULL
);
373 this->shader
= shader
;
375 this->next_abstract_grf
= 1;
376 this->variable_ht
= hash_table_ctor(0,
377 hash_table_pointer_hash
,
378 hash_table_pointer_compare
);
380 this->frag_color
= NULL
;
381 this->frag_data
= NULL
;
382 this->frag_depth
= NULL
;
383 this->first_non_payload_grf
= 0;
385 this->current_annotation
= NULL
;
386 this->annotation_string
= NULL
;
387 this->annotation_ir
= NULL
;
391 talloc_free(this->mem_ctx
);
392 hash_table_dtor(this->variable_ht
);
395 fs_reg
*variable_storage(ir_variable
*var
);
397 void visit(ir_variable
*ir
);
398 void visit(ir_assignment
*ir
);
399 void visit(ir_dereference_variable
*ir
);
400 void visit(ir_dereference_record
*ir
);
401 void visit(ir_dereference_array
*ir
);
402 void visit(ir_expression
*ir
);
403 void visit(ir_texture
*ir
);
404 void visit(ir_if
*ir
);
405 void visit(ir_constant
*ir
);
406 void visit(ir_swizzle
*ir
);
407 void visit(ir_return
*ir
);
408 void visit(ir_loop
*ir
);
409 void visit(ir_loop_jump
*ir
);
410 void visit(ir_discard
*ir
);
411 void visit(ir_call
*ir
);
412 void visit(ir_function
*ir
);
413 void visit(ir_function_signature
*ir
);
415 fs_inst
*emit(fs_inst inst
);
416 void assign_curb_setup();
417 void assign_urb_setup();
419 void generate_code();
420 void generate_fb_write(fs_inst
*inst
);
421 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
422 struct brw_reg
*src
);
423 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
425 void emit_dummy_fs();
426 void emit_interpolation();
427 void emit_pinterp(int location
);
428 void emit_fb_writes();
430 struct brw_reg
interp_reg(int location
, int channel
);
432 struct brw_context
*brw
;
433 struct intel_context
*intel
;
434 struct brw_wm_compile
*c
;
435 struct brw_compile
*p
;
436 struct brw_shader
*shader
;
438 exec_list instructions
;
439 int next_abstract_grf
;
440 struct hash_table
*variable_ht
;
441 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
442 int first_non_payload_grf
;
444 /** @{ debug annotation info */
445 const char *current_annotation
;
446 ir_instruction
*base_ir
;
447 const char **annotation_string
;
448 ir_instruction
**annotation_ir
;
453 /* Result of last visit() method. */
461 fs_reg interp_attrs
[64];
467 /** Fixed HW reg constructor. */
468 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
472 this->reg_offset
= 0;
473 this->hw_reg
= hw_reg
;
474 this->type
= BRW_REGISTER_TYPE_F
;
479 /** Automatic reg constructor. */
480 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
483 this->reg
= v
->next_abstract_grf
;
484 this->reg_offset
= 0;
485 v
->next_abstract_grf
+= type_size(type
);
490 switch (type
->base_type
) {
491 case GLSL_TYPE_FLOAT
:
492 this->type
= BRW_REGISTER_TYPE_F
;
496 this->type
= BRW_REGISTER_TYPE_D
;
499 this->type
= BRW_REGISTER_TYPE_UD
;
502 assert(!"not reached");
503 this->type
= BRW_REGISTER_TYPE_F
;
509 fs_visitor::variable_storage(ir_variable
*var
)
511 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
515 fs_visitor::visit(ir_variable
*ir
)
519 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
520 this->frag_color
= ir
;
521 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
522 this->frag_data
= ir
;
523 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
524 this->frag_depth
= ir
;
525 assert(!"FINISHME: this hangs currently.");
528 if (ir
->mode
== ir_var_in
) {
529 reg
= &this->interp_attrs
[ir
->location
];
532 if (ir
->mode
== ir_var_uniform
) {
533 const float *vec_values
;
534 int param_index
= c
->prog_data
.nr_params
;
536 /* FINISHME: This is wildly incomplete. */
537 assert(ir
->type
->is_scalar() || ir
->type
->is_vector());
539 const struct gl_program
*fp
= &this->brw
->fragment_program
->Base
;
540 /* Our support for uniforms is piggy-backed on the struct
541 * gl_fragment_program, because that's where the values actually
542 * get stored, rather than in some global gl_shader_program uniform
545 vec_values
= fp
->Parameters
->ParameterValues
[ir
->location
];
546 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
547 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
550 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
554 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
556 hash_table_insert(this->variable_ht
, reg
, ir
);
560 fs_visitor::visit(ir_dereference_variable
*ir
)
562 fs_reg
*reg
= variable_storage(ir
->var
);
567 fs_visitor::visit(ir_dereference_record
*ir
)
573 fs_visitor::visit(ir_dereference_array
*ir
)
578 ir
->array
->accept(this);
579 index
= ir
->array_index
->as_constant();
581 if (ir
->type
->is_matrix()) {
582 element_size
= ir
->type
->vector_elements
;
584 element_size
= type_size(ir
->type
);
588 assert(this->result
.file
== UNIFORM
||
589 (this->result
.file
== GRF
&&
590 this->result
.reg
!= 0));
591 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
593 assert(!"FINISHME: non-constant matrix column");
598 fs_visitor::visit(ir_expression
*ir
)
600 unsigned int operand
;
605 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
606 ir
->operands
[operand
]->accept(this);
607 if (this->result
.file
== BAD_FILE
) {
609 printf("Failed to get tree for expression operand:\n");
610 ir
->operands
[operand
]->accept(&v
);
613 op
[operand
] = this->result
;
615 /* Matrix expression operands should have been broken down to vector
616 * operations already.
618 assert(!ir
->operands
[operand
]->type
->is_matrix());
619 /* And then those vector operands should have been broken down to scalar.
621 assert(!ir
->operands
[operand
]->type
->is_vector());
624 /* Storage for our result. If our result goes into an assignment, it will
625 * just get copy-propagated out, so no worries.
627 this->result
= fs_reg(this, ir
->type
);
629 switch (ir
->operation
) {
630 case ir_unop_logic_not
:
631 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
634 this->result
= op
[0];
635 op
[0].negate
= ~op
[0].negate
;
638 this->result
= op
[0];
642 temp
= fs_reg(this, ir
->type
);
644 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
645 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
647 inst
= emit(fs_inst(BRW_OPCODE_CMP
, temp
, op
[0], fs_reg(0.0f
)));
648 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
651 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, this->result
, temp
));
655 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
659 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
662 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
666 assert(!"not reached: should be handled by ir_explog_to_explog2");
669 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
672 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
676 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
679 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
683 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
686 assert(!"not reached: should be handled by ir_sub_to_add_neg");
690 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
693 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
696 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
700 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
701 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
703 case ir_binop_greater
:
704 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
705 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
707 case ir_binop_lequal
:
708 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
709 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
711 case ir_binop_gequal
:
712 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
713 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
716 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
717 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
719 case ir_binop_nequal
:
720 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
721 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
724 case ir_binop_logic_xor
:
725 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
728 case ir_binop_logic_or
:
729 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
732 case ir_binop_logic_and
:
733 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
739 assert(!"not reached: should be handled by brw_channel_expressions");
743 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
747 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
753 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
756 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
760 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
761 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
764 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
767 op
[0].negate
= ~op
[0].negate
;
768 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
769 this->result
.negate
= true;
772 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
775 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
779 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
780 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
782 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
783 inst
->predicated
= true;
786 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
787 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
789 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
790 inst
->predicated
= true;
794 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
797 case ir_unop_bit_not
:
799 case ir_binop_lshift
:
800 case ir_binop_rshift
:
801 case ir_binop_bit_and
:
802 case ir_binop_bit_xor
:
803 case ir_binop_bit_or
:
804 assert(!"GLSL 1.30 features unsupported");
810 fs_visitor::visit(ir_assignment
*ir
)
817 /* FINISHME: arrays on the lhs */
818 ir
->lhs
->accept(this);
821 ir
->rhs
->accept(this);
824 /* FINISHME: This should really set to the correct maximal writemask for each
825 * FINISHME: component written (in the loops below). This case can only
826 * FINISHME: occur for matrices, arrays, and structures.
828 if (ir
->write_mask
== 0) {
829 assert(!ir
->lhs
->type
->is_scalar() && !ir
->lhs
->type
->is_vector());
830 write_mask
= WRITEMASK_XYZW
;
832 assert(ir
->lhs
->type
->is_vector() || ir
->lhs
->type
->is_scalar());
833 write_mask
= ir
->write_mask
;
836 assert(l
.file
!= BAD_FILE
);
837 assert(r
.file
!= BAD_FILE
);
840 /* Get the condition bool into the predicate. */
841 ir
->condition
->accept(this);
842 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, fs_reg(0)));
843 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
846 for (i
= 0; i
< type_size(ir
->lhs
->type
); i
++) {
847 if (i
>= 4 || (write_mask
& (1 << i
))) {
848 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
850 inst
->predicated
= true;
858 fs_visitor::visit(ir_texture
*ir
)
864 fs_visitor::visit(ir_swizzle
*ir
)
866 ir
->val
->accept(this);
867 fs_reg val
= this->result
;
869 fs_reg result
= fs_reg(this, ir
->type
);
870 this->result
= result
;
872 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
873 fs_reg channel
= val
;
891 channel
.reg_offset
+= swiz
;
892 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
898 fs_visitor::visit(ir_discard
*ir
)
904 fs_visitor::visit(ir_constant
*ir
)
906 fs_reg
reg(this, ir
->type
);
909 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
910 switch (ir
->type
->base_type
) {
911 case GLSL_TYPE_FLOAT
:
912 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
915 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
918 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
921 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
924 assert(!"Non-float/uint/int/bool constant");
931 fs_visitor::visit(ir_if
*ir
)
937 fs_visitor::visit(ir_loop
*ir
)
943 fs_visitor::visit(ir_loop_jump
*ir
)
949 fs_visitor::visit(ir_call
*ir
)
955 fs_visitor::visit(ir_return
*ir
)
961 fs_visitor::visit(ir_function
*ir
)
963 /* Ignore function bodies other than main() -- we shouldn't see calls to
964 * them since they should all be inlined before we get to ir_to_mesa.
966 if (strcmp(ir
->name
, "main") == 0) {
967 const ir_function_signature
*sig
;
970 sig
= ir
->matching_signature(&empty
);
974 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
975 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
984 fs_visitor::visit(ir_function_signature
*ir
)
986 assert(!"not reached");
991 fs_visitor::emit(fs_inst inst
)
993 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
996 list_inst
->annotation
= this->current_annotation
;
997 list_inst
->ir
= this->base_ir
;
999 this->instructions
.push_tail(list_inst
);
1004 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1006 fs_visitor::emit_dummy_fs()
1008 /* Everyone's favorite color. */
1009 emit(fs_inst(BRW_OPCODE_MOV
,
1012 emit(fs_inst(BRW_OPCODE_MOV
,
1015 emit(fs_inst(BRW_OPCODE_MOV
,
1018 emit(fs_inst(BRW_OPCODE_MOV
,
1023 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1028 /* The register location here is relative to the start of the URB
1029 * data. It will get adjusted to be a real location before
1030 * generate_code() time.
1033 fs_visitor::interp_reg(int location
, int channel
)
1035 int regnr
= location
* 2 + channel
/ 2;
1036 int stride
= (channel
& 1) * 4;
1038 return brw_vec1_grf(regnr
, stride
);
1041 /** Emits the interpolation for the varying inputs. */
1043 fs_visitor::emit_interpolation()
1045 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1046 /* For now, the source regs for the setup URB data will be unset,
1047 * since we don't know until codegen how many push constants we'll
1048 * use, and therefore what the setup URB offset is.
1050 fs_reg src_reg
= reg_undef
;
1052 this->current_annotation
= "compute pixel centers";
1053 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1054 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1055 emit(fs_inst(BRW_OPCODE_ADD
,
1057 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1058 fs_reg(brw_imm_v(0x10101010))));
1059 emit(fs_inst(BRW_OPCODE_ADD
,
1061 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1062 fs_reg(brw_imm_v(0x11001100))));
1064 this->current_annotation
= "compute pixel deltas from v0";
1065 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1066 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1067 emit(fs_inst(BRW_OPCODE_ADD
,
1070 fs_reg(negate(brw_vec1_grf(1, 0)))));
1071 emit(fs_inst(BRW_OPCODE_ADD
,
1074 fs_reg(brw_vec1_grf(1, 1))));
1076 this->current_annotation
= "compute pos.w and 1/pos.w";
1077 /* Compute wpos. Unlike many other varying inputs, we usually need it
1078 * to produce 1/w, and the varying variable wouldn't show up.
1080 fs_reg wpos
= fs_reg(this, glsl_type::vec4_type
);
1081 this->interp_attrs
[FRAG_ATTRIB_WPOS
] = wpos
;
1082 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
)); /* FINISHME: ARB_fcc */
1084 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
)); /* FINISHME: ARB_fcc */
1086 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1087 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
1089 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
1090 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1091 /* Compute the pixel W value from wpos.w. */
1092 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1093 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos
));
1095 /* FINISHME: gl_FrontFacing */
1097 foreach_iter(exec_list_iterator
, iter
, *this->shader
->ir
) {
1098 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1099 ir_variable
*var
= ir
->as_variable();
1104 if (var
->mode
!= ir_var_in
)
1107 /* If it's already set up (WPOS), skip. */
1108 if (var
->location
== 0)
1111 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1113 "(FRAG_ATTRIB[%d])",
1116 emit_pinterp(var
->location
);
1118 this->current_annotation
= NULL
;
1122 fs_visitor::emit_pinterp(int location
)
1124 fs_reg interp_attr
= fs_reg(this, glsl_type::vec4_type
);
1125 this->interp_attrs
[location
] = interp_attr
;
1127 for (unsigned int i
= 0; i
< 4; i
++) {
1128 struct brw_reg interp
= interp_reg(location
, i
);
1129 emit(fs_inst(FS_OPCODE_LINTERP
,
1134 interp_attr
.reg_offset
++;
1136 interp_attr
.reg_offset
-= 4;
1138 for (unsigned int i
= 0; i
< 4; i
++) {
1139 emit(fs_inst(BRW_OPCODE_MUL
,
1143 interp_attr
.reg_offset
++;
1148 fs_visitor::emit_fb_writes()
1150 this->current_annotation
= "FB write";
1152 assert(this->frag_color
|| !"FINISHME: MRT");
1153 fs_reg color
= *(variable_storage(this->frag_color
));
1155 for (int i
= 0; i
< 4; i
++) {
1156 emit(fs_inst(BRW_OPCODE_MOV
,
1162 emit(fs_inst(FS_OPCODE_FB_WRITE
,
1166 this->current_annotation
= NULL
;
1170 fs_visitor::generate_fb_write(fs_inst
*inst
)
1172 GLboolean eot
= 1; /* FINISHME: MRT */
1173 /* FINISHME: AADS */
1175 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1178 brw_push_insn_state(p
);
1179 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1180 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1183 brw_vec8_grf(1, 0));
1184 brw_pop_insn_state(p
);
1189 8, /* dispatch_width */
1190 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1192 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
1193 0, /* FINISHME: MRT target */
1200 fs_visitor::generate_linterp(fs_inst
*inst
,
1201 struct brw_reg dst
, struct brw_reg
*src
)
1203 struct brw_reg delta_x
= src
[0];
1204 struct brw_reg delta_y
= src
[1];
1205 struct brw_reg interp
= src
[2];
1208 delta_y
.nr
== delta_x
.nr
+ 1 &&
1209 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1210 brw_PLN(p
, dst
, interp
, delta_x
);
1212 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1213 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1218 fs_visitor::generate_math(fs_inst
*inst
,
1219 struct brw_reg dst
, struct brw_reg
*src
)
1223 switch (inst
->opcode
) {
1225 op
= BRW_MATH_FUNCTION_INV
;
1228 op
= BRW_MATH_FUNCTION_RSQ
;
1230 case FS_OPCODE_SQRT
:
1231 op
= BRW_MATH_FUNCTION_SQRT
;
1233 case FS_OPCODE_EXP2
:
1234 op
= BRW_MATH_FUNCTION_EXP
;
1236 case FS_OPCODE_LOG2
:
1237 op
= BRW_MATH_FUNCTION_LOG
;
1240 op
= BRW_MATH_FUNCTION_POW
;
1243 op
= BRW_MATH_FUNCTION_SIN
;
1246 op
= BRW_MATH_FUNCTION_COS
;
1249 assert(!"not reached: unknown math function");
1254 if (inst
->opcode
== FS_OPCODE_POW
) {
1255 brw_MOV(p
, brw_message_reg(3), src
[1]);
1260 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1261 BRW_MATH_SATURATE_NONE
,
1263 BRW_MATH_DATA_VECTOR
,
1264 BRW_MATH_PRECISION_FULL
);
1268 trivial_assign_reg(int header_size
, fs_reg
*reg
)
1270 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
1271 reg
->hw_reg
= header_size
+ reg
->reg
- 1 + reg
->reg_offset
;
1277 fs_visitor::assign_curb_setup()
1279 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
1280 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
1282 /* Map the offsets in the UNIFORM file to fixed HW regs. */
1283 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1284 fs_inst
*inst
= (fs_inst
*)iter
.get();
1286 for (unsigned int i
= 0; i
< 3; i
++) {
1287 if (inst
->src
[i
].file
== UNIFORM
) {
1288 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
1289 struct brw_reg brw_reg
;
1291 brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
1294 inst
->src
[i
] = fs_reg(brw_reg
);
1301 fs_visitor::assign_urb_setup()
1303 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
1304 int interp_reg_nr
[FRAG_ATTRIB_MAX
];
1306 c
->prog_data
.urb_read_length
= 0;
1308 /* Figure out where each of the incoming setup attributes lands. */
1309 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
1310 interp_reg_nr
[i
] = -1;
1312 if (i
!= FRAG_ATTRIB_WPOS
&&
1313 !(brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)))
1316 /* Each attribute is 4 setup channels, each of which is half a reg. */
1317 interp_reg_nr
[i
] = urb_start
+ c
->prog_data
.urb_read_length
;
1318 c
->prog_data
.urb_read_length
+= 2;
1321 /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1322 * the correct setup input.
1324 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1325 fs_inst
*inst
= (fs_inst
*)iter
.get();
1327 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
1330 assert(inst
->src
[2].file
== FIXED_HW_REG
);
1332 int location
= inst
->src
[2].fixed_hw_reg
.nr
/ 2;
1333 assert(interp_reg_nr
[location
] != -1);
1334 inst
->src
[2].fixed_hw_reg
.nr
= (interp_reg_nr
[location
] +
1335 (inst
->src
[2].fixed_hw_reg
.nr
& 1));
1338 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
1342 fs_visitor::assign_regs()
1344 int header_size
= this->first_non_payload_grf
;
1347 /* FINISHME: trivial assignment of register numbers */
1348 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1349 fs_inst
*inst
= (fs_inst
*)iter
.get();
1351 trivial_assign_reg(header_size
, &inst
->dst
);
1352 trivial_assign_reg(header_size
, &inst
->src
[0]);
1353 trivial_assign_reg(header_size
, &inst
->src
[1]);
1355 last_grf
= MAX2(last_grf
, inst
->dst
.hw_reg
);
1356 last_grf
= MAX2(last_grf
, inst
->src
[0].hw_reg
);
1357 last_grf
= MAX2(last_grf
, inst
->src
[1].hw_reg
);
1360 this->grf_used
= last_grf
;
1363 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
1365 struct brw_reg brw_reg
;
1367 switch (reg
->file
) {
1371 brw_reg
= brw_vec8_reg(reg
->file
,
1373 brw_reg
= retype(brw_reg
, reg
->type
);
1376 switch (reg
->type
) {
1377 case BRW_REGISTER_TYPE_F
:
1378 brw_reg
= brw_imm_f(reg
->imm
.f
);
1380 case BRW_REGISTER_TYPE_D
:
1381 brw_reg
= brw_imm_f(reg
->imm
.i
);
1383 case BRW_REGISTER_TYPE_UD
:
1384 brw_reg
= brw_imm_f(reg
->imm
.u
);
1387 assert(!"not reached");
1392 brw_reg
= reg
->fixed_hw_reg
;
1395 /* Probably unused. */
1396 brw_reg
= brw_null_reg();
1399 assert(!"not reached");
1400 brw_reg
= brw_null_reg();
1404 brw_reg
= brw_abs(brw_reg
);
1406 brw_reg
= negate(brw_reg
);
1412 fs_visitor::generate_code()
1414 unsigned int annotation_len
= 0;
1415 int last_native_inst
= 0;
1417 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
1418 fs_inst
*inst
= (fs_inst
*)iter
.get();
1419 struct brw_reg src
[3], dst
;
1421 for (unsigned int i
= 0; i
< 3; i
++) {
1422 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
1424 dst
= brw_reg_from_fs_reg(&inst
->dst
);
1426 brw_set_conditionalmod(p
, inst
->conditional_mod
);
1427 brw_set_predicate_control(p
, inst
->predicated
);
1429 switch (inst
->opcode
) {
1430 case BRW_OPCODE_MOV
:
1431 brw_MOV(p
, dst
, src
[0]);
1433 case BRW_OPCODE_ADD
:
1434 brw_ADD(p
, dst
, src
[0], src
[1]);
1436 case BRW_OPCODE_MUL
:
1437 brw_MUL(p
, dst
, src
[0], src
[1]);
1441 case FS_OPCODE_SQRT
:
1442 case FS_OPCODE_EXP2
:
1443 case FS_OPCODE_LOG2
:
1447 generate_math(inst
, dst
, src
);
1449 case FS_OPCODE_LINTERP
:
1450 generate_linterp(inst
, dst
, src
);
1452 case FS_OPCODE_FB_WRITE
:
1453 generate_fb_write(inst
);
1456 assert(!"not reached");
1459 if (annotation_len
< p
->nr_insn
) {
1460 annotation_len
*= 2;
1461 if (annotation_len
< 16)
1462 annotation_len
= 16;
1464 this->annotation_string
= talloc_realloc(this->mem_ctx
,
1468 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
1474 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
1475 this->annotation_string
[i
] = inst
->annotation
;
1476 this->annotation_ir
[i
] = inst
->ir
;
1478 last_native_inst
= p
->nr_insn
;
1483 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
1485 struct brw_compile
*p
= &c
->func
;
1486 struct intel_context
*intel
= &brw
->intel
;
1487 GLcontext
*ctx
= &intel
->ctx
;
1488 struct brw_shader
*shader
= NULL
;
1489 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
1497 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
1498 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
1499 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
1506 /* We always use 8-wide mode, at least for now. For one, flow
1507 * control only works in 8-wide. Also, when we're fragment shader
1508 * bound, we're almost always under register pressure as well, so
1509 * 8-wide would save us from the performance cliff of spilling
1512 c
->dispatch_width
= 8;
1514 if (INTEL_DEBUG
& DEBUG_WM
) {
1515 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
1516 _mesa_print_ir(shader
->ir
, NULL
);
1520 /* Now the main event: Visit the shader IR and generate our FS IR for it.
1522 fs_visitor
v(c
, shader
);
1527 v
.emit_interpolation();
1529 /* Generate FS IR for main(). (the visitor only descends into
1530 * functions called "main").
1532 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
1533 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1542 v
.assign_curb_setup();
1543 v
.assign_urb_setup();
1549 if (INTEL_DEBUG
& DEBUG_WM
) {
1550 const char *last_annotation_string
= NULL
;
1551 ir_instruction
*last_annotation_ir
= NULL
;
1553 printf("Native code for fragment shader %d:\n", prog
->Name
);
1554 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
1555 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
1556 last_annotation_ir
= v
.annotation_ir
[i
];
1557 if (last_annotation_ir
) {
1559 last_annotation_ir
->print();
1563 if (last_annotation_string
!= v
.annotation_string
[i
]) {
1564 last_annotation_string
= v
.annotation_string
[i
];
1565 if (last_annotation_string
)
1566 printf(" %s\n", last_annotation_string
);
1568 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
1573 c
->prog_data
.total_grf
= v
.grf_used
;
1574 c
->prog_data
.total_scratch
= 0;