2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
46 #include "../glsl/glsl_types.h"
47 #include "../glsl/ir_optimization.h"
48 #include "../glsl/ir_print_visitor.h"
51 ARF
= BRW_ARCHITECTURE_REGISTER_FILE
,
52 GRF
= BRW_GENERAL_REGISTER_FILE
,
53 MRF
= BRW_MESSAGE_REGISTER_FILE
,
54 IMM
= BRW_IMMEDIATE_VALUE
,
55 FIXED_HW_REG
, /* a struct brw_reg */
56 UNIFORM
, /* prog_data->params[hw_reg] */
61 FS_OPCODE_FB_WRITE
= 256,
79 static int using_new_fs
= -1;
80 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
83 brw_new_shader(GLcontext
*ctx
, GLuint name
, GLuint type
)
85 struct brw_shader
*shader
;
87 shader
= talloc_zero(NULL
, struct brw_shader
);
89 shader
->base
.Type
= type
;
90 shader
->base
.Name
= name
;
91 _mesa_init_shader(ctx
, &shader
->base
);
97 struct gl_shader_program
*
98 brw_new_shader_program(GLcontext
*ctx
, GLuint name
)
100 struct brw_shader_program
*prog
;
101 prog
= talloc_zero(NULL
, struct brw_shader_program
);
103 prog
->base
.Name
= name
;
104 _mesa_init_shader_program(ctx
, &prog
->base
);
110 brw_compile_shader(GLcontext
*ctx
, struct gl_shader
*shader
)
112 if (!_mesa_ir_compile_shader(ctx
, shader
))
119 brw_link_shader(GLcontext
*ctx
, struct gl_shader_program
*prog
)
121 if (using_new_fs
== -1)
122 using_new_fs
= getenv("INTEL_NEW_FS") != NULL
;
124 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
125 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
127 if (using_new_fs
&& shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
128 void *mem_ctx
= talloc_new(NULL
);
132 talloc_free(shader
->ir
);
133 shader
->ir
= new(shader
) exec_list
;
134 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
136 do_mat_op_to_vec(shader
->ir
);
137 do_mod_to_fract(shader
->ir
);
138 do_div_to_mul_rcp(shader
->ir
);
139 do_sub_to_add_neg(shader
->ir
);
140 do_explog_to_explog2(shader
->ir
);
141 do_lower_texture_projection(shader
->ir
);
146 brw_do_channel_expressions(shader
->ir
);
147 brw_do_vector_splitting(shader
->ir
);
149 progress
= do_lower_jumps(shader
->ir
, true, true,
150 true, /* main return */
151 false, /* continue */
155 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
157 progress
= lower_noise(shader
->ir
) || progress
;
159 lower_variable_index_to_cond_assign(shader
->ir
,
161 GL_TRUE
, /* output */
163 GL_TRUE
/* uniform */
167 validate_ir_tree(shader
->ir
);
169 reparent_ir(shader
->ir
, shader
->ir
);
170 talloc_free(mem_ctx
);
174 if (!_mesa_ir_link_shader(ctx
, prog
))
181 type_size(const struct glsl_type
*type
)
183 unsigned int size
, i
;
185 switch (type
->base_type
) {
188 case GLSL_TYPE_FLOAT
:
190 return type
->components();
191 case GLSL_TYPE_ARRAY
:
192 return type_size(type
->fields
.array
) * type
->length
;
193 case GLSL_TYPE_STRUCT
:
195 for (i
= 0; i
< type
->length
; i
++) {
196 size
+= type_size(type
->fields
.structure
[i
].type
);
199 case GLSL_TYPE_SAMPLER
:
200 /* Samplers take up no register space, since they're baked in at
205 assert(!"not reached");
212 /* Callers of this talloc-based new need not call delete. It's
213 * easier to just talloc_free 'ctx' (or any of its ancestors). */
214 static void* operator new(size_t size
, void *ctx
)
218 node
= talloc_size(ctx
, size
);
219 assert(node
!= NULL
);
227 this->reg_offset
= 0;
233 /** Generic unset register constructor. */
237 this->file
= BAD_FILE
;
240 /** Immediate value constructor. */
245 this->type
= BRW_REGISTER_TYPE_F
;
249 /** Immediate value constructor. */
254 this->type
= BRW_REGISTER_TYPE_D
;
258 /** Immediate value constructor. */
263 this->type
= BRW_REGISTER_TYPE_UD
;
267 /** Fixed brw_reg Immediate value constructor. */
268 fs_reg(struct brw_reg fixed_hw_reg
)
271 this->file
= FIXED_HW_REG
;
272 this->fixed_hw_reg
= fixed_hw_reg
;
273 this->type
= fixed_hw_reg
.type
;
276 fs_reg(enum register_file file
, int hw_reg
);
277 fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
);
279 /** Register file: ARF, GRF, MRF, IMM. */
280 enum register_file file
;
281 /** virtual register number. 0 = fixed hw reg */
283 /** Offset within the virtual register. */
285 /** HW register number. Generally unset until register allocation. */
287 /** Register type. BRW_REGISTER_TYPE_* */
291 struct brw_reg fixed_hw_reg
;
293 /** Value for file == BRW_IMMMEDIATE_FILE */
301 static const fs_reg reg_undef
;
302 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
304 class fs_inst
: public exec_node
{
306 /* Callers of this talloc-based new need not call delete. It's
307 * easier to just talloc_free 'ctx' (or any of its ancestors). */
308 static void* operator new(size_t size
, void *ctx
)
312 node
= talloc_zero_size(ctx
, size
);
313 assert(node
!= NULL
);
320 this->opcode
= BRW_OPCODE_NOP
;
321 this->saturate
= false;
322 this->conditional_mod
= BRW_CONDITIONAL_NONE
;
323 this->predicated
= false;
327 this->header_present
= false;
328 this->shadow_compare
= false;
339 this->opcode
= opcode
;
342 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
)
345 this->opcode
= opcode
;
350 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
353 this->opcode
= opcode
;
359 fs_inst(int opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
, fs_reg src2
)
362 this->opcode
= opcode
;
369 int opcode
; /* BRW_OPCODE_* or FS_OPCODE_* */
374 int conditional_mod
; /**< BRW_CONDITIONAL_* */
376 int mlen
; /**< SEND message length */
378 int target
; /**< MRT target. */
384 * Annotation for the generated IR. One of the two can be set.
387 const char *annotation
;
391 class fs_visitor
: public ir_visitor
395 fs_visitor(struct brw_wm_compile
*c
, struct brw_shader
*shader
)
400 this->fp
= brw
->fragment_program
;
401 this->intel
= &brw
->intel
;
402 this->ctx
= &intel
->ctx
;
403 this->mem_ctx
= talloc_new(NULL
);
404 this->shader
= shader
;
406 this->variable_ht
= hash_table_ctor(0,
407 hash_table_pointer_hash
,
408 hash_table_pointer_compare
);
410 this->frag_color
= NULL
;
411 this->frag_data
= NULL
;
412 this->frag_depth
= NULL
;
413 this->first_non_payload_grf
= 0;
415 this->current_annotation
= NULL
;
416 this->annotation_string
= NULL
;
417 this->annotation_ir
= NULL
;
418 this->base_ir
= NULL
;
420 this->virtual_grf_sizes
= NULL
;
421 this->virtual_grf_next
= 1;
422 this->virtual_grf_array_size
= 0;
423 this->virtual_grf_def
= NULL
;
424 this->virtual_grf_use
= NULL
;
426 this->kill_emitted
= false;
431 talloc_free(this->mem_ctx
);
432 hash_table_dtor(this->variable_ht
);
435 fs_reg
*variable_storage(ir_variable
*var
);
436 int virtual_grf_alloc(int size
);
438 void visit(ir_variable
*ir
);
439 void visit(ir_assignment
*ir
);
440 void visit(ir_dereference_variable
*ir
);
441 void visit(ir_dereference_record
*ir
);
442 void visit(ir_dereference_array
*ir
);
443 void visit(ir_expression
*ir
);
444 void visit(ir_texture
*ir
);
445 void visit(ir_if
*ir
);
446 void visit(ir_constant
*ir
);
447 void visit(ir_swizzle
*ir
);
448 void visit(ir_return
*ir
);
449 void visit(ir_loop
*ir
);
450 void visit(ir_loop_jump
*ir
);
451 void visit(ir_discard
*ir
);
452 void visit(ir_call
*ir
);
453 void visit(ir_function
*ir
);
454 void visit(ir_function_signature
*ir
);
456 fs_inst
*emit(fs_inst inst
);
457 void assign_curb_setup();
458 void calculate_urb_setup();
459 void assign_urb_setup();
461 void assign_regs_trivial();
462 void calculate_live_intervals();
463 bool propagate_constants();
464 bool dead_code_eliminate();
465 bool virtual_grf_interferes(int a
, int b
);
466 void generate_code();
467 void generate_fb_write(fs_inst
*inst
);
468 void generate_linterp(fs_inst
*inst
, struct brw_reg dst
,
469 struct brw_reg
*src
);
470 void generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
471 void generate_math(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg
*src
);
472 void generate_discard(fs_inst
*inst
, struct brw_reg temp
);
473 void generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
474 void generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
);
476 void emit_dummy_fs();
477 fs_reg
*emit_fragcoord_interpolation(ir_variable
*ir
);
478 fs_reg
*emit_frontfacing_interpolation(ir_variable
*ir
);
479 fs_reg
*emit_general_interpolation(ir_variable
*ir
);
480 void emit_interpolation_setup_gen4();
481 void emit_interpolation_setup_gen6();
482 fs_inst
*emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
483 fs_inst
*emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
);
484 void emit_fb_writes();
485 void emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
486 const glsl_type
*type
, bool predicated
);
488 struct brw_reg
interp_reg(int location
, int channel
);
489 int setup_uniform_values(int loc
, const glsl_type
*type
);
490 void setup_builtin_uniform_values(ir_variable
*ir
);
492 struct brw_context
*brw
;
493 const struct gl_fragment_program
*fp
;
494 struct intel_context
*intel
;
496 struct brw_wm_compile
*c
;
497 struct brw_compile
*p
;
498 struct brw_shader
*shader
;
500 exec_list instructions
;
502 int *virtual_grf_sizes
;
503 int virtual_grf_next
;
504 int virtual_grf_array_size
;
505 int *virtual_grf_def
;
506 int *virtual_grf_use
;
508 struct hash_table
*variable_ht
;
509 ir_variable
*frag_color
, *frag_data
, *frag_depth
;
510 int first_non_payload_grf
;
511 int urb_setup
[FRAG_ATTRIB_MAX
];
514 /** @{ debug annotation info */
515 const char *current_annotation
;
516 ir_instruction
*base_ir
;
517 const char **annotation_string
;
518 ir_instruction
**annotation_ir
;
523 /* Result of last visit() method. */
538 fs_visitor::virtual_grf_alloc(int size
)
540 if (virtual_grf_array_size
<= virtual_grf_next
) {
541 if (virtual_grf_array_size
== 0)
542 virtual_grf_array_size
= 16;
544 virtual_grf_array_size
*= 2;
545 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
546 int, virtual_grf_array_size
);
548 /* This slot is always unused. */
549 virtual_grf_sizes
[0] = 0;
551 virtual_grf_sizes
[virtual_grf_next
] = size
;
552 return virtual_grf_next
++;
555 /** Fixed HW reg constructor. */
556 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
560 this->hw_reg
= hw_reg
;
561 this->type
= BRW_REGISTER_TYPE_F
;
565 brw_type_for_base_type(const struct glsl_type
*type
)
567 switch (type
->base_type
) {
568 case GLSL_TYPE_FLOAT
:
569 return BRW_REGISTER_TYPE_F
;
572 return BRW_REGISTER_TYPE_D
;
574 return BRW_REGISTER_TYPE_UD
;
575 case GLSL_TYPE_ARRAY
:
576 case GLSL_TYPE_STRUCT
:
577 /* These should be overridden with the type of the member when
578 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
579 * way to trip up if we don't.
581 return BRW_REGISTER_TYPE_UD
;
583 assert(!"not reached");
584 return BRW_REGISTER_TYPE_F
;
588 /** Automatic reg constructor. */
589 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
594 this->reg
= v
->virtual_grf_alloc(type_size(type
));
595 this->reg_offset
= 0;
596 this->type
= brw_type_for_base_type(type
);
600 fs_visitor::variable_storage(ir_variable
*var
)
602 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
605 /* Our support for uniforms is piggy-backed on the struct
606 * gl_fragment_program, because that's where the values actually
607 * get stored, rather than in some global gl_shader_program uniform
611 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
613 unsigned int offset
= 0;
616 if (type
->is_matrix()) {
617 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
618 type
->vector_elements
,
621 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
622 offset
+= setup_uniform_values(loc
+ offset
, column
);
628 switch (type
->base_type
) {
629 case GLSL_TYPE_FLOAT
:
633 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
634 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
635 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
639 case GLSL_TYPE_STRUCT
:
640 for (unsigned int i
= 0; i
< type
->length
; i
++) {
641 offset
+= setup_uniform_values(loc
+ offset
,
642 type
->fields
.structure
[i
].type
);
646 case GLSL_TYPE_ARRAY
:
647 for (unsigned int i
= 0; i
< type
->length
; i
++) {
648 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
652 case GLSL_TYPE_SAMPLER
:
653 /* The sampler takes up a slot, but we don't use any values from it. */
657 assert(!"not reached");
663 /* Our support for builtin uniforms is even scarier than non-builtin.
664 * It sits on top of the PROG_STATE_VAR parameters that are
665 * automatically updated from GL context state.
668 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
670 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
672 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
673 statevar
= &_mesa_builtin_uniform_desc
[i
];
674 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
678 if (!statevar
->name
) {
680 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
685 if (ir
->type
->is_array()) {
686 array_count
= ir
->type
->length
;
691 for (int a
= 0; a
< array_count
; a
++) {
692 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
693 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
694 int tokens
[STATE_LENGTH
];
696 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
697 if (ir
->type
->is_array()) {
701 /* This state reference has already been setup by ir_to_mesa,
702 * but we'll get the same index back here.
704 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
705 (gl_state_index
*)tokens
);
706 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
708 /* Add each of the unique swizzles of the element as a
709 * parameter. This'll end up matching the expected layout of
710 * the array/matrix/structure we're trying to fill in.
713 for (unsigned int i
= 0; i
< 4; i
++) {
714 int swiz
= GET_SWZ(element
->swizzle
, i
);
715 if (swiz
== last_swiz
)
719 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
726 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
728 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
730 fs_reg neg_y
= this->pixel_y
;
734 if (ir
->pixel_center_integer
) {
735 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
737 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
742 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
743 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
745 fs_reg pixel_y
= this->pixel_y
;
746 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
748 if (!ir
->origin_upper_left
) {
749 pixel_y
.negate
= true;
750 offset
+= c
->key
.drawable_height
- 1.0;
753 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
758 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
759 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
762 /* gl_FragCoord.w: Already set up in emit_interpolation */
763 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
769 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
771 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
772 /* Interpolation is always in floating point regs. */
773 reg
->type
= BRW_REGISTER_TYPE_F
;
776 unsigned int array_elements
;
777 const glsl_type
*type
;
779 if (ir
->type
->is_array()) {
780 array_elements
= ir
->type
->length
;
781 if (array_elements
== 0) {
784 type
= ir
->type
->fields
.array
;
790 int location
= ir
->location
;
791 for (unsigned int i
= 0; i
< array_elements
; i
++) {
792 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
793 if (urb_setup
[location
] == -1) {
794 /* If there's no incoming setup data for this slot, don't
795 * emit interpolation for it.
797 attr
.reg_offset
+= type
->vector_elements
;
802 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
803 struct brw_reg interp
= interp_reg(location
, c
);
804 emit(fs_inst(FS_OPCODE_LINTERP
,
811 attr
.reg_offset
-= type
->vector_elements
;
813 if (intel
->gen
< 6) {
814 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
815 emit(fs_inst(BRW_OPCODE_MUL
,
830 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
832 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
834 /* The frontfacing comes in as a bit in the thread payload. */
835 if (intel
->gen
>= 6) {
836 emit(fs_inst(BRW_OPCODE_ASR
,
838 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
840 emit(fs_inst(BRW_OPCODE_NOT
,
843 emit(fs_inst(BRW_OPCODE_AND
,
848 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
849 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
850 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
853 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
857 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
858 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
865 fs_visitor::visit(ir_variable
*ir
)
869 if (variable_storage(ir
))
872 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
873 this->frag_color
= ir
;
874 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
875 this->frag_data
= ir
;
876 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
877 this->frag_depth
= ir
;
880 if (ir
->mode
== ir_var_in
) {
881 if (!strcmp(ir
->name
, "gl_FragCoord")) {
882 reg
= emit_fragcoord_interpolation(ir
);
883 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
884 reg
= emit_frontfacing_interpolation(ir
);
886 reg
= emit_general_interpolation(ir
);
889 hash_table_insert(this->variable_ht
, reg
, ir
);
893 if (ir
->mode
== ir_var_uniform
) {
894 int param_index
= c
->prog_data
.nr_params
;
896 if (!strncmp(ir
->name
, "gl_", 3)) {
897 setup_builtin_uniform_values(ir
);
899 setup_uniform_values(ir
->location
, ir
->type
);
902 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
906 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
908 hash_table_insert(this->variable_ht
, reg
, ir
);
912 fs_visitor::visit(ir_dereference_variable
*ir
)
914 fs_reg
*reg
= variable_storage(ir
->var
);
919 fs_visitor::visit(ir_dereference_record
*ir
)
921 const glsl_type
*struct_type
= ir
->record
->type
;
923 ir
->record
->accept(this);
925 unsigned int offset
= 0;
926 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
927 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
929 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
931 this->result
.reg_offset
+= offset
;
932 this->result
.type
= brw_type_for_base_type(ir
->type
);
936 fs_visitor::visit(ir_dereference_array
*ir
)
941 ir
->array
->accept(this);
942 index
= ir
->array_index
->as_constant();
944 element_size
= type_size(ir
->type
);
945 this->result
.type
= brw_type_for_base_type(ir
->type
);
948 assert(this->result
.file
== UNIFORM
||
949 (this->result
.file
== GRF
&&
950 this->result
.reg
!= 0));
951 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
953 assert(!"FINISHME: non-constant array element");
958 fs_visitor::visit(ir_expression
*ir
)
960 unsigned int operand
;
965 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
966 ir
->operands
[operand
]->accept(this);
967 if (this->result
.file
== BAD_FILE
) {
969 printf("Failed to get tree for expression operand:\n");
970 ir
->operands
[operand
]->accept(&v
);
973 op
[operand
] = this->result
;
975 /* Matrix expression operands should have been broken down to vector
976 * operations already.
978 assert(!ir
->operands
[operand
]->type
->is_matrix());
979 /* And then those vector operands should have been broken down to scalar.
981 assert(!ir
->operands
[operand
]->type
->is_vector());
984 /* Storage for our result. If our result goes into an assignment, it will
985 * just get copy-propagated out, so no worries.
987 this->result
= fs_reg(this, ir
->type
);
989 switch (ir
->operation
) {
990 case ir_unop_logic_not
:
991 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
994 op
[0].negate
= !op
[0].negate
;
995 this->result
= op
[0];
999 this->result
= op
[0];
1002 temp
= fs_reg(this, ir
->type
);
1004 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
1006 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1007 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1008 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
1009 inst
->predicated
= true;
1011 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1012 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1013 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
1014 inst
->predicated
= true;
1018 emit(fs_inst(FS_OPCODE_RCP
, this->result
, op
[0]));
1022 emit(fs_inst(FS_OPCODE_EXP2
, this->result
, op
[0]));
1025 emit(fs_inst(FS_OPCODE_LOG2
, this->result
, op
[0]));
1029 assert(!"not reached: should be handled by ir_explog_to_explog2");
1032 emit(fs_inst(FS_OPCODE_SIN
, this->result
, op
[0]));
1035 emit(fs_inst(FS_OPCODE_COS
, this->result
, op
[0]));
1039 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
1042 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
1046 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
1049 assert(!"not reached: should be handled by ir_sub_to_add_neg");
1053 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
1056 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
1059 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
1063 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1064 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1065 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1067 case ir_binop_greater
:
1068 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1069 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1070 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1072 case ir_binop_lequal
:
1073 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1074 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1075 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1077 case ir_binop_gequal
:
1078 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1079 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1080 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1082 case ir_binop_equal
:
1083 case ir_binop_all_equal
: /* same as nequal for scalars */
1084 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1085 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1086 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1088 case ir_binop_nequal
:
1089 case ir_binop_any_nequal
: /* same as nequal for scalars */
1090 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1091 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1092 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
1095 case ir_binop_logic_xor
:
1096 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
1099 case ir_binop_logic_or
:
1100 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
1103 case ir_binop_logic_and
:
1104 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
1108 case ir_binop_cross
:
1110 assert(!"not reached: should be handled by brw_fs_channel_expressions");
1114 assert(!"not reached: should be handled by lower_noise");
1118 emit(fs_inst(FS_OPCODE_SQRT
, this->result
, op
[0]));
1122 emit(fs_inst(FS_OPCODE_RSQ
, this->result
, op
[0]));
1128 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1131 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
1135 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
1136 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1139 emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1142 op
[0].negate
= ~op
[0].negate
;
1143 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1144 this->result
.negate
= true;
1147 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
1150 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
1154 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1155 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1157 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1158 inst
->predicated
= true;
1161 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
1162 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1164 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
1165 inst
->predicated
= true;
1169 inst
= emit(fs_inst(FS_OPCODE_POW
, this->result
, op
[0], op
[1]));
1172 case ir_unop_bit_not
:
1174 case ir_binop_lshift
:
1175 case ir_binop_rshift
:
1176 case ir_binop_bit_and
:
1177 case ir_binop_bit_xor
:
1178 case ir_binop_bit_or
:
1179 assert(!"GLSL 1.30 features unsupported");
1185 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
1186 const glsl_type
*type
, bool predicated
)
1188 switch (type
->base_type
) {
1189 case GLSL_TYPE_FLOAT
:
1190 case GLSL_TYPE_UINT
:
1192 case GLSL_TYPE_BOOL
:
1193 for (unsigned int i
= 0; i
< type
->components(); i
++) {
1194 l
.type
= brw_type_for_base_type(type
);
1195 r
.type
= brw_type_for_base_type(type
);
1197 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1198 inst
->predicated
= predicated
;
1204 case GLSL_TYPE_ARRAY
:
1205 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1206 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
1209 case GLSL_TYPE_STRUCT
:
1210 for (unsigned int i
= 0; i
< type
->length
; i
++) {
1211 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
1216 case GLSL_TYPE_SAMPLER
:
1220 assert(!"not reached");
1226 fs_visitor::visit(ir_assignment
*ir
)
1231 /* FINISHME: arrays on the lhs */
1232 ir
->lhs
->accept(this);
1235 ir
->rhs
->accept(this);
1238 assert(l
.file
!= BAD_FILE
);
1239 assert(r
.file
!= BAD_FILE
);
1241 if (ir
->condition
) {
1242 /* Get the condition bool into the predicate. */
1243 ir
->condition
->accept(this);
1244 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, this->result
, fs_reg(0)));
1245 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1248 if (ir
->lhs
->type
->is_scalar() ||
1249 ir
->lhs
->type
->is_vector()) {
1250 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
1251 if (ir
->write_mask
& (1 << i
)) {
1252 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1254 inst
->predicated
= true;
1260 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
1265 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1269 bool simd16
= false;
1272 if (ir
->shadow_comparitor
) {
1273 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1274 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1276 coordinate
.reg_offset
++;
1278 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1281 if (ir
->op
== ir_tex
) {
1282 /* There's no plain shadow compare message, so we use shadow
1283 * compare with a bias of 0.0.
1285 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1288 } else if (ir
->op
== ir_txb
) {
1289 ir
->lod_info
.bias
->accept(this);
1290 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1294 assert(ir
->op
== ir_txl
);
1295 ir
->lod_info
.lod
->accept(this);
1296 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1301 ir
->shadow_comparitor
->accept(this);
1302 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1304 } else if (ir
->op
== ir_tex
) {
1305 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1306 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1308 coordinate
.reg_offset
++;
1310 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1313 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1314 * instructions. We'll need to do SIMD16 here.
1316 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1318 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
* 2;) {
1319 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1321 coordinate
.reg_offset
++;
1324 /* The unused upper half. */
1328 /* lod/bias appears after u/v/r. */
1331 if (ir
->op
== ir_txb
) {
1332 ir
->lod_info
.bias
->accept(this);
1333 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1337 ir
->lod_info
.lod
->accept(this);
1338 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1343 /* The unused upper half. */
1346 /* Now, since we're doing simd16, the return is 2 interleaved
1347 * vec4s where the odd-indexed ones are junk. We'll need to move
1348 * this weirdness around to the expected layout.
1352 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1354 dst
.type
= BRW_REGISTER_TYPE_F
;
1357 fs_inst
*inst
= NULL
;
1360 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1363 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1366 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1370 assert(!"GLSL 1.30 features unsupported");
1376 for (int i
= 0; i
< 4; i
++) {
1377 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1378 orig_dst
.reg_offset
++;
1379 dst
.reg_offset
+= 2;
1387 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1389 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1390 * optional parameters like shadow comparitor or LOD bias. If
1391 * optional parameters aren't present, those base slots are
1392 * optional and don't need to be included in the message.
1394 * We don't fill in the unnecessary slots regardless, which may
1395 * look surprising in the disassembly.
1400 for (mlen
= 0; mlen
< ir
->coordinate
->type
->vector_elements
; mlen
++) {
1401 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), coordinate
));
1402 coordinate
.reg_offset
++;
1405 if (ir
->shadow_comparitor
) {
1406 mlen
= MAX2(mlen
, 4);
1408 ir
->shadow_comparitor
->accept(this);
1409 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1413 fs_inst
*inst
= NULL
;
1416 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
, fs_reg(MRF
, base_mrf
)));
1419 ir
->lod_info
.bias
->accept(this);
1420 mlen
= MAX2(mlen
, 4);
1421 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1424 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
, fs_reg(MRF
, base_mrf
)));
1427 ir
->lod_info
.lod
->accept(this);
1428 mlen
= MAX2(mlen
, 4);
1429 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1432 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
, fs_reg(MRF
, base_mrf
)));
1436 assert(!"GLSL 1.30 features unsupported");
1445 fs_visitor::visit(ir_texture
*ir
)
1447 fs_inst
*inst
= NULL
;
1449 ir
->coordinate
->accept(this);
1450 fs_reg coordinate
= this->result
;
1452 /* Should be lowered by do_lower_texture_projection */
1453 assert(!ir
->projector
);
1455 /* Writemasking doesn't eliminate channels on SIMD8 texture
1456 * samples, so don't worry about them.
1458 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1460 if (intel
->gen
< 5) {
1461 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1463 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1467 _mesa_get_sampler_uniform_value(ir
->sampler
,
1468 ctx
->Shader
.CurrentProgram
,
1469 &brw
->fragment_program
->Base
);
1470 inst
->sampler
= c
->fp
->program
.Base
.SamplerUnits
[inst
->sampler
];
1474 if (ir
->shadow_comparitor
)
1475 inst
->shadow_compare
= true;
1477 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1478 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1480 for (int i
= 0; i
< 4; i
++) {
1481 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1482 fs_reg l
= swizzle_dst
;
1485 if (swiz
== SWIZZLE_ZERO
) {
1486 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1487 } else if (swiz
== SWIZZLE_ONE
) {
1488 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1491 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1492 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1495 this->result
= swizzle_dst
;
1500 fs_visitor::visit(ir_swizzle
*ir
)
1502 ir
->val
->accept(this);
1503 fs_reg val
= this->result
;
1505 if (ir
->type
->vector_elements
== 1) {
1506 this->result
.reg_offset
+= ir
->mask
.x
;
1510 fs_reg result
= fs_reg(this, ir
->type
);
1511 this->result
= result
;
1513 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1514 fs_reg channel
= val
;
1532 channel
.reg_offset
+= swiz
;
1533 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1534 result
.reg_offset
++;
1539 fs_visitor::visit(ir_discard
*ir
)
1541 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1543 assert(ir
->condition
== NULL
); /* FINISHME */
1545 emit(fs_inst(FS_OPCODE_DISCARD
, temp
, temp
));
1546 kill_emitted
= true;
1550 fs_visitor::visit(ir_constant
*ir
)
1552 fs_reg
reg(this, ir
->type
);
1555 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1556 switch (ir
->type
->base_type
) {
1557 case GLSL_TYPE_FLOAT
:
1558 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1560 case GLSL_TYPE_UINT
:
1561 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1564 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1566 case GLSL_TYPE_BOOL
:
1567 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1570 assert(!"Non-float/uint/int/bool constant");
1577 fs_visitor::visit(ir_if
*ir
)
1581 /* Don't point the annotation at the if statement, because then it plus
1582 * the then and else blocks get printed.
1584 this->base_ir
= ir
->condition
;
1586 /* Generate the condition into the condition code. */
1587 ir
->condition
->accept(this);
1588 inst
= emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(brw_null_reg()), this->result
));
1589 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1591 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1592 inst
->predicated
= true;
1594 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1595 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1601 if (!ir
->else_instructions
.is_empty()) {
1602 emit(fs_inst(BRW_OPCODE_ELSE
));
1604 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1605 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1612 emit(fs_inst(BRW_OPCODE_ENDIF
));
1616 fs_visitor::visit(ir_loop
*ir
)
1618 fs_reg counter
= reg_undef
;
1621 this->base_ir
= ir
->counter
;
1622 ir
->counter
->accept(this);
1623 counter
= *(variable_storage(ir
->counter
));
1626 this->base_ir
= ir
->from
;
1627 ir
->from
->accept(this);
1629 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1633 emit(fs_inst(BRW_OPCODE_DO
));
1636 this->base_ir
= ir
->to
;
1637 ir
->to
->accept(this);
1639 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1640 counter
, this->result
));
1642 case ir_binop_equal
:
1643 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1645 case ir_binop_nequal
:
1646 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1648 case ir_binop_gequal
:
1649 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1651 case ir_binop_lequal
:
1652 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1654 case ir_binop_greater
:
1655 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1658 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1661 assert(!"not reached: unknown loop condition");
1666 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1667 inst
->predicated
= true;
1670 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1671 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1677 if (ir
->increment
) {
1678 this->base_ir
= ir
->increment
;
1679 ir
->increment
->accept(this);
1680 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1683 emit(fs_inst(BRW_OPCODE_WHILE
));
1687 fs_visitor::visit(ir_loop_jump
*ir
)
1690 case ir_loop_jump::jump_break
:
1691 emit(fs_inst(BRW_OPCODE_BREAK
));
1693 case ir_loop_jump::jump_continue
:
1694 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1700 fs_visitor::visit(ir_call
*ir
)
1702 assert(!"FINISHME");
1706 fs_visitor::visit(ir_return
*ir
)
1708 assert(!"FINISHME");
1712 fs_visitor::visit(ir_function
*ir
)
1714 /* Ignore function bodies other than main() -- we shouldn't see calls to
1715 * them since they should all be inlined before we get to ir_to_mesa.
1717 if (strcmp(ir
->name
, "main") == 0) {
1718 const ir_function_signature
*sig
;
1721 sig
= ir
->matching_signature(&empty
);
1725 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1726 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1735 fs_visitor::visit(ir_function_signature
*ir
)
1737 assert(!"not reached");
1742 fs_visitor::emit(fs_inst inst
)
1744 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1747 list_inst
->annotation
= this->current_annotation
;
1748 list_inst
->ir
= this->base_ir
;
1750 this->instructions
.push_tail(list_inst
);
1755 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1757 fs_visitor::emit_dummy_fs()
1759 /* Everyone's favorite color. */
1760 emit(fs_inst(BRW_OPCODE_MOV
,
1763 emit(fs_inst(BRW_OPCODE_MOV
,
1766 emit(fs_inst(BRW_OPCODE_MOV
,
1769 emit(fs_inst(BRW_OPCODE_MOV
,
1774 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1779 /* The register location here is relative to the start of the URB
1780 * data. It will get adjusted to be a real location before
1781 * generate_code() time.
1784 fs_visitor::interp_reg(int location
, int channel
)
1786 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1787 int stride
= (channel
& 1) * 4;
1789 assert(urb_setup
[location
] != -1);
1791 return brw_vec1_grf(regnr
, stride
);
1794 /** Emits the interpolation for the varying inputs. */
1796 fs_visitor::emit_interpolation_setup_gen4()
1798 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1800 this->current_annotation
= "compute pixel centers";
1801 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1802 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1803 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1804 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1805 emit(fs_inst(BRW_OPCODE_ADD
,
1807 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1808 fs_reg(brw_imm_v(0x10101010))));
1809 emit(fs_inst(BRW_OPCODE_ADD
,
1811 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1812 fs_reg(brw_imm_v(0x11001100))));
1814 this->current_annotation
= "compute pixel deltas from v0";
1816 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1817 this->delta_y
= this->delta_x
;
1818 this->delta_y
.reg_offset
++;
1820 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1821 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1823 emit(fs_inst(BRW_OPCODE_ADD
,
1826 fs_reg(negate(brw_vec1_grf(1, 0)))));
1827 emit(fs_inst(BRW_OPCODE_ADD
,
1830 fs_reg(negate(brw_vec1_grf(1, 1)))));
1832 this->current_annotation
= "compute pos.w and 1/pos.w";
1833 /* Compute wpos.w. It's always in our setup, since it's needed to
1834 * interpolate the other attributes.
1836 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1837 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1838 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1839 /* Compute the pixel 1/W value from wpos.w. */
1840 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1841 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1842 this->current_annotation
= NULL
;
1845 /** Emits the interpolation for the varying inputs. */
1847 fs_visitor::emit_interpolation_setup_gen6()
1849 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1851 /* If the pixel centers end up used, the setup is the same as for gen4. */
1852 this->current_annotation
= "compute pixel centers";
1853 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1854 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1855 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1856 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1857 emit(fs_inst(BRW_OPCODE_ADD
,
1859 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1860 fs_reg(brw_imm_v(0x10101010))));
1861 emit(fs_inst(BRW_OPCODE_ADD
,
1863 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1864 fs_reg(brw_imm_v(0x11001100))));
1866 this->current_annotation
= "compute 1/pos.w";
1867 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1868 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1869 emit(fs_inst(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
));
1871 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1872 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1874 this->current_annotation
= NULL
;
1878 fs_visitor::emit_fb_writes()
1880 this->current_annotation
= "FB write header";
1881 GLboolean header_present
= GL_TRUE
;
1884 if (intel
->gen
>= 6 &&
1885 !this->kill_emitted
&&
1886 c
->key
.nr_color_regions
== 1) {
1887 header_present
= false;
1890 if (header_present
) {
1895 if (c
->key
.aa_dest_stencil_reg
) {
1896 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1897 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1900 /* Reserve space for color. It'll be filled in per MRT below. */
1904 if (c
->key
.source_depth_to_render_target
) {
1905 if (c
->key
.computes_depth
) {
1906 /* Hand over gl_FragDepth. */
1907 assert(this->frag_depth
);
1908 fs_reg depth
= *(variable_storage(this->frag_depth
));
1910 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1912 /* Pass through the payload depth. */
1913 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1914 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1918 if (c
->key
.dest_depth_reg
) {
1919 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1920 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1923 fs_reg color
= reg_undef
;
1924 if (this->frag_color
)
1925 color
= *(variable_storage(this->frag_color
));
1926 else if (this->frag_data
)
1927 color
= *(variable_storage(this->frag_data
));
1929 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1930 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1931 "FB write target %d",
1933 if (this->frag_color
|| this->frag_data
) {
1934 for (int i
= 0; i
< 4; i
++) {
1935 emit(fs_inst(BRW_OPCODE_MOV
,
1936 fs_reg(MRF
, color_mrf
+ i
),
1942 if (this->frag_color
)
1943 color
.reg_offset
-= 4;
1945 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1946 reg_undef
, reg_undef
));
1947 inst
->target
= target
;
1949 if (target
== c
->key
.nr_color_regions
- 1)
1951 inst
->header_present
= header_present
;
1954 if (c
->key
.nr_color_regions
== 0) {
1955 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1956 reg_undef
, reg_undef
));
1959 inst
->header_present
= header_present
;
1962 this->current_annotation
= NULL
;
1966 fs_visitor::generate_fb_write(fs_inst
*inst
)
1968 GLboolean eot
= inst
->eot
;
1969 struct brw_reg implied_header
;
1971 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1974 brw_push_insn_state(p
);
1975 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1976 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1978 if (inst
->header_present
) {
1979 if (intel
->gen
>= 6) {
1982 brw_vec8_grf(0, 0));
1983 implied_header
= brw_null_reg();
1985 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1990 brw_vec8_grf(1, 0));
1992 implied_header
= brw_null_reg();
1995 brw_pop_insn_state(p
);
1998 8, /* dispatch_width */
1999 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2009 fs_visitor::generate_linterp(fs_inst
*inst
,
2010 struct brw_reg dst
, struct brw_reg
*src
)
2012 struct brw_reg delta_x
= src
[0];
2013 struct brw_reg delta_y
= src
[1];
2014 struct brw_reg interp
= src
[2];
2017 delta_y
.nr
== delta_x
.nr
+ 1 &&
2018 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2019 brw_PLN(p
, dst
, interp
, delta_x
);
2021 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2022 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2027 fs_visitor::generate_math(fs_inst
*inst
,
2028 struct brw_reg dst
, struct brw_reg
*src
)
2032 switch (inst
->opcode
) {
2034 op
= BRW_MATH_FUNCTION_INV
;
2037 op
= BRW_MATH_FUNCTION_RSQ
;
2039 case FS_OPCODE_SQRT
:
2040 op
= BRW_MATH_FUNCTION_SQRT
;
2042 case FS_OPCODE_EXP2
:
2043 op
= BRW_MATH_FUNCTION_EXP
;
2045 case FS_OPCODE_LOG2
:
2046 op
= BRW_MATH_FUNCTION_LOG
;
2049 op
= BRW_MATH_FUNCTION_POW
;
2052 op
= BRW_MATH_FUNCTION_SIN
;
2055 op
= BRW_MATH_FUNCTION_COS
;
2058 assert(!"not reached: unknown math function");
2063 if (inst
->opcode
== FS_OPCODE_POW
) {
2064 brw_MOV(p
, brw_message_reg(3), src
[1]);
2069 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2070 BRW_MATH_SATURATE_NONE
,
2072 BRW_MATH_DATA_VECTOR
,
2073 BRW_MATH_PRECISION_FULL
);
2077 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2081 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2083 if (intel
->gen
>= 5) {
2084 switch (inst
->opcode
) {
2086 if (inst
->shadow_compare
) {
2087 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2089 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2093 if (inst
->shadow_compare
) {
2094 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2096 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2101 switch (inst
->opcode
) {
2103 /* Note that G45 and older determines shadow compare and dispatch width
2104 * from message length for most messages.
2106 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2107 if (inst
->shadow_compare
) {
2108 assert(inst
->mlen
== 5);
2110 assert(inst
->mlen
<= 6);
2114 if (inst
->shadow_compare
) {
2115 assert(inst
->mlen
== 5);
2116 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2118 assert(inst
->mlen
== 8);
2119 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2120 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2125 assert(msg_type
!= -1);
2127 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2136 retype(dst
, BRW_REGISTER_TYPE_UW
),
2138 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2139 SURF_INDEX_TEXTURE(inst
->sampler
),
2151 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2154 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2156 * and we're trying to produce:
2159 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2160 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2161 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2162 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2163 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2164 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2165 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2166 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2168 * and add another set of two more subspans if in 16-pixel dispatch mode.
2170 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2171 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2172 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2173 * between each other. We could probably do it like ddx and swizzle the right
2174 * order later, but bail for now and just produce
2175 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2178 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2180 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2181 BRW_REGISTER_TYPE_F
,
2182 BRW_VERTICAL_STRIDE_2
,
2184 BRW_HORIZONTAL_STRIDE_0
,
2185 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2186 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2187 BRW_REGISTER_TYPE_F
,
2188 BRW_VERTICAL_STRIDE_2
,
2190 BRW_HORIZONTAL_STRIDE_0
,
2191 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2192 brw_ADD(p
, dst
, src0
, negate(src1
));
2196 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2198 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2199 BRW_REGISTER_TYPE_F
,
2200 BRW_VERTICAL_STRIDE_4
,
2202 BRW_HORIZONTAL_STRIDE_0
,
2203 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2204 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2205 BRW_REGISTER_TYPE_F
,
2206 BRW_VERTICAL_STRIDE_4
,
2208 BRW_HORIZONTAL_STRIDE_0
,
2209 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2210 brw_ADD(p
, dst
, src0
, negate(src1
));
2214 fs_visitor::generate_discard(fs_inst
*inst
, struct brw_reg temp
)
2216 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2217 temp
= brw_uw1_reg(temp
.file
, temp
.nr
, 0);
2219 brw_push_insn_state(p
);
2220 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2221 brw_NOT(p
, temp
, brw_mask_reg(1)); /* IMASK */
2222 brw_AND(p
, g0
, temp
, g0
);
2223 brw_pop_insn_state(p
);
2227 fs_visitor::assign_curb_setup()
2229 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2230 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2232 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2233 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2234 fs_inst
*inst
= (fs_inst
*)iter
.get();
2236 for (unsigned int i
= 0; i
< 3; i
++) {
2237 if (inst
->src
[i
].file
== UNIFORM
) {
2238 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2239 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2243 inst
->src
[i
].file
= FIXED_HW_REG
;
2244 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2251 fs_visitor::calculate_urb_setup()
2253 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2258 /* Figure out where each of the incoming setup attributes lands. */
2259 if (intel
->gen
>= 6) {
2260 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2261 if (i
== FRAG_ATTRIB_WPOS
||
2262 (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
))) {
2263 urb_setup
[i
] = urb_next
++;
2267 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2268 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2269 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2272 if (i
>= VERT_RESULT_VAR0
)
2273 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2274 else if (i
<= VERT_RESULT_TEX7
)
2280 urb_setup
[fp_index
] = urb_next
++;
2285 /* Each attribute is 4 setup channels, each of which is half a reg. */
2286 c
->prog_data
.urb_read_length
= urb_next
* 2;
2290 fs_visitor::assign_urb_setup()
2292 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2294 /* Offset all the urb_setup[] index by the actual position of the
2295 * setup regs, now that the location of the constants has been chosen.
2297 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2298 fs_inst
*inst
= (fs_inst
*)iter
.get();
2300 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2303 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2305 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2308 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2312 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2314 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2315 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2321 fs_visitor::assign_regs_trivial()
2324 int hw_reg_mapping
[this->virtual_grf_next
];
2327 hw_reg_mapping
[0] = 0;
2328 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2329 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2330 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2331 this->virtual_grf_sizes
[i
- 1]);
2333 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2335 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2336 fs_inst
*inst
= (fs_inst
*)iter
.get();
2338 assign_reg(hw_reg_mapping
, &inst
->dst
);
2339 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2340 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2343 this->grf_used
= last_grf
+ 1;
2347 fs_visitor::assign_regs()
2350 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2351 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2352 int class_sizes
[base_reg_count
];
2353 int class_count
= 0;
2354 int aligned_pair_class
= -1;
2356 /* Set up the register classes.
2358 * The base registers store a scalar value. For texture samples,
2359 * we get virtual GRFs composed of 4 contiguous hw register. For
2360 * structures and arrays, we store them as contiguous larger things
2361 * than that, though we should be able to do better most of the
2364 class_sizes
[class_count
++] = 1;
2365 if (brw
->has_pln
&& intel
->gen
< 6) {
2366 /* Always set up the (unaligned) pairs for gen5, so we can find
2367 * them for making the aligned pair class.
2369 class_sizes
[class_count
++] = 2;
2371 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2374 for (i
= 0; i
< class_count
; i
++) {
2375 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2378 if (i
== class_count
) {
2379 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2380 fprintf(stderr
, "Object too large to register allocate.\n");
2384 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2388 int ra_reg_count
= 0;
2389 int class_base_reg
[class_count
];
2390 int class_reg_count
[class_count
];
2391 int classes
[class_count
+ 1];
2393 for (int i
= 0; i
< class_count
; i
++) {
2394 class_base_reg
[i
] = ra_reg_count
;
2395 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2396 ra_reg_count
+= class_reg_count
[i
];
2399 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2400 for (int i
= 0; i
< class_count
; i
++) {
2401 classes
[i
] = ra_alloc_reg_class(regs
);
2403 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2404 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2407 /* Add conflicts between our contiguous registers aliasing
2408 * base regs and other register classes' contiguous registers
2409 * that alias base regs, or the base regs themselves for classes[0].
2411 for (int c
= 0; c
<= i
; c
++) {
2412 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2413 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2414 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2418 printf("%d/%d conflicts %d/%d\n",
2419 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2420 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2423 ra_add_reg_conflict(regs
,
2424 class_base_reg
[i
] + i_r
,
2425 class_base_reg
[c
] + c_r
);
2431 /* Add a special class for aligned pairs, which we'll put delta_x/y
2432 * in on gen5 so that we can do PLN.
2434 if (brw
->has_pln
&& intel
->gen
< 6) {
2435 int reg_count
= (base_reg_count
- 1) / 2;
2436 int unaligned_pair_class
= 1;
2437 assert(class_sizes
[unaligned_pair_class
] == 2);
2439 aligned_pair_class
= class_count
;
2440 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2441 class_base_reg
[aligned_pair_class
] = 0;
2442 class_reg_count
[aligned_pair_class
] = 0;
2443 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2445 for (int i
= 0; i
< reg_count
; i
++) {
2446 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2447 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2452 ra_set_finalize(regs
);
2454 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2455 this->virtual_grf_next
);
2456 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2459 ra_set_node_class(g
, 0, classes
[0]);
2461 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2462 for (int c
= 0; c
< class_count
; c
++) {
2463 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2464 if (aligned_pair_class
>= 0 &&
2465 this->delta_x
.reg
== i
) {
2466 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2468 ra_set_node_class(g
, i
, classes
[c
]);
2474 for (int j
= 1; j
< i
; j
++) {
2475 if (virtual_grf_interferes(i
, j
)) {
2476 ra_add_node_interference(g
, i
, j
);
2481 /* FINISHME: Handle spilling */
2482 if (!ra_allocate_no_spills(g
)) {
2483 fprintf(stderr
, "Failed to allocate registers.\n");
2488 /* Get the chosen virtual registers for each node, and map virtual
2489 * regs in the register classes back down to real hardware reg
2492 hw_reg_mapping
[0] = 0; /* unused */
2493 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2494 int reg
= ra_get_node_reg(g
, i
);
2497 for (int c
= 0; c
< class_count
; c
++) {
2498 if (reg
>= class_base_reg
[c
] &&
2499 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2500 hw_reg
= reg
- class_base_reg
[c
];
2505 assert(hw_reg
!= -1);
2506 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2507 last_grf
= MAX2(last_grf
,
2508 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2511 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2512 fs_inst
*inst
= (fs_inst
*)iter
.get();
2514 assign_reg(hw_reg_mapping
, &inst
->dst
);
2515 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2516 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2519 this->grf_used
= last_grf
+ 1;
2526 fs_visitor::calculate_live_intervals()
2528 int num_vars
= this->virtual_grf_next
;
2529 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2530 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2534 for (int i
= 0; i
< num_vars
; i
++) {
2540 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2541 fs_inst
*inst
= (fs_inst
*)iter
.get();
2543 if (inst
->opcode
== BRW_OPCODE_DO
) {
2544 if (loop_depth
++ == 0)
2546 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2549 if (loop_depth
== 0) {
2552 * Patches up any vars marked for use within the loop as
2553 * live until the end. This is conservative, as there
2554 * will often be variables defined and used inside the
2555 * loop but dead at the end of the loop body.
2557 for (int i
= 0; i
< num_vars
; i
++) {
2558 if (use
[i
] == loop_start
) {
2569 for (unsigned int i
= 0; i
< 3; i
++) {
2570 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2571 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2574 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2575 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2582 talloc_free(this->virtual_grf_def
);
2583 talloc_free(this->virtual_grf_use
);
2584 this->virtual_grf_def
= def
;
2585 this->virtual_grf_use
= use
;
2589 * Attempts to move immediate constants into the immediate
2590 * constant slot of following instructions.
2592 * Immediate constants are a bit tricky -- they have to be in the last
2593 * operand slot, you can't do abs/negate on them,
2597 fs_visitor::propagate_constants()
2599 bool progress
= false;
2601 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2602 fs_inst
*inst
= (fs_inst
*)iter
.get();
2604 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2606 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2607 inst
->dst
.type
!= inst
->src
[0].type
)
2610 /* Don't bother with cases where we should have had the
2611 * operation on the constant folded in GLSL already.
2616 /* Found a move of a constant to a GRF. Find anything else using the GRF
2617 * before it's written, and replace it with the constant if we can.
2619 exec_list_iterator scan_iter
= iter
;
2621 for (; scan_iter
.has_next(); scan_iter
.next()) {
2622 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2624 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2625 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2626 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2627 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2631 for (int i
= 2; i
>= 0; i
--) {
2632 if (scan_inst
->src
[i
].file
!= GRF
||
2633 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2634 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2637 /* Don't bother with cases where we should have had the
2638 * operation on the constant folded in GLSL already.
2640 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2643 switch (scan_inst
->opcode
) {
2644 case BRW_OPCODE_MOV
:
2645 scan_inst
->src
[i
] = inst
->src
[0];
2649 case BRW_OPCODE_MUL
:
2650 case BRW_OPCODE_ADD
:
2652 scan_inst
->src
[i
] = inst
->src
[0];
2654 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2655 /* Fit this constant in by commuting the operands */
2656 scan_inst
->src
[0] = scan_inst
->src
[1];
2657 scan_inst
->src
[1] = inst
->src
[0];
2660 case BRW_OPCODE_CMP
:
2662 scan_inst
->src
[i
] = inst
->src
[0];
2668 if (scan_inst
->dst
.file
== GRF
&&
2669 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2670 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2671 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2680 * Must be called after calculate_live_intervales() to remove unused
2681 * writes to registers -- register allocation will fail otherwise
2682 * because something deffed but not used won't be considered to
2683 * interfere with other regs.
2686 fs_visitor::dead_code_eliminate()
2688 bool progress
= false;
2689 int num_vars
= this->virtual_grf_next
;
2690 bool dead
[num_vars
];
2692 for (int i
= 0; i
< num_vars
; i
++) {
2693 /* This would be ">=", but FS_OPCODE_DISCARD has a src == dst where
2694 * it writes dst then reads it as src.
2696 dead
[i
] = this->virtual_grf_def
[i
] > this->virtual_grf_use
[i
];
2699 /* Mark off its interval so it won't interfere with anything. */
2700 this->virtual_grf_def
[i
] = -1;
2701 this->virtual_grf_use
[i
] = -1;
2705 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2706 fs_inst
*inst
= (fs_inst
*)iter
.get();
2708 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2718 fs_visitor::virtual_grf_interferes(int a
, int b
)
2720 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2721 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2723 /* For dead code, just check if the def interferes with the other range. */
2724 if (this->virtual_grf_use
[a
] == -1) {
2725 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2726 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2728 if (this->virtual_grf_use
[b
] == -1) {
2729 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2730 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2733 return start
<= end
;
2736 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2738 struct brw_reg brw_reg
;
2740 switch (reg
->file
) {
2744 brw_reg
= brw_vec8_reg(reg
->file
,
2746 brw_reg
= retype(brw_reg
, reg
->type
);
2749 switch (reg
->type
) {
2750 case BRW_REGISTER_TYPE_F
:
2751 brw_reg
= brw_imm_f(reg
->imm
.f
);
2753 case BRW_REGISTER_TYPE_D
:
2754 brw_reg
= brw_imm_d(reg
->imm
.i
);
2756 case BRW_REGISTER_TYPE_UD
:
2757 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2760 assert(!"not reached");
2765 brw_reg
= reg
->fixed_hw_reg
;
2768 /* Probably unused. */
2769 brw_reg
= brw_null_reg();
2772 assert(!"not reached");
2773 brw_reg
= brw_null_reg();
2777 brw_reg
= brw_abs(brw_reg
);
2779 brw_reg
= negate(brw_reg
);
2785 fs_visitor::generate_code()
2787 unsigned int annotation_len
= 0;
2788 int last_native_inst
= 0;
2789 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2790 int if_stack_depth
= 0, loop_stack_depth
= 0;
2791 int if_depth_in_loop
[16];
2793 if_depth_in_loop
[loop_stack_depth
] = 0;
2795 memset(&if_stack
, 0, sizeof(if_stack
));
2796 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2797 fs_inst
*inst
= (fs_inst
*)iter
.get();
2798 struct brw_reg src
[3], dst
;
2800 for (unsigned int i
= 0; i
< 3; i
++) {
2801 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
2803 dst
= brw_reg_from_fs_reg(&inst
->dst
);
2805 brw_set_conditionalmod(p
, inst
->conditional_mod
);
2806 brw_set_predicate_control(p
, inst
->predicated
);
2808 switch (inst
->opcode
) {
2809 case BRW_OPCODE_MOV
:
2810 brw_MOV(p
, dst
, src
[0]);
2812 case BRW_OPCODE_ADD
:
2813 brw_ADD(p
, dst
, src
[0], src
[1]);
2815 case BRW_OPCODE_MUL
:
2816 brw_MUL(p
, dst
, src
[0], src
[1]);
2819 case BRW_OPCODE_FRC
:
2820 brw_FRC(p
, dst
, src
[0]);
2822 case BRW_OPCODE_RNDD
:
2823 brw_RNDD(p
, dst
, src
[0]);
2825 case BRW_OPCODE_RNDZ
:
2826 brw_RNDZ(p
, dst
, src
[0]);
2829 case BRW_OPCODE_AND
:
2830 brw_AND(p
, dst
, src
[0], src
[1]);
2833 brw_OR(p
, dst
, src
[0], src
[1]);
2835 case BRW_OPCODE_XOR
:
2836 brw_XOR(p
, dst
, src
[0], src
[1]);
2838 case BRW_OPCODE_NOT
:
2839 brw_NOT(p
, dst
, src
[0]);
2841 case BRW_OPCODE_ASR
:
2842 brw_ASR(p
, dst
, src
[0], src
[1]);
2844 case BRW_OPCODE_SHR
:
2845 brw_SHR(p
, dst
, src
[0], src
[1]);
2847 case BRW_OPCODE_SHL
:
2848 brw_SHL(p
, dst
, src
[0], src
[1]);
2851 case BRW_OPCODE_CMP
:
2852 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
2854 case BRW_OPCODE_SEL
:
2855 brw_SEL(p
, dst
, src
[0], src
[1]);
2859 assert(if_stack_depth
< 16);
2860 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
2861 if_depth_in_loop
[loop_stack_depth
]++;
2864 case BRW_OPCODE_ELSE
:
2865 if_stack
[if_stack_depth
- 1] =
2866 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
2868 case BRW_OPCODE_ENDIF
:
2870 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
2871 if_depth_in_loop
[loop_stack_depth
]--;
2875 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
2876 if_depth_in_loop
[loop_stack_depth
] = 0;
2879 case BRW_OPCODE_BREAK
:
2880 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
2881 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2883 case BRW_OPCODE_CONTINUE
:
2884 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
2885 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2888 case BRW_OPCODE_WHILE
: {
2889 struct brw_instruction
*inst0
, *inst1
;
2892 if (intel
->gen
>= 5)
2895 assert(loop_stack_depth
> 0);
2897 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
2898 /* patch all the BREAK/CONT instructions from last BGNLOOP */
2899 while (inst0
> loop_stack
[loop_stack_depth
]) {
2901 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
2902 inst0
->bits3
.if_else
.jump_count
== 0) {
2903 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
2905 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
2906 inst0
->bits3
.if_else
.jump_count
== 0) {
2907 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
2915 case FS_OPCODE_SQRT
:
2916 case FS_OPCODE_EXP2
:
2917 case FS_OPCODE_LOG2
:
2921 generate_math(inst
, dst
, src
);
2923 case FS_OPCODE_LINTERP
:
2924 generate_linterp(inst
, dst
, src
);
2929 generate_tex(inst
, dst
, src
[0]);
2931 case FS_OPCODE_DISCARD
:
2932 generate_discard(inst
, dst
/* src0 == dst */);
2935 generate_ddx(inst
, dst
, src
[0]);
2938 generate_ddy(inst
, dst
, src
[0]);
2940 case FS_OPCODE_FB_WRITE
:
2941 generate_fb_write(inst
);
2944 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
2945 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
2946 brw_opcodes
[inst
->opcode
].name
);
2948 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
2953 if (annotation_len
< p
->nr_insn
) {
2954 annotation_len
*= 2;
2955 if (annotation_len
< 16)
2956 annotation_len
= 16;
2958 this->annotation_string
= talloc_realloc(this->mem_ctx
,
2962 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
2968 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
2969 this->annotation_string
[i
] = inst
->annotation
;
2970 this->annotation_ir
[i
] = inst
->ir
;
2972 last_native_inst
= p
->nr_insn
;
2977 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
2979 struct brw_compile
*p
= &c
->func
;
2980 struct intel_context
*intel
= &brw
->intel
;
2981 GLcontext
*ctx
= &intel
->ctx
;
2982 struct brw_shader
*shader
= NULL
;
2983 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
2991 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
2992 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
2993 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
3000 /* We always use 8-wide mode, at least for now. For one, flow
3001 * control only works in 8-wide. Also, when we're fragment shader
3002 * bound, we're almost always under register pressure as well, so
3003 * 8-wide would save us from the performance cliff of spilling
3006 c
->dispatch_width
= 8;
3008 if (INTEL_DEBUG
& DEBUG_WM
) {
3009 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3010 _mesa_print_ir(shader
->ir
, NULL
);
3014 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3016 fs_visitor
v(c
, shader
);
3021 v
.calculate_urb_setup();
3023 v
.emit_interpolation_setup_gen4();
3025 v
.emit_interpolation_setup_gen6();
3027 /* Generate FS IR for main(). (the visitor only descends into
3028 * functions called "main").
3030 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3031 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3037 v
.assign_curb_setup();
3038 v
.assign_urb_setup();
3044 v
.calculate_live_intervals();
3045 progress
= v
.propagate_constants() || progress
;
3046 progress
= v
.dead_code_eliminate() || progress
;
3050 v
.assign_regs_trivial();
3058 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3063 if (INTEL_DEBUG
& DEBUG_WM
) {
3064 const char *last_annotation_string
= NULL
;
3065 ir_instruction
*last_annotation_ir
= NULL
;
3067 printf("Native code for fragment shader %d:\n", prog
->Name
);
3068 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3069 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3070 last_annotation_ir
= v
.annotation_ir
[i
];
3071 if (last_annotation_ir
) {
3073 last_annotation_ir
->print();
3077 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3078 last_annotation_string
= v
.annotation_string
[i
];
3079 if (last_annotation_string
)
3080 printf(" %s\n", last_annotation_string
);
3082 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3087 c
->prog_data
.total_grf
= v
.grf_used
;
3088 c
->prog_data
.total_scratch
= 0;