src/mesa/drivers/dri/i965/brw_fs.cpp

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 extern "C" {
  29 #include "main/macros.h"
  30 #include "main/shaderobj.h"
  31 #include "program/prog_parameter.h"
  32 #include "program/prog_print.h"
  33 #include "program/prog_optimize.h"
  34 #include "program/hash_table.h"
  35 #include "brw_context.h"
  36 #include "brw_eu.h"
  37 #include "brw_wm.h"
  38 #include "talloc.h"
  39 }
  40 #include "../glsl/glsl_types.h"
  41 #include "../glsl/ir_optimization.h"
  42 #include "../glsl/ir_print_visitor.h"
  43
  44 enum register_file {
  45    ARF = BRW_ARCHITECTURE_REGISTER_FILE,
  46    GRF = BRW_GENERAL_REGISTER_FILE,
  47    MRF = BRW_MESSAGE_REGISTER_FILE,
  48    IMM = BRW_IMMEDIATE_VALUE,
  49    FIXED_HW_REG,
  50    BAD_FILE
  51 };
  52
  53 enum fs_opcodes {
  54    FS_OPCODE_FB_WRITE = 256,
  55    FS_OPCODE_RCP,
  56    FS_OPCODE_RSQ,
  57    FS_OPCODE_SQRT,
  58    FS_OPCODE_EXP2,
  59    FS_OPCODE_LOG2,
  60    FS_OPCODE_POW,
  61    FS_OPCODE_SIN,
  62    FS_OPCODE_COS,
  63    FS_OPCODE_DDX,
  64    FS_OPCODE_DDY,
  65    FS_OPCODE_LINTERP,
  66 };
  67
  68 static int using_new_fs = -1;
  69
  70 struct gl_shader *
  71 brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
  72 {
  73    struct brw_shader *shader;
  74
  75    shader = talloc_zero(NULL, struct brw_shader);
  76    shader->base.Type = type;
  77    shader->base.Name = name;
  78    if (shader) {
  79       _mesa_init_shader(ctx, &shader->base);
  80    }
  81
  82    return &shader->base;
  83 }
  84
  85 struct gl_shader_program *
  86 brw_new_shader_program(GLcontext *ctx, GLuint name)
  87 {
  88    struct brw_shader_program *prog;
  89    prog = talloc_zero(NULL, struct brw_shader_program);
  90    if (prog) {
  91       _mesa_init_shader_program(ctx, &prog->base);
  92    }
  93    return &prog->base;
  94 }
  95
  96 GLboolean
  97 brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
  98 {
  99    if (!_mesa_ir_compile_shader(ctx, shader))
 100       return GL_FALSE;
 101
 102    return GL_TRUE;
 103 }
 104
 105 GLboolean
 106 brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
 107 {
 108    if (using_new_fs == -1)
 109       using_new_fs = getenv("INTEL_NEW_FS") != NULL;
 110
 111    for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
 112       struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
 113
 114       if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) {
 115          void *mem_ctx = talloc_new(NULL);
 116          bool progress;
 117
 118          shader->ir = new(shader) exec_list;
 119          clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
 120
 121          do_mat_op_to_vec(shader->ir);
 122          do_div_to_mul_rcp(shader->ir);
 123          do_sub_to_add_neg(shader->ir);
 124          do_explog_to_explog2(shader->ir);
 125
 126          brw_do_channel_expressions(shader->ir);
 127          brw_do_vector_splitting(shader->ir);
 128
 129          do {
 130             progress = false;
 131
 132             progress = do_common_optimization(shader->ir, true) || progress;
 133          } while (progress);
 134
 135          reparent_ir(shader->ir, shader);
 136          talloc_free(mem_ctx);
 137       }
 138    }
 139
 140    if (!_mesa_ir_link_shader(ctx, prog))
 141       return GL_FALSE;
 142
 143    return GL_TRUE;
 144 }
 145
 146 static int
 147 type_size(const struct glsl_type *type)
 148 {
 149    unsigned int size, i;
 150
 151    switch (type->base_type) {
 152    case GLSL_TYPE_UINT:
 153    case GLSL_TYPE_INT:
 154    case GLSL_TYPE_FLOAT:
 155    case GLSL_TYPE_BOOL:
 156       if (type->is_matrix()) {
 157          /* In case of incoming uniform/varying matrices, match their
 158           * allocation behavior.  FINISHME: We could just use
 159           * glsl_type->components() for variables and temps within the
 160           * shader.
 161           */
 162          return type->matrix_columns * 4;
 163       } else {
 164          return type->vector_elements;
 165       }
 166    case GLSL_TYPE_ARRAY:
 167       /* FINISHME: uniform/varying arrays. */
 168       return type_size(type->fields.array) * type->length;
 169    case GLSL_TYPE_STRUCT:
 170       size = 0;
 171       for (i = 0; i < type->length; i++) {
 172          size += type_size(type->fields.structure[i].type);
 173       }
 174       return size;
 175    case GLSL_TYPE_SAMPLER:
 176       /* Samplers take up no register space, since they're baked in at
 177        * link time.
 178        */
 179       return 0;
 180    default:
 181       assert(!"not reached");
 182       return 0;
 183    }
 184 }
 185
 186 class fs_reg {
 187 public:
 188    /* Callers of this talloc-based new need not call delete. It's
 189     * easier to just talloc_free 'ctx' (or any of its ancestors). */
 190    static void* operator new(size_t size, void *ctx)
 191    {
 192       void *node;
 193
 194       node = talloc_size(ctx, size);
 195       assert(node != NULL);
 196
 197       return node;
 198    }
 199
 200    /** Generic unset register constructor. */
 201    fs_reg()
 202    {
 203       this->file = BAD_FILE;
 204       this->reg = 0;
 205       this->reg_offset = 0;
 206       this->hw_reg = -1;
 207       this->negate = 0;
 208       this->abs = 0;
 209    }
 210
 211    /** Immediate value constructor. */
 212    fs_reg(float f)
 213    {
 214       this->file = IMM;
 215       this->reg = 0;
 216       this->hw_reg = 0;
 217       this->type = BRW_REGISTER_TYPE_F;
 218       this->imm.f = f;
 219       this->negate = 0;
 220       this->abs = 0;
 221    }
 222
 223    /** Immediate value constructor. */
 224    fs_reg(int32_t i)
 225    {
 226       this->file = IMM;
 227       this->reg = 0;
 228       this->hw_reg = 0;
 229       this->type = BRW_REGISTER_TYPE_D;
 230       this->imm.i = i;
 231       this->negate = 0;
 232       this->abs = 0;
 233    }
 234
 235    /** Immediate value constructor. */
 236    fs_reg(uint32_t u)
 237    {
 238       this->file = IMM;
 239       this->reg = 0;
 240       this->hw_reg = 0;
 241       this->type = BRW_REGISTER_TYPE_UD;
 242       this->imm.u = u;
 243       this->negate = 0;
 244       this->abs = 0;
 245    }
 246
 247    /** Fixed brw_reg Immediate value constructor. */
 248    fs_reg(struct brw_reg fixed_hw_reg)
 249    {
 250       this->file = FIXED_HW_REG;
 251       this->fixed_hw_reg = fixed_hw_reg;
 252       this->reg = 0;
 253       this->hw_reg = 0;
 254       this->type = fixed_hw_reg.type;
 255       this->negate = 0;
 256       this->abs = 0;
 257    }
 258
 259    fs_reg(enum register_file file, int hw_reg);
 260    fs_reg(class fs_visitor *v, const struct glsl_type *type);
 261
 262    /** Register file: ARF, GRF, MRF, IMM. */
 263    enum register_file file;
 264    /** Abstract register number.  0 = fixed hw reg */
 265    int reg;
 266    /** Offset within the abstract register. */
 267    int reg_offset;
 268    /** HW register number.  Generally unset until register allocation. */
 269    int hw_reg;
 270    /** Register type.  BRW_REGISTER_TYPE_* */
 271    int type;
 272    bool negate;
 273    bool abs;
 274    struct brw_reg fixed_hw_reg;
 275
 276    /** Value for file == BRW_IMMMEDIATE_FILE */
 277    union {
 278       int32_t i;
 279       uint32_t u;
 280       float f;
 281    } imm;
 282 };
 283
 284 static const fs_reg reg_undef;
 285 static const fs_reg reg_null(ARF, BRW_ARF_NULL);
 286
 287 class fs_inst : public exec_node {
 288 public:
 289    /* Callers of this talloc-based new need not call delete. It's
 290     * easier to just talloc_free 'ctx' (or any of its ancestors). */
 291    static void* operator new(size_t size, void *ctx)
 292    {
 293       void *node;
 294
 295       node = talloc_zero_size(ctx, size);
 296       assert(node != NULL);
 297
 298       return node;
 299    }
 300
 301    fs_inst()
 302    {
 303       this->opcode = BRW_OPCODE_NOP;
 304       this->saturate = false;
 305       this->conditional_mod = BRW_CONDITIONAL_NONE;
 306       this->predicated = false;
 307    }
 308
 309    fs_inst(int opcode, fs_reg dst, fs_reg src0)
 310    {
 311       this->opcode = opcode;
 312       this->dst = dst;
 313       this->src[0] = src0;
 314       this->saturate = false;
 315       this->conditional_mod = BRW_CONDITIONAL_NONE;
 316       this->predicated = false;
 317    }
 318
 319    fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
 320    {
 321       this->opcode = opcode;
 322       this->dst = dst;
 323       this->src[0] = src0;
 324       this->src[1] = src1;
 325       this->saturate = false;
 326       this->conditional_mod = BRW_CONDITIONAL_NONE;
 327       this->predicated = false;
 328    }
 329
 330    fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
 331    {
 332       this->opcode = opcode;
 333       this->dst = dst;
 334       this->src[0] = src0;
 335       this->src[1] = src1;
 336       this->src[2] = src2;
 337       this->saturate = false;
 338       this->conditional_mod = BRW_CONDITIONAL_NONE;
 339       this->predicated = false;
 340    }
 341
 342    int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
 343    fs_reg dst;
 344    fs_reg src[3];
 345    bool saturate;
 346    bool predicated;
 347    int conditional_mod; /**< BRW_CONDITIONAL_* */
 348
 349    /** @{
 350     * Annotation for the generated IR.  One of the two can be set.
 351     */
 352    ir_instruction *ir;
 353    const char *annotation;
 354    /** @} */
 355 };
 356
 357 class fs_visitor : public ir_visitor
 358 {
 359 public:
 360
 361    fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader)
 362    {
 363       this->c = c;
 364       this->p = &c->func;
 365       this->brw = p->brw;
 366       this->intel = &brw->intel;
 367       this->mem_ctx = talloc_new(NULL);
 368       this->shader = shader;
 369       this->fail = false;
 370       this->next_abstract_grf = 1;
 371       this->variable_ht = hash_table_ctor(0,
 372                                           hash_table_pointer_hash,
 373                                           hash_table_pointer_compare);
 374
 375       this->frag_color = NULL;
 376       this->frag_data = NULL;
 377       this->frag_depth = NULL;
 378       this->first_non_payload_grf = 0;
 379
 380       this->current_annotation = NULL;
 381       this->annotation_string = NULL;
 382       this->annotation_ir = NULL;
 383    }
 384    ~fs_visitor()
 385    {
 386       talloc_free(this->mem_ctx);
 387       hash_table_dtor(this->variable_ht);
 388    }
 389
 390    fs_reg *variable_storage(ir_variable *var);
 391
 392    void visit(ir_variable *ir);
 393    void visit(ir_assignment *ir);
 394    void visit(ir_dereference_variable *ir);
 395    void visit(ir_dereference_record *ir);
 396    void visit(ir_dereference_array *ir);
 397    void visit(ir_expression *ir);
 398    void visit(ir_texture *ir);
 399    void visit(ir_if *ir);
 400    void visit(ir_constant *ir);
 401    void visit(ir_swizzle *ir);
 402    void visit(ir_return *ir);
 403    void visit(ir_loop *ir);
 404    void visit(ir_loop_jump *ir);
 405    void visit(ir_discard *ir);
 406    void visit(ir_call *ir);
 407    void visit(ir_function *ir);
 408    void visit(ir_function_signature *ir);
 409
 410    fs_inst *emit(fs_inst inst);
 411    void assign_urb_setup();
 412    void assign_regs();
 413    void generate_code();
 414    void generate_fb_write(fs_inst *inst);
 415    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 416                          struct brw_reg *src);
 417    void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src);
 418
 419    void emit_dummy_fs();
 420    void emit_interpolation();
 421    void emit_pinterp(int location);
 422    void emit_fb_writes();
 423
 424    struct brw_reg interp_reg(int location, int channel);
 425
 426    struct brw_context *brw;
 427    struct intel_context *intel;
 428    struct brw_wm_compile *c;
 429    struct brw_compile *p;
 430    struct brw_shader *shader;
 431    void *mem_ctx;
 432    exec_list instructions;
 433    int next_abstract_grf;
 434    struct hash_table *variable_ht;
 435    ir_variable *frag_color, *frag_data, *frag_depth;
 436    int first_non_payload_grf;
 437
 438    /** @{ debug annotation info */
 439    const char *current_annotation;
 440    ir_instruction *base_ir;
 441    const char **annotation_string;
 442    ir_instruction **annotation_ir;
 443    /** @} */
 444
 445    bool fail;
 446
 447    /* Result of last visit() method. */
 448    fs_reg result;
 449
 450    fs_reg pixel_x;
 451    fs_reg pixel_y;
 452    fs_reg pixel_w;
 453    fs_reg delta_x;
 454    fs_reg delta_y;
 455    fs_reg interp_attrs[64];
 456
 457    int grf_used;
 458
 459 };
 460
 461 /** Fixed HW reg constructor. */
 462 fs_reg::fs_reg(enum register_file file, int hw_reg)
 463 {
 464    this->file = file;
 465    this->reg = 0;
 466    this->reg_offset = 0;
 467    this->hw_reg = hw_reg;
 468    this->type = BRW_REGISTER_TYPE_F;
 469    this->negate = 0;
 470    this->abs = 0;
 471 }
 472
 473 /** Automatic reg constructor. */
 474 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
 475 {
 476    this->file = GRF;
 477    this->reg = v->next_abstract_grf;
 478    this->reg_offset = 0;
 479    v->next_abstract_grf += type_size(type);
 480    this->hw_reg = -1;
 481    this->negate = 0;
 482    this->abs = 0;
 483
 484    switch (type->base_type) {
 485    case GLSL_TYPE_FLOAT:
 486       this->type = BRW_REGISTER_TYPE_F;
 487       break;
 488    case GLSL_TYPE_INT:
 489    case GLSL_TYPE_BOOL:
 490       this->type = BRW_REGISTER_TYPE_D;
 491       break;
 492    case GLSL_TYPE_UINT:
 493       this->type = BRW_REGISTER_TYPE_UD;
 494       break;
 495    default:
 496       assert(!"not reached");
 497       this->type =  BRW_REGISTER_TYPE_F;
 498       break;
 499    }
 500 }
 501
 502 fs_reg *
 503 fs_visitor::variable_storage(ir_variable *var)
 504 {
 505    return (fs_reg *)hash_table_find(this->variable_ht, var);
 506 }
 507
 508 void
 509 fs_visitor::visit(ir_variable *ir)
 510 {
 511    fs_reg *reg = NULL;
 512
 513    /* FINISHME */
 514    assert(ir->mode != ir_var_uniform);
 515
 516    if (strcmp(ir->name, "gl_FragColor") == 0) {
 517       this->frag_color = ir;
 518    } else if (strcmp(ir->name, "gl_FragData") == 0) {
 519       this->frag_data = ir;
 520    } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
 521       this->frag_depth = ir;
 522    }
 523
 524    if (ir->mode == ir_var_in) {
 525       reg = &this->interp_attrs[ir->location];
 526    }
 527
 528    if (!reg)
 529       reg = new(this->mem_ctx) fs_reg(this, ir->type);
 530
 531    hash_table_insert(this->variable_ht, reg, ir);
 532 }
 533
 534 void
 535 fs_visitor::visit(ir_dereference_variable *ir)
 536 {
 537    fs_reg *reg = variable_storage(ir->var);
 538    this->result = *reg;
 539 }
 540
 541 void
 542 fs_visitor::visit(ir_dereference_record *ir)
 543 {
 544    assert(!"FINISHME");
 545 }
 546
 547 void
 548 fs_visitor::visit(ir_dereference_array *ir)
 549 {
 550    assert(!"FINISHME");
 551 }
 552
 553 void
 554 fs_visitor::visit(ir_expression *ir)
 555 {
 556    unsigned int operand;
 557    fs_reg op[2], temp;
 558    fs_reg result;
 559    fs_inst *inst;
 560
 561    for (operand = 0; operand < ir->get_num_operands(); operand++) {
 562       ir->operands[operand]->accept(this);
 563       if (this->result.file == BAD_FILE) {
 564          ir_print_visitor v;
 565          printf("Failed to get tree for expression operand:\n");
 566          ir->operands[operand]->accept(&v);
 567          this->fail = true;
 568       }
 569       op[operand] = this->result;
 570
 571       /* Matrix expression operands should have been broken down to vector
 572        * operations already.
 573        */
 574       assert(!ir->operands[operand]->type->is_matrix());
 575       /* And then those vector operands should have been broken down to scalar.
 576        */
 577       assert(!ir->operands[operand]->type->is_vector());
 578    }
 579
 580    /* Storage for our result.  If our result goes into an assignment, it will
 581     * just get copy-propagated out, so no worries.
 582     */
 583    this->result = fs_reg(this, ir->type);
 584
 585    switch (ir->operation) {
 586    case ir_unop_logic_not:
 587       emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1)));
 588       break;
 589    case ir_unop_neg:
 590       this->result = op[0];
 591       op[0].negate = ~op[0].negate;
 592       break;
 593    case ir_unop_abs:
 594       this->result = op[0];
 595       op[0].abs = true;
 596       break;
 597    case ir_unop_sign:
 598       temp = fs_reg(this, ir->type);
 599
 600       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
 601       inst->conditional_mod = BRW_CONDITIONAL_G;
 602
 603       inst = emit(fs_inst(BRW_OPCODE_CMP, temp, op[0], fs_reg(0.0f)));
 604       inst->conditional_mod = BRW_CONDITIONAL_L;
 605
 606       temp.negate = true;
 607       emit(fs_inst(BRW_OPCODE_ADD, this->result, this->result, temp));
 608
 609       break;
 610    case ir_unop_rcp:
 611       emit(fs_inst(FS_OPCODE_RCP, this->result, op[0]));
 612       break;
 613
 614    case ir_unop_exp2:
 615       emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0]));
 616       break;
 617    case ir_unop_log2:
 618       emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0]));
 619       break;
 620    case ir_unop_exp:
 621    case ir_unop_log:
 622       assert(!"not reached: should be handled by ir_explog_to_explog2");
 623       break;
 624    case ir_unop_sin:
 625       emit(fs_inst(FS_OPCODE_SIN, this->result, op[0]));
 626       break;
 627    case ir_unop_cos:
 628       emit(fs_inst(FS_OPCODE_COS, this->result, op[0]));
 629       break;
 630
 631    case ir_unop_dFdx:
 632       emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
 633       break;
 634    case ir_unop_dFdy:
 635       emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
 636       break;
 637
 638    case ir_binop_add:
 639       emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
 640       break;
 641    case ir_binop_sub:
 642       assert(!"not reached: should be handled by ir_sub_to_add_neg");
 643       break;
 644
 645    case ir_binop_mul:
 646       emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
 647       break;
 648    case ir_binop_div:
 649       assert(!"not reached: should be handled by ir_div_to_mul_rcp");
 650       break;
 651    case ir_binop_mod:
 652       assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
 653       break;
 654
 655    case ir_binop_less:
 656       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 657       inst->conditional_mod = BRW_CONDITIONAL_L;
 658       break;
 659    case ir_binop_greater:
 660       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 661       inst->conditional_mod = BRW_CONDITIONAL_G;
 662       break;
 663    case ir_binop_lequal:
 664       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 665       inst->conditional_mod = BRW_CONDITIONAL_LE;
 666       break;
 667    case ir_binop_gequal:
 668       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 669       inst->conditional_mod = BRW_CONDITIONAL_GE;
 670       break;
 671    case ir_binop_equal:
 672       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 673       inst->conditional_mod = BRW_CONDITIONAL_Z;
 674       break;
 675    case ir_binop_nequal:
 676       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 677       inst->conditional_mod = BRW_CONDITIONAL_NZ;
 678       break;
 679
 680    case ir_binop_logic_xor:
 681       emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
 682       break;
 683
 684    case ir_binop_logic_or:
 685       emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
 686       break;
 687
 688    case ir_binop_logic_and:
 689       emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
 690       break;
 691
 692    case ir_binop_dot:
 693    case ir_binop_cross:
 694    case ir_unop_any:
 695       assert(!"not reached: should be handled by brw_channel_expressions");
 696       break;
 697
 698    case ir_unop_sqrt:
 699       emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0]));
 700       break;
 701
 702    case ir_unop_rsq:
 703       emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0]));
 704       break;
 705
 706    case ir_unop_i2f:
 707    case ir_unop_b2f:
 708    case ir_unop_b2i:
 709       emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
 710       break;
 711    case ir_unop_f2i:
 712       emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0]));
 713       break;
 714    case ir_unop_f2b:
 715    case ir_unop_i2b:
 716       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
 717       inst->conditional_mod = BRW_CONDITIONAL_NZ;
 718
 719    case ir_unop_trunc:
 720       emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
 721       break;
 722    case ir_unop_ceil:
 723       op[0].negate = ~op[0].negate;
 724       inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
 725       this->result.negate = true;
 726       break;
 727    case ir_unop_floor:
 728       inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
 729       break;
 730    case ir_unop_fract:
 731       inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
 732       break;
 733
 734    case ir_binop_min:
 735       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 736       inst->conditional_mod = BRW_CONDITIONAL_L;
 737
 738       inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
 739       inst->predicated = true;
 740       break;
 741    case ir_binop_max:
 742       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
 743       inst->conditional_mod = BRW_CONDITIONAL_G;
 744
 745       inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
 746       inst->predicated = true;
 747       break;
 748
 749    case ir_binop_pow:
 750       inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1]));
 751       break;
 752
 753    case ir_unop_bit_not:
 754    case ir_unop_u2f:
 755    case ir_binop_lshift:
 756    case ir_binop_rshift:
 757    case ir_binop_bit_and:
 758    case ir_binop_bit_xor:
 759    case ir_binop_bit_or:
 760       assert(!"GLSL 1.30 features unsupported");
 761       break;
 762    }
 763 }
 764
 765 void
 766 fs_visitor::visit(ir_assignment *ir)
 767 {
 768    struct fs_reg l, r;
 769    int i;
 770    int write_mask;
 771    fs_inst *inst;
 772
 773    /* FINISHME: arrays on the lhs */
 774    ir->lhs->accept(this);
 775    l = this->result;
 776
 777    ir->rhs->accept(this);
 778    r = this->result;
 779
 780    /* FINISHME: This should really set to the correct maximal writemask for each
 781     * FINISHME: component written (in the loops below).  This case can only
 782     * FINISHME: occur for matrices, arrays, and structures.
 783     */
 784    if (ir->write_mask == 0) {
 785       assert(!ir->lhs->type->is_scalar() && !ir->lhs->type->is_vector());
 786       write_mask = WRITEMASK_XYZW;
 787    } else {
 788       assert(ir->lhs->type->is_vector() || ir->lhs->type->is_scalar());
 789       write_mask = ir->write_mask;
 790    }
 791
 792    assert(l.file != BAD_FILE);
 793    assert(r.file != BAD_FILE);
 794
 795    if (ir->condition) {
 796       /* Get the condition bool into the predicate. */
 797       ir->condition->accept(this);
 798       inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, fs_reg(0)));
 799       inst->conditional_mod = BRW_CONDITIONAL_NZ;
 800    }
 801
 802    for (i = 0; i < type_size(ir->lhs->type); i++) {
 803       if (i < 4 && !(write_mask & (1 << i)))
 804          continue;
 805
 806       inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
 807       if (ir->condition)
 808          inst->predicated = true;
 809       l.reg_offset++;
 810       r.reg_offset++;
 811    }
 812 }
 813
 814 void
 815 fs_visitor::visit(ir_texture *ir)
 816 {
 817    assert(!"FINISHME");
 818 }
 819
 820 void
 821 fs_visitor::visit(ir_swizzle *ir)
 822 {
 823    ir->val->accept(this);
 824    fs_reg val = this->result;
 825
 826    fs_reg result = fs_reg(this, ir->type);
 827    this->result = result;
 828
 829    for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
 830       fs_reg channel = val;
 831       int swiz = 0;
 832
 833       switch (i) {
 834       case 0:
 835          swiz = ir->mask.x;
 836          break;
 837       case 1:
 838          swiz = ir->mask.y;
 839          break;
 840       case 2:
 841          swiz = ir->mask.z;
 842          break;
 843       case 3:
 844          swiz = ir->mask.w;
 845          break;
 846       }
 847
 848       channel.reg_offset += swiz;
 849       emit(fs_inst(BRW_OPCODE_MOV, result, channel));
 850       result.reg_offset++;
 851    }
 852 }
 853
 854 void
 855 fs_visitor::visit(ir_discard *ir)
 856 {
 857    assert(!"FINISHME");
 858 }
 859
 860 void
 861 fs_visitor::visit(ir_constant *ir)
 862 {
 863    fs_reg reg(this, ir->type);
 864    this->result = reg;
 865
 866    for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
 867       switch (ir->type->base_type) {
 868       case GLSL_TYPE_FLOAT:
 869          emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
 870          break;
 871       case GLSL_TYPE_UINT:
 872          emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
 873          break;
 874       case GLSL_TYPE_INT:
 875          emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
 876          break;
 877       case GLSL_TYPE_BOOL:
 878          emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
 879          break;
 880       default:
 881          assert(!"Non-float/uint/int/bool constant");
 882       }
 883       reg.reg_offset++;
 884    }
 885 }
 886
 887 void
 888 fs_visitor::visit(ir_if *ir)
 889 {
 890    assert(!"FINISHME");
 891 }
 892
 893 void
 894 fs_visitor::visit(ir_loop *ir)
 895 {
 896    assert(!"FINISHME");
 897 }
 898
 899 void
 900 fs_visitor::visit(ir_loop_jump *ir)
 901 {
 902    assert(!"FINISHME");
 903 }
 904
 905 void
 906 fs_visitor::visit(ir_call *ir)
 907 {
 908    assert(!"FINISHME");
 909 }
 910
 911 void
 912 fs_visitor::visit(ir_return *ir)
 913 {
 914    assert(!"FINISHME");
 915 }
 916
 917 void
 918 fs_visitor::visit(ir_function *ir)
 919 {
 920    /* Ignore function bodies other than main() -- we shouldn't see calls to
 921     * them since they should all be inlined before we get to ir_to_mesa.
 922     */
 923    if (strcmp(ir->name, "main") == 0) {
 924       const ir_function_signature *sig;
 925       exec_list empty;
 926
 927       sig = ir->matching_signature(&empty);
 928
 929       assert(sig);
 930
 931       foreach_iter(exec_list_iterator, iter, sig->body) {
 932          ir_instruction *ir = (ir_instruction *)iter.get();
 933          this->base_ir = ir;
 934
 935          ir->accept(this);
 936       }
 937    }
 938 }
 939
 940 void
 941 fs_visitor::visit(ir_function_signature *ir)
 942 {
 943    assert(!"not reached");
 944    (void)ir;
 945 }
 946
 947 fs_inst *
 948 fs_visitor::emit(fs_inst inst)
 949 {
 950    fs_inst *list_inst = new(mem_ctx) fs_inst;
 951    *list_inst = inst;
 952
 953    list_inst->annotation = this->current_annotation;
 954    list_inst->ir = this->base_ir;
 955
 956    this->instructions.push_tail(list_inst);
 957
 958    return list_inst;
 959 }
 960
 961 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
 962 void
 963 fs_visitor::emit_dummy_fs()
 964 {
 965    /* Everyone's favorite color. */
 966    emit(fs_inst(BRW_OPCODE_MOV,
 967                 fs_reg(MRF, 2),
 968                 fs_reg(1.0f)));
 969    emit(fs_inst(BRW_OPCODE_MOV,
 970                 fs_reg(MRF, 3),
 971                 fs_reg(0.0f)));
 972    emit(fs_inst(BRW_OPCODE_MOV,
 973                 fs_reg(MRF, 4),
 974                 fs_reg(1.0f)));
 975    emit(fs_inst(BRW_OPCODE_MOV,
 976                 fs_reg(MRF, 5),
 977                 fs_reg(0.0f)));
 978
 979    fs_inst *write;
 980    write = emit(fs_inst(FS_OPCODE_FB_WRITE,
 981                         fs_reg(0),
 982                         fs_reg(0)));
 983 }
 984
 985 /* The register location here is relative to the start of the URB
 986  * data.  It will get adjusted to be a real location before
 987  * generate_code() time.
 988  */
 989 struct brw_reg
 990 fs_visitor::interp_reg(int location, int channel)
 991 {
 992    int regnr = location * 2 + channel / 2;
 993    int stride = (channel & 1) * 4;
 994
 995    return brw_vec1_grf(regnr, stride);
 996 }
 997
 998 /** Emits the interpolation for the varying inputs. */
 999 void
1000 fs_visitor::emit_interpolation()
1001 {
1002    struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1003    /* For now, the source regs for the setup URB data will be unset,
1004     * since we don't know until codegen how many push constants we'll
1005     * use, and therefore what the setup URB offset is.
1006     */
1007    fs_reg src_reg = reg_undef;
1008
1009    this->current_annotation = "compute pixel centers";
1010    this->pixel_x = fs_reg(this, glsl_type::uint_type);
1011    this->pixel_y = fs_reg(this, glsl_type::uint_type);
1012    emit(fs_inst(BRW_OPCODE_ADD,
1013                 this->pixel_x,
1014                 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1015                 fs_reg(brw_imm_v(0x10101010))));
1016    emit(fs_inst(BRW_OPCODE_ADD,
1017                 this->pixel_y,
1018                 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1019                 fs_reg(brw_imm_v(0x11001100))));
1020
1021    this->current_annotation = "compute pixel deltas from v0";
1022    this->delta_x = fs_reg(this, glsl_type::float_type);
1023    this->delta_y = fs_reg(this, glsl_type::float_type);
1024    emit(fs_inst(BRW_OPCODE_ADD,
1025                 this->delta_x,
1026                 this->pixel_x,
1027                 fs_reg(negate(brw_vec1_grf(1, 0)))));
1028    emit(fs_inst(BRW_OPCODE_ADD,
1029                 this->delta_y,
1030                 this->pixel_y,
1031                 fs_reg(brw_vec1_grf(1, 1))));
1032
1033    this->current_annotation = "compute pos.w and 1/pos.w";
1034    /* Compute wpos.  Unlike many other varying inputs, we usually need it
1035     * to produce 1/w, and the varying variable wouldn't show up.
1036     */
1037    fs_reg wpos = fs_reg(this, glsl_type::vec4_type);
1038    this->interp_attrs[FRAG_ATTRIB_WPOS] = wpos;
1039    emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x)); /* FINISHME: ARB_fcc */
1040    wpos.reg_offset++;
1041    emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y)); /* FINISHME: ARB_fcc */
1042    wpos.reg_offset++;
1043    emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
1044                 interp_reg(FRAG_ATTRIB_WPOS, 2)));
1045    wpos.reg_offset++;
1046    emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
1047                 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1048    /* Compute the pixel W value from wpos.w. */
1049    this->pixel_w = fs_reg(this, glsl_type::float_type);
1050    emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos));
1051
1052    /* FINISHME: gl_FrontFacing */
1053
1054    foreach_iter(exec_list_iterator, iter, *this->shader->ir) {
1055       ir_instruction *ir = (ir_instruction *)iter.get();
1056       ir_variable *var = ir->as_variable();
1057
1058       if (!var)
1059          continue;
1060
1061       if (var->mode != ir_var_in)
1062          continue;
1063
1064       /* If it's already set up (WPOS), skip. */
1065       if (var->location == 0)
1066          continue;
1067
1068       this->current_annotation = talloc_asprintf(this->mem_ctx,
1069                                                  "interpolate %s "
1070                                                  "(FRAG_ATTRIB[%d])",
1071                                                  var->name,
1072                                                  var->location);
1073       emit_pinterp(var->location);
1074    }
1075    this->current_annotation = NULL;
1076 }
1077
1078 void
1079 fs_visitor::emit_pinterp(int location)
1080 {
1081    fs_reg interp_attr = fs_reg(this, glsl_type::vec4_type);
1082    this->interp_attrs[location] = interp_attr;
1083
1084    for (unsigned int i = 0; i < 4; i++) {
1085       struct brw_reg interp = interp_reg(location, i);
1086       emit(fs_inst(FS_OPCODE_LINTERP,
1087                    interp_attr,
1088                    this->delta_x,
1089                    this->delta_y,
1090                    fs_reg(interp)));
1091       interp_attr.reg_offset++;
1092    }
1093    interp_attr.reg_offset -= 4;
1094
1095    for (unsigned int i = 0; i < 4; i++) {
1096       emit(fs_inst(BRW_OPCODE_MUL,
1097                    interp_attr,
1098                    interp_attr,
1099                    this->pixel_w));
1100       interp_attr.reg_offset++;
1101    }
1102 }
1103
1104 void
1105 fs_visitor::emit_fb_writes()
1106 {
1107    this->current_annotation = "FB write";
1108
1109    assert(this->frag_color || !"FINISHME: MRT");
1110    fs_reg color = *(variable_storage(this->frag_color));
1111
1112    for (int i = 0; i < 4; i++) {
1113       emit(fs_inst(BRW_OPCODE_MOV,
1114                    fs_reg(MRF, 2 + i),
1115                    color));
1116       color.reg_offset++;
1117    }
1118
1119    emit(fs_inst(FS_OPCODE_FB_WRITE,
1120                 fs_reg(0),
1121                 fs_reg(0)));
1122
1123    this->current_annotation = NULL;
1124 }
1125
1126 void
1127 fs_visitor::generate_fb_write(fs_inst *inst)
1128 {
1129    GLboolean eot = 1; /* FINISHME: MRT */
1130    /* FINISHME: AADS */
1131
1132    /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1133     * move, here's g1.
1134     */
1135    brw_push_insn_state(p);
1136    brw_set_mask_control(p, BRW_MASK_DISABLE);
1137    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1138    brw_MOV(p,
1139            brw_message_reg(1),
1140            brw_vec8_grf(1, 0));
1141    brw_pop_insn_state(p);
1142
1143    int nr = 2 + 4;
1144
1145    brw_fb_WRITE(p,
1146                 8, /* dispatch_width */
1147                 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
1148                 0, /* base MRF */
1149                 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
1150                 0, /* FINISHME: MRT target */
1151                 nr,
1152                 0,
1153                 eot);
1154 }
1155
1156 void
1157 fs_visitor::generate_linterp(fs_inst *inst,
1158                              struct brw_reg dst, struct brw_reg *src)
1159 {
1160    struct brw_reg delta_x = src[0];
1161    struct brw_reg delta_y = src[1];
1162    struct brw_reg interp = src[2];
1163
1164    if (brw->has_pln &&
1165        delta_y.nr == delta_x.nr + 1 &&
1166        (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
1167       brw_PLN(p, dst, interp, delta_x);
1168    } else {
1169       brw_LINE(p, brw_null_reg(), interp, delta_x);
1170       brw_MAC(p, dst, suboffset(interp, 1), delta_y);
1171    }
1172 }
1173
1174 void
1175 fs_visitor::generate_math(fs_inst *inst,
1176                           struct brw_reg dst, struct brw_reg *src)
1177 {
1178    int op;
1179
1180    switch (inst->opcode) {
1181    case FS_OPCODE_RCP:
1182       op = BRW_MATH_FUNCTION_INV;
1183       break;
1184    case FS_OPCODE_RSQ:
1185       op = BRW_MATH_FUNCTION_RSQ;
1186       break;
1187    case FS_OPCODE_SQRT:
1188       op = BRW_MATH_FUNCTION_SQRT;
1189       break;
1190    case FS_OPCODE_EXP2:
1191       op = BRW_MATH_FUNCTION_EXP;
1192       break;
1193    case FS_OPCODE_LOG2:
1194       op = BRW_MATH_FUNCTION_LOG;
1195       break;
1196    case FS_OPCODE_POW:
1197       op = BRW_MATH_FUNCTION_POW;
1198       break;
1199    case FS_OPCODE_SIN:
1200       op = BRW_MATH_FUNCTION_SIN;
1201       break;
1202    case FS_OPCODE_COS:
1203       op = BRW_MATH_FUNCTION_COS;
1204       break;
1205    default:
1206       assert(!"not reached: unknown math function");
1207       op = 0;
1208       break;
1209    }
1210
1211    if (inst->opcode == FS_OPCODE_POW) {
1212       brw_MOV(p, brw_message_reg(3), src[1]);
1213    }
1214
1215    brw_math(p, dst,
1216             op,
1217             inst->saturate ? BRW_MATH_SATURATE_SATURATE :
1218             BRW_MATH_SATURATE_NONE,
1219             2, src[0],
1220             BRW_MATH_DATA_VECTOR,
1221             BRW_MATH_PRECISION_FULL);
1222 }
1223
1224 static void
1225 trivial_assign_reg(int header_size, fs_reg *reg)
1226 {
1227    if (reg->file == GRF && reg->reg != 0) {
1228       reg->hw_reg = header_size + reg->reg - 1 + reg->reg_offset;
1229       reg->reg = 0;
1230    }
1231 }
1232
1233 void
1234 fs_visitor::assign_urb_setup()
1235 {
1236    int urb_start = c->key.nr_payload_regs; /* FINISHME: push constants */
1237    int interp_reg_nr[FRAG_ATTRIB_MAX];
1238
1239    c->prog_data.urb_read_length = 0;
1240
1241    /* Figure out where each of the incoming setup attributes lands. */
1242    for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
1243       interp_reg_nr[i] = -1;
1244
1245       if (i != FRAG_ATTRIB_WPOS &&
1246           !(brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)))
1247          continue;
1248
1249       /* Each attribute is 4 setup channels, each of which is half a reg. */
1250       interp_reg_nr[i] = urb_start + c->prog_data.urb_read_length;
1251       c->prog_data.urb_read_length += 2;
1252    }
1253
1254    /* Map the register numbers for FS_OPCODE_LINTERP so that it uses
1255     * the correct setup input.
1256     */
1257    foreach_iter(exec_list_iterator, iter, this->instructions) {
1258       fs_inst *inst = (fs_inst *)iter.get();
1259
1260       if (inst->opcode != FS_OPCODE_LINTERP)
1261          continue;
1262
1263       assert(inst->src[2].file == FIXED_HW_REG);
1264
1265       int location = inst->src[2].fixed_hw_reg.nr / 2;
1266       assert(interp_reg_nr[location] != -1);
1267       inst->src[2].fixed_hw_reg.nr = (interp_reg_nr[location] +
1268                                       (inst->src[2].fixed_hw_reg.nr & 1));
1269    }
1270
1271    this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
1272 }
1273
1274 void
1275 fs_visitor::assign_regs()
1276 {
1277    int header_size = this->first_non_payload_grf;
1278    int last_grf = 0;
1279
1280    /* FINISHME: trivial assignment of register numbers */
1281    foreach_iter(exec_list_iterator, iter, this->instructions) {
1282       fs_inst *inst = (fs_inst *)iter.get();
1283
1284       trivial_assign_reg(header_size, &inst->dst);
1285       trivial_assign_reg(header_size, &inst->src[0]);
1286       trivial_assign_reg(header_size, &inst->src[1]);
1287
1288       last_grf = MAX2(last_grf, inst->dst.hw_reg);
1289       last_grf = MAX2(last_grf, inst->src[0].hw_reg);
1290       last_grf = MAX2(last_grf, inst->src[1].hw_reg);
1291    }
1292
1293    this->grf_used = last_grf;
1294 }
1295
1296 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
1297 {
1298    struct brw_reg brw_reg;
1299
1300    switch (reg->file) {
1301    case GRF:
1302    case ARF:
1303    case MRF:
1304       brw_reg = brw_vec8_reg(reg->file,
1305                             reg->hw_reg, 0);
1306       brw_reg = retype(brw_reg, reg->type);
1307       break;
1308    case IMM:
1309       switch (reg->type) {
1310       case BRW_REGISTER_TYPE_F:
1311          brw_reg = brw_imm_f(reg->imm.f);
1312          break;
1313       case BRW_REGISTER_TYPE_D:
1314          brw_reg = brw_imm_f(reg->imm.i);
1315          break;
1316       case BRW_REGISTER_TYPE_UD:
1317          brw_reg = brw_imm_f(reg->imm.u);
1318          break;
1319       default:
1320          assert(!"not reached");
1321          break;
1322       }
1323       break;
1324    case FIXED_HW_REG:
1325       brw_reg = reg->fixed_hw_reg;
1326       break;
1327    case BAD_FILE:
1328       /* Probably unused. */
1329       brw_reg = brw_null_reg();
1330    }
1331    if (reg->abs)
1332       brw_reg = brw_abs(brw_reg);
1333    if (reg->negate)
1334       brw_reg = negate(brw_reg);
1335
1336    return brw_reg;
1337 }
1338
1339 void
1340 fs_visitor::generate_code()
1341 {
1342    unsigned int annotation_len = 0;
1343    int last_native_inst = 0;
1344
1345    foreach_iter(exec_list_iterator, iter, this->instructions) {
1346       fs_inst *inst = (fs_inst *)iter.get();
1347       struct brw_reg src[3], dst;
1348
1349       for (unsigned int i = 0; i < 3; i++) {
1350          src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1351       }
1352       dst = brw_reg_from_fs_reg(&inst->dst);
1353
1354       brw_set_conditionalmod(p, inst->conditional_mod);
1355       brw_set_predicate_control(p, inst->predicated);
1356
1357       switch (inst->opcode) {
1358       case BRW_OPCODE_MOV:
1359          brw_MOV(p, dst, src[0]);
1360          break;
1361       case BRW_OPCODE_ADD:
1362          brw_ADD(p, dst, src[0], src[1]);
1363          break;
1364       case BRW_OPCODE_MUL:
1365          brw_MUL(p, dst, src[0], src[1]);
1366          break;
1367       case FS_OPCODE_RCP:
1368       case FS_OPCODE_RSQ:
1369       case FS_OPCODE_SQRT:
1370       case FS_OPCODE_EXP2:
1371       case FS_OPCODE_LOG2:
1372       case FS_OPCODE_POW:
1373       case FS_OPCODE_SIN:
1374       case FS_OPCODE_COS:
1375          generate_math(inst, dst, src);
1376          break;
1377       case FS_OPCODE_LINTERP:
1378          generate_linterp(inst, dst, src);
1379          break;
1380       case FS_OPCODE_FB_WRITE:
1381          generate_fb_write(inst);
1382          break;
1383       default:
1384          assert(!"not reached");
1385       }
1386
1387       if (annotation_len < p->nr_insn) {
1388          annotation_len *= 2;
1389          if (annotation_len < 16)
1390             annotation_len = 16;
1391
1392          this->annotation_string = talloc_realloc(this->mem_ctx,
1393                                                   annotation_string,
1394                                                   const char *,
1395                                                   annotation_len);
1396          this->annotation_ir = talloc_realloc(this->mem_ctx,
1397                                               annotation_ir,
1398                                               ir_instruction *,
1399                                               annotation_len);
1400       }
1401
1402       for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
1403          this->annotation_string[i] = inst->annotation;
1404          this->annotation_ir[i] = inst->ir;
1405       }
1406       last_native_inst = p->nr_insn;
1407    }
1408 }
1409
1410 GLboolean
1411 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
1412 {
1413    struct brw_compile *p = &c->func;
1414    struct intel_context *intel = &brw->intel;
1415    GLcontext *ctx = &intel->ctx;
1416    struct brw_shader *shader = NULL;
1417    struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
1418
1419    if (!prog)
1420       return GL_FALSE;
1421
1422    if (!using_new_fs)
1423       return GL_FALSE;
1424
1425    for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) {
1426       if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) {
1427          shader = (struct brw_shader *)prog->_LinkedShaders[i];
1428          break;
1429       }
1430    }
1431    if (!shader)
1432       return GL_FALSE;
1433
1434    /* We always use 8-wide mode, at least for now.  For one, flow
1435     * control only works in 8-wide.  Also, when we're fragment shader
1436     * bound, we're almost always under register pressure as well, so
1437     * 8-wide would save us from the performance cliff of spilling
1438     * regs.
1439     */
1440    c->dispatch_width = 8;
1441
1442    if (INTEL_DEBUG & DEBUG_WM) {
1443       printf("GLSL IR for native fragment shader %d:\n", prog->Name);
1444       _mesa_print_ir(shader->ir, NULL);
1445       printf("\n");
1446    }
1447
1448    /* Now the main event: Visit the shader IR and generate our FS IR for it.
1449     */
1450    fs_visitor v(c, shader);
1451
1452    if (0) {
1453       v.emit_dummy_fs();
1454    } else {
1455       v.emit_interpolation();
1456
1457       /* Generate FS IR for main().  (the visitor only descends into
1458        * functions called "main").
1459        */
1460       foreach_iter(exec_list_iterator, iter, *shader->ir) {
1461          ir_instruction *ir = (ir_instruction *)iter.get();
1462          v.base_ir = ir;
1463          ir->accept(&v);
1464       }
1465
1466       if (v.fail)
1467          return GL_FALSE;
1468
1469       v.emit_fb_writes();
1470       v.assign_urb_setup();
1471       v.assign_regs();
1472    }
1473
1474    v.generate_code();
1475
1476    if (INTEL_DEBUG & DEBUG_WM) {
1477       const char *last_annotation_string = NULL;
1478       ir_instruction *last_annotation_ir = NULL;
1479
1480       printf("Native code for fragment shader %d:\n", prog->Name);
1481       for (unsigned int i = 0; i < p->nr_insn; i++) {
1482          if (last_annotation_ir != v.annotation_ir[i]) {
1483             last_annotation_ir = v.annotation_ir[i];
1484             if (last_annotation_ir) {
1485                printf("   ");
1486                last_annotation_ir->print();
1487                printf("\n");
1488             }
1489          }
1490          if (last_annotation_string != v.annotation_string[i]) {
1491             last_annotation_string = v.annotation_string[i];
1492             if (last_annotation_string)
1493                printf("   %s\n", last_annotation_string);
1494          }
1495          brw_disasm(stdout, &p->store[i], intel->gen);
1496       }
1497       printf("\n");
1498    }
1499
1500    c->prog_data.nr_params = 0; /* FINISHME */
1501    c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
1502    c->prog_data.curb_read_length = 0; /* FINISHME */
1503    c->prog_data.total_grf = v.grf_used;
1504    c->prog_data.total_scratch = 0;
1505
1506    return GL_TRUE;
1507 }