2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct intel_context
*intel
= intel_context(ctx
);
94 for (unsigned i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
95 struct brw_shader
*shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
97 if (shader
->base
.Type
== GL_FRAGMENT_SHADER
) {
98 void *mem_ctx
= talloc_new(NULL
);
102 talloc_free(shader
->ir
);
103 shader
->ir
= new(shader
) exec_list
;
104 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
106 do_mat_op_to_vec(shader
->ir
);
107 do_mod_to_fract(shader
->ir
);
108 do_div_to_mul_rcp(shader
->ir
);
109 do_sub_to_add_neg(shader
->ir
);
110 do_explog_to_explog2(shader
->ir
);
111 do_lower_texture_projection(shader
->ir
);
112 brw_do_cubemap_normalize(shader
->ir
);
117 brw_do_channel_expressions(shader
->ir
);
118 brw_do_vector_splitting(shader
->ir
);
120 progress
= do_lower_jumps(shader
->ir
, true, true,
121 true, /* main return */
122 false, /* continue */
126 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
128 progress
= lower_noise(shader
->ir
) || progress
;
130 lower_variable_index_to_cond_assign(shader
->ir
,
132 GL_TRUE
, /* output */
134 GL_TRUE
/* uniform */
136 if (intel
->gen
== 6) {
137 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
141 validate_ir_tree(shader
->ir
);
143 reparent_ir(shader
->ir
, shader
->ir
);
144 talloc_free(mem_ctx
);
148 if (!_mesa_ir_link_shader(ctx
, prog
))
155 type_size(const struct glsl_type
*type
)
157 unsigned int size
, i
;
159 switch (type
->base_type
) {
162 case GLSL_TYPE_FLOAT
:
164 return type
->components();
165 case GLSL_TYPE_ARRAY
:
166 return type_size(type
->fields
.array
) * type
->length
;
167 case GLSL_TYPE_STRUCT
:
169 for (i
= 0; i
< type
->length
; i
++) {
170 size
+= type_size(type
->fields
.structure
[i
].type
);
173 case GLSL_TYPE_SAMPLER
:
174 /* Samplers take up no register space, since they're baked in at
179 assert(!"not reached");
184 static const fs_reg reg_undef
;
185 static const fs_reg
reg_null(ARF
, BRW_ARF_NULL
);
188 fs_visitor::virtual_grf_alloc(int size
)
190 if (virtual_grf_array_size
<= virtual_grf_next
) {
191 if (virtual_grf_array_size
== 0)
192 virtual_grf_array_size
= 16;
194 virtual_grf_array_size
*= 2;
195 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
196 int, virtual_grf_array_size
);
198 /* This slot is always unused. */
199 virtual_grf_sizes
[0] = 0;
201 virtual_grf_sizes
[virtual_grf_next
] = size
;
202 return virtual_grf_next
++;
205 /** Fixed HW reg constructor. */
206 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
210 this->hw_reg
= hw_reg
;
211 this->type
= BRW_REGISTER_TYPE_F
;
215 brw_type_for_base_type(const struct glsl_type
*type
)
217 switch (type
->base_type
) {
218 case GLSL_TYPE_FLOAT
:
219 return BRW_REGISTER_TYPE_F
;
222 return BRW_REGISTER_TYPE_D
;
224 return BRW_REGISTER_TYPE_UD
;
225 case GLSL_TYPE_ARRAY
:
226 case GLSL_TYPE_STRUCT
:
227 /* These should be overridden with the type of the member when
228 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
229 * way to trip up if we don't.
231 return BRW_REGISTER_TYPE_UD
;
233 assert(!"not reached");
234 return BRW_REGISTER_TYPE_F
;
238 /** Automatic reg constructor. */
239 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
244 this->reg
= v
->virtual_grf_alloc(type_size(type
));
245 this->reg_offset
= 0;
246 this->type
= brw_type_for_base_type(type
);
250 fs_visitor::variable_storage(ir_variable
*var
)
252 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
255 /* Our support for uniforms is piggy-backed on the struct
256 * gl_fragment_program, because that's where the values actually
257 * get stored, rather than in some global gl_shader_program uniform
261 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
263 unsigned int offset
= 0;
266 if (type
->is_matrix()) {
267 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
268 type
->vector_elements
,
271 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
272 offset
+= setup_uniform_values(loc
+ offset
, column
);
278 switch (type
->base_type
) {
279 case GLSL_TYPE_FLOAT
:
283 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
284 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
285 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
289 case GLSL_TYPE_STRUCT
:
290 for (unsigned int i
= 0; i
< type
->length
; i
++) {
291 offset
+= setup_uniform_values(loc
+ offset
,
292 type
->fields
.structure
[i
].type
);
296 case GLSL_TYPE_ARRAY
:
297 for (unsigned int i
= 0; i
< type
->length
; i
++) {
298 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
302 case GLSL_TYPE_SAMPLER
:
303 /* The sampler takes up a slot, but we don't use any values from it. */
307 assert(!"not reached");
313 /* Our support for builtin uniforms is even scarier than non-builtin.
314 * It sits on top of the PROG_STATE_VAR parameters that are
315 * automatically updated from GL context state.
318 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
320 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
322 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
323 statevar
= &_mesa_builtin_uniform_desc
[i
];
324 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
328 if (!statevar
->name
) {
330 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
335 if (ir
->type
->is_array()) {
336 array_count
= ir
->type
->length
;
341 for (int a
= 0; a
< array_count
; a
++) {
342 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
343 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
344 int tokens
[STATE_LENGTH
];
346 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
347 if (ir
->type
->is_array()) {
351 /* This state reference has already been setup by ir_to_mesa,
352 * but we'll get the same index back here.
354 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
355 (gl_state_index
*)tokens
);
356 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
358 /* Add each of the unique swizzles of the element as a
359 * parameter. This'll end up matching the expected layout of
360 * the array/matrix/structure we're trying to fill in.
363 for (unsigned int i
= 0; i
< 4; i
++) {
364 int swiz
= GET_SWZ(element
->swizzle
, i
);
365 if (swiz
== last_swiz
)
369 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
376 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
378 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
380 fs_reg neg_y
= this->pixel_y
;
384 if (ir
->pixel_center_integer
) {
385 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
387 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
392 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
393 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
395 fs_reg pixel_y
= this->pixel_y
;
396 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
398 if (!ir
->origin_upper_left
) {
399 pixel_y
.negate
= true;
400 offset
+= c
->key
.drawable_height
- 1.0;
403 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
408 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
409 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
412 /* gl_FragCoord.w: Already set up in emit_interpolation */
413 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
419 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
421 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
422 /* Interpolation is always in floating point regs. */
423 reg
->type
= BRW_REGISTER_TYPE_F
;
426 unsigned int array_elements
;
427 const glsl_type
*type
;
429 if (ir
->type
->is_array()) {
430 array_elements
= ir
->type
->length
;
431 if (array_elements
== 0) {
434 type
= ir
->type
->fields
.array
;
440 int location
= ir
->location
;
441 for (unsigned int i
= 0; i
< array_elements
; i
++) {
442 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
443 if (urb_setup
[location
] == -1) {
444 /* If there's no incoming setup data for this slot, don't
445 * emit interpolation for it.
447 attr
.reg_offset
+= type
->vector_elements
;
452 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
453 struct brw_reg interp
= interp_reg(location
, c
);
454 emit(fs_inst(FS_OPCODE_LINTERP
,
462 if (intel
->gen
< 6) {
463 attr
.reg_offset
-= type
->vector_elements
;
464 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
465 emit(fs_inst(BRW_OPCODE_MUL
,
480 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
482 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
484 /* The frontfacing comes in as a bit in the thread payload. */
485 if (intel
->gen
>= 6) {
486 emit(fs_inst(BRW_OPCODE_ASR
,
488 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
490 emit(fs_inst(BRW_OPCODE_NOT
,
493 emit(fs_inst(BRW_OPCODE_AND
,
498 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
499 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
500 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
503 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
507 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
508 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
515 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
527 assert(!"not reached: bad math opcode");
531 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
532 * might be able to do better by doing execsize = 1 math and then
533 * expanding that result out, but we would need to be careful with
536 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
537 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
538 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
542 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
544 if (intel
->gen
< 6) {
553 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
558 assert(opcode
== FS_OPCODE_POW
);
560 if (intel
->gen
>= 6) {
561 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
562 if (src0
.file
== UNIFORM
) {
563 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
564 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
568 if (src1
.file
== UNIFORM
) {
569 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
570 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
574 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
576 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
577 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null
));
579 inst
->base_mrf
= base_mrf
;
586 fs_visitor::visit(ir_variable
*ir
)
590 if (variable_storage(ir
))
593 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
594 this->frag_color
= ir
;
595 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
596 this->frag_data
= ir
;
597 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
598 this->frag_depth
= ir
;
601 if (ir
->mode
== ir_var_in
) {
602 if (!strcmp(ir
->name
, "gl_FragCoord")) {
603 reg
= emit_fragcoord_interpolation(ir
);
604 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
605 reg
= emit_frontfacing_interpolation(ir
);
607 reg
= emit_general_interpolation(ir
);
610 hash_table_insert(this->variable_ht
, reg
, ir
);
614 if (ir
->mode
== ir_var_uniform
) {
615 int param_index
= c
->prog_data
.nr_params
;
617 if (!strncmp(ir
->name
, "gl_", 3)) {
618 setup_builtin_uniform_values(ir
);
620 setup_uniform_values(ir
->location
, ir
->type
);
623 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
627 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
629 hash_table_insert(this->variable_ht
, reg
, ir
);
633 fs_visitor::visit(ir_dereference_variable
*ir
)
635 fs_reg
*reg
= variable_storage(ir
->var
);
640 fs_visitor::visit(ir_dereference_record
*ir
)
642 const glsl_type
*struct_type
= ir
->record
->type
;
644 ir
->record
->accept(this);
646 unsigned int offset
= 0;
647 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
648 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
650 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
652 this->result
.reg_offset
+= offset
;
653 this->result
.type
= brw_type_for_base_type(ir
->type
);
657 fs_visitor::visit(ir_dereference_array
*ir
)
662 ir
->array
->accept(this);
663 index
= ir
->array_index
->as_constant();
665 element_size
= type_size(ir
->type
);
666 this->result
.type
= brw_type_for_base_type(ir
->type
);
669 assert(this->result
.file
== UNIFORM
||
670 (this->result
.file
== GRF
&&
671 this->result
.reg
!= 0));
672 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
674 assert(!"FINISHME: non-constant array element");
679 fs_visitor::visit(ir_expression
*ir
)
681 unsigned int operand
;
686 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
687 ir
->operands
[operand
]->accept(this);
688 if (this->result
.file
== BAD_FILE
) {
690 printf("Failed to get tree for expression operand:\n");
691 ir
->operands
[operand
]->accept(&v
);
694 op
[operand
] = this->result
;
696 /* Matrix expression operands should have been broken down to vector
697 * operations already.
699 assert(!ir
->operands
[operand
]->type
->is_matrix());
700 /* And then those vector operands should have been broken down to scalar.
702 assert(!ir
->operands
[operand
]->type
->is_vector());
705 /* Storage for our result. If our result goes into an assignment, it will
706 * just get copy-propagated out, so no worries.
708 this->result
= fs_reg(this, ir
->type
);
710 switch (ir
->operation
) {
711 case ir_unop_logic_not
:
712 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
713 * ones complement of the whole register, not just bit 0.
715 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], fs_reg(-1)));
718 op
[0].negate
= !op
[0].negate
;
719 this->result
= op
[0];
723 this->result
= op
[0];
726 temp
= fs_reg(this, ir
->type
);
728 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
730 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
731 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
732 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
733 inst
->predicated
= true;
735 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
736 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
737 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
738 inst
->predicated
= true;
742 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
746 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
749 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
753 assert(!"not reached: should be handled by ir_explog_to_explog2");
756 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
759 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
763 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
766 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
770 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
773 assert(!"not reached: should be handled by ir_sub_to_add_neg");
777 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
780 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
783 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
787 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
788 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
789 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
791 case ir_binop_greater
:
792 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
793 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
794 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
796 case ir_binop_lequal
:
797 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
798 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
799 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
801 case ir_binop_gequal
:
802 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
803 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
804 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
807 case ir_binop_all_equal
: /* same as nequal for scalars */
808 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
809 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
810 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
812 case ir_binop_nequal
:
813 case ir_binop_any_nequal
: /* same as nequal for scalars */
814 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
815 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
816 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
819 case ir_binop_logic_xor
:
820 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
823 case ir_binop_logic_or
:
824 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
827 case ir_binop_logic_and
:
828 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
834 assert(!"not reached: should be handled by brw_fs_channel_expressions");
838 assert(!"not reached: should be handled by lower_noise");
842 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
846 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
853 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
857 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
858 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
859 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
860 this->result
, fs_reg(1)));
864 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
867 op
[0].negate
= !op
[0].negate
;
868 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
869 this->result
.negate
= true;
872 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
875 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
877 case ir_unop_round_even
:
878 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
882 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
883 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
885 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
886 inst
->predicated
= true;
889 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
890 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
892 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
893 inst
->predicated
= true;
897 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
900 case ir_unop_bit_not
:
902 case ir_binop_lshift
:
903 case ir_binop_rshift
:
904 case ir_binop_bit_and
:
905 case ir_binop_bit_xor
:
906 case ir_binop_bit_or
:
907 assert(!"GLSL 1.30 features unsupported");
913 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
914 const glsl_type
*type
, bool predicated
)
916 switch (type
->base_type
) {
917 case GLSL_TYPE_FLOAT
:
921 for (unsigned int i
= 0; i
< type
->components(); i
++) {
922 l
.type
= brw_type_for_base_type(type
);
923 r
.type
= brw_type_for_base_type(type
);
925 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
926 inst
->predicated
= predicated
;
932 case GLSL_TYPE_ARRAY
:
933 for (unsigned int i
= 0; i
< type
->length
; i
++) {
934 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
937 case GLSL_TYPE_STRUCT
:
938 for (unsigned int i
= 0; i
< type
->length
; i
++) {
939 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
944 case GLSL_TYPE_SAMPLER
:
948 assert(!"not reached");
954 fs_visitor::visit(ir_assignment
*ir
)
959 /* FINISHME: arrays on the lhs */
960 ir
->lhs
->accept(this);
963 ir
->rhs
->accept(this);
966 assert(l
.file
!= BAD_FILE
);
967 assert(r
.file
!= BAD_FILE
);
970 emit_bool_to_cond_code(ir
->condition
);
973 if (ir
->lhs
->type
->is_scalar() ||
974 ir
->lhs
->type
->is_vector()) {
975 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
976 if (ir
->write_mask
& (1 << i
)) {
977 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
979 inst
->predicated
= true;
985 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
990 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1000 if (ir
->shadow_comparitor
) {
1001 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1002 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1004 coordinate
.reg_offset
++;
1006 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1009 if (ir
->op
== ir_tex
) {
1010 /* There's no plain shadow compare message, so we use shadow
1011 * compare with a bias of 0.0.
1013 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1016 } else if (ir
->op
== ir_txb
) {
1017 ir
->lod_info
.bias
->accept(this);
1018 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1022 assert(ir
->op
== ir_txl
);
1023 ir
->lod_info
.lod
->accept(this);
1024 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1029 ir
->shadow_comparitor
->accept(this);
1030 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1032 } else if (ir
->op
== ir_tex
) {
1033 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1034 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1036 coordinate
.reg_offset
++;
1038 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1041 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1042 * instructions. We'll need to do SIMD16 here.
1044 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1046 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1047 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1049 coordinate
.reg_offset
++;
1052 /* lod/bias appears after u/v/r. */
1055 if (ir
->op
== ir_txb
) {
1056 ir
->lod_info
.bias
->accept(this);
1057 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1061 ir
->lod_info
.lod
->accept(this);
1062 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1067 /* The unused upper half. */
1070 /* Now, since we're doing simd16, the return is 2 interleaved
1071 * vec4s where the odd-indexed ones are junk. We'll need to move
1072 * this weirdness around to the expected layout.
1076 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1078 dst
.type
= BRW_REGISTER_TYPE_F
;
1081 fs_inst
*inst
= NULL
;
1084 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1087 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1090 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1094 assert(!"GLSL 1.30 features unsupported");
1097 inst
->base_mrf
= base_mrf
;
1101 for (int i
= 0; i
< 4; i
++) {
1102 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1103 orig_dst
.reg_offset
++;
1104 dst
.reg_offset
+= 2;
1112 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1114 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1115 * optional parameters like shadow comparitor or LOD bias. If
1116 * optional parameters aren't present, those base slots are
1117 * optional and don't need to be included in the message.
1119 * We don't fill in the unnecessary slots regardless, which may
1120 * look surprising in the disassembly.
1122 int mlen
= 1; /* g0 header always present. */
1125 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1126 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1128 coordinate
.reg_offset
++;
1130 mlen
+= ir
->coordinate
->type
->vector_elements
;
1132 if (ir
->shadow_comparitor
) {
1133 mlen
= MAX2(mlen
, 5);
1135 ir
->shadow_comparitor
->accept(this);
1136 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1140 fs_inst
*inst
= NULL
;
1143 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1146 ir
->lod_info
.bias
->accept(this);
1147 mlen
= MAX2(mlen
, 5);
1148 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1151 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1154 ir
->lod_info
.lod
->accept(this);
1155 mlen
= MAX2(mlen
, 5);
1156 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1159 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1163 assert(!"GLSL 1.30 features unsupported");
1166 inst
->base_mrf
= base_mrf
;
1173 fs_visitor::visit(ir_texture
*ir
)
1176 fs_inst
*inst
= NULL
;
1178 ir
->coordinate
->accept(this);
1179 fs_reg coordinate
= this->result
;
1181 /* Should be lowered by do_lower_texture_projection */
1182 assert(!ir
->projector
);
1184 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1185 ctx
->Shader
.CurrentProgram
,
1186 &brw
->fragment_program
->Base
);
1187 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1189 /* The 965 requires the EU to do the normalization of GL rectangle
1190 * texture coordinates. We use the program parameter state
1191 * tracking to get the scaling factor.
1193 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1194 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1195 int tokens
[STATE_LENGTH
] = {
1197 STATE_TEXRECT_SCALE
,
1203 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1204 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1205 GLuint index
= _mesa_add_state_reference(params
,
1206 (gl_state_index
*)tokens
);
1207 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1209 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1210 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1212 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1213 fs_reg src
= coordinate
;
1216 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1219 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1222 /* Writemasking doesn't eliminate channels on SIMD8 texture
1223 * samples, so don't worry about them.
1225 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1227 if (intel
->gen
< 5) {
1228 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1230 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1233 inst
->sampler
= sampler
;
1237 if (ir
->shadow_comparitor
)
1238 inst
->shadow_compare
= true;
1240 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1241 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1243 for (int i
= 0; i
< 4; i
++) {
1244 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1245 fs_reg l
= swizzle_dst
;
1248 if (swiz
== SWIZZLE_ZERO
) {
1249 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1250 } else if (swiz
== SWIZZLE_ONE
) {
1251 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1254 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1255 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1258 this->result
= swizzle_dst
;
1263 fs_visitor::visit(ir_swizzle
*ir
)
1265 ir
->val
->accept(this);
1266 fs_reg val
= this->result
;
1268 if (ir
->type
->vector_elements
== 1) {
1269 this->result
.reg_offset
+= ir
->mask
.x
;
1273 fs_reg result
= fs_reg(this, ir
->type
);
1274 this->result
= result
;
1276 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1277 fs_reg channel
= val
;
1295 channel
.reg_offset
+= swiz
;
1296 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1297 result
.reg_offset
++;
1302 fs_visitor::visit(ir_discard
*ir
)
1304 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1306 assert(ir
->condition
== NULL
); /* FINISHME */
1308 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null
));
1309 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null
, temp
));
1310 kill_emitted
= true;
1314 fs_visitor::visit(ir_constant
*ir
)
1316 fs_reg
reg(this, ir
->type
);
1319 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1320 switch (ir
->type
->base_type
) {
1321 case GLSL_TYPE_FLOAT
:
1322 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1324 case GLSL_TYPE_UINT
:
1325 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1328 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1330 case GLSL_TYPE_BOOL
:
1331 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1334 assert(!"Non-float/uint/int/bool constant");
1341 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1343 ir_expression
*expr
= ir
->as_expression();
1349 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1350 assert(expr
->operands
[i
]->type
->is_scalar());
1352 expr
->operands
[i
]->accept(this);
1353 op
[i
] = this->result
;
1356 switch (expr
->operation
) {
1357 case ir_unop_logic_not
:
1358 inst
= emit(fs_inst(BRW_OPCODE_ADD
, reg_null
, op
[0], fs_reg(-1)));
1359 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1362 case ir_binop_logic_xor
:
1363 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null
, op
[0], op
[1]));
1364 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1367 case ir_binop_logic_or
:
1368 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null
, op
[0], op
[1]));
1369 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1372 case ir_binop_logic_and
:
1373 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null
, op
[0], op
[1]));
1374 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1378 if (intel
->gen
>= 6) {
1379 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0.0f
)));
1381 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null
, op
[0]));
1383 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1387 if (intel
->gen
>= 6) {
1388 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], fs_reg(0)));
1390 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null
, op
[0]));
1392 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1395 case ir_binop_greater
:
1396 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], op
[1]));
1397 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1399 case ir_binop_gequal
:
1400 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], op
[1]));
1401 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1404 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], op
[1]));
1405 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1407 case ir_binop_lequal
:
1408 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], op
[1]));
1409 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1411 case ir_binop_equal
:
1412 case ir_binop_all_equal
:
1413 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], op
[1]));
1414 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1416 case ir_binop_nequal
:
1417 case ir_binop_any_nequal
:
1418 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
, op
[0], op
[1]));
1419 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1422 assert(!"not reached");
1431 if (intel
->gen
>= 6) {
1432 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null
,
1433 this->result
, fs_reg(1)));
1434 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1436 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null
, this->result
));
1437 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1442 fs_visitor::visit(ir_if
*ir
)
1446 /* Don't point the annotation at the if statement, because then it plus
1447 * the then and else blocks get printed.
1449 this->base_ir
= ir
->condition
;
1451 emit_bool_to_cond_code(ir
->condition
);
1453 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1454 inst
->predicated
= true;
1456 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1457 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1463 if (!ir
->else_instructions
.is_empty()) {
1464 emit(fs_inst(BRW_OPCODE_ELSE
));
1466 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1467 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1474 emit(fs_inst(BRW_OPCODE_ENDIF
));
1478 fs_visitor::visit(ir_loop
*ir
)
1480 fs_reg counter
= reg_undef
;
1483 this->base_ir
= ir
->counter
;
1484 ir
->counter
->accept(this);
1485 counter
= *(variable_storage(ir
->counter
));
1488 this->base_ir
= ir
->from
;
1489 ir
->from
->accept(this);
1491 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1495 emit(fs_inst(BRW_OPCODE_DO
));
1498 this->base_ir
= ir
->to
;
1499 ir
->to
->accept(this);
1501 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null
,
1502 counter
, this->result
));
1504 case ir_binop_equal
:
1505 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1507 case ir_binop_nequal
:
1508 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1510 case ir_binop_gequal
:
1511 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1513 case ir_binop_lequal
:
1514 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1516 case ir_binop_greater
:
1517 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1520 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1523 assert(!"not reached: unknown loop condition");
1528 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1529 inst
->predicated
= true;
1532 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1533 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1539 if (ir
->increment
) {
1540 this->base_ir
= ir
->increment
;
1541 ir
->increment
->accept(this);
1542 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1545 emit(fs_inst(BRW_OPCODE_WHILE
));
1549 fs_visitor::visit(ir_loop_jump
*ir
)
1552 case ir_loop_jump::jump_break
:
1553 emit(fs_inst(BRW_OPCODE_BREAK
));
1555 case ir_loop_jump::jump_continue
:
1556 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1562 fs_visitor::visit(ir_call
*ir
)
1564 assert(!"FINISHME");
1568 fs_visitor::visit(ir_return
*ir
)
1570 assert(!"FINISHME");
1574 fs_visitor::visit(ir_function
*ir
)
1576 /* Ignore function bodies other than main() -- we shouldn't see calls to
1577 * them since they should all be inlined before we get to ir_to_mesa.
1579 if (strcmp(ir
->name
, "main") == 0) {
1580 const ir_function_signature
*sig
;
1583 sig
= ir
->matching_signature(&empty
);
1587 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1588 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1597 fs_visitor::visit(ir_function_signature
*ir
)
1599 assert(!"not reached");
1604 fs_visitor::emit(fs_inst inst
)
1606 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1609 list_inst
->annotation
= this->current_annotation
;
1610 list_inst
->ir
= this->base_ir
;
1612 this->instructions
.push_tail(list_inst
);
1617 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1619 fs_visitor::emit_dummy_fs()
1621 /* Everyone's favorite color. */
1622 emit(fs_inst(BRW_OPCODE_MOV
,
1625 emit(fs_inst(BRW_OPCODE_MOV
,
1628 emit(fs_inst(BRW_OPCODE_MOV
,
1631 emit(fs_inst(BRW_OPCODE_MOV
,
1636 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1639 write
->base_mrf
= 0;
1642 /* The register location here is relative to the start of the URB
1643 * data. It will get adjusted to be a real location before
1644 * generate_code() time.
1647 fs_visitor::interp_reg(int location
, int channel
)
1649 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1650 int stride
= (channel
& 1) * 4;
1652 assert(urb_setup
[location
] != -1);
1654 return brw_vec1_grf(regnr
, stride
);
1657 /** Emits the interpolation for the varying inputs. */
1659 fs_visitor::emit_interpolation_setup_gen4()
1661 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1663 this->current_annotation
= "compute pixel centers";
1664 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1665 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1666 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1667 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1668 emit(fs_inst(BRW_OPCODE_ADD
,
1670 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1671 fs_reg(brw_imm_v(0x10101010))));
1672 emit(fs_inst(BRW_OPCODE_ADD
,
1674 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1675 fs_reg(brw_imm_v(0x11001100))));
1677 this->current_annotation
= "compute pixel deltas from v0";
1679 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1680 this->delta_y
= this->delta_x
;
1681 this->delta_y
.reg_offset
++;
1683 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1684 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1686 emit(fs_inst(BRW_OPCODE_ADD
,
1689 fs_reg(negate(brw_vec1_grf(1, 0)))));
1690 emit(fs_inst(BRW_OPCODE_ADD
,
1693 fs_reg(negate(brw_vec1_grf(1, 1)))));
1695 this->current_annotation
= "compute pos.w and 1/pos.w";
1696 /* Compute wpos.w. It's always in our setup, since it's needed to
1697 * interpolate the other attributes.
1699 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1700 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1701 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1702 /* Compute the pixel 1/W value from wpos.w. */
1703 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1704 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1705 this->current_annotation
= NULL
;
1708 /** Emits the interpolation for the varying inputs. */
1710 fs_visitor::emit_interpolation_setup_gen6()
1712 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1714 /* If the pixel centers end up used, the setup is the same as for gen4. */
1715 this->current_annotation
= "compute pixel centers";
1716 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1717 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1718 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1719 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1720 emit(fs_inst(BRW_OPCODE_ADD
,
1722 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1723 fs_reg(brw_imm_v(0x10101010))));
1724 emit(fs_inst(BRW_OPCODE_ADD
,
1726 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1727 fs_reg(brw_imm_v(0x11001100))));
1729 /* As of gen6, we can no longer mix float and int sources. We have
1730 * to turn the integer pixel centers into floats for their actual
1733 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1734 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1735 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1736 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1738 this->current_annotation
= "compute 1/pos.w";
1739 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1740 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1741 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1743 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1744 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1746 this->current_annotation
= NULL
;
1750 fs_visitor::emit_fb_writes()
1752 this->current_annotation
= "FB write header";
1753 GLboolean header_present
= GL_TRUE
;
1756 if (intel
->gen
>= 6 &&
1757 !this->kill_emitted
&&
1758 c
->key
.nr_color_regions
== 1) {
1759 header_present
= false;
1762 if (header_present
) {
1767 if (c
->key
.aa_dest_stencil_reg
) {
1768 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1769 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1772 /* Reserve space for color. It'll be filled in per MRT below. */
1776 if (c
->key
.source_depth_to_render_target
) {
1777 if (c
->key
.computes_depth
) {
1778 /* Hand over gl_FragDepth. */
1779 assert(this->frag_depth
);
1780 fs_reg depth
= *(variable_storage(this->frag_depth
));
1782 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1784 /* Pass through the payload depth. */
1785 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1786 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1790 if (c
->key
.dest_depth_reg
) {
1791 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1792 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1795 fs_reg color
= reg_undef
;
1796 if (this->frag_color
)
1797 color
= *(variable_storage(this->frag_color
));
1798 else if (this->frag_data
)
1799 color
= *(variable_storage(this->frag_data
));
1801 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1802 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1803 "FB write target %d",
1805 if (this->frag_color
|| this->frag_data
) {
1806 for (int i
= 0; i
< 4; i
++) {
1807 emit(fs_inst(BRW_OPCODE_MOV
,
1808 fs_reg(MRF
, color_mrf
+ i
),
1814 if (this->frag_color
)
1815 color
.reg_offset
-= 4;
1817 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1818 reg_undef
, reg_undef
));
1819 inst
->target
= target
;
1822 if (target
== c
->key
.nr_color_regions
- 1)
1824 inst
->header_present
= header_present
;
1827 if (c
->key
.nr_color_regions
== 0) {
1828 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1829 reg_undef
, reg_undef
));
1833 inst
->header_present
= header_present
;
1836 this->current_annotation
= NULL
;
1840 fs_visitor::generate_fb_write(fs_inst
*inst
)
1842 GLboolean eot
= inst
->eot
;
1843 struct brw_reg implied_header
;
1845 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1848 brw_push_insn_state(p
);
1849 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1850 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1852 if (inst
->header_present
) {
1853 if (intel
->gen
>= 6) {
1855 brw_message_reg(inst
->base_mrf
),
1856 brw_vec8_grf(0, 0));
1857 implied_header
= brw_null_reg();
1859 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1863 brw_message_reg(inst
->base_mrf
+ 1),
1864 brw_vec8_grf(1, 0));
1866 implied_header
= brw_null_reg();
1869 brw_pop_insn_state(p
);
1872 8, /* dispatch_width */
1873 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
1883 fs_visitor::generate_linterp(fs_inst
*inst
,
1884 struct brw_reg dst
, struct brw_reg
*src
)
1886 struct brw_reg delta_x
= src
[0];
1887 struct brw_reg delta_y
= src
[1];
1888 struct brw_reg interp
= src
[2];
1891 delta_y
.nr
== delta_x
.nr
+ 1 &&
1892 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
1893 brw_PLN(p
, dst
, interp
, delta_x
);
1895 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
1896 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
1901 fs_visitor::generate_math(fs_inst
*inst
,
1902 struct brw_reg dst
, struct brw_reg
*src
)
1906 switch (inst
->opcode
) {
1908 op
= BRW_MATH_FUNCTION_INV
;
1911 op
= BRW_MATH_FUNCTION_RSQ
;
1913 case FS_OPCODE_SQRT
:
1914 op
= BRW_MATH_FUNCTION_SQRT
;
1916 case FS_OPCODE_EXP2
:
1917 op
= BRW_MATH_FUNCTION_EXP
;
1919 case FS_OPCODE_LOG2
:
1920 op
= BRW_MATH_FUNCTION_LOG
;
1923 op
= BRW_MATH_FUNCTION_POW
;
1926 op
= BRW_MATH_FUNCTION_SIN
;
1929 op
= BRW_MATH_FUNCTION_COS
;
1932 assert(!"not reached: unknown math function");
1937 if (intel
->gen
>= 6) {
1938 assert(inst
->mlen
== 0);
1940 if (inst
->opcode
== FS_OPCODE_POW
) {
1941 brw_math2(p
, dst
, op
, src
[0], src
[1]);
1945 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1946 BRW_MATH_SATURATE_NONE
,
1948 BRW_MATH_DATA_VECTOR
,
1949 BRW_MATH_PRECISION_FULL
);
1952 assert(inst
->mlen
>= 1);
1956 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
1957 BRW_MATH_SATURATE_NONE
,
1958 inst
->base_mrf
, src
[0],
1959 BRW_MATH_DATA_VECTOR
,
1960 BRW_MATH_PRECISION_FULL
);
1965 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
1969 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1971 if (intel
->gen
>= 5) {
1972 switch (inst
->opcode
) {
1974 if (inst
->shadow_compare
) {
1975 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
1977 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
1981 if (inst
->shadow_compare
) {
1982 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
1984 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
1989 switch (inst
->opcode
) {
1991 /* Note that G45 and older determines shadow compare and dispatch width
1992 * from message length for most messages.
1994 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
1995 if (inst
->shadow_compare
) {
1996 assert(inst
->mlen
== 6);
1998 assert(inst
->mlen
<= 4);
2002 if (inst
->shadow_compare
) {
2003 assert(inst
->mlen
== 6);
2004 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2006 assert(inst
->mlen
== 9);
2007 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2008 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2013 assert(msg_type
!= -1);
2015 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2021 retype(dst
, BRW_REGISTER_TYPE_UW
),
2023 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2024 SURF_INDEX_TEXTURE(inst
->sampler
),
2036 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2039 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2041 * and we're trying to produce:
2044 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2045 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2046 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2047 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2048 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2049 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2050 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2051 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2053 * and add another set of two more subspans if in 16-pixel dispatch mode.
2055 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2056 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2057 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2058 * between each other. We could probably do it like ddx and swizzle the right
2059 * order later, but bail for now and just produce
2060 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2063 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2065 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2066 BRW_REGISTER_TYPE_F
,
2067 BRW_VERTICAL_STRIDE_2
,
2069 BRW_HORIZONTAL_STRIDE_0
,
2070 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2071 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2072 BRW_REGISTER_TYPE_F
,
2073 BRW_VERTICAL_STRIDE_2
,
2075 BRW_HORIZONTAL_STRIDE_0
,
2076 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2077 brw_ADD(p
, dst
, src0
, negate(src1
));
2081 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2083 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2084 BRW_REGISTER_TYPE_F
,
2085 BRW_VERTICAL_STRIDE_4
,
2087 BRW_HORIZONTAL_STRIDE_0
,
2088 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2089 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2090 BRW_REGISTER_TYPE_F
,
2091 BRW_VERTICAL_STRIDE_4
,
2093 BRW_HORIZONTAL_STRIDE_0
,
2094 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2095 brw_ADD(p
, dst
, src0
, negate(src1
));
2099 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2101 brw_push_insn_state(p
);
2102 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2103 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2104 brw_pop_insn_state(p
);
2108 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2110 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2111 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2113 brw_push_insn_state(p
);
2114 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2115 brw_AND(p
, g0
, mask
, g0
);
2116 brw_pop_insn_state(p
);
2120 fs_visitor::assign_curb_setup()
2122 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2123 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2125 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2126 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2127 fs_inst
*inst
= (fs_inst
*)iter
.get();
2129 for (unsigned int i
= 0; i
< 3; i
++) {
2130 if (inst
->src
[i
].file
== UNIFORM
) {
2131 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2132 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2136 inst
->src
[i
].file
= FIXED_HW_REG
;
2137 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2144 fs_visitor::calculate_urb_setup()
2146 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2151 /* Figure out where each of the incoming setup attributes lands. */
2152 if (intel
->gen
>= 6) {
2153 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2154 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2155 urb_setup
[i
] = urb_next
++;
2159 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2160 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2161 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2164 if (i
>= VERT_RESULT_VAR0
)
2165 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2166 else if (i
<= VERT_RESULT_TEX7
)
2172 urb_setup
[fp_index
] = urb_next
++;
2177 /* Each attribute is 4 setup channels, each of which is half a reg. */
2178 c
->prog_data
.urb_read_length
= urb_next
* 2;
2182 fs_visitor::assign_urb_setup()
2184 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2186 /* Offset all the urb_setup[] index by the actual position of the
2187 * setup regs, now that the location of the constants has been chosen.
2189 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2190 fs_inst
*inst
= (fs_inst
*)iter
.get();
2192 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2195 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2197 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2200 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2204 assign_reg(int *reg_hw_locations
, fs_reg
*reg
)
2206 if (reg
->file
== GRF
&& reg
->reg
!= 0) {
2207 assert(reg
->reg_offset
>= 0);
2208 reg
->hw_reg
= reg_hw_locations
[reg
->reg
] + reg
->reg_offset
;
2214 fs_visitor::assign_regs_trivial()
2217 int hw_reg_mapping
[this->virtual_grf_next
];
2220 hw_reg_mapping
[0] = 0;
2221 hw_reg_mapping
[1] = this->first_non_payload_grf
;
2222 for (i
= 2; i
< this->virtual_grf_next
; i
++) {
2223 hw_reg_mapping
[i
] = (hw_reg_mapping
[i
- 1] +
2224 this->virtual_grf_sizes
[i
- 1]);
2226 last_grf
= hw_reg_mapping
[i
- 1] + this->virtual_grf_sizes
[i
- 1];
2228 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2229 fs_inst
*inst
= (fs_inst
*)iter
.get();
2231 assign_reg(hw_reg_mapping
, &inst
->dst
);
2232 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2233 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2236 this->grf_used
= last_grf
+ 1;
2240 fs_visitor::assign_regs()
2243 int hw_reg_mapping
[this->virtual_grf_next
+ 1];
2244 int base_reg_count
= BRW_MAX_GRF
- this->first_non_payload_grf
;
2245 int class_sizes
[base_reg_count
];
2246 int class_count
= 0;
2247 int aligned_pair_class
= -1;
2249 /* Set up the register classes.
2251 * The base registers store a scalar value. For texture samples,
2252 * we get virtual GRFs composed of 4 contiguous hw register. For
2253 * structures and arrays, we store them as contiguous larger things
2254 * than that, though we should be able to do better most of the
2257 class_sizes
[class_count
++] = 1;
2258 if (brw
->has_pln
&& intel
->gen
< 6) {
2259 /* Always set up the (unaligned) pairs for gen5, so we can find
2260 * them for making the aligned pair class.
2262 class_sizes
[class_count
++] = 2;
2264 for (int r
= 1; r
< this->virtual_grf_next
; r
++) {
2267 for (i
= 0; i
< class_count
; i
++) {
2268 if (class_sizes
[i
] == this->virtual_grf_sizes
[r
])
2271 if (i
== class_count
) {
2272 if (this->virtual_grf_sizes
[r
] >= base_reg_count
) {
2273 fprintf(stderr
, "Object too large to register allocate.\n");
2277 class_sizes
[class_count
++] = this->virtual_grf_sizes
[r
];
2281 int ra_reg_count
= 0;
2282 int class_base_reg
[class_count
];
2283 int class_reg_count
[class_count
];
2284 int classes
[class_count
+ 1];
2286 for (int i
= 0; i
< class_count
; i
++) {
2287 class_base_reg
[i
] = ra_reg_count
;
2288 class_reg_count
[i
] = base_reg_count
- (class_sizes
[i
] - 1);
2289 ra_reg_count
+= class_reg_count
[i
];
2292 struct ra_regs
*regs
= ra_alloc_reg_set(ra_reg_count
);
2293 for (int i
= 0; i
< class_count
; i
++) {
2294 classes
[i
] = ra_alloc_reg_class(regs
);
2296 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2297 ra_class_add_reg(regs
, classes
[i
], class_base_reg
[i
] + i_r
);
2300 /* Add conflicts between our contiguous registers aliasing
2301 * base regs and other register classes' contiguous registers
2302 * that alias base regs, or the base regs themselves for classes[0].
2304 for (int c
= 0; c
<= i
; c
++) {
2305 for (int i_r
= 0; i_r
< class_reg_count
[i
]; i_r
++) {
2306 for (int c_r
= MAX2(0, i_r
- (class_sizes
[c
] - 1));
2307 c_r
< MIN2(class_reg_count
[c
], i_r
+ class_sizes
[i
]);
2311 printf("%d/%d conflicts %d/%d\n",
2312 class_sizes
[i
], this->first_non_payload_grf
+ i_r
,
2313 class_sizes
[c
], this->first_non_payload_grf
+ c_r
);
2316 ra_add_reg_conflict(regs
,
2317 class_base_reg
[i
] + i_r
,
2318 class_base_reg
[c
] + c_r
);
2324 /* Add a special class for aligned pairs, which we'll put delta_x/y
2325 * in on gen5 so that we can do PLN.
2327 if (brw
->has_pln
&& intel
->gen
< 6) {
2328 int reg_count
= (base_reg_count
- 1) / 2;
2329 int unaligned_pair_class
= 1;
2330 assert(class_sizes
[unaligned_pair_class
] == 2);
2332 aligned_pair_class
= class_count
;
2333 classes
[aligned_pair_class
] = ra_alloc_reg_class(regs
);
2334 class_sizes
[aligned_pair_class
] = 2;
2335 class_base_reg
[aligned_pair_class
] = 0;
2336 class_reg_count
[aligned_pair_class
] = 0;
2337 int start
= (this->first_non_payload_grf
& 1) ? 1 : 0;
2339 for (int i
= 0; i
< reg_count
; i
++) {
2340 ra_class_add_reg(regs
, classes
[aligned_pair_class
],
2341 class_base_reg
[unaligned_pair_class
] + i
* 2 + start
);
2346 ra_set_finalize(regs
);
2348 struct ra_graph
*g
= ra_alloc_interference_graph(regs
,
2349 this->virtual_grf_next
);
2350 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2353 ra_set_node_class(g
, 0, classes
[0]);
2355 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2356 for (int c
= 0; c
< class_count
; c
++) {
2357 if (class_sizes
[c
] == this->virtual_grf_sizes
[i
]) {
2358 if (aligned_pair_class
>= 0 &&
2359 this->delta_x
.reg
== i
) {
2360 ra_set_node_class(g
, i
, classes
[aligned_pair_class
]);
2362 ra_set_node_class(g
, i
, classes
[c
]);
2368 for (int j
= 1; j
< i
; j
++) {
2369 if (virtual_grf_interferes(i
, j
)) {
2370 ra_add_node_interference(g
, i
, j
);
2375 /* FINISHME: Handle spilling */
2376 if (!ra_allocate_no_spills(g
)) {
2377 fprintf(stderr
, "Failed to allocate registers.\n");
2382 /* Get the chosen virtual registers for each node, and map virtual
2383 * regs in the register classes back down to real hardware reg
2386 hw_reg_mapping
[0] = 0; /* unused */
2387 for (int i
= 1; i
< this->virtual_grf_next
; i
++) {
2388 int reg
= ra_get_node_reg(g
, i
);
2391 for (int c
= 0; c
< class_count
; c
++) {
2392 if (reg
>= class_base_reg
[c
] &&
2393 reg
< class_base_reg
[c
] + class_reg_count
[c
]) {
2394 hw_reg
= reg
- class_base_reg
[c
];
2399 assert(hw_reg
>= 0);
2400 hw_reg_mapping
[i
] = this->first_non_payload_grf
+ hw_reg
;
2401 last_grf
= MAX2(last_grf
,
2402 hw_reg_mapping
[i
] + this->virtual_grf_sizes
[i
] - 1);
2405 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2406 fs_inst
*inst
= (fs_inst
*)iter
.get();
2408 assign_reg(hw_reg_mapping
, &inst
->dst
);
2409 assign_reg(hw_reg_mapping
, &inst
->src
[0]);
2410 assign_reg(hw_reg_mapping
, &inst
->src
[1]);
2413 this->grf_used
= last_grf
+ 1;
2420 * Split large virtual GRFs into separate components if we can.
2422 * This is mostly duplicated with what brw_fs_vector_splitting does,
2423 * but that's really conservative because it's afraid of doing
2424 * splitting that doesn't result in real progress after the rest of
2425 * the optimization phases, which would cause infinite looping in
2426 * optimization. We can do it once here, safely. This also has the
2427 * opportunity to split interpolated values, or maybe even uniforms,
2428 * which we don't have at the IR level.
2430 * We want to split, because virtual GRFs are what we register
2431 * allocate and spill (due to contiguousness requirements for some
2432 * instructions), and they're what we naturally generate in the
2433 * codegen process, but most virtual GRFs don't actually need to be
2434 * contiguous sets of GRFs. If we split, we'll end up with reduced
2435 * live intervals and better dead code elimination and coalescing.
2438 fs_visitor::split_virtual_grfs()
2440 int num_vars
= this->virtual_grf_next
;
2441 bool split_grf
[num_vars
];
2442 int new_virtual_grf
[num_vars
];
2444 /* Try to split anything > 0 sized. */
2445 for (int i
= 0; i
< num_vars
; i
++) {
2446 if (this->virtual_grf_sizes
[i
] != 1)
2447 split_grf
[i
] = true;
2449 split_grf
[i
] = false;
2453 /* PLN opcodes rely on the delta_xy being contiguous. */
2454 split_grf
[this->delta_x
.reg
] = false;
2457 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2458 fs_inst
*inst
= (fs_inst
*)iter
.get();
2460 /* Texturing produces 4 contiguous registers, so no splitting. */
2461 if ((inst
->opcode
== FS_OPCODE_TEX
||
2462 inst
->opcode
== FS_OPCODE_TXB
||
2463 inst
->opcode
== FS_OPCODE_TXL
) &&
2464 inst
->dst
.file
== GRF
) {
2465 split_grf
[inst
->dst
.reg
] = false;
2469 /* Allocate new space for split regs. Note that the virtual
2470 * numbers will be contiguous.
2472 for (int i
= 0; i
< num_vars
; i
++) {
2474 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2475 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2476 int reg
= virtual_grf_alloc(1);
2477 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2479 this->virtual_grf_sizes
[i
] = 1;
2483 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2484 fs_inst
*inst
= (fs_inst
*)iter
.get();
2486 if (inst
->dst
.file
== GRF
&&
2487 split_grf
[inst
->dst
.reg
] &&
2488 inst
->dst
.reg_offset
!= 0) {
2489 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2490 inst
->dst
.reg_offset
- 1);
2491 inst
->dst
.reg_offset
= 0;
2493 for (int i
= 0; i
< 3; i
++) {
2494 if (inst
->src
[i
].file
== GRF
&&
2495 split_grf
[inst
->src
[i
].reg
] &&
2496 inst
->src
[i
].reg_offset
!= 0) {
2497 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2498 inst
->src
[i
].reg_offset
- 1);
2499 inst
->src
[i
].reg_offset
= 0;
2506 fs_visitor::calculate_live_intervals()
2508 int num_vars
= this->virtual_grf_next
;
2509 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2510 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2514 for (int i
= 0; i
< num_vars
; i
++) {
2520 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2521 fs_inst
*inst
= (fs_inst
*)iter
.get();
2523 if (inst
->opcode
== BRW_OPCODE_DO
) {
2524 if (loop_depth
++ == 0)
2526 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2529 if (loop_depth
== 0) {
2532 * Patches up any vars marked for use within the loop as
2533 * live until the end. This is conservative, as there
2534 * will often be variables defined and used inside the
2535 * loop but dead at the end of the loop body.
2537 for (int i
= 0; i
< num_vars
; i
++) {
2538 if (use
[i
] == loop_start
) {
2549 for (unsigned int i
= 0; i
< 3; i
++) {
2550 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2551 use
[inst
->src
[i
].reg
] = MAX2(use
[inst
->src
[i
].reg
], eip
);
2554 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2555 def
[inst
->dst
.reg
] = MIN2(def
[inst
->dst
.reg
], eip
);
2562 talloc_free(this->virtual_grf_def
);
2563 talloc_free(this->virtual_grf_use
);
2564 this->virtual_grf_def
= def
;
2565 this->virtual_grf_use
= use
;
2569 * Attempts to move immediate constants into the immediate
2570 * constant slot of following instructions.
2572 * Immediate constants are a bit tricky -- they have to be in the last
2573 * operand slot, you can't do abs/negate on them,
2577 fs_visitor::propagate_constants()
2579 bool progress
= false;
2581 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2582 fs_inst
*inst
= (fs_inst
*)iter
.get();
2584 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2586 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2587 inst
->dst
.type
!= inst
->src
[0].type
)
2590 /* Don't bother with cases where we should have had the
2591 * operation on the constant folded in GLSL already.
2596 /* Found a move of a constant to a GRF. Find anything else using the GRF
2597 * before it's written, and replace it with the constant if we can.
2599 exec_list_iterator scan_iter
= iter
;
2601 for (; scan_iter
.has_next(); scan_iter
.next()) {
2602 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2604 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2605 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2606 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2607 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2611 for (int i
= 2; i
>= 0; i
--) {
2612 if (scan_inst
->src
[i
].file
!= GRF
||
2613 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2614 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2617 /* Don't bother with cases where we should have had the
2618 * operation on the constant folded in GLSL already.
2620 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2623 switch (scan_inst
->opcode
) {
2624 case BRW_OPCODE_MOV
:
2625 scan_inst
->src
[i
] = inst
->src
[0];
2629 case BRW_OPCODE_MUL
:
2630 case BRW_OPCODE_ADD
:
2632 scan_inst
->src
[i
] = inst
->src
[0];
2634 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2635 /* Fit this constant in by commuting the operands */
2636 scan_inst
->src
[0] = scan_inst
->src
[1];
2637 scan_inst
->src
[1] = inst
->src
[0];
2640 case BRW_OPCODE_CMP
:
2642 scan_inst
->src
[i
] = inst
->src
[0];
2648 if (scan_inst
->dst
.file
== GRF
&&
2649 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2650 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2651 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2660 * Must be called after calculate_live_intervales() to remove unused
2661 * writes to registers -- register allocation will fail otherwise
2662 * because something deffed but not used won't be considered to
2663 * interfere with other regs.
2666 fs_visitor::dead_code_eliminate()
2668 bool progress
= false;
2669 int num_vars
= this->virtual_grf_next
;
2670 bool dead
[num_vars
];
2672 for (int i
= 0; i
< num_vars
; i
++) {
2673 dead
[i
] = this->virtual_grf_def
[i
] >= this->virtual_grf_use
[i
];
2676 /* Mark off its interval so it won't interfere with anything. */
2677 this->virtual_grf_def
[i
] = -1;
2678 this->virtual_grf_use
[i
] = -1;
2682 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2683 fs_inst
*inst
= (fs_inst
*)iter
.get();
2685 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2695 fs_visitor::register_coalesce()
2697 bool progress
= false;
2699 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2700 fs_inst
*inst
= (fs_inst
*)iter
.get();
2702 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2705 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2706 inst
->dst
.type
!= inst
->src
[0].type
)
2709 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2710 * them: check for no writes to either one until the exit of the
2713 bool interfered
= false;
2714 exec_list_iterator scan_iter
= iter
;
2716 for (; scan_iter
.has_next(); scan_iter
.next()) {
2717 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2719 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2720 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2721 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2727 if (scan_inst
->dst
.file
== GRF
) {
2728 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2729 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2730 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2734 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2735 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2736 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2746 /* Update live interval so we don't have to recalculate. */
2747 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2748 virtual_grf_use
[inst
->dst
.reg
]);
2750 /* Rewrite the later usage to point at the source of the move to
2753 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2755 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2757 for (int i
= 0; i
< 3; i
++) {
2758 if (scan_inst
->src
[i
].file
== GRF
&&
2759 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2760 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2761 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2762 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2763 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2764 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2778 fs_visitor::compute_to_mrf()
2780 bool progress
= false;
2783 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2784 fs_inst
*inst
= (fs_inst
*)iter
.get();
2789 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2791 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2792 inst
->dst
.type
!= inst
->src
[0].type
||
2793 inst
->src
[0].abs
|| inst
->src
[0].negate
)
2796 /* Can't compute-to-MRF this GRF if someone else was going to
2799 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2802 /* Found a move of a GRF to a MRF. Let's see if we can go
2803 * rewrite the thing that made this GRF to write into the MRF.
2807 for (scan_inst
= (fs_inst
*)inst
->prev
;
2808 scan_inst
->prev
!= NULL
;
2809 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2810 /* We don't handle flow control here. Most computation of
2811 * values that end up in MRFs are shortly before the MRF
2814 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2815 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2816 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2820 /* You can't read from an MRF, so if someone else reads our
2821 * MRF's source GRF that we wanted to rewrite, that stops us.
2823 bool interfered
= false;
2824 for (int i
= 0; i
< 3; i
++) {
2825 if (scan_inst
->src
[i
].file
== GRF
&&
2826 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2827 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2834 if (scan_inst
->dst
.file
== MRF
&&
2835 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2836 /* Somebody else wrote our MRF here, so we can't can't
2837 * compute-to-MRF before that.
2842 if (scan_inst
->mlen
> 0) {
2843 /* Found a SEND instruction, which will do some amount of
2844 * implied write that may overwrite our MRF that we were
2845 * hoping to compute-to-MRF somewhere above it. Nothing
2846 * we have implied-writes more than 2 MRFs from base_mrf,
2849 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2850 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2851 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2856 if (scan_inst
->dst
.file
== GRF
&&
2857 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2858 /* Found the last thing to write our reg we want to turn
2859 * into a compute-to-MRF.
2862 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2863 /* texturing writes several continuous regs, so we can't
2864 * compute-to-mrf that.
2869 /* If it's predicated, it (probably) didn't populate all
2872 if (scan_inst
->predicated
)
2875 /* SEND instructions can't have MRF as a destination. */
2876 if (scan_inst
->mlen
)
2879 if (intel
->gen
>= 6) {
2880 /* gen6 math instructions must have the destination be
2881 * GRF, so no compute-to-MRF for them.
2883 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
2884 scan_inst
->opcode
== FS_OPCODE_RSQ
||
2885 scan_inst
->opcode
== FS_OPCODE_SQRT
||
2886 scan_inst
->opcode
== FS_OPCODE_EXP2
||
2887 scan_inst
->opcode
== FS_OPCODE_LOG2
||
2888 scan_inst
->opcode
== FS_OPCODE_SIN
||
2889 scan_inst
->opcode
== FS_OPCODE_COS
||
2890 scan_inst
->opcode
== FS_OPCODE_POW
) {
2895 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2896 /* Found the creator of our MRF's source value. */
2903 scan_inst
->dst
.file
= MRF
;
2904 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
2905 scan_inst
->saturate
|= inst
->saturate
;
2915 fs_visitor::virtual_grf_interferes(int a
, int b
)
2917 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
2918 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
2920 /* For dead code, just check if the def interferes with the other range. */
2921 if (this->virtual_grf_use
[a
] == -1) {
2922 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
2923 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
2925 if (this->virtual_grf_use
[b
] == -1) {
2926 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
2927 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
2933 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
2935 struct brw_reg brw_reg
;
2937 switch (reg
->file
) {
2941 brw_reg
= brw_vec8_reg(reg
->file
,
2943 brw_reg
= retype(brw_reg
, reg
->type
);
2946 switch (reg
->type
) {
2947 case BRW_REGISTER_TYPE_F
:
2948 brw_reg
= brw_imm_f(reg
->imm
.f
);
2950 case BRW_REGISTER_TYPE_D
:
2951 brw_reg
= brw_imm_d(reg
->imm
.i
);
2953 case BRW_REGISTER_TYPE_UD
:
2954 brw_reg
= brw_imm_ud(reg
->imm
.u
);
2957 assert(!"not reached");
2962 brw_reg
= reg
->fixed_hw_reg
;
2965 /* Probably unused. */
2966 brw_reg
= brw_null_reg();
2969 assert(!"not reached");
2970 brw_reg
= brw_null_reg();
2974 brw_reg
= brw_abs(brw_reg
);
2976 brw_reg
= negate(brw_reg
);
2982 fs_visitor::generate_code()
2984 unsigned int annotation_len
= 0;
2985 int last_native_inst
= 0;
2986 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
2987 int if_stack_depth
= 0, loop_stack_depth
= 0;
2988 int if_depth_in_loop
[16];
2990 if_depth_in_loop
[loop_stack_depth
] = 0;
2992 memset(&if_stack
, 0, sizeof(if_stack
));
2993 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2994 fs_inst
*inst
= (fs_inst
*)iter
.get();
2995 struct brw_reg src
[3], dst
;
2997 for (unsigned int i
= 0; i
< 3; i
++) {
2998 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3000 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3002 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3003 brw_set_predicate_control(p
, inst
->predicated
);
3005 switch (inst
->opcode
) {
3006 case BRW_OPCODE_MOV
:
3007 brw_MOV(p
, dst
, src
[0]);
3009 case BRW_OPCODE_ADD
:
3010 brw_ADD(p
, dst
, src
[0], src
[1]);
3012 case BRW_OPCODE_MUL
:
3013 brw_MUL(p
, dst
, src
[0], src
[1]);
3016 case BRW_OPCODE_FRC
:
3017 brw_FRC(p
, dst
, src
[0]);
3019 case BRW_OPCODE_RNDD
:
3020 brw_RNDD(p
, dst
, src
[0]);
3022 case BRW_OPCODE_RNDE
:
3023 brw_RNDE(p
, dst
, src
[0]);
3025 case BRW_OPCODE_RNDZ
:
3026 brw_RNDZ(p
, dst
, src
[0]);
3029 case BRW_OPCODE_AND
:
3030 brw_AND(p
, dst
, src
[0], src
[1]);
3033 brw_OR(p
, dst
, src
[0], src
[1]);
3035 case BRW_OPCODE_XOR
:
3036 brw_XOR(p
, dst
, src
[0], src
[1]);
3038 case BRW_OPCODE_NOT
:
3039 brw_NOT(p
, dst
, src
[0]);
3041 case BRW_OPCODE_ASR
:
3042 brw_ASR(p
, dst
, src
[0], src
[1]);
3044 case BRW_OPCODE_SHR
:
3045 brw_SHR(p
, dst
, src
[0], src
[1]);
3047 case BRW_OPCODE_SHL
:
3048 brw_SHL(p
, dst
, src
[0], src
[1]);
3051 case BRW_OPCODE_CMP
:
3052 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3054 case BRW_OPCODE_SEL
:
3055 brw_SEL(p
, dst
, src
[0], src
[1]);
3059 assert(if_stack_depth
< 16);
3060 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3061 if_depth_in_loop
[loop_stack_depth
]++;
3064 case BRW_OPCODE_ELSE
:
3065 if_stack
[if_stack_depth
- 1] =
3066 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3068 case BRW_OPCODE_ENDIF
:
3070 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3071 if_depth_in_loop
[loop_stack_depth
]--;
3075 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3076 if_depth_in_loop
[loop_stack_depth
] = 0;
3079 case BRW_OPCODE_BREAK
:
3080 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3081 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3083 case BRW_OPCODE_CONTINUE
:
3084 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3085 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3088 case BRW_OPCODE_WHILE
: {
3089 struct brw_instruction
*inst0
, *inst1
;
3092 if (intel
->gen
>= 5)
3095 assert(loop_stack_depth
> 0);
3097 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3098 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3099 while (inst0
> loop_stack
[loop_stack_depth
]) {
3101 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3102 inst0
->bits3
.if_else
.jump_count
== 0) {
3103 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3105 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3106 inst0
->bits3
.if_else
.jump_count
== 0) {
3107 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3115 case FS_OPCODE_SQRT
:
3116 case FS_OPCODE_EXP2
:
3117 case FS_OPCODE_LOG2
:
3121 generate_math(inst
, dst
, src
);
3123 case FS_OPCODE_LINTERP
:
3124 generate_linterp(inst
, dst
, src
);
3129 generate_tex(inst
, dst
);
3131 case FS_OPCODE_DISCARD_NOT
:
3132 generate_discard_not(inst
, dst
);
3134 case FS_OPCODE_DISCARD_AND
:
3135 generate_discard_and(inst
, src
[0]);
3138 generate_ddx(inst
, dst
, src
[0]);
3141 generate_ddy(inst
, dst
, src
[0]);
3143 case FS_OPCODE_FB_WRITE
:
3144 generate_fb_write(inst
);
3147 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3148 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3149 brw_opcodes
[inst
->opcode
].name
);
3151 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3156 if (annotation_len
< p
->nr_insn
) {
3157 annotation_len
*= 2;
3158 if (annotation_len
< 16)
3159 annotation_len
= 16;
3161 this->annotation_string
= talloc_realloc(this->mem_ctx
,
3165 this->annotation_ir
= talloc_realloc(this->mem_ctx
,
3171 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3172 this->annotation_string
[i
] = inst
->annotation
;
3173 this->annotation_ir
[i
] = inst
->ir
;
3175 last_native_inst
= p
->nr_insn
;
3180 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3182 struct brw_compile
*p
= &c
->func
;
3183 struct intel_context
*intel
= &brw
->intel
;
3184 struct gl_context
*ctx
= &intel
->ctx
;
3185 struct brw_shader
*shader
= NULL
;
3186 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
3191 for (unsigned int i
= 0; i
< prog
->_NumLinkedShaders
; i
++) {
3192 if (prog
->_LinkedShaders
[i
]->Type
== GL_FRAGMENT_SHADER
) {
3193 shader
= (struct brw_shader
*)prog
->_LinkedShaders
[i
];
3200 /* We always use 8-wide mode, at least for now. For one, flow
3201 * control only works in 8-wide. Also, when we're fragment shader
3202 * bound, we're almost always under register pressure as well, so
3203 * 8-wide would save us from the performance cliff of spilling
3206 c
->dispatch_width
= 8;
3208 if (INTEL_DEBUG
& DEBUG_WM
) {
3209 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3210 _mesa_print_ir(shader
->ir
, NULL
);
3214 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3216 fs_visitor
v(c
, shader
);
3221 v
.calculate_urb_setup();
3223 v
.emit_interpolation_setup_gen4();
3225 v
.emit_interpolation_setup_gen6();
3227 /* Generate FS IR for main(). (the visitor only descends into
3228 * functions called "main").
3230 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3231 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3238 v
.split_virtual_grfs();
3240 v
.assign_curb_setup();
3241 v
.assign_urb_setup();
3246 v
.calculate_live_intervals();
3247 progress
= v
.propagate_constants() || progress
;
3248 progress
= v
.register_coalesce() || progress
;
3249 progress
= v
.compute_to_mrf() || progress
;
3250 progress
= v
.dead_code_eliminate() || progress
;
3254 v
.assign_regs_trivial();
3262 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3267 if (INTEL_DEBUG
& DEBUG_WM
) {
3268 const char *last_annotation_string
= NULL
;
3269 ir_instruction
*last_annotation_ir
= NULL
;
3271 printf("Native code for fragment shader %d:\n", prog
->Name
);
3272 for (unsigned int i
= 0; i
< p
->nr_insn
; i
++) {
3273 if (last_annotation_ir
!= v
.annotation_ir
[i
]) {
3274 last_annotation_ir
= v
.annotation_ir
[i
];
3275 if (last_annotation_ir
) {
3277 last_annotation_ir
->print();
3281 if (last_annotation_string
!= v
.annotation_string
[i
]) {
3282 last_annotation_string
= v
.annotation_string
[i
];
3283 if (last_annotation_string
)
3284 printf(" %s\n", last_annotation_string
);
3286 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3291 c
->prog_data
.total_grf
= v
.grf_used
;
3292 c
->prog_data
.total_scratch
= 0;