2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
30 #include <sys/types.h>
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
51 static struct brw_reg
brw_reg_from_fs_reg(class fs_reg
*reg
);
54 brw_new_shader(struct gl_context
*ctx
, GLuint name
, GLuint type
)
56 struct brw_shader
*shader
;
58 shader
= talloc_zero(NULL
, struct brw_shader
);
60 shader
->base
.Type
= type
;
61 shader
->base
.Name
= name
;
62 _mesa_init_shader(ctx
, &shader
->base
);
68 struct gl_shader_program
*
69 brw_new_shader_program(struct gl_context
*ctx
, GLuint name
)
71 struct brw_shader_program
*prog
;
72 prog
= talloc_zero(NULL
, struct brw_shader_program
);
74 prog
->base
.Name
= name
;
75 _mesa_init_shader_program(ctx
, &prog
->base
);
81 brw_compile_shader(struct gl_context
*ctx
, struct gl_shader
*shader
)
83 if (!_mesa_ir_compile_shader(ctx
, shader
))
90 brw_link_shader(struct gl_context
*ctx
, struct gl_shader_program
*prog
)
92 struct intel_context
*intel
= intel_context(ctx
);
94 struct brw_shader
*shader
=
95 (struct brw_shader
*)prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
97 void *mem_ctx
= talloc_new(NULL
);
101 talloc_free(shader
->ir
);
102 shader
->ir
= new(shader
) exec_list
;
103 clone_ir_list(mem_ctx
, shader
->ir
, shader
->base
.ir
);
105 do_mat_op_to_vec(shader
->ir
);
106 do_mod_to_fract(shader
->ir
);
107 do_div_to_mul_rcp(shader
->ir
);
108 do_sub_to_add_neg(shader
->ir
);
109 do_explog_to_explog2(shader
->ir
);
110 do_lower_texture_projection(shader
->ir
);
111 brw_do_cubemap_normalize(shader
->ir
);
116 brw_do_channel_expressions(shader
->ir
);
117 brw_do_vector_splitting(shader
->ir
);
119 progress
= do_lower_jumps(shader
->ir
, true, true,
120 true, /* main return */
121 false, /* continue */
125 progress
= do_common_optimization(shader
->ir
, true, 32) || progress
;
127 progress
= lower_noise(shader
->ir
) || progress
;
129 lower_variable_index_to_cond_assign(shader
->ir
,
131 GL_TRUE
, /* output */
133 GL_TRUE
/* uniform */
135 if (intel
->gen
== 6) {
136 progress
= do_if_to_cond_assign(shader
->ir
) || progress
;
140 validate_ir_tree(shader
->ir
);
142 reparent_ir(shader
->ir
, shader
->ir
);
143 talloc_free(mem_ctx
);
146 if (!_mesa_ir_link_shader(ctx
, prog
))
153 type_size(const struct glsl_type
*type
)
155 unsigned int size
, i
;
157 switch (type
->base_type
) {
160 case GLSL_TYPE_FLOAT
:
162 return type
->components();
163 case GLSL_TYPE_ARRAY
:
164 return type_size(type
->fields
.array
) * type
->length
;
165 case GLSL_TYPE_STRUCT
:
167 for (i
= 0; i
< type
->length
; i
++) {
168 size
+= type_size(type
->fields
.structure
[i
].type
);
171 case GLSL_TYPE_SAMPLER
:
172 /* Samplers take up no register space, since they're baked in at
177 assert(!"not reached");
183 fs_visitor::virtual_grf_alloc(int size
)
185 if (virtual_grf_array_size
<= virtual_grf_next
) {
186 if (virtual_grf_array_size
== 0)
187 virtual_grf_array_size
= 16;
189 virtual_grf_array_size
*= 2;
190 virtual_grf_sizes
= talloc_realloc(mem_ctx
, virtual_grf_sizes
,
191 int, virtual_grf_array_size
);
193 /* This slot is always unused. */
194 virtual_grf_sizes
[0] = 0;
196 virtual_grf_sizes
[virtual_grf_next
] = size
;
197 return virtual_grf_next
++;
200 /** Fixed HW reg constructor. */
201 fs_reg::fs_reg(enum register_file file
, int hw_reg
)
205 this->hw_reg
= hw_reg
;
206 this->type
= BRW_REGISTER_TYPE_F
;
209 /** Fixed HW reg constructor. */
210 fs_reg::fs_reg(enum register_file file
, int hw_reg
, uint32_t type
)
214 this->hw_reg
= hw_reg
;
219 brw_type_for_base_type(const struct glsl_type
*type
)
221 switch (type
->base_type
) {
222 case GLSL_TYPE_FLOAT
:
223 return BRW_REGISTER_TYPE_F
;
226 return BRW_REGISTER_TYPE_D
;
228 return BRW_REGISTER_TYPE_UD
;
229 case GLSL_TYPE_ARRAY
:
230 case GLSL_TYPE_STRUCT
:
231 /* These should be overridden with the type of the member when
232 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
233 * way to trip up if we don't.
235 return BRW_REGISTER_TYPE_UD
;
237 assert(!"not reached");
238 return BRW_REGISTER_TYPE_F
;
242 /** Automatic reg constructor. */
243 fs_reg::fs_reg(class fs_visitor
*v
, const struct glsl_type
*type
)
248 this->reg
= v
->virtual_grf_alloc(type_size(type
));
249 this->reg_offset
= 0;
250 this->type
= brw_type_for_base_type(type
);
254 fs_visitor::variable_storage(ir_variable
*var
)
256 return (fs_reg
*)hash_table_find(this->variable_ht
, var
);
259 /* Our support for uniforms is piggy-backed on the struct
260 * gl_fragment_program, because that's where the values actually
261 * get stored, rather than in some global gl_shader_program uniform
265 fs_visitor::setup_uniform_values(int loc
, const glsl_type
*type
)
267 unsigned int offset
= 0;
270 if (type
->is_matrix()) {
271 const glsl_type
*column
= glsl_type::get_instance(GLSL_TYPE_FLOAT
,
272 type
->vector_elements
,
275 for (unsigned int i
= 0; i
< type
->matrix_columns
; i
++) {
276 offset
+= setup_uniform_values(loc
+ offset
, column
);
282 switch (type
->base_type
) {
283 case GLSL_TYPE_FLOAT
:
287 vec_values
= fp
->Base
.Parameters
->ParameterValues
[loc
];
288 for (unsigned int i
= 0; i
< type
->vector_elements
; i
++) {
289 assert(c
->prog_data
.nr_params
< ARRAY_SIZE(c
->prog_data
.param
));
290 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[i
];
294 case GLSL_TYPE_STRUCT
:
295 for (unsigned int i
= 0; i
< type
->length
; i
++) {
296 offset
+= setup_uniform_values(loc
+ offset
,
297 type
->fields
.structure
[i
].type
);
301 case GLSL_TYPE_ARRAY
:
302 for (unsigned int i
= 0; i
< type
->length
; i
++) {
303 offset
+= setup_uniform_values(loc
+ offset
, type
->fields
.array
);
307 case GLSL_TYPE_SAMPLER
:
308 /* The sampler takes up a slot, but we don't use any values from it. */
312 assert(!"not reached");
318 /* Our support for builtin uniforms is even scarier than non-builtin.
319 * It sits on top of the PROG_STATE_VAR parameters that are
320 * automatically updated from GL context state.
323 fs_visitor::setup_builtin_uniform_values(ir_variable
*ir
)
325 const struct gl_builtin_uniform_desc
*statevar
= NULL
;
327 for (unsigned int i
= 0; _mesa_builtin_uniform_desc
[i
].name
; i
++) {
328 statevar
= &_mesa_builtin_uniform_desc
[i
];
329 if (strcmp(ir
->name
, _mesa_builtin_uniform_desc
[i
].name
) == 0)
333 if (!statevar
->name
) {
335 printf("Failed to find builtin uniform `%s'\n", ir
->name
);
340 if (ir
->type
->is_array()) {
341 array_count
= ir
->type
->length
;
346 for (int a
= 0; a
< array_count
; a
++) {
347 for (unsigned int i
= 0; i
< statevar
->num_elements
; i
++) {
348 struct gl_builtin_uniform_element
*element
= &statevar
->elements
[i
];
349 int tokens
[STATE_LENGTH
];
351 memcpy(tokens
, element
->tokens
, sizeof(element
->tokens
));
352 if (ir
->type
->is_array()) {
356 /* This state reference has already been setup by ir_to_mesa,
357 * but we'll get the same index back here.
359 int index
= _mesa_add_state_reference(this->fp
->Base
.Parameters
,
360 (gl_state_index
*)tokens
);
361 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
363 /* Add each of the unique swizzles of the element as a
364 * parameter. This'll end up matching the expected layout of
365 * the array/matrix/structure we're trying to fill in.
368 for (unsigned int i
= 0; i
< 4; i
++) {
369 int swiz
= GET_SWZ(element
->swizzle
, i
);
370 if (swiz
== last_swiz
)
374 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[swiz
];
381 fs_visitor::emit_fragcoord_interpolation(ir_variable
*ir
)
383 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
385 fs_reg neg_y
= this->pixel_y
;
389 if (ir
->pixel_center_integer
) {
390 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_x
));
392 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, this->pixel_x
, fs_reg(0.5f
)));
397 if (ir
->origin_upper_left
&& ir
->pixel_center_integer
) {
398 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->pixel_y
));
400 fs_reg pixel_y
= this->pixel_y
;
401 float offset
= (ir
->pixel_center_integer
? 0.0 : 0.5);
403 if (!ir
->origin_upper_left
) {
404 pixel_y
.negate
= true;
405 offset
+= c
->key
.drawable_height
- 1.0;
408 emit(fs_inst(BRW_OPCODE_ADD
, wpos
, pixel_y
, fs_reg(offset
)));
413 emit(fs_inst(FS_OPCODE_LINTERP
, wpos
, this->delta_x
, this->delta_y
,
414 interp_reg(FRAG_ATTRIB_WPOS
, 2)));
417 /* gl_FragCoord.w: Already set up in emit_interpolation */
418 emit(fs_inst(BRW_OPCODE_MOV
, wpos
, this->wpos_w
));
424 fs_visitor::emit_general_interpolation(ir_variable
*ir
)
426 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
427 /* Interpolation is always in floating point regs. */
428 reg
->type
= BRW_REGISTER_TYPE_F
;
431 unsigned int array_elements
;
432 const glsl_type
*type
;
434 if (ir
->type
->is_array()) {
435 array_elements
= ir
->type
->length
;
436 if (array_elements
== 0) {
439 type
= ir
->type
->fields
.array
;
445 int location
= ir
->location
;
446 for (unsigned int i
= 0; i
< array_elements
; i
++) {
447 for (unsigned int j
= 0; j
< type
->matrix_columns
; j
++) {
448 if (urb_setup
[location
] == -1) {
449 /* If there's no incoming setup data for this slot, don't
450 * emit interpolation for it.
452 attr
.reg_offset
+= type
->vector_elements
;
457 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
458 struct brw_reg interp
= interp_reg(location
, c
);
459 emit(fs_inst(FS_OPCODE_LINTERP
,
467 if (intel
->gen
< 6) {
468 attr
.reg_offset
-= type
->vector_elements
;
469 for (unsigned int c
= 0; c
< type
->vector_elements
; c
++) {
470 emit(fs_inst(BRW_OPCODE_MUL
,
485 fs_visitor::emit_frontfacing_interpolation(ir_variable
*ir
)
487 fs_reg
*reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
489 /* The frontfacing comes in as a bit in the thread payload. */
490 if (intel
->gen
>= 6) {
491 emit(fs_inst(BRW_OPCODE_ASR
,
493 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D
)),
495 emit(fs_inst(BRW_OPCODE_NOT
,
498 emit(fs_inst(BRW_OPCODE_AND
,
503 struct brw_reg r1_6ud
= retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
);
504 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
507 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
,
511 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
512 emit(fs_inst(BRW_OPCODE_AND
, *reg
, *reg
, fs_reg(1u)));
519 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src
)
531 assert(!"not reached: bad math opcode");
535 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
536 * might be able to do better by doing execsize = 1 math and then
537 * expanding that result out, but we would need to be careful with
540 if (intel
->gen
>= 6 && src
.file
== UNIFORM
) {
541 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
542 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src
));
546 fs_inst
*inst
= emit(fs_inst(opcode
, dst
, src
));
548 if (intel
->gen
< 6) {
557 fs_visitor::emit_math(fs_opcodes opcode
, fs_reg dst
, fs_reg src0
, fs_reg src1
)
562 assert(opcode
== FS_OPCODE_POW
);
564 if (intel
->gen
>= 6) {
565 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
566 if (src0
.file
== UNIFORM
) {
567 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
568 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src0
));
572 if (src1
.file
== UNIFORM
) {
573 fs_reg expanded
= fs_reg(this, glsl_type::float_type
);
574 emit(fs_inst(BRW_OPCODE_MOV
, expanded
, src1
));
578 inst
= emit(fs_inst(opcode
, dst
, src0
, src1
));
580 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ 1), src1
));
581 inst
= emit(fs_inst(opcode
, dst
, src0
, reg_null_f
));
583 inst
->base_mrf
= base_mrf
;
590 fs_visitor::visit(ir_variable
*ir
)
594 if (variable_storage(ir
))
597 if (strcmp(ir
->name
, "gl_FragColor") == 0) {
598 this->frag_color
= ir
;
599 } else if (strcmp(ir
->name
, "gl_FragData") == 0) {
600 this->frag_data
= ir
;
601 } else if (strcmp(ir
->name
, "gl_FragDepth") == 0) {
602 this->frag_depth
= ir
;
605 if (ir
->mode
== ir_var_in
) {
606 if (!strcmp(ir
->name
, "gl_FragCoord")) {
607 reg
= emit_fragcoord_interpolation(ir
);
608 } else if (!strcmp(ir
->name
, "gl_FrontFacing")) {
609 reg
= emit_frontfacing_interpolation(ir
);
611 reg
= emit_general_interpolation(ir
);
614 hash_table_insert(this->variable_ht
, reg
, ir
);
618 if (ir
->mode
== ir_var_uniform
) {
619 int param_index
= c
->prog_data
.nr_params
;
621 if (!strncmp(ir
->name
, "gl_", 3)) {
622 setup_builtin_uniform_values(ir
);
624 setup_uniform_values(ir
->location
, ir
->type
);
627 reg
= new(this->mem_ctx
) fs_reg(UNIFORM
, param_index
);
631 reg
= new(this->mem_ctx
) fs_reg(this, ir
->type
);
633 hash_table_insert(this->variable_ht
, reg
, ir
);
637 fs_visitor::visit(ir_dereference_variable
*ir
)
639 fs_reg
*reg
= variable_storage(ir
->var
);
644 fs_visitor::visit(ir_dereference_record
*ir
)
646 const glsl_type
*struct_type
= ir
->record
->type
;
648 ir
->record
->accept(this);
650 unsigned int offset
= 0;
651 for (unsigned int i
= 0; i
< struct_type
->length
; i
++) {
652 if (strcmp(struct_type
->fields
.structure
[i
].name
, ir
->field
) == 0)
654 offset
+= type_size(struct_type
->fields
.structure
[i
].type
);
656 this->result
.reg_offset
+= offset
;
657 this->result
.type
= brw_type_for_base_type(ir
->type
);
661 fs_visitor::visit(ir_dereference_array
*ir
)
666 ir
->array
->accept(this);
667 index
= ir
->array_index
->as_constant();
669 element_size
= type_size(ir
->type
);
670 this->result
.type
= brw_type_for_base_type(ir
->type
);
673 assert(this->result
.file
== UNIFORM
||
674 (this->result
.file
== GRF
&&
675 this->result
.reg
!= 0));
676 this->result
.reg_offset
+= index
->value
.i
[0] * element_size
;
678 assert(!"FINISHME: non-constant array element");
683 fs_visitor::visit(ir_expression
*ir
)
685 unsigned int operand
;
689 for (operand
= 0; operand
< ir
->get_num_operands(); operand
++) {
690 ir
->operands
[operand
]->accept(this);
691 if (this->result
.file
== BAD_FILE
) {
693 printf("Failed to get tree for expression operand:\n");
694 ir
->operands
[operand
]->accept(&v
);
697 op
[operand
] = this->result
;
699 /* Matrix expression operands should have been broken down to vector
700 * operations already.
702 assert(!ir
->operands
[operand
]->type
->is_matrix());
703 /* And then those vector operands should have been broken down to scalar.
705 assert(!ir
->operands
[operand
]->type
->is_vector());
708 /* Storage for our result. If our result goes into an assignment, it will
709 * just get copy-propagated out, so no worries.
711 this->result
= fs_reg(this, ir
->type
);
713 switch (ir
->operation
) {
714 case ir_unop_logic_not
:
715 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
716 * ones complement of the whole register, not just bit 0.
718 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], fs_reg(1)));
721 op
[0].negate
= !op
[0].negate
;
722 this->result
= op
[0];
726 this->result
= op
[0];
729 temp
= fs_reg(this, ir
->type
);
731 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(0.0f
)));
733 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
734 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
735 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(1.0f
)));
736 inst
->predicated
= true;
738 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_f
, op
[0], fs_reg(0.0f
)));
739 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
740 inst
= emit(fs_inst(BRW_OPCODE_MOV
, this->result
, fs_reg(-1.0f
)));
741 inst
->predicated
= true;
745 emit_math(FS_OPCODE_RCP
, this->result
, op
[0]);
749 emit_math(FS_OPCODE_EXP2
, this->result
, op
[0]);
752 emit_math(FS_OPCODE_LOG2
, this->result
, op
[0]);
756 assert(!"not reached: should be handled by ir_explog_to_explog2");
759 emit_math(FS_OPCODE_SIN
, this->result
, op
[0]);
762 emit_math(FS_OPCODE_COS
, this->result
, op
[0]);
766 emit(fs_inst(FS_OPCODE_DDX
, this->result
, op
[0]));
769 emit(fs_inst(FS_OPCODE_DDY
, this->result
, op
[0]));
773 emit(fs_inst(BRW_OPCODE_ADD
, this->result
, op
[0], op
[1]));
776 assert(!"not reached: should be handled by ir_sub_to_add_neg");
780 emit(fs_inst(BRW_OPCODE_MUL
, this->result
, op
[0], op
[1]));
783 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
786 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
790 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
791 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
792 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
794 case ir_binop_greater
:
795 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
796 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
797 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
799 case ir_binop_lequal
:
800 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
801 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
802 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
804 case ir_binop_gequal
:
805 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
806 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
807 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
810 case ir_binop_all_equal
: /* same as nequal for scalars */
811 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
812 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
813 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
815 case ir_binop_nequal
:
816 case ir_binop_any_nequal
: /* same as nequal for scalars */
817 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
818 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
819 emit(fs_inst(BRW_OPCODE_AND
, this->result
, this->result
, fs_reg(0x1)));
822 case ir_binop_logic_xor
:
823 emit(fs_inst(BRW_OPCODE_XOR
, this->result
, op
[0], op
[1]));
826 case ir_binop_logic_or
:
827 emit(fs_inst(BRW_OPCODE_OR
, this->result
, op
[0], op
[1]));
830 case ir_binop_logic_and
:
831 emit(fs_inst(BRW_OPCODE_AND
, this->result
, op
[0], op
[1]));
837 assert(!"not reached: should be handled by brw_fs_channel_expressions");
841 assert(!"not reached: should be handled by lower_noise");
845 emit_math(FS_OPCODE_SQRT
, this->result
, op
[0]);
849 emit_math(FS_OPCODE_RSQ
, this->result
, op
[0]);
856 emit(fs_inst(BRW_OPCODE_MOV
, this->result
, op
[0]));
860 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], fs_reg(0.0f
)));
861 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
862 inst
= emit(fs_inst(BRW_OPCODE_AND
, this->result
,
863 this->result
, fs_reg(1)));
867 emit(fs_inst(BRW_OPCODE_RNDZ
, this->result
, op
[0]));
870 op
[0].negate
= !op
[0].negate
;
871 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
872 this->result
.negate
= true;
875 inst
= emit(fs_inst(BRW_OPCODE_RNDD
, this->result
, op
[0]));
878 inst
= emit(fs_inst(BRW_OPCODE_FRC
, this->result
, op
[0]));
880 case ir_unop_round_even
:
881 emit(fs_inst(BRW_OPCODE_RNDE
, this->result
, op
[0]));
885 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
886 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
888 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
889 inst
->predicated
= true;
892 inst
= emit(fs_inst(BRW_OPCODE_CMP
, this->result
, op
[0], op
[1]));
893 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
895 inst
= emit(fs_inst(BRW_OPCODE_SEL
, this->result
, op
[0], op
[1]));
896 inst
->predicated
= true;
900 emit_math(FS_OPCODE_POW
, this->result
, op
[0], op
[1]);
903 case ir_unop_bit_not
:
905 case ir_binop_lshift
:
906 case ir_binop_rshift
:
907 case ir_binop_bit_and
:
908 case ir_binop_bit_xor
:
909 case ir_binop_bit_or
:
910 assert(!"GLSL 1.30 features unsupported");
916 fs_visitor::emit_assignment_writes(fs_reg
&l
, fs_reg
&r
,
917 const glsl_type
*type
, bool predicated
)
919 switch (type
->base_type
) {
920 case GLSL_TYPE_FLOAT
:
924 for (unsigned int i
= 0; i
< type
->components(); i
++) {
925 l
.type
= brw_type_for_base_type(type
);
926 r
.type
= brw_type_for_base_type(type
);
928 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
929 inst
->predicated
= predicated
;
935 case GLSL_TYPE_ARRAY
:
936 for (unsigned int i
= 0; i
< type
->length
; i
++) {
937 emit_assignment_writes(l
, r
, type
->fields
.array
, predicated
);
941 case GLSL_TYPE_STRUCT
:
942 for (unsigned int i
= 0; i
< type
->length
; i
++) {
943 emit_assignment_writes(l
, r
, type
->fields
.structure
[i
].type
,
948 case GLSL_TYPE_SAMPLER
:
952 assert(!"not reached");
958 fs_visitor::visit(ir_assignment
*ir
)
963 /* FINISHME: arrays on the lhs */
964 ir
->lhs
->accept(this);
967 ir
->rhs
->accept(this);
970 assert(l
.file
!= BAD_FILE
);
971 assert(r
.file
!= BAD_FILE
);
974 emit_bool_to_cond_code(ir
->condition
);
977 if (ir
->lhs
->type
->is_scalar() ||
978 ir
->lhs
->type
->is_vector()) {
979 for (int i
= 0; i
< ir
->lhs
->type
->vector_elements
; i
++) {
980 if (ir
->write_mask
& (1 << i
)) {
981 inst
= emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
983 inst
->predicated
= true;
989 emit_assignment_writes(l
, r
, ir
->lhs
->type
, ir
->condition
!= NULL
);
994 fs_visitor::emit_texture_gen4(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1004 if (ir
->shadow_comparitor
) {
1005 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1006 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1008 coordinate
.reg_offset
++;
1010 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1013 if (ir
->op
== ir_tex
) {
1014 /* There's no plain shadow compare message, so we use shadow
1015 * compare with a bias of 0.0.
1017 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1020 } else if (ir
->op
== ir_txb
) {
1021 ir
->lod_info
.bias
->accept(this);
1022 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1026 assert(ir
->op
== ir_txl
);
1027 ir
->lod_info
.lod
->accept(this);
1028 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1033 ir
->shadow_comparitor
->accept(this);
1034 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1036 } else if (ir
->op
== ir_tex
) {
1037 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1038 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1040 coordinate
.reg_offset
++;
1042 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1045 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1046 * instructions. We'll need to do SIMD16 here.
1048 assert(ir
->op
== ir_txb
|| ir
->op
== ir_txl
);
1050 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1051 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
* 2),
1053 coordinate
.reg_offset
++;
1056 /* lod/bias appears after u/v/r. */
1059 if (ir
->op
== ir_txb
) {
1060 ir
->lod_info
.bias
->accept(this);
1061 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1065 ir
->lod_info
.lod
->accept(this);
1066 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
),
1071 /* The unused upper half. */
1074 /* Now, since we're doing simd16, the return is 2 interleaved
1075 * vec4s where the odd-indexed ones are junk. We'll need to move
1076 * this weirdness around to the expected layout.
1080 dst
= fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type
,
1082 dst
.type
= BRW_REGISTER_TYPE_F
;
1085 fs_inst
*inst
= NULL
;
1088 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1091 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1094 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1098 assert(!"GLSL 1.30 features unsupported");
1101 inst
->base_mrf
= base_mrf
;
1105 for (int i
= 0; i
< 4; i
++) {
1106 emit(fs_inst(BRW_OPCODE_MOV
, orig_dst
, dst
));
1107 orig_dst
.reg_offset
++;
1108 dst
.reg_offset
+= 2;
1116 fs_visitor::emit_texture_gen5(ir_texture
*ir
, fs_reg dst
, fs_reg coordinate
)
1118 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1119 * optional parameters like shadow comparitor or LOD bias. If
1120 * optional parameters aren't present, those base slots are
1121 * optional and don't need to be included in the message.
1123 * We don't fill in the unnecessary slots regardless, which may
1124 * look surprising in the disassembly.
1126 int mlen
= 1; /* g0 header always present. */
1129 for (int i
= 0; i
< ir
->coordinate
->type
->vector_elements
; i
++) {
1130 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
+ i
),
1132 coordinate
.reg_offset
++;
1134 mlen
+= ir
->coordinate
->type
->vector_elements
;
1136 if (ir
->shadow_comparitor
) {
1137 mlen
= MAX2(mlen
, 5);
1139 ir
->shadow_comparitor
->accept(this);
1140 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1144 fs_inst
*inst
= NULL
;
1147 inst
= emit(fs_inst(FS_OPCODE_TEX
, dst
));
1150 ir
->lod_info
.bias
->accept(this);
1151 mlen
= MAX2(mlen
, 5);
1152 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1155 inst
= emit(fs_inst(FS_OPCODE_TXB
, dst
));
1158 ir
->lod_info
.lod
->accept(this);
1159 mlen
= MAX2(mlen
, 5);
1160 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, base_mrf
+ mlen
), this->result
));
1163 inst
= emit(fs_inst(FS_OPCODE_TXL
, dst
));
1167 assert(!"GLSL 1.30 features unsupported");
1170 inst
->base_mrf
= base_mrf
;
1177 fs_visitor::visit(ir_texture
*ir
)
1180 fs_inst
*inst
= NULL
;
1182 ir
->coordinate
->accept(this);
1183 fs_reg coordinate
= this->result
;
1185 /* Should be lowered by do_lower_texture_projection */
1186 assert(!ir
->projector
);
1188 sampler
= _mesa_get_sampler_uniform_value(ir
->sampler
,
1189 ctx
->Shader
.CurrentProgram
,
1190 &brw
->fragment_program
->Base
);
1191 sampler
= c
->fp
->program
.Base
.SamplerUnits
[sampler
];
1193 /* The 965 requires the EU to do the normalization of GL rectangle
1194 * texture coordinates. We use the program parameter state
1195 * tracking to get the scaling factor.
1197 if (ir
->sampler
->type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_RECT
) {
1198 struct gl_program_parameter_list
*params
= c
->fp
->program
.Base
.Parameters
;
1199 int tokens
[STATE_LENGTH
] = {
1201 STATE_TEXRECT_SCALE
,
1207 fs_reg scale_x
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
);
1208 fs_reg scale_y
= fs_reg(UNIFORM
, c
->prog_data
.nr_params
+ 1);
1209 GLuint index
= _mesa_add_state_reference(params
,
1210 (gl_state_index
*)tokens
);
1211 float *vec_values
= this->fp
->Base
.Parameters
->ParameterValues
[index
];
1213 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[0];
1214 c
->prog_data
.param
[c
->prog_data
.nr_params
++] = &vec_values
[1];
1216 fs_reg dst
= fs_reg(this, ir
->coordinate
->type
);
1217 fs_reg src
= coordinate
;
1220 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_x
));
1223 emit(fs_inst(BRW_OPCODE_MUL
, dst
, src
, scale_y
));
1226 /* Writemasking doesn't eliminate channels on SIMD8 texture
1227 * samples, so don't worry about them.
1229 fs_reg dst
= fs_reg(this, glsl_type::vec4_type
);
1231 if (intel
->gen
< 5) {
1232 inst
= emit_texture_gen4(ir
, dst
, coordinate
);
1234 inst
= emit_texture_gen5(ir
, dst
, coordinate
);
1237 inst
->sampler
= sampler
;
1241 if (ir
->shadow_comparitor
)
1242 inst
->shadow_compare
= true;
1244 if (c
->key
.tex_swizzles
[inst
->sampler
] != SWIZZLE_NOOP
) {
1245 fs_reg swizzle_dst
= fs_reg(this, glsl_type::vec4_type
);
1247 for (int i
= 0; i
< 4; i
++) {
1248 int swiz
= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1249 fs_reg l
= swizzle_dst
;
1252 if (swiz
== SWIZZLE_ZERO
) {
1253 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(0.0f
)));
1254 } else if (swiz
== SWIZZLE_ONE
) {
1255 emit(fs_inst(BRW_OPCODE_MOV
, l
, fs_reg(1.0f
)));
1258 r
.reg_offset
+= GET_SWZ(c
->key
.tex_swizzles
[inst
->sampler
], i
);
1259 emit(fs_inst(BRW_OPCODE_MOV
, l
, r
));
1262 this->result
= swizzle_dst
;
1267 fs_visitor::visit(ir_swizzle
*ir
)
1269 ir
->val
->accept(this);
1270 fs_reg val
= this->result
;
1272 if (ir
->type
->vector_elements
== 1) {
1273 this->result
.reg_offset
+= ir
->mask
.x
;
1277 fs_reg result
= fs_reg(this, ir
->type
);
1278 this->result
= result
;
1280 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1281 fs_reg channel
= val
;
1299 channel
.reg_offset
+= swiz
;
1300 emit(fs_inst(BRW_OPCODE_MOV
, result
, channel
));
1301 result
.reg_offset
++;
1306 fs_visitor::visit(ir_discard
*ir
)
1308 fs_reg temp
= fs_reg(this, glsl_type::uint_type
);
1310 assert(ir
->condition
== NULL
); /* FINISHME */
1312 emit(fs_inst(FS_OPCODE_DISCARD_NOT
, temp
, reg_null_d
));
1313 emit(fs_inst(FS_OPCODE_DISCARD_AND
, reg_null_d
, temp
));
1314 kill_emitted
= true;
1318 fs_visitor::visit(ir_constant
*ir
)
1320 fs_reg
reg(this, ir
->type
);
1323 for (unsigned int i
= 0; i
< ir
->type
->vector_elements
; i
++) {
1324 switch (ir
->type
->base_type
) {
1325 case GLSL_TYPE_FLOAT
:
1326 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.f
[i
])));
1328 case GLSL_TYPE_UINT
:
1329 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.u
[i
])));
1332 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg(ir
->value
.i
[i
])));
1334 case GLSL_TYPE_BOOL
:
1335 emit(fs_inst(BRW_OPCODE_MOV
, reg
, fs_reg((int)ir
->value
.b
[i
])));
1338 assert(!"Non-float/uint/int/bool constant");
1345 fs_visitor::emit_bool_to_cond_code(ir_rvalue
*ir
)
1347 ir_expression
*expr
= ir
->as_expression();
1353 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1354 assert(expr
->operands
[i
]->type
->is_scalar());
1356 expr
->operands
[i
]->accept(this);
1357 op
[i
] = this->result
;
1360 switch (expr
->operation
) {
1361 case ir_unop_logic_not
:
1362 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], fs_reg(1)));
1363 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1366 case ir_binop_logic_xor
:
1367 inst
= emit(fs_inst(BRW_OPCODE_XOR
, reg_null_d
, op
[0], op
[1]));
1368 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1371 case ir_binop_logic_or
:
1372 inst
= emit(fs_inst(BRW_OPCODE_OR
, reg_null_d
, op
[0], op
[1]));
1373 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1376 case ir_binop_logic_and
:
1377 inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
, op
[0], op
[1]));
1378 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1382 if (intel
->gen
>= 6) {
1383 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1384 op
[0], fs_reg(0.0f
)));
1386 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1388 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1392 if (intel
->gen
>= 6) {
1393 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], fs_reg(0)));
1395 inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, op
[0]));
1397 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1400 case ir_binop_greater
:
1401 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1402 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1404 case ir_binop_gequal
:
1405 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1406 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1409 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1410 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1412 case ir_binop_lequal
:
1413 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1414 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1416 case ir_binop_equal
:
1417 case ir_binop_all_equal
:
1418 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1419 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1421 case ir_binop_nequal
:
1422 case ir_binop_any_nequal
:
1423 inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
, op
[0], op
[1]));
1424 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1427 assert(!"not reached");
1436 if (intel
->gen
>= 6) {
1437 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_AND
, reg_null_d
,
1438 this->result
, fs_reg(1)));
1439 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1441 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_MOV
, reg_null_d
, this->result
));
1442 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1447 * Emit a gen6 IF statement with the comparison folded into the IF
1451 fs_visitor::emit_if_gen6(ir_if
*ir
)
1453 ir_expression
*expr
= ir
->condition
->as_expression();
1460 for (unsigned int i
= 0; i
< expr
->get_num_operands(); i
++) {
1461 assert(expr
->operands
[i
]->type
->is_scalar());
1463 expr
->operands
[i
]->accept(this);
1464 op
[i
] = this->result
;
1467 switch (expr
->operation
) {
1468 case ir_unop_logic_not
:
1469 inst
= emit(fs_inst(BRW_OPCODE_IF
, temp
, op
[0], fs_reg(1)));
1470 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1473 case ir_binop_logic_xor
:
1474 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1475 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1478 case ir_binop_logic_or
:
1479 temp
= fs_reg(this, glsl_type::bool_type
);
1480 emit(fs_inst(BRW_OPCODE_OR
, temp
, op
[0], op
[1]));
1481 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1482 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1485 case ir_binop_logic_and
:
1486 temp
= fs_reg(this, glsl_type::bool_type
);
1487 emit(fs_inst(BRW_OPCODE_AND
, temp
, op
[0], op
[1]));
1488 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, temp
, fs_reg(0)));
1489 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1493 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_f
, op
[0], fs_reg(0)));
1494 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1498 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1499 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1502 case ir_binop_greater
:
1503 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1504 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1506 case ir_binop_gequal
:
1507 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1508 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1511 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1512 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1514 case ir_binop_lequal
:
1515 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1516 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1518 case ir_binop_equal
:
1519 case ir_binop_all_equal
:
1520 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1521 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1523 case ir_binop_nequal
:
1524 case ir_binop_any_nequal
:
1525 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], op
[1]));
1526 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1529 assert(!"not reached");
1530 inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, op
[0], fs_reg(0)));
1531 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1538 ir
->condition
->accept(this);
1540 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_IF
, reg_null_d
, this->result
, fs_reg(0)));
1541 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1545 fs_visitor::visit(ir_if
*ir
)
1549 /* Don't point the annotation at the if statement, because then it plus
1550 * the then and else blocks get printed.
1552 this->base_ir
= ir
->condition
;
1554 if (intel
->gen
>= 6) {
1557 emit_bool_to_cond_code(ir
->condition
);
1559 inst
= emit(fs_inst(BRW_OPCODE_IF
));
1560 inst
->predicated
= true;
1563 foreach_iter(exec_list_iterator
, iter
, ir
->then_instructions
) {
1564 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1570 if (!ir
->else_instructions
.is_empty()) {
1571 emit(fs_inst(BRW_OPCODE_ELSE
));
1573 foreach_iter(exec_list_iterator
, iter
, ir
->else_instructions
) {
1574 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1581 emit(fs_inst(BRW_OPCODE_ENDIF
));
1585 fs_visitor::visit(ir_loop
*ir
)
1587 fs_reg counter
= reg_undef
;
1590 this->base_ir
= ir
->counter
;
1591 ir
->counter
->accept(this);
1592 counter
= *(variable_storage(ir
->counter
));
1595 this->base_ir
= ir
->from
;
1596 ir
->from
->accept(this);
1598 emit(fs_inst(BRW_OPCODE_MOV
, counter
, this->result
));
1602 emit(fs_inst(BRW_OPCODE_DO
));
1605 this->base_ir
= ir
->to
;
1606 ir
->to
->accept(this);
1608 fs_inst
*inst
= emit(fs_inst(BRW_OPCODE_CMP
, reg_null_d
,
1609 counter
, this->result
));
1611 case ir_binop_equal
:
1612 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1614 case ir_binop_nequal
:
1615 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
1617 case ir_binop_gequal
:
1618 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
1620 case ir_binop_lequal
:
1621 inst
->conditional_mod
= BRW_CONDITIONAL_LE
;
1623 case ir_binop_greater
:
1624 inst
->conditional_mod
= BRW_CONDITIONAL_G
;
1627 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
1630 assert(!"not reached: unknown loop condition");
1635 inst
= emit(fs_inst(BRW_OPCODE_BREAK
));
1636 inst
->predicated
= true;
1639 foreach_iter(exec_list_iterator
, iter
, ir
->body_instructions
) {
1640 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1646 if (ir
->increment
) {
1647 this->base_ir
= ir
->increment
;
1648 ir
->increment
->accept(this);
1649 emit(fs_inst(BRW_OPCODE_ADD
, counter
, counter
, this->result
));
1652 emit(fs_inst(BRW_OPCODE_WHILE
));
1656 fs_visitor::visit(ir_loop_jump
*ir
)
1659 case ir_loop_jump::jump_break
:
1660 emit(fs_inst(BRW_OPCODE_BREAK
));
1662 case ir_loop_jump::jump_continue
:
1663 emit(fs_inst(BRW_OPCODE_CONTINUE
));
1669 fs_visitor::visit(ir_call
*ir
)
1671 assert(!"FINISHME");
1675 fs_visitor::visit(ir_return
*ir
)
1677 assert(!"FINISHME");
1681 fs_visitor::visit(ir_function
*ir
)
1683 /* Ignore function bodies other than main() -- we shouldn't see calls to
1684 * them since they should all be inlined before we get to ir_to_mesa.
1686 if (strcmp(ir
->name
, "main") == 0) {
1687 const ir_function_signature
*sig
;
1690 sig
= ir
->matching_signature(&empty
);
1694 foreach_iter(exec_list_iterator
, iter
, sig
->body
) {
1695 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
1704 fs_visitor::visit(ir_function_signature
*ir
)
1706 assert(!"not reached");
1711 fs_visitor::emit(fs_inst inst
)
1713 fs_inst
*list_inst
= new(mem_ctx
) fs_inst
;
1716 list_inst
->annotation
= this->current_annotation
;
1717 list_inst
->ir
= this->base_ir
;
1719 this->instructions
.push_tail(list_inst
);
1724 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1726 fs_visitor::emit_dummy_fs()
1728 /* Everyone's favorite color. */
1729 emit(fs_inst(BRW_OPCODE_MOV
,
1732 emit(fs_inst(BRW_OPCODE_MOV
,
1735 emit(fs_inst(BRW_OPCODE_MOV
,
1738 emit(fs_inst(BRW_OPCODE_MOV
,
1743 write
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1746 write
->base_mrf
= 0;
1749 /* The register location here is relative to the start of the URB
1750 * data. It will get adjusted to be a real location before
1751 * generate_code() time.
1754 fs_visitor::interp_reg(int location
, int channel
)
1756 int regnr
= urb_setup
[location
] * 2 + channel
/ 2;
1757 int stride
= (channel
& 1) * 4;
1759 assert(urb_setup
[location
] != -1);
1761 return brw_vec1_grf(regnr
, stride
);
1764 /** Emits the interpolation for the varying inputs. */
1766 fs_visitor::emit_interpolation_setup_gen4()
1768 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1770 this->current_annotation
= "compute pixel centers";
1771 this->pixel_x
= fs_reg(this, glsl_type::uint_type
);
1772 this->pixel_y
= fs_reg(this, glsl_type::uint_type
);
1773 this->pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1774 this->pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1775 emit(fs_inst(BRW_OPCODE_ADD
,
1777 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1778 fs_reg(brw_imm_v(0x10101010))));
1779 emit(fs_inst(BRW_OPCODE_ADD
,
1781 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1782 fs_reg(brw_imm_v(0x11001100))));
1784 this->current_annotation
= "compute pixel deltas from v0";
1786 this->delta_x
= fs_reg(this, glsl_type::vec2_type
);
1787 this->delta_y
= this->delta_x
;
1788 this->delta_y
.reg_offset
++;
1790 this->delta_x
= fs_reg(this, glsl_type::float_type
);
1791 this->delta_y
= fs_reg(this, glsl_type::float_type
);
1793 emit(fs_inst(BRW_OPCODE_ADD
,
1796 fs_reg(negate(brw_vec1_grf(1, 0)))));
1797 emit(fs_inst(BRW_OPCODE_ADD
,
1800 fs_reg(negate(brw_vec1_grf(1, 1)))));
1802 this->current_annotation
= "compute pos.w and 1/pos.w";
1803 /* Compute wpos.w. It's always in our setup, since it's needed to
1804 * interpolate the other attributes.
1806 this->wpos_w
= fs_reg(this, glsl_type::float_type
);
1807 emit(fs_inst(FS_OPCODE_LINTERP
, wpos_w
, this->delta_x
, this->delta_y
,
1808 interp_reg(FRAG_ATTRIB_WPOS
, 3)));
1809 /* Compute the pixel 1/W value from wpos.w. */
1810 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1811 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1812 this->current_annotation
= NULL
;
1815 /** Emits the interpolation for the varying inputs. */
1817 fs_visitor::emit_interpolation_setup_gen6()
1819 struct brw_reg g1_uw
= retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW
);
1821 /* If the pixel centers end up used, the setup is the same as for gen4. */
1822 this->current_annotation
= "compute pixel centers";
1823 fs_reg int_pixel_x
= fs_reg(this, glsl_type::uint_type
);
1824 fs_reg int_pixel_y
= fs_reg(this, glsl_type::uint_type
);
1825 int_pixel_x
.type
= BRW_REGISTER_TYPE_UW
;
1826 int_pixel_y
.type
= BRW_REGISTER_TYPE_UW
;
1827 emit(fs_inst(BRW_OPCODE_ADD
,
1829 fs_reg(stride(suboffset(g1_uw
, 4), 2, 4, 0)),
1830 fs_reg(brw_imm_v(0x10101010))));
1831 emit(fs_inst(BRW_OPCODE_ADD
,
1833 fs_reg(stride(suboffset(g1_uw
, 5), 2, 4, 0)),
1834 fs_reg(brw_imm_v(0x11001100))));
1836 /* As of gen6, we can no longer mix float and int sources. We have
1837 * to turn the integer pixel centers into floats for their actual
1840 this->pixel_x
= fs_reg(this, glsl_type::float_type
);
1841 this->pixel_y
= fs_reg(this, glsl_type::float_type
);
1842 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_x
, int_pixel_x
));
1843 emit(fs_inst(BRW_OPCODE_MOV
, this->pixel_y
, int_pixel_y
));
1845 this->current_annotation
= "compute 1/pos.w";
1846 this->wpos_w
= fs_reg(brw_vec8_grf(c
->key
.source_w_reg
, 0));
1847 this->pixel_w
= fs_reg(this, glsl_type::float_type
);
1848 emit_math(FS_OPCODE_RCP
, this->pixel_w
, wpos_w
);
1850 this->delta_x
= fs_reg(brw_vec8_grf(2, 0));
1851 this->delta_y
= fs_reg(brw_vec8_grf(3, 0));
1853 this->current_annotation
= NULL
;
1857 fs_visitor::emit_fb_writes()
1859 this->current_annotation
= "FB write header";
1860 GLboolean header_present
= GL_TRUE
;
1863 if (intel
->gen
>= 6 &&
1864 !this->kill_emitted
&&
1865 c
->key
.nr_color_regions
== 1) {
1866 header_present
= false;
1869 if (header_present
) {
1874 if (c
->key
.aa_dest_stencil_reg
) {
1875 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1876 fs_reg(brw_vec8_grf(c
->key
.aa_dest_stencil_reg
, 0))));
1879 /* Reserve space for color. It'll be filled in per MRT below. */
1883 if (c
->key
.source_depth_to_render_target
) {
1884 if (c
->key
.computes_depth
) {
1885 /* Hand over gl_FragDepth. */
1886 assert(this->frag_depth
);
1887 fs_reg depth
= *(variable_storage(this->frag_depth
));
1889 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++), depth
));
1891 /* Pass through the payload depth. */
1892 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1893 fs_reg(brw_vec8_grf(c
->key
.source_depth_reg
, 0))));
1897 if (c
->key
.dest_depth_reg
) {
1898 emit(fs_inst(BRW_OPCODE_MOV
, fs_reg(MRF
, nr
++),
1899 fs_reg(brw_vec8_grf(c
->key
.dest_depth_reg
, 0))));
1902 fs_reg color
= reg_undef
;
1903 if (this->frag_color
)
1904 color
= *(variable_storage(this->frag_color
));
1905 else if (this->frag_data
)
1906 color
= *(variable_storage(this->frag_data
));
1908 for (int target
= 0; target
< c
->key
.nr_color_regions
; target
++) {
1909 this->current_annotation
= talloc_asprintf(this->mem_ctx
,
1910 "FB write target %d",
1912 if (this->frag_color
|| this->frag_data
) {
1913 for (int i
= 0; i
< 4; i
++) {
1914 emit(fs_inst(BRW_OPCODE_MOV
,
1915 fs_reg(MRF
, color_mrf
+ i
),
1921 if (this->frag_color
)
1922 color
.reg_offset
-= 4;
1924 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1925 reg_undef
, reg_undef
));
1926 inst
->target
= target
;
1929 if (target
== c
->key
.nr_color_regions
- 1)
1931 inst
->header_present
= header_present
;
1934 if (c
->key
.nr_color_regions
== 0) {
1935 fs_inst
*inst
= emit(fs_inst(FS_OPCODE_FB_WRITE
,
1936 reg_undef
, reg_undef
));
1940 inst
->header_present
= header_present
;
1943 this->current_annotation
= NULL
;
1947 fs_visitor::generate_fb_write(fs_inst
*inst
)
1949 GLboolean eot
= inst
->eot
;
1950 struct brw_reg implied_header
;
1952 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1955 brw_push_insn_state(p
);
1956 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
1957 brw_set_compression_control(p
, BRW_COMPRESSION_NONE
);
1959 if (inst
->header_present
) {
1960 if (intel
->gen
>= 6) {
1962 brw_message_reg(inst
->base_mrf
),
1963 brw_vec8_grf(0, 0));
1965 if (inst
->target
> 0) {
1966 /* Set the render target index for choosing BLEND_STATE. */
1967 brw_MOV(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 2),
1968 BRW_REGISTER_TYPE_UD
),
1969 brw_imm_ud(inst
->target
));
1972 /* Clear viewport index, render target array index. */
1973 brw_AND(p
, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE
, 0, 0),
1974 BRW_REGISTER_TYPE_UD
),
1975 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
1976 brw_imm_ud(0xf7ff));
1978 implied_header
= brw_null_reg();
1980 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1984 brw_message_reg(inst
->base_mrf
+ 1),
1985 brw_vec8_grf(1, 0));
1987 implied_header
= brw_null_reg();
1990 brw_pop_insn_state(p
);
1993 8, /* dispatch_width */
1994 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW
),
2004 fs_visitor::generate_linterp(fs_inst
*inst
,
2005 struct brw_reg dst
, struct brw_reg
*src
)
2007 struct brw_reg delta_x
= src
[0];
2008 struct brw_reg delta_y
= src
[1];
2009 struct brw_reg interp
= src
[2];
2012 delta_y
.nr
== delta_x
.nr
+ 1 &&
2013 (intel
->gen
>= 6 || (delta_x
.nr
& 1) == 0)) {
2014 brw_PLN(p
, dst
, interp
, delta_x
);
2016 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
2017 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
2022 fs_visitor::generate_math(fs_inst
*inst
,
2023 struct brw_reg dst
, struct brw_reg
*src
)
2027 switch (inst
->opcode
) {
2029 op
= BRW_MATH_FUNCTION_INV
;
2032 op
= BRW_MATH_FUNCTION_RSQ
;
2034 case FS_OPCODE_SQRT
:
2035 op
= BRW_MATH_FUNCTION_SQRT
;
2037 case FS_OPCODE_EXP2
:
2038 op
= BRW_MATH_FUNCTION_EXP
;
2040 case FS_OPCODE_LOG2
:
2041 op
= BRW_MATH_FUNCTION_LOG
;
2044 op
= BRW_MATH_FUNCTION_POW
;
2047 op
= BRW_MATH_FUNCTION_SIN
;
2050 op
= BRW_MATH_FUNCTION_COS
;
2053 assert(!"not reached: unknown math function");
2058 if (intel
->gen
>= 6) {
2059 assert(inst
->mlen
== 0);
2061 if (inst
->opcode
== FS_OPCODE_POW
) {
2062 brw_math2(p
, dst
, op
, src
[0], src
[1]);
2066 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2067 BRW_MATH_SATURATE_NONE
,
2069 BRW_MATH_DATA_VECTOR
,
2070 BRW_MATH_PRECISION_FULL
);
2073 assert(inst
->mlen
>= 1);
2077 inst
->saturate
? BRW_MATH_SATURATE_SATURATE
:
2078 BRW_MATH_SATURATE_NONE
,
2079 inst
->base_mrf
, src
[0],
2080 BRW_MATH_DATA_VECTOR
,
2081 BRW_MATH_PRECISION_FULL
);
2086 fs_visitor::generate_tex(fs_inst
*inst
, struct brw_reg dst
)
2090 uint32_t simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
2092 if (intel
->gen
>= 5) {
2093 switch (inst
->opcode
) {
2095 if (inst
->shadow_compare
) {
2096 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5
;
2098 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_GEN5
;
2102 if (inst
->shadow_compare
) {
2103 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5
;
2105 msg_type
= BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5
;
2110 switch (inst
->opcode
) {
2112 /* Note that G45 and older determines shadow compare and dispatch width
2113 * from message length for most messages.
2115 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2116 if (inst
->shadow_compare
) {
2117 assert(inst
->mlen
== 6);
2119 assert(inst
->mlen
<= 4);
2123 if (inst
->shadow_compare
) {
2124 assert(inst
->mlen
== 6);
2125 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
2127 assert(inst
->mlen
== 9);
2128 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
2129 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
2134 assert(msg_type
!= -1);
2136 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
2142 retype(dst
, BRW_REGISTER_TYPE_UW
),
2144 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
),
2145 SURF_INDEX_TEXTURE(inst
->sampler
),
2157 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2160 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2162 * and we're trying to produce:
2165 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2166 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2167 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2168 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2169 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2170 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2171 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2172 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2174 * and add another set of two more subspans if in 16-pixel dispatch mode.
2176 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2177 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2178 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2179 * between each other. We could probably do it like ddx and swizzle the right
2180 * order later, but bail for now and just produce
2181 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2184 fs_visitor::generate_ddx(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2186 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
2187 BRW_REGISTER_TYPE_F
,
2188 BRW_VERTICAL_STRIDE_2
,
2190 BRW_HORIZONTAL_STRIDE_0
,
2191 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2192 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
2193 BRW_REGISTER_TYPE_F
,
2194 BRW_VERTICAL_STRIDE_2
,
2196 BRW_HORIZONTAL_STRIDE_0
,
2197 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2198 brw_ADD(p
, dst
, src0
, negate(src1
));
2202 fs_visitor::generate_ddy(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
)
2204 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
2205 BRW_REGISTER_TYPE_F
,
2206 BRW_VERTICAL_STRIDE_4
,
2208 BRW_HORIZONTAL_STRIDE_0
,
2209 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2210 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
2211 BRW_REGISTER_TYPE_F
,
2212 BRW_VERTICAL_STRIDE_4
,
2214 BRW_HORIZONTAL_STRIDE_0
,
2215 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
2216 brw_ADD(p
, dst
, src0
, negate(src1
));
2220 fs_visitor::generate_discard_not(fs_inst
*inst
, struct brw_reg mask
)
2222 if (intel
->gen
>= 6) {
2223 /* Gen6 no longer has the mask reg for us to just read the
2224 * active channels from. However, cmp updates just the channels
2225 * of the flag reg that are enabled, so we can get at the
2226 * channel enables that way. In this step, make a reg of ones
2229 brw_MOV(p
, mask
, brw_imm_ud(1));
2231 brw_push_insn_state(p
);
2232 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2233 brw_NOT(p
, mask
, brw_mask_reg(1)); /* IMASK */
2234 brw_pop_insn_state(p
);
2239 fs_visitor::generate_discard_and(fs_inst
*inst
, struct brw_reg mask
)
2241 if (intel
->gen
>= 6) {
2242 struct brw_reg f0
= brw_flag_reg();
2243 struct brw_reg g1
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
2245 brw_push_insn_state(p
);
2246 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2247 brw_MOV(p
, f0
, brw_imm_uw(0xffff)); /* inactive channels undiscarded */
2248 brw_pop_insn_state(p
);
2250 brw_CMP(p
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
),
2251 BRW_CONDITIONAL_Z
, mask
, brw_imm_ud(0)); /* active channels fail test */
2252 /* Undo CMP's whacking of predication*/
2253 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
2255 brw_push_insn_state(p
);
2256 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2257 brw_AND(p
, g1
, f0
, g1
);
2258 brw_pop_insn_state(p
);
2260 struct brw_reg g0
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
2262 mask
= brw_uw1_reg(mask
.file
, mask
.nr
, 0);
2264 brw_push_insn_state(p
);
2265 brw_set_mask_control(p
, BRW_MASK_DISABLE
);
2266 brw_AND(p
, g0
, mask
, g0
);
2267 brw_pop_insn_state(p
);
2272 fs_visitor::generate_spill(fs_inst
*inst
, struct brw_reg src
)
2274 assert(inst
->mlen
!= 0);
2277 retype(brw_message_reg(inst
->base_mrf
+ 1), BRW_REGISTER_TYPE_UD
),
2278 retype(src
, BRW_REGISTER_TYPE_UD
));
2279 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
), 1,
2284 fs_visitor::generate_unspill(fs_inst
*inst
, struct brw_reg dst
)
2286 assert(inst
->mlen
!= 0);
2288 /* Clear any post destination dependencies that would be ignored by
2289 * the block read. See the B-Spec for pre-gen5 send instruction.
2291 * This could use a better solution, since texture sampling and
2292 * math reads could potentially run into it as well -- anywhere
2293 * that we have a SEND with a destination that is a register that
2294 * was written but not read within the last N instructions (what's
2295 * N? unsure). This is rare because of dead code elimination, but
2298 if (intel
->gen
== 4 && !intel
->is_g4x
)
2299 brw_MOV(p
, brw_null_reg(), dst
);
2301 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
), 1,
2304 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2305 /* gen4 errata: destination from a send can't be used as a
2306 * destination until it's been read. Just read it so we don't
2309 brw_MOV(p
, brw_null_reg(), dst
);
2315 fs_visitor::generate_pull_constant_load(fs_inst
*inst
, struct brw_reg dst
)
2317 assert(inst
->mlen
!= 0);
2319 /* Clear any post destination dependencies that would be ignored by
2320 * the block read. See the B-Spec for pre-gen5 send instruction.
2322 * This could use a better solution, since texture sampling and
2323 * math reads could potentially run into it as well -- anywhere
2324 * that we have a SEND with a destination that is a register that
2325 * was written but not read within the last N instructions (what's
2326 * N? unsure). This is rare because of dead code elimination, but
2329 if (intel
->gen
== 4 && !intel
->is_g4x
)
2330 brw_MOV(p
, brw_null_reg(), dst
);
2332 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
2333 inst
->offset
, SURF_INDEX_FRAG_CONST_BUFFER
);
2335 if (intel
->gen
== 4 && !intel
->is_g4x
) {
2336 /* gen4 errata: destination from a send can't be used as a
2337 * destination until it's been read. Just read it so we don't
2340 brw_MOV(p
, brw_null_reg(), dst
);
2345 fs_visitor::assign_curb_setup()
2347 c
->prog_data
.first_curbe_grf
= c
->key
.nr_payload_regs
;
2348 c
->prog_data
.curb_read_length
= ALIGN(c
->prog_data
.nr_params
, 8) / 8;
2350 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2351 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2352 fs_inst
*inst
= (fs_inst
*)iter
.get();
2354 for (unsigned int i
= 0; i
< 3; i
++) {
2355 if (inst
->src
[i
].file
== UNIFORM
) {
2356 int constant_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2357 struct brw_reg brw_reg
= brw_vec1_grf(c
->prog_data
.first_curbe_grf
+
2361 inst
->src
[i
].file
= FIXED_HW_REG
;
2362 inst
->src
[i
].fixed_hw_reg
= brw_reg
;
2369 fs_visitor::calculate_urb_setup()
2371 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2376 /* Figure out where each of the incoming setup attributes lands. */
2377 if (intel
->gen
>= 6) {
2378 for (unsigned int i
= 0; i
< FRAG_ATTRIB_MAX
; i
++) {
2379 if (brw
->fragment_program
->Base
.InputsRead
& BITFIELD64_BIT(i
)) {
2380 urb_setup
[i
] = urb_next
++;
2384 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2385 for (unsigned int i
= 0; i
< VERT_RESULT_MAX
; i
++) {
2386 if (c
->key
.vp_outputs_written
& BITFIELD64_BIT(i
)) {
2389 if (i
>= VERT_RESULT_VAR0
)
2390 fp_index
= i
- (VERT_RESULT_VAR0
- FRAG_ATTRIB_VAR0
);
2391 else if (i
<= VERT_RESULT_TEX7
)
2397 urb_setup
[fp_index
] = urb_next
++;
2402 /* Each attribute is 4 setup channels, each of which is half a reg. */
2403 c
->prog_data
.urb_read_length
= urb_next
* 2;
2407 fs_visitor::assign_urb_setup()
2409 int urb_start
= c
->prog_data
.first_curbe_grf
+ c
->prog_data
.curb_read_length
;
2411 /* Offset all the urb_setup[] index by the actual position of the
2412 * setup regs, now that the location of the constants has been chosen.
2414 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2415 fs_inst
*inst
= (fs_inst
*)iter
.get();
2417 if (inst
->opcode
!= FS_OPCODE_LINTERP
)
2420 assert(inst
->src
[2].file
== FIXED_HW_REG
);
2422 inst
->src
[2].fixed_hw_reg
.nr
+= urb_start
;
2425 this->first_non_payload_grf
= urb_start
+ c
->prog_data
.urb_read_length
;
2429 * Split large virtual GRFs into separate components if we can.
2431 * This is mostly duplicated with what brw_fs_vector_splitting does,
2432 * but that's really conservative because it's afraid of doing
2433 * splitting that doesn't result in real progress after the rest of
2434 * the optimization phases, which would cause infinite looping in
2435 * optimization. We can do it once here, safely. This also has the
2436 * opportunity to split interpolated values, or maybe even uniforms,
2437 * which we don't have at the IR level.
2439 * We want to split, because virtual GRFs are what we register
2440 * allocate and spill (due to contiguousness requirements for some
2441 * instructions), and they're what we naturally generate in the
2442 * codegen process, but most virtual GRFs don't actually need to be
2443 * contiguous sets of GRFs. If we split, we'll end up with reduced
2444 * live intervals and better dead code elimination and coalescing.
2447 fs_visitor::split_virtual_grfs()
2449 int num_vars
= this->virtual_grf_next
;
2450 bool split_grf
[num_vars
];
2451 int new_virtual_grf
[num_vars
];
2453 /* Try to split anything > 0 sized. */
2454 for (int i
= 0; i
< num_vars
; i
++) {
2455 if (this->virtual_grf_sizes
[i
] != 1)
2456 split_grf
[i
] = true;
2458 split_grf
[i
] = false;
2462 /* PLN opcodes rely on the delta_xy being contiguous. */
2463 split_grf
[this->delta_x
.reg
] = false;
2466 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2467 fs_inst
*inst
= (fs_inst
*)iter
.get();
2469 /* Texturing produces 4 contiguous registers, so no splitting. */
2470 if ((inst
->opcode
== FS_OPCODE_TEX
||
2471 inst
->opcode
== FS_OPCODE_TXB
||
2472 inst
->opcode
== FS_OPCODE_TXL
) &&
2473 inst
->dst
.file
== GRF
) {
2474 split_grf
[inst
->dst
.reg
] = false;
2478 /* Allocate new space for split regs. Note that the virtual
2479 * numbers will be contiguous.
2481 for (int i
= 0; i
< num_vars
; i
++) {
2483 new_virtual_grf
[i
] = virtual_grf_alloc(1);
2484 for (int j
= 2; j
< this->virtual_grf_sizes
[i
]; j
++) {
2485 int reg
= virtual_grf_alloc(1);
2486 assert(reg
== new_virtual_grf
[i
] + j
- 1);
2488 this->virtual_grf_sizes
[i
] = 1;
2492 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2493 fs_inst
*inst
= (fs_inst
*)iter
.get();
2495 if (inst
->dst
.file
== GRF
&&
2496 split_grf
[inst
->dst
.reg
] &&
2497 inst
->dst
.reg_offset
!= 0) {
2498 inst
->dst
.reg
= (new_virtual_grf
[inst
->dst
.reg
] +
2499 inst
->dst
.reg_offset
- 1);
2500 inst
->dst
.reg_offset
= 0;
2502 for (int i
= 0; i
< 3; i
++) {
2503 if (inst
->src
[i
].file
== GRF
&&
2504 split_grf
[inst
->src
[i
].reg
] &&
2505 inst
->src
[i
].reg_offset
!= 0) {
2506 inst
->src
[i
].reg
= (new_virtual_grf
[inst
->src
[i
].reg
] +
2507 inst
->src
[i
].reg_offset
- 1);
2508 inst
->src
[i
].reg_offset
= 0;
2515 * Choose accesses from the UNIFORM file to demote to using the pull
2518 * We allow a fragment shader to have more than the specified minimum
2519 * maximum number of fragment shader uniform components (64). If
2520 * there are too many of these, they'd fill up all of register space.
2521 * So, this will push some of them out to the pull constant buffer and
2522 * update the program to load them.
2525 fs_visitor::setup_pull_constants()
2527 /* Only allow 16 registers (128 uniform components) as push constants. */
2528 unsigned int max_uniform_components
= 16 * 8;
2529 if (c
->prog_data
.nr_params
<= max_uniform_components
)
2532 /* Just demote the end of the list. We could probably do better
2533 * here, demoting things that are rarely used in the program first.
2535 int pull_uniform_base
= max_uniform_components
;
2536 int pull_uniform_count
= c
->prog_data
.nr_params
- pull_uniform_base
;
2538 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2539 fs_inst
*inst
= (fs_inst
*)iter
.get();
2541 for (int i
= 0; i
< 3; i
++) {
2542 if (inst
->src
[i
].file
!= UNIFORM
)
2545 int uniform_nr
= inst
->src
[i
].hw_reg
+ inst
->src
[i
].reg_offset
;
2546 if (uniform_nr
< pull_uniform_base
)
2549 fs_reg dst
= fs_reg(this, glsl_type::float_type
);
2550 fs_inst
*pull
= new(mem_ctx
) fs_inst(FS_OPCODE_PULL_CONSTANT_LOAD
,
2552 pull
->offset
= ((uniform_nr
- pull_uniform_base
) * 4) & ~15;
2553 pull
->ir
= inst
->ir
;
2554 pull
->annotation
= inst
->annotation
;
2555 pull
->base_mrf
= 14;
2558 inst
->insert_before(pull
);
2560 inst
->src
[i
].file
= GRF
;
2561 inst
->src
[i
].reg
= dst
.reg
;
2562 inst
->src
[i
].reg_offset
= 0;
2563 inst
->src
[i
].smear
= (uniform_nr
- pull_uniform_base
) & 3;
2567 for (int i
= 0; i
< pull_uniform_count
; i
++) {
2568 c
->prog_data
.pull_param
[i
] = c
->prog_data
.param
[pull_uniform_base
+ i
];
2570 c
->prog_data
.nr_params
-= pull_uniform_count
;
2571 c
->prog_data
.nr_pull_params
= pull_uniform_count
;
2575 fs_visitor::calculate_live_intervals()
2577 int num_vars
= this->virtual_grf_next
;
2578 int *def
= talloc_array(mem_ctx
, int, num_vars
);
2579 int *use
= talloc_array(mem_ctx
, int, num_vars
);
2582 int bb_header_ip
= 0;
2584 for (int i
= 0; i
< num_vars
; i
++) {
2590 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2591 fs_inst
*inst
= (fs_inst
*)iter
.get();
2593 if (inst
->opcode
== BRW_OPCODE_DO
) {
2594 if (loop_depth
++ == 0)
2596 } else if (inst
->opcode
== BRW_OPCODE_WHILE
) {
2599 if (loop_depth
== 0) {
2600 /* Patches up the use of vars marked for being live across
2603 for (int i
= 0; i
< num_vars
; i
++) {
2604 if (use
[i
] == loop_start
) {
2610 for (unsigned int i
= 0; i
< 3; i
++) {
2611 if (inst
->src
[i
].file
== GRF
&& inst
->src
[i
].reg
!= 0) {
2612 int reg
= inst
->src
[i
].reg
;
2614 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2615 def
[reg
] >= bb_header_ip
)) {
2618 def
[reg
] = MIN2(loop_start
, def
[reg
]);
2619 use
[reg
] = loop_start
;
2621 /* Nobody else is going to go smash our start to
2622 * later in the loop now, because def[reg] now
2623 * points before the bb header.
2628 if (inst
->dst
.file
== GRF
&& inst
->dst
.reg
!= 0) {
2629 int reg
= inst
->dst
.reg
;
2631 if (!loop_depth
|| (this->virtual_grf_sizes
[reg
] == 1 &&
2632 !inst
->predicated
)) {
2633 def
[reg
] = MIN2(def
[reg
], ip
);
2635 def
[reg
] = MIN2(def
[reg
], loop_start
);
2642 /* Set the basic block header IP. This is used for determining
2643 * if a complete def of single-register virtual GRF in a loop
2644 * dominates a use in the same basic block. It's a quick way to
2645 * reduce the live interval range of most register used in a
2648 if (inst
->opcode
== BRW_OPCODE_IF
||
2649 inst
->opcode
== BRW_OPCODE_ELSE
||
2650 inst
->opcode
== BRW_OPCODE_ENDIF
||
2651 inst
->opcode
== BRW_OPCODE_DO
||
2652 inst
->opcode
== BRW_OPCODE_WHILE
||
2653 inst
->opcode
== BRW_OPCODE_BREAK
||
2654 inst
->opcode
== BRW_OPCODE_CONTINUE
) {
2659 talloc_free(this->virtual_grf_def
);
2660 talloc_free(this->virtual_grf_use
);
2661 this->virtual_grf_def
= def
;
2662 this->virtual_grf_use
= use
;
2666 * Attempts to move immediate constants into the immediate
2667 * constant slot of following instructions.
2669 * Immediate constants are a bit tricky -- they have to be in the last
2670 * operand slot, you can't do abs/negate on them,
2674 fs_visitor::propagate_constants()
2676 bool progress
= false;
2678 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2679 fs_inst
*inst
= (fs_inst
*)iter
.get();
2681 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2683 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= IMM
||
2684 inst
->dst
.type
!= inst
->src
[0].type
)
2687 /* Don't bother with cases where we should have had the
2688 * operation on the constant folded in GLSL already.
2693 /* Found a move of a constant to a GRF. Find anything else using the GRF
2694 * before it's written, and replace it with the constant if we can.
2696 exec_list_iterator scan_iter
= iter
;
2698 for (; scan_iter
.has_next(); scan_iter
.next()) {
2699 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2701 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2702 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2703 scan_inst
->opcode
== BRW_OPCODE_ELSE
||
2704 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2708 for (int i
= 2; i
>= 0; i
--) {
2709 if (scan_inst
->src
[i
].file
!= GRF
||
2710 scan_inst
->src
[i
].reg
!= inst
->dst
.reg
||
2711 scan_inst
->src
[i
].reg_offset
!= inst
->dst
.reg_offset
)
2714 /* Don't bother with cases where we should have had the
2715 * operation on the constant folded in GLSL already.
2717 if (scan_inst
->src
[i
].negate
|| scan_inst
->src
[i
].abs
)
2720 switch (scan_inst
->opcode
) {
2721 case BRW_OPCODE_MOV
:
2722 scan_inst
->src
[i
] = inst
->src
[0];
2726 case BRW_OPCODE_MUL
:
2727 case BRW_OPCODE_ADD
:
2729 scan_inst
->src
[i
] = inst
->src
[0];
2731 } else if (i
== 0 && scan_inst
->src
[1].file
!= IMM
) {
2732 /* Fit this constant in by commuting the operands */
2733 scan_inst
->src
[0] = scan_inst
->src
[1];
2734 scan_inst
->src
[1] = inst
->src
[0];
2737 case BRW_OPCODE_CMP
:
2739 scan_inst
->src
[i
] = inst
->src
[0];
2745 if (scan_inst
->dst
.file
== GRF
&&
2746 scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2747 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2748 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2757 * Must be called after calculate_live_intervales() to remove unused
2758 * writes to registers -- register allocation will fail otherwise
2759 * because something deffed but not used won't be considered to
2760 * interfere with other regs.
2763 fs_visitor::dead_code_eliminate()
2765 bool progress
= false;
2766 int num_vars
= this->virtual_grf_next
;
2767 bool dead
[num_vars
];
2769 for (int i
= 0; i
< num_vars
; i
++) {
2770 dead
[i
] = this->virtual_grf_def
[i
] >= this->virtual_grf_use
[i
];
2773 /* Mark off its interval so it won't interfere with anything. */
2774 this->virtual_grf_def
[i
] = -1;
2775 this->virtual_grf_use
[i
] = -1;
2779 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2780 fs_inst
*inst
= (fs_inst
*)iter
.get();
2782 if (inst
->dst
.file
== GRF
&& dead
[inst
->dst
.reg
]) {
2792 fs_visitor::register_coalesce()
2794 bool progress
= false;
2796 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2797 fs_inst
*inst
= (fs_inst
*)iter
.get();
2799 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2802 inst
->dst
.file
!= GRF
|| inst
->src
[0].file
!= GRF
||
2803 inst
->dst
.type
!= inst
->src
[0].type
)
2806 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2807 * them: check for no writes to either one until the exit of the
2810 bool interfered
= false;
2811 exec_list_iterator scan_iter
= iter
;
2813 for (; scan_iter
.has_next(); scan_iter
.next()) {
2814 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2816 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2817 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2818 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2824 if (scan_inst
->dst
.file
== GRF
) {
2825 if (scan_inst
->dst
.reg
== inst
->dst
.reg
&&
2826 (scan_inst
->dst
.reg_offset
== inst
->dst
.reg_offset
||
2827 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2831 if (scan_inst
->dst
.reg
== inst
->src
[0].reg
&&
2832 (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
||
2833 scan_inst
->opcode
== FS_OPCODE_TEX
)) {
2843 /* Update live interval so we don't have to recalculate. */
2844 this->virtual_grf_use
[inst
->src
[0].reg
] = MAX2(virtual_grf_use
[inst
->src
[0].reg
],
2845 virtual_grf_use
[inst
->dst
.reg
]);
2847 /* Rewrite the later usage to point at the source of the move to
2850 for (exec_list_iterator scan_iter
= iter
; scan_iter
.has_next();
2852 fs_inst
*scan_inst
= (fs_inst
*)scan_iter
.get();
2854 for (int i
= 0; i
< 3; i
++) {
2855 if (scan_inst
->src
[i
].file
== GRF
&&
2856 scan_inst
->src
[i
].reg
== inst
->dst
.reg
&&
2857 scan_inst
->src
[i
].reg_offset
== inst
->dst
.reg_offset
) {
2858 scan_inst
->src
[i
].reg
= inst
->src
[0].reg
;
2859 scan_inst
->src
[i
].reg_offset
= inst
->src
[0].reg_offset
;
2860 scan_inst
->src
[i
].abs
|= inst
->src
[0].abs
;
2861 scan_inst
->src
[i
].negate
^= inst
->src
[0].negate
;
2862 scan_inst
->src
[i
].smear
= inst
->src
[0].smear
;
2876 fs_visitor::compute_to_mrf()
2878 bool progress
= false;
2881 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
2882 fs_inst
*inst
= (fs_inst
*)iter
.get();
2887 if (inst
->opcode
!= BRW_OPCODE_MOV
||
2889 inst
->dst
.file
!= MRF
|| inst
->src
[0].file
!= GRF
||
2890 inst
->dst
.type
!= inst
->src
[0].type
||
2891 inst
->src
[0].abs
|| inst
->src
[0].negate
|| inst
->src
[0].smear
!= -1)
2894 /* Can't compute-to-MRF this GRF if someone else was going to
2897 if (this->virtual_grf_use
[inst
->src
[0].reg
] > ip
)
2900 /* Found a move of a GRF to a MRF. Let's see if we can go
2901 * rewrite the thing that made this GRF to write into the MRF.
2905 for (scan_inst
= (fs_inst
*)inst
->prev
;
2906 scan_inst
->prev
!= NULL
;
2907 scan_inst
= (fs_inst
*)scan_inst
->prev
) {
2908 /* We don't handle flow control here. Most computation of
2909 * values that end up in MRFs are shortly before the MRF
2912 if (scan_inst
->opcode
== BRW_OPCODE_DO
||
2913 scan_inst
->opcode
== BRW_OPCODE_WHILE
||
2914 scan_inst
->opcode
== BRW_OPCODE_ENDIF
) {
2918 /* You can't read from an MRF, so if someone else reads our
2919 * MRF's source GRF that we wanted to rewrite, that stops us.
2921 bool interfered
= false;
2922 for (int i
= 0; i
< 3; i
++) {
2923 if (scan_inst
->src
[i
].file
== GRF
&&
2924 scan_inst
->src
[i
].reg
== inst
->src
[0].reg
&&
2925 scan_inst
->src
[i
].reg_offset
== inst
->src
[0].reg_offset
) {
2932 if (scan_inst
->dst
.file
== MRF
&&
2933 scan_inst
->dst
.hw_reg
== inst
->dst
.hw_reg
) {
2934 /* Somebody else wrote our MRF here, so we can't can't
2935 * compute-to-MRF before that.
2940 if (scan_inst
->mlen
> 0) {
2941 /* Found a SEND instruction, which will do some amount of
2942 * implied write that may overwrite our MRF that we were
2943 * hoping to compute-to-MRF somewhere above it. Nothing
2944 * we have implied-writes more than 2 MRFs from base_mrf,
2947 int implied_write_len
= MIN2(scan_inst
->mlen
, 2);
2948 if (inst
->dst
.hw_reg
>= scan_inst
->base_mrf
&&
2949 inst
->dst
.hw_reg
< scan_inst
->base_mrf
+ implied_write_len
) {
2954 if (scan_inst
->dst
.file
== GRF
&&
2955 scan_inst
->dst
.reg
== inst
->src
[0].reg
) {
2956 /* Found the last thing to write our reg we want to turn
2957 * into a compute-to-MRF.
2960 if (scan_inst
->opcode
== FS_OPCODE_TEX
) {
2961 /* texturing writes several continuous regs, so we can't
2962 * compute-to-mrf that.
2967 /* If it's predicated, it (probably) didn't populate all
2970 if (scan_inst
->predicated
)
2973 /* SEND instructions can't have MRF as a destination. */
2974 if (scan_inst
->mlen
)
2977 if (intel
->gen
>= 6) {
2978 /* gen6 math instructions must have the destination be
2979 * GRF, so no compute-to-MRF for them.
2981 if (scan_inst
->opcode
== FS_OPCODE_RCP
||
2982 scan_inst
->opcode
== FS_OPCODE_RSQ
||
2983 scan_inst
->opcode
== FS_OPCODE_SQRT
||
2984 scan_inst
->opcode
== FS_OPCODE_EXP2
||
2985 scan_inst
->opcode
== FS_OPCODE_LOG2
||
2986 scan_inst
->opcode
== FS_OPCODE_SIN
||
2987 scan_inst
->opcode
== FS_OPCODE_COS
||
2988 scan_inst
->opcode
== FS_OPCODE_POW
) {
2993 if (scan_inst
->dst
.reg_offset
== inst
->src
[0].reg_offset
) {
2994 /* Found the creator of our MRF's source value. */
3001 scan_inst
->dst
.file
= MRF
;
3002 scan_inst
->dst
.hw_reg
= inst
->dst
.hw_reg
;
3003 scan_inst
->saturate
|= inst
->saturate
;
3013 fs_visitor::virtual_grf_interferes(int a
, int b
)
3015 int start
= MAX2(this->virtual_grf_def
[a
], this->virtual_grf_def
[b
]);
3016 int end
= MIN2(this->virtual_grf_use
[a
], this->virtual_grf_use
[b
]);
3018 /* For dead code, just check if the def interferes with the other range. */
3019 if (this->virtual_grf_use
[a
] == -1) {
3020 return (this->virtual_grf_def
[a
] >= this->virtual_grf_def
[b
] &&
3021 this->virtual_grf_def
[a
] < this->virtual_grf_use
[b
]);
3023 if (this->virtual_grf_use
[b
] == -1) {
3024 return (this->virtual_grf_def
[b
] >= this->virtual_grf_def
[a
] &&
3025 this->virtual_grf_def
[b
] < this->virtual_grf_use
[a
]);
3031 static struct brw_reg
brw_reg_from_fs_reg(fs_reg
*reg
)
3033 struct brw_reg brw_reg
;
3035 switch (reg
->file
) {
3039 if (reg
->smear
== -1) {
3040 brw_reg
= brw_vec8_reg(reg
->file
,
3043 brw_reg
= brw_vec1_reg(reg
->file
,
3044 reg
->hw_reg
, reg
->smear
);
3046 brw_reg
= retype(brw_reg
, reg
->type
);
3049 switch (reg
->type
) {
3050 case BRW_REGISTER_TYPE_F
:
3051 brw_reg
= brw_imm_f(reg
->imm
.f
);
3053 case BRW_REGISTER_TYPE_D
:
3054 brw_reg
= brw_imm_d(reg
->imm
.i
);
3056 case BRW_REGISTER_TYPE_UD
:
3057 brw_reg
= brw_imm_ud(reg
->imm
.u
);
3060 assert(!"not reached");
3065 brw_reg
= reg
->fixed_hw_reg
;
3068 /* Probably unused. */
3069 brw_reg
= brw_null_reg();
3072 assert(!"not reached");
3073 brw_reg
= brw_null_reg();
3077 brw_reg
= brw_abs(brw_reg
);
3079 brw_reg
= negate(brw_reg
);
3085 fs_visitor::generate_code()
3087 int last_native_inst
= 0;
3088 struct brw_instruction
*if_stack
[16], *loop_stack
[16];
3089 int if_stack_depth
= 0, loop_stack_depth
= 0;
3090 int if_depth_in_loop
[16];
3091 const char *last_annotation_string
= NULL
;
3092 ir_instruction
*last_annotation_ir
= NULL
;
3094 if (INTEL_DEBUG
& DEBUG_WM
) {
3095 printf("Native code for fragment shader %d:\n",
3096 ctx
->Shader
.CurrentProgram
->Name
);
3099 if_depth_in_loop
[loop_stack_depth
] = 0;
3101 memset(&if_stack
, 0, sizeof(if_stack
));
3102 foreach_iter(exec_list_iterator
, iter
, this->instructions
) {
3103 fs_inst
*inst
= (fs_inst
*)iter
.get();
3104 struct brw_reg src
[3], dst
;
3106 if (INTEL_DEBUG
& DEBUG_WM
) {
3107 if (last_annotation_ir
!= inst
->ir
) {
3108 last_annotation_ir
= inst
->ir
;
3109 if (last_annotation_ir
) {
3111 last_annotation_ir
->print();
3115 if (last_annotation_string
!= inst
->annotation
) {
3116 last_annotation_string
= inst
->annotation
;
3117 if (last_annotation_string
)
3118 printf(" %s\n", last_annotation_string
);
3122 for (unsigned int i
= 0; i
< 3; i
++) {
3123 src
[i
] = brw_reg_from_fs_reg(&inst
->src
[i
]);
3125 dst
= brw_reg_from_fs_reg(&inst
->dst
);
3127 brw_set_conditionalmod(p
, inst
->conditional_mod
);
3128 brw_set_predicate_control(p
, inst
->predicated
);
3130 switch (inst
->opcode
) {
3131 case BRW_OPCODE_MOV
:
3132 brw_MOV(p
, dst
, src
[0]);
3134 case BRW_OPCODE_ADD
:
3135 brw_ADD(p
, dst
, src
[0], src
[1]);
3137 case BRW_OPCODE_MUL
:
3138 brw_MUL(p
, dst
, src
[0], src
[1]);
3141 case BRW_OPCODE_FRC
:
3142 brw_FRC(p
, dst
, src
[0]);
3144 case BRW_OPCODE_RNDD
:
3145 brw_RNDD(p
, dst
, src
[0]);
3147 case BRW_OPCODE_RNDE
:
3148 brw_RNDE(p
, dst
, src
[0]);
3150 case BRW_OPCODE_RNDZ
:
3151 brw_RNDZ(p
, dst
, src
[0]);
3154 case BRW_OPCODE_AND
:
3155 brw_AND(p
, dst
, src
[0], src
[1]);
3158 brw_OR(p
, dst
, src
[0], src
[1]);
3160 case BRW_OPCODE_XOR
:
3161 brw_XOR(p
, dst
, src
[0], src
[1]);
3163 case BRW_OPCODE_NOT
:
3164 brw_NOT(p
, dst
, src
[0]);
3166 case BRW_OPCODE_ASR
:
3167 brw_ASR(p
, dst
, src
[0], src
[1]);
3169 case BRW_OPCODE_SHR
:
3170 brw_SHR(p
, dst
, src
[0], src
[1]);
3172 case BRW_OPCODE_SHL
:
3173 brw_SHL(p
, dst
, src
[0], src
[1]);
3176 case BRW_OPCODE_CMP
:
3177 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
3179 case BRW_OPCODE_SEL
:
3180 brw_SEL(p
, dst
, src
[0], src
[1]);
3184 assert(if_stack_depth
< 16);
3185 if (inst
->src
[0].file
!= BAD_FILE
) {
3186 assert(intel
->gen
>= 6);
3187 if_stack
[if_stack_depth
] = brw_IF_gen6(p
, inst
->conditional_mod
, src
[0], src
[1]);
3189 if_stack
[if_stack_depth
] = brw_IF(p
, BRW_EXECUTE_8
);
3191 if_depth_in_loop
[loop_stack_depth
]++;
3195 case BRW_OPCODE_ELSE
:
3196 if_stack
[if_stack_depth
- 1] =
3197 brw_ELSE(p
, if_stack
[if_stack_depth
- 1]);
3199 case BRW_OPCODE_ENDIF
:
3201 brw_ENDIF(p
, if_stack
[if_stack_depth
]);
3202 if_depth_in_loop
[loop_stack_depth
]--;
3206 loop_stack
[loop_stack_depth
++] = brw_DO(p
, BRW_EXECUTE_8
);
3207 if_depth_in_loop
[loop_stack_depth
] = 0;
3210 case BRW_OPCODE_BREAK
:
3211 brw_BREAK(p
, if_depth_in_loop
[loop_stack_depth
]);
3212 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3214 case BRW_OPCODE_CONTINUE
:
3215 brw_CONT(p
, if_depth_in_loop
[loop_stack_depth
]);
3216 brw_set_predicate_control(p
, BRW_PREDICATE_NONE
);
3219 case BRW_OPCODE_WHILE
: {
3220 struct brw_instruction
*inst0
, *inst1
;
3223 if (intel
->gen
>= 5)
3226 assert(loop_stack_depth
> 0);
3228 inst0
= inst1
= brw_WHILE(p
, loop_stack
[loop_stack_depth
]);
3229 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3230 while (inst0
> loop_stack
[loop_stack_depth
]) {
3232 if (inst0
->header
.opcode
== BRW_OPCODE_BREAK
&&
3233 inst0
->bits3
.if_else
.jump_count
== 0) {
3234 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
+ 1);
3236 else if (inst0
->header
.opcode
== BRW_OPCODE_CONTINUE
&&
3237 inst0
->bits3
.if_else
.jump_count
== 0) {
3238 inst0
->bits3
.if_else
.jump_count
= br
* (inst1
- inst0
);
3246 case FS_OPCODE_SQRT
:
3247 case FS_OPCODE_EXP2
:
3248 case FS_OPCODE_LOG2
:
3252 generate_math(inst
, dst
, src
);
3254 case FS_OPCODE_LINTERP
:
3255 generate_linterp(inst
, dst
, src
);
3260 generate_tex(inst
, dst
);
3262 case FS_OPCODE_DISCARD_NOT
:
3263 generate_discard_not(inst
, dst
);
3265 case FS_OPCODE_DISCARD_AND
:
3266 generate_discard_and(inst
, src
[0]);
3269 generate_ddx(inst
, dst
, src
[0]);
3272 generate_ddy(inst
, dst
, src
[0]);
3275 case FS_OPCODE_SPILL
:
3276 generate_spill(inst
, src
[0]);
3279 case FS_OPCODE_UNSPILL
:
3280 generate_unspill(inst
, dst
);
3283 case FS_OPCODE_PULL_CONSTANT_LOAD
:
3284 generate_pull_constant_load(inst
, dst
);
3287 case FS_OPCODE_FB_WRITE
:
3288 generate_fb_write(inst
);
3291 if (inst
->opcode
< (int)ARRAY_SIZE(brw_opcodes
)) {
3292 _mesa_problem(ctx
, "Unsupported opcode `%s' in FS",
3293 brw_opcodes
[inst
->opcode
].name
);
3295 _mesa_problem(ctx
, "Unsupported opcode %d in FS", inst
->opcode
);
3300 if (INTEL_DEBUG
& DEBUG_WM
) {
3301 for (unsigned int i
= last_native_inst
; i
< p
->nr_insn
; i
++) {
3303 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3304 ((uint32_t *)&p
->store
[i
])[3],
3305 ((uint32_t *)&p
->store
[i
])[2],
3306 ((uint32_t *)&p
->store
[i
])[1],
3307 ((uint32_t *)&p
->store
[i
])[0]);
3309 brw_disasm(stdout
, &p
->store
[i
], intel
->gen
);
3314 last_native_inst
= p
->nr_insn
;
3319 brw_wm_fs_emit(struct brw_context
*brw
, struct brw_wm_compile
*c
)
3321 struct intel_context
*intel
= &brw
->intel
;
3322 struct gl_context
*ctx
= &intel
->ctx
;
3323 struct gl_shader_program
*prog
= ctx
->Shader
.CurrentProgram
;
3328 struct brw_shader
*shader
=
3329 (brw_shader
*) prog
->_LinkedShaders
[MESA_SHADER_FRAGMENT
];
3333 /* We always use 8-wide mode, at least for now. For one, flow
3334 * control only works in 8-wide. Also, when we're fragment shader
3335 * bound, we're almost always under register pressure as well, so
3336 * 8-wide would save us from the performance cliff of spilling
3339 c
->dispatch_width
= 8;
3341 if (INTEL_DEBUG
& DEBUG_WM
) {
3342 printf("GLSL IR for native fragment shader %d:\n", prog
->Name
);
3343 _mesa_print_ir(shader
->ir
, NULL
);
3347 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3349 fs_visitor
v(c
, shader
);
3354 v
.calculate_urb_setup();
3356 v
.emit_interpolation_setup_gen4();
3358 v
.emit_interpolation_setup_gen6();
3360 /* Generate FS IR for main(). (the visitor only descends into
3361 * functions called "main").
3363 foreach_iter(exec_list_iterator
, iter
, *shader
->ir
) {
3364 ir_instruction
*ir
= (ir_instruction
*)iter
.get();
3371 v
.split_virtual_grfs();
3372 v
.setup_pull_constants();
3374 v
.assign_curb_setup();
3375 v
.assign_urb_setup();
3380 v
.calculate_live_intervals();
3381 progress
= v
.propagate_constants() || progress
;
3382 progress
= v
.register_coalesce() || progress
;
3383 progress
= v
.compute_to_mrf() || progress
;
3384 progress
= v
.dead_code_eliminate() || progress
;
3388 /* Debug of register spilling: Go spill everything. */
3389 int virtual_grf_count
= v
.virtual_grf_next
;
3390 for (int i
= 1; i
< virtual_grf_count
; i
++) {
3393 v
.calculate_live_intervals();
3397 v
.assign_regs_trivial();
3399 while (!v
.assign_regs()) {
3403 v
.calculate_live_intervals();
3411 assert(!v
.fail
); /* FINISHME: Cleanly fail, tested at link time, etc. */
3416 c
->prog_data
.total_grf
= v
.grf_used
;