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i965: Use the new style of IF statement with embedded comparison on gen6.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28 extern "C" {
29
30 #include <sys/types.h>
31
32 #include "main/macros.h"
33 #include "main/shaderobj.h"
34 #include "main/uniforms.h"
35 #include "program/prog_parameter.h"
36 #include "program/prog_print.h"
37 #include "program/prog_optimize.h"
38 #include "program/register_allocate.h"
39 #include "program/sampler.h"
40 #include "program/hash_table.h"
41 #include "brw_context.h"
42 #include "brw_eu.h"
43 #include "brw_wm.h"
44 #include "talloc.h"
45 }
46 #include "brw_fs.h"
47 #include "../glsl/glsl_types.h"
48 #include "../glsl/ir_optimization.h"
49 #include "../glsl/ir_print_visitor.h"
50
51 static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
52
53 struct gl_shader *
54 brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
55 {
56 struct brw_shader *shader;
57
58 shader = talloc_zero(NULL, struct brw_shader);
59 if (shader) {
60 shader->base.Type = type;
61 shader->base.Name = name;
62 _mesa_init_shader(ctx, &shader->base);
63 }
64
65 return &shader->base;
66 }
67
68 struct gl_shader_program *
69 brw_new_shader_program(struct gl_context *ctx, GLuint name)
70 {
71 struct brw_shader_program *prog;
72 prog = talloc_zero(NULL, struct brw_shader_program);
73 if (prog) {
74 prog->base.Name = name;
75 _mesa_init_shader_program(ctx, &prog->base);
76 }
77 return &prog->base;
78 }
79
80 GLboolean
81 brw_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
82 {
83 if (!_mesa_ir_compile_shader(ctx, shader))
84 return GL_FALSE;
85
86 return GL_TRUE;
87 }
88
89 GLboolean
90 brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
91 {
92 struct intel_context *intel = intel_context(ctx);
93
94 struct brw_shader *shader =
95 (struct brw_shader *)prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
96 if (shader != NULL) {
97 void *mem_ctx = talloc_new(NULL);
98 bool progress;
99
100 if (shader->ir)
101 talloc_free(shader->ir);
102 shader->ir = new(shader) exec_list;
103 clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
104
105 do_mat_op_to_vec(shader->ir);
106 do_mod_to_fract(shader->ir);
107 do_div_to_mul_rcp(shader->ir);
108 do_sub_to_add_neg(shader->ir);
109 do_explog_to_explog2(shader->ir);
110 do_lower_texture_projection(shader->ir);
111 brw_do_cubemap_normalize(shader->ir);
112
113 do {
114 progress = false;
115
116 brw_do_channel_expressions(shader->ir);
117 brw_do_vector_splitting(shader->ir);
118
119 progress = do_lower_jumps(shader->ir, true, true,
120 true, /* main return */
121 false, /* continue */
122 false /* loops */
123 ) || progress;
124
125 progress = do_common_optimization(shader->ir, true, 32) || progress;
126
127 progress = lower_noise(shader->ir) || progress;
128 progress =
129 lower_variable_index_to_cond_assign(shader->ir,
130 GL_TRUE, /* input */
131 GL_TRUE, /* output */
132 GL_TRUE, /* temp */
133 GL_TRUE /* uniform */
134 ) || progress;
135 if (intel->gen == 6) {
136 progress = do_if_to_cond_assign(shader->ir) || progress;
137 }
138 } while (progress);
139
140 validate_ir_tree(shader->ir);
141
142 reparent_ir(shader->ir, shader->ir);
143 talloc_free(mem_ctx);
144 }
145
146 if (!_mesa_ir_link_shader(ctx, prog))
147 return GL_FALSE;
148
149 return GL_TRUE;
150 }
151
152 static int
153 type_size(const struct glsl_type *type)
154 {
155 unsigned int size, i;
156
157 switch (type->base_type) {
158 case GLSL_TYPE_UINT:
159 case GLSL_TYPE_INT:
160 case GLSL_TYPE_FLOAT:
161 case GLSL_TYPE_BOOL:
162 return type->components();
163 case GLSL_TYPE_ARRAY:
164 return type_size(type->fields.array) * type->length;
165 case GLSL_TYPE_STRUCT:
166 size = 0;
167 for (i = 0; i < type->length; i++) {
168 size += type_size(type->fields.structure[i].type);
169 }
170 return size;
171 case GLSL_TYPE_SAMPLER:
172 /* Samplers take up no register space, since they're baked in at
173 * link time.
174 */
175 return 0;
176 default:
177 assert(!"not reached");
178 return 0;
179 }
180 }
181
182 static const fs_reg reg_undef;
183 static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
184 static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
185
186 int
187 fs_visitor::virtual_grf_alloc(int size)
188 {
189 if (virtual_grf_array_size <= virtual_grf_next) {
190 if (virtual_grf_array_size == 0)
191 virtual_grf_array_size = 16;
192 else
193 virtual_grf_array_size *= 2;
194 virtual_grf_sizes = talloc_realloc(mem_ctx, virtual_grf_sizes,
195 int, virtual_grf_array_size);
196
197 /* This slot is always unused. */
198 virtual_grf_sizes[0] = 0;
199 }
200 virtual_grf_sizes[virtual_grf_next] = size;
201 return virtual_grf_next++;
202 }
203
204 /** Fixed HW reg constructor. */
205 fs_reg::fs_reg(enum register_file file, int hw_reg)
206 {
207 init();
208 this->file = file;
209 this->hw_reg = hw_reg;
210 this->type = BRW_REGISTER_TYPE_F;
211 }
212
213 /** Fixed HW reg constructor. */
214 fs_reg::fs_reg(enum register_file file, int hw_reg, uint32_t type)
215 {
216 init();
217 this->file = file;
218 this->hw_reg = hw_reg;
219 this->type = type;
220 }
221
222 int
223 brw_type_for_base_type(const struct glsl_type *type)
224 {
225 switch (type->base_type) {
226 case GLSL_TYPE_FLOAT:
227 return BRW_REGISTER_TYPE_F;
228 case GLSL_TYPE_INT:
229 case GLSL_TYPE_BOOL:
230 return BRW_REGISTER_TYPE_D;
231 case GLSL_TYPE_UINT:
232 return BRW_REGISTER_TYPE_UD;
233 case GLSL_TYPE_ARRAY:
234 case GLSL_TYPE_STRUCT:
235 /* These should be overridden with the type of the member when
236 * dereferenced into. BRW_REGISTER_TYPE_UD seems like a likely
237 * way to trip up if we don't.
238 */
239 return BRW_REGISTER_TYPE_UD;
240 default:
241 assert(!"not reached");
242 return BRW_REGISTER_TYPE_F;
243 }
244 }
245
246 /** Automatic reg constructor. */
247 fs_reg::fs_reg(class fs_visitor *v, const struct glsl_type *type)
248 {
249 init();
250
251 this->file = GRF;
252 this->reg = v->virtual_grf_alloc(type_size(type));
253 this->reg_offset = 0;
254 this->type = brw_type_for_base_type(type);
255 }
256
257 fs_reg *
258 fs_visitor::variable_storage(ir_variable *var)
259 {
260 return (fs_reg *)hash_table_find(this->variable_ht, var);
261 }
262
263 /* Our support for uniforms is piggy-backed on the struct
264 * gl_fragment_program, because that's where the values actually
265 * get stored, rather than in some global gl_shader_program uniform
266 * store.
267 */
268 int
269 fs_visitor::setup_uniform_values(int loc, const glsl_type *type)
270 {
271 unsigned int offset = 0;
272 float *vec_values;
273
274 if (type->is_matrix()) {
275 const glsl_type *column = glsl_type::get_instance(GLSL_TYPE_FLOAT,
276 type->vector_elements,
277 1);
278
279 for (unsigned int i = 0; i < type->matrix_columns; i++) {
280 offset += setup_uniform_values(loc + offset, column);
281 }
282
283 return offset;
284 }
285
286 switch (type->base_type) {
287 case GLSL_TYPE_FLOAT:
288 case GLSL_TYPE_UINT:
289 case GLSL_TYPE_INT:
290 case GLSL_TYPE_BOOL:
291 vec_values = fp->Base.Parameters->ParameterValues[loc];
292 for (unsigned int i = 0; i < type->vector_elements; i++) {
293 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[i];
294 }
295 return 1;
296
297 case GLSL_TYPE_STRUCT:
298 for (unsigned int i = 0; i < type->length; i++) {
299 offset += setup_uniform_values(loc + offset,
300 type->fields.structure[i].type);
301 }
302 return offset;
303
304 case GLSL_TYPE_ARRAY:
305 for (unsigned int i = 0; i < type->length; i++) {
306 offset += setup_uniform_values(loc + offset, type->fields.array);
307 }
308 return offset;
309
310 case GLSL_TYPE_SAMPLER:
311 /* The sampler takes up a slot, but we don't use any values from it. */
312 return 1;
313
314 default:
315 assert(!"not reached");
316 return 0;
317 }
318 }
319
320
321 /* Our support for builtin uniforms is even scarier than non-builtin.
322 * It sits on top of the PROG_STATE_VAR parameters that are
323 * automatically updated from GL context state.
324 */
325 void
326 fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
327 {
328 const struct gl_builtin_uniform_desc *statevar = NULL;
329
330 for (unsigned int i = 0; _mesa_builtin_uniform_desc[i].name; i++) {
331 statevar = &_mesa_builtin_uniform_desc[i];
332 if (strcmp(ir->name, _mesa_builtin_uniform_desc[i].name) == 0)
333 break;
334 }
335
336 if (!statevar->name) {
337 this->fail = true;
338 printf("Failed to find builtin uniform `%s'\n", ir->name);
339 return;
340 }
341
342 int array_count;
343 if (ir->type->is_array()) {
344 array_count = ir->type->length;
345 } else {
346 array_count = 1;
347 }
348
349 for (int a = 0; a < array_count; a++) {
350 for (unsigned int i = 0; i < statevar->num_elements; i++) {
351 struct gl_builtin_uniform_element *element = &statevar->elements[i];
352 int tokens[STATE_LENGTH];
353
354 memcpy(tokens, element->tokens, sizeof(element->tokens));
355 if (ir->type->is_array()) {
356 tokens[1] = a;
357 }
358
359 /* This state reference has already been setup by ir_to_mesa,
360 * but we'll get the same index back here.
361 */
362 int index = _mesa_add_state_reference(this->fp->Base.Parameters,
363 (gl_state_index *)tokens);
364 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
365
366 /* Add each of the unique swizzles of the element as a
367 * parameter. This'll end up matching the expected layout of
368 * the array/matrix/structure we're trying to fill in.
369 */
370 int last_swiz = -1;
371 for (unsigned int i = 0; i < 4; i++) {
372 int swiz = GET_SWZ(element->swizzle, i);
373 if (swiz == last_swiz)
374 break;
375 last_swiz = swiz;
376
377 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[swiz];
378 }
379 }
380 }
381 }
382
383 fs_reg *
384 fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
385 {
386 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
387 fs_reg wpos = *reg;
388 fs_reg neg_y = this->pixel_y;
389 neg_y.negate = true;
390
391 /* gl_FragCoord.x */
392 if (ir->pixel_center_integer) {
393 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_x));
394 } else {
395 emit(fs_inst(BRW_OPCODE_ADD, wpos, this->pixel_x, fs_reg(0.5f)));
396 }
397 wpos.reg_offset++;
398
399 /* gl_FragCoord.y */
400 if (ir->origin_upper_left && ir->pixel_center_integer) {
401 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->pixel_y));
402 } else {
403 fs_reg pixel_y = this->pixel_y;
404 float offset = (ir->pixel_center_integer ? 0.0 : 0.5);
405
406 if (!ir->origin_upper_left) {
407 pixel_y.negate = true;
408 offset += c->key.drawable_height - 1.0;
409 }
410
411 emit(fs_inst(BRW_OPCODE_ADD, wpos, pixel_y, fs_reg(offset)));
412 }
413 wpos.reg_offset++;
414
415 /* gl_FragCoord.z */
416 emit(fs_inst(FS_OPCODE_LINTERP, wpos, this->delta_x, this->delta_y,
417 interp_reg(FRAG_ATTRIB_WPOS, 2)));
418 wpos.reg_offset++;
419
420 /* gl_FragCoord.w: Already set up in emit_interpolation */
421 emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
422
423 return reg;
424 }
425
426 fs_reg *
427 fs_visitor::emit_general_interpolation(ir_variable *ir)
428 {
429 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
430 /* Interpolation is always in floating point regs. */
431 reg->type = BRW_REGISTER_TYPE_F;
432 fs_reg attr = *reg;
433
434 unsigned int array_elements;
435 const glsl_type *type;
436
437 if (ir->type->is_array()) {
438 array_elements = ir->type->length;
439 if (array_elements == 0) {
440 this->fail = true;
441 }
442 type = ir->type->fields.array;
443 } else {
444 array_elements = 1;
445 type = ir->type;
446 }
447
448 int location = ir->location;
449 for (unsigned int i = 0; i < array_elements; i++) {
450 for (unsigned int j = 0; j < type->matrix_columns; j++) {
451 if (urb_setup[location] == -1) {
452 /* If there's no incoming setup data for this slot, don't
453 * emit interpolation for it.
454 */
455 attr.reg_offset += type->vector_elements;
456 location++;
457 continue;
458 }
459
460 for (unsigned int c = 0; c < type->vector_elements; c++) {
461 struct brw_reg interp = interp_reg(location, c);
462 emit(fs_inst(FS_OPCODE_LINTERP,
463 attr,
464 this->delta_x,
465 this->delta_y,
466 fs_reg(interp)));
467 attr.reg_offset++;
468 }
469
470 if (intel->gen < 6) {
471 attr.reg_offset -= type->vector_elements;
472 for (unsigned int c = 0; c < type->vector_elements; c++) {
473 emit(fs_inst(BRW_OPCODE_MUL,
474 attr,
475 attr,
476 this->pixel_w));
477 attr.reg_offset++;
478 }
479 }
480 location++;
481 }
482 }
483
484 return reg;
485 }
486
487 fs_reg *
488 fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
489 {
490 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
491
492 /* The frontfacing comes in as a bit in the thread payload. */
493 if (intel->gen >= 6) {
494 emit(fs_inst(BRW_OPCODE_ASR,
495 *reg,
496 fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
497 fs_reg(15)));
498 emit(fs_inst(BRW_OPCODE_NOT,
499 *reg,
500 *reg));
501 emit(fs_inst(BRW_OPCODE_AND,
502 *reg,
503 *reg,
504 fs_reg(1)));
505 } else {
506 fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
507 struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
508 /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
509 * us front face
510 */
511 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
512 *reg,
513 fs_reg(r1_6ud),
514 fs_reg(1u << 31)));
515 inst->conditional_mod = BRW_CONDITIONAL_L;
516 emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
517 }
518
519 return reg;
520 }
521
522 fs_inst *
523 fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
524 {
525 switch (opcode) {
526 case FS_OPCODE_RCP:
527 case FS_OPCODE_RSQ:
528 case FS_OPCODE_SQRT:
529 case FS_OPCODE_EXP2:
530 case FS_OPCODE_LOG2:
531 case FS_OPCODE_SIN:
532 case FS_OPCODE_COS:
533 break;
534 default:
535 assert(!"not reached: bad math opcode");
536 return NULL;
537 }
538
539 /* Can't do hstride == 0 args to gen6 math, so expand it out. We
540 * might be able to do better by doing execsize = 1 math and then
541 * expanding that result out, but we would need to be careful with
542 * masking.
543 */
544 if (intel->gen >= 6 && src.file == UNIFORM) {
545 fs_reg expanded = fs_reg(this, glsl_type::float_type);
546 emit(fs_inst(BRW_OPCODE_MOV, expanded, src));
547 src = expanded;
548 }
549
550 fs_inst *inst = emit(fs_inst(opcode, dst, src));
551
552 if (intel->gen < 6) {
553 inst->base_mrf = 2;
554 inst->mlen = 1;
555 }
556
557 return inst;
558 }
559
560 fs_inst *
561 fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
562 {
563 int base_mrf = 2;
564 fs_inst *inst;
565
566 assert(opcode == FS_OPCODE_POW);
567
568 if (intel->gen >= 6) {
569 /* Can't do hstride == 0 args to gen6 math, so expand it out. */
570 if (src0.file == UNIFORM) {
571 fs_reg expanded = fs_reg(this, glsl_type::float_type);
572 emit(fs_inst(BRW_OPCODE_MOV, expanded, src0));
573 src0 = expanded;
574 }
575
576 if (src1.file == UNIFORM) {
577 fs_reg expanded = fs_reg(this, glsl_type::float_type);
578 emit(fs_inst(BRW_OPCODE_MOV, expanded, src1));
579 src1 = expanded;
580 }
581
582 inst = emit(fs_inst(opcode, dst, src0, src1));
583 } else {
584 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1));
585 inst = emit(fs_inst(opcode, dst, src0, reg_null_f));
586
587 inst->base_mrf = base_mrf;
588 inst->mlen = 2;
589 }
590 return inst;
591 }
592
593 void
594 fs_visitor::visit(ir_variable *ir)
595 {
596 fs_reg *reg = NULL;
597
598 if (variable_storage(ir))
599 return;
600
601 if (strcmp(ir->name, "gl_FragColor") == 0) {
602 this->frag_color = ir;
603 } else if (strcmp(ir->name, "gl_FragData") == 0) {
604 this->frag_data = ir;
605 } else if (strcmp(ir->name, "gl_FragDepth") == 0) {
606 this->frag_depth = ir;
607 }
608
609 if (ir->mode == ir_var_in) {
610 if (!strcmp(ir->name, "gl_FragCoord")) {
611 reg = emit_fragcoord_interpolation(ir);
612 } else if (!strcmp(ir->name, "gl_FrontFacing")) {
613 reg = emit_frontfacing_interpolation(ir);
614 } else {
615 reg = emit_general_interpolation(ir);
616 }
617 assert(reg);
618 hash_table_insert(this->variable_ht, reg, ir);
619 return;
620 }
621
622 if (ir->mode == ir_var_uniform) {
623 int param_index = c->prog_data.nr_params;
624
625 if (!strncmp(ir->name, "gl_", 3)) {
626 setup_builtin_uniform_values(ir);
627 } else {
628 setup_uniform_values(ir->location, ir->type);
629 }
630
631 reg = new(this->mem_ctx) fs_reg(UNIFORM, param_index);
632 }
633
634 if (!reg)
635 reg = new(this->mem_ctx) fs_reg(this, ir->type);
636
637 hash_table_insert(this->variable_ht, reg, ir);
638 }
639
640 void
641 fs_visitor::visit(ir_dereference_variable *ir)
642 {
643 fs_reg *reg = variable_storage(ir->var);
644 this->result = *reg;
645 }
646
647 void
648 fs_visitor::visit(ir_dereference_record *ir)
649 {
650 const glsl_type *struct_type = ir->record->type;
651
652 ir->record->accept(this);
653
654 unsigned int offset = 0;
655 for (unsigned int i = 0; i < struct_type->length; i++) {
656 if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
657 break;
658 offset += type_size(struct_type->fields.structure[i].type);
659 }
660 this->result.reg_offset += offset;
661 this->result.type = brw_type_for_base_type(ir->type);
662 }
663
664 void
665 fs_visitor::visit(ir_dereference_array *ir)
666 {
667 ir_constant *index;
668 int element_size;
669
670 ir->array->accept(this);
671 index = ir->array_index->as_constant();
672
673 element_size = type_size(ir->type);
674 this->result.type = brw_type_for_base_type(ir->type);
675
676 if (index) {
677 assert(this->result.file == UNIFORM ||
678 (this->result.file == GRF &&
679 this->result.reg != 0));
680 this->result.reg_offset += index->value.i[0] * element_size;
681 } else {
682 assert(!"FINISHME: non-constant array element");
683 }
684 }
685
686 void
687 fs_visitor::visit(ir_expression *ir)
688 {
689 unsigned int operand;
690 fs_reg op[2], temp;
691 fs_inst *inst;
692
693 for (operand = 0; operand < ir->get_num_operands(); operand++) {
694 ir->operands[operand]->accept(this);
695 if (this->result.file == BAD_FILE) {
696 ir_print_visitor v;
697 printf("Failed to get tree for expression operand:\n");
698 ir->operands[operand]->accept(&v);
699 this->fail = true;
700 }
701 op[operand] = this->result;
702
703 /* Matrix expression operands should have been broken down to vector
704 * operations already.
705 */
706 assert(!ir->operands[operand]->type->is_matrix());
707 /* And then those vector operands should have been broken down to scalar.
708 */
709 assert(!ir->operands[operand]->type->is_vector());
710 }
711
712 /* Storage for our result. If our result goes into an assignment, it will
713 * just get copy-propagated out, so no worries.
714 */
715 this->result = fs_reg(this, ir->type);
716
717 switch (ir->operation) {
718 case ir_unop_logic_not:
719 /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
720 * ones complement of the whole register, not just bit 0.
721 */
722 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], fs_reg(1)));
723 break;
724 case ir_unop_neg:
725 op[0].negate = !op[0].negate;
726 this->result = op[0];
727 break;
728 case ir_unop_abs:
729 op[0].abs = true;
730 this->result = op[0];
731 break;
732 case ir_unop_sign:
733 temp = fs_reg(this, ir->type);
734
735 emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
736
737 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
738 inst->conditional_mod = BRW_CONDITIONAL_G;
739 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
740 inst->predicated = true;
741
742 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
743 inst->conditional_mod = BRW_CONDITIONAL_L;
744 inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
745 inst->predicated = true;
746
747 break;
748 case ir_unop_rcp:
749 emit_math(FS_OPCODE_RCP, this->result, op[0]);
750 break;
751
752 case ir_unop_exp2:
753 emit_math(FS_OPCODE_EXP2, this->result, op[0]);
754 break;
755 case ir_unop_log2:
756 emit_math(FS_OPCODE_LOG2, this->result, op[0]);
757 break;
758 case ir_unop_exp:
759 case ir_unop_log:
760 assert(!"not reached: should be handled by ir_explog_to_explog2");
761 break;
762 case ir_unop_sin:
763 emit_math(FS_OPCODE_SIN, this->result, op[0]);
764 break;
765 case ir_unop_cos:
766 emit_math(FS_OPCODE_COS, this->result, op[0]);
767 break;
768
769 case ir_unop_dFdx:
770 emit(fs_inst(FS_OPCODE_DDX, this->result, op[0]));
771 break;
772 case ir_unop_dFdy:
773 emit(fs_inst(FS_OPCODE_DDY, this->result, op[0]));
774 break;
775
776 case ir_binop_add:
777 emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], op[1]));
778 break;
779 case ir_binop_sub:
780 assert(!"not reached: should be handled by ir_sub_to_add_neg");
781 break;
782
783 case ir_binop_mul:
784 emit(fs_inst(BRW_OPCODE_MUL, this->result, op[0], op[1]));
785 break;
786 case ir_binop_div:
787 assert(!"not reached: should be handled by ir_div_to_mul_rcp");
788 break;
789 case ir_binop_mod:
790 assert(!"ir_binop_mod should have been converted to b * fract(a/b)");
791 break;
792
793 case ir_binop_less:
794 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
795 inst->conditional_mod = BRW_CONDITIONAL_L;
796 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
797 break;
798 case ir_binop_greater:
799 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
800 inst->conditional_mod = BRW_CONDITIONAL_G;
801 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
802 break;
803 case ir_binop_lequal:
804 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
805 inst->conditional_mod = BRW_CONDITIONAL_LE;
806 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
807 break;
808 case ir_binop_gequal:
809 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
810 inst->conditional_mod = BRW_CONDITIONAL_GE;
811 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
812 break;
813 case ir_binop_equal:
814 case ir_binop_all_equal: /* same as nequal for scalars */
815 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
816 inst->conditional_mod = BRW_CONDITIONAL_Z;
817 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
818 break;
819 case ir_binop_nequal:
820 case ir_binop_any_nequal: /* same as nequal for scalars */
821 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
822 inst->conditional_mod = BRW_CONDITIONAL_NZ;
823 emit(fs_inst(BRW_OPCODE_AND, this->result, this->result, fs_reg(0x1)));
824 break;
825
826 case ir_binop_logic_xor:
827 emit(fs_inst(BRW_OPCODE_XOR, this->result, op[0], op[1]));
828 break;
829
830 case ir_binop_logic_or:
831 emit(fs_inst(BRW_OPCODE_OR, this->result, op[0], op[1]));
832 break;
833
834 case ir_binop_logic_and:
835 emit(fs_inst(BRW_OPCODE_AND, this->result, op[0], op[1]));
836 break;
837
838 case ir_binop_dot:
839 case ir_binop_cross:
840 case ir_unop_any:
841 assert(!"not reached: should be handled by brw_fs_channel_expressions");
842 break;
843
844 case ir_unop_noise:
845 assert(!"not reached: should be handled by lower_noise");
846 break;
847
848 case ir_unop_sqrt:
849 emit_math(FS_OPCODE_SQRT, this->result, op[0]);
850 break;
851
852 case ir_unop_rsq:
853 emit_math(FS_OPCODE_RSQ, this->result, op[0]);
854 break;
855
856 case ir_unop_i2f:
857 case ir_unop_b2f:
858 case ir_unop_b2i:
859 case ir_unop_f2i:
860 emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
861 break;
862 case ir_unop_f2b:
863 case ir_unop_i2b:
864 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
865 inst->conditional_mod = BRW_CONDITIONAL_NZ;
866 inst = emit(fs_inst(BRW_OPCODE_AND, this->result,
867 this->result, fs_reg(1)));
868 break;
869
870 case ir_unop_trunc:
871 emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0]));
872 break;
873 case ir_unop_ceil:
874 op[0].negate = !op[0].negate;
875 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
876 this->result.negate = true;
877 break;
878 case ir_unop_floor:
879 inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
880 break;
881 case ir_unop_fract:
882 inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
883 break;
884 case ir_unop_round_even:
885 emit(fs_inst(BRW_OPCODE_RNDE, this->result, op[0]));
886 break;
887
888 case ir_binop_min:
889 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
890 inst->conditional_mod = BRW_CONDITIONAL_L;
891
892 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
893 inst->predicated = true;
894 break;
895 case ir_binop_max:
896 inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
897 inst->conditional_mod = BRW_CONDITIONAL_G;
898
899 inst = emit(fs_inst(BRW_OPCODE_SEL, this->result, op[0], op[1]));
900 inst->predicated = true;
901 break;
902
903 case ir_binop_pow:
904 emit_math(FS_OPCODE_POW, this->result, op[0], op[1]);
905 break;
906
907 case ir_unop_bit_not:
908 case ir_unop_u2f:
909 case ir_binop_lshift:
910 case ir_binop_rshift:
911 case ir_binop_bit_and:
912 case ir_binop_bit_xor:
913 case ir_binop_bit_or:
914 assert(!"GLSL 1.30 features unsupported");
915 break;
916 }
917 }
918
919 void
920 fs_visitor::emit_assignment_writes(fs_reg &l, fs_reg &r,
921 const glsl_type *type, bool predicated)
922 {
923 switch (type->base_type) {
924 case GLSL_TYPE_FLOAT:
925 case GLSL_TYPE_UINT:
926 case GLSL_TYPE_INT:
927 case GLSL_TYPE_BOOL:
928 for (unsigned int i = 0; i < type->components(); i++) {
929 l.type = brw_type_for_base_type(type);
930 r.type = brw_type_for_base_type(type);
931
932 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
933 inst->predicated = predicated;
934
935 l.reg_offset++;
936 r.reg_offset++;
937 }
938 break;
939 case GLSL_TYPE_ARRAY:
940 for (unsigned int i = 0; i < type->length; i++) {
941 emit_assignment_writes(l, r, type->fields.array, predicated);
942 }
943 break;
944
945 case GLSL_TYPE_STRUCT:
946 for (unsigned int i = 0; i < type->length; i++) {
947 emit_assignment_writes(l, r, type->fields.structure[i].type,
948 predicated);
949 }
950 break;
951
952 case GLSL_TYPE_SAMPLER:
953 break;
954
955 default:
956 assert(!"not reached");
957 break;
958 }
959 }
960
961 void
962 fs_visitor::visit(ir_assignment *ir)
963 {
964 struct fs_reg l, r;
965 fs_inst *inst;
966
967 /* FINISHME: arrays on the lhs */
968 ir->lhs->accept(this);
969 l = this->result;
970
971 ir->rhs->accept(this);
972 r = this->result;
973
974 assert(l.file != BAD_FILE);
975 assert(r.file != BAD_FILE);
976
977 if (ir->condition) {
978 emit_bool_to_cond_code(ir->condition);
979 }
980
981 if (ir->lhs->type->is_scalar() ||
982 ir->lhs->type->is_vector()) {
983 for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
984 if (ir->write_mask & (1 << i)) {
985 inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
986 if (ir->condition)
987 inst->predicated = true;
988 r.reg_offset++;
989 }
990 l.reg_offset++;
991 }
992 } else {
993 emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
994 }
995 }
996
997 fs_inst *
998 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
999 {
1000 int mlen;
1001 int base_mrf = 1;
1002 bool simd16 = false;
1003 fs_reg orig_dst;
1004
1005 /* g0 header. */
1006 mlen = 1;
1007
1008 if (ir->shadow_comparitor) {
1009 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1010 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
1011 coordinate));
1012 coordinate.reg_offset++;
1013 }
1014 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1015 mlen += 3;
1016
1017 if (ir->op == ir_tex) {
1018 /* There's no plain shadow compare message, so we use shadow
1019 * compare with a bias of 0.0.
1020 */
1021 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1022 fs_reg(0.0f)));
1023 mlen++;
1024 } else if (ir->op == ir_txb) {
1025 ir->lod_info.bias->accept(this);
1026 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1027 this->result));
1028 mlen++;
1029 } else {
1030 assert(ir->op == ir_txl);
1031 ir->lod_info.lod->accept(this);
1032 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1033 this->result));
1034 mlen++;
1035 }
1036
1037 ir->shadow_comparitor->accept(this);
1038 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1039 mlen++;
1040 } else if (ir->op == ir_tex) {
1041 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1042 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
1043 coordinate));
1044 coordinate.reg_offset++;
1045 }
1046 /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
1047 mlen += 3;
1048 } else {
1049 /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
1050 * instructions. We'll need to do SIMD16 here.
1051 */
1052 assert(ir->op == ir_txb || ir->op == ir_txl);
1053
1054 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1055 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2),
1056 coordinate));
1057 coordinate.reg_offset++;
1058 }
1059
1060 /* lod/bias appears after u/v/r. */
1061 mlen += 6;
1062
1063 if (ir->op == ir_txb) {
1064 ir->lod_info.bias->accept(this);
1065 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1066 this->result));
1067 mlen++;
1068 } else {
1069 ir->lod_info.lod->accept(this);
1070 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
1071 this->result));
1072 mlen++;
1073 }
1074
1075 /* The unused upper half. */
1076 mlen++;
1077
1078 /* Now, since we're doing simd16, the return is 2 interleaved
1079 * vec4s where the odd-indexed ones are junk. We'll need to move
1080 * this weirdness around to the expected layout.
1081 */
1082 simd16 = true;
1083 orig_dst = dst;
1084 dst = fs_reg(this, glsl_type::get_array_instance(glsl_type::vec4_type,
1085 2));
1086 dst.type = BRW_REGISTER_TYPE_F;
1087 }
1088
1089 fs_inst *inst = NULL;
1090 switch (ir->op) {
1091 case ir_tex:
1092 inst = emit(fs_inst(FS_OPCODE_TEX, dst));
1093 break;
1094 case ir_txb:
1095 inst = emit(fs_inst(FS_OPCODE_TXB, dst));
1096 break;
1097 case ir_txl:
1098 inst = emit(fs_inst(FS_OPCODE_TXL, dst));
1099 break;
1100 case ir_txd:
1101 case ir_txf:
1102 assert(!"GLSL 1.30 features unsupported");
1103 break;
1104 }
1105 inst->base_mrf = base_mrf;
1106 inst->mlen = mlen;
1107
1108 if (simd16) {
1109 for (int i = 0; i < 4; i++) {
1110 emit(fs_inst(BRW_OPCODE_MOV, orig_dst, dst));
1111 orig_dst.reg_offset++;
1112 dst.reg_offset += 2;
1113 }
1114 }
1115
1116 return inst;
1117 }
1118
1119 fs_inst *
1120 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate)
1121 {
1122 /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
1123 * optional parameters like shadow comparitor or LOD bias. If
1124 * optional parameters aren't present, those base slots are
1125 * optional and don't need to be included in the message.
1126 *
1127 * We don't fill in the unnecessary slots regardless, which may
1128 * look surprising in the disassembly.
1129 */
1130 int mlen = 1; /* g0 header always present. */
1131 int base_mrf = 1;
1132
1133 for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
1134 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
1135 coordinate));
1136 coordinate.reg_offset++;
1137 }
1138 mlen += ir->coordinate->type->vector_elements;
1139
1140 if (ir->shadow_comparitor) {
1141 mlen = MAX2(mlen, 5);
1142
1143 ir->shadow_comparitor->accept(this);
1144 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1145 mlen++;
1146 }
1147
1148 fs_inst *inst = NULL;
1149 switch (ir->op) {
1150 case ir_tex:
1151 inst = emit(fs_inst(FS_OPCODE_TEX, dst));
1152 break;
1153 case ir_txb:
1154 ir->lod_info.bias->accept(this);
1155 mlen = MAX2(mlen, 5);
1156 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1157 mlen++;
1158
1159 inst = emit(fs_inst(FS_OPCODE_TXB, dst));
1160 break;
1161 case ir_txl:
1162 ir->lod_info.lod->accept(this);
1163 mlen = MAX2(mlen, 5);
1164 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
1165 mlen++;
1166
1167 inst = emit(fs_inst(FS_OPCODE_TXL, dst));
1168 break;
1169 case ir_txd:
1170 case ir_txf:
1171 assert(!"GLSL 1.30 features unsupported");
1172 break;
1173 }
1174 inst->base_mrf = base_mrf;
1175 inst->mlen = mlen;
1176
1177 return inst;
1178 }
1179
1180 void
1181 fs_visitor::visit(ir_texture *ir)
1182 {
1183 int sampler;
1184 fs_inst *inst = NULL;
1185
1186 ir->coordinate->accept(this);
1187 fs_reg coordinate = this->result;
1188
1189 /* Should be lowered by do_lower_texture_projection */
1190 assert(!ir->projector);
1191
1192 sampler = _mesa_get_sampler_uniform_value(ir->sampler,
1193 ctx->Shader.CurrentProgram,
1194 &brw->fragment_program->Base);
1195 sampler = c->fp->program.Base.SamplerUnits[sampler];
1196
1197 /* The 965 requires the EU to do the normalization of GL rectangle
1198 * texture coordinates. We use the program parameter state
1199 * tracking to get the scaling factor.
1200 */
1201 if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) {
1202 struct gl_program_parameter_list *params = c->fp->program.Base.Parameters;
1203 int tokens[STATE_LENGTH] = {
1204 STATE_INTERNAL,
1205 STATE_TEXRECT_SCALE,
1206 sampler,
1207 0,
1208 0
1209 };
1210
1211 fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
1212 fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
1213 GLuint index = _mesa_add_state_reference(params,
1214 (gl_state_index *)tokens);
1215 float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
1216
1217 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[0];
1218 c->prog_data.param[c->prog_data.nr_params++] = &vec_values[1];
1219
1220 fs_reg dst = fs_reg(this, ir->coordinate->type);
1221 fs_reg src = coordinate;
1222 coordinate = dst;
1223
1224 emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_x));
1225 dst.reg_offset++;
1226 src.reg_offset++;
1227 emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_y));
1228 }
1229
1230 /* Writemasking doesn't eliminate channels on SIMD8 texture
1231 * samples, so don't worry about them.
1232 */
1233 fs_reg dst = fs_reg(this, glsl_type::vec4_type);
1234
1235 if (intel->gen < 5) {
1236 inst = emit_texture_gen4(ir, dst, coordinate);
1237 } else {
1238 inst = emit_texture_gen5(ir, dst, coordinate);
1239 }
1240
1241 inst->sampler = sampler;
1242
1243 this->result = dst;
1244
1245 if (ir->shadow_comparitor)
1246 inst->shadow_compare = true;
1247
1248 if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) {
1249 fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type);
1250
1251 for (int i = 0; i < 4; i++) {
1252 int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
1253 fs_reg l = swizzle_dst;
1254 l.reg_offset += i;
1255
1256 if (swiz == SWIZZLE_ZERO) {
1257 emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(0.0f)));
1258 } else if (swiz == SWIZZLE_ONE) {
1259 emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(1.0f)));
1260 } else {
1261 fs_reg r = dst;
1262 r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
1263 emit(fs_inst(BRW_OPCODE_MOV, l, r));
1264 }
1265 }
1266 this->result = swizzle_dst;
1267 }
1268 }
1269
1270 void
1271 fs_visitor::visit(ir_swizzle *ir)
1272 {
1273 ir->val->accept(this);
1274 fs_reg val = this->result;
1275
1276 if (ir->type->vector_elements == 1) {
1277 this->result.reg_offset += ir->mask.x;
1278 return;
1279 }
1280
1281 fs_reg result = fs_reg(this, ir->type);
1282 this->result = result;
1283
1284 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1285 fs_reg channel = val;
1286 int swiz = 0;
1287
1288 switch (i) {
1289 case 0:
1290 swiz = ir->mask.x;
1291 break;
1292 case 1:
1293 swiz = ir->mask.y;
1294 break;
1295 case 2:
1296 swiz = ir->mask.z;
1297 break;
1298 case 3:
1299 swiz = ir->mask.w;
1300 break;
1301 }
1302
1303 channel.reg_offset += swiz;
1304 emit(fs_inst(BRW_OPCODE_MOV, result, channel));
1305 result.reg_offset++;
1306 }
1307 }
1308
1309 void
1310 fs_visitor::visit(ir_discard *ir)
1311 {
1312 fs_reg temp = fs_reg(this, glsl_type::uint_type);
1313
1314 assert(ir->condition == NULL); /* FINISHME */
1315
1316 emit(fs_inst(FS_OPCODE_DISCARD_NOT, temp, reg_null_d));
1317 emit(fs_inst(FS_OPCODE_DISCARD_AND, reg_null_d, temp));
1318 kill_emitted = true;
1319 }
1320
1321 void
1322 fs_visitor::visit(ir_constant *ir)
1323 {
1324 fs_reg reg(this, ir->type);
1325 this->result = reg;
1326
1327 for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
1328 switch (ir->type->base_type) {
1329 case GLSL_TYPE_FLOAT:
1330 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.f[i])));
1331 break;
1332 case GLSL_TYPE_UINT:
1333 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.u[i])));
1334 break;
1335 case GLSL_TYPE_INT:
1336 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg(ir->value.i[i])));
1337 break;
1338 case GLSL_TYPE_BOOL:
1339 emit(fs_inst(BRW_OPCODE_MOV, reg, fs_reg((int)ir->value.b[i])));
1340 break;
1341 default:
1342 assert(!"Non-float/uint/int/bool constant");
1343 }
1344 reg.reg_offset++;
1345 }
1346 }
1347
1348 void
1349 fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
1350 {
1351 ir_expression *expr = ir->as_expression();
1352
1353 if (expr) {
1354 fs_reg op[2];
1355 fs_inst *inst;
1356
1357 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1358 assert(expr->operands[i]->type->is_scalar());
1359
1360 expr->operands[i]->accept(this);
1361 op[i] = this->result;
1362 }
1363
1364 switch (expr->operation) {
1365 case ir_unop_logic_not:
1366 inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)));
1367 inst->conditional_mod = BRW_CONDITIONAL_Z;
1368 break;
1369
1370 case ir_binop_logic_xor:
1371 inst = emit(fs_inst(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]));
1372 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1373 break;
1374
1375 case ir_binop_logic_or:
1376 inst = emit(fs_inst(BRW_OPCODE_OR, reg_null_d, op[0], op[1]));
1377 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1378 break;
1379
1380 case ir_binop_logic_and:
1381 inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], op[1]));
1382 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1383 break;
1384
1385 case ir_unop_f2b:
1386 if (intel->gen >= 6) {
1387 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
1388 op[0], fs_reg(0.0f)));
1389 } else {
1390 inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
1391 }
1392 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1393 break;
1394
1395 case ir_unop_i2b:
1396 if (intel->gen >= 6) {
1397 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)));
1398 } else {
1399 inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
1400 }
1401 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1402 break;
1403
1404 case ir_binop_greater:
1405 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1406 inst->conditional_mod = BRW_CONDITIONAL_G;
1407 break;
1408 case ir_binop_gequal:
1409 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1410 inst->conditional_mod = BRW_CONDITIONAL_GE;
1411 break;
1412 case ir_binop_less:
1413 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1414 inst->conditional_mod = BRW_CONDITIONAL_L;
1415 break;
1416 case ir_binop_lequal:
1417 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1418 inst->conditional_mod = BRW_CONDITIONAL_LE;
1419 break;
1420 case ir_binop_equal:
1421 case ir_binop_all_equal:
1422 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1423 inst->conditional_mod = BRW_CONDITIONAL_Z;
1424 break;
1425 case ir_binop_nequal:
1426 case ir_binop_any_nequal:
1427 inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
1428 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1429 break;
1430 default:
1431 assert(!"not reached");
1432 this->fail = true;
1433 break;
1434 }
1435 return;
1436 }
1437
1438 ir->accept(this);
1439
1440 if (intel->gen >= 6) {
1441 fs_inst *inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d,
1442 this->result, fs_reg(1)));
1443 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1444 } else {
1445 fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, this->result));
1446 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1447 }
1448 }
1449
1450 /**
1451 * Emit a gen6 IF statement with the comparison folded into the IF
1452 * instruction.
1453 */
1454 void
1455 fs_visitor::emit_if_gen6(ir_if *ir)
1456 {
1457 ir_expression *expr = ir->condition->as_expression();
1458
1459 if (expr) {
1460 fs_reg op[2];
1461 fs_inst *inst;
1462 fs_reg temp;
1463
1464 for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
1465 assert(expr->operands[i]->type->is_scalar());
1466
1467 expr->operands[i]->accept(this);
1468 op[i] = this->result;
1469 }
1470
1471 switch (expr->operation) {
1472 case ir_unop_logic_not:
1473 inst = emit(fs_inst(BRW_OPCODE_IF, temp, op[0], fs_reg(1)));
1474 inst->conditional_mod = BRW_CONDITIONAL_Z;
1475 return;
1476
1477 case ir_binop_logic_xor:
1478 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1479 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1480 return;
1481
1482 case ir_binop_logic_or:
1483 temp = fs_reg(this, glsl_type::bool_type);
1484 emit(fs_inst(BRW_OPCODE_OR, temp, op[0], op[1]));
1485 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)));
1486 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1487 return;
1488
1489 case ir_binop_logic_and:
1490 temp = fs_reg(this, glsl_type::bool_type);
1491 emit(fs_inst(BRW_OPCODE_AND, temp, op[0], op[1]));
1492 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, temp, fs_reg(0)));
1493 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1494 return;
1495
1496 case ir_unop_f2b:
1497 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0)));
1498 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1499 return;
1500
1501 case ir_unop_i2b:
1502 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)));
1503 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1504 return;
1505
1506 case ir_binop_greater:
1507 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1508 inst->conditional_mod = BRW_CONDITIONAL_G;
1509 return;
1510 case ir_binop_gequal:
1511 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1512 inst->conditional_mod = BRW_CONDITIONAL_GE;
1513 return;
1514 case ir_binop_less:
1515 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1516 inst->conditional_mod = BRW_CONDITIONAL_L;
1517 return;
1518 case ir_binop_lequal:
1519 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1520 inst->conditional_mod = BRW_CONDITIONAL_LE;
1521 return;
1522 case ir_binop_equal:
1523 case ir_binop_all_equal:
1524 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1525 inst->conditional_mod = BRW_CONDITIONAL_Z;
1526 return;
1527 case ir_binop_nequal:
1528 case ir_binop_any_nequal:
1529 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], op[1]));
1530 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1531 return;
1532 default:
1533 assert(!"not reached");
1534 inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, op[0], fs_reg(0)));
1535 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1536 this->fail = true;
1537 return;
1538 }
1539 return;
1540 }
1541
1542 ir->condition->accept(this);
1543
1544 fs_inst *inst = emit(fs_inst(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0)));
1545 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1546 }
1547
1548 void
1549 fs_visitor::visit(ir_if *ir)
1550 {
1551 fs_inst *inst;
1552
1553 /* Don't point the annotation at the if statement, because then it plus
1554 * the then and else blocks get printed.
1555 */
1556 this->base_ir = ir->condition;
1557
1558 if (intel->gen >= 6) {
1559 emit_if_gen6(ir);
1560 } else {
1561 emit_bool_to_cond_code(ir->condition);
1562
1563 inst = emit(fs_inst(BRW_OPCODE_IF));
1564 inst->predicated = true;
1565 }
1566
1567 foreach_iter(exec_list_iterator, iter, ir->then_instructions) {
1568 ir_instruction *ir = (ir_instruction *)iter.get();
1569 this->base_ir = ir;
1570
1571 ir->accept(this);
1572 }
1573
1574 if (!ir->else_instructions.is_empty()) {
1575 emit(fs_inst(BRW_OPCODE_ELSE));
1576
1577 foreach_iter(exec_list_iterator, iter, ir->else_instructions) {
1578 ir_instruction *ir = (ir_instruction *)iter.get();
1579 this->base_ir = ir;
1580
1581 ir->accept(this);
1582 }
1583 }
1584
1585 emit(fs_inst(BRW_OPCODE_ENDIF));
1586 }
1587
1588 void
1589 fs_visitor::visit(ir_loop *ir)
1590 {
1591 fs_reg counter = reg_undef;
1592
1593 if (ir->counter) {
1594 this->base_ir = ir->counter;
1595 ir->counter->accept(this);
1596 counter = *(variable_storage(ir->counter));
1597
1598 if (ir->from) {
1599 this->base_ir = ir->from;
1600 ir->from->accept(this);
1601
1602 emit(fs_inst(BRW_OPCODE_MOV, counter, this->result));
1603 }
1604 }
1605
1606 emit(fs_inst(BRW_OPCODE_DO));
1607
1608 if (ir->to) {
1609 this->base_ir = ir->to;
1610 ir->to->accept(this);
1611
1612 fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
1613 counter, this->result));
1614 switch (ir->cmp) {
1615 case ir_binop_equal:
1616 inst->conditional_mod = BRW_CONDITIONAL_Z;
1617 break;
1618 case ir_binop_nequal:
1619 inst->conditional_mod = BRW_CONDITIONAL_NZ;
1620 break;
1621 case ir_binop_gequal:
1622 inst->conditional_mod = BRW_CONDITIONAL_GE;
1623 break;
1624 case ir_binop_lequal:
1625 inst->conditional_mod = BRW_CONDITIONAL_LE;
1626 break;
1627 case ir_binop_greater:
1628 inst->conditional_mod = BRW_CONDITIONAL_G;
1629 break;
1630 case ir_binop_less:
1631 inst->conditional_mod = BRW_CONDITIONAL_L;
1632 break;
1633 default:
1634 assert(!"not reached: unknown loop condition");
1635 this->fail = true;
1636 break;
1637 }
1638
1639 inst = emit(fs_inst(BRW_OPCODE_BREAK));
1640 inst->predicated = true;
1641 }
1642
1643 foreach_iter(exec_list_iterator, iter, ir->body_instructions) {
1644 ir_instruction *ir = (ir_instruction *)iter.get();
1645
1646 this->base_ir = ir;
1647 ir->accept(this);
1648 }
1649
1650 if (ir->increment) {
1651 this->base_ir = ir->increment;
1652 ir->increment->accept(this);
1653 emit(fs_inst(BRW_OPCODE_ADD, counter, counter, this->result));
1654 }
1655
1656 emit(fs_inst(BRW_OPCODE_WHILE));
1657 }
1658
1659 void
1660 fs_visitor::visit(ir_loop_jump *ir)
1661 {
1662 switch (ir->mode) {
1663 case ir_loop_jump::jump_break:
1664 emit(fs_inst(BRW_OPCODE_BREAK));
1665 break;
1666 case ir_loop_jump::jump_continue:
1667 emit(fs_inst(BRW_OPCODE_CONTINUE));
1668 break;
1669 }
1670 }
1671
1672 void
1673 fs_visitor::visit(ir_call *ir)
1674 {
1675 assert(!"FINISHME");
1676 }
1677
1678 void
1679 fs_visitor::visit(ir_return *ir)
1680 {
1681 assert(!"FINISHME");
1682 }
1683
1684 void
1685 fs_visitor::visit(ir_function *ir)
1686 {
1687 /* Ignore function bodies other than main() -- we shouldn't see calls to
1688 * them since they should all be inlined before we get to ir_to_mesa.
1689 */
1690 if (strcmp(ir->name, "main") == 0) {
1691 const ir_function_signature *sig;
1692 exec_list empty;
1693
1694 sig = ir->matching_signature(&empty);
1695
1696 assert(sig);
1697
1698 foreach_iter(exec_list_iterator, iter, sig->body) {
1699 ir_instruction *ir = (ir_instruction *)iter.get();
1700 this->base_ir = ir;
1701
1702 ir->accept(this);
1703 }
1704 }
1705 }
1706
1707 void
1708 fs_visitor::visit(ir_function_signature *ir)
1709 {
1710 assert(!"not reached");
1711 (void)ir;
1712 }
1713
1714 fs_inst *
1715 fs_visitor::emit(fs_inst inst)
1716 {
1717 fs_inst *list_inst = new(mem_ctx) fs_inst;
1718 *list_inst = inst;
1719
1720 list_inst->annotation = this->current_annotation;
1721 list_inst->ir = this->base_ir;
1722
1723 this->instructions.push_tail(list_inst);
1724
1725 return list_inst;
1726 }
1727
1728 /** Emits a dummy fragment shader consisting of magenta for bringup purposes. */
1729 void
1730 fs_visitor::emit_dummy_fs()
1731 {
1732 /* Everyone's favorite color. */
1733 emit(fs_inst(BRW_OPCODE_MOV,
1734 fs_reg(MRF, 2),
1735 fs_reg(1.0f)));
1736 emit(fs_inst(BRW_OPCODE_MOV,
1737 fs_reg(MRF, 3),
1738 fs_reg(0.0f)));
1739 emit(fs_inst(BRW_OPCODE_MOV,
1740 fs_reg(MRF, 4),
1741 fs_reg(1.0f)));
1742 emit(fs_inst(BRW_OPCODE_MOV,
1743 fs_reg(MRF, 5),
1744 fs_reg(0.0f)));
1745
1746 fs_inst *write;
1747 write = emit(fs_inst(FS_OPCODE_FB_WRITE,
1748 fs_reg(0),
1749 fs_reg(0)));
1750 write->base_mrf = 0;
1751 }
1752
1753 /* The register location here is relative to the start of the URB
1754 * data. It will get adjusted to be a real location before
1755 * generate_code() time.
1756 */
1757 struct brw_reg
1758 fs_visitor::interp_reg(int location, int channel)
1759 {
1760 int regnr = urb_setup[location] * 2 + channel / 2;
1761 int stride = (channel & 1) * 4;
1762
1763 assert(urb_setup[location] != -1);
1764
1765 return brw_vec1_grf(regnr, stride);
1766 }
1767
1768 /** Emits the interpolation for the varying inputs. */
1769 void
1770 fs_visitor::emit_interpolation_setup_gen4()
1771 {
1772 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1773
1774 this->current_annotation = "compute pixel centers";
1775 this->pixel_x = fs_reg(this, glsl_type::uint_type);
1776 this->pixel_y = fs_reg(this, glsl_type::uint_type);
1777 this->pixel_x.type = BRW_REGISTER_TYPE_UW;
1778 this->pixel_y.type = BRW_REGISTER_TYPE_UW;
1779 emit(fs_inst(BRW_OPCODE_ADD,
1780 this->pixel_x,
1781 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1782 fs_reg(brw_imm_v(0x10101010))));
1783 emit(fs_inst(BRW_OPCODE_ADD,
1784 this->pixel_y,
1785 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1786 fs_reg(brw_imm_v(0x11001100))));
1787
1788 this->current_annotation = "compute pixel deltas from v0";
1789 if (brw->has_pln) {
1790 this->delta_x = fs_reg(this, glsl_type::vec2_type);
1791 this->delta_y = this->delta_x;
1792 this->delta_y.reg_offset++;
1793 } else {
1794 this->delta_x = fs_reg(this, glsl_type::float_type);
1795 this->delta_y = fs_reg(this, glsl_type::float_type);
1796 }
1797 emit(fs_inst(BRW_OPCODE_ADD,
1798 this->delta_x,
1799 this->pixel_x,
1800 fs_reg(negate(brw_vec1_grf(1, 0)))));
1801 emit(fs_inst(BRW_OPCODE_ADD,
1802 this->delta_y,
1803 this->pixel_y,
1804 fs_reg(negate(brw_vec1_grf(1, 1)))));
1805
1806 this->current_annotation = "compute pos.w and 1/pos.w";
1807 /* Compute wpos.w. It's always in our setup, since it's needed to
1808 * interpolate the other attributes.
1809 */
1810 this->wpos_w = fs_reg(this, glsl_type::float_type);
1811 emit(fs_inst(FS_OPCODE_LINTERP, wpos_w, this->delta_x, this->delta_y,
1812 interp_reg(FRAG_ATTRIB_WPOS, 3)));
1813 /* Compute the pixel 1/W value from wpos.w. */
1814 this->pixel_w = fs_reg(this, glsl_type::float_type);
1815 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
1816 this->current_annotation = NULL;
1817 }
1818
1819 /** Emits the interpolation for the varying inputs. */
1820 void
1821 fs_visitor::emit_interpolation_setup_gen6()
1822 {
1823 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
1824
1825 /* If the pixel centers end up used, the setup is the same as for gen4. */
1826 this->current_annotation = "compute pixel centers";
1827 fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
1828 fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
1829 int_pixel_x.type = BRW_REGISTER_TYPE_UW;
1830 int_pixel_y.type = BRW_REGISTER_TYPE_UW;
1831 emit(fs_inst(BRW_OPCODE_ADD,
1832 int_pixel_x,
1833 fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
1834 fs_reg(brw_imm_v(0x10101010))));
1835 emit(fs_inst(BRW_OPCODE_ADD,
1836 int_pixel_y,
1837 fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
1838 fs_reg(brw_imm_v(0x11001100))));
1839
1840 /* As of gen6, we can no longer mix float and int sources. We have
1841 * to turn the integer pixel centers into floats for their actual
1842 * use.
1843 */
1844 this->pixel_x = fs_reg(this, glsl_type::float_type);
1845 this->pixel_y = fs_reg(this, glsl_type::float_type);
1846 emit(fs_inst(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x));
1847 emit(fs_inst(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y));
1848
1849 this->current_annotation = "compute 1/pos.w";
1850 this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0));
1851 this->pixel_w = fs_reg(this, glsl_type::float_type);
1852 emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
1853
1854 this->delta_x = fs_reg(brw_vec8_grf(2, 0));
1855 this->delta_y = fs_reg(brw_vec8_grf(3, 0));
1856
1857 this->current_annotation = NULL;
1858 }
1859
1860 void
1861 fs_visitor::emit_fb_writes()
1862 {
1863 this->current_annotation = "FB write header";
1864 GLboolean header_present = GL_TRUE;
1865 int nr = 0;
1866
1867 if (intel->gen >= 6 &&
1868 !this->kill_emitted &&
1869 c->key.nr_color_regions == 1) {
1870 header_present = false;
1871 }
1872
1873 if (header_present) {
1874 /* m0, m1 header */
1875 nr += 2;
1876 }
1877
1878 if (c->key.aa_dest_stencil_reg) {
1879 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1880 fs_reg(brw_vec8_grf(c->key.aa_dest_stencil_reg, 0))));
1881 }
1882
1883 /* Reserve space for color. It'll be filled in per MRT below. */
1884 int color_mrf = nr;
1885 nr += 4;
1886
1887 if (c->key.source_depth_to_render_target) {
1888 if (c->key.computes_depth) {
1889 /* Hand over gl_FragDepth. */
1890 assert(this->frag_depth);
1891 fs_reg depth = *(variable_storage(this->frag_depth));
1892
1893 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++), depth));
1894 } else {
1895 /* Pass through the payload depth. */
1896 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1897 fs_reg(brw_vec8_grf(c->key.source_depth_reg, 0))));
1898 }
1899 }
1900
1901 if (c->key.dest_depth_reg) {
1902 emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
1903 fs_reg(brw_vec8_grf(c->key.dest_depth_reg, 0))));
1904 }
1905
1906 fs_reg color = reg_undef;
1907 if (this->frag_color)
1908 color = *(variable_storage(this->frag_color));
1909 else if (this->frag_data)
1910 color = *(variable_storage(this->frag_data));
1911
1912 for (int target = 0; target < c->key.nr_color_regions; target++) {
1913 this->current_annotation = talloc_asprintf(this->mem_ctx,
1914 "FB write target %d",
1915 target);
1916 if (this->frag_color || this->frag_data) {
1917 for (int i = 0; i < 4; i++) {
1918 emit(fs_inst(BRW_OPCODE_MOV,
1919 fs_reg(MRF, color_mrf + i),
1920 color));
1921 color.reg_offset++;
1922 }
1923 }
1924
1925 if (this->frag_color)
1926 color.reg_offset -= 4;
1927
1928 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1929 reg_undef, reg_undef));
1930 inst->target = target;
1931 inst->base_mrf = 0;
1932 inst->mlen = nr;
1933 if (target == c->key.nr_color_regions - 1)
1934 inst->eot = true;
1935 inst->header_present = header_present;
1936 }
1937
1938 if (c->key.nr_color_regions == 0) {
1939 fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
1940 reg_undef, reg_undef));
1941 inst->base_mrf = 0;
1942 inst->mlen = nr;
1943 inst->eot = true;
1944 inst->header_present = header_present;
1945 }
1946
1947 this->current_annotation = NULL;
1948 }
1949
1950 void
1951 fs_visitor::generate_fb_write(fs_inst *inst)
1952 {
1953 GLboolean eot = inst->eot;
1954 struct brw_reg implied_header;
1955
1956 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
1957 * move, here's g1.
1958 */
1959 brw_push_insn_state(p);
1960 brw_set_mask_control(p, BRW_MASK_DISABLE);
1961 brw_set_compression_control(p, BRW_COMPRESSION_NONE);
1962
1963 if (inst->header_present) {
1964 if (intel->gen >= 6) {
1965 brw_MOV(p,
1966 brw_message_reg(inst->base_mrf),
1967 brw_vec8_grf(0, 0));
1968 implied_header = brw_null_reg();
1969 } else {
1970 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
1971 }
1972
1973 brw_MOV(p,
1974 brw_message_reg(inst->base_mrf + 1),
1975 brw_vec8_grf(1, 0));
1976 } else {
1977 implied_header = brw_null_reg();
1978 }
1979
1980 brw_pop_insn_state(p);
1981
1982 brw_fb_WRITE(p,
1983 8, /* dispatch_width */
1984 retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
1985 inst->base_mrf,
1986 implied_header,
1987 inst->target,
1988 inst->mlen,
1989 0,
1990 eot);
1991 }
1992
1993 void
1994 fs_visitor::generate_linterp(fs_inst *inst,
1995 struct brw_reg dst, struct brw_reg *src)
1996 {
1997 struct brw_reg delta_x = src[0];
1998 struct brw_reg delta_y = src[1];
1999 struct brw_reg interp = src[2];
2000
2001 if (brw->has_pln &&
2002 delta_y.nr == delta_x.nr + 1 &&
2003 (intel->gen >= 6 || (delta_x.nr & 1) == 0)) {
2004 brw_PLN(p, dst, interp, delta_x);
2005 } else {
2006 brw_LINE(p, brw_null_reg(), interp, delta_x);
2007 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
2008 }
2009 }
2010
2011 void
2012 fs_visitor::generate_math(fs_inst *inst,
2013 struct brw_reg dst, struct brw_reg *src)
2014 {
2015 int op;
2016
2017 switch (inst->opcode) {
2018 case FS_OPCODE_RCP:
2019 op = BRW_MATH_FUNCTION_INV;
2020 break;
2021 case FS_OPCODE_RSQ:
2022 op = BRW_MATH_FUNCTION_RSQ;
2023 break;
2024 case FS_OPCODE_SQRT:
2025 op = BRW_MATH_FUNCTION_SQRT;
2026 break;
2027 case FS_OPCODE_EXP2:
2028 op = BRW_MATH_FUNCTION_EXP;
2029 break;
2030 case FS_OPCODE_LOG2:
2031 op = BRW_MATH_FUNCTION_LOG;
2032 break;
2033 case FS_OPCODE_POW:
2034 op = BRW_MATH_FUNCTION_POW;
2035 break;
2036 case FS_OPCODE_SIN:
2037 op = BRW_MATH_FUNCTION_SIN;
2038 break;
2039 case FS_OPCODE_COS:
2040 op = BRW_MATH_FUNCTION_COS;
2041 break;
2042 default:
2043 assert(!"not reached: unknown math function");
2044 op = 0;
2045 break;
2046 }
2047
2048 if (intel->gen >= 6) {
2049 assert(inst->mlen == 0);
2050
2051 if (inst->opcode == FS_OPCODE_POW) {
2052 brw_math2(p, dst, op, src[0], src[1]);
2053 } else {
2054 brw_math(p, dst,
2055 op,
2056 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
2057 BRW_MATH_SATURATE_NONE,
2058 0, src[0],
2059 BRW_MATH_DATA_VECTOR,
2060 BRW_MATH_PRECISION_FULL);
2061 }
2062 } else {
2063 assert(inst->mlen >= 1);
2064
2065 brw_math(p, dst,
2066 op,
2067 inst->saturate ? BRW_MATH_SATURATE_SATURATE :
2068 BRW_MATH_SATURATE_NONE,
2069 inst->base_mrf, src[0],
2070 BRW_MATH_DATA_VECTOR,
2071 BRW_MATH_PRECISION_FULL);
2072 }
2073 }
2074
2075 void
2076 fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst)
2077 {
2078 int msg_type = -1;
2079 int rlen = 4;
2080 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
2081
2082 if (intel->gen >= 5) {
2083 switch (inst->opcode) {
2084 case FS_OPCODE_TEX:
2085 if (inst->shadow_compare) {
2086 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_COMPARE_GEN5;
2087 } else {
2088 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_GEN5;
2089 }
2090 break;
2091 case FS_OPCODE_TXB:
2092 if (inst->shadow_compare) {
2093 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE_GEN5;
2094 } else {
2095 msg_type = BRW_SAMPLER_MESSAGE_SAMPLE_BIAS_GEN5;
2096 }
2097 break;
2098 }
2099 } else {
2100 switch (inst->opcode) {
2101 case FS_OPCODE_TEX:
2102 /* Note that G45 and older determines shadow compare and dispatch width
2103 * from message length for most messages.
2104 */
2105 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
2106 if (inst->shadow_compare) {
2107 assert(inst->mlen == 6);
2108 } else {
2109 assert(inst->mlen <= 4);
2110 }
2111 break;
2112 case FS_OPCODE_TXB:
2113 if (inst->shadow_compare) {
2114 assert(inst->mlen == 6);
2115 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
2116 } else {
2117 assert(inst->mlen == 9);
2118 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
2119 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
2120 }
2121 break;
2122 }
2123 }
2124 assert(msg_type != -1);
2125
2126 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
2127 rlen = 8;
2128 dst = vec16(dst);
2129 }
2130
2131 brw_SAMPLE(p,
2132 retype(dst, BRW_REGISTER_TYPE_UW),
2133 inst->base_mrf,
2134 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
2135 SURF_INDEX_TEXTURE(inst->sampler),
2136 inst->sampler,
2137 WRITEMASK_XYZW,
2138 msg_type,
2139 rlen,
2140 inst->mlen,
2141 0,
2142 1,
2143 simd_mode);
2144 }
2145
2146
2147 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
2148 * looking like:
2149 *
2150 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
2151 *
2152 * and we're trying to produce:
2153 *
2154 * DDX DDY
2155 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
2156 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
2157 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
2158 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
2159 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
2160 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
2161 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
2162 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
2163 *
2164 * and add another set of two more subspans if in 16-pixel dispatch mode.
2165 *
2166 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
2167 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
2168 * pair. But for DDY, it's harder, as we want to produce the pairs swizzled
2169 * between each other. We could probably do it like ddx and swizzle the right
2170 * order later, but bail for now and just produce
2171 * ((ss0.tl - ss0.bl)x4 (ss1.tl - ss1.bl)x4)
2172 */
2173 void
2174 fs_visitor::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
2175 {
2176 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
2177 BRW_REGISTER_TYPE_F,
2178 BRW_VERTICAL_STRIDE_2,
2179 BRW_WIDTH_2,
2180 BRW_HORIZONTAL_STRIDE_0,
2181 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2182 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
2183 BRW_REGISTER_TYPE_F,
2184 BRW_VERTICAL_STRIDE_2,
2185 BRW_WIDTH_2,
2186 BRW_HORIZONTAL_STRIDE_0,
2187 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2188 brw_ADD(p, dst, src0, negate(src1));
2189 }
2190
2191 void
2192 fs_visitor::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
2193 {
2194 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
2195 BRW_REGISTER_TYPE_F,
2196 BRW_VERTICAL_STRIDE_4,
2197 BRW_WIDTH_4,
2198 BRW_HORIZONTAL_STRIDE_0,
2199 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2200 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
2201 BRW_REGISTER_TYPE_F,
2202 BRW_VERTICAL_STRIDE_4,
2203 BRW_WIDTH_4,
2204 BRW_HORIZONTAL_STRIDE_0,
2205 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
2206 brw_ADD(p, dst, src0, negate(src1));
2207 }
2208
2209 void
2210 fs_visitor::generate_discard_not(fs_inst *inst, struct brw_reg mask)
2211 {
2212 brw_push_insn_state(p);
2213 brw_set_mask_control(p, BRW_MASK_DISABLE);
2214 brw_NOT(p, mask, brw_mask_reg(1)); /* IMASK */
2215 brw_pop_insn_state(p);
2216 }
2217
2218 void
2219 fs_visitor::generate_discard_and(fs_inst *inst, struct brw_reg mask)
2220 {
2221 struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
2222 mask = brw_uw1_reg(mask.file, mask.nr, 0);
2223
2224 brw_push_insn_state(p);
2225 brw_set_mask_control(p, BRW_MASK_DISABLE);
2226 brw_AND(p, g0, mask, g0);
2227 brw_pop_insn_state(p);
2228 }
2229
2230 void
2231 fs_visitor::assign_curb_setup()
2232 {
2233 c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
2234 c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
2235
2236 /* Map the offsets in the UNIFORM file to fixed HW regs. */
2237 foreach_iter(exec_list_iterator, iter, this->instructions) {
2238 fs_inst *inst = (fs_inst *)iter.get();
2239
2240 for (unsigned int i = 0; i < 3; i++) {
2241 if (inst->src[i].file == UNIFORM) {
2242 int constant_nr = inst->src[i].hw_reg + inst->src[i].reg_offset;
2243 struct brw_reg brw_reg = brw_vec1_grf(c->prog_data.first_curbe_grf +
2244 constant_nr / 8,
2245 constant_nr % 8);
2246
2247 inst->src[i].file = FIXED_HW_REG;
2248 inst->src[i].fixed_hw_reg = brw_reg;
2249 }
2250 }
2251 }
2252 }
2253
2254 void
2255 fs_visitor::calculate_urb_setup()
2256 {
2257 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2258 urb_setup[i] = -1;
2259 }
2260
2261 int urb_next = 0;
2262 /* Figure out where each of the incoming setup attributes lands. */
2263 if (intel->gen >= 6) {
2264 for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
2265 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)) {
2266 urb_setup[i] = urb_next++;
2267 }
2268 }
2269 } else {
2270 /* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
2271 for (unsigned int i = 0; i < VERT_RESULT_MAX; i++) {
2272 if (c->key.vp_outputs_written & BITFIELD64_BIT(i)) {
2273 int fp_index;
2274
2275 if (i >= VERT_RESULT_VAR0)
2276 fp_index = i - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
2277 else if (i <= VERT_RESULT_TEX7)
2278 fp_index = i;
2279 else
2280 fp_index = -1;
2281
2282 if (fp_index >= 0)
2283 urb_setup[fp_index] = urb_next++;
2284 }
2285 }
2286 }
2287
2288 /* Each attribute is 4 setup channels, each of which is half a reg. */
2289 c->prog_data.urb_read_length = urb_next * 2;
2290 }
2291
2292 void
2293 fs_visitor::assign_urb_setup()
2294 {
2295 int urb_start = c->prog_data.first_curbe_grf + c->prog_data.curb_read_length;
2296
2297 /* Offset all the urb_setup[] index by the actual position of the
2298 * setup regs, now that the location of the constants has been chosen.
2299 */
2300 foreach_iter(exec_list_iterator, iter, this->instructions) {
2301 fs_inst *inst = (fs_inst *)iter.get();
2302
2303 if (inst->opcode != FS_OPCODE_LINTERP)
2304 continue;
2305
2306 assert(inst->src[2].file == FIXED_HW_REG);
2307
2308 inst->src[2].fixed_hw_reg.nr += urb_start;
2309 }
2310
2311 this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
2312 }
2313
2314 static void
2315 assign_reg(int *reg_hw_locations, fs_reg *reg)
2316 {
2317 if (reg->file == GRF && reg->reg != 0) {
2318 assert(reg->reg_offset >= 0);
2319 reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
2320 reg->reg = 0;
2321 }
2322 }
2323
2324 void
2325 fs_visitor::assign_regs_trivial()
2326 {
2327 int last_grf = 0;
2328 int hw_reg_mapping[this->virtual_grf_next];
2329 int i;
2330
2331 hw_reg_mapping[0] = 0;
2332 hw_reg_mapping[1] = this->first_non_payload_grf;
2333 for (i = 2; i < this->virtual_grf_next; i++) {
2334 hw_reg_mapping[i] = (hw_reg_mapping[i - 1] +
2335 this->virtual_grf_sizes[i - 1]);
2336 }
2337 last_grf = hw_reg_mapping[i - 1] + this->virtual_grf_sizes[i - 1];
2338
2339 foreach_iter(exec_list_iterator, iter, this->instructions) {
2340 fs_inst *inst = (fs_inst *)iter.get();
2341
2342 assign_reg(hw_reg_mapping, &inst->dst);
2343 assign_reg(hw_reg_mapping, &inst->src[0]);
2344 assign_reg(hw_reg_mapping, &inst->src[1]);
2345 }
2346
2347 this->grf_used = last_grf + 1;
2348 }
2349
2350 void
2351 fs_visitor::assign_regs()
2352 {
2353 int last_grf = 0;
2354 int hw_reg_mapping[this->virtual_grf_next + 1];
2355 int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
2356 int class_sizes[base_reg_count];
2357 int class_count = 0;
2358 int aligned_pair_class = -1;
2359
2360 /* Set up the register classes.
2361 *
2362 * The base registers store a scalar value. For texture samples,
2363 * we get virtual GRFs composed of 4 contiguous hw register. For
2364 * structures and arrays, we store them as contiguous larger things
2365 * than that, though we should be able to do better most of the
2366 * time.
2367 */
2368 class_sizes[class_count++] = 1;
2369 if (brw->has_pln && intel->gen < 6) {
2370 /* Always set up the (unaligned) pairs for gen5, so we can find
2371 * them for making the aligned pair class.
2372 */
2373 class_sizes[class_count++] = 2;
2374 }
2375 for (int r = 1; r < this->virtual_grf_next; r++) {
2376 int i;
2377
2378 for (i = 0; i < class_count; i++) {
2379 if (class_sizes[i] == this->virtual_grf_sizes[r])
2380 break;
2381 }
2382 if (i == class_count) {
2383 if (this->virtual_grf_sizes[r] >= base_reg_count) {
2384 fprintf(stderr, "Object too large to register allocate.\n");
2385 this->fail = true;
2386 }
2387
2388 class_sizes[class_count++] = this->virtual_grf_sizes[r];
2389 }
2390 }
2391
2392 int ra_reg_count = 0;
2393 int class_base_reg[class_count];
2394 int class_reg_count[class_count];
2395 int classes[class_count + 1];
2396
2397 for (int i = 0; i < class_count; i++) {
2398 class_base_reg[i] = ra_reg_count;
2399 class_reg_count[i] = base_reg_count - (class_sizes[i] - 1);
2400 ra_reg_count += class_reg_count[i];
2401 }
2402
2403 struct ra_regs *regs = ra_alloc_reg_set(ra_reg_count);
2404 for (int i = 0; i < class_count; i++) {
2405 classes[i] = ra_alloc_reg_class(regs);
2406
2407 for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
2408 ra_class_add_reg(regs, classes[i], class_base_reg[i] + i_r);
2409 }
2410
2411 /* Add conflicts between our contiguous registers aliasing
2412 * base regs and other register classes' contiguous registers
2413 * that alias base regs, or the base regs themselves for classes[0].
2414 */
2415 for (int c = 0; c <= i; c++) {
2416 for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
2417 for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
2418 c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
2419 c_r++) {
2420
2421 if (0) {
2422 printf("%d/%d conflicts %d/%d\n",
2423 class_sizes[i], this->first_non_payload_grf + i_r,
2424 class_sizes[c], this->first_non_payload_grf + c_r);
2425 }
2426
2427 ra_add_reg_conflict(regs,
2428 class_base_reg[i] + i_r,
2429 class_base_reg[c] + c_r);
2430 }
2431 }
2432 }
2433 }
2434
2435 /* Add a special class for aligned pairs, which we'll put delta_x/y
2436 * in on gen5 so that we can do PLN.
2437 */
2438 if (brw->has_pln && intel->gen < 6) {
2439 int reg_count = (base_reg_count - 1) / 2;
2440 int unaligned_pair_class = 1;
2441 assert(class_sizes[unaligned_pair_class] == 2);
2442
2443 aligned_pair_class = class_count;
2444 classes[aligned_pair_class] = ra_alloc_reg_class(regs);
2445 class_sizes[aligned_pair_class] = 2;
2446 class_base_reg[aligned_pair_class] = 0;
2447 class_reg_count[aligned_pair_class] = 0;
2448 int start = (this->first_non_payload_grf & 1) ? 1 : 0;
2449
2450 for (int i = 0; i < reg_count; i++) {
2451 ra_class_add_reg(regs, classes[aligned_pair_class],
2452 class_base_reg[unaligned_pair_class] + i * 2 + start);
2453 }
2454 class_count++;
2455 }
2456
2457 ra_set_finalize(regs);
2458
2459 struct ra_graph *g = ra_alloc_interference_graph(regs,
2460 this->virtual_grf_next);
2461 /* Node 0 is just a placeholder to keep virtual_grf[] mapping 1:1
2462 * with nodes.
2463 */
2464 ra_set_node_class(g, 0, classes[0]);
2465
2466 for (int i = 1; i < this->virtual_grf_next; i++) {
2467 for (int c = 0; c < class_count; c++) {
2468 if (class_sizes[c] == this->virtual_grf_sizes[i]) {
2469 if (aligned_pair_class >= 0 &&
2470 this->delta_x.reg == i) {
2471 ra_set_node_class(g, i, classes[aligned_pair_class]);
2472 } else {
2473 ra_set_node_class(g, i, classes[c]);
2474 }
2475 break;
2476 }
2477 }
2478
2479 for (int j = 1; j < i; j++) {
2480 if (virtual_grf_interferes(i, j)) {
2481 ra_add_node_interference(g, i, j);
2482 }
2483 }
2484 }
2485
2486 /* FINISHME: Handle spilling */
2487 if (!ra_allocate_no_spills(g)) {
2488 fprintf(stderr, "Failed to allocate registers.\n");
2489 this->fail = true;
2490 return;
2491 }
2492
2493 /* Get the chosen virtual registers for each node, and map virtual
2494 * regs in the register classes back down to real hardware reg
2495 * numbers.
2496 */
2497 hw_reg_mapping[0] = 0; /* unused */
2498 for (int i = 1; i < this->virtual_grf_next; i++) {
2499 int reg = ra_get_node_reg(g, i);
2500 int hw_reg = -1;
2501
2502 for (int c = 0; c < class_count; c++) {
2503 if (reg >= class_base_reg[c] &&
2504 reg < class_base_reg[c] + class_reg_count[c]) {
2505 hw_reg = reg - class_base_reg[c];
2506 break;
2507 }
2508 }
2509
2510 assert(hw_reg >= 0);
2511 hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
2512 last_grf = MAX2(last_grf,
2513 hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
2514 }
2515
2516 foreach_iter(exec_list_iterator, iter, this->instructions) {
2517 fs_inst *inst = (fs_inst *)iter.get();
2518
2519 assign_reg(hw_reg_mapping, &inst->dst);
2520 assign_reg(hw_reg_mapping, &inst->src[0]);
2521 assign_reg(hw_reg_mapping, &inst->src[1]);
2522 }
2523
2524 this->grf_used = last_grf + 1;
2525
2526 talloc_free(g);
2527 talloc_free(regs);
2528 }
2529
2530 /**
2531 * Split large virtual GRFs into separate components if we can.
2532 *
2533 * This is mostly duplicated with what brw_fs_vector_splitting does,
2534 * but that's really conservative because it's afraid of doing
2535 * splitting that doesn't result in real progress after the rest of
2536 * the optimization phases, which would cause infinite looping in
2537 * optimization. We can do it once here, safely. This also has the
2538 * opportunity to split interpolated values, or maybe even uniforms,
2539 * which we don't have at the IR level.
2540 *
2541 * We want to split, because virtual GRFs are what we register
2542 * allocate and spill (due to contiguousness requirements for some
2543 * instructions), and they're what we naturally generate in the
2544 * codegen process, but most virtual GRFs don't actually need to be
2545 * contiguous sets of GRFs. If we split, we'll end up with reduced
2546 * live intervals and better dead code elimination and coalescing.
2547 */
2548 void
2549 fs_visitor::split_virtual_grfs()
2550 {
2551 int num_vars = this->virtual_grf_next;
2552 bool split_grf[num_vars];
2553 int new_virtual_grf[num_vars];
2554
2555 /* Try to split anything > 0 sized. */
2556 for (int i = 0; i < num_vars; i++) {
2557 if (this->virtual_grf_sizes[i] != 1)
2558 split_grf[i] = true;
2559 else
2560 split_grf[i] = false;
2561 }
2562
2563 if (brw->has_pln) {
2564 /* PLN opcodes rely on the delta_xy being contiguous. */
2565 split_grf[this->delta_x.reg] = false;
2566 }
2567
2568 foreach_iter(exec_list_iterator, iter, this->instructions) {
2569 fs_inst *inst = (fs_inst *)iter.get();
2570
2571 /* Texturing produces 4 contiguous registers, so no splitting. */
2572 if ((inst->opcode == FS_OPCODE_TEX ||
2573 inst->opcode == FS_OPCODE_TXB ||
2574 inst->opcode == FS_OPCODE_TXL) &&
2575 inst->dst.file == GRF) {
2576 split_grf[inst->dst.reg] = false;
2577 }
2578 }
2579
2580 /* Allocate new space for split regs. Note that the virtual
2581 * numbers will be contiguous.
2582 */
2583 for (int i = 0; i < num_vars; i++) {
2584 if (split_grf[i]) {
2585 new_virtual_grf[i] = virtual_grf_alloc(1);
2586 for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
2587 int reg = virtual_grf_alloc(1);
2588 assert(reg == new_virtual_grf[i] + j - 1);
2589 }
2590 this->virtual_grf_sizes[i] = 1;
2591 }
2592 }
2593
2594 foreach_iter(exec_list_iterator, iter, this->instructions) {
2595 fs_inst *inst = (fs_inst *)iter.get();
2596
2597 if (inst->dst.file == GRF &&
2598 split_grf[inst->dst.reg] &&
2599 inst->dst.reg_offset != 0) {
2600 inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
2601 inst->dst.reg_offset - 1);
2602 inst->dst.reg_offset = 0;
2603 }
2604 for (int i = 0; i < 3; i++) {
2605 if (inst->src[i].file == GRF &&
2606 split_grf[inst->src[i].reg] &&
2607 inst->src[i].reg_offset != 0) {
2608 inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
2609 inst->src[i].reg_offset - 1);
2610 inst->src[i].reg_offset = 0;
2611 }
2612 }
2613 }
2614 }
2615
2616 void
2617 fs_visitor::calculate_live_intervals()
2618 {
2619 int num_vars = this->virtual_grf_next;
2620 int *def = talloc_array(mem_ctx, int, num_vars);
2621 int *use = talloc_array(mem_ctx, int, num_vars);
2622 int loop_depth = 0;
2623 int loop_start = 0;
2624
2625 for (int i = 0; i < num_vars; i++) {
2626 def[i] = 1 << 30;
2627 use[i] = -1;
2628 }
2629
2630 int ip = 0;
2631 foreach_iter(exec_list_iterator, iter, this->instructions) {
2632 fs_inst *inst = (fs_inst *)iter.get();
2633
2634 if (inst->opcode == BRW_OPCODE_DO) {
2635 if (loop_depth++ == 0)
2636 loop_start = ip;
2637 } else if (inst->opcode == BRW_OPCODE_WHILE) {
2638 loop_depth--;
2639
2640 if (loop_depth == 0) {
2641 /* FINISHME:
2642 *
2643 * Patches up any vars marked for use within the loop as
2644 * live until the end. This is conservative, as there
2645 * will often be variables defined and used inside the
2646 * loop but dead at the end of the loop body.
2647 */
2648 for (int i = 0; i < num_vars; i++) {
2649 if (use[i] == loop_start) {
2650 use[i] = ip;
2651 }
2652 }
2653 }
2654 } else {
2655 int eip = ip;
2656
2657 if (loop_depth)
2658 eip = loop_start;
2659
2660 for (unsigned int i = 0; i < 3; i++) {
2661 if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
2662 use[inst->src[i].reg] = MAX2(use[inst->src[i].reg], eip);
2663 }
2664 }
2665 if (inst->dst.file == GRF && inst->dst.reg != 0) {
2666 def[inst->dst.reg] = MIN2(def[inst->dst.reg], eip);
2667 }
2668 }
2669
2670 ip++;
2671 }
2672
2673 talloc_free(this->virtual_grf_def);
2674 talloc_free(this->virtual_grf_use);
2675 this->virtual_grf_def = def;
2676 this->virtual_grf_use = use;
2677 }
2678
2679 /**
2680 * Attempts to move immediate constants into the immediate
2681 * constant slot of following instructions.
2682 *
2683 * Immediate constants are a bit tricky -- they have to be in the last
2684 * operand slot, you can't do abs/negate on them,
2685 */
2686
2687 bool
2688 fs_visitor::propagate_constants()
2689 {
2690 bool progress = false;
2691
2692 foreach_iter(exec_list_iterator, iter, this->instructions) {
2693 fs_inst *inst = (fs_inst *)iter.get();
2694
2695 if (inst->opcode != BRW_OPCODE_MOV ||
2696 inst->predicated ||
2697 inst->dst.file != GRF || inst->src[0].file != IMM ||
2698 inst->dst.type != inst->src[0].type)
2699 continue;
2700
2701 /* Don't bother with cases where we should have had the
2702 * operation on the constant folded in GLSL already.
2703 */
2704 if (inst->saturate)
2705 continue;
2706
2707 /* Found a move of a constant to a GRF. Find anything else using the GRF
2708 * before it's written, and replace it with the constant if we can.
2709 */
2710 exec_list_iterator scan_iter = iter;
2711 scan_iter.next();
2712 for (; scan_iter.has_next(); scan_iter.next()) {
2713 fs_inst *scan_inst = (fs_inst *)scan_iter.get();
2714
2715 if (scan_inst->opcode == BRW_OPCODE_DO ||
2716 scan_inst->opcode == BRW_OPCODE_WHILE ||
2717 scan_inst->opcode == BRW_OPCODE_ELSE ||
2718 scan_inst->opcode == BRW_OPCODE_ENDIF) {
2719 break;
2720 }
2721
2722 for (int i = 2; i >= 0; i--) {
2723 if (scan_inst->src[i].file != GRF ||
2724 scan_inst->src[i].reg != inst->dst.reg ||
2725 scan_inst->src[i].reg_offset != inst->dst.reg_offset)
2726 continue;
2727
2728 /* Don't bother with cases where we should have had the
2729 * operation on the constant folded in GLSL already.
2730 */
2731 if (scan_inst->src[i].negate || scan_inst->src[i].abs)
2732 continue;
2733
2734 switch (scan_inst->opcode) {
2735 case BRW_OPCODE_MOV:
2736 scan_inst->src[i] = inst->src[0];
2737 progress = true;
2738 break;
2739
2740 case BRW_OPCODE_MUL:
2741 case BRW_OPCODE_ADD:
2742 if (i == 1) {
2743 scan_inst->src[i] = inst->src[0];
2744 progress = true;
2745 } else if (i == 0 && scan_inst->src[1].file != IMM) {
2746 /* Fit this constant in by commuting the operands */
2747 scan_inst->src[0] = scan_inst->src[1];
2748 scan_inst->src[1] = inst->src[0];
2749 }
2750 break;
2751 case BRW_OPCODE_CMP:
2752 if (i == 1) {
2753 scan_inst->src[i] = inst->src[0];
2754 progress = true;
2755 }
2756 }
2757 }
2758
2759 if (scan_inst->dst.file == GRF &&
2760 scan_inst->dst.reg == inst->dst.reg &&
2761 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
2762 scan_inst->opcode == FS_OPCODE_TEX)) {
2763 break;
2764 }
2765 }
2766 }
2767
2768 return progress;
2769 }
2770 /**
2771 * Must be called after calculate_live_intervales() to remove unused
2772 * writes to registers -- register allocation will fail otherwise
2773 * because something deffed but not used won't be considered to
2774 * interfere with other regs.
2775 */
2776 bool
2777 fs_visitor::dead_code_eliminate()
2778 {
2779 bool progress = false;
2780 int num_vars = this->virtual_grf_next;
2781 bool dead[num_vars];
2782
2783 for (int i = 0; i < num_vars; i++) {
2784 dead[i] = this->virtual_grf_def[i] >= this->virtual_grf_use[i];
2785
2786 if (dead[i]) {
2787 /* Mark off its interval so it won't interfere with anything. */
2788 this->virtual_grf_def[i] = -1;
2789 this->virtual_grf_use[i] = -1;
2790 }
2791 }
2792
2793 foreach_iter(exec_list_iterator, iter, this->instructions) {
2794 fs_inst *inst = (fs_inst *)iter.get();
2795
2796 if (inst->dst.file == GRF && dead[inst->dst.reg]) {
2797 inst->remove();
2798 progress = true;
2799 }
2800 }
2801
2802 return progress;
2803 }
2804
2805 bool
2806 fs_visitor::register_coalesce()
2807 {
2808 bool progress = false;
2809
2810 foreach_iter(exec_list_iterator, iter, this->instructions) {
2811 fs_inst *inst = (fs_inst *)iter.get();
2812
2813 if (inst->opcode != BRW_OPCODE_MOV ||
2814 inst->predicated ||
2815 inst->saturate ||
2816 inst->dst.file != GRF || inst->src[0].file != GRF ||
2817 inst->dst.type != inst->src[0].type)
2818 continue;
2819
2820 /* Found a move of a GRF to a GRF. Let's see if we can coalesce
2821 * them: check for no writes to either one until the exit of the
2822 * program.
2823 */
2824 bool interfered = false;
2825 exec_list_iterator scan_iter = iter;
2826 scan_iter.next();
2827 for (; scan_iter.has_next(); scan_iter.next()) {
2828 fs_inst *scan_inst = (fs_inst *)scan_iter.get();
2829
2830 if (scan_inst->opcode == BRW_OPCODE_DO ||
2831 scan_inst->opcode == BRW_OPCODE_WHILE ||
2832 scan_inst->opcode == BRW_OPCODE_ENDIF) {
2833 interfered = true;
2834 iter = scan_iter;
2835 break;
2836 }
2837
2838 if (scan_inst->dst.file == GRF) {
2839 if (scan_inst->dst.reg == inst->dst.reg &&
2840 (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
2841 scan_inst->opcode == FS_OPCODE_TEX)) {
2842 interfered = true;
2843 break;
2844 }
2845 if (scan_inst->dst.reg == inst->src[0].reg &&
2846 (scan_inst->dst.reg_offset == inst->src[0].reg_offset ||
2847 scan_inst->opcode == FS_OPCODE_TEX)) {
2848 interfered = true;
2849 break;
2850 }
2851 }
2852 }
2853 if (interfered) {
2854 continue;
2855 }
2856
2857 /* Update live interval so we don't have to recalculate. */
2858 this->virtual_grf_use[inst->src[0].reg] = MAX2(virtual_grf_use[inst->src[0].reg],
2859 virtual_grf_use[inst->dst.reg]);
2860
2861 /* Rewrite the later usage to point at the source of the move to
2862 * be removed.
2863 */
2864 for (exec_list_iterator scan_iter = iter; scan_iter.has_next();
2865 scan_iter.next()) {
2866 fs_inst *scan_inst = (fs_inst *)scan_iter.get();
2867
2868 for (int i = 0; i < 3; i++) {
2869 if (scan_inst->src[i].file == GRF &&
2870 scan_inst->src[i].reg == inst->dst.reg &&
2871 scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
2872 scan_inst->src[i].reg = inst->src[0].reg;
2873 scan_inst->src[i].reg_offset = inst->src[0].reg_offset;
2874 scan_inst->src[i].abs |= inst->src[0].abs;
2875 scan_inst->src[i].negate ^= inst->src[0].negate;
2876 }
2877 }
2878 }
2879
2880 inst->remove();
2881 progress = true;
2882 }
2883
2884 return progress;
2885 }
2886
2887
2888 bool
2889 fs_visitor::compute_to_mrf()
2890 {
2891 bool progress = false;
2892 int next_ip = 0;
2893
2894 foreach_iter(exec_list_iterator, iter, this->instructions) {
2895 fs_inst *inst = (fs_inst *)iter.get();
2896
2897 int ip = next_ip;
2898 next_ip++;
2899
2900 if (inst->opcode != BRW_OPCODE_MOV ||
2901 inst->predicated ||
2902 inst->dst.file != MRF || inst->src[0].file != GRF ||
2903 inst->dst.type != inst->src[0].type ||
2904 inst->src[0].abs || inst->src[0].negate)
2905 continue;
2906
2907 /* Can't compute-to-MRF this GRF if someone else was going to
2908 * read it later.
2909 */
2910 if (this->virtual_grf_use[inst->src[0].reg] > ip)
2911 continue;
2912
2913 /* Found a move of a GRF to a MRF. Let's see if we can go
2914 * rewrite the thing that made this GRF to write into the MRF.
2915 */
2916 bool found = false;
2917 fs_inst *scan_inst;
2918 for (scan_inst = (fs_inst *)inst->prev;
2919 scan_inst->prev != NULL;
2920 scan_inst = (fs_inst *)scan_inst->prev) {
2921 /* We don't handle flow control here. Most computation of
2922 * values that end up in MRFs are shortly before the MRF
2923 * write anyway.
2924 */
2925 if (scan_inst->opcode == BRW_OPCODE_DO ||
2926 scan_inst->opcode == BRW_OPCODE_WHILE ||
2927 scan_inst->opcode == BRW_OPCODE_ENDIF) {
2928 break;
2929 }
2930
2931 /* You can't read from an MRF, so if someone else reads our
2932 * MRF's source GRF that we wanted to rewrite, that stops us.
2933 */
2934 bool interfered = false;
2935 for (int i = 0; i < 3; i++) {
2936 if (scan_inst->src[i].file == GRF &&
2937 scan_inst->src[i].reg == inst->src[0].reg &&
2938 scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
2939 interfered = true;
2940 }
2941 }
2942 if (interfered)
2943 break;
2944
2945 if (scan_inst->dst.file == MRF &&
2946 scan_inst->dst.hw_reg == inst->dst.hw_reg) {
2947 /* Somebody else wrote our MRF here, so we can't can't
2948 * compute-to-MRF before that.
2949 */
2950 break;
2951 }
2952
2953 if (scan_inst->mlen > 0) {
2954 /* Found a SEND instruction, which will do some amount of
2955 * implied write that may overwrite our MRF that we were
2956 * hoping to compute-to-MRF somewhere above it. Nothing
2957 * we have implied-writes more than 2 MRFs from base_mrf,
2958 * though.
2959 */
2960 int implied_write_len = MIN2(scan_inst->mlen, 2);
2961 if (inst->dst.hw_reg >= scan_inst->base_mrf &&
2962 inst->dst.hw_reg < scan_inst->base_mrf + implied_write_len) {
2963 break;
2964 }
2965 }
2966
2967 if (scan_inst->dst.file == GRF &&
2968 scan_inst->dst.reg == inst->src[0].reg) {
2969 /* Found the last thing to write our reg we want to turn
2970 * into a compute-to-MRF.
2971 */
2972
2973 if (scan_inst->opcode == FS_OPCODE_TEX) {
2974 /* texturing writes several continuous regs, so we can't
2975 * compute-to-mrf that.
2976 */
2977 break;
2978 }
2979
2980 /* If it's predicated, it (probably) didn't populate all
2981 * the channels.
2982 */
2983 if (scan_inst->predicated)
2984 break;
2985
2986 /* SEND instructions can't have MRF as a destination. */
2987 if (scan_inst->mlen)
2988 break;
2989
2990 if (intel->gen >= 6) {
2991 /* gen6 math instructions must have the destination be
2992 * GRF, so no compute-to-MRF for them.
2993 */
2994 if (scan_inst->opcode == FS_OPCODE_RCP ||
2995 scan_inst->opcode == FS_OPCODE_RSQ ||
2996 scan_inst->opcode == FS_OPCODE_SQRT ||
2997 scan_inst->opcode == FS_OPCODE_EXP2 ||
2998 scan_inst->opcode == FS_OPCODE_LOG2 ||
2999 scan_inst->opcode == FS_OPCODE_SIN ||
3000 scan_inst->opcode == FS_OPCODE_COS ||
3001 scan_inst->opcode == FS_OPCODE_POW) {
3002 break;
3003 }
3004 }
3005
3006 if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
3007 /* Found the creator of our MRF's source value. */
3008 found = true;
3009 break;
3010 }
3011 }
3012 }
3013 if (found) {
3014 scan_inst->dst.file = MRF;
3015 scan_inst->dst.hw_reg = inst->dst.hw_reg;
3016 scan_inst->saturate |= inst->saturate;
3017 inst->remove();
3018 progress = true;
3019 }
3020 }
3021
3022 return progress;
3023 }
3024
3025 bool
3026 fs_visitor::virtual_grf_interferes(int a, int b)
3027 {
3028 int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
3029 int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
3030
3031 /* For dead code, just check if the def interferes with the other range. */
3032 if (this->virtual_grf_use[a] == -1) {
3033 return (this->virtual_grf_def[a] >= this->virtual_grf_def[b] &&
3034 this->virtual_grf_def[a] < this->virtual_grf_use[b]);
3035 }
3036 if (this->virtual_grf_use[b] == -1) {
3037 return (this->virtual_grf_def[b] >= this->virtual_grf_def[a] &&
3038 this->virtual_grf_def[b] < this->virtual_grf_use[a]);
3039 }
3040
3041 return start < end;
3042 }
3043
3044 static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
3045 {
3046 struct brw_reg brw_reg;
3047
3048 switch (reg->file) {
3049 case GRF:
3050 case ARF:
3051 case MRF:
3052 brw_reg = brw_vec8_reg(reg->file,
3053 reg->hw_reg, 0);
3054 brw_reg = retype(brw_reg, reg->type);
3055 break;
3056 case IMM:
3057 switch (reg->type) {
3058 case BRW_REGISTER_TYPE_F:
3059 brw_reg = brw_imm_f(reg->imm.f);
3060 break;
3061 case BRW_REGISTER_TYPE_D:
3062 brw_reg = brw_imm_d(reg->imm.i);
3063 break;
3064 case BRW_REGISTER_TYPE_UD:
3065 brw_reg = brw_imm_ud(reg->imm.u);
3066 break;
3067 default:
3068 assert(!"not reached");
3069 break;
3070 }
3071 break;
3072 case FIXED_HW_REG:
3073 brw_reg = reg->fixed_hw_reg;
3074 break;
3075 case BAD_FILE:
3076 /* Probably unused. */
3077 brw_reg = brw_null_reg();
3078 break;
3079 case UNIFORM:
3080 assert(!"not reached");
3081 brw_reg = brw_null_reg();
3082 break;
3083 }
3084 if (reg->abs)
3085 brw_reg = brw_abs(brw_reg);
3086 if (reg->negate)
3087 brw_reg = negate(brw_reg);
3088
3089 return brw_reg;
3090 }
3091
3092 void
3093 fs_visitor::generate_code()
3094 {
3095 unsigned int annotation_len = 0;
3096 int last_native_inst = 0;
3097 struct brw_instruction *if_stack[16], *loop_stack[16];
3098 int if_stack_depth = 0, loop_stack_depth = 0;
3099 int if_depth_in_loop[16];
3100
3101 if_depth_in_loop[loop_stack_depth] = 0;
3102
3103 memset(&if_stack, 0, sizeof(if_stack));
3104 foreach_iter(exec_list_iterator, iter, this->instructions) {
3105 fs_inst *inst = (fs_inst *)iter.get();
3106 struct brw_reg src[3], dst;
3107
3108 for (unsigned int i = 0; i < 3; i++) {
3109 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
3110 }
3111 dst = brw_reg_from_fs_reg(&inst->dst);
3112
3113 brw_set_conditionalmod(p, inst->conditional_mod);
3114 brw_set_predicate_control(p, inst->predicated);
3115
3116 switch (inst->opcode) {
3117 case BRW_OPCODE_MOV:
3118 brw_MOV(p, dst, src[0]);
3119 break;
3120 case BRW_OPCODE_ADD:
3121 brw_ADD(p, dst, src[0], src[1]);
3122 break;
3123 case BRW_OPCODE_MUL:
3124 brw_MUL(p, dst, src[0], src[1]);
3125 break;
3126
3127 case BRW_OPCODE_FRC:
3128 brw_FRC(p, dst, src[0]);
3129 break;
3130 case BRW_OPCODE_RNDD:
3131 brw_RNDD(p, dst, src[0]);
3132 break;
3133 case BRW_OPCODE_RNDE:
3134 brw_RNDE(p, dst, src[0]);
3135 break;
3136 case BRW_OPCODE_RNDZ:
3137 brw_RNDZ(p, dst, src[0]);
3138 break;
3139
3140 case BRW_OPCODE_AND:
3141 brw_AND(p, dst, src[0], src[1]);
3142 break;
3143 case BRW_OPCODE_OR:
3144 brw_OR(p, dst, src[0], src[1]);
3145 break;
3146 case BRW_OPCODE_XOR:
3147 brw_XOR(p, dst, src[0], src[1]);
3148 break;
3149 case BRW_OPCODE_NOT:
3150 brw_NOT(p, dst, src[0]);
3151 break;
3152 case BRW_OPCODE_ASR:
3153 brw_ASR(p, dst, src[0], src[1]);
3154 break;
3155 case BRW_OPCODE_SHR:
3156 brw_SHR(p, dst, src[0], src[1]);
3157 break;
3158 case BRW_OPCODE_SHL:
3159 brw_SHL(p, dst, src[0], src[1]);
3160 break;
3161
3162 case BRW_OPCODE_CMP:
3163 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
3164 break;
3165 case BRW_OPCODE_SEL:
3166 brw_SEL(p, dst, src[0], src[1]);
3167 break;
3168
3169 case BRW_OPCODE_IF:
3170 assert(if_stack_depth < 16);
3171 if (inst->src[0].file != BAD_FILE) {
3172 assert(intel->gen >= 6);
3173 if_stack[if_stack_depth] = brw_IF_gen6(p, inst->conditional_mod, src[0], src[1]);
3174 } else {
3175 if_stack[if_stack_depth] = brw_IF(p, BRW_EXECUTE_8);
3176 }
3177 if_depth_in_loop[loop_stack_depth]++;
3178 if_stack_depth++;
3179 break;
3180
3181 case BRW_OPCODE_ELSE:
3182 if_stack[if_stack_depth - 1] =
3183 brw_ELSE(p, if_stack[if_stack_depth - 1]);
3184 break;
3185 case BRW_OPCODE_ENDIF:
3186 if_stack_depth--;
3187 brw_ENDIF(p , if_stack[if_stack_depth]);
3188 if_depth_in_loop[loop_stack_depth]--;
3189 break;
3190
3191 case BRW_OPCODE_DO:
3192 loop_stack[loop_stack_depth++] = brw_DO(p, BRW_EXECUTE_8);
3193 if_depth_in_loop[loop_stack_depth] = 0;
3194 break;
3195
3196 case BRW_OPCODE_BREAK:
3197 brw_BREAK(p, if_depth_in_loop[loop_stack_depth]);
3198 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
3199 break;
3200 case BRW_OPCODE_CONTINUE:
3201 brw_CONT(p, if_depth_in_loop[loop_stack_depth]);
3202 brw_set_predicate_control(p, BRW_PREDICATE_NONE);
3203 break;
3204
3205 case BRW_OPCODE_WHILE: {
3206 struct brw_instruction *inst0, *inst1;
3207 GLuint br = 1;
3208
3209 if (intel->gen >= 5)
3210 br = 2;
3211
3212 assert(loop_stack_depth > 0);
3213 loop_stack_depth--;
3214 inst0 = inst1 = brw_WHILE(p, loop_stack[loop_stack_depth]);
3215 /* patch all the BREAK/CONT instructions from last BGNLOOP */
3216 while (inst0 > loop_stack[loop_stack_depth]) {
3217 inst0--;
3218 if (inst0->header.opcode == BRW_OPCODE_BREAK &&
3219 inst0->bits3.if_else.jump_count == 0) {
3220 inst0->bits3.if_else.jump_count = br * (inst1 - inst0 + 1);
3221 }
3222 else if (inst0->header.opcode == BRW_OPCODE_CONTINUE &&
3223 inst0->bits3.if_else.jump_count == 0) {
3224 inst0->bits3.if_else.jump_count = br * (inst1 - inst0);
3225 }
3226 }
3227 }
3228 break;
3229
3230 case FS_OPCODE_RCP:
3231 case FS_OPCODE_RSQ:
3232 case FS_OPCODE_SQRT:
3233 case FS_OPCODE_EXP2:
3234 case FS_OPCODE_LOG2:
3235 case FS_OPCODE_POW:
3236 case FS_OPCODE_SIN:
3237 case FS_OPCODE_COS:
3238 generate_math(inst, dst, src);
3239 break;
3240 case FS_OPCODE_LINTERP:
3241 generate_linterp(inst, dst, src);
3242 break;
3243 case FS_OPCODE_TEX:
3244 case FS_OPCODE_TXB:
3245 case FS_OPCODE_TXL:
3246 generate_tex(inst, dst);
3247 break;
3248 case FS_OPCODE_DISCARD_NOT:
3249 generate_discard_not(inst, dst);
3250 break;
3251 case FS_OPCODE_DISCARD_AND:
3252 generate_discard_and(inst, src[0]);
3253 break;
3254 case FS_OPCODE_DDX:
3255 generate_ddx(inst, dst, src[0]);
3256 break;
3257 case FS_OPCODE_DDY:
3258 generate_ddy(inst, dst, src[0]);
3259 break;
3260 case FS_OPCODE_FB_WRITE:
3261 generate_fb_write(inst);
3262 break;
3263 default:
3264 if (inst->opcode < (int)ARRAY_SIZE(brw_opcodes)) {
3265 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
3266 brw_opcodes[inst->opcode].name);
3267 } else {
3268 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
3269 }
3270 this->fail = true;
3271 }
3272
3273 if (annotation_len < p->nr_insn) {
3274 annotation_len *= 2;
3275 if (annotation_len < 16)
3276 annotation_len = 16;
3277
3278 this->annotation_string = talloc_realloc(this->mem_ctx,
3279 annotation_string,
3280 const char *,
3281 annotation_len);
3282 this->annotation_ir = talloc_realloc(this->mem_ctx,
3283 annotation_ir,
3284 ir_instruction *,
3285 annotation_len);
3286 }
3287
3288 for (unsigned int i = last_native_inst; i < p->nr_insn; i++) {
3289 this->annotation_string[i] = inst->annotation;
3290 this->annotation_ir[i] = inst->ir;
3291 }
3292 last_native_inst = p->nr_insn;
3293 }
3294 }
3295
3296 GLboolean
3297 brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c)
3298 {
3299 struct brw_compile *p = &c->func;
3300 struct intel_context *intel = &brw->intel;
3301 struct gl_context *ctx = &intel->ctx;
3302 struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
3303
3304 if (!prog)
3305 return GL_FALSE;
3306
3307 struct brw_shader *shader =
3308 (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
3309 if (!shader)
3310 return GL_FALSE;
3311
3312 /* We always use 8-wide mode, at least for now. For one, flow
3313 * control only works in 8-wide. Also, when we're fragment shader
3314 * bound, we're almost always under register pressure as well, so
3315 * 8-wide would save us from the performance cliff of spilling
3316 * regs.
3317 */
3318 c->dispatch_width = 8;
3319
3320 if (INTEL_DEBUG & DEBUG_WM) {
3321 printf("GLSL IR for native fragment shader %d:\n", prog->Name);
3322 _mesa_print_ir(shader->ir, NULL);
3323 printf("\n");
3324 }
3325
3326 /* Now the main event: Visit the shader IR and generate our FS IR for it.
3327 */
3328 fs_visitor v(c, shader);
3329
3330 if (0) {
3331 v.emit_dummy_fs();
3332 } else {
3333 v.calculate_urb_setup();
3334 if (intel->gen < 6)
3335 v.emit_interpolation_setup_gen4();
3336 else
3337 v.emit_interpolation_setup_gen6();
3338
3339 /* Generate FS IR for main(). (the visitor only descends into
3340 * functions called "main").
3341 */
3342 foreach_iter(exec_list_iterator, iter, *shader->ir) {
3343 ir_instruction *ir = (ir_instruction *)iter.get();
3344 v.base_ir = ir;
3345 ir->accept(&v);
3346 }
3347
3348 v.emit_fb_writes();
3349
3350 v.split_virtual_grfs();
3351
3352 v.assign_curb_setup();
3353 v.assign_urb_setup();
3354
3355 bool progress;
3356 do {
3357 progress = false;
3358 v.calculate_live_intervals();
3359 progress = v.propagate_constants() || progress;
3360 progress = v.register_coalesce() || progress;
3361 progress = v.compute_to_mrf() || progress;
3362 progress = v.dead_code_eliminate() || progress;
3363 } while (progress);
3364
3365 if (0)
3366 v.assign_regs_trivial();
3367 else
3368 v.assign_regs();
3369 }
3370
3371 if (!v.fail)
3372 v.generate_code();
3373
3374 assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
3375
3376 if (v.fail)
3377 return GL_FALSE;
3378
3379 if (INTEL_DEBUG & DEBUG_WM) {
3380 const char *last_annotation_string = NULL;
3381 ir_instruction *last_annotation_ir = NULL;
3382
3383 printf("Native code for fragment shader %d:\n", prog->Name);
3384 for (unsigned int i = 0; i < p->nr_insn; i++) {
3385 if (last_annotation_ir != v.annotation_ir[i]) {
3386 last_annotation_ir = v.annotation_ir[i];
3387 if (last_annotation_ir) {
3388 printf(" ");
3389 last_annotation_ir->print();
3390 printf("\n");
3391 }
3392 }
3393 if (last_annotation_string != v.annotation_string[i]) {
3394 last_annotation_string = v.annotation_string[i];
3395 if (last_annotation_string)
3396 printf(" %s\n", last_annotation_string);
3397 }
3398 if (0) {
3399 printf("0x%08x 0x%08x 0x%08x 0x%08x ",
3400 ((uint32_t *)&p->store[i])[3],
3401 ((uint32_t *)&p->store[i])[2],
3402 ((uint32_t *)&p->store[i])[1],
3403 ((uint32_t *)&p->store[i])[0]);
3404 }
3405 brw_disasm(stdout, &p->store[i], intel->gen);
3406 }
3407 printf("\n");
3408 }
3409
3410 c->prog_data.total_grf = v.grf_used;
3411 c->prog_data.total_scratch = 0;
3412
3413 return GL_TRUE;
3414 }