src/mesa/drivers/dri/i965/brw_fs.h

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #pragma once
  29
  30 #include "brw_shader.h"
  31
  32 extern "C" {
  33
  34 #include <sys/types.h>
  35
  36 #include "main/macros.h"
  37 #include "main/shaderobj.h"
  38 #include "main/uniforms.h"
  39 #include "program/prog_parameter.h"
  40 #include "program/prog_print.h"
  41 #include "program/prog_optimize.h"
  42 #include "util/register_allocate.h"
  43 #include "program/sampler.h"
  44 #include "program/hash_table.h"
  45 #include "brw_context.h"
  46 #include "brw_eu.h"
  47 #include "brw_wm.h"
  48 #include "brw_shader.h"
  49 #include "intel_asm_annotation.h"
  50 }
  51 #include "glsl/glsl_types.h"
  52 #include "glsl/ir.h"
  53
  54 #define MAX_SAMPLER_MESSAGE_SIZE 11
  55 #define MAX_VGRF_SIZE 16
  56
  57 struct bblock_t;
  58 namespace {
  59    struct acp_entry;
  60 }
  61
  62 namespace brw {
  63    class fs_live_variables;
  64 }
  65
  66 class fs_inst;
  67 class fs_visitor;
  68
  69 class fs_reg : public backend_reg {
  70 public:
  71    DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
  72
  73    void init();
  74
  75    fs_reg();
  76    explicit fs_reg(float f);
  77    explicit fs_reg(int32_t i);
  78    explicit fs_reg(uint32_t u);
  79    explicit fs_reg(uint8_t vf[4]);
  80    explicit fs_reg(uint8_t vf0, uint8_t vf1, uint8_t vf2, uint8_t vf3);
  81    fs_reg(struct brw_reg fixed_hw_reg);
  82    fs_reg(enum register_file file, int reg);
  83    fs_reg(enum register_file file, int reg, enum brw_reg_type type);
  84    fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
  85    fs_reg(fs_visitor *v, const struct glsl_type *type);
  86
  87    bool equals(const fs_reg &r) const;
  88    bool is_contiguous() const;
  89
  90    /** Smear a channel of the reg to all channels. */
  91    fs_reg &set_smear(unsigned subreg);
  92
  93    /**
  94     * Offset in bytes from the start of the register.  Values up to a
  95     * backend_reg::reg_offset unit are valid.
  96     */
  97    int subreg_offset;
  98
  99    fs_reg *reladdr;
 100
 101    /**
 102     * The register width.  This indicates how many hardware values are
 103     * represented by each virtual value.  Valid values are 1, 8, or 16.
 104     * For immediate values, this is 1.  Most of the rest of the time, it
 105     * will be equal to the dispatch width.
 106     */
 107    uint8_t width;
 108
 109    /**
 110     * Returns the effective register width when used as a source in the
 111     * given instruction.  Registers such as uniforms and immediates
 112     * effectively take on the width of the instruction in which they are
 113     * used.
 114     */
 115    uint8_t effective_width;
 116
 117    /** Register region horizontal stride */
 118    uint8_t stride;
 119 };
 120
 121 static inline fs_reg
 122 negate(fs_reg reg)
 123 {
 124    assert(reg.file != HW_REG && reg.file != IMM);
 125    reg.negate = !reg.negate;
 126    return reg;
 127 }
 128
 129 static inline fs_reg
 130 retype(fs_reg reg, enum brw_reg_type type)
 131 {
 132    reg.fixed_hw_reg.type = reg.type = type;
 133    return reg;
 134 }
 135
 136 static inline fs_reg
 137 byte_offset(fs_reg reg, unsigned delta)
 138 {
 139    switch (reg.file) {
 140    case BAD_FILE:
 141       break;
 142    case GRF:
 143       reg.reg_offset += delta / 32;
 144       break;
 145    case MRF:
 146       reg.reg += delta / 32;
 147       break;
 148    default:
 149       assert(delta == 0);
 150    }
 151    reg.subreg_offset += delta % 32;
 152    return reg;
 153 }
 154
 155 static inline fs_reg
 156 horiz_offset(fs_reg reg, unsigned delta)
 157 {
 158    switch (reg.file) {
 159    case BAD_FILE:
 160    case UNIFORM:
 161    case IMM:
 162       /* These only have a single component that is implicitly splatted.  A
 163        * horizontal offset should be a harmless no-op.
 164        */
 165       break;
 166    case GRF:
 167    case MRF:
 168       return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
 169    default:
 170       assert(delta == 0);
 171    }
 172    return reg;
 173 }
 174
 175 static inline fs_reg
 176 offset(fs_reg reg, unsigned delta)
 177 {
 178    assert(reg.stride > 0);
 179    switch (reg.file) {
 180    case BAD_FILE:
 181       break;
 182    case GRF:
 183    case MRF:
 184       return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
 185    case UNIFORM:
 186       reg.reg_offset += delta;
 187       break;
 188    default:
 189       assert(delta == 0);
 190    }
 191    return reg;
 192 }
 193
 194 static inline fs_reg
 195 component(fs_reg reg, unsigned idx)
 196 {
 197    assert(reg.subreg_offset == 0);
 198    assert(idx < reg.width);
 199    reg.subreg_offset = idx * type_sz(reg.type);
 200    reg.width = 1;
 201    return reg;
 202 }
 203
 204 /**
 205  * Get either of the 8-component halves of a 16-component register.
 206  *
 207  * Note: this also works if \c reg represents a SIMD16 pair of registers.
 208  */
 209 static inline fs_reg
 210 half(fs_reg reg, unsigned idx)
 211 {
 212    assert(idx < 2);
 213
 214    if (reg.file == UNIFORM)
 215       return reg;
 216
 217    assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
 218    assert(reg.width == 16);
 219    reg.width = 8;
 220    return horiz_offset(reg, 8 * idx);
 221 }
 222
 223 static const fs_reg reg_undef;
 224
 225 class fs_inst : public backend_instruction {
 226    fs_inst &operator=(const fs_inst &);
 227
 228    void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
 229              fs_reg *src, int sources);
 230
 231 public:
 232    DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
 233
 234    fs_inst();
 235    fs_inst(enum opcode opcode, uint8_t exec_size);
 236    fs_inst(enum opcode opcode, const fs_reg &dst);
 237    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 238            const fs_reg &src0);
 239    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 240    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 241            const fs_reg &src0, const fs_reg &src1);
 242    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 243            const fs_reg &src1);
 244    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 245            const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 246    fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 247            const fs_reg &src1, const fs_reg &src2);
 248    fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
 249    fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
 250            fs_reg src[], int sources);
 251    fs_inst(const fs_inst &that);
 252
 253    void resize_sources(uint8_t num_sources);
 254
 255    bool equals(fs_inst *inst) const;
 256    bool overwrites_reg(const fs_reg &reg) const;
 257    bool is_send_from_grf() const;
 258    bool is_partial_write() const;
 259    int regs_read(fs_visitor *v, int arg) const;
 260    bool can_do_source_mods(struct brw_context *brw);
 261
 262    bool reads_flag() const;
 263    bool writes_flag() const;
 264
 265    fs_reg dst;
 266    fs_reg *src;
 267
 268    uint8_t sources; /**< Number of fs_reg sources. */
 269
 270    /**
 271     * Execution size of the instruction.  This is used by the generator to
 272     * generate the correct binary for the given fs_inst.  Current valid
 273     * values are 1, 8, 16.
 274     */
 275    uint8_t exec_size;
 276
 277    /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
 278     * mod and predication.
 279     */
 280    uint8_t flag_subreg;
 281
 282    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
 283    bool eot:1;
 284    bool force_uncompressed:1;
 285    bool force_sechalf:1;
 286    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 287 };
 288
 289 /**
 290  * The fragment shader front-end.
 291  *
 292  * Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
 293  */
 294 class fs_visitor : public backend_visitor
 295 {
 296 public:
 297    const fs_reg reg_null_f;
 298    const fs_reg reg_null_d;
 299    const fs_reg reg_null_ud;
 300
 301    fs_visitor(struct brw_context *brw,
 302               void *mem_ctx,
 303               const struct brw_wm_prog_key *key,
 304               struct brw_wm_prog_data *prog_data,
 305               struct gl_shader_program *shader_prog,
 306               struct gl_fragment_program *fp,
 307               unsigned dispatch_width);
 308    ~fs_visitor();
 309    void init();
 310
 311    fs_reg *variable_storage(ir_variable *var);
 312    int virtual_grf_alloc(int size);
 313    void import_uniforms(fs_visitor *v);
 314
 315    void visit(ir_variable *ir);
 316    void visit(ir_assignment *ir);
 317    void visit(ir_dereference_variable *ir);
 318    void visit(ir_dereference_record *ir);
 319    void visit(ir_dereference_array *ir);
 320    void visit(ir_expression *ir);
 321    void visit(ir_texture *ir);
 322    void visit(ir_if *ir);
 323    void visit(ir_constant *ir);
 324    void visit(ir_swizzle *ir);
 325    void visit(ir_return *ir);
 326    void visit(ir_loop *ir);
 327    void visit(ir_loop_jump *ir);
 328    void visit(ir_discard *ir);
 329    void visit(ir_call *ir);
 330    void visit(ir_function *ir);
 331    void visit(ir_function_signature *ir);
 332    void visit(ir_emit_vertex *);
 333    void visit(ir_end_primitive *);
 334
 335    uint32_t gather_channel(int orig_chan, uint32_t sampler);
 336    void swizzle_result(ir_texture_opcode op, int dest_components,
 337                        fs_reg orig_val, uint32_t sampler);
 338
 339    fs_inst *emit(fs_inst *inst);
 340    void emit(exec_list list);
 341
 342    fs_inst *emit(enum opcode opcode);
 343    fs_inst *emit(enum opcode opcode, const fs_reg &dst);
 344    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
 345    fs_inst *emit(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
 346                  const fs_reg &src1);
 347    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 348                  const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
 349    fs_inst *emit(enum opcode opcode, const fs_reg &dst,
 350                  fs_reg src[], int sources);
 351
 352    fs_inst *MOV(const fs_reg &dst, const fs_reg &src);
 353    fs_inst *NOT(const fs_reg &dst, const fs_reg &src);
 354    fs_inst *RNDD(const fs_reg &dst, const fs_reg &src);
 355    fs_inst *RNDE(const fs_reg &dst, const fs_reg &src);
 356    fs_inst *RNDZ(const fs_reg &dst, const fs_reg &src);
 357    fs_inst *FRC(const fs_reg &dst, const fs_reg &src);
 358    fs_inst *ADD(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 359    fs_inst *MUL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 360    fs_inst *MACH(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 361    fs_inst *MAC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 362    fs_inst *SHL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 363    fs_inst *SHR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 364    fs_inst *ASR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 365    fs_inst *AND(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 366    fs_inst *OR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 367    fs_inst *XOR(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 368    fs_inst *IF(enum brw_predicate predicate);
 369    fs_inst *IF(const fs_reg &src0, const fs_reg &src1,
 370                enum brw_conditional_mod condition);
 371    fs_inst *CMP(fs_reg dst, fs_reg src0, fs_reg src1,
 372                 enum brw_conditional_mod condition);
 373    fs_inst *LRP(const fs_reg &dst, const fs_reg &a, const fs_reg &y,
 374                 const fs_reg &x);
 375    fs_inst *DEP_RESOLVE_MOV(int grf);
 376    fs_inst *BFREV(const fs_reg &dst, const fs_reg &value);
 377    fs_inst *BFE(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset,
 378                 const fs_reg &value);
 379    fs_inst *BFI1(const fs_reg &dst, const fs_reg &bits, const fs_reg &offset);
 380    fs_inst *BFI2(const fs_reg &dst, const fs_reg &bfi1_dst,
 381                  const fs_reg &insert, const fs_reg &base);
 382    fs_inst *FBH(const fs_reg &dst, const fs_reg &value);
 383    fs_inst *FBL(const fs_reg &dst, const fs_reg &value);
 384    fs_inst *CBIT(const fs_reg &dst, const fs_reg &value);
 385    fs_inst *MAD(const fs_reg &dst, const fs_reg &c, const fs_reg &b,
 386                 const fs_reg &a);
 387    fs_inst *ADDC(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 388    fs_inst *SUBB(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 389    fs_inst *SEL(const fs_reg &dst, const fs_reg &src0, const fs_reg &src1);
 390
 391    int type_size(const struct glsl_type *type);
 392    fs_inst *get_instruction_generating_reg(fs_inst *start,
 393                                            fs_inst *end,
 394                                            const fs_reg &reg);
 395
 396    fs_inst *LOAD_PAYLOAD(const fs_reg &dst, fs_reg *src, int sources);
 397
 398    exec_list VARYING_PULL_CONSTANT_LOAD(const fs_reg &dst,
 399                                         const fs_reg &surf_index,
 400                                         const fs_reg &varying_offset,
 401                                         uint32_t const_offset);
 402
 403    bool run();
 404    void optimize();
 405    void allocate_registers();
 406    void assign_binding_table_offsets();
 407    void setup_payload_gen4();
 408    void setup_payload_gen6();
 409    void assign_curb_setup();
 410    void calculate_urb_setup();
 411    void assign_urb_setup();
 412    bool assign_regs(bool allow_spilling);
 413    void assign_regs_trivial();
 414    void get_used_mrfs(bool *mrf_used);
 415    void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
 416                                    int first_payload_node);
 417    void setup_mrf_hack_interference(struct ra_graph *g,
 418                                     int first_mrf_hack_node);
 419    int choose_spill_reg(struct ra_graph *g);
 420    void spill_reg(int spill_reg);
 421    void split_virtual_grfs();
 422    bool compact_virtual_grfs();
 423    void move_uniform_array_access_to_pull_constants();
 424    void assign_constant_locations();
 425    void demote_pull_constants();
 426    void invalidate_live_intervals();
 427    void calculate_live_intervals();
 428    void calculate_register_pressure();
 429    bool opt_algebraic();
 430    bool opt_cse();
 431    bool opt_cse_local(bblock_t *block);
 432    bool opt_copy_propagate();
 433    bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
 434    bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
 435    bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
 436                                  exec_list *acp);
 437    bool opt_register_renaming();
 438    bool register_coalesce();
 439    bool compute_to_mrf();
 440    bool dead_code_eliminate();
 441    bool remove_duplicate_mrf_writes();
 442    bool virtual_grf_interferes(int a, int b);
 443    void schedule_instructions(instruction_scheduler_mode mode);
 444    void insert_gen4_send_dependency_workarounds();
 445    void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
 446                                                     fs_inst *inst);
 447    void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
 448                                                      fs_inst *inst);
 449    void vfail(const char *msg, va_list args);
 450    void fail(const char *msg, ...);
 451    void no16(const char *msg, ...);
 452    void lower_uniform_pull_constant_loads();
 453    bool lower_load_payload();
 454
 455    void emit_dummy_fs();
 456    void emit_repclear_shader();
 457    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
 458    fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
 459                          glsl_interp_qualifier interpolation_mode,
 460                          bool is_centroid, bool is_sample);
 461    fs_reg *emit_frontfacing_interpolation();
 462    fs_reg *emit_samplepos_setup();
 463    fs_reg *emit_sampleid_setup();
 464    fs_reg *emit_general_interpolation(ir_variable *ir);
 465    void emit_interpolation_setup_gen4();
 466    void emit_interpolation_setup_gen6();
 467    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
 468    fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
 469                            bool is_rect, uint32_t sampler, int texunit);
 470    fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
 471                               fs_reg coordinate, int coord_components,
 472                               fs_reg shadow_comp,
 473                               fs_reg lod, fs_reg lod2, int grad_components,
 474                               uint32_t sampler);
 475    fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
 476                               fs_reg coordinate, int coord_components,
 477                               fs_reg shadow_comp,
 478                               fs_reg lod, fs_reg lod2, int grad_components,
 479                               fs_reg sample_index, uint32_t sampler,
 480                               bool has_offset);
 481    fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
 482                               fs_reg coordinate, int coord_components,
 483                               fs_reg shadow_comp,
 484                               fs_reg lod, fs_reg lod2, int grad_components,
 485                               fs_reg sample_index, fs_reg mcs, fs_reg sampler,
 486                               fs_reg offset_value);
 487    void emit_texture(ir_texture_opcode op,
 488                      const glsl_type *dest_type,
 489                      fs_reg coordinate, const struct glsl_type *coord_type,
 490                      fs_reg shadow_c,
 491                      fs_reg lod, fs_reg dpdy, int grad_components,
 492                      fs_reg sample_index,
 493                      fs_reg offset, unsigned offset_components,
 494                      fs_reg mcs,
 495                      int gather_component,
 496                      bool is_cube_array,
 497                      bool is_rect,
 498                      uint32_t sampler,
 499                      fs_reg sampler_reg,
 500                      int texunit);
 501    fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
 502    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
 503    fs_reg fix_math_operand(fs_reg src);
 504    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
 505    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
 506    void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
 507                  const fs_reg &a);
 508    void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
 509                     const fs_reg &src0, const fs_reg &src1);
 510    bool try_emit_saturate(ir_expression *ir);
 511    bool try_emit_mad(ir_expression *ir);
 512    void try_replace_with_sel();
 513    bool opt_peephole_sel();
 514    bool opt_peephole_predicated_break();
 515    bool opt_saturate_propagation();
 516    void emit_bool_to_cond_code(ir_rvalue *condition);
 517    void emit_if_gen6(ir_if *ir);
 518    void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
 519                      uint32_t spill_offset, int count);
 520    void emit_spill(bblock_t *block, fs_inst *inst, fs_reg reg,
 521                    uint32_t spill_offset, int count);
 522
 523    void emit_fragment_program_code();
 524    void setup_fp_regs();
 525    fs_reg get_fp_src_reg(const prog_src_register *src);
 526    fs_reg get_fp_dst_reg(const prog_dst_register *dst);
 527    void emit_fp_alu1(enum opcode opcode,
 528                      const struct prog_instruction *fpi,
 529                      fs_reg dst, fs_reg src);
 530    void emit_fp_alu2(enum opcode opcode,
 531                      const struct prog_instruction *fpi,
 532                      fs_reg dst, fs_reg src0, fs_reg src1);
 533    void emit_fp_scalar_write(const struct prog_instruction *fpi,
 534                              fs_reg dst, fs_reg src);
 535    void emit_fp_scalar_math(enum opcode opcode,
 536                             const struct prog_instruction *fpi,
 537                             fs_reg dst, fs_reg src);
 538
 539    void emit_fp_minmax(const struct prog_instruction *fpi,
 540                        fs_reg dst, fs_reg src0, fs_reg src1);
 541
 542    void emit_fp_sop(enum brw_conditional_mod conditional_mod,
 543                     const struct prog_instruction *fpi,
 544                     fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
 545
 546    int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
 547    void emit_alpha_test();
 548    fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
 549                                  fs_reg src0_alpha, unsigned components);
 550    void emit_fb_writes();
 551
 552    void emit_shader_time_begin();
 553    void emit_shader_time_end();
 554    void emit_shader_time_write(enum shader_time_shader_type type,
 555                                fs_reg value);
 556
 557    void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
 558                             fs_reg dst, fs_reg offset, fs_reg src0,
 559                             fs_reg src1);
 560
 561    void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
 562                                   fs_reg offset);
 563
 564    void emit_interpolate_expression(ir_expression *ir);
 565
 566    bool try_rewrite_rhs_to_dst(ir_assignment *ir,
 567                                fs_reg dst,
 568                                fs_reg src,
 569                                fs_inst *pre_rhs_inst,
 570                                fs_inst *last_rhs_inst);
 571    void emit_assignment_writes(fs_reg &l, fs_reg &r,
 572                                const glsl_type *type, bool predicated);
 573    void resolve_ud_negate(fs_reg *reg);
 574    void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
 575
 576    fs_reg get_timestamp();
 577
 578    struct brw_reg interp_reg(int location, int channel);
 579    void setup_uniform_values(ir_variable *ir);
 580    void setup_builtin_uniform_values(ir_variable *ir);
 581    int implied_mrf_writes(fs_inst *inst);
 582
 583    virtual void dump_instructions();
 584    virtual void dump_instructions(const char *name);
 585    void dump_instruction(backend_instruction *inst);
 586    void dump_instruction(backend_instruction *inst, FILE *file);
 587
 588    void visit_atomic_counter_intrinsic(ir_call *ir);
 589
 590    const void *const key;
 591    struct brw_stage_prog_data *prog_data;
 592    unsigned int sanity_param_count;
 593
 594    int *param_size;
 595
 596    int *virtual_grf_sizes;
 597    int virtual_grf_count;
 598    int virtual_grf_array_size;
 599    int *virtual_grf_start;
 600    int *virtual_grf_end;
 601    brw::fs_live_variables *live_intervals;
 602
 603    int *regs_live_at_ip;
 604
 605    /** Number of uniform variable components visited. */
 606    unsigned uniforms;
 607
 608    /** Byte-offset for the next available spot in the scratch space buffer. */
 609    unsigned last_scratch;
 610
 611    /**
 612     * Array mapping UNIFORM register numbers to the pull parameter index,
 613     * or -1 if this uniform register isn't being uploaded as a pull constant.
 614     */
 615    int *pull_constant_loc;
 616
 617    /**
 618     * Array mapping UNIFORM register numbers to the push parameter index,
 619     * or -1 if this uniform register isn't being uploaded as a push constant.
 620     */
 621    int *push_constant_loc;
 622
 623    struct hash_table *variable_ht;
 624    fs_reg frag_depth;
 625    fs_reg sample_mask;
 626    fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
 627    unsigned output_components[BRW_MAX_DRAW_BUFFERS];
 628    fs_reg dual_src_output;
 629    bool do_dual_src;
 630    int first_non_payload_grf;
 631    /** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
 632    int max_grf;
 633
 634    fs_reg *fp_temp_regs;
 635    fs_reg *fp_input_regs;
 636
 637    /** @{ debug annotation info */
 638    const char *current_annotation;
 639    const void *base_ir;
 640    /** @} */
 641
 642    bool failed;
 643    char *fail_msg;
 644    bool simd16_unsupported;
 645    char *no16_msg;
 646
 647    /* Result of last visit() method. */
 648    fs_reg result;
 649
 650    /** Register numbers for thread payload fields. */
 651    struct {
 652       uint8_t source_depth_reg;
 653       uint8_t source_w_reg;
 654       uint8_t aa_dest_stencil_reg;
 655       uint8_t dest_depth_reg;
 656       uint8_t sample_pos_reg;
 657       uint8_t sample_mask_in_reg;
 658       uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 659
 660       /** The number of thread payload registers the hardware will supply. */
 661       uint8_t num_regs;
 662    } payload;
 663
 664    bool source_depth_to_render_target;
 665    bool runtime_check_aads_emit;
 666
 667    fs_reg pixel_x;
 668    fs_reg pixel_y;
 669    fs_reg wpos_w;
 670    fs_reg pixel_w;
 671    fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 672    fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
 673    fs_reg shader_start_time;
 674
 675    int grf_used;
 676    bool spilled_any_registers;
 677
 678    const unsigned dispatch_width; /**< 8 or 16 */
 679 };
 680
 681 /**
 682  * The fragment shader code generator.
 683  *
 684  * Translates FS IR to actual i965 assembly code.
 685  */
 686 class fs_generator
 687 {
 688 public:
 689    fs_generator(struct brw_context *brw,
 690                 void *mem_ctx,
 691                 const struct brw_wm_prog_key *key,
 692                 struct brw_wm_prog_data *prog_data,
 693                 struct gl_shader_program *shader_prog,
 694                 struct gl_fragment_program *fp,
 695                 bool runtime_check_aads_emit,
 696                 bool debug_flag);
 697    ~fs_generator();
 698
 699    int generate_code(const cfg_t *cfg, int dispatch_width);
 700    const unsigned *get_assembly(unsigned int *assembly_size);
 701
 702 private:
 703    void fire_fb_write(fs_inst *inst,
 704                       struct brw_reg payload,
 705                       struct brw_reg implied_header,
 706                       GLuint nr);
 707    void generate_fb_write(fs_inst *inst, struct brw_reg payload);
 708    void generate_blorp_fb_write(fs_inst *inst);
 709    void generate_pixel_xy(struct brw_reg dst, bool is_x);
 710    void generate_linterp(fs_inst *inst, struct brw_reg dst,
 711                          struct brw_reg *src);
 712    void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
 713                      struct brw_reg sampler_index);
 714    void generate_math_gen6(fs_inst *inst,
 715                            struct brw_reg dst,
 716                            struct brw_reg src0,
 717                            struct brw_reg src1);
 718    void generate_math_gen4(fs_inst *inst,
 719                            struct brw_reg dst,
 720                            struct brw_reg src);
 721    void generate_math_g45(fs_inst *inst,
 722                           struct brw_reg dst,
 723                           struct brw_reg src);
 724    void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
 725    void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
 726                      bool negate_value);
 727    void generate_scratch_write(fs_inst *inst, struct brw_reg src);
 728    void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
 729    void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
 730    void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 731                                             struct brw_reg index,
 732                                             struct brw_reg offset);
 733    void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
 734                                                  struct brw_reg dst,
 735                                                  struct brw_reg surf_index,
 736                                                  struct brw_reg offset);
 737    void generate_varying_pull_constant_load(fs_inst *inst, struct brw_reg dst,
 738                                             struct brw_reg index,
 739                                             struct brw_reg offset);
 740    void generate_varying_pull_constant_load_gen7(fs_inst *inst,
 741                                                  struct brw_reg dst,
 742                                                  struct brw_reg index,
 743                                                  struct brw_reg offset);
 744    void generate_mov_dispatch_to_flags(fs_inst *inst);
 745
 746    void generate_pixel_interpolator_query(fs_inst *inst,
 747                                           struct brw_reg dst,
 748                                           struct brw_reg src,
 749                                           struct brw_reg msg_data,
 750                                           unsigned msg_type);
 751
 752    void generate_set_omask(fs_inst *inst,
 753                            struct brw_reg dst,
 754                            struct brw_reg sample_mask);
 755
 756    void generate_set_sample_id(fs_inst *inst,
 757                                struct brw_reg dst,
 758                                struct brw_reg src0,
 759                                struct brw_reg src1);
 760
 761    void generate_set_simd4x2_offset(fs_inst *inst,
 762                                     struct brw_reg dst,
 763                                     struct brw_reg offset);
 764    void generate_discard_jump(fs_inst *inst);
 765
 766    void generate_pack_half_2x16_split(fs_inst *inst,
 767                                       struct brw_reg dst,
 768                                       struct brw_reg x,
 769                                       struct brw_reg y);
 770    void generate_unpack_half_2x16_split(fs_inst *inst,
 771                                         struct brw_reg dst,
 772                                         struct brw_reg src);
 773
 774    void generate_shader_time_add(fs_inst *inst,
 775                                  struct brw_reg payload,
 776                                  struct brw_reg offset,
 777                                  struct brw_reg value);
 778
 779    void generate_untyped_atomic(fs_inst *inst,
 780                                 struct brw_reg dst,
 781                                 struct brw_reg payload,
 782                                 struct brw_reg atomic_op,
 783                                 struct brw_reg surf_index);
 784
 785    void generate_untyped_surface_read(fs_inst *inst,
 786                                       struct brw_reg dst,
 787                                       struct brw_reg payload,
 788                                       struct brw_reg surf_index);
 789
 790    bool patch_discard_jumps_to_fb_writes();
 791
 792    struct brw_context *brw;
 793    struct gl_context *ctx;
 794
 795    struct brw_compile *p;
 796    gl_shader_stage stage;
 797    const void * const key;
 798    struct brw_stage_prog_data * const prog_data;
 799
 800    struct gl_shader_program * const shader_prog;
 801    const struct gl_program *prog;
 802
 803    unsigned dispatch_width; /**< 8 or 16 */
 804
 805    exec_list discard_halt_patches;
 806    bool runtime_check_aads_emit;
 807    const bool debug_flag;
 808    void *mem_ctx;
 809 };
 810
 811 bool brw_do_channel_expressions(struct exec_list *instructions);
 812 bool brw_do_vector_splitting(struct exec_list *instructions);
 813
 814 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);