src/mesa/drivers/dri/i965/brw_fs_cse.cpp

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "brw_fs.h"
  25 #include "brw_cfg.h"
  26
  27 /** @file brw_fs_cse.cpp
  28  *
  29  * Support for local common subexpression elimination.
  30  *
  31  * See Muchnick's Advanced Compiler Design and Implementation, section
  32  * 13.1 (p378).
  33  */
  34
  35 namespace {
  36 struct aeb_entry : public exec_node {
  37    /** The instruction that generates the expression value. */
  38    fs_inst *generator;
  39
  40    /** The temporary where the value is stored. */
  41    fs_reg tmp;
  42 };
  43 }
  44
  45 static bool
  46 is_copy_payload(const fs_inst *inst)
  47 {
  48    const int reg = inst->src[0].reg;
  49    if (inst->src[0].reg_offset != 0)
  50       return false;
  51
  52    for (int i = 1; i < inst->sources; i++) {
  53       if (inst->src[i].reg != reg ||
  54           inst->src[i].reg_offset != i) {
  55          return false;
  56       }
  57    }
  58    return true;
  59 }
  60
  61 static bool
  62 is_expression(const fs_inst *const inst)
  63 {
  64    switch (inst->opcode) {
  65    case BRW_OPCODE_MOV:
  66    case BRW_OPCODE_SEL:
  67    case BRW_OPCODE_NOT:
  68    case BRW_OPCODE_AND:
  69    case BRW_OPCODE_OR:
  70    case BRW_OPCODE_XOR:
  71    case BRW_OPCODE_SHR:
  72    case BRW_OPCODE_SHL:
  73    case BRW_OPCODE_ASR:
  74    case BRW_OPCODE_CMP:
  75    case BRW_OPCODE_CMPN:
  76    case BRW_OPCODE_ADD:
  77    case BRW_OPCODE_MUL:
  78    case BRW_OPCODE_FRC:
  79    case BRW_OPCODE_RNDU:
  80    case BRW_OPCODE_RNDD:
  81    case BRW_OPCODE_RNDE:
  82    case BRW_OPCODE_RNDZ:
  83    case BRW_OPCODE_LINE:
  84    case BRW_OPCODE_PLN:
  85    case BRW_OPCODE_MAD:
  86    case BRW_OPCODE_LRP:
  87    case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
  88    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
  89    case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
  90    case FS_OPCODE_CINTERP:
  91    case FS_OPCODE_LINTERP:
  92       return true;
  93    case SHADER_OPCODE_RCP:
  94    case SHADER_OPCODE_RSQ:
  95    case SHADER_OPCODE_SQRT:
  96    case SHADER_OPCODE_EXP2:
  97    case SHADER_OPCODE_LOG2:
  98    case SHADER_OPCODE_POW:
  99    case SHADER_OPCODE_INT_QUOTIENT:
 100    case SHADER_OPCODE_INT_REMAINDER:
 101    case SHADER_OPCODE_SIN:
 102    case SHADER_OPCODE_COS:
 103       return inst->mlen < 2;
 104    case SHADER_OPCODE_LOAD_PAYLOAD:
 105       return !is_copy_payload(inst);
 106    default:
 107       return inst->is_send_from_grf() && !inst->has_side_effects();
 108    }
 109 }
 110
 111 static bool
 112 operands_match(const fs_inst *a, const fs_inst *b, bool *negate)
 113 {
 114    fs_reg *xs = a->src;
 115    fs_reg *ys = b->src;
 116
 117    if (a->opcode == BRW_OPCODE_MAD) {
 118       return xs[0].equals(ys[0]) &&
 119              ((xs[1].equals(ys[1]) && xs[2].equals(ys[2])) ||
 120               (xs[2].equals(ys[1]) && xs[1].equals(ys[2])));
 121    } else if (a->opcode == BRW_OPCODE_MUL && a->dst.type == BRW_REGISTER_TYPE_F) {
 122       bool xs0_negate = xs[0].negate;
 123       bool xs1_negate = xs[1].file == IMM ? xs[1].fixed_hw_reg.dw1.f < 0.0f
 124                                           : xs[1].negate;
 125       bool ys0_negate = ys[0].negate;
 126       bool ys1_negate = ys[1].file == IMM ? ys[1].fixed_hw_reg.dw1.f < 0.0f
 127                                           : ys[1].negate;
 128       float xs1_imm = xs[1].fixed_hw_reg.dw1.f;
 129       float ys1_imm = ys[1].fixed_hw_reg.dw1.f;
 130
 131       xs[0].negate = false;
 132       xs[1].negate = false;
 133       ys[0].negate = false;
 134       ys[1].negate = false;
 135       xs[1].fixed_hw_reg.dw1.f = fabsf(xs[1].fixed_hw_reg.dw1.f);
 136       ys[1].fixed_hw_reg.dw1.f = fabsf(ys[1].fixed_hw_reg.dw1.f);
 137
 138       bool ret = (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 139                  (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 140
 141       xs[0].negate = xs0_negate;
 142       xs[1].negate = xs[1].file == IMM ? false : xs1_negate;
 143       ys[0].negate = ys0_negate;
 144       ys[1].negate = ys[1].file == IMM ? false : ys1_negate;
 145       xs[1].fixed_hw_reg.dw1.f = xs1_imm;
 146       ys[1].fixed_hw_reg.dw1.f = ys1_imm;
 147
 148       *negate = (xs0_negate != xs1_negate) != (ys0_negate != ys1_negate);
 149       return ret;
 150    } else if (!a->is_commutative()) {
 151       bool match = true;
 152       for (int i = 0; i < a->sources; i++) {
 153          if (!xs[i].equals(ys[i])) {
 154             match = false;
 155             break;
 156          }
 157       }
 158       return match;
 159    } else {
 160       return (xs[0].equals(ys[0]) && xs[1].equals(ys[1])) ||
 161              (xs[1].equals(ys[0]) && xs[0].equals(ys[1]));
 162    }
 163 }
 164
 165 static bool
 166 instructions_match(fs_inst *a, fs_inst *b, bool *negate)
 167 {
 168    return a->opcode == b->opcode &&
 169           a->saturate == b->saturate &&
 170           a->predicate == b->predicate &&
 171           a->predicate_inverse == b->predicate_inverse &&
 172           a->conditional_mod == b->conditional_mod &&
 173           a->dst.type == b->dst.type &&
 174           a->sources == b->sources &&
 175           (a->is_tex() ? (a->offset == b->offset &&
 176                           a->mlen == b->mlen &&
 177                           a->regs_written == b->regs_written &&
 178                           a->base_mrf == b->base_mrf &&
 179                           a->eot == b->eot &&
 180                           a->header_present == b->header_present &&
 181                           a->shadow_compare == b->shadow_compare)
 182                        : true) &&
 183           operands_match(a, b, negate);
 184 }
 185
 186 bool
 187 fs_visitor::opt_cse_local(bblock_t *block)
 188 {
 189    bool progress = false;
 190    exec_list aeb;
 191
 192    void *cse_ctx = ralloc_context(NULL);
 193
 194    int ip = block->start_ip;
 195    foreach_inst_in_block(fs_inst, inst, block) {
 196       /* Skip some cases. */
 197       if (is_expression(inst) && !inst->is_partial_write() &&
 198           (inst->dst.file != HW_REG || inst->dst.is_null()))
 199       {
 200          bool found = false;
 201          bool negate = false;
 202
 203          foreach_in_list_use_after(aeb_entry, entry, &aeb) {
 204             /* Match current instruction's expression against those in AEB. */
 205             if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
 206                 instructions_match(inst, entry->generator, &negate)) {
 207                found = true;
 208                progress = true;
 209                break;
 210             }
 211          }
 212
 213          if (!found) {
 214             if (inst->opcode != BRW_OPCODE_MOV ||
 215                 (inst->opcode == BRW_OPCODE_MOV &&
 216                  inst->src[0].file == IMM &&
 217                  inst->src[0].type == BRW_REGISTER_TYPE_VF)) {
 218                /* Our first sighting of this expression.  Create an entry. */
 219                aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
 220                entry->tmp = reg_undef;
 221                entry->generator = inst;
 222                aeb.push_tail(entry);
 223             }
 224          } else {
 225             /* This is at least our second sighting of this expression.
 226              * If we don't have a temporary already, make one.
 227              */
 228             bool no_existing_temp = entry->tmp.file == BAD_FILE;
 229             if (no_existing_temp && !entry->generator->dst.is_null()) {
 230                int written = entry->generator->regs_written;
 231                int dst_width = entry->generator->dst.width / 8;
 232                assert(written % dst_width == 0);
 233
 234                fs_reg orig_dst = entry->generator->dst;
 235                fs_reg tmp = fs_reg(GRF, alloc.allocate(written),
 236                                    orig_dst.type, orig_dst.width);
 237                entry->tmp = tmp;
 238                entry->generator->dst = tmp;
 239
 240                fs_inst *copy;
 241                if (written > dst_width) {
 242                   fs_reg *sources = ralloc_array(mem_ctx, fs_reg, written / dst_width);
 243                   for (int i = 0; i < written / dst_width; i++)
 244                      sources[i] = offset(tmp, i);
 245                   copy = LOAD_PAYLOAD(orig_dst, sources, written / dst_width);
 246                } else {
 247                   copy = MOV(orig_dst, tmp);
 248                   copy->force_writemask_all =
 249                      entry->generator->force_writemask_all;
 250                }
 251                entry->generator->insert_after(block, copy);
 252             }
 253
 254             /* dest <- temp */
 255             if (!inst->dst.is_null()) {
 256                int written = inst->regs_written;
 257                int dst_width = inst->dst.width / 8;
 258                assert(written == entry->generator->regs_written);
 259                assert(dst_width == entry->generator->dst.width / 8);
 260                assert(inst->dst.type == entry->tmp.type);
 261                fs_reg dst = inst->dst;
 262                fs_reg tmp = entry->tmp;
 263                fs_inst *copy;
 264                if (written > dst_width) {
 265                   fs_reg *sources = ralloc_array(mem_ctx, fs_reg, written / dst_width);
 266                   for (int i = 0; i < written / dst_width; i++)
 267                      sources[i] = offset(tmp, i);
 268                   copy = LOAD_PAYLOAD(dst, sources, written / dst_width);
 269                } else {
 270                   copy = MOV(dst, tmp);
 271                   copy->force_writemask_all = inst->force_writemask_all;
 272                   copy->src[0].negate = negate;
 273                }
 274                inst->insert_before(block, copy);
 275             }
 276
 277             /* Set our iterator so that next time through the loop inst->next
 278              * will get the instruction in the basic block after the one we've
 279              * removed.
 280              */
 281             fs_inst *prev = (fs_inst *)inst->prev;
 282
 283             inst->remove(block);
 284             inst = prev;
 285          }
 286       }
 287
 288       foreach_in_list_safe(aeb_entry, entry, &aeb) {
 289          /* Kill all AEB entries that write a different value to or read from
 290           * the flag register if we just wrote it.
 291           */
 292          if (inst->writes_flag()) {
 293             bool negate; /* dummy */
 294             if (entry->generator->reads_flag() ||
 295                 (entry->generator->writes_flag() &&
 296                  !instructions_match(inst, entry->generator, &negate))) {
 297                entry->remove();
 298                ralloc_free(entry);
 299                continue;
 300             }
 301          }
 302
 303          for (int i = 0; i < entry->generator->sources; i++) {
 304             fs_reg *src_reg = &entry->generator->src[i];
 305
 306             /* Kill all AEB entries that use the destination we just
 307              * overwrote.
 308              */
 309             if (inst->overwrites_reg(entry->generator->src[i])) {
 310                entry->remove();
 311                ralloc_free(entry);
 312                break;
 313             }
 314
 315             /* Kill any AEB entries using registers that don't get reused any
 316              * more -- a sure sign they'll fail operands_match().
 317              */
 318             if (src_reg->file == GRF && virtual_grf_end[src_reg->reg] < ip) {
 319                entry->remove();
 320                ralloc_free(entry);
 321                break;
 322             }
 323          }
 324       }
 325
 326       ip++;
 327    }
 328
 329    ralloc_free(cse_ctx);
 330
 331    return progress;
 332 }
 333
 334 bool
 335 fs_visitor::opt_cse()
 336 {
 337    bool progress = false;
 338
 339    calculate_live_intervals();
 340
 341    foreach_block (block, cfg) {
 342       progress = opt_cse_local(block) || progress;
 343    }
 344
 345    if (progress)
 346       invalidate_live_intervals();
 347
 348    return progress;
 349 }