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i965: Push down inclusion of brw_program.h.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35 #include "brw_program.h"
36
37 static enum brw_reg_file
38 brw_file_from_reg(fs_reg *reg)
39 {
40 switch (reg->file) {
41 case ARF:
42 return BRW_ARCHITECTURE_REGISTER_FILE;
43 case FIXED_GRF:
44 case VGRF:
45 return BRW_GENERAL_REGISTER_FILE;
46 case MRF:
47 return BRW_MESSAGE_REGISTER_FILE;
48 case IMM:
49 return BRW_IMMEDIATE_VALUE;
50 case BAD_FILE:
51 case ATTR:
52 case UNIFORM:
53 unreachable("not reached");
54 }
55 return BRW_ARCHITECTURE_REGISTER_FILE;
56 }
57
58 static struct brw_reg
59 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
60 {
61 struct brw_reg brw_reg;
62
63 switch (reg->file) {
64 case MRF:
65 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
66 /* Fallthrough */
67 case VGRF:
68 if (reg->stride == 0) {
69 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
70 } else if (inst->exec_size < 8) {
71 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
72 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
73 inst->exec_size, reg->stride);
74 } else {
75 /* From the Haswell PRM:
76 *
77 * VertStride must be used to cross GRF register boundaries. This
78 * rule implies that elements within a 'Width' cannot cross GRF
79 * boundaries.
80 *
81 * So, for registers with width > 8, we have to use a width of 8
82 * and trust the compression state to sort out the exec size.
83 */
84 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
85 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
86 }
87
88 brw_reg = retype(brw_reg, reg->type);
89 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
90 brw_reg.abs = reg->abs;
91 brw_reg.negate = reg->negate;
92 break;
93 case ARF:
94 case FIXED_GRF:
95 case IMM:
96 brw_reg = reg->as_brw_reg();
97 break;
98 case BAD_FILE:
99 /* Probably unused. */
100 brw_reg = brw_null_reg();
101 break;
102 case ATTR:
103 case UNIFORM:
104 unreachable("not reached");
105 }
106
107 return brw_reg;
108 }
109
110 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
111 void *mem_ctx,
112 const void *key,
113 struct brw_stage_prog_data *prog_data,
114 unsigned promoted_constants,
115 bool runtime_check_aads_emit,
116 const char *stage_abbrev)
117
118 : compiler(compiler), log_data(log_data),
119 devinfo(compiler->devinfo), key(key),
120 prog_data(prog_data),
121 promoted_constants(promoted_constants),
122 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
123 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
124 {
125 p = rzalloc(mem_ctx, struct brw_codegen);
126 brw_init_codegen(devinfo, p, mem_ctx);
127 }
128
129 fs_generator::~fs_generator()
130 {
131 }
132
133 class ip_record : public exec_node {
134 public:
135 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
136
137 ip_record(int ip)
138 {
139 this->ip = ip;
140 }
141
142 int ip;
143 };
144
145 bool
146 fs_generator::patch_discard_jumps_to_fb_writes()
147 {
148 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
149 return false;
150
151 int scale = brw_jump_scale(p->devinfo);
152
153 /* There is a somewhat strange undocumented requirement of using
154 * HALT, according to the simulator. If some channel has HALTed to
155 * a particular UIP, then by the end of the program, every channel
156 * must have HALTed to that UIP. Furthermore, the tracking is a
157 * stack, so you can't do the final halt of a UIP after starting
158 * halting to a new UIP.
159 *
160 * Symptoms of not emitting this instruction on actual hardware
161 * included GPU hangs and sparkly rendering on the piglit discard
162 * tests.
163 */
164 brw_inst *last_halt = gen6_HALT(p);
165 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
166 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
167
168 int ip = p->nr_insn;
169
170 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
171 brw_inst *patch = &p->store[patch_ip->ip];
172
173 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
174 /* HALT takes a half-instruction distance from the pre-incremented IP. */
175 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
176 }
177
178 this->discard_halt_patches.make_empty();
179 return true;
180 }
181
182 void
183 fs_generator::fire_fb_write(fs_inst *inst,
184 struct brw_reg payload,
185 struct brw_reg implied_header,
186 GLuint nr)
187 {
188 uint32_t msg_control;
189
190 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
191
192 if (devinfo->gen < 6) {
193 brw_push_insn_state(p);
194 brw_set_default_exec_size(p, BRW_EXECUTE_8);
195 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
196 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
197 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
198 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
199 brw_pop_insn_state(p);
200 }
201
202 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
203 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
204 else if (prog_data->dual_src_blend) {
205 if (!inst->force_sechalf)
206 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
207 else
208 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
209 } else if (inst->exec_size == 16)
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
211 else
212 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
213
214 uint32_t surf_index =
215 prog_data->binding_table.render_target_start + inst->target;
216
217 bool last_render_target = inst->eot ||
218 (prog_data->dual_src_blend && dispatch_width == 16);
219
220
221 brw_fb_WRITE(p,
222 dispatch_width,
223 payload,
224 implied_header,
225 msg_control,
226 surf_index,
227 nr,
228 0,
229 inst->eot,
230 last_render_target,
231 inst->header_size != 0);
232
233 brw_mark_surface_used(&prog_data->base, surf_index);
234 }
235
236 void
237 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
238 {
239 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
240 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
241 struct brw_reg implied_header;
242
243 if (devinfo->gen < 8 && !devinfo->is_haswell) {
244 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
245 }
246
247 if (inst->base_mrf >= 0)
248 payload = brw_message_reg(inst->base_mrf);
249
250 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
251 * move, here's g1.
252 */
253 if (inst->header_size != 0) {
254 brw_push_insn_state(p);
255 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
256 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
257 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
258 brw_set_default_flag_reg(p, 0, 0);
259
260 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
261 * present.
262 */
263 if (prog_data->uses_kill) {
264 struct brw_reg pixel_mask;
265
266 if (devinfo->gen >= 6)
267 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
268 else
269 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
270
271 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
272 }
273
274 if (devinfo->gen >= 6) {
275 brw_push_insn_state(p);
276 brw_set_default_exec_size(p, BRW_EXECUTE_16);
277 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
278 brw_MOV(p,
279 retype(payload, BRW_REGISTER_TYPE_UD),
280 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
281 brw_pop_insn_state(p);
282
283 if (inst->target > 0 && key->replicate_alpha) {
284 /* Set "Source0 Alpha Present to RenderTarget" bit in message
285 * header.
286 */
287 brw_OR(p,
288 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
289 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
290 brw_imm_ud(0x1 << 11));
291 }
292
293 if (inst->target > 0) {
294 /* Set the render target index for choosing BLEND_STATE. */
295 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
296 BRW_REGISTER_TYPE_UD),
297 brw_imm_ud(inst->target));
298 }
299
300 /* Set computes stencil to render target */
301 if (prog_data->computed_stencil) {
302 brw_OR(p,
303 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
304 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
305 brw_imm_ud(0x1 << 14));
306 }
307
308 implied_header = brw_null_reg();
309 } else {
310 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
311 }
312
313 brw_pop_insn_state(p);
314 } else {
315 implied_header = brw_null_reg();
316 }
317
318 if (!runtime_check_aads_emit) {
319 fire_fb_write(inst, payload, implied_header, inst->mlen);
320 } else {
321 /* This can only happen in gen < 6 */
322 assert(devinfo->gen < 6);
323
324 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
325
326 /* Check runtime bit to detect if we have to send AA data or not */
327 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
328 brw_AND(p,
329 v1_null_ud,
330 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
331 brw_imm_ud(1<<26));
332 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
333
334 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
335 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
336 {
337 /* Don't send AA data */
338 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
339 }
340 brw_land_fwd_jump(p, jmp);
341 fire_fb_write(inst, payload, implied_header, inst->mlen);
342 }
343 }
344
345 void
346 fs_generator::generate_mov_indirect(fs_inst *inst,
347 struct brw_reg dst,
348 struct brw_reg reg,
349 struct brw_reg indirect_byte_offset)
350 {
351 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
352 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
353
354 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
355
356 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
357 struct brw_reg addr = vec8(brw_address_reg(0));
358
359 /* The destination stride of an instruction (in bytes) must be greater
360 * than or equal to the size of the rest of the instruction. Since the
361 * address register is of type UW, we can't use a D-type instruction.
362 * In order to get around this, re re-type to UW and use a stride.
363 */
364 indirect_byte_offset =
365 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
366
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst->exec_size == 8 || devinfo->gen >= 8);
369
370 brw_MOV(p, addr, indirect_byte_offset);
371 brw_inst_set_mask_control(devinfo, brw_last_inst, BRW_MASK_DISABLE);
372 brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
373 }
374
375 void
376 fs_generator::generate_urb_read(fs_inst *inst,
377 struct brw_reg dst,
378 struct brw_reg header)
379 {
380 assert(header.file == BRW_GENERAL_REGISTER_FILE);
381 assert(header.type == BRW_REGISTER_TYPE_UD);
382
383 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
384 brw_set_dest(p, send, dst);
385 brw_set_src0(p, send, header);
386 brw_set_src1(p, send, brw_imm_ud(0u));
387
388 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
389 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
390
391 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
392 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
393
394 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
395 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
396 brw_inst_set_header_present(p->devinfo, send, true);
397 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
398 }
399
400 void
401 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
402 {
403 brw_inst *insn;
404
405 insn = brw_next_insn(p, BRW_OPCODE_SEND);
406
407 brw_set_dest(p, insn, brw_null_reg());
408 brw_set_src0(p, insn, payload);
409 brw_set_src1(p, insn, brw_imm_d(0));
410
411 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
412 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
413
414 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
415 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
416 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
417
418 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
419 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
420 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
421
422 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
423 brw_inst_set_rlen(p->devinfo, insn, 0);
424 brw_inst_set_eot(p->devinfo, insn, inst->eot);
425 brw_inst_set_header_present(p->devinfo, insn, true);
426 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
427 }
428
429 void
430 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
431 {
432 struct brw_inst *insn;
433
434 insn = brw_next_insn(p, BRW_OPCODE_SEND);
435
436 brw_set_dest(p, insn, brw_null_reg());
437 brw_set_src0(p, insn, payload);
438 brw_set_src1(p, insn, brw_imm_d(0));
439
440 /* Terminate a compute shader by sending a message to the thread spawner.
441 */
442 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
443 brw_inst_set_mlen(devinfo, insn, 1);
444 brw_inst_set_rlen(devinfo, insn, 0);
445 brw_inst_set_eot(devinfo, insn, inst->eot);
446 brw_inst_set_header_present(devinfo, insn, false);
447
448 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
449 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
450
451 /* Note that even though the thread has a URB resource associated with it,
452 * we set the "do not dereference URB" bit, because the URB resource is
453 * managed by the fixed-function unit, so it will free it automatically.
454 */
455 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
456
457 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
458 }
459
460 void
461 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
462 struct brw_reg dst,
463 struct brw_reg src)
464 {
465 assert(dispatch_width == 8);
466 assert(devinfo->gen >= 9);
467
468 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
469 * Presumably, in order to save memory bandwidth, the stencil reference
470 * values written from the FS need to be packed into 2 dwords (this makes
471 * sense because the stencil values are limited to 1 byte each and a SIMD8
472 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
473 *
474 * The spec is confusing here because in the payload definition of MDP_RTW_S8
475 * (Message Data Payload for Render Target Writes with Stencil 8b) the
476 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
477 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
478 * packed values specified above and diagrammed below:
479 *
480 * 31 0
481 * --------------------------------
482 * DW | |
483 * 2-7 | IGNORED |
484 * | |
485 * --------------------------------
486 * DW1 | STC | STC | STC | STC |
487 * | slot7 | slot6 | slot5 | slot4|
488 * --------------------------------
489 * DW0 | STC | STC | STC | STC |
490 * | slot3 | slot2 | slot1 | slot0|
491 * --------------------------------
492 */
493
494 src.vstride = BRW_VERTICAL_STRIDE_4;
495 src.width = BRW_WIDTH_1;
496 src.hstride = BRW_HORIZONTAL_STRIDE_0;
497 assert(src.type == BRW_REGISTER_TYPE_UB);
498 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
499 }
500
501 void
502 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
503 {
504 brw_barrier(p, src);
505 brw_WAIT(p);
506 }
507
508 void
509 fs_generator::generate_blorp_fb_write(fs_inst *inst)
510 {
511 brw_fb_WRITE(p,
512 16 /* dispatch_width */,
513 brw_message_reg(inst->base_mrf),
514 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
515 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
516 inst->target,
517 inst->mlen,
518 0,
519 true,
520 true,
521 inst->header_size != 0);
522 }
523
524 void
525 fs_generator::generate_linterp(fs_inst *inst,
526 struct brw_reg dst, struct brw_reg *src)
527 {
528 /* PLN reads:
529 * / in SIMD16 \
530 * -----------------------------------
531 * | src1+0 | src1+1 | src1+2 | src1+3 |
532 * |-----------------------------------|
533 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
534 * -----------------------------------
535 *
536 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
537 *
538 * -----------------------------------
539 * | src1+0 | src1+1 | src1+2 | src1+3 |
540 * |-----------------------------------|
541 * |(x0, x1)|(y0, y1)| | | in SIMD8
542 * |-----------------------------------|
543 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
544 * -----------------------------------
545 *
546 * See also: emit_interpolation_setup_gen4().
547 */
548 struct brw_reg delta_x = src[0];
549 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
550 struct brw_reg interp = src[1];
551
552 if (devinfo->has_pln &&
553 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
554 brw_PLN(p, dst, interp, delta_x);
555 } else {
556 brw_LINE(p, brw_null_reg(), interp, delta_x);
557 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
558 }
559 }
560
561 void
562 fs_generator::generate_math_gen6(fs_inst *inst,
563 struct brw_reg dst,
564 struct brw_reg src0,
565 struct brw_reg src1)
566 {
567 int op = brw_math_function(inst->opcode);
568 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
569
570 if (dispatch_width == 8) {
571 gen6_math(p, dst, op, src0, src1);
572 } else if (dispatch_width == 16) {
573 brw_push_insn_state(p);
574 brw_set_default_exec_size(p, BRW_EXECUTE_8);
575 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
576 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
577 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
578 gen6_math(p, sechalf(dst), op, sechalf(src0),
579 binop ? sechalf(src1) : brw_null_reg());
580 brw_pop_insn_state(p);
581 }
582 }
583
584 void
585 fs_generator::generate_math_gen4(fs_inst *inst,
586 struct brw_reg dst,
587 struct brw_reg src)
588 {
589 int op = brw_math_function(inst->opcode);
590
591 assert(inst->mlen >= 1);
592
593 if (dispatch_width == 8) {
594 gen4_math(p, dst,
595 op,
596 inst->base_mrf, src,
597 BRW_MATH_PRECISION_FULL);
598 } else if (dispatch_width == 16) {
599 brw_set_default_exec_size(p, BRW_EXECUTE_8);
600 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
601 gen4_math(p, firsthalf(dst),
602 op,
603 inst->base_mrf, firsthalf(src),
604 BRW_MATH_PRECISION_FULL);
605 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
606 gen4_math(p, sechalf(dst),
607 op,
608 inst->base_mrf + 1, sechalf(src),
609 BRW_MATH_PRECISION_FULL);
610
611 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
612 }
613 }
614
615 void
616 fs_generator::generate_math_g45(fs_inst *inst,
617 struct brw_reg dst,
618 struct brw_reg src)
619 {
620 if (inst->opcode == SHADER_OPCODE_POW ||
621 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
622 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
623 generate_math_gen4(inst, dst, src);
624 return;
625 }
626
627 int op = brw_math_function(inst->opcode);
628
629 assert(inst->mlen >= 1);
630
631 gen4_math(p, dst,
632 op,
633 inst->base_mrf, src,
634 BRW_MATH_PRECISION_FULL);
635 }
636
637 void
638 fs_generator::generate_get_buffer_size(fs_inst *inst,
639 struct brw_reg dst,
640 struct brw_reg src,
641 struct brw_reg surf_index)
642 {
643 assert(devinfo->gen >= 7);
644 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
645
646 uint32_t simd_mode;
647 int rlen = 4;
648
649 switch (inst->exec_size) {
650 case 8:
651 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
652 break;
653 case 16:
654 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
655 break;
656 default:
657 unreachable("Invalid width for texture instruction");
658 }
659
660 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
661 rlen = 8;
662 dst = vec16(dst);
663 }
664
665 brw_SAMPLE(p,
666 retype(dst, BRW_REGISTER_TYPE_UW),
667 inst->base_mrf,
668 src,
669 surf_index.ud,
670 0,
671 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
672 rlen, /* response length */
673 inst->mlen,
674 inst->header_size > 0,
675 simd_mode,
676 BRW_SAMPLER_RETURN_FORMAT_SINT32);
677
678 brw_mark_surface_used(prog_data, surf_index.ud);
679 }
680
681 void
682 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
683 struct brw_reg sampler_index)
684 {
685 int msg_type = -1;
686 int rlen = 4;
687 uint32_t simd_mode;
688 uint32_t return_format;
689 bool is_combined_send = inst->eot;
690
691 switch (dst.type) {
692 case BRW_REGISTER_TYPE_D:
693 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
694 break;
695 case BRW_REGISTER_TYPE_UD:
696 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
697 break;
698 default:
699 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
700 break;
701 }
702
703 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
704 * is set as part of the message descriptor. On gen4, the PRM seems to
705 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
706 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
707 * gone from the message descriptor entirely and you just get UINT32 all
708 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
709 * just stomp it to UINT32 all the time.
710 */
711 if (inst->opcode == SHADER_OPCODE_TXS)
712 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
713
714 switch (inst->exec_size) {
715 case 8:
716 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
717 break;
718 case 16:
719 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
720 break;
721 default:
722 unreachable("Invalid width for texture instruction");
723 }
724
725 if (devinfo->gen >= 5) {
726 switch (inst->opcode) {
727 case SHADER_OPCODE_TEX:
728 if (inst->shadow_compare) {
729 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
730 } else {
731 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
732 }
733 break;
734 case FS_OPCODE_TXB:
735 if (inst->shadow_compare) {
736 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
737 } else {
738 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
739 }
740 break;
741 case SHADER_OPCODE_TXL:
742 if (inst->shadow_compare) {
743 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
744 } else {
745 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
746 }
747 break;
748 case SHADER_OPCODE_TXS:
749 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
750 break;
751 case SHADER_OPCODE_TXD:
752 if (inst->shadow_compare) {
753 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
754 assert(devinfo->gen >= 8 || devinfo->is_haswell);
755 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
756 } else {
757 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
758 }
759 break;
760 case SHADER_OPCODE_TXF:
761 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
762 break;
763 case SHADER_OPCODE_TXF_CMS_W:
764 assert(devinfo->gen >= 9);
765 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
766 break;
767 case SHADER_OPCODE_TXF_CMS:
768 if (devinfo->gen >= 7)
769 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
770 else
771 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
772 break;
773 case SHADER_OPCODE_TXF_UMS:
774 assert(devinfo->gen >= 7);
775 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
776 break;
777 case SHADER_OPCODE_TXF_MCS:
778 assert(devinfo->gen >= 7);
779 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
780 break;
781 case SHADER_OPCODE_LOD:
782 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
783 break;
784 case SHADER_OPCODE_TG4:
785 if (inst->shadow_compare) {
786 assert(devinfo->gen >= 7);
787 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
788 } else {
789 assert(devinfo->gen >= 6);
790 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
791 }
792 break;
793 case SHADER_OPCODE_TG4_OFFSET:
794 assert(devinfo->gen >= 7);
795 if (inst->shadow_compare) {
796 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
797 } else {
798 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
799 }
800 break;
801 case SHADER_OPCODE_SAMPLEINFO:
802 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
803 break;
804 default:
805 unreachable("not reached");
806 }
807 } else {
808 switch (inst->opcode) {
809 case SHADER_OPCODE_TEX:
810 /* Note that G45 and older determines shadow compare and dispatch width
811 * from message length for most messages.
812 */
813 if (inst->exec_size == 8) {
814 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
815 if (inst->shadow_compare) {
816 assert(inst->mlen == 6);
817 } else {
818 assert(inst->mlen <= 4);
819 }
820 } else {
821 if (inst->shadow_compare) {
822 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
823 assert(inst->mlen == 9);
824 } else {
825 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
826 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
827 }
828 }
829 break;
830 case FS_OPCODE_TXB:
831 if (inst->shadow_compare) {
832 assert(inst->exec_size == 8);
833 assert(inst->mlen == 6);
834 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
835 } else {
836 assert(inst->mlen == 9);
837 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
838 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
839 }
840 break;
841 case SHADER_OPCODE_TXL:
842 if (inst->shadow_compare) {
843 assert(inst->exec_size == 8);
844 assert(inst->mlen == 6);
845 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
846 } else {
847 assert(inst->mlen == 9);
848 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
849 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
850 }
851 break;
852 case SHADER_OPCODE_TXD:
853 /* There is no sample_d_c message; comparisons are done manually */
854 assert(inst->exec_size == 8);
855 assert(inst->mlen == 7 || inst->mlen == 10);
856 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
857 break;
858 case SHADER_OPCODE_TXF:
859 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
860 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
861 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
862 break;
863 case SHADER_OPCODE_TXS:
864 assert(inst->mlen == 3);
865 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
866 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
867 break;
868 default:
869 unreachable("not reached");
870 }
871 }
872 assert(msg_type != -1);
873
874 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
875 rlen = 8;
876 dst = vec16(dst);
877 }
878
879 if (is_combined_send) {
880 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
881 rlen = 0;
882 }
883
884 assert(devinfo->gen < 7 || inst->header_size == 0 ||
885 src.file == BRW_GENERAL_REGISTER_FILE);
886
887 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
888
889 /* Load the message header if present. If there's a texture offset,
890 * we need to set it up explicitly and load the offset bitfield.
891 * Otherwise, we can use an implied move from g0 to the first message reg.
892 */
893 if (inst->header_size != 0) {
894 if (devinfo->gen < 6 && !inst->offset) {
895 /* Set up an implied move from g0 to the MRF. */
896 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
897 } else {
898 struct brw_reg header_reg;
899
900 if (devinfo->gen >= 7) {
901 header_reg = src;
902 } else {
903 assert(inst->base_mrf != -1);
904 header_reg = brw_message_reg(inst->base_mrf);
905 }
906
907 brw_push_insn_state(p);
908 brw_set_default_exec_size(p, BRW_EXECUTE_8);
909 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
910 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
911 /* Explicitly set up the message header by copying g0 to the MRF. */
912 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
913
914 if (inst->offset) {
915 /* Set the offset bits in DWord 2. */
916 brw_MOV(p, get_element_ud(header_reg, 2),
917 brw_imm_ud(inst->offset));
918 }
919
920 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
921 brw_pop_insn_state(p);
922 }
923 }
924
925 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
926 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
927 ? prog_data->binding_table.gather_texture_start
928 : prog_data->binding_table.texture_start;
929
930 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
931 uint32_t sampler = sampler_index.ud;
932
933 brw_SAMPLE(p,
934 retype(dst, BRW_REGISTER_TYPE_UW),
935 inst->base_mrf,
936 src,
937 sampler + base_binding_table_index,
938 sampler % 16,
939 msg_type,
940 rlen,
941 inst->mlen,
942 inst->header_size != 0,
943 simd_mode,
944 return_format);
945
946 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
947 } else {
948 /* Non-const sampler index */
949
950 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
951 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
952
953 brw_push_insn_state(p);
954 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
955 brw_set_default_access_mode(p, BRW_ALIGN_1);
956
957 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
958 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
959 if (base_binding_table_index)
960 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
961 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
962
963 brw_pop_insn_state(p);
964
965 /* dst = send(offset, a0.0 | <descriptor>) */
966 brw_inst *insn = brw_send_indirect_message(
967 p, BRW_SFID_SAMPLER, dst, src, addr);
968 brw_set_sampler_message(p, insn,
969 0 /* surface */,
970 0 /* sampler */,
971 msg_type,
972 rlen,
973 inst->mlen /* mlen */,
974 inst->header_size != 0 /* header */,
975 simd_mode,
976 return_format);
977
978 /* visitor knows more than we do about the surface limit required,
979 * so has already done marking.
980 */
981 }
982
983 if (is_combined_send) {
984 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
985 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
986 }
987 }
988
989
990 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
991 * looking like:
992 *
993 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
994 *
995 * Ideally, we want to produce:
996 *
997 * DDX DDY
998 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
999 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1000 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1001 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1002 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1003 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1004 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1005 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1006 *
1007 * and add another set of two more subspans if in 16-pixel dispatch mode.
1008 *
1009 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1010 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1011 * pair. But the ideal approximation may impose a huge performance cost on
1012 * sample_d. On at least Haswell, sample_d instruction does some
1013 * optimizations if the same LOD is used for all pixels in the subspan.
1014 *
1015 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1016 * appropriate swizzling.
1017 */
1018 void
1019 fs_generator::generate_ddx(enum opcode opcode,
1020 struct brw_reg dst, struct brw_reg src)
1021 {
1022 unsigned vstride, width;
1023
1024 if (opcode == FS_OPCODE_DDX_FINE) {
1025 /* produce accurate derivatives */
1026 vstride = BRW_VERTICAL_STRIDE_2;
1027 width = BRW_WIDTH_2;
1028 } else {
1029 /* replicate the derivative at the top-left pixel to other pixels */
1030 vstride = BRW_VERTICAL_STRIDE_4;
1031 width = BRW_WIDTH_4;
1032 }
1033
1034 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1035 src.negate, src.abs,
1036 BRW_REGISTER_TYPE_F,
1037 vstride,
1038 width,
1039 BRW_HORIZONTAL_STRIDE_0,
1040 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1041 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1042 src.negate, src.abs,
1043 BRW_REGISTER_TYPE_F,
1044 vstride,
1045 width,
1046 BRW_HORIZONTAL_STRIDE_0,
1047 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1048 brw_ADD(p, dst, src0, negate(src1));
1049 }
1050
1051 /* The negate_value boolean is used to negate the derivative computation for
1052 * FBOs, since they place the origin at the upper left instead of the lower
1053 * left.
1054 */
1055 void
1056 fs_generator::generate_ddy(enum opcode opcode,
1057 struct brw_reg dst, struct brw_reg src,
1058 bool negate_value)
1059 {
1060 if (opcode == FS_OPCODE_DDY_FINE) {
1061 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1062 * Region Restrictions):
1063 *
1064 * In Align16 access mode, SIMD16 is not allowed for DW operations
1065 * and SIMD8 is not allowed for DF operations.
1066 *
1067 * In this context, "DW operations" means "operations acting on 32-bit
1068 * values", so it includes operations on floats.
1069 *
1070 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1071 * (Instruction Compression -> Rules and Restrictions):
1072 *
1073 * A compressed instruction must be in Align1 access mode. Align16
1074 * mode instructions cannot be compressed.
1075 *
1076 * Similar text exists in the g45 PRM.
1077 *
1078 * On these platforms, if we're building a SIMD16 shader, we need to
1079 * manually unroll to a pair of SIMD8 instructions.
1080 */
1081 bool unroll_to_simd8 =
1082 (dispatch_width == 16 &&
1083 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1084
1085 /* produce accurate derivatives */
1086 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1087 src.negate, src.abs,
1088 BRW_REGISTER_TYPE_F,
1089 BRW_VERTICAL_STRIDE_4,
1090 BRW_WIDTH_4,
1091 BRW_HORIZONTAL_STRIDE_1,
1092 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1093 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1094 src.negate, src.abs,
1095 BRW_REGISTER_TYPE_F,
1096 BRW_VERTICAL_STRIDE_4,
1097 BRW_WIDTH_4,
1098 BRW_HORIZONTAL_STRIDE_1,
1099 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1100 brw_push_insn_state(p);
1101 brw_set_default_access_mode(p, BRW_ALIGN_16);
1102 if (unroll_to_simd8) {
1103 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1104 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1105 if (negate_value) {
1106 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1107 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1108 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1109 } else {
1110 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1111 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1112 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1113 }
1114 } else {
1115 if (negate_value)
1116 brw_ADD(p, dst, src1, negate(src0));
1117 else
1118 brw_ADD(p, dst, src0, negate(src1));
1119 }
1120 brw_pop_insn_state(p);
1121 } else {
1122 /* replicate the derivative at the top-left pixel to other pixels */
1123 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1124 src.negate, src.abs,
1125 BRW_REGISTER_TYPE_F,
1126 BRW_VERTICAL_STRIDE_4,
1127 BRW_WIDTH_4,
1128 BRW_HORIZONTAL_STRIDE_0,
1129 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1130 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1131 src.negate, src.abs,
1132 BRW_REGISTER_TYPE_F,
1133 BRW_VERTICAL_STRIDE_4,
1134 BRW_WIDTH_4,
1135 BRW_HORIZONTAL_STRIDE_0,
1136 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1137 if (negate_value)
1138 brw_ADD(p, dst, src1, negate(src0));
1139 else
1140 brw_ADD(p, dst, src0, negate(src1));
1141 }
1142 }
1143
1144 void
1145 fs_generator::generate_discard_jump(fs_inst *inst)
1146 {
1147 assert(devinfo->gen >= 6);
1148
1149 /* This HALT will be patched up at FB write time to point UIP at the end of
1150 * the program, and at brw_uip_jip() JIP will be set to the end of the
1151 * current block (or the program).
1152 */
1153 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1154
1155 brw_push_insn_state(p);
1156 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1157 gen6_HALT(p);
1158 brw_pop_insn_state(p);
1159 }
1160
1161 void
1162 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1163 {
1164 assert(inst->mlen != 0);
1165
1166 brw_MOV(p,
1167 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1168 retype(src, BRW_REGISTER_TYPE_UD));
1169 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1170 inst->exec_size / 8, inst->offset);
1171 }
1172
1173 void
1174 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1175 {
1176 assert(inst->mlen != 0);
1177
1178 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1179 inst->exec_size / 8, inst->offset);
1180 }
1181
1182 void
1183 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1184 {
1185 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1186 }
1187
1188 void
1189 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1190 struct brw_reg dst,
1191 struct brw_reg index,
1192 struct brw_reg offset)
1193 {
1194 assert(inst->mlen != 0);
1195
1196 assert(index.file == BRW_IMMEDIATE_VALUE &&
1197 index.type == BRW_REGISTER_TYPE_UD);
1198 uint32_t surf_index = index.ud;
1199
1200 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1201 offset.type == BRW_REGISTER_TYPE_UD);
1202 uint32_t read_offset = offset.ud;
1203
1204 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1205 read_offset, surf_index);
1206 }
1207
1208 void
1209 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1210 struct brw_reg dst,
1211 struct brw_reg index,
1212 struct brw_reg offset)
1213 {
1214 assert(index.type == BRW_REGISTER_TYPE_UD);
1215
1216 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1217 /* Reference just the dword we need, to avoid angering validate_reg(). */
1218 offset = brw_vec1_grf(offset.nr, 0);
1219
1220 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1221 * the destination loaded consecutively from the same offset (which appears
1222 * in the first component, and the rest are ignored).
1223 */
1224 dst.width = BRW_WIDTH_4;
1225
1226 struct brw_reg src = offset;
1227 bool header_present = false;
1228
1229 if (devinfo->gen >= 9) {
1230 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1231 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1232 header_present = true;
1233
1234 brw_push_insn_state(p);
1235 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1236 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1237 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1238 brw_set_default_access_mode(p, BRW_ALIGN_1);
1239
1240 brw_MOV(p, get_element_ud(src, 2),
1241 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1242 brw_pop_insn_state(p);
1243 }
1244
1245 if (index.file == BRW_IMMEDIATE_VALUE) {
1246
1247 uint32_t surf_index = index.ud;
1248
1249 brw_push_insn_state(p);
1250 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1251 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1252 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1253 brw_pop_insn_state(p);
1254
1255 brw_set_dest(p, send, dst);
1256 brw_set_src0(p, send, src);
1257 brw_set_sampler_message(p, send,
1258 surf_index,
1259 0, /* LD message ignores sampler unit */
1260 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1261 1, /* rlen */
1262 inst->mlen,
1263 header_present,
1264 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1265 0);
1266 } else {
1267
1268 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1269
1270 brw_push_insn_state(p);
1271 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1272 brw_set_default_access_mode(p, BRW_ALIGN_1);
1273
1274 /* a0.0 = surf_index & 0xff */
1275 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1276 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1277 brw_set_dest(p, insn_and, addr);
1278 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1279 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1280
1281 /* dst = send(payload, a0.0 | <descriptor>) */
1282 brw_inst *insn = brw_send_indirect_message(
1283 p, BRW_SFID_SAMPLER, dst, src, addr);
1284 brw_set_sampler_message(p, insn,
1285 0,
1286 0, /* LD message ignores sampler unit */
1287 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1288 1, /* rlen */
1289 inst->mlen,
1290 header_present,
1291 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1292 0);
1293
1294 brw_pop_insn_state(p);
1295 }
1296 }
1297
1298 void
1299 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1300 struct brw_reg dst,
1301 struct brw_reg index,
1302 struct brw_reg offset)
1303 {
1304 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1305 assert(inst->header_size != 0);
1306 assert(inst->mlen);
1307
1308 assert(index.file == BRW_IMMEDIATE_VALUE &&
1309 index.type == BRW_REGISTER_TYPE_UD);
1310 uint32_t surf_index = index.ud;
1311
1312 uint32_t simd_mode, rlen, msg_type;
1313 if (dispatch_width == 16) {
1314 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1315 rlen = 8;
1316 } else {
1317 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1318 rlen = 4;
1319 }
1320
1321 if (devinfo->gen >= 5)
1322 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1323 else {
1324 /* We always use the SIMD16 message so that we only have to load U, and
1325 * not V or R.
1326 */
1327 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1328 assert(inst->mlen == 3);
1329 assert(inst->regs_written == 8);
1330 rlen = 8;
1331 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1332 }
1333
1334 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1335 BRW_REGISTER_TYPE_D);
1336 brw_MOV(p, offset_mrf, offset);
1337
1338 struct brw_reg header = brw_vec8_grf(0, 0);
1339 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1340
1341 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1342 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1343 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1344 brw_set_src0(p, send, header);
1345 if (devinfo->gen < 6)
1346 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1347
1348 /* Our surface is set up as floats, regardless of what actual data is
1349 * stored in it.
1350 */
1351 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1352 brw_set_sampler_message(p, send,
1353 surf_index,
1354 0, /* sampler (unused) */
1355 msg_type,
1356 rlen,
1357 inst->mlen,
1358 inst->header_size != 0,
1359 simd_mode,
1360 return_format);
1361 }
1362
1363 void
1364 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1365 struct brw_reg dst,
1366 struct brw_reg index,
1367 struct brw_reg offset)
1368 {
1369 assert(devinfo->gen >= 7);
1370 /* Varying-offset pull constant loads are treated as a normal expression on
1371 * gen7, so the fact that it's a send message is hidden at the IR level.
1372 */
1373 assert(inst->header_size == 0);
1374 assert(!inst->mlen);
1375 assert(index.type == BRW_REGISTER_TYPE_UD);
1376
1377 uint32_t simd_mode, rlen, mlen;
1378 if (dispatch_width == 16) {
1379 mlen = 2;
1380 rlen = 8;
1381 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1382 } else {
1383 mlen = 1;
1384 rlen = 4;
1385 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1386 }
1387
1388 if (index.file == BRW_IMMEDIATE_VALUE) {
1389
1390 uint32_t surf_index = index.ud;
1391
1392 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1393 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1394 brw_set_src0(p, send, offset);
1395 brw_set_sampler_message(p, send,
1396 surf_index,
1397 0, /* LD message ignores sampler unit */
1398 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1399 rlen,
1400 mlen,
1401 false, /* no header */
1402 simd_mode,
1403 0);
1404
1405 } else {
1406
1407 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1408
1409 brw_push_insn_state(p);
1410 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1411 brw_set_default_access_mode(p, BRW_ALIGN_1);
1412
1413 /* a0.0 = surf_index & 0xff */
1414 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1415 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1416 brw_set_dest(p, insn_and, addr);
1417 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1418 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1419
1420 brw_pop_insn_state(p);
1421
1422 /* dst = send(offset, a0.0 | <descriptor>) */
1423 brw_inst *insn = brw_send_indirect_message(
1424 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1425 offset, addr);
1426 brw_set_sampler_message(p, insn,
1427 0 /* surface */,
1428 0 /* sampler */,
1429 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1430 rlen /* rlen */,
1431 mlen /* mlen */,
1432 false /* header */,
1433 simd_mode,
1434 0);
1435 }
1436 }
1437
1438 /**
1439 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1440 * into the flags register (f0.0).
1441 *
1442 * Used only on Gen6 and above.
1443 */
1444 void
1445 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1446 {
1447 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1448 struct brw_reg dispatch_mask;
1449
1450 if (devinfo->gen >= 6)
1451 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1452 else
1453 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1454
1455 brw_push_insn_state(p);
1456 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1457 brw_MOV(p, flags, dispatch_mask);
1458 brw_pop_insn_state(p);
1459 }
1460
1461 void
1462 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1463 struct brw_reg dst,
1464 struct brw_reg src,
1465 struct brw_reg msg_data,
1466 unsigned msg_type)
1467 {
1468 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1469
1470 brw_pixel_interpolator_query(p,
1471 retype(dst, BRW_REGISTER_TYPE_UW),
1472 src,
1473 inst->pi_noperspective,
1474 msg_type,
1475 msg_data,
1476 inst->mlen,
1477 inst->regs_written);
1478 }
1479
1480
1481 /**
1482 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1483 * sampler LD messages.
1484 *
1485 * We don't want to bake it into the send message's code generation because
1486 * that means we don't get a chance to schedule the instructions.
1487 */
1488 void
1489 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1490 struct brw_reg dst,
1491 struct brw_reg value)
1492 {
1493 assert(value.file == BRW_IMMEDIATE_VALUE);
1494
1495 brw_push_insn_state(p);
1496 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1497 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1498 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1499 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1500 brw_pop_insn_state(p);
1501 }
1502
1503 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1504 * the ADD instruction.
1505 */
1506 void
1507 fs_generator::generate_set_sample_id(fs_inst *inst,
1508 struct brw_reg dst,
1509 struct brw_reg src0,
1510 struct brw_reg src1)
1511 {
1512 assert(dst.type == BRW_REGISTER_TYPE_D ||
1513 dst.type == BRW_REGISTER_TYPE_UD);
1514 assert(src0.type == BRW_REGISTER_TYPE_D ||
1515 src0.type == BRW_REGISTER_TYPE_UD);
1516
1517 struct brw_reg reg = stride(src1, 1, 4, 0);
1518 if (devinfo->gen >= 8 || dispatch_width == 8) {
1519 brw_ADD(p, dst, src0, reg);
1520 } else if (dispatch_width == 16) {
1521 brw_push_insn_state(p);
1522 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1523 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1524 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1525 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1526 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1527 brw_pop_insn_state(p);
1528 }
1529 }
1530
1531 void
1532 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1533 struct brw_reg dst,
1534 struct brw_reg x,
1535 struct brw_reg y)
1536 {
1537 assert(devinfo->gen >= 7);
1538 assert(dst.type == BRW_REGISTER_TYPE_UD);
1539 assert(x.type == BRW_REGISTER_TYPE_F);
1540 assert(y.type == BRW_REGISTER_TYPE_F);
1541
1542 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1543 *
1544 * Because this instruction does not have a 16-bit floating-point type,
1545 * the destination data type must be Word (W).
1546 *
1547 * The destination must be DWord-aligned and specify a horizontal stride
1548 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1549 * each destination channel and the upper word is not modified.
1550 */
1551 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1552
1553 /* Give each 32-bit channel of dst the form below, where "." means
1554 * unchanged.
1555 * 0x....hhhh
1556 */
1557 brw_F32TO16(p, dst_w, y);
1558
1559 /* Now the form:
1560 * 0xhhhh0000
1561 */
1562 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1563
1564 /* And, finally the form of packHalf2x16's output:
1565 * 0xhhhhllll
1566 */
1567 brw_F32TO16(p, dst_w, x);
1568 }
1569
1570 void
1571 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1572 struct brw_reg dst,
1573 struct brw_reg src)
1574 {
1575 assert(devinfo->gen >= 7);
1576 assert(dst.type == BRW_REGISTER_TYPE_F);
1577 assert(src.type == BRW_REGISTER_TYPE_UD);
1578
1579 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1580 *
1581 * Because this instruction does not have a 16-bit floating-point type,
1582 * the source data type must be Word (W). The destination type must be
1583 * F (Float).
1584 */
1585 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1586
1587 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1588 * For the Y case, we wish to access only the upper word; therefore
1589 * a 16-bit subregister offset is needed.
1590 */
1591 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1592 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1593 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1594 src_w.subnr += 2;
1595
1596 brw_F16TO32(p, dst, src_w);
1597 }
1598
1599 void
1600 fs_generator::generate_shader_time_add(fs_inst *inst,
1601 struct brw_reg payload,
1602 struct brw_reg offset,
1603 struct brw_reg value)
1604 {
1605 assert(devinfo->gen >= 7);
1606 brw_push_insn_state(p);
1607 brw_set_default_mask_control(p, true);
1608
1609 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1610 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1611 offset.type);
1612 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1613 value.type);
1614
1615 assert(offset.file == BRW_IMMEDIATE_VALUE);
1616 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1617 value.width = BRW_WIDTH_1;
1618 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1619 value.vstride = BRW_VERTICAL_STRIDE_0;
1620 } else {
1621 assert(value.file == BRW_IMMEDIATE_VALUE);
1622 }
1623
1624 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1625 * case, and we don't really care about squeezing every bit of performance
1626 * out of this path, so we just emit the MOVs from here.
1627 */
1628 brw_MOV(p, payload_offset, offset);
1629 brw_MOV(p, payload_value, value);
1630 brw_shader_time_add(p, payload,
1631 prog_data->binding_table.shader_time_start);
1632 brw_pop_insn_state(p);
1633
1634 brw_mark_surface_used(prog_data,
1635 prog_data->binding_table.shader_time_start);
1636 }
1637
1638 void
1639 fs_generator::enable_debug(const char *shader_name)
1640 {
1641 debug_flag = true;
1642 this->shader_name = shader_name;
1643 }
1644
1645 int
1646 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1647 {
1648 /* align to 64 byte boundary. */
1649 while (p->next_insn_offset % 64)
1650 brw_NOP(p);
1651
1652 this->dispatch_width = dispatch_width;
1653 if (dispatch_width == 16)
1654 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1655
1656 int start_offset = p->next_insn_offset;
1657 int spill_count = 0, fill_count = 0;
1658 int loop_count = 0;
1659
1660 struct annotation_info annotation;
1661 memset(&annotation, 0, sizeof(annotation));
1662
1663 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1664 struct brw_reg src[3], dst;
1665 unsigned int last_insn_offset = p->next_insn_offset;
1666 bool multiple_instructions_emitted = false;
1667
1668 if (unlikely(debug_flag))
1669 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1670
1671 for (unsigned int i = 0; i < inst->sources; i++) {
1672 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1673
1674 /* The accumulator result appears to get used for the
1675 * conditional modifier generation. When negating a UD
1676 * value, there is a 33rd bit generated for the sign in the
1677 * accumulator value, so now you can't check, for example,
1678 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1679 */
1680 assert(!inst->conditional_mod ||
1681 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1682 !inst->src[i].negate);
1683 }
1684 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1685
1686 brw_set_default_predicate_control(p, inst->predicate);
1687 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1688 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1689 brw_set_default_saturate(p, inst->saturate);
1690 brw_set_default_mask_control(p, inst->force_writemask_all);
1691 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1692 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1693
1694 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1695 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1696
1697 switch (inst->exec_size) {
1698 case 1:
1699 case 2:
1700 case 4:
1701 assert(inst->force_writemask_all);
1702 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1703 break;
1704 case 8:
1705 if (inst->force_sechalf) {
1706 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1707 } else {
1708 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1709 }
1710 break;
1711 case 16:
1712 case 32:
1713 /* If the instruction writes to more than one register, it needs to
1714 * be a "compressed" instruction on Gen <= 5.
1715 */
1716 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1717 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1718 else
1719 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1720 break;
1721 default:
1722 unreachable("Invalid instruction width");
1723 }
1724
1725 switch (inst->opcode) {
1726 case BRW_OPCODE_MOV:
1727 brw_MOV(p, dst, src[0]);
1728 break;
1729 case BRW_OPCODE_ADD:
1730 brw_ADD(p, dst, src[0], src[1]);
1731 break;
1732 case BRW_OPCODE_MUL:
1733 brw_MUL(p, dst, src[0], src[1]);
1734 break;
1735 case BRW_OPCODE_AVG:
1736 brw_AVG(p, dst, src[0], src[1]);
1737 break;
1738 case BRW_OPCODE_MACH:
1739 brw_MACH(p, dst, src[0], src[1]);
1740 break;
1741
1742 case BRW_OPCODE_LINE:
1743 brw_LINE(p, dst, src[0], src[1]);
1744 break;
1745
1746 case BRW_OPCODE_MAD:
1747 assert(devinfo->gen >= 6);
1748 brw_set_default_access_mode(p, BRW_ALIGN_16);
1749 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1750 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1751 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1752 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1753 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1754 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1755 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1756
1757 if (inst->conditional_mod) {
1758 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1759 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1760 multiple_instructions_emitted = true;
1761 }
1762 } else {
1763 brw_MAD(p, dst, src[0], src[1], src[2]);
1764 }
1765 brw_set_default_access_mode(p, BRW_ALIGN_1);
1766 break;
1767
1768 case BRW_OPCODE_LRP:
1769 assert(devinfo->gen >= 6);
1770 brw_set_default_access_mode(p, BRW_ALIGN_16);
1771 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1772 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1773 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1774 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1775 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1776 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1777 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1778
1779 if (inst->conditional_mod) {
1780 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1781 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1782 multiple_instructions_emitted = true;
1783 }
1784 } else {
1785 brw_LRP(p, dst, src[0], src[1], src[2]);
1786 }
1787 brw_set_default_access_mode(p, BRW_ALIGN_1);
1788 break;
1789
1790 case BRW_OPCODE_FRC:
1791 brw_FRC(p, dst, src[0]);
1792 break;
1793 case BRW_OPCODE_RNDD:
1794 brw_RNDD(p, dst, src[0]);
1795 break;
1796 case BRW_OPCODE_RNDE:
1797 brw_RNDE(p, dst, src[0]);
1798 break;
1799 case BRW_OPCODE_RNDZ:
1800 brw_RNDZ(p, dst, src[0]);
1801 break;
1802
1803 case BRW_OPCODE_AND:
1804 brw_AND(p, dst, src[0], src[1]);
1805 break;
1806 case BRW_OPCODE_OR:
1807 brw_OR(p, dst, src[0], src[1]);
1808 break;
1809 case BRW_OPCODE_XOR:
1810 brw_XOR(p, dst, src[0], src[1]);
1811 break;
1812 case BRW_OPCODE_NOT:
1813 brw_NOT(p, dst, src[0]);
1814 break;
1815 case BRW_OPCODE_ASR:
1816 brw_ASR(p, dst, src[0], src[1]);
1817 break;
1818 case BRW_OPCODE_SHR:
1819 brw_SHR(p, dst, src[0], src[1]);
1820 break;
1821 case BRW_OPCODE_SHL:
1822 brw_SHL(p, dst, src[0], src[1]);
1823 break;
1824 case BRW_OPCODE_F32TO16:
1825 assert(devinfo->gen >= 7);
1826 brw_F32TO16(p, dst, src[0]);
1827 break;
1828 case BRW_OPCODE_F16TO32:
1829 assert(devinfo->gen >= 7);
1830 brw_F16TO32(p, dst, src[0]);
1831 break;
1832 case BRW_OPCODE_CMP:
1833 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1834 * that when the destination is a GRF that the dependency-clear bit on
1835 * the flag register is cleared early.
1836 *
1837 * Suggested workarounds are to disable coissuing CMP instructions
1838 * or to split CMP(16) instructions into two CMP(8) instructions.
1839 *
1840 * We choose to split into CMP(8) instructions since disabling
1841 * coissuing would affect CMP instructions not otherwise affected by
1842 * the errata.
1843 */
1844 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1845 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1846 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1847 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1848 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1849 firsthalf(src[0]), firsthalf(src[1]));
1850 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1851 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1852 sechalf(src[0]), sechalf(src[1]));
1853 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1854
1855 multiple_instructions_emitted = true;
1856 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1857 /* For unknown reasons, the aforementioned workaround is not
1858 * sufficient. Overriding the type when the destination is the
1859 * null register is necessary but not sufficient by itself.
1860 */
1861 assert(dst.nr == BRW_ARF_NULL);
1862 dst.type = BRW_REGISTER_TYPE_D;
1863 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1864 } else {
1865 unreachable("not reached");
1866 }
1867 } else {
1868 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1869 }
1870 break;
1871 case BRW_OPCODE_SEL:
1872 brw_SEL(p, dst, src[0], src[1]);
1873 break;
1874 case BRW_OPCODE_BFREV:
1875 assert(devinfo->gen >= 7);
1876 /* BFREV only supports UD type for src and dst. */
1877 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1878 retype(src[0], BRW_REGISTER_TYPE_UD));
1879 break;
1880 case BRW_OPCODE_FBH:
1881 assert(devinfo->gen >= 7);
1882 /* FBH only supports UD type for dst. */
1883 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1884 break;
1885 case BRW_OPCODE_FBL:
1886 assert(devinfo->gen >= 7);
1887 /* FBL only supports UD type for dst. */
1888 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1889 break;
1890 case BRW_OPCODE_CBIT:
1891 assert(devinfo->gen >= 7);
1892 /* CBIT only supports UD type for dst. */
1893 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1894 break;
1895 case BRW_OPCODE_ADDC:
1896 assert(devinfo->gen >= 7);
1897 brw_ADDC(p, dst, src[0], src[1]);
1898 break;
1899 case BRW_OPCODE_SUBB:
1900 assert(devinfo->gen >= 7);
1901 brw_SUBB(p, dst, src[0], src[1]);
1902 break;
1903 case BRW_OPCODE_MAC:
1904 brw_MAC(p, dst, src[0], src[1]);
1905 break;
1906
1907 case BRW_OPCODE_BFE:
1908 assert(devinfo->gen >= 7);
1909 brw_set_default_access_mode(p, BRW_ALIGN_16);
1910 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1911 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1912 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1913 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1914 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1915 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1916 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1917 } else {
1918 brw_BFE(p, dst, src[0], src[1], src[2]);
1919 }
1920 brw_set_default_access_mode(p, BRW_ALIGN_1);
1921 break;
1922
1923 case BRW_OPCODE_BFI1:
1924 assert(devinfo->gen >= 7);
1925 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1926 * should
1927 *
1928 * "Force BFI instructions to be executed always in SIMD8."
1929 */
1930 if (dispatch_width == 16 && devinfo->is_haswell) {
1931 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1932 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1933 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1934 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1935 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1936 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1937 } else {
1938 brw_BFI1(p, dst, src[0], src[1]);
1939 }
1940 break;
1941 case BRW_OPCODE_BFI2:
1942 assert(devinfo->gen >= 7);
1943 brw_set_default_access_mode(p, BRW_ALIGN_16);
1944 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1945 * should
1946 *
1947 * "Force BFI instructions to be executed always in SIMD8."
1948 *
1949 * Otherwise we would be able to emit compressed instructions like we
1950 * do for the other three-source instructions.
1951 */
1952 if (dispatch_width == 16 &&
1953 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1954 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1955 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1956 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1957 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1958 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1959 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1960 } else {
1961 brw_BFI2(p, dst, src[0], src[1], src[2]);
1962 }
1963 brw_set_default_access_mode(p, BRW_ALIGN_1);
1964 break;
1965
1966 case BRW_OPCODE_IF:
1967 if (inst->src[0].file != BAD_FILE) {
1968 /* The instruction has an embedded compare (only allowed on gen6) */
1969 assert(devinfo->gen == 6);
1970 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1971 } else {
1972 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1973 }
1974 break;
1975
1976 case BRW_OPCODE_ELSE:
1977 brw_ELSE(p);
1978 break;
1979 case BRW_OPCODE_ENDIF:
1980 brw_ENDIF(p);
1981 break;
1982
1983 case BRW_OPCODE_DO:
1984 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1985 break;
1986
1987 case BRW_OPCODE_BREAK:
1988 brw_BREAK(p);
1989 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1990 break;
1991 case BRW_OPCODE_CONTINUE:
1992 brw_CONT(p);
1993 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1994 break;
1995
1996 case BRW_OPCODE_WHILE:
1997 brw_WHILE(p);
1998 loop_count++;
1999 break;
2000
2001 case SHADER_OPCODE_RCP:
2002 case SHADER_OPCODE_RSQ:
2003 case SHADER_OPCODE_SQRT:
2004 case SHADER_OPCODE_EXP2:
2005 case SHADER_OPCODE_LOG2:
2006 case SHADER_OPCODE_SIN:
2007 case SHADER_OPCODE_COS:
2008 assert(devinfo->gen < 6 || inst->mlen == 0);
2009 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2010 if (devinfo->gen >= 7) {
2011 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2012 brw_null_reg());
2013 } else if (devinfo->gen == 6) {
2014 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2015 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2016 generate_math_g45(inst, dst, src[0]);
2017 } else {
2018 generate_math_gen4(inst, dst, src[0]);
2019 }
2020 break;
2021 case SHADER_OPCODE_INT_QUOTIENT:
2022 case SHADER_OPCODE_INT_REMAINDER:
2023 case SHADER_OPCODE_POW:
2024 assert(devinfo->gen < 6 || inst->mlen == 0);
2025 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2026 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2027 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2028 } else if (devinfo->gen >= 6) {
2029 generate_math_gen6(inst, dst, src[0], src[1]);
2030 } else {
2031 generate_math_gen4(inst, dst, src[0]);
2032 }
2033 break;
2034 case FS_OPCODE_CINTERP:
2035 brw_MOV(p, dst, src[0]);
2036 break;
2037 case FS_OPCODE_LINTERP:
2038 generate_linterp(inst, dst, src);
2039 break;
2040 case FS_OPCODE_PIXEL_X:
2041 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2042 src[0].subnr = 0 * type_sz(src[0].type);
2043 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2044 break;
2045 case FS_OPCODE_PIXEL_Y:
2046 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2047 src[0].subnr = 4 * type_sz(src[0].type);
2048 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2049 break;
2050 case FS_OPCODE_GET_BUFFER_SIZE:
2051 generate_get_buffer_size(inst, dst, src[0], src[1]);
2052 break;
2053 case SHADER_OPCODE_TEX:
2054 case FS_OPCODE_TXB:
2055 case SHADER_OPCODE_TXD:
2056 case SHADER_OPCODE_TXF:
2057 case SHADER_OPCODE_TXF_CMS:
2058 case SHADER_OPCODE_TXF_CMS_W:
2059 case SHADER_OPCODE_TXF_UMS:
2060 case SHADER_OPCODE_TXF_MCS:
2061 case SHADER_OPCODE_TXL:
2062 case SHADER_OPCODE_TXS:
2063 case SHADER_OPCODE_LOD:
2064 case SHADER_OPCODE_TG4:
2065 case SHADER_OPCODE_TG4_OFFSET:
2066 case SHADER_OPCODE_SAMPLEINFO:
2067 generate_tex(inst, dst, src[0], src[1]);
2068 break;
2069 case FS_OPCODE_DDX_COARSE:
2070 case FS_OPCODE_DDX_FINE:
2071 generate_ddx(inst->opcode, dst, src[0]);
2072 break;
2073 case FS_OPCODE_DDY_COARSE:
2074 case FS_OPCODE_DDY_FINE:
2075 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2076 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2077 break;
2078
2079 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2080 generate_scratch_write(inst, src[0]);
2081 spill_count++;
2082 break;
2083
2084 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2085 generate_scratch_read(inst, dst);
2086 fill_count++;
2087 break;
2088
2089 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2090 generate_scratch_read_gen7(inst, dst);
2091 fill_count++;
2092 break;
2093
2094 case SHADER_OPCODE_MOV_INDIRECT:
2095 generate_mov_indirect(inst, dst, src[0], src[1]);
2096 break;
2097
2098 case SHADER_OPCODE_URB_READ_SIMD8:
2099 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2100 generate_urb_read(inst, dst, src[0]);
2101 break;
2102
2103 case SHADER_OPCODE_URB_WRITE_SIMD8:
2104 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2105 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2106 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2107 generate_urb_write(inst, src[0]);
2108 break;
2109
2110 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2111 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2112 break;
2113
2114 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2115 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2116 break;
2117
2118 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2119 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2120 break;
2121
2122 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2123 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2124 break;
2125
2126 case FS_OPCODE_REP_FB_WRITE:
2127 case FS_OPCODE_FB_WRITE:
2128 generate_fb_write(inst, src[0]);
2129 break;
2130
2131 case FS_OPCODE_BLORP_FB_WRITE:
2132 generate_blorp_fb_write(inst);
2133 break;
2134
2135 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2136 generate_mov_dispatch_to_flags(inst);
2137 break;
2138
2139 case FS_OPCODE_DISCARD_JUMP:
2140 generate_discard_jump(inst);
2141 break;
2142
2143 case SHADER_OPCODE_SHADER_TIME_ADD:
2144 generate_shader_time_add(inst, src[0], src[1], src[2]);
2145 break;
2146
2147 case SHADER_OPCODE_UNTYPED_ATOMIC:
2148 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2149 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2150 inst->mlen, !inst->dst.is_null());
2151 break;
2152
2153 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2154 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2155 brw_untyped_surface_read(p, dst, src[0], src[1],
2156 inst->mlen, src[2].ud);
2157 break;
2158
2159 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2160 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2161 brw_untyped_surface_write(p, src[0], src[1],
2162 inst->mlen, src[2].ud);
2163 break;
2164
2165 case SHADER_OPCODE_TYPED_ATOMIC:
2166 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2167 brw_typed_atomic(p, dst, src[0], src[1],
2168 src[2].ud, inst->mlen, !inst->dst.is_null());
2169 break;
2170
2171 case SHADER_OPCODE_TYPED_SURFACE_READ:
2172 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2173 brw_typed_surface_read(p, dst, src[0], src[1],
2174 inst->mlen, src[2].ud);
2175 break;
2176
2177 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2178 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2179 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2180 break;
2181
2182 case SHADER_OPCODE_MEMORY_FENCE:
2183 brw_memory_fence(p, dst);
2184 break;
2185
2186 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2187 generate_set_simd4x2_offset(inst, dst, src[0]);
2188 break;
2189
2190 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2191 brw_find_live_channel(p, dst);
2192 break;
2193
2194 case SHADER_OPCODE_BROADCAST:
2195 brw_broadcast(p, dst, src[0], src[1]);
2196 break;
2197
2198 case FS_OPCODE_SET_SAMPLE_ID:
2199 generate_set_sample_id(inst, dst, src[0], src[1]);
2200 break;
2201
2202 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2203 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2204 break;
2205
2206 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2207 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2208 generate_unpack_half_2x16_split(inst, dst, src[0]);
2209 break;
2210
2211 case FS_OPCODE_PLACEHOLDER_HALT:
2212 /* This is the place where the final HALT needs to be inserted if
2213 * we've emitted any discards. If not, this will emit no code.
2214 */
2215 if (!patch_discard_jumps_to_fb_writes()) {
2216 if (unlikely(debug_flag)) {
2217 annotation.ann_count--;
2218 }
2219 }
2220 break;
2221
2222 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2223 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2224 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2225 break;
2226
2227 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2228 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2229 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2230 break;
2231
2232 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2233 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2234 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2235 break;
2236
2237 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2238 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2239 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2240 break;
2241
2242 case CS_OPCODE_CS_TERMINATE:
2243 generate_cs_terminate(inst, src[0]);
2244 break;
2245
2246 case SHADER_OPCODE_BARRIER:
2247 generate_barrier(inst, src[0]);
2248 break;
2249
2250 case FS_OPCODE_PACK_STENCIL_REF:
2251 generate_stencil_ref_packing(inst, dst, src[0]);
2252 break;
2253
2254 default:
2255 unreachable("Unsupported opcode");
2256
2257 case SHADER_OPCODE_LOAD_PAYLOAD:
2258 unreachable("Should be lowered by lower_load_payload()");
2259 }
2260
2261 if (multiple_instructions_emitted)
2262 continue;
2263
2264 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2265 assert(p->next_insn_offset == last_insn_offset + 16 ||
2266 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2267 "emitting more than 1 instruction");
2268
2269 brw_inst *last = &p->store[last_insn_offset / 16];
2270
2271 if (inst->conditional_mod)
2272 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2273 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2274 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2275 }
2276 }
2277
2278 brw_set_uip_jip(p);
2279 annotation_finalize(&annotation, p->next_insn_offset);
2280
2281 #ifndef NDEBUG
2282 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2283 #else
2284 if (unlikely(debug_flag))
2285 brw_validate_instructions(p, start_offset, &annotation);
2286 #endif
2287
2288 int before_size = p->next_insn_offset - start_offset;
2289 brw_compact_instructions(p, start_offset, annotation.ann_count,
2290 annotation.ann);
2291 int after_size = p->next_insn_offset - start_offset;
2292
2293 if (unlikely(debug_flag)) {
2294 fprintf(stderr, "Native code for %s\n"
2295 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2296 " bytes (%.0f%%)\n",
2297 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2298 spill_count, fill_count, promoted_constants, before_size, after_size,
2299 100.0f * (before_size - after_size) / before_size);
2300
2301 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2302 p->devinfo);
2303 ralloc_free(annotation.mem_ctx);
2304 }
2305 assert(validated);
2306
2307 compiler->shader_debug_log(log_data,
2308 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2309 "%d:%d spills:fills, Promoted %u constants, "
2310 "compacted %d to %d bytes.\n",
2311 stage_abbrev, dispatch_width, before_size / 16,
2312 loop_count, cfg->cycle_count, spill_count,
2313 fill_count, promoted_constants, before_size,
2314 after_size);
2315
2316 return start_offset;
2317 }
2318
2319 const unsigned *
2320 fs_generator::get_assembly(unsigned int *assembly_size)
2321 {
2322 return brw_get_program(p, assembly_size);
2323 }