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[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "main/macros.h"
31 #include "brw_context.h"
32 #include "brw_eu.h"
33 #include "brw_fs.h"
34 #include "brw_cfg.h"
35
36 static enum brw_reg_file
37 brw_file_from_reg(fs_reg *reg)
38 {
39 switch (reg->file) {
40 case ARF:
41 return BRW_ARCHITECTURE_REGISTER_FILE;
42 case FIXED_GRF:
43 case VGRF:
44 return BRW_GENERAL_REGISTER_FILE;
45 case MRF:
46 return BRW_MESSAGE_REGISTER_FILE;
47 case IMM:
48 return BRW_IMMEDIATE_VALUE;
49 case BAD_FILE:
50 case ATTR:
51 case UNIFORM:
52 unreachable("not reached");
53 }
54 return BRW_ARCHITECTURE_REGISTER_FILE;
55 }
56
57 static struct brw_reg
58 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else if (inst->exec_size < 8) {
70 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
71 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
72 inst->exec_size, reg->stride);
73 } else {
74 /* From the Haswell PRM:
75 *
76 * VertStride must be used to cross GRF register boundaries. This
77 * rule implies that elements within a 'Width' cannot cross GRF
78 * boundaries.
79 *
80 * So, for registers with width > 8, we have to use a width of 8
81 * and trust the compression state to sort out the exec size.
82 */
83 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
84 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
85 }
86
87 brw_reg = retype(brw_reg, reg->type);
88 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
89 brw_reg.abs = reg->abs;
90 brw_reg.negate = reg->negate;
91 break;
92 case ARF:
93 case FIXED_GRF:
94 case IMM:
95 brw_reg = reg->as_brw_reg();
96 break;
97 case BAD_FILE:
98 /* Probably unused. */
99 brw_reg = brw_null_reg();
100 break;
101 case ATTR:
102 case UNIFORM:
103 unreachable("not reached");
104 }
105
106 return brw_reg;
107 }
108
109 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
110 void *mem_ctx,
111 const void *key,
112 struct brw_stage_prog_data *prog_data,
113 unsigned promoted_constants,
114 bool runtime_check_aads_emit,
115 const char *stage_abbrev)
116
117 : compiler(compiler), log_data(log_data),
118 devinfo(compiler->devinfo), key(key),
119 prog_data(prog_data),
120 promoted_constants(promoted_constants),
121 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
122 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
123 {
124 p = rzalloc(mem_ctx, struct brw_codegen);
125 brw_init_codegen(devinfo, p, mem_ctx);
126 }
127
128 fs_generator::~fs_generator()
129 {
130 }
131
132 class ip_record : public exec_node {
133 public:
134 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
135
136 ip_record(int ip)
137 {
138 this->ip = ip;
139 }
140
141 int ip;
142 };
143
144 bool
145 fs_generator::patch_discard_jumps_to_fb_writes()
146 {
147 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
148 return false;
149
150 int scale = brw_jump_scale(p->devinfo);
151
152 /* There is a somewhat strange undocumented requirement of using
153 * HALT, according to the simulator. If some channel has HALTed to
154 * a particular UIP, then by the end of the program, every channel
155 * must have HALTed to that UIP. Furthermore, the tracking is a
156 * stack, so you can't do the final halt of a UIP after starting
157 * halting to a new UIP.
158 *
159 * Symptoms of not emitting this instruction on actual hardware
160 * included GPU hangs and sparkly rendering on the piglit discard
161 * tests.
162 */
163 brw_inst *last_halt = gen6_HALT(p);
164 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
165 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
166
167 int ip = p->nr_insn;
168
169 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
170 brw_inst *patch = &p->store[patch_ip->ip];
171
172 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
173 /* HALT takes a half-instruction distance from the pre-incremented IP. */
174 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
175 }
176
177 this->discard_halt_patches.make_empty();
178 return true;
179 }
180
181 void
182 fs_generator::fire_fb_write(fs_inst *inst,
183 struct brw_reg payload,
184 struct brw_reg implied_header,
185 GLuint nr)
186 {
187 uint32_t msg_control;
188
189 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
190
191 if (devinfo->gen < 6) {
192 brw_push_insn_state(p);
193 brw_set_default_exec_size(p, BRW_EXECUTE_8);
194 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
195 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
196 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
197 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
198 brw_pop_insn_state(p);
199 }
200
201 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
202 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
203 else if (prog_data->dual_src_blend) {
204 if (!inst->force_sechalf)
205 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
206 else
207 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
208 } else if (inst->exec_size == 16)
209 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
210 else
211 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
212
213 uint32_t surf_index =
214 prog_data->binding_table.render_target_start + inst->target;
215
216 bool last_render_target = inst->eot ||
217 (prog_data->dual_src_blend && dispatch_width == 16);
218
219
220 brw_fb_WRITE(p,
221 dispatch_width,
222 payload,
223 implied_header,
224 msg_control,
225 surf_index,
226 nr,
227 0,
228 inst->eot,
229 last_render_target,
230 inst->header_size != 0);
231
232 brw_mark_surface_used(&prog_data->base, surf_index);
233 }
234
235 void
236 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
237 {
238 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
239 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
240 struct brw_reg implied_header;
241
242 if (devinfo->gen < 8 && !devinfo->is_haswell) {
243 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
244 }
245
246 if (inst->base_mrf >= 0)
247 payload = brw_message_reg(inst->base_mrf);
248
249 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
250 * move, here's g1.
251 */
252 if (inst->header_size != 0) {
253 brw_push_insn_state(p);
254 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
255 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
256 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
257 brw_set_default_flag_reg(p, 0, 0);
258
259 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
260 * present.
261 */
262 if (prog_data->uses_kill) {
263 struct brw_reg pixel_mask;
264
265 if (devinfo->gen >= 6)
266 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
267 else
268 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
269
270 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
271 }
272
273 if (devinfo->gen >= 6) {
274 brw_push_insn_state(p);
275 brw_set_default_exec_size(p, BRW_EXECUTE_16);
276 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
277 brw_MOV(p,
278 retype(payload, BRW_REGISTER_TYPE_UD),
279 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
280 brw_pop_insn_state(p);
281
282 if (inst->target > 0 && key->replicate_alpha) {
283 /* Set "Source0 Alpha Present to RenderTarget" bit in message
284 * header.
285 */
286 brw_OR(p,
287 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
288 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
289 brw_imm_ud(0x1 << 11));
290 }
291
292 if (inst->target > 0) {
293 /* Set the render target index for choosing BLEND_STATE. */
294 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
295 BRW_REGISTER_TYPE_UD),
296 brw_imm_ud(inst->target));
297 }
298
299 /* Set computes stencil to render target */
300 if (prog_data->computed_stencil) {
301 brw_OR(p,
302 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
303 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
304 brw_imm_ud(0x1 << 14));
305 }
306
307 implied_header = brw_null_reg();
308 } else {
309 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
310 }
311
312 brw_pop_insn_state(p);
313 } else {
314 implied_header = brw_null_reg();
315 }
316
317 if (!runtime_check_aads_emit) {
318 fire_fb_write(inst, payload, implied_header, inst->mlen);
319 } else {
320 /* This can only happen in gen < 6 */
321 assert(devinfo->gen < 6);
322
323 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
324
325 /* Check runtime bit to detect if we have to send AA data or not */
326 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
327 brw_AND(p,
328 v1_null_ud,
329 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
330 brw_imm_ud(1<<26));
331 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
332
333 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
334 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
335 {
336 /* Don't send AA data */
337 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
338 }
339 brw_land_fwd_jump(p, jmp);
340 fire_fb_write(inst, payload, implied_header, inst->mlen);
341 }
342 }
343
344 void
345 fs_generator::generate_mov_indirect(fs_inst *inst,
346 struct brw_reg dst,
347 struct brw_reg reg,
348 struct brw_reg indirect_byte_offset)
349 {
350 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
351 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
352
353 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
354
355 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
356 struct brw_reg addr = vec8(brw_address_reg(0));
357
358 /* The destination stride of an instruction (in bytes) must be greater
359 * than or equal to the size of the rest of the instruction. Since the
360 * address register is of type UW, we can't use a D-type instruction.
361 * In order to get around this, re re-type to UW and use a stride.
362 */
363 indirect_byte_offset =
364 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
365
366 /* Prior to Broadwell, there are only 8 address registers. */
367 assert(inst->exec_size == 8 || devinfo->gen >= 8);
368
369 brw_MOV(p, addr, indirect_byte_offset);
370 brw_inst_set_mask_control(devinfo, brw_last_inst, BRW_MASK_DISABLE);
371 brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
372 }
373
374 void
375 fs_generator::generate_urb_read(fs_inst *inst,
376 struct brw_reg dst,
377 struct brw_reg header)
378 {
379 assert(header.file == BRW_GENERAL_REGISTER_FILE);
380 assert(header.type == BRW_REGISTER_TYPE_UD);
381
382 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
383 brw_set_dest(p, send, dst);
384 brw_set_src0(p, send, header);
385 brw_set_src1(p, send, brw_imm_ud(0u));
386
387 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
388 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
389
390 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
391 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
392
393 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
394 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
395 brw_inst_set_header_present(p->devinfo, send, true);
396 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
397 }
398
399 void
400 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
401 {
402 brw_inst *insn;
403
404 insn = brw_next_insn(p, BRW_OPCODE_SEND);
405
406 brw_set_dest(p, insn, brw_null_reg());
407 brw_set_src0(p, insn, payload);
408 brw_set_src1(p, insn, brw_imm_d(0));
409
410 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
411 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
412
413 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
414 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
415 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
416
417 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
418 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
419 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
420
421 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
422 brw_inst_set_rlen(p->devinfo, insn, 0);
423 brw_inst_set_eot(p->devinfo, insn, inst->eot);
424 brw_inst_set_header_present(p->devinfo, insn, true);
425 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
426 }
427
428 void
429 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
430 {
431 struct brw_inst *insn;
432
433 insn = brw_next_insn(p, BRW_OPCODE_SEND);
434
435 brw_set_dest(p, insn, brw_null_reg());
436 brw_set_src0(p, insn, payload);
437 brw_set_src1(p, insn, brw_imm_d(0));
438
439 /* Terminate a compute shader by sending a message to the thread spawner.
440 */
441 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
442 brw_inst_set_mlen(devinfo, insn, 1);
443 brw_inst_set_rlen(devinfo, insn, 0);
444 brw_inst_set_eot(devinfo, insn, inst->eot);
445 brw_inst_set_header_present(devinfo, insn, false);
446
447 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
448 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
449
450 /* Note that even though the thread has a URB resource associated with it,
451 * we set the "do not dereference URB" bit, because the URB resource is
452 * managed by the fixed-function unit, so it will free it automatically.
453 */
454 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
455
456 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
457 }
458
459 void
460 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
461 struct brw_reg dst,
462 struct brw_reg src)
463 {
464 assert(dispatch_width == 8);
465 assert(devinfo->gen >= 9);
466
467 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
468 * Presumably, in order to save memory bandwidth, the stencil reference
469 * values written from the FS need to be packed into 2 dwords (this makes
470 * sense because the stencil values are limited to 1 byte each and a SIMD8
471 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
472 *
473 * The spec is confusing here because in the payload definition of MDP_RTW_S8
474 * (Message Data Payload for Render Target Writes with Stencil 8b) the
475 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
476 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
477 * packed values specified above and diagrammed below:
478 *
479 * 31 0
480 * --------------------------------
481 * DW | |
482 * 2-7 | IGNORED |
483 * | |
484 * --------------------------------
485 * DW1 | STC | STC | STC | STC |
486 * | slot7 | slot6 | slot5 | slot4|
487 * --------------------------------
488 * DW0 | STC | STC | STC | STC |
489 * | slot3 | slot2 | slot1 | slot0|
490 * --------------------------------
491 */
492
493 src.vstride = BRW_VERTICAL_STRIDE_4;
494 src.width = BRW_WIDTH_1;
495 src.hstride = BRW_HORIZONTAL_STRIDE_0;
496 assert(src.type == BRW_REGISTER_TYPE_UB);
497 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
498 }
499
500 void
501 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
502 {
503 brw_barrier(p, src);
504 brw_WAIT(p);
505 }
506
507 void
508 fs_generator::generate_blorp_fb_write(fs_inst *inst)
509 {
510 brw_fb_WRITE(p,
511 16 /* dispatch_width */,
512 brw_message_reg(inst->base_mrf),
513 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
514 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
515 inst->target,
516 inst->mlen,
517 0,
518 true,
519 true,
520 inst->header_size != 0);
521 }
522
523 void
524 fs_generator::generate_linterp(fs_inst *inst,
525 struct brw_reg dst, struct brw_reg *src)
526 {
527 /* PLN reads:
528 * / in SIMD16 \
529 * -----------------------------------
530 * | src1+0 | src1+1 | src1+2 | src1+3 |
531 * |-----------------------------------|
532 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
533 * -----------------------------------
534 *
535 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
536 *
537 * -----------------------------------
538 * | src1+0 | src1+1 | src1+2 | src1+3 |
539 * |-----------------------------------|
540 * |(x0, x1)|(y0, y1)| | | in SIMD8
541 * |-----------------------------------|
542 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
543 * -----------------------------------
544 *
545 * See also: emit_interpolation_setup_gen4().
546 */
547 struct brw_reg delta_x = src[0];
548 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
549 struct brw_reg interp = src[1];
550
551 if (devinfo->has_pln &&
552 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
553 brw_PLN(p, dst, interp, delta_x);
554 } else {
555 brw_LINE(p, brw_null_reg(), interp, delta_x);
556 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
557 }
558 }
559
560 void
561 fs_generator::generate_math_gen6(fs_inst *inst,
562 struct brw_reg dst,
563 struct brw_reg src0,
564 struct brw_reg src1)
565 {
566 int op = brw_math_function(inst->opcode);
567 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
568
569 if (dispatch_width == 8) {
570 gen6_math(p, dst, op, src0, src1);
571 } else if (dispatch_width == 16) {
572 brw_push_insn_state(p);
573 brw_set_default_exec_size(p, BRW_EXECUTE_8);
574 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
575 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
576 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
577 gen6_math(p, sechalf(dst), op, sechalf(src0),
578 binop ? sechalf(src1) : brw_null_reg());
579 brw_pop_insn_state(p);
580 }
581 }
582
583 void
584 fs_generator::generate_math_gen4(fs_inst *inst,
585 struct brw_reg dst,
586 struct brw_reg src)
587 {
588 int op = brw_math_function(inst->opcode);
589
590 assert(inst->mlen >= 1);
591
592 if (dispatch_width == 8) {
593 gen4_math(p, dst,
594 op,
595 inst->base_mrf, src,
596 BRW_MATH_PRECISION_FULL);
597 } else if (dispatch_width == 16) {
598 brw_set_default_exec_size(p, BRW_EXECUTE_8);
599 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
600 gen4_math(p, firsthalf(dst),
601 op,
602 inst->base_mrf, firsthalf(src),
603 BRW_MATH_PRECISION_FULL);
604 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
605 gen4_math(p, sechalf(dst),
606 op,
607 inst->base_mrf + 1, sechalf(src),
608 BRW_MATH_PRECISION_FULL);
609
610 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
611 }
612 }
613
614 void
615 fs_generator::generate_math_g45(fs_inst *inst,
616 struct brw_reg dst,
617 struct brw_reg src)
618 {
619 if (inst->opcode == SHADER_OPCODE_POW ||
620 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
621 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
622 generate_math_gen4(inst, dst, src);
623 return;
624 }
625
626 int op = brw_math_function(inst->opcode);
627
628 assert(inst->mlen >= 1);
629
630 gen4_math(p, dst,
631 op,
632 inst->base_mrf, src,
633 BRW_MATH_PRECISION_FULL);
634 }
635
636 void
637 fs_generator::generate_get_buffer_size(fs_inst *inst,
638 struct brw_reg dst,
639 struct brw_reg src,
640 struct brw_reg surf_index)
641 {
642 assert(devinfo->gen >= 7);
643 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
644
645 uint32_t simd_mode;
646 int rlen = 4;
647
648 switch (inst->exec_size) {
649 case 8:
650 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
651 break;
652 case 16:
653 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
654 break;
655 default:
656 unreachable("Invalid width for texture instruction");
657 }
658
659 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
660 rlen = 8;
661 dst = vec16(dst);
662 }
663
664 brw_SAMPLE(p,
665 retype(dst, BRW_REGISTER_TYPE_UW),
666 inst->base_mrf,
667 src,
668 surf_index.ud,
669 0,
670 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
671 rlen, /* response length */
672 inst->mlen,
673 inst->header_size > 0,
674 simd_mode,
675 BRW_SAMPLER_RETURN_FORMAT_SINT32);
676
677 brw_mark_surface_used(prog_data, surf_index.ud);
678 }
679
680 void
681 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
682 struct brw_reg sampler_index)
683 {
684 int msg_type = -1;
685 int rlen = 4;
686 uint32_t simd_mode;
687 uint32_t return_format;
688 bool is_combined_send = inst->eot;
689
690 switch (dst.type) {
691 case BRW_REGISTER_TYPE_D:
692 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
693 break;
694 case BRW_REGISTER_TYPE_UD:
695 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
696 break;
697 default:
698 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
699 break;
700 }
701
702 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
703 * is set as part of the message descriptor. On gen4, the PRM seems to
704 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
705 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
706 * gone from the message descriptor entirely and you just get UINT32 all
707 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
708 * just stomp it to UINT32 all the time.
709 */
710 if (inst->opcode == SHADER_OPCODE_TXS)
711 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
712
713 switch (inst->exec_size) {
714 case 8:
715 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
716 break;
717 case 16:
718 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
719 break;
720 default:
721 unreachable("Invalid width for texture instruction");
722 }
723
724 if (devinfo->gen >= 5) {
725 switch (inst->opcode) {
726 case SHADER_OPCODE_TEX:
727 if (inst->shadow_compare) {
728 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
729 } else {
730 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
731 }
732 break;
733 case FS_OPCODE_TXB:
734 if (inst->shadow_compare) {
735 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
736 } else {
737 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
738 }
739 break;
740 case SHADER_OPCODE_TXL:
741 if (inst->shadow_compare) {
742 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
743 } else {
744 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
745 }
746 break;
747 case SHADER_OPCODE_TXS:
748 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
749 break;
750 case SHADER_OPCODE_TXD:
751 if (inst->shadow_compare) {
752 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
753 assert(devinfo->gen >= 8 || devinfo->is_haswell);
754 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
755 } else {
756 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
757 }
758 break;
759 case SHADER_OPCODE_TXF:
760 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
761 break;
762 case SHADER_OPCODE_TXF_CMS_W:
763 assert(devinfo->gen >= 9);
764 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
765 break;
766 case SHADER_OPCODE_TXF_CMS:
767 if (devinfo->gen >= 7)
768 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
769 else
770 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
771 break;
772 case SHADER_OPCODE_TXF_UMS:
773 assert(devinfo->gen >= 7);
774 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
775 break;
776 case SHADER_OPCODE_TXF_MCS:
777 assert(devinfo->gen >= 7);
778 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
779 break;
780 case SHADER_OPCODE_LOD:
781 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
782 break;
783 case SHADER_OPCODE_TG4:
784 if (inst->shadow_compare) {
785 assert(devinfo->gen >= 7);
786 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
787 } else {
788 assert(devinfo->gen >= 6);
789 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
790 }
791 break;
792 case SHADER_OPCODE_TG4_OFFSET:
793 assert(devinfo->gen >= 7);
794 if (inst->shadow_compare) {
795 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
796 } else {
797 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
798 }
799 break;
800 case SHADER_OPCODE_SAMPLEINFO:
801 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
802 break;
803 default:
804 unreachable("not reached");
805 }
806 } else {
807 switch (inst->opcode) {
808 case SHADER_OPCODE_TEX:
809 /* Note that G45 and older determines shadow compare and dispatch width
810 * from message length for most messages.
811 */
812 if (inst->exec_size == 8) {
813 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
814 if (inst->shadow_compare) {
815 assert(inst->mlen == 6);
816 } else {
817 assert(inst->mlen <= 4);
818 }
819 } else {
820 if (inst->shadow_compare) {
821 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
822 assert(inst->mlen == 9);
823 } else {
824 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
825 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
826 }
827 }
828 break;
829 case FS_OPCODE_TXB:
830 if (inst->shadow_compare) {
831 assert(inst->exec_size == 8);
832 assert(inst->mlen == 6);
833 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
834 } else {
835 assert(inst->mlen == 9);
836 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
837 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
838 }
839 break;
840 case SHADER_OPCODE_TXL:
841 if (inst->shadow_compare) {
842 assert(inst->exec_size == 8);
843 assert(inst->mlen == 6);
844 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
845 } else {
846 assert(inst->mlen == 9);
847 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
848 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
849 }
850 break;
851 case SHADER_OPCODE_TXD:
852 /* There is no sample_d_c message; comparisons are done manually */
853 assert(inst->exec_size == 8);
854 assert(inst->mlen == 7 || inst->mlen == 10);
855 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
856 break;
857 case SHADER_OPCODE_TXF:
858 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
859 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
860 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
861 break;
862 case SHADER_OPCODE_TXS:
863 assert(inst->mlen == 3);
864 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
865 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
866 break;
867 default:
868 unreachable("not reached");
869 }
870 }
871 assert(msg_type != -1);
872
873 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
874 rlen = 8;
875 dst = vec16(dst);
876 }
877
878 if (is_combined_send) {
879 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
880 rlen = 0;
881 }
882
883 assert(devinfo->gen < 7 || inst->header_size == 0 ||
884 src.file == BRW_GENERAL_REGISTER_FILE);
885
886 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
887
888 /* Load the message header if present. If there's a texture offset,
889 * we need to set it up explicitly and load the offset bitfield.
890 * Otherwise, we can use an implied move from g0 to the first message reg.
891 */
892 if (inst->header_size != 0) {
893 if (devinfo->gen < 6 && !inst->offset) {
894 /* Set up an implied move from g0 to the MRF. */
895 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
896 } else {
897 struct brw_reg header_reg;
898
899 if (devinfo->gen >= 7) {
900 header_reg = src;
901 } else {
902 assert(inst->base_mrf != -1);
903 header_reg = brw_message_reg(inst->base_mrf);
904 }
905
906 brw_push_insn_state(p);
907 brw_set_default_exec_size(p, BRW_EXECUTE_8);
908 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
909 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
910 /* Explicitly set up the message header by copying g0 to the MRF. */
911 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
912
913 if (inst->offset) {
914 /* Set the offset bits in DWord 2. */
915 brw_MOV(p, get_element_ud(header_reg, 2),
916 brw_imm_ud(inst->offset));
917 }
918
919 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
920 brw_pop_insn_state(p);
921 }
922 }
923
924 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
925 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
926 ? prog_data->binding_table.gather_texture_start
927 : prog_data->binding_table.texture_start;
928
929 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
930 uint32_t sampler = sampler_index.ud;
931
932 brw_SAMPLE(p,
933 retype(dst, BRW_REGISTER_TYPE_UW),
934 inst->base_mrf,
935 src,
936 sampler + base_binding_table_index,
937 sampler % 16,
938 msg_type,
939 rlen,
940 inst->mlen,
941 inst->header_size != 0,
942 simd_mode,
943 return_format);
944
945 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
946 } else {
947 /* Non-const sampler index */
948
949 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
950 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
951
952 brw_push_insn_state(p);
953 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
954 brw_set_default_access_mode(p, BRW_ALIGN_1);
955
956 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
957 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
958 if (base_binding_table_index)
959 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
960 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
961
962 brw_pop_insn_state(p);
963
964 /* dst = send(offset, a0.0 | <descriptor>) */
965 brw_inst *insn = brw_send_indirect_message(
966 p, BRW_SFID_SAMPLER, dst, src, addr);
967 brw_set_sampler_message(p, insn,
968 0 /* surface */,
969 0 /* sampler */,
970 msg_type,
971 rlen,
972 inst->mlen /* mlen */,
973 inst->header_size != 0 /* header */,
974 simd_mode,
975 return_format);
976
977 /* visitor knows more than we do about the surface limit required,
978 * so has already done marking.
979 */
980 }
981
982 if (is_combined_send) {
983 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
984 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
985 }
986 }
987
988
989 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
990 * looking like:
991 *
992 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
993 *
994 * Ideally, we want to produce:
995 *
996 * DDX DDY
997 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
998 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
999 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1000 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1001 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1002 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1003 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1004 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1005 *
1006 * and add another set of two more subspans if in 16-pixel dispatch mode.
1007 *
1008 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1009 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1010 * pair. But the ideal approximation may impose a huge performance cost on
1011 * sample_d. On at least Haswell, sample_d instruction does some
1012 * optimizations if the same LOD is used for all pixels in the subspan.
1013 *
1014 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1015 * appropriate swizzling.
1016 */
1017 void
1018 fs_generator::generate_ddx(enum opcode opcode,
1019 struct brw_reg dst, struct brw_reg src)
1020 {
1021 unsigned vstride, width;
1022
1023 if (opcode == FS_OPCODE_DDX_FINE) {
1024 /* produce accurate derivatives */
1025 vstride = BRW_VERTICAL_STRIDE_2;
1026 width = BRW_WIDTH_2;
1027 } else {
1028 /* replicate the derivative at the top-left pixel to other pixels */
1029 vstride = BRW_VERTICAL_STRIDE_4;
1030 width = BRW_WIDTH_4;
1031 }
1032
1033 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1034 src.negate, src.abs,
1035 BRW_REGISTER_TYPE_F,
1036 vstride,
1037 width,
1038 BRW_HORIZONTAL_STRIDE_0,
1039 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1040 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1041 src.negate, src.abs,
1042 BRW_REGISTER_TYPE_F,
1043 vstride,
1044 width,
1045 BRW_HORIZONTAL_STRIDE_0,
1046 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1047 brw_ADD(p, dst, src0, negate(src1));
1048 }
1049
1050 /* The negate_value boolean is used to negate the derivative computation for
1051 * FBOs, since they place the origin at the upper left instead of the lower
1052 * left.
1053 */
1054 void
1055 fs_generator::generate_ddy(enum opcode opcode,
1056 struct brw_reg dst, struct brw_reg src,
1057 bool negate_value)
1058 {
1059 if (opcode == FS_OPCODE_DDY_FINE) {
1060 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1061 * Region Restrictions):
1062 *
1063 * In Align16 access mode, SIMD16 is not allowed for DW operations
1064 * and SIMD8 is not allowed for DF operations.
1065 *
1066 * In this context, "DW operations" means "operations acting on 32-bit
1067 * values", so it includes operations on floats.
1068 *
1069 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1070 * (Instruction Compression -> Rules and Restrictions):
1071 *
1072 * A compressed instruction must be in Align1 access mode. Align16
1073 * mode instructions cannot be compressed.
1074 *
1075 * Similar text exists in the g45 PRM.
1076 *
1077 * On these platforms, if we're building a SIMD16 shader, we need to
1078 * manually unroll to a pair of SIMD8 instructions.
1079 */
1080 bool unroll_to_simd8 =
1081 (dispatch_width == 16 &&
1082 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1083
1084 /* produce accurate derivatives */
1085 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1086 src.negate, src.abs,
1087 BRW_REGISTER_TYPE_F,
1088 BRW_VERTICAL_STRIDE_4,
1089 BRW_WIDTH_4,
1090 BRW_HORIZONTAL_STRIDE_1,
1091 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1092 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1093 src.negate, src.abs,
1094 BRW_REGISTER_TYPE_F,
1095 BRW_VERTICAL_STRIDE_4,
1096 BRW_WIDTH_4,
1097 BRW_HORIZONTAL_STRIDE_1,
1098 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1099 brw_push_insn_state(p);
1100 brw_set_default_access_mode(p, BRW_ALIGN_16);
1101 if (unroll_to_simd8) {
1102 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1103 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1104 if (negate_value) {
1105 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1106 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1107 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1108 } else {
1109 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1110 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1111 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1112 }
1113 } else {
1114 if (negate_value)
1115 brw_ADD(p, dst, src1, negate(src0));
1116 else
1117 brw_ADD(p, dst, src0, negate(src1));
1118 }
1119 brw_pop_insn_state(p);
1120 } else {
1121 /* replicate the derivative at the top-left pixel to other pixels */
1122 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1123 src.negate, src.abs,
1124 BRW_REGISTER_TYPE_F,
1125 BRW_VERTICAL_STRIDE_4,
1126 BRW_WIDTH_4,
1127 BRW_HORIZONTAL_STRIDE_0,
1128 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1129 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1130 src.negate, src.abs,
1131 BRW_REGISTER_TYPE_F,
1132 BRW_VERTICAL_STRIDE_4,
1133 BRW_WIDTH_4,
1134 BRW_HORIZONTAL_STRIDE_0,
1135 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1136 if (negate_value)
1137 brw_ADD(p, dst, src1, negate(src0));
1138 else
1139 brw_ADD(p, dst, src0, negate(src1));
1140 }
1141 }
1142
1143 void
1144 fs_generator::generate_discard_jump(fs_inst *inst)
1145 {
1146 assert(devinfo->gen >= 6);
1147
1148 /* This HALT will be patched up at FB write time to point UIP at the end of
1149 * the program, and at brw_uip_jip() JIP will be set to the end of the
1150 * current block (or the program).
1151 */
1152 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1153
1154 brw_push_insn_state(p);
1155 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1156 gen6_HALT(p);
1157 brw_pop_insn_state(p);
1158 }
1159
1160 void
1161 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1162 {
1163 assert(inst->mlen != 0);
1164
1165 brw_MOV(p,
1166 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1167 retype(src, BRW_REGISTER_TYPE_UD));
1168 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1169 inst->exec_size / 8, inst->offset);
1170 }
1171
1172 void
1173 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1174 {
1175 assert(inst->mlen != 0);
1176
1177 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1178 inst->exec_size / 8, inst->offset);
1179 }
1180
1181 void
1182 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1183 {
1184 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1185 }
1186
1187 void
1188 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1189 struct brw_reg dst,
1190 struct brw_reg index,
1191 struct brw_reg offset)
1192 {
1193 assert(inst->mlen != 0);
1194
1195 assert(index.file == BRW_IMMEDIATE_VALUE &&
1196 index.type == BRW_REGISTER_TYPE_UD);
1197 uint32_t surf_index = index.ud;
1198
1199 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1200 offset.type == BRW_REGISTER_TYPE_UD);
1201 uint32_t read_offset = offset.ud;
1202
1203 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1204 read_offset, surf_index);
1205 }
1206
1207 void
1208 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1209 struct brw_reg dst,
1210 struct brw_reg index,
1211 struct brw_reg offset)
1212 {
1213 assert(index.type == BRW_REGISTER_TYPE_UD);
1214
1215 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1216 /* Reference just the dword we need, to avoid angering validate_reg(). */
1217 offset = brw_vec1_grf(offset.nr, 0);
1218
1219 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1220 * the destination loaded consecutively from the same offset (which appears
1221 * in the first component, and the rest are ignored).
1222 */
1223 dst.width = BRW_WIDTH_4;
1224
1225 struct brw_reg src = offset;
1226 bool header_present = false;
1227
1228 if (devinfo->gen >= 9) {
1229 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1230 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1231 header_present = true;
1232
1233 brw_push_insn_state(p);
1234 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1235 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1236 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1237 brw_set_default_access_mode(p, BRW_ALIGN_1);
1238
1239 brw_MOV(p, get_element_ud(src, 2),
1240 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1241 brw_pop_insn_state(p);
1242 }
1243
1244 if (index.file == BRW_IMMEDIATE_VALUE) {
1245
1246 uint32_t surf_index = index.ud;
1247
1248 brw_push_insn_state(p);
1249 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1250 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1251 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1252 brw_pop_insn_state(p);
1253
1254 brw_set_dest(p, send, dst);
1255 brw_set_src0(p, send, src);
1256 brw_set_sampler_message(p, send,
1257 surf_index,
1258 0, /* LD message ignores sampler unit */
1259 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1260 1, /* rlen */
1261 inst->mlen,
1262 header_present,
1263 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1264 0);
1265 } else {
1266
1267 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1268
1269 brw_push_insn_state(p);
1270 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1271 brw_set_default_access_mode(p, BRW_ALIGN_1);
1272
1273 /* a0.0 = surf_index & 0xff */
1274 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1275 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1276 brw_set_dest(p, insn_and, addr);
1277 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1278 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1279
1280 /* dst = send(payload, a0.0 | <descriptor>) */
1281 brw_inst *insn = brw_send_indirect_message(
1282 p, BRW_SFID_SAMPLER, dst, src, addr);
1283 brw_set_sampler_message(p, insn,
1284 0,
1285 0, /* LD message ignores sampler unit */
1286 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1287 1, /* rlen */
1288 inst->mlen,
1289 header_present,
1290 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1291 0);
1292
1293 brw_pop_insn_state(p);
1294 }
1295 }
1296
1297 void
1298 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1299 struct brw_reg dst,
1300 struct brw_reg index,
1301 struct brw_reg offset)
1302 {
1303 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1304 assert(inst->header_size != 0);
1305 assert(inst->mlen);
1306
1307 assert(index.file == BRW_IMMEDIATE_VALUE &&
1308 index.type == BRW_REGISTER_TYPE_UD);
1309 uint32_t surf_index = index.ud;
1310
1311 uint32_t simd_mode, rlen, msg_type;
1312 if (dispatch_width == 16) {
1313 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1314 rlen = 8;
1315 } else {
1316 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1317 rlen = 4;
1318 }
1319
1320 if (devinfo->gen >= 5)
1321 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1322 else {
1323 /* We always use the SIMD16 message so that we only have to load U, and
1324 * not V or R.
1325 */
1326 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1327 assert(inst->mlen == 3);
1328 assert(inst->regs_written == 8);
1329 rlen = 8;
1330 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1331 }
1332
1333 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1334 BRW_REGISTER_TYPE_D);
1335 brw_MOV(p, offset_mrf, offset);
1336
1337 struct brw_reg header = brw_vec8_grf(0, 0);
1338 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1339
1340 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1341 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1342 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1343 brw_set_src0(p, send, header);
1344 if (devinfo->gen < 6)
1345 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1346
1347 /* Our surface is set up as floats, regardless of what actual data is
1348 * stored in it.
1349 */
1350 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1351 brw_set_sampler_message(p, send,
1352 surf_index,
1353 0, /* sampler (unused) */
1354 msg_type,
1355 rlen,
1356 inst->mlen,
1357 inst->header_size != 0,
1358 simd_mode,
1359 return_format);
1360 }
1361
1362 void
1363 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1364 struct brw_reg dst,
1365 struct brw_reg index,
1366 struct brw_reg offset)
1367 {
1368 assert(devinfo->gen >= 7);
1369 /* Varying-offset pull constant loads are treated as a normal expression on
1370 * gen7, so the fact that it's a send message is hidden at the IR level.
1371 */
1372 assert(inst->header_size == 0);
1373 assert(!inst->mlen);
1374 assert(index.type == BRW_REGISTER_TYPE_UD);
1375
1376 uint32_t simd_mode, rlen, mlen;
1377 if (dispatch_width == 16) {
1378 mlen = 2;
1379 rlen = 8;
1380 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1381 } else {
1382 mlen = 1;
1383 rlen = 4;
1384 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1385 }
1386
1387 if (index.file == BRW_IMMEDIATE_VALUE) {
1388
1389 uint32_t surf_index = index.ud;
1390
1391 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1392 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1393 brw_set_src0(p, send, offset);
1394 brw_set_sampler_message(p, send,
1395 surf_index,
1396 0, /* LD message ignores sampler unit */
1397 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1398 rlen,
1399 mlen,
1400 false, /* no header */
1401 simd_mode,
1402 0);
1403
1404 } else {
1405
1406 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1407
1408 brw_push_insn_state(p);
1409 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1410 brw_set_default_access_mode(p, BRW_ALIGN_1);
1411
1412 /* a0.0 = surf_index & 0xff */
1413 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1414 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1415 brw_set_dest(p, insn_and, addr);
1416 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1417 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1418
1419 brw_pop_insn_state(p);
1420
1421 /* dst = send(offset, a0.0 | <descriptor>) */
1422 brw_inst *insn = brw_send_indirect_message(
1423 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1424 offset, addr);
1425 brw_set_sampler_message(p, insn,
1426 0 /* surface */,
1427 0 /* sampler */,
1428 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1429 rlen /* rlen */,
1430 mlen /* mlen */,
1431 false /* header */,
1432 simd_mode,
1433 0);
1434 }
1435 }
1436
1437 /**
1438 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1439 * into the flags register (f0.0).
1440 *
1441 * Used only on Gen6 and above.
1442 */
1443 void
1444 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1445 {
1446 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1447 struct brw_reg dispatch_mask;
1448
1449 if (devinfo->gen >= 6)
1450 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1451 else
1452 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1453
1454 brw_push_insn_state(p);
1455 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1456 brw_MOV(p, flags, dispatch_mask);
1457 brw_pop_insn_state(p);
1458 }
1459
1460 void
1461 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1462 struct brw_reg dst,
1463 struct brw_reg src,
1464 struct brw_reg msg_data,
1465 unsigned msg_type)
1466 {
1467 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1468
1469 brw_pixel_interpolator_query(p,
1470 retype(dst, BRW_REGISTER_TYPE_UW),
1471 src,
1472 inst->pi_noperspective,
1473 msg_type,
1474 msg_data,
1475 inst->mlen,
1476 inst->regs_written);
1477 }
1478
1479
1480 /**
1481 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1482 * sampler LD messages.
1483 *
1484 * We don't want to bake it into the send message's code generation because
1485 * that means we don't get a chance to schedule the instructions.
1486 */
1487 void
1488 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1489 struct brw_reg dst,
1490 struct brw_reg value)
1491 {
1492 assert(value.file == BRW_IMMEDIATE_VALUE);
1493
1494 brw_push_insn_state(p);
1495 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1496 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1497 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1498 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1499 brw_pop_insn_state(p);
1500 }
1501
1502 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1503 * the ADD instruction.
1504 */
1505 void
1506 fs_generator::generate_set_sample_id(fs_inst *inst,
1507 struct brw_reg dst,
1508 struct brw_reg src0,
1509 struct brw_reg src1)
1510 {
1511 assert(dst.type == BRW_REGISTER_TYPE_D ||
1512 dst.type == BRW_REGISTER_TYPE_UD);
1513 assert(src0.type == BRW_REGISTER_TYPE_D ||
1514 src0.type == BRW_REGISTER_TYPE_UD);
1515
1516 struct brw_reg reg = stride(src1, 1, 4, 0);
1517 if (devinfo->gen >= 8 || dispatch_width == 8) {
1518 brw_ADD(p, dst, src0, reg);
1519 } else if (dispatch_width == 16) {
1520 brw_push_insn_state(p);
1521 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1522 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1523 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1524 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1525 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1526 brw_pop_insn_state(p);
1527 }
1528 }
1529
1530 void
1531 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1532 struct brw_reg dst,
1533 struct brw_reg x,
1534 struct brw_reg y)
1535 {
1536 assert(devinfo->gen >= 7);
1537 assert(dst.type == BRW_REGISTER_TYPE_UD);
1538 assert(x.type == BRW_REGISTER_TYPE_F);
1539 assert(y.type == BRW_REGISTER_TYPE_F);
1540
1541 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1542 *
1543 * Because this instruction does not have a 16-bit floating-point type,
1544 * the destination data type must be Word (W).
1545 *
1546 * The destination must be DWord-aligned and specify a horizontal stride
1547 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1548 * each destination channel and the upper word is not modified.
1549 */
1550 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1551
1552 /* Give each 32-bit channel of dst the form below, where "." means
1553 * unchanged.
1554 * 0x....hhhh
1555 */
1556 brw_F32TO16(p, dst_w, y);
1557
1558 /* Now the form:
1559 * 0xhhhh0000
1560 */
1561 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1562
1563 /* And, finally the form of packHalf2x16's output:
1564 * 0xhhhhllll
1565 */
1566 brw_F32TO16(p, dst_w, x);
1567 }
1568
1569 void
1570 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1571 struct brw_reg dst,
1572 struct brw_reg src)
1573 {
1574 assert(devinfo->gen >= 7);
1575 assert(dst.type == BRW_REGISTER_TYPE_F);
1576 assert(src.type == BRW_REGISTER_TYPE_UD);
1577
1578 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1579 *
1580 * Because this instruction does not have a 16-bit floating-point type,
1581 * the source data type must be Word (W). The destination type must be
1582 * F (Float).
1583 */
1584 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1585
1586 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1587 * For the Y case, we wish to access only the upper word; therefore
1588 * a 16-bit subregister offset is needed.
1589 */
1590 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1591 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1592 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1593 src_w.subnr += 2;
1594
1595 brw_F16TO32(p, dst, src_w);
1596 }
1597
1598 void
1599 fs_generator::generate_shader_time_add(fs_inst *inst,
1600 struct brw_reg payload,
1601 struct brw_reg offset,
1602 struct brw_reg value)
1603 {
1604 assert(devinfo->gen >= 7);
1605 brw_push_insn_state(p);
1606 brw_set_default_mask_control(p, true);
1607
1608 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1609 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1610 offset.type);
1611 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1612 value.type);
1613
1614 assert(offset.file == BRW_IMMEDIATE_VALUE);
1615 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1616 value.width = BRW_WIDTH_1;
1617 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1618 value.vstride = BRW_VERTICAL_STRIDE_0;
1619 } else {
1620 assert(value.file == BRW_IMMEDIATE_VALUE);
1621 }
1622
1623 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1624 * case, and we don't really care about squeezing every bit of performance
1625 * out of this path, so we just emit the MOVs from here.
1626 */
1627 brw_MOV(p, payload_offset, offset);
1628 brw_MOV(p, payload_value, value);
1629 brw_shader_time_add(p, payload,
1630 prog_data->binding_table.shader_time_start);
1631 brw_pop_insn_state(p);
1632
1633 brw_mark_surface_used(prog_data,
1634 prog_data->binding_table.shader_time_start);
1635 }
1636
1637 void
1638 fs_generator::enable_debug(const char *shader_name)
1639 {
1640 debug_flag = true;
1641 this->shader_name = shader_name;
1642 }
1643
1644 int
1645 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1646 {
1647 /* align to 64 byte boundary. */
1648 while (p->next_insn_offset % 64)
1649 brw_NOP(p);
1650
1651 this->dispatch_width = dispatch_width;
1652 if (dispatch_width == 16)
1653 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1654
1655 int start_offset = p->next_insn_offset;
1656 int spill_count = 0, fill_count = 0;
1657 int loop_count = 0;
1658
1659 struct annotation_info annotation;
1660 memset(&annotation, 0, sizeof(annotation));
1661
1662 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1663 struct brw_reg src[3], dst;
1664 unsigned int last_insn_offset = p->next_insn_offset;
1665 bool multiple_instructions_emitted = false;
1666
1667 if (unlikely(debug_flag))
1668 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1669
1670 for (unsigned int i = 0; i < inst->sources; i++) {
1671 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1672
1673 /* The accumulator result appears to get used for the
1674 * conditional modifier generation. When negating a UD
1675 * value, there is a 33rd bit generated for the sign in the
1676 * accumulator value, so now you can't check, for example,
1677 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1678 */
1679 assert(!inst->conditional_mod ||
1680 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1681 !inst->src[i].negate);
1682 }
1683 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1684
1685 brw_set_default_predicate_control(p, inst->predicate);
1686 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1687 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1688 brw_set_default_saturate(p, inst->saturate);
1689 brw_set_default_mask_control(p, inst->force_writemask_all);
1690 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1691 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1692
1693 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1694 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1695
1696 switch (inst->exec_size) {
1697 case 1:
1698 case 2:
1699 case 4:
1700 assert(inst->force_writemask_all);
1701 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1702 break;
1703 case 8:
1704 if (inst->force_sechalf) {
1705 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1706 } else {
1707 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1708 }
1709 break;
1710 case 16:
1711 case 32:
1712 /* If the instruction writes to more than one register, it needs to
1713 * be a "compressed" instruction on Gen <= 5.
1714 */
1715 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1716 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1717 else
1718 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1719 break;
1720 default:
1721 unreachable("Invalid instruction width");
1722 }
1723
1724 switch (inst->opcode) {
1725 case BRW_OPCODE_MOV:
1726 brw_MOV(p, dst, src[0]);
1727 break;
1728 case BRW_OPCODE_ADD:
1729 brw_ADD(p, dst, src[0], src[1]);
1730 break;
1731 case BRW_OPCODE_MUL:
1732 brw_MUL(p, dst, src[0], src[1]);
1733 break;
1734 case BRW_OPCODE_AVG:
1735 brw_AVG(p, dst, src[0], src[1]);
1736 break;
1737 case BRW_OPCODE_MACH:
1738 brw_MACH(p, dst, src[0], src[1]);
1739 break;
1740
1741 case BRW_OPCODE_LINE:
1742 brw_LINE(p, dst, src[0], src[1]);
1743 break;
1744
1745 case BRW_OPCODE_MAD:
1746 assert(devinfo->gen >= 6);
1747 brw_set_default_access_mode(p, BRW_ALIGN_16);
1748 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1749 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1750 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1751 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1752 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1753 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1754 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1755
1756 if (inst->conditional_mod) {
1757 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1758 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1759 multiple_instructions_emitted = true;
1760 }
1761 } else {
1762 brw_MAD(p, dst, src[0], src[1], src[2]);
1763 }
1764 brw_set_default_access_mode(p, BRW_ALIGN_1);
1765 break;
1766
1767 case BRW_OPCODE_LRP:
1768 assert(devinfo->gen >= 6);
1769 brw_set_default_access_mode(p, BRW_ALIGN_16);
1770 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1771 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1772 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1773 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1774 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1775 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1776 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1777
1778 if (inst->conditional_mod) {
1779 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1780 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1781 multiple_instructions_emitted = true;
1782 }
1783 } else {
1784 brw_LRP(p, dst, src[0], src[1], src[2]);
1785 }
1786 brw_set_default_access_mode(p, BRW_ALIGN_1);
1787 break;
1788
1789 case BRW_OPCODE_FRC:
1790 brw_FRC(p, dst, src[0]);
1791 break;
1792 case BRW_OPCODE_RNDD:
1793 brw_RNDD(p, dst, src[0]);
1794 break;
1795 case BRW_OPCODE_RNDE:
1796 brw_RNDE(p, dst, src[0]);
1797 break;
1798 case BRW_OPCODE_RNDZ:
1799 brw_RNDZ(p, dst, src[0]);
1800 break;
1801
1802 case BRW_OPCODE_AND:
1803 brw_AND(p, dst, src[0], src[1]);
1804 break;
1805 case BRW_OPCODE_OR:
1806 brw_OR(p, dst, src[0], src[1]);
1807 break;
1808 case BRW_OPCODE_XOR:
1809 brw_XOR(p, dst, src[0], src[1]);
1810 break;
1811 case BRW_OPCODE_NOT:
1812 brw_NOT(p, dst, src[0]);
1813 break;
1814 case BRW_OPCODE_ASR:
1815 brw_ASR(p, dst, src[0], src[1]);
1816 break;
1817 case BRW_OPCODE_SHR:
1818 brw_SHR(p, dst, src[0], src[1]);
1819 break;
1820 case BRW_OPCODE_SHL:
1821 brw_SHL(p, dst, src[0], src[1]);
1822 break;
1823 case BRW_OPCODE_F32TO16:
1824 assert(devinfo->gen >= 7);
1825 brw_F32TO16(p, dst, src[0]);
1826 break;
1827 case BRW_OPCODE_F16TO32:
1828 assert(devinfo->gen >= 7);
1829 brw_F16TO32(p, dst, src[0]);
1830 break;
1831 case BRW_OPCODE_CMP:
1832 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1833 * that when the destination is a GRF that the dependency-clear bit on
1834 * the flag register is cleared early.
1835 *
1836 * Suggested workarounds are to disable coissuing CMP instructions
1837 * or to split CMP(16) instructions into two CMP(8) instructions.
1838 *
1839 * We choose to split into CMP(8) instructions since disabling
1840 * coissuing would affect CMP instructions not otherwise affected by
1841 * the errata.
1842 */
1843 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1844 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1845 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1846 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1847 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1848 firsthalf(src[0]), firsthalf(src[1]));
1849 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1850 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1851 sechalf(src[0]), sechalf(src[1]));
1852 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1853
1854 multiple_instructions_emitted = true;
1855 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1856 /* For unknown reasons, the aforementioned workaround is not
1857 * sufficient. Overriding the type when the destination is the
1858 * null register is necessary but not sufficient by itself.
1859 */
1860 assert(dst.nr == BRW_ARF_NULL);
1861 dst.type = BRW_REGISTER_TYPE_D;
1862 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1863 } else {
1864 unreachable("not reached");
1865 }
1866 } else {
1867 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1868 }
1869 break;
1870 case BRW_OPCODE_SEL:
1871 brw_SEL(p, dst, src[0], src[1]);
1872 break;
1873 case BRW_OPCODE_BFREV:
1874 assert(devinfo->gen >= 7);
1875 /* BFREV only supports UD type for src and dst. */
1876 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1877 retype(src[0], BRW_REGISTER_TYPE_UD));
1878 break;
1879 case BRW_OPCODE_FBH:
1880 assert(devinfo->gen >= 7);
1881 /* FBH only supports UD type for dst. */
1882 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1883 break;
1884 case BRW_OPCODE_FBL:
1885 assert(devinfo->gen >= 7);
1886 /* FBL only supports UD type for dst. */
1887 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1888 break;
1889 case BRW_OPCODE_CBIT:
1890 assert(devinfo->gen >= 7);
1891 /* CBIT only supports UD type for dst. */
1892 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1893 break;
1894 case BRW_OPCODE_ADDC:
1895 assert(devinfo->gen >= 7);
1896 brw_ADDC(p, dst, src[0], src[1]);
1897 break;
1898 case BRW_OPCODE_SUBB:
1899 assert(devinfo->gen >= 7);
1900 brw_SUBB(p, dst, src[0], src[1]);
1901 break;
1902 case BRW_OPCODE_MAC:
1903 brw_MAC(p, dst, src[0], src[1]);
1904 break;
1905
1906 case BRW_OPCODE_BFE:
1907 assert(devinfo->gen >= 7);
1908 brw_set_default_access_mode(p, BRW_ALIGN_16);
1909 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1910 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1911 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1912 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1913 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1914 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1915 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1916 } else {
1917 brw_BFE(p, dst, src[0], src[1], src[2]);
1918 }
1919 brw_set_default_access_mode(p, BRW_ALIGN_1);
1920 break;
1921
1922 case BRW_OPCODE_BFI1:
1923 assert(devinfo->gen >= 7);
1924 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1925 * should
1926 *
1927 * "Force BFI instructions to be executed always in SIMD8."
1928 */
1929 if (dispatch_width == 16 && devinfo->is_haswell) {
1930 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1931 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1932 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1933 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1934 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1935 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1936 } else {
1937 brw_BFI1(p, dst, src[0], src[1]);
1938 }
1939 break;
1940 case BRW_OPCODE_BFI2:
1941 assert(devinfo->gen >= 7);
1942 brw_set_default_access_mode(p, BRW_ALIGN_16);
1943 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1944 * should
1945 *
1946 * "Force BFI instructions to be executed always in SIMD8."
1947 *
1948 * Otherwise we would be able to emit compressed instructions like we
1949 * do for the other three-source instructions.
1950 */
1951 if (dispatch_width == 16 &&
1952 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1953 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1954 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1955 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1956 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1957 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1958 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1959 } else {
1960 brw_BFI2(p, dst, src[0], src[1], src[2]);
1961 }
1962 brw_set_default_access_mode(p, BRW_ALIGN_1);
1963 break;
1964
1965 case BRW_OPCODE_IF:
1966 if (inst->src[0].file != BAD_FILE) {
1967 /* The instruction has an embedded compare (only allowed on gen6) */
1968 assert(devinfo->gen == 6);
1969 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1970 } else {
1971 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1972 }
1973 break;
1974
1975 case BRW_OPCODE_ELSE:
1976 brw_ELSE(p);
1977 break;
1978 case BRW_OPCODE_ENDIF:
1979 brw_ENDIF(p);
1980 break;
1981
1982 case BRW_OPCODE_DO:
1983 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1984 break;
1985
1986 case BRW_OPCODE_BREAK:
1987 brw_BREAK(p);
1988 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1989 break;
1990 case BRW_OPCODE_CONTINUE:
1991 brw_CONT(p);
1992 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1993 break;
1994
1995 case BRW_OPCODE_WHILE:
1996 brw_WHILE(p);
1997 loop_count++;
1998 break;
1999
2000 case SHADER_OPCODE_RCP:
2001 case SHADER_OPCODE_RSQ:
2002 case SHADER_OPCODE_SQRT:
2003 case SHADER_OPCODE_EXP2:
2004 case SHADER_OPCODE_LOG2:
2005 case SHADER_OPCODE_SIN:
2006 case SHADER_OPCODE_COS:
2007 assert(devinfo->gen < 6 || inst->mlen == 0);
2008 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2009 if (devinfo->gen >= 7) {
2010 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2011 brw_null_reg());
2012 } else if (devinfo->gen == 6) {
2013 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2014 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2015 generate_math_g45(inst, dst, src[0]);
2016 } else {
2017 generate_math_gen4(inst, dst, src[0]);
2018 }
2019 break;
2020 case SHADER_OPCODE_INT_QUOTIENT:
2021 case SHADER_OPCODE_INT_REMAINDER:
2022 case SHADER_OPCODE_POW:
2023 assert(devinfo->gen < 6 || inst->mlen == 0);
2024 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2025 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2026 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2027 } else if (devinfo->gen >= 6) {
2028 generate_math_gen6(inst, dst, src[0], src[1]);
2029 } else {
2030 generate_math_gen4(inst, dst, src[0]);
2031 }
2032 break;
2033 case FS_OPCODE_CINTERP:
2034 brw_MOV(p, dst, src[0]);
2035 break;
2036 case FS_OPCODE_LINTERP:
2037 generate_linterp(inst, dst, src);
2038 break;
2039 case FS_OPCODE_PIXEL_X:
2040 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2041 src[0].subnr = 0 * type_sz(src[0].type);
2042 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2043 break;
2044 case FS_OPCODE_PIXEL_Y:
2045 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2046 src[0].subnr = 4 * type_sz(src[0].type);
2047 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2048 break;
2049 case FS_OPCODE_GET_BUFFER_SIZE:
2050 generate_get_buffer_size(inst, dst, src[0], src[1]);
2051 break;
2052 case SHADER_OPCODE_TEX:
2053 case FS_OPCODE_TXB:
2054 case SHADER_OPCODE_TXD:
2055 case SHADER_OPCODE_TXF:
2056 case SHADER_OPCODE_TXF_CMS:
2057 case SHADER_OPCODE_TXF_CMS_W:
2058 case SHADER_OPCODE_TXF_UMS:
2059 case SHADER_OPCODE_TXF_MCS:
2060 case SHADER_OPCODE_TXL:
2061 case SHADER_OPCODE_TXS:
2062 case SHADER_OPCODE_LOD:
2063 case SHADER_OPCODE_TG4:
2064 case SHADER_OPCODE_TG4_OFFSET:
2065 case SHADER_OPCODE_SAMPLEINFO:
2066 generate_tex(inst, dst, src[0], src[1]);
2067 break;
2068 case FS_OPCODE_DDX_COARSE:
2069 case FS_OPCODE_DDX_FINE:
2070 generate_ddx(inst->opcode, dst, src[0]);
2071 break;
2072 case FS_OPCODE_DDY_COARSE:
2073 case FS_OPCODE_DDY_FINE:
2074 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2075 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2076 break;
2077
2078 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2079 generate_scratch_write(inst, src[0]);
2080 spill_count++;
2081 break;
2082
2083 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2084 generate_scratch_read(inst, dst);
2085 fill_count++;
2086 break;
2087
2088 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2089 generate_scratch_read_gen7(inst, dst);
2090 fill_count++;
2091 break;
2092
2093 case SHADER_OPCODE_MOV_INDIRECT:
2094 generate_mov_indirect(inst, dst, src[0], src[1]);
2095 break;
2096
2097 case SHADER_OPCODE_URB_READ_SIMD8:
2098 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2099 generate_urb_read(inst, dst, src[0]);
2100 break;
2101
2102 case SHADER_OPCODE_URB_WRITE_SIMD8:
2103 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2104 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2105 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2106 generate_urb_write(inst, src[0]);
2107 break;
2108
2109 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2110 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2111 break;
2112
2113 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2114 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2115 break;
2116
2117 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2118 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2119 break;
2120
2121 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2122 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2123 break;
2124
2125 case FS_OPCODE_REP_FB_WRITE:
2126 case FS_OPCODE_FB_WRITE:
2127 generate_fb_write(inst, src[0]);
2128 break;
2129
2130 case FS_OPCODE_BLORP_FB_WRITE:
2131 generate_blorp_fb_write(inst);
2132 break;
2133
2134 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2135 generate_mov_dispatch_to_flags(inst);
2136 break;
2137
2138 case FS_OPCODE_DISCARD_JUMP:
2139 generate_discard_jump(inst);
2140 break;
2141
2142 case SHADER_OPCODE_SHADER_TIME_ADD:
2143 generate_shader_time_add(inst, src[0], src[1], src[2]);
2144 break;
2145
2146 case SHADER_OPCODE_UNTYPED_ATOMIC:
2147 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2148 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2149 inst->mlen, !inst->dst.is_null());
2150 break;
2151
2152 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2153 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2154 brw_untyped_surface_read(p, dst, src[0], src[1],
2155 inst->mlen, src[2].ud);
2156 break;
2157
2158 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2159 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2160 brw_untyped_surface_write(p, src[0], src[1],
2161 inst->mlen, src[2].ud);
2162 break;
2163
2164 case SHADER_OPCODE_TYPED_ATOMIC:
2165 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2166 brw_typed_atomic(p, dst, src[0], src[1],
2167 src[2].ud, inst->mlen, !inst->dst.is_null());
2168 break;
2169
2170 case SHADER_OPCODE_TYPED_SURFACE_READ:
2171 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2172 brw_typed_surface_read(p, dst, src[0], src[1],
2173 inst->mlen, src[2].ud);
2174 break;
2175
2176 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2177 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2178 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2179 break;
2180
2181 case SHADER_OPCODE_MEMORY_FENCE:
2182 brw_memory_fence(p, dst);
2183 break;
2184
2185 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2186 generate_set_simd4x2_offset(inst, dst, src[0]);
2187 break;
2188
2189 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2190 brw_find_live_channel(p, dst);
2191 break;
2192
2193 case SHADER_OPCODE_BROADCAST:
2194 brw_broadcast(p, dst, src[0], src[1]);
2195 break;
2196
2197 case FS_OPCODE_SET_SAMPLE_ID:
2198 generate_set_sample_id(inst, dst, src[0], src[1]);
2199 break;
2200
2201 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2202 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2203 break;
2204
2205 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2206 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2207 generate_unpack_half_2x16_split(inst, dst, src[0]);
2208 break;
2209
2210 case FS_OPCODE_PLACEHOLDER_HALT:
2211 /* This is the place where the final HALT needs to be inserted if
2212 * we've emitted any discards. If not, this will emit no code.
2213 */
2214 if (!patch_discard_jumps_to_fb_writes()) {
2215 if (unlikely(debug_flag)) {
2216 annotation.ann_count--;
2217 }
2218 }
2219 break;
2220
2221 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2222 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2223 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2224 break;
2225
2226 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2227 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2228 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2229 break;
2230
2231 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2232 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2233 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2234 break;
2235
2236 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2237 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2238 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2239 break;
2240
2241 case CS_OPCODE_CS_TERMINATE:
2242 generate_cs_terminate(inst, src[0]);
2243 break;
2244
2245 case SHADER_OPCODE_BARRIER:
2246 generate_barrier(inst, src[0]);
2247 break;
2248
2249 case FS_OPCODE_PACK_STENCIL_REF:
2250 generate_stencil_ref_packing(inst, dst, src[0]);
2251 break;
2252
2253 default:
2254 unreachable("Unsupported opcode");
2255
2256 case SHADER_OPCODE_LOAD_PAYLOAD:
2257 unreachable("Should be lowered by lower_load_payload()");
2258 }
2259
2260 if (multiple_instructions_emitted)
2261 continue;
2262
2263 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2264 assert(p->next_insn_offset == last_insn_offset + 16 ||
2265 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2266 "emitting more than 1 instruction");
2267
2268 brw_inst *last = &p->store[last_insn_offset / 16];
2269
2270 if (inst->conditional_mod)
2271 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2272 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2273 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2274 }
2275 }
2276
2277 brw_set_uip_jip(p);
2278 annotation_finalize(&annotation, p->next_insn_offset);
2279
2280 #ifndef NDEBUG
2281 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2282 #else
2283 if (unlikely(debug_flag))
2284 brw_validate_instructions(p, start_offset, &annotation);
2285 #endif
2286
2287 int before_size = p->next_insn_offset - start_offset;
2288 brw_compact_instructions(p, start_offset, annotation.ann_count,
2289 annotation.ann);
2290 int after_size = p->next_insn_offset - start_offset;
2291
2292 if (unlikely(debug_flag)) {
2293 fprintf(stderr, "Native code for %s\n"
2294 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2295 " bytes (%.0f%%)\n",
2296 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2297 spill_count, fill_count, promoted_constants, before_size, after_size,
2298 100.0f * (before_size - after_size) / before_size);
2299
2300 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2301 p->devinfo);
2302 ralloc_free(annotation.mem_ctx);
2303 }
2304 assert(validated);
2305
2306 compiler->shader_debug_log(log_data,
2307 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2308 "%d:%d spills:fills, Promoted %u constants, "
2309 "compacted %d to %d bytes.\n",
2310 stage_abbrev, dispatch_width, before_size / 16,
2311 loop_count, cfg->cycle_count, spill_count,
2312 fill_count, promoted_constants, before_size,
2313 after_size);
2314
2315 return start_offset;
2316 }
2317
2318 const unsigned *
2319 fs_generator::get_assembly(unsigned int *assembly_size)
2320 {
2321 return brw_get_program(p, assembly_size);
2322 }