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nir: Get rid of *_indirect variants of input/output load/store intrinsics
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else if (inst->exec_size < 8) {
69 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
70 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
71 inst->exec_size, reg->stride);
72 } else {
73 /* From the Haswell PRM:
74 *
75 * VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
77 * boundaries.
78 *
79 * So, for registers with width > 8, we have to use a width of 8
80 * and trust the compression state to sort out the exec size.
81 */
82 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
83 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
84 }
85
86 brw_reg = retype(brw_reg, reg->type);
87 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
88 brw_reg.abs = reg->abs;
89 brw_reg.negate = reg->negate;
90 break;
91 case ARF:
92 case FIXED_GRF:
93 case IMM:
94 brw_reg = reg->as_brw_reg();
95 break;
96 case BAD_FILE:
97 /* Probably unused. */
98 brw_reg = brw_null_reg();
99 break;
100 case ATTR:
101 case UNIFORM:
102 unreachable("not reached");
103 }
104
105 return brw_reg;
106 }
107
108 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
109 void *mem_ctx,
110 const void *key,
111 struct brw_stage_prog_data *prog_data,
112 unsigned promoted_constants,
113 bool runtime_check_aads_emit,
114 const char *stage_abbrev)
115
116 : compiler(compiler), log_data(log_data),
117 devinfo(compiler->devinfo), key(key),
118 prog_data(prog_data),
119 promoted_constants(promoted_constants),
120 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
121 stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
122 {
123 p = rzalloc(mem_ctx, struct brw_codegen);
124 brw_init_codegen(devinfo, p, mem_ctx);
125 }
126
127 fs_generator::~fs_generator()
128 {
129 }
130
131 class ip_record : public exec_node {
132 public:
133 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
134
135 ip_record(int ip)
136 {
137 this->ip = ip;
138 }
139
140 int ip;
141 };
142
143 bool
144 fs_generator::patch_discard_jumps_to_fb_writes()
145 {
146 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
147 return false;
148
149 int scale = brw_jump_scale(p->devinfo);
150
151 /* There is a somewhat strange undocumented requirement of using
152 * HALT, according to the simulator. If some channel has HALTed to
153 * a particular UIP, then by the end of the program, every channel
154 * must have HALTed to that UIP. Furthermore, the tracking is a
155 * stack, so you can't do the final halt of a UIP after starting
156 * halting to a new UIP.
157 *
158 * Symptoms of not emitting this instruction on actual hardware
159 * included GPU hangs and sparkly rendering on the piglit discard
160 * tests.
161 */
162 brw_inst *last_halt = gen6_HALT(p);
163 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
164 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
165
166 int ip = p->nr_insn;
167
168 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
169 brw_inst *patch = &p->store[patch_ip->ip];
170
171 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
172 /* HALT takes a half-instruction distance from the pre-incremented IP. */
173 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
174 }
175
176 this->discard_halt_patches.make_empty();
177 return true;
178 }
179
180 void
181 fs_generator::fire_fb_write(fs_inst *inst,
182 struct brw_reg payload,
183 struct brw_reg implied_header,
184 GLuint nr)
185 {
186 uint32_t msg_control;
187
188 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
189
190 if (devinfo->gen < 6) {
191 brw_push_insn_state(p);
192 brw_set_default_exec_size(p, BRW_EXECUTE_8);
193 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
194 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
195 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
196 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
197 brw_pop_insn_state(p);
198 }
199
200 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
201 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
202 else if (prog_data->dual_src_blend) {
203 if (!inst->force_sechalf)
204 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
205 else
206 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
207 } else if (inst->exec_size == 16)
208 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
209 else
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
211
212 uint32_t surf_index =
213 prog_data->binding_table.render_target_start + inst->target;
214
215 bool last_render_target = inst->eot ||
216 (prog_data->dual_src_blend && dispatch_width == 16);
217
218
219 brw_fb_WRITE(p,
220 dispatch_width,
221 payload,
222 implied_header,
223 msg_control,
224 surf_index,
225 nr,
226 0,
227 inst->eot,
228 last_render_target,
229 inst->header_size != 0);
230
231 brw_mark_surface_used(&prog_data->base, surf_index);
232 }
233
234 void
235 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
236 {
237 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
238 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
239 struct brw_reg implied_header;
240
241 if (devinfo->gen < 8 && !devinfo->is_haswell) {
242 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
243 }
244
245 if (inst->base_mrf >= 0)
246 payload = brw_message_reg(inst->base_mrf);
247
248 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
249 * move, here's g1.
250 */
251 if (inst->header_size != 0) {
252 brw_push_insn_state(p);
253 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
254 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
255 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
256 brw_set_default_flag_reg(p, 0, 0);
257
258 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
259 * present.
260 */
261 if (prog_data->uses_kill) {
262 struct brw_reg pixel_mask;
263
264 if (devinfo->gen >= 6)
265 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
266 else
267 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
268
269 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
270 }
271
272 if (devinfo->gen >= 6) {
273 brw_push_insn_state(p);
274 brw_set_default_exec_size(p, BRW_EXECUTE_16);
275 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
276 brw_MOV(p,
277 retype(payload, BRW_REGISTER_TYPE_UD),
278 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
279 brw_pop_insn_state(p);
280
281 if (inst->target > 0 && key->replicate_alpha) {
282 /* Set "Source0 Alpha Present to RenderTarget" bit in message
283 * header.
284 */
285 brw_OR(p,
286 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
287 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
288 brw_imm_ud(0x1 << 11));
289 }
290
291 if (inst->target > 0) {
292 /* Set the render target index for choosing BLEND_STATE. */
293 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
294 BRW_REGISTER_TYPE_UD),
295 brw_imm_ud(inst->target));
296 }
297
298 /* Set computes stencil to render target */
299 if (prog_data->computed_stencil) {
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 14));
304 }
305
306 implied_header = brw_null_reg();
307 } else {
308 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
309 }
310
311 brw_pop_insn_state(p);
312 } else {
313 implied_header = brw_null_reg();
314 }
315
316 if (!runtime_check_aads_emit) {
317 fire_fb_write(inst, payload, implied_header, inst->mlen);
318 } else {
319 /* This can only happen in gen < 6 */
320 assert(devinfo->gen < 6);
321
322 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
323
324 /* Check runtime bit to detect if we have to send AA data or not */
325 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
326 brw_AND(p,
327 v1_null_ud,
328 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
329 brw_imm_ud(1<<26));
330 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
331
332 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
333 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
334 {
335 /* Don't send AA data */
336 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
337 }
338 brw_land_fwd_jump(p, jmp);
339 fire_fb_write(inst, payload, implied_header, inst->mlen);
340 }
341 }
342
343 void
344 fs_generator::generate_mov_indirect(fs_inst *inst,
345 struct brw_reg dst,
346 struct brw_reg reg,
347 struct brw_reg indirect_byte_offset)
348 {
349 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
350 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
351
352 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
353
354 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
355 struct brw_reg addr = vec8(brw_address_reg(0));
356
357 /* The destination stride of an instruction (in bytes) must be greater
358 * than or equal to the size of the rest of the instruction. Since the
359 * address register is of type UW, we can't use a D-type instruction.
360 * In order to get around this, re re-type to UW and use a stride.
361 */
362 indirect_byte_offset =
363 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
364
365 /* Prior to Broadwell, there are only 8 address registers. */
366 assert(inst->exec_size == 8 || devinfo->gen >= 8);
367
368 brw_MOV(p, addr, indirect_byte_offset);
369 brw_inst_set_mask_control(devinfo, brw_last_inst, BRW_MASK_DISABLE);
370 brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
371 }
372
373 void
374 fs_generator::generate_urb_read(fs_inst *inst,
375 struct brw_reg dst,
376 struct brw_reg header)
377 {
378 assert(header.file == BRW_GENERAL_REGISTER_FILE);
379 assert(header.type == BRW_REGISTER_TYPE_UD);
380
381 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
382 brw_set_dest(p, send, dst);
383 brw_set_src0(p, send, header);
384 brw_set_src1(p, send, brw_imm_ud(0u));
385
386 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
387 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
388
389 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
390 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
391
392 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
393 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
394 brw_inst_set_header_present(p->devinfo, send, true);
395 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
396 }
397
398 void
399 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
400 {
401 brw_inst *insn;
402
403 insn = brw_next_insn(p, BRW_OPCODE_SEND);
404
405 brw_set_dest(p, insn, brw_null_reg());
406 brw_set_src0(p, insn, payload);
407 brw_set_src1(p, insn, brw_imm_d(0));
408
409 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
410 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
411
412 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
413 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
414 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
415
416 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
417 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
418 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
419
420 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
421 brw_inst_set_rlen(p->devinfo, insn, 0);
422 brw_inst_set_eot(p->devinfo, insn, inst->eot);
423 brw_inst_set_header_present(p->devinfo, insn, true);
424 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
425 }
426
427 void
428 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
429 {
430 struct brw_inst *insn;
431
432 insn = brw_next_insn(p, BRW_OPCODE_SEND);
433
434 brw_set_dest(p, insn, brw_null_reg());
435 brw_set_src0(p, insn, payload);
436 brw_set_src1(p, insn, brw_imm_d(0));
437
438 /* Terminate a compute shader by sending a message to the thread spawner.
439 */
440 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
441 brw_inst_set_mlen(devinfo, insn, 1);
442 brw_inst_set_rlen(devinfo, insn, 0);
443 brw_inst_set_eot(devinfo, insn, inst->eot);
444 brw_inst_set_header_present(devinfo, insn, false);
445
446 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
447 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
448
449 /* Note that even though the thread has a URB resource associated with it,
450 * we set the "do not dereference URB" bit, because the URB resource is
451 * managed by the fixed-function unit, so it will free it automatically.
452 */
453 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
454
455 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
456 }
457
458 void
459 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
460 struct brw_reg dst,
461 struct brw_reg src)
462 {
463 assert(dispatch_width == 8);
464 assert(devinfo->gen >= 9);
465
466 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
467 * Presumably, in order to save memory bandwidth, the stencil reference
468 * values written from the FS need to be packed into 2 dwords (this makes
469 * sense because the stencil values are limited to 1 byte each and a SIMD8
470 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
471 *
472 * The spec is confusing here because in the payload definition of MDP_RTW_S8
473 * (Message Data Payload for Render Target Writes with Stencil 8b) the
474 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
475 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
476 * packed values specified above and diagrammed below:
477 *
478 * 31 0
479 * --------------------------------
480 * DW | |
481 * 2-7 | IGNORED |
482 * | |
483 * --------------------------------
484 * DW1 | STC | STC | STC | STC |
485 * | slot7 | slot6 | slot5 | slot4|
486 * --------------------------------
487 * DW0 | STC | STC | STC | STC |
488 * | slot3 | slot2 | slot1 | slot0|
489 * --------------------------------
490 */
491
492 src.vstride = BRW_VERTICAL_STRIDE_4;
493 src.width = BRW_WIDTH_1;
494 src.hstride = BRW_HORIZONTAL_STRIDE_0;
495 assert(src.type == BRW_REGISTER_TYPE_UB);
496 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
497 }
498
499 void
500 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
501 {
502 brw_barrier(p, src);
503 brw_WAIT(p);
504 }
505
506 void
507 fs_generator::generate_blorp_fb_write(fs_inst *inst)
508 {
509 brw_fb_WRITE(p,
510 16 /* dispatch_width */,
511 brw_message_reg(inst->base_mrf),
512 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
513 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
514 inst->target,
515 inst->mlen,
516 0,
517 true,
518 true,
519 inst->header_size != 0);
520 }
521
522 void
523 fs_generator::generate_linterp(fs_inst *inst,
524 struct brw_reg dst, struct brw_reg *src)
525 {
526 /* PLN reads:
527 * / in SIMD16 \
528 * -----------------------------------
529 * | src1+0 | src1+1 | src1+2 | src1+3 |
530 * |-----------------------------------|
531 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
532 * -----------------------------------
533 *
534 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
535 *
536 * -----------------------------------
537 * | src1+0 | src1+1 | src1+2 | src1+3 |
538 * |-----------------------------------|
539 * |(x0, x1)|(y0, y1)| | | in SIMD8
540 * |-----------------------------------|
541 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
542 * -----------------------------------
543 *
544 * See also: emit_interpolation_setup_gen4().
545 */
546 struct brw_reg delta_x = src[0];
547 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
548 struct brw_reg interp = src[1];
549
550 if (devinfo->has_pln &&
551 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
552 brw_PLN(p, dst, interp, delta_x);
553 } else {
554 brw_LINE(p, brw_null_reg(), interp, delta_x);
555 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
556 }
557 }
558
559 void
560 fs_generator::generate_math_gen6(fs_inst *inst,
561 struct brw_reg dst,
562 struct brw_reg src0,
563 struct brw_reg src1)
564 {
565 int op = brw_math_function(inst->opcode);
566 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
567
568 if (dispatch_width == 8) {
569 gen6_math(p, dst, op, src0, src1);
570 } else if (dispatch_width == 16) {
571 brw_push_insn_state(p);
572 brw_set_default_exec_size(p, BRW_EXECUTE_8);
573 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
574 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
575 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
576 gen6_math(p, sechalf(dst), op, sechalf(src0),
577 binop ? sechalf(src1) : brw_null_reg());
578 brw_pop_insn_state(p);
579 }
580 }
581
582 void
583 fs_generator::generate_math_gen4(fs_inst *inst,
584 struct brw_reg dst,
585 struct brw_reg src)
586 {
587 int op = brw_math_function(inst->opcode);
588
589 assert(inst->mlen >= 1);
590
591 if (dispatch_width == 8) {
592 gen4_math(p, dst,
593 op,
594 inst->base_mrf, src,
595 BRW_MATH_PRECISION_FULL);
596 } else if (dispatch_width == 16) {
597 brw_set_default_exec_size(p, BRW_EXECUTE_8);
598 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
599 gen4_math(p, firsthalf(dst),
600 op,
601 inst->base_mrf, firsthalf(src),
602 BRW_MATH_PRECISION_FULL);
603 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
604 gen4_math(p, sechalf(dst),
605 op,
606 inst->base_mrf + 1, sechalf(src),
607 BRW_MATH_PRECISION_FULL);
608
609 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
610 }
611 }
612
613 void
614 fs_generator::generate_math_g45(fs_inst *inst,
615 struct brw_reg dst,
616 struct brw_reg src)
617 {
618 if (inst->opcode == SHADER_OPCODE_POW ||
619 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
620 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
621 generate_math_gen4(inst, dst, src);
622 return;
623 }
624
625 int op = brw_math_function(inst->opcode);
626
627 assert(inst->mlen >= 1);
628
629 gen4_math(p, dst,
630 op,
631 inst->base_mrf, src,
632 BRW_MATH_PRECISION_FULL);
633 }
634
635 void
636 fs_generator::generate_get_buffer_size(fs_inst *inst,
637 struct brw_reg dst,
638 struct brw_reg src,
639 struct brw_reg surf_index)
640 {
641 assert(devinfo->gen >= 7);
642 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
643
644 uint32_t simd_mode;
645 int rlen = 4;
646
647 switch (inst->exec_size) {
648 case 8:
649 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
650 break;
651 case 16:
652 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
653 break;
654 default:
655 unreachable("Invalid width for texture instruction");
656 }
657
658 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
659 rlen = 8;
660 dst = vec16(dst);
661 }
662
663 brw_SAMPLE(p,
664 retype(dst, BRW_REGISTER_TYPE_UW),
665 inst->base_mrf,
666 src,
667 surf_index.ud,
668 0,
669 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
670 rlen, /* response length */
671 inst->mlen,
672 inst->header_size > 0,
673 simd_mode,
674 BRW_SAMPLER_RETURN_FORMAT_SINT32);
675
676 brw_mark_surface_used(prog_data, surf_index.ud);
677 }
678
679 void
680 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
681 struct brw_reg sampler_index)
682 {
683 int msg_type = -1;
684 int rlen = 4;
685 uint32_t simd_mode;
686 uint32_t return_format;
687 bool is_combined_send = inst->eot;
688
689 switch (dst.type) {
690 case BRW_REGISTER_TYPE_D:
691 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
692 break;
693 case BRW_REGISTER_TYPE_UD:
694 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
695 break;
696 default:
697 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
698 break;
699 }
700
701 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
702 * is set as part of the message descriptor. On gen4, the PRM seems to
703 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
704 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
705 * gone from the message descriptor entirely and you just get UINT32 all
706 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
707 * just stomp it to UINT32 all the time.
708 */
709 if (inst->opcode == SHADER_OPCODE_TXS)
710 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
711
712 switch (inst->exec_size) {
713 case 8:
714 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
715 break;
716 case 16:
717 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
718 break;
719 default:
720 unreachable("Invalid width for texture instruction");
721 }
722
723 if (devinfo->gen >= 5) {
724 switch (inst->opcode) {
725 case SHADER_OPCODE_TEX:
726 if (inst->shadow_compare) {
727 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
728 } else {
729 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
730 }
731 break;
732 case FS_OPCODE_TXB:
733 if (inst->shadow_compare) {
734 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
735 } else {
736 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
737 }
738 break;
739 case SHADER_OPCODE_TXL:
740 if (inst->shadow_compare) {
741 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
742 } else {
743 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
744 }
745 break;
746 case SHADER_OPCODE_TXS:
747 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
748 break;
749 case SHADER_OPCODE_TXD:
750 if (inst->shadow_compare) {
751 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
752 assert(devinfo->gen >= 8 || devinfo->is_haswell);
753 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
754 } else {
755 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
756 }
757 break;
758 case SHADER_OPCODE_TXF:
759 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
760 break;
761 case SHADER_OPCODE_TXF_CMS_W:
762 assert(devinfo->gen >= 9);
763 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
764 break;
765 case SHADER_OPCODE_TXF_CMS:
766 if (devinfo->gen >= 7)
767 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
768 else
769 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
770 break;
771 case SHADER_OPCODE_TXF_UMS:
772 assert(devinfo->gen >= 7);
773 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
774 break;
775 case SHADER_OPCODE_TXF_MCS:
776 assert(devinfo->gen >= 7);
777 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
778 break;
779 case SHADER_OPCODE_LOD:
780 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
781 break;
782 case SHADER_OPCODE_TG4:
783 if (inst->shadow_compare) {
784 assert(devinfo->gen >= 7);
785 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
786 } else {
787 assert(devinfo->gen >= 6);
788 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
789 }
790 break;
791 case SHADER_OPCODE_TG4_OFFSET:
792 assert(devinfo->gen >= 7);
793 if (inst->shadow_compare) {
794 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
795 } else {
796 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
797 }
798 break;
799 case SHADER_OPCODE_SAMPLEINFO:
800 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
801 break;
802 default:
803 unreachable("not reached");
804 }
805 } else {
806 switch (inst->opcode) {
807 case SHADER_OPCODE_TEX:
808 /* Note that G45 and older determines shadow compare and dispatch width
809 * from message length for most messages.
810 */
811 if (inst->exec_size == 8) {
812 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
813 if (inst->shadow_compare) {
814 assert(inst->mlen == 6);
815 } else {
816 assert(inst->mlen <= 4);
817 }
818 } else {
819 if (inst->shadow_compare) {
820 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
821 assert(inst->mlen == 9);
822 } else {
823 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
824 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
825 }
826 }
827 break;
828 case FS_OPCODE_TXB:
829 if (inst->shadow_compare) {
830 assert(inst->exec_size == 8);
831 assert(inst->mlen == 6);
832 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
833 } else {
834 assert(inst->mlen == 9);
835 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
836 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
837 }
838 break;
839 case SHADER_OPCODE_TXL:
840 if (inst->shadow_compare) {
841 assert(inst->exec_size == 8);
842 assert(inst->mlen == 6);
843 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
844 } else {
845 assert(inst->mlen == 9);
846 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
847 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
848 }
849 break;
850 case SHADER_OPCODE_TXD:
851 /* There is no sample_d_c message; comparisons are done manually */
852 assert(inst->exec_size == 8);
853 assert(inst->mlen == 7 || inst->mlen == 10);
854 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
855 break;
856 case SHADER_OPCODE_TXF:
857 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
858 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
859 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
860 break;
861 case SHADER_OPCODE_TXS:
862 assert(inst->mlen == 3);
863 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
864 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
865 break;
866 default:
867 unreachable("not reached");
868 }
869 }
870 assert(msg_type != -1);
871
872 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
873 rlen = 8;
874 dst = vec16(dst);
875 }
876
877 if (is_combined_send) {
878 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
879 rlen = 0;
880 }
881
882 assert(devinfo->gen < 7 || inst->header_size == 0 ||
883 src.file == BRW_GENERAL_REGISTER_FILE);
884
885 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
886
887 /* Load the message header if present. If there's a texture offset,
888 * we need to set it up explicitly and load the offset bitfield.
889 * Otherwise, we can use an implied move from g0 to the first message reg.
890 */
891 if (inst->header_size != 0) {
892 if (devinfo->gen < 6 && !inst->offset) {
893 /* Set up an implied move from g0 to the MRF. */
894 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
895 } else {
896 struct brw_reg header_reg;
897
898 if (devinfo->gen >= 7) {
899 header_reg = src;
900 } else {
901 assert(inst->base_mrf != -1);
902 header_reg = brw_message_reg(inst->base_mrf);
903 }
904
905 brw_push_insn_state(p);
906 brw_set_default_exec_size(p, BRW_EXECUTE_8);
907 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
908 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
909 /* Explicitly set up the message header by copying g0 to the MRF. */
910 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
911
912 if (inst->offset) {
913 /* Set the offset bits in DWord 2. */
914 brw_MOV(p, get_element_ud(header_reg, 2),
915 brw_imm_ud(inst->offset));
916 }
917
918 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
919 brw_pop_insn_state(p);
920 }
921 }
922
923 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
924 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
925 ? prog_data->binding_table.gather_texture_start
926 : prog_data->binding_table.texture_start;
927
928 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
929 uint32_t sampler = sampler_index.ud;
930
931 brw_SAMPLE(p,
932 retype(dst, BRW_REGISTER_TYPE_UW),
933 inst->base_mrf,
934 src,
935 sampler + base_binding_table_index,
936 sampler % 16,
937 msg_type,
938 rlen,
939 inst->mlen,
940 inst->header_size != 0,
941 simd_mode,
942 return_format);
943
944 brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
945 } else {
946 /* Non-const sampler index */
947
948 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
949 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
950
951 brw_push_insn_state(p);
952 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
953 brw_set_default_access_mode(p, BRW_ALIGN_1);
954
955 /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
956 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
957 if (base_binding_table_index)
958 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
959 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
960
961 brw_pop_insn_state(p);
962
963 /* dst = send(offset, a0.0 | <descriptor>) */
964 brw_inst *insn = brw_send_indirect_message(
965 p, BRW_SFID_SAMPLER, dst, src, addr);
966 brw_set_sampler_message(p, insn,
967 0 /* surface */,
968 0 /* sampler */,
969 msg_type,
970 rlen,
971 inst->mlen /* mlen */,
972 inst->header_size != 0 /* header */,
973 simd_mode,
974 return_format);
975
976 /* visitor knows more than we do about the surface limit required,
977 * so has already done marking.
978 */
979 }
980
981 if (is_combined_send) {
982 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
983 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
984 }
985 }
986
987
988 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
989 * looking like:
990 *
991 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
992 *
993 * Ideally, we want to produce:
994 *
995 * DDX DDY
996 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
997 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
998 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
999 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1000 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1001 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1002 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1003 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1004 *
1005 * and add another set of two more subspans if in 16-pixel dispatch mode.
1006 *
1007 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1008 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1009 * pair. But the ideal approximation may impose a huge performance cost on
1010 * sample_d. On at least Haswell, sample_d instruction does some
1011 * optimizations if the same LOD is used for all pixels in the subspan.
1012 *
1013 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1014 * appropriate swizzling.
1015 */
1016 void
1017 fs_generator::generate_ddx(enum opcode opcode,
1018 struct brw_reg dst, struct brw_reg src)
1019 {
1020 unsigned vstride, width;
1021
1022 if (opcode == FS_OPCODE_DDX_FINE) {
1023 /* produce accurate derivatives */
1024 vstride = BRW_VERTICAL_STRIDE_2;
1025 width = BRW_WIDTH_2;
1026 } else {
1027 /* replicate the derivative at the top-left pixel to other pixels */
1028 vstride = BRW_VERTICAL_STRIDE_4;
1029 width = BRW_WIDTH_4;
1030 }
1031
1032 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1033 src.negate, src.abs,
1034 BRW_REGISTER_TYPE_F,
1035 vstride,
1036 width,
1037 BRW_HORIZONTAL_STRIDE_0,
1038 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1039 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1040 src.negate, src.abs,
1041 BRW_REGISTER_TYPE_F,
1042 vstride,
1043 width,
1044 BRW_HORIZONTAL_STRIDE_0,
1045 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1046 brw_ADD(p, dst, src0, negate(src1));
1047 }
1048
1049 /* The negate_value boolean is used to negate the derivative computation for
1050 * FBOs, since they place the origin at the upper left instead of the lower
1051 * left.
1052 */
1053 void
1054 fs_generator::generate_ddy(enum opcode opcode,
1055 struct brw_reg dst, struct brw_reg src,
1056 bool negate_value)
1057 {
1058 if (opcode == FS_OPCODE_DDY_FINE) {
1059 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1060 * Region Restrictions):
1061 *
1062 * In Align16 access mode, SIMD16 is not allowed for DW operations
1063 * and SIMD8 is not allowed for DF operations.
1064 *
1065 * In this context, "DW operations" means "operations acting on 32-bit
1066 * values", so it includes operations on floats.
1067 *
1068 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1069 * (Instruction Compression -> Rules and Restrictions):
1070 *
1071 * A compressed instruction must be in Align1 access mode. Align16
1072 * mode instructions cannot be compressed.
1073 *
1074 * Similar text exists in the g45 PRM.
1075 *
1076 * On these platforms, if we're building a SIMD16 shader, we need to
1077 * manually unroll to a pair of SIMD8 instructions.
1078 */
1079 bool unroll_to_simd8 =
1080 (dispatch_width == 16 &&
1081 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1082
1083 /* produce accurate derivatives */
1084 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1085 src.negate, src.abs,
1086 BRW_REGISTER_TYPE_F,
1087 BRW_VERTICAL_STRIDE_4,
1088 BRW_WIDTH_4,
1089 BRW_HORIZONTAL_STRIDE_1,
1090 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1091 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1092 src.negate, src.abs,
1093 BRW_REGISTER_TYPE_F,
1094 BRW_VERTICAL_STRIDE_4,
1095 BRW_WIDTH_4,
1096 BRW_HORIZONTAL_STRIDE_1,
1097 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1098 brw_push_insn_state(p);
1099 brw_set_default_access_mode(p, BRW_ALIGN_16);
1100 if (unroll_to_simd8) {
1101 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1102 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1103 if (negate_value) {
1104 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1105 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1106 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1107 } else {
1108 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1109 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1110 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1111 }
1112 } else {
1113 if (negate_value)
1114 brw_ADD(p, dst, src1, negate(src0));
1115 else
1116 brw_ADD(p, dst, src0, negate(src1));
1117 }
1118 brw_pop_insn_state(p);
1119 } else {
1120 /* replicate the derivative at the top-left pixel to other pixels */
1121 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1122 src.negate, src.abs,
1123 BRW_REGISTER_TYPE_F,
1124 BRW_VERTICAL_STRIDE_4,
1125 BRW_WIDTH_4,
1126 BRW_HORIZONTAL_STRIDE_0,
1127 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1128 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1129 src.negate, src.abs,
1130 BRW_REGISTER_TYPE_F,
1131 BRW_VERTICAL_STRIDE_4,
1132 BRW_WIDTH_4,
1133 BRW_HORIZONTAL_STRIDE_0,
1134 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1135 if (negate_value)
1136 brw_ADD(p, dst, src1, negate(src0));
1137 else
1138 brw_ADD(p, dst, src0, negate(src1));
1139 }
1140 }
1141
1142 void
1143 fs_generator::generate_discard_jump(fs_inst *inst)
1144 {
1145 assert(devinfo->gen >= 6);
1146
1147 /* This HALT will be patched up at FB write time to point UIP at the end of
1148 * the program, and at brw_uip_jip() JIP will be set to the end of the
1149 * current block (or the program).
1150 */
1151 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1152
1153 brw_push_insn_state(p);
1154 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1155 gen6_HALT(p);
1156 brw_pop_insn_state(p);
1157 }
1158
1159 void
1160 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1161 {
1162 assert(inst->mlen != 0);
1163
1164 brw_MOV(p,
1165 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1166 retype(src, BRW_REGISTER_TYPE_UD));
1167 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1168 inst->exec_size / 8, inst->offset);
1169 }
1170
1171 void
1172 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1173 {
1174 assert(inst->mlen != 0);
1175
1176 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1177 inst->exec_size / 8, inst->offset);
1178 }
1179
1180 void
1181 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1182 {
1183 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1184 }
1185
1186 void
1187 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1188 struct brw_reg dst,
1189 struct brw_reg index,
1190 struct brw_reg offset)
1191 {
1192 assert(inst->mlen != 0);
1193
1194 assert(index.file == BRW_IMMEDIATE_VALUE &&
1195 index.type == BRW_REGISTER_TYPE_UD);
1196 uint32_t surf_index = index.ud;
1197
1198 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1199 offset.type == BRW_REGISTER_TYPE_UD);
1200 uint32_t read_offset = offset.ud;
1201
1202 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1203 read_offset, surf_index);
1204 }
1205
1206 void
1207 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1208 struct brw_reg dst,
1209 struct brw_reg index,
1210 struct brw_reg offset)
1211 {
1212 assert(index.type == BRW_REGISTER_TYPE_UD);
1213
1214 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1215 /* Reference just the dword we need, to avoid angering validate_reg(). */
1216 offset = brw_vec1_grf(offset.nr, 0);
1217
1218 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1219 * the destination loaded consecutively from the same offset (which appears
1220 * in the first component, and the rest are ignored).
1221 */
1222 dst.width = BRW_WIDTH_4;
1223
1224 struct brw_reg src = offset;
1225 bool header_present = false;
1226
1227 if (devinfo->gen >= 9) {
1228 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1229 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1230 header_present = true;
1231
1232 brw_push_insn_state(p);
1233 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1234 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1235 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1236 brw_set_default_access_mode(p, BRW_ALIGN_1);
1237
1238 brw_MOV(p, get_element_ud(src, 2),
1239 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1240 brw_pop_insn_state(p);
1241 }
1242
1243 if (index.file == BRW_IMMEDIATE_VALUE) {
1244
1245 uint32_t surf_index = index.ud;
1246
1247 brw_push_insn_state(p);
1248 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1249 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1250 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1251 brw_pop_insn_state(p);
1252
1253 brw_set_dest(p, send, dst);
1254 brw_set_src0(p, send, src);
1255 brw_set_sampler_message(p, send,
1256 surf_index,
1257 0, /* LD message ignores sampler unit */
1258 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1259 1, /* rlen */
1260 inst->mlen,
1261 header_present,
1262 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1263 0);
1264 } else {
1265
1266 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1267
1268 brw_push_insn_state(p);
1269 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1270 brw_set_default_access_mode(p, BRW_ALIGN_1);
1271
1272 /* a0.0 = surf_index & 0xff */
1273 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1274 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1275 brw_set_dest(p, insn_and, addr);
1276 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1277 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1278
1279 /* dst = send(payload, a0.0 | <descriptor>) */
1280 brw_inst *insn = brw_send_indirect_message(
1281 p, BRW_SFID_SAMPLER, dst, src, addr);
1282 brw_set_sampler_message(p, insn,
1283 0,
1284 0, /* LD message ignores sampler unit */
1285 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1286 1, /* rlen */
1287 inst->mlen,
1288 header_present,
1289 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1290 0);
1291
1292 brw_pop_insn_state(p);
1293 }
1294 }
1295
1296 void
1297 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1298 struct brw_reg dst,
1299 struct brw_reg index,
1300 struct brw_reg offset)
1301 {
1302 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1303 assert(inst->header_size != 0);
1304 assert(inst->mlen);
1305
1306 assert(index.file == BRW_IMMEDIATE_VALUE &&
1307 index.type == BRW_REGISTER_TYPE_UD);
1308 uint32_t surf_index = index.ud;
1309
1310 uint32_t simd_mode, rlen, msg_type;
1311 if (dispatch_width == 16) {
1312 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1313 rlen = 8;
1314 } else {
1315 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1316 rlen = 4;
1317 }
1318
1319 if (devinfo->gen >= 5)
1320 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1321 else {
1322 /* We always use the SIMD16 message so that we only have to load U, and
1323 * not V or R.
1324 */
1325 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1326 assert(inst->mlen == 3);
1327 assert(inst->regs_written == 8);
1328 rlen = 8;
1329 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1330 }
1331
1332 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1333 BRW_REGISTER_TYPE_D);
1334 brw_MOV(p, offset_mrf, offset);
1335
1336 struct brw_reg header = brw_vec8_grf(0, 0);
1337 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1338
1339 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1340 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1341 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1342 brw_set_src0(p, send, header);
1343 if (devinfo->gen < 6)
1344 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1345
1346 /* Our surface is set up as floats, regardless of what actual data is
1347 * stored in it.
1348 */
1349 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1350 brw_set_sampler_message(p, send,
1351 surf_index,
1352 0, /* sampler (unused) */
1353 msg_type,
1354 rlen,
1355 inst->mlen,
1356 inst->header_size != 0,
1357 simd_mode,
1358 return_format);
1359 }
1360
1361 void
1362 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1363 struct brw_reg dst,
1364 struct brw_reg index,
1365 struct brw_reg offset)
1366 {
1367 assert(devinfo->gen >= 7);
1368 /* Varying-offset pull constant loads are treated as a normal expression on
1369 * gen7, so the fact that it's a send message is hidden at the IR level.
1370 */
1371 assert(inst->header_size == 0);
1372 assert(!inst->mlen);
1373 assert(index.type == BRW_REGISTER_TYPE_UD);
1374
1375 uint32_t simd_mode, rlen, mlen;
1376 if (dispatch_width == 16) {
1377 mlen = 2;
1378 rlen = 8;
1379 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1380 } else {
1381 mlen = 1;
1382 rlen = 4;
1383 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1384 }
1385
1386 if (index.file == BRW_IMMEDIATE_VALUE) {
1387
1388 uint32_t surf_index = index.ud;
1389
1390 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1391 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1392 brw_set_src0(p, send, offset);
1393 brw_set_sampler_message(p, send,
1394 surf_index,
1395 0, /* LD message ignores sampler unit */
1396 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1397 rlen,
1398 mlen,
1399 false, /* no header */
1400 simd_mode,
1401 0);
1402
1403 } else {
1404
1405 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1406
1407 brw_push_insn_state(p);
1408 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1409 brw_set_default_access_mode(p, BRW_ALIGN_1);
1410
1411 /* a0.0 = surf_index & 0xff */
1412 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1413 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1414 brw_set_dest(p, insn_and, addr);
1415 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1416 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1417
1418 brw_pop_insn_state(p);
1419
1420 /* dst = send(offset, a0.0 | <descriptor>) */
1421 brw_inst *insn = brw_send_indirect_message(
1422 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1423 offset, addr);
1424 brw_set_sampler_message(p, insn,
1425 0 /* surface */,
1426 0 /* sampler */,
1427 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1428 rlen /* rlen */,
1429 mlen /* mlen */,
1430 false /* header */,
1431 simd_mode,
1432 0);
1433 }
1434 }
1435
1436 /**
1437 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1438 * into the flags register (f0.0).
1439 *
1440 * Used only on Gen6 and above.
1441 */
1442 void
1443 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1444 {
1445 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1446 struct brw_reg dispatch_mask;
1447
1448 if (devinfo->gen >= 6)
1449 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1450 else
1451 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1452
1453 brw_push_insn_state(p);
1454 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1455 brw_MOV(p, flags, dispatch_mask);
1456 brw_pop_insn_state(p);
1457 }
1458
1459 void
1460 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1461 struct brw_reg dst,
1462 struct brw_reg src,
1463 struct brw_reg msg_data,
1464 unsigned msg_type)
1465 {
1466 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1467
1468 brw_pixel_interpolator_query(p,
1469 retype(dst, BRW_REGISTER_TYPE_UW),
1470 src,
1471 inst->pi_noperspective,
1472 msg_type,
1473 msg_data,
1474 inst->mlen,
1475 inst->regs_written);
1476 }
1477
1478
1479 /**
1480 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1481 * sampler LD messages.
1482 *
1483 * We don't want to bake it into the send message's code generation because
1484 * that means we don't get a chance to schedule the instructions.
1485 */
1486 void
1487 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1488 struct brw_reg dst,
1489 struct brw_reg value)
1490 {
1491 assert(value.file == BRW_IMMEDIATE_VALUE);
1492
1493 brw_push_insn_state(p);
1494 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1495 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1496 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1497 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1498 brw_pop_insn_state(p);
1499 }
1500
1501 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1502 * the ADD instruction.
1503 */
1504 void
1505 fs_generator::generate_set_sample_id(fs_inst *inst,
1506 struct brw_reg dst,
1507 struct brw_reg src0,
1508 struct brw_reg src1)
1509 {
1510 assert(dst.type == BRW_REGISTER_TYPE_D ||
1511 dst.type == BRW_REGISTER_TYPE_UD);
1512 assert(src0.type == BRW_REGISTER_TYPE_D ||
1513 src0.type == BRW_REGISTER_TYPE_UD);
1514
1515 struct brw_reg reg = stride(src1, 1, 4, 0);
1516 if (devinfo->gen >= 8 || dispatch_width == 8) {
1517 brw_ADD(p, dst, src0, reg);
1518 } else if (dispatch_width == 16) {
1519 brw_push_insn_state(p);
1520 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1521 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1522 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1523 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1524 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1525 brw_pop_insn_state(p);
1526 }
1527 }
1528
1529 void
1530 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1531 struct brw_reg dst,
1532 struct brw_reg x,
1533 struct brw_reg y)
1534 {
1535 assert(devinfo->gen >= 7);
1536 assert(dst.type == BRW_REGISTER_TYPE_UD);
1537 assert(x.type == BRW_REGISTER_TYPE_F);
1538 assert(y.type == BRW_REGISTER_TYPE_F);
1539
1540 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1541 *
1542 * Because this instruction does not have a 16-bit floating-point type,
1543 * the destination data type must be Word (W).
1544 *
1545 * The destination must be DWord-aligned and specify a horizontal stride
1546 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1547 * each destination channel and the upper word is not modified.
1548 */
1549 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1550
1551 /* Give each 32-bit channel of dst the form below, where "." means
1552 * unchanged.
1553 * 0x....hhhh
1554 */
1555 brw_F32TO16(p, dst_w, y);
1556
1557 /* Now the form:
1558 * 0xhhhh0000
1559 */
1560 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1561
1562 /* And, finally the form of packHalf2x16's output:
1563 * 0xhhhhllll
1564 */
1565 brw_F32TO16(p, dst_w, x);
1566 }
1567
1568 void
1569 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1570 struct brw_reg dst,
1571 struct brw_reg src)
1572 {
1573 assert(devinfo->gen >= 7);
1574 assert(dst.type == BRW_REGISTER_TYPE_F);
1575 assert(src.type == BRW_REGISTER_TYPE_UD);
1576
1577 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1578 *
1579 * Because this instruction does not have a 16-bit floating-point type,
1580 * the source data type must be Word (W). The destination type must be
1581 * F (Float).
1582 */
1583 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1584
1585 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1586 * For the Y case, we wish to access only the upper word; therefore
1587 * a 16-bit subregister offset is needed.
1588 */
1589 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1590 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1591 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1592 src_w.subnr += 2;
1593
1594 brw_F16TO32(p, dst, src_w);
1595 }
1596
1597 void
1598 fs_generator::generate_shader_time_add(fs_inst *inst,
1599 struct brw_reg payload,
1600 struct brw_reg offset,
1601 struct brw_reg value)
1602 {
1603 assert(devinfo->gen >= 7);
1604 brw_push_insn_state(p);
1605 brw_set_default_mask_control(p, true);
1606
1607 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1608 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1609 offset.type);
1610 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1611 value.type);
1612
1613 assert(offset.file == BRW_IMMEDIATE_VALUE);
1614 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1615 value.width = BRW_WIDTH_1;
1616 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1617 value.vstride = BRW_VERTICAL_STRIDE_0;
1618 } else {
1619 assert(value.file == BRW_IMMEDIATE_VALUE);
1620 }
1621
1622 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1623 * case, and we don't really care about squeezing every bit of performance
1624 * out of this path, so we just emit the MOVs from here.
1625 */
1626 brw_MOV(p, payload_offset, offset);
1627 brw_MOV(p, payload_value, value);
1628 brw_shader_time_add(p, payload,
1629 prog_data->binding_table.shader_time_start);
1630 brw_pop_insn_state(p);
1631
1632 brw_mark_surface_used(prog_data,
1633 prog_data->binding_table.shader_time_start);
1634 }
1635
1636 void
1637 fs_generator::enable_debug(const char *shader_name)
1638 {
1639 debug_flag = true;
1640 this->shader_name = shader_name;
1641 }
1642
1643 int
1644 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1645 {
1646 /* align to 64 byte boundary. */
1647 while (p->next_insn_offset % 64)
1648 brw_NOP(p);
1649
1650 this->dispatch_width = dispatch_width;
1651 if (dispatch_width == 16)
1652 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1653
1654 int start_offset = p->next_insn_offset;
1655 int spill_count = 0, fill_count = 0;
1656 int loop_count = 0;
1657
1658 struct annotation_info annotation;
1659 memset(&annotation, 0, sizeof(annotation));
1660
1661 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1662 struct brw_reg src[3], dst;
1663 unsigned int last_insn_offset = p->next_insn_offset;
1664 bool multiple_instructions_emitted = false;
1665
1666 if (unlikely(debug_flag))
1667 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1668
1669 for (unsigned int i = 0; i < inst->sources; i++) {
1670 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1671
1672 /* The accumulator result appears to get used for the
1673 * conditional modifier generation. When negating a UD
1674 * value, there is a 33rd bit generated for the sign in the
1675 * accumulator value, so now you can't check, for example,
1676 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1677 */
1678 assert(!inst->conditional_mod ||
1679 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1680 !inst->src[i].negate);
1681 }
1682 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1683
1684 brw_set_default_predicate_control(p, inst->predicate);
1685 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1686 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1687 brw_set_default_saturate(p, inst->saturate);
1688 brw_set_default_mask_control(p, inst->force_writemask_all);
1689 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1690 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1691
1692 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1693 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1694
1695 switch (inst->exec_size) {
1696 case 1:
1697 case 2:
1698 case 4:
1699 assert(inst->force_writemask_all);
1700 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1701 break;
1702 case 8:
1703 if (inst->force_sechalf) {
1704 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1705 } else {
1706 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1707 }
1708 break;
1709 case 16:
1710 case 32:
1711 /* If the instruction writes to more than one register, it needs to
1712 * be a "compressed" instruction on Gen <= 5.
1713 */
1714 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1715 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1716 else
1717 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1718 break;
1719 default:
1720 unreachable("Invalid instruction width");
1721 }
1722
1723 switch (inst->opcode) {
1724 case BRW_OPCODE_MOV:
1725 brw_MOV(p, dst, src[0]);
1726 break;
1727 case BRW_OPCODE_ADD:
1728 brw_ADD(p, dst, src[0], src[1]);
1729 break;
1730 case BRW_OPCODE_MUL:
1731 brw_MUL(p, dst, src[0], src[1]);
1732 break;
1733 case BRW_OPCODE_AVG:
1734 brw_AVG(p, dst, src[0], src[1]);
1735 break;
1736 case BRW_OPCODE_MACH:
1737 brw_MACH(p, dst, src[0], src[1]);
1738 break;
1739
1740 case BRW_OPCODE_LINE:
1741 brw_LINE(p, dst, src[0], src[1]);
1742 break;
1743
1744 case BRW_OPCODE_MAD:
1745 assert(devinfo->gen >= 6);
1746 brw_set_default_access_mode(p, BRW_ALIGN_16);
1747 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1748 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1749 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1750 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1751 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1752 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1753 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1754
1755 if (inst->conditional_mod) {
1756 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1757 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1758 multiple_instructions_emitted = true;
1759 }
1760 } else {
1761 brw_MAD(p, dst, src[0], src[1], src[2]);
1762 }
1763 brw_set_default_access_mode(p, BRW_ALIGN_1);
1764 break;
1765
1766 case BRW_OPCODE_LRP:
1767 assert(devinfo->gen >= 6);
1768 brw_set_default_access_mode(p, BRW_ALIGN_16);
1769 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1770 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1771 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1772 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1773 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1774 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1775 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1776
1777 if (inst->conditional_mod) {
1778 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1779 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1780 multiple_instructions_emitted = true;
1781 }
1782 } else {
1783 brw_LRP(p, dst, src[0], src[1], src[2]);
1784 }
1785 brw_set_default_access_mode(p, BRW_ALIGN_1);
1786 break;
1787
1788 case BRW_OPCODE_FRC:
1789 brw_FRC(p, dst, src[0]);
1790 break;
1791 case BRW_OPCODE_RNDD:
1792 brw_RNDD(p, dst, src[0]);
1793 break;
1794 case BRW_OPCODE_RNDE:
1795 brw_RNDE(p, dst, src[0]);
1796 break;
1797 case BRW_OPCODE_RNDZ:
1798 brw_RNDZ(p, dst, src[0]);
1799 break;
1800
1801 case BRW_OPCODE_AND:
1802 brw_AND(p, dst, src[0], src[1]);
1803 break;
1804 case BRW_OPCODE_OR:
1805 brw_OR(p, dst, src[0], src[1]);
1806 break;
1807 case BRW_OPCODE_XOR:
1808 brw_XOR(p, dst, src[0], src[1]);
1809 break;
1810 case BRW_OPCODE_NOT:
1811 brw_NOT(p, dst, src[0]);
1812 break;
1813 case BRW_OPCODE_ASR:
1814 brw_ASR(p, dst, src[0], src[1]);
1815 break;
1816 case BRW_OPCODE_SHR:
1817 brw_SHR(p, dst, src[0], src[1]);
1818 break;
1819 case BRW_OPCODE_SHL:
1820 brw_SHL(p, dst, src[0], src[1]);
1821 break;
1822 case BRW_OPCODE_F32TO16:
1823 assert(devinfo->gen >= 7);
1824 brw_F32TO16(p, dst, src[0]);
1825 break;
1826 case BRW_OPCODE_F16TO32:
1827 assert(devinfo->gen >= 7);
1828 brw_F16TO32(p, dst, src[0]);
1829 break;
1830 case BRW_OPCODE_CMP:
1831 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1832 * that when the destination is a GRF that the dependency-clear bit on
1833 * the flag register is cleared early.
1834 *
1835 * Suggested workarounds are to disable coissuing CMP instructions
1836 * or to split CMP(16) instructions into two CMP(8) instructions.
1837 *
1838 * We choose to split into CMP(8) instructions since disabling
1839 * coissuing would affect CMP instructions not otherwise affected by
1840 * the errata.
1841 */
1842 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1843 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1844 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1845 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1846 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1847 firsthalf(src[0]), firsthalf(src[1]));
1848 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1849 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1850 sechalf(src[0]), sechalf(src[1]));
1851 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1852
1853 multiple_instructions_emitted = true;
1854 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1855 /* For unknown reasons, the aforementioned workaround is not
1856 * sufficient. Overriding the type when the destination is the
1857 * null register is necessary but not sufficient by itself.
1858 */
1859 assert(dst.nr == BRW_ARF_NULL);
1860 dst.type = BRW_REGISTER_TYPE_D;
1861 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1862 } else {
1863 unreachable("not reached");
1864 }
1865 } else {
1866 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1867 }
1868 break;
1869 case BRW_OPCODE_SEL:
1870 brw_SEL(p, dst, src[0], src[1]);
1871 break;
1872 case BRW_OPCODE_BFREV:
1873 assert(devinfo->gen >= 7);
1874 /* BFREV only supports UD type for src and dst. */
1875 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1876 retype(src[0], BRW_REGISTER_TYPE_UD));
1877 break;
1878 case BRW_OPCODE_FBH:
1879 assert(devinfo->gen >= 7);
1880 /* FBH only supports UD type for dst. */
1881 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1882 break;
1883 case BRW_OPCODE_FBL:
1884 assert(devinfo->gen >= 7);
1885 /* FBL only supports UD type for dst. */
1886 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1887 break;
1888 case BRW_OPCODE_CBIT:
1889 assert(devinfo->gen >= 7);
1890 /* CBIT only supports UD type for dst. */
1891 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1892 break;
1893 case BRW_OPCODE_ADDC:
1894 assert(devinfo->gen >= 7);
1895 brw_ADDC(p, dst, src[0], src[1]);
1896 break;
1897 case BRW_OPCODE_SUBB:
1898 assert(devinfo->gen >= 7);
1899 brw_SUBB(p, dst, src[0], src[1]);
1900 break;
1901 case BRW_OPCODE_MAC:
1902 brw_MAC(p, dst, src[0], src[1]);
1903 break;
1904
1905 case BRW_OPCODE_BFE:
1906 assert(devinfo->gen >= 7);
1907 brw_set_default_access_mode(p, BRW_ALIGN_16);
1908 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1909 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1910 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1911 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1912 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1913 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1914 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1915 } else {
1916 brw_BFE(p, dst, src[0], src[1], src[2]);
1917 }
1918 brw_set_default_access_mode(p, BRW_ALIGN_1);
1919 break;
1920
1921 case BRW_OPCODE_BFI1:
1922 assert(devinfo->gen >= 7);
1923 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1924 * should
1925 *
1926 * "Force BFI instructions to be executed always in SIMD8."
1927 */
1928 if (dispatch_width == 16 && devinfo->is_haswell) {
1929 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1930 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1931 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1932 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1933 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1934 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1935 } else {
1936 brw_BFI1(p, dst, src[0], src[1]);
1937 }
1938 break;
1939 case BRW_OPCODE_BFI2:
1940 assert(devinfo->gen >= 7);
1941 brw_set_default_access_mode(p, BRW_ALIGN_16);
1942 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1943 * should
1944 *
1945 * "Force BFI instructions to be executed always in SIMD8."
1946 *
1947 * Otherwise we would be able to emit compressed instructions like we
1948 * do for the other three-source instructions.
1949 */
1950 if (dispatch_width == 16 &&
1951 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1952 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1953 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1954 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1955 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1956 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1957 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1958 } else {
1959 brw_BFI2(p, dst, src[0], src[1], src[2]);
1960 }
1961 brw_set_default_access_mode(p, BRW_ALIGN_1);
1962 break;
1963
1964 case BRW_OPCODE_IF:
1965 if (inst->src[0].file != BAD_FILE) {
1966 /* The instruction has an embedded compare (only allowed on gen6) */
1967 assert(devinfo->gen == 6);
1968 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1969 } else {
1970 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1971 }
1972 break;
1973
1974 case BRW_OPCODE_ELSE:
1975 brw_ELSE(p);
1976 break;
1977 case BRW_OPCODE_ENDIF:
1978 brw_ENDIF(p);
1979 break;
1980
1981 case BRW_OPCODE_DO:
1982 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1983 break;
1984
1985 case BRW_OPCODE_BREAK:
1986 brw_BREAK(p);
1987 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1988 break;
1989 case BRW_OPCODE_CONTINUE:
1990 brw_CONT(p);
1991 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1992 break;
1993
1994 case BRW_OPCODE_WHILE:
1995 brw_WHILE(p);
1996 loop_count++;
1997 break;
1998
1999 case SHADER_OPCODE_RCP:
2000 case SHADER_OPCODE_RSQ:
2001 case SHADER_OPCODE_SQRT:
2002 case SHADER_OPCODE_EXP2:
2003 case SHADER_OPCODE_LOG2:
2004 case SHADER_OPCODE_SIN:
2005 case SHADER_OPCODE_COS:
2006 assert(devinfo->gen < 6 || inst->mlen == 0);
2007 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2008 if (devinfo->gen >= 7) {
2009 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2010 brw_null_reg());
2011 } else if (devinfo->gen == 6) {
2012 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2013 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2014 generate_math_g45(inst, dst, src[0]);
2015 } else {
2016 generate_math_gen4(inst, dst, src[0]);
2017 }
2018 break;
2019 case SHADER_OPCODE_INT_QUOTIENT:
2020 case SHADER_OPCODE_INT_REMAINDER:
2021 case SHADER_OPCODE_POW:
2022 assert(devinfo->gen < 6 || inst->mlen == 0);
2023 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2024 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2025 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2026 } else if (devinfo->gen >= 6) {
2027 generate_math_gen6(inst, dst, src[0], src[1]);
2028 } else {
2029 generate_math_gen4(inst, dst, src[0]);
2030 }
2031 break;
2032 case FS_OPCODE_CINTERP:
2033 brw_MOV(p, dst, src[0]);
2034 break;
2035 case FS_OPCODE_LINTERP:
2036 generate_linterp(inst, dst, src);
2037 break;
2038 case FS_OPCODE_PIXEL_X:
2039 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2040 src[0].subnr = 0 * type_sz(src[0].type);
2041 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2042 break;
2043 case FS_OPCODE_PIXEL_Y:
2044 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2045 src[0].subnr = 4 * type_sz(src[0].type);
2046 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2047 break;
2048 case FS_OPCODE_GET_BUFFER_SIZE:
2049 generate_get_buffer_size(inst, dst, src[0], src[1]);
2050 break;
2051 case SHADER_OPCODE_TEX:
2052 case FS_OPCODE_TXB:
2053 case SHADER_OPCODE_TXD:
2054 case SHADER_OPCODE_TXF:
2055 case SHADER_OPCODE_TXF_CMS:
2056 case SHADER_OPCODE_TXF_CMS_W:
2057 case SHADER_OPCODE_TXF_UMS:
2058 case SHADER_OPCODE_TXF_MCS:
2059 case SHADER_OPCODE_TXL:
2060 case SHADER_OPCODE_TXS:
2061 case SHADER_OPCODE_LOD:
2062 case SHADER_OPCODE_TG4:
2063 case SHADER_OPCODE_TG4_OFFSET:
2064 case SHADER_OPCODE_SAMPLEINFO:
2065 generate_tex(inst, dst, src[0], src[1]);
2066 break;
2067 case FS_OPCODE_DDX_COARSE:
2068 case FS_OPCODE_DDX_FINE:
2069 generate_ddx(inst->opcode, dst, src[0]);
2070 break;
2071 case FS_OPCODE_DDY_COARSE:
2072 case FS_OPCODE_DDY_FINE:
2073 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2074 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2075 break;
2076
2077 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2078 generate_scratch_write(inst, src[0]);
2079 spill_count++;
2080 break;
2081
2082 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2083 generate_scratch_read(inst, dst);
2084 fill_count++;
2085 break;
2086
2087 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2088 generate_scratch_read_gen7(inst, dst);
2089 fill_count++;
2090 break;
2091
2092 case SHADER_OPCODE_MOV_INDIRECT:
2093 generate_mov_indirect(inst, dst, src[0], src[1]);
2094 break;
2095
2096 case SHADER_OPCODE_URB_READ_SIMD8:
2097 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2098 generate_urb_read(inst, dst, src[0]);
2099 break;
2100
2101 case SHADER_OPCODE_URB_WRITE_SIMD8:
2102 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2103 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2104 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2105 generate_urb_write(inst, src[0]);
2106 break;
2107
2108 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2109 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2110 break;
2111
2112 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2113 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2114 break;
2115
2116 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2117 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2118 break;
2119
2120 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2121 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2122 break;
2123
2124 case FS_OPCODE_REP_FB_WRITE:
2125 case FS_OPCODE_FB_WRITE:
2126 generate_fb_write(inst, src[0]);
2127 break;
2128
2129 case FS_OPCODE_BLORP_FB_WRITE:
2130 generate_blorp_fb_write(inst);
2131 break;
2132
2133 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2134 generate_mov_dispatch_to_flags(inst);
2135 break;
2136
2137 case FS_OPCODE_DISCARD_JUMP:
2138 generate_discard_jump(inst);
2139 break;
2140
2141 case SHADER_OPCODE_SHADER_TIME_ADD:
2142 generate_shader_time_add(inst, src[0], src[1], src[2]);
2143 break;
2144
2145 case SHADER_OPCODE_UNTYPED_ATOMIC:
2146 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2147 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2148 inst->mlen, !inst->dst.is_null());
2149 break;
2150
2151 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2152 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2153 brw_untyped_surface_read(p, dst, src[0], src[1],
2154 inst->mlen, src[2].ud);
2155 break;
2156
2157 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2158 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2159 brw_untyped_surface_write(p, src[0], src[1],
2160 inst->mlen, src[2].ud);
2161 break;
2162
2163 case SHADER_OPCODE_TYPED_ATOMIC:
2164 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2165 brw_typed_atomic(p, dst, src[0], src[1],
2166 src[2].ud, inst->mlen, !inst->dst.is_null());
2167 break;
2168
2169 case SHADER_OPCODE_TYPED_SURFACE_READ:
2170 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2171 brw_typed_surface_read(p, dst, src[0], src[1],
2172 inst->mlen, src[2].ud);
2173 break;
2174
2175 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2176 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2177 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2178 break;
2179
2180 case SHADER_OPCODE_MEMORY_FENCE:
2181 brw_memory_fence(p, dst);
2182 break;
2183
2184 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2185 generate_set_simd4x2_offset(inst, dst, src[0]);
2186 break;
2187
2188 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2189 brw_find_live_channel(p, dst);
2190 break;
2191
2192 case SHADER_OPCODE_BROADCAST:
2193 brw_broadcast(p, dst, src[0], src[1]);
2194 break;
2195
2196 case FS_OPCODE_SET_SAMPLE_ID:
2197 generate_set_sample_id(inst, dst, src[0], src[1]);
2198 break;
2199
2200 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2201 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2202 break;
2203
2204 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2205 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2206 generate_unpack_half_2x16_split(inst, dst, src[0]);
2207 break;
2208
2209 case FS_OPCODE_PLACEHOLDER_HALT:
2210 /* This is the place where the final HALT needs to be inserted if
2211 * we've emitted any discards. If not, this will emit no code.
2212 */
2213 if (!patch_discard_jumps_to_fb_writes()) {
2214 if (unlikely(debug_flag)) {
2215 annotation.ann_count--;
2216 }
2217 }
2218 break;
2219
2220 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2221 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2222 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2223 break;
2224
2225 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2226 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2227 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2228 break;
2229
2230 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2231 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2232 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2233 break;
2234
2235 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2236 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2237 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2238 break;
2239
2240 case CS_OPCODE_CS_TERMINATE:
2241 generate_cs_terminate(inst, src[0]);
2242 break;
2243
2244 case SHADER_OPCODE_BARRIER:
2245 generate_barrier(inst, src[0]);
2246 break;
2247
2248 case FS_OPCODE_PACK_STENCIL_REF:
2249 generate_stencil_ref_packing(inst, dst, src[0]);
2250 break;
2251
2252 default:
2253 unreachable("Unsupported opcode");
2254
2255 case SHADER_OPCODE_LOAD_PAYLOAD:
2256 unreachable("Should be lowered by lower_load_payload()");
2257 }
2258
2259 if (multiple_instructions_emitted)
2260 continue;
2261
2262 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2263 assert(p->next_insn_offset == last_insn_offset + 16 ||
2264 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2265 "emitting more than 1 instruction");
2266
2267 brw_inst *last = &p->store[last_insn_offset / 16];
2268
2269 if (inst->conditional_mod)
2270 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2271 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2272 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2273 }
2274 }
2275
2276 brw_set_uip_jip(p);
2277 annotation_finalize(&annotation, p->next_insn_offset);
2278
2279 #ifndef NDEBUG
2280 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2281 #else
2282 if (unlikely(debug_flag))
2283 brw_validate_instructions(p, start_offset, &annotation);
2284 #endif
2285
2286 int before_size = p->next_insn_offset - start_offset;
2287 brw_compact_instructions(p, start_offset, annotation.ann_count,
2288 annotation.ann);
2289 int after_size = p->next_insn_offset - start_offset;
2290
2291 if (unlikely(debug_flag)) {
2292 fprintf(stderr, "Native code for %s\n"
2293 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2294 " bytes (%.0f%%)\n",
2295 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2296 spill_count, fill_count, promoted_constants, before_size, after_size,
2297 100.0f * (before_size - after_size) / before_size);
2298
2299 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2300 p->devinfo);
2301 ralloc_free(annotation.mem_ctx);
2302 }
2303 assert(validated);
2304
2305 compiler->shader_debug_log(log_data,
2306 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2307 "%d:%d spills:fills, Promoted %u constants, "
2308 "compacted %d to %d bytes.\n",
2309 stage_abbrev, dispatch_width, before_size / 16,
2310 loop_count, cfg->cycle_count, spill_count,
2311 fill_count, promoted_constants, before_size,
2312 after_size);
2313
2314 return start_offset;
2315 }
2316
2317 const unsigned *
2318 fs_generator::get_assembly(unsigned int *assembly_size)
2319 {
2320 return brw_get_program(p, assembly_size);
2321 }