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i965/fs: Refactor generate_tex in prep for nonconst sampler indexing
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 extern "C" {
31 #include "main/macros.h"
32 #include "brw_context.h"
33 #include "brw_eu.h"
34 } /* extern "C" */
35
36 #include "brw_fs.h"
37 #include "brw_cfg.h"
38
39 fs_generator::fs_generator(struct brw_context *brw,
40 void *mem_ctx,
41 const struct brw_wm_prog_key *key,
42 struct brw_wm_prog_data *prog_data,
43 struct gl_shader_program *prog,
44 struct gl_fragment_program *fp,
45 bool runtime_check_aads_emit,
46 bool debug_flag)
47
48 : brw(brw), key(key), prog_data(prog_data), prog(prog), fp(fp),
49 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(debug_flag),
50 mem_ctx(mem_ctx)
51 {
52 ctx = &brw->ctx;
53
54 p = rzalloc(mem_ctx, struct brw_compile);
55 brw_init_compile(brw, p, mem_ctx);
56 }
57
58 fs_generator::~fs_generator()
59 {
60 }
61
62 bool
63 fs_generator::patch_discard_jumps_to_fb_writes()
64 {
65 if (brw->gen < 6 || this->discard_halt_patches.is_empty())
66 return false;
67
68 int scale = brw_jump_scale(brw);
69
70 /* There is a somewhat strange undocumented requirement of using
71 * HALT, according to the simulator. If some channel has HALTed to
72 * a particular UIP, then by the end of the program, every channel
73 * must have HALTed to that UIP. Furthermore, the tracking is a
74 * stack, so you can't do the final halt of a UIP after starting
75 * halting to a new UIP.
76 *
77 * Symptoms of not emitting this instruction on actual hardware
78 * included GPU hangs and sparkly rendering on the piglit discard
79 * tests.
80 */
81 brw_inst *last_halt = gen6_HALT(p);
82 brw_inst_set_uip(brw, last_halt, 1 * scale);
83 brw_inst_set_jip(brw, last_halt, 1 * scale);
84
85 int ip = p->nr_insn;
86
87 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
88 brw_inst *patch = &p->store[patch_ip->ip];
89
90 assert(brw_inst_opcode(brw, patch) == BRW_OPCODE_HALT);
91 /* HALT takes a half-instruction distance from the pre-incremented IP. */
92 brw_inst_set_uip(brw, patch, (ip - patch_ip->ip) * scale);
93 }
94
95 this->discard_halt_patches.make_empty();
96 return true;
97 }
98
99 void
100 fs_generator::fire_fb_write(fs_inst *inst,
101 GLuint base_reg,
102 struct brw_reg implied_header,
103 GLuint nr)
104 {
105 uint32_t msg_control;
106
107 if (brw->gen < 6) {
108 brw_push_insn_state(p);
109 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
110 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
111 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
112 brw_MOV(p,
113 brw_message_reg(base_reg + 1),
114 brw_vec8_grf(1, 0));
115 brw_pop_insn_state(p);
116 }
117
118 if (prog_data->dual_src_blend)
119 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
120 else if (dispatch_width == 16)
121 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
122 else
123 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
124
125 uint32_t surf_index =
126 prog_data->binding_table.render_target_start + inst->target;
127
128 brw_fb_WRITE(p,
129 dispatch_width,
130 base_reg,
131 implied_header,
132 msg_control,
133 surf_index,
134 nr,
135 0,
136 inst->eot,
137 inst->header_present);
138
139 brw_mark_surface_used(&prog_data->base, surf_index);
140 }
141
142 void
143 fs_generator::generate_fb_write(fs_inst *inst)
144 {
145 struct brw_reg implied_header;
146
147 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
148 * move, here's g1.
149 */
150 if (inst->header_present) {
151 brw_push_insn_state(p);
152 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
153 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
154 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
155 brw_set_default_flag_reg(p, 0, 0);
156
157 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
158 * present.
159 */
160 if ((fp && fp->UsesKill) || key->alpha_test_func) {
161 struct brw_reg pixel_mask;
162
163 if (brw->gen >= 6)
164 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
165 else
166 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
167
168 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
169 }
170
171 if (brw->gen >= 6) {
172 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
173 brw_MOV(p,
174 retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD),
175 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
176 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
177
178 if (inst->target > 0 && key->replicate_alpha) {
179 /* Set "Source0 Alpha Present to RenderTarget" bit in message
180 * header.
181 */
182 brw_OR(p,
183 vec1(retype(brw_message_reg(inst->base_mrf), BRW_REGISTER_TYPE_UD)),
184 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
185 brw_imm_ud(0x1 << 11));
186 }
187
188 if (inst->target > 0) {
189 /* Set the render target index for choosing BLEND_STATE. */
190 brw_MOV(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
191 inst->base_mrf, 2),
192 BRW_REGISTER_TYPE_UD),
193 brw_imm_ud(inst->target));
194 }
195
196 implied_header = brw_null_reg();
197 } else {
198 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
199 }
200
201 brw_pop_insn_state(p);
202 } else {
203 implied_header = brw_null_reg();
204 }
205
206 if (!runtime_check_aads_emit) {
207 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
208 } else {
209 /* This can only happen in gen < 6 */
210 assert(brw->gen < 6);
211
212 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
213
214 /* Check runtime bit to detect if we have to send AA data or not */
215 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
216 brw_AND(p,
217 v1_null_ud,
218 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
219 brw_imm_ud(1<<26));
220 brw_inst_set_cond_modifier(brw, brw_last_inst, BRW_CONDITIONAL_NZ);
221
222 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
223 brw_inst_set_exec_size(brw, brw_last_inst, BRW_EXECUTE_1);
224 {
225 /* Don't send AA data */
226 fire_fb_write(inst, inst->base_mrf+1, implied_header, inst->mlen-1);
227 }
228 brw_land_fwd_jump(p, jmp);
229 fire_fb_write(inst, inst->base_mrf, implied_header, inst->mlen);
230 }
231 }
232
233 void
234 fs_generator::generate_blorp_fb_write(fs_inst *inst)
235 {
236 brw_fb_WRITE(p,
237 16 /* dispatch_width */,
238 inst->base_mrf,
239 brw_reg_from_fs_reg(&inst->src[0]),
240 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
241 inst->target,
242 inst->mlen,
243 0,
244 true,
245 inst->header_present);
246 }
247
248 /* Computes the integer pixel x,y values from the origin.
249 *
250 * This is the basis of gl_FragCoord computation, but is also used
251 * pre-gen6 for computing the deltas from v0 for computing
252 * interpolation.
253 */
254 void
255 fs_generator::generate_pixel_xy(struct brw_reg dst, bool is_x)
256 {
257 struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
258 struct brw_reg src;
259 struct brw_reg deltas;
260
261 if (is_x) {
262 src = stride(suboffset(g1_uw, 4), 2, 4, 0);
263 deltas = brw_imm_v(0x10101010);
264 } else {
265 src = stride(suboffset(g1_uw, 5), 2, 4, 0);
266 deltas = brw_imm_v(0x11001100);
267 }
268
269 if (dispatch_width == 16) {
270 dst = vec16(dst);
271 }
272
273 /* We do this SIMD8 or SIMD16, but since the destination is UW we
274 * don't do compression in the SIMD16 case.
275 */
276 brw_push_insn_state(p);
277 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
278 brw_ADD(p, dst, src, deltas);
279 brw_pop_insn_state(p);
280 }
281
282 void
283 fs_generator::generate_linterp(fs_inst *inst,
284 struct brw_reg dst, struct brw_reg *src)
285 {
286 struct brw_reg delta_x = src[0];
287 struct brw_reg delta_y = src[1];
288 struct brw_reg interp = src[2];
289
290 if (brw->has_pln &&
291 delta_y.nr == delta_x.nr + 1 &&
292 (brw->gen >= 6 || (delta_x.nr & 1) == 0)) {
293 brw_PLN(p, dst, interp, delta_x);
294 } else {
295 brw_LINE(p, brw_null_reg(), interp, delta_x);
296 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
297 }
298 }
299
300 void
301 fs_generator::generate_math_gen6(fs_inst *inst,
302 struct brw_reg dst,
303 struct brw_reg src0,
304 struct brw_reg src1)
305 {
306 int op = brw_math_function(inst->opcode);
307 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
308
309 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
310 gen6_math(p, dst, op, src0, src1);
311
312 if (dispatch_width == 16) {
313 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
314 gen6_math(p, sechalf(dst), op, sechalf(src0),
315 binop ? sechalf(src1) : brw_null_reg());
316 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
317 }
318 }
319
320 void
321 fs_generator::generate_math_gen4(fs_inst *inst,
322 struct brw_reg dst,
323 struct brw_reg src)
324 {
325 int op = brw_math_function(inst->opcode);
326
327 assert(inst->mlen >= 1);
328
329 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
330 gen4_math(p, dst,
331 op,
332 inst->base_mrf, src,
333 BRW_MATH_DATA_VECTOR,
334 BRW_MATH_PRECISION_FULL);
335
336 if (dispatch_width == 16) {
337 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
338 gen4_math(p, sechalf(dst),
339 op,
340 inst->base_mrf + 1, sechalf(src),
341 BRW_MATH_DATA_VECTOR,
342 BRW_MATH_PRECISION_FULL);
343
344 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
345 }
346 }
347
348 void
349 fs_generator::generate_math_g45(fs_inst *inst,
350 struct brw_reg dst,
351 struct brw_reg src)
352 {
353 if (inst->opcode == SHADER_OPCODE_POW ||
354 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
355 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
356 generate_math_gen4(inst, dst, src);
357 return;
358 }
359
360 int op = brw_math_function(inst->opcode);
361
362 assert(inst->mlen >= 1);
363
364 gen4_math(p, dst,
365 op,
366 inst->base_mrf, src,
367 BRW_MATH_DATA_VECTOR,
368 BRW_MATH_PRECISION_FULL);
369 }
370
371 void
372 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
373 struct brw_reg sampler_index)
374 {
375 int msg_type = -1;
376 int rlen = 4;
377 uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
378 uint32_t return_format;
379
380 switch (dst.type) {
381 case BRW_REGISTER_TYPE_D:
382 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
383 break;
384 case BRW_REGISTER_TYPE_UD:
385 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
386 break;
387 default:
388 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
389 break;
390 }
391
392 if (dispatch_width == 16 &&
393 !inst->force_uncompressed && !inst->force_sechalf)
394 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
395
396 if (brw->gen >= 5) {
397 switch (inst->opcode) {
398 case SHADER_OPCODE_TEX:
399 if (inst->shadow_compare) {
400 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
401 } else {
402 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
403 }
404 break;
405 case FS_OPCODE_TXB:
406 if (inst->shadow_compare) {
407 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
408 } else {
409 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
410 }
411 break;
412 case SHADER_OPCODE_TXL:
413 if (inst->shadow_compare) {
414 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
415 } else {
416 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
417 }
418 break;
419 case SHADER_OPCODE_TXS:
420 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
421 break;
422 case SHADER_OPCODE_TXD:
423 if (inst->shadow_compare) {
424 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
425 assert(brw->gen >= 8 || brw->is_haswell);
426 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
427 } else {
428 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
429 }
430 break;
431 case SHADER_OPCODE_TXF:
432 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
433 break;
434 case SHADER_OPCODE_TXF_CMS:
435 if (brw->gen >= 7)
436 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
437 else
438 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
439 break;
440 case SHADER_OPCODE_TXF_UMS:
441 assert(brw->gen >= 7);
442 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
443 break;
444 case SHADER_OPCODE_TXF_MCS:
445 assert(brw->gen >= 7);
446 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
447 break;
448 case SHADER_OPCODE_LOD:
449 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
450 break;
451 case SHADER_OPCODE_TG4:
452 if (inst->shadow_compare) {
453 assert(brw->gen >= 7);
454 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
455 } else {
456 assert(brw->gen >= 6);
457 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
458 }
459 break;
460 case SHADER_OPCODE_TG4_OFFSET:
461 assert(brw->gen >= 7);
462 if (inst->shadow_compare) {
463 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
464 } else {
465 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
466 }
467 break;
468 default:
469 unreachable("not reached");
470 }
471 } else {
472 switch (inst->opcode) {
473 case SHADER_OPCODE_TEX:
474 /* Note that G45 and older determines shadow compare and dispatch width
475 * from message length for most messages.
476 */
477 assert(dispatch_width == 8);
478 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
479 if (inst->shadow_compare) {
480 assert(inst->mlen == 6);
481 } else {
482 assert(inst->mlen <= 4);
483 }
484 break;
485 case FS_OPCODE_TXB:
486 if (inst->shadow_compare) {
487 assert(inst->mlen == 6);
488 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
489 } else {
490 assert(inst->mlen == 9);
491 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
492 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
493 }
494 break;
495 case SHADER_OPCODE_TXL:
496 if (inst->shadow_compare) {
497 assert(inst->mlen == 6);
498 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
499 } else {
500 assert(inst->mlen == 9);
501 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
502 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
503 }
504 break;
505 case SHADER_OPCODE_TXD:
506 /* There is no sample_d_c message; comparisons are done manually */
507 assert(inst->mlen == 7 || inst->mlen == 10);
508 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
509 break;
510 case SHADER_OPCODE_TXF:
511 assert(inst->mlen == 9);
512 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
513 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
514 break;
515 case SHADER_OPCODE_TXS:
516 assert(inst->mlen == 3);
517 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
518 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
519 break;
520 default:
521 unreachable("not reached");
522 }
523 }
524 assert(msg_type != -1);
525
526 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
527 rlen = 8;
528 dst = vec16(dst);
529 }
530
531 if (brw->gen >= 7 && inst->header_present && dispatch_width == 16) {
532 /* The send-from-GRF for SIMD16 texturing with a header has an extra
533 * hardware register allocated to it, which we need to skip over (since
534 * our coordinates in the payload are in the even-numbered registers,
535 * and the header comes right before the first one).
536 */
537 assert(src.file == BRW_GENERAL_REGISTER_FILE);
538 src.nr++;
539 }
540
541 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
542
543 /* Load the message header if present. If there's a texture offset,
544 * we need to set it up explicitly and load the offset bitfield.
545 * Otherwise, we can use an implied move from g0 to the first message reg.
546 */
547 if (inst->header_present) {
548 if (brw->gen < 6 && !inst->texture_offset) {
549 /* Set up an implied move from g0 to the MRF. */
550 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
551 } else {
552 struct brw_reg header_reg;
553
554 if (brw->gen >= 7) {
555 header_reg = src;
556 } else {
557 assert(inst->base_mrf != -1);
558 header_reg = brw_message_reg(inst->base_mrf);
559 }
560
561 brw_push_insn_state(p);
562 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
563 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
564 /* Explicitly set up the message header by copying g0 to the MRF. */
565 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
566
567 if (inst->texture_offset) {
568 /* Set the offset bits in DWord 2. */
569 brw_MOV(p, get_element_ud(header_reg, 2),
570 brw_imm_ud(inst->texture_offset));
571 }
572
573 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
574 brw_pop_insn_state(p);
575 }
576 }
577
578 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
579 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
580 ? prog_data->base.binding_table.gather_texture_start
581 : prog_data->base.binding_table.texture_start;
582
583 if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
584 uint32_t sampler = sampler_index.dw1.ud;
585
586 brw_SAMPLE(p,
587 retype(dst, BRW_REGISTER_TYPE_UW),
588 inst->base_mrf,
589 src,
590 sampler + base_binding_table_index,
591 sampler % 16,
592 msg_type,
593 rlen,
594 inst->mlen,
595 inst->header_present,
596 simd_mode,
597 return_format);
598
599 brw_mark_surface_used(&prog_data->base, sampler + base_binding_table_index);
600 } else {
601 /* XXX: Non-const sampler index */
602 }
603 }
604
605
606 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
607 * looking like:
608 *
609 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
610 *
611 * Ideally, we want to produce:
612 *
613 * DDX DDY
614 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
615 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
616 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
617 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
618 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
619 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
620 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
621 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
622 *
623 * and add another set of two more subspans if in 16-pixel dispatch mode.
624 *
625 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
626 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
627 * pair. But the ideal approximation may impose a huge performance cost on
628 * sample_d. On at least Haswell, sample_d instruction does some
629 * optimizations if the same LOD is used for all pixels in the subspan.
630 *
631 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
632 * appropriate swizzling.
633 */
634 void
635 fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
636 struct brw_reg quality)
637 {
638 unsigned vstride, width;
639 assert(quality.file == BRW_IMMEDIATE_VALUE);
640 assert(quality.type == BRW_REGISTER_TYPE_D);
641
642 int quality_value = quality.dw1.d;
643
644 if (quality_value == BRW_DERIVATIVE_FINE ||
645 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
646 /* produce accurate derivatives */
647 vstride = BRW_VERTICAL_STRIDE_2;
648 width = BRW_WIDTH_2;
649 }
650 else {
651 /* replicate the derivative at the top-left pixel to other pixels */
652 vstride = BRW_VERTICAL_STRIDE_4;
653 width = BRW_WIDTH_4;
654 }
655
656 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
657 BRW_REGISTER_TYPE_F,
658 vstride,
659 width,
660 BRW_HORIZONTAL_STRIDE_0,
661 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
662 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
663 BRW_REGISTER_TYPE_F,
664 vstride,
665 width,
666 BRW_HORIZONTAL_STRIDE_0,
667 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
668 brw_ADD(p, dst, src0, negate(src1));
669 }
670
671 /* The negate_value boolean is used to negate the derivative computation for
672 * FBOs, since they place the origin at the upper left instead of the lower
673 * left.
674 */
675 void
676 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
677 struct brw_reg quality, bool negate_value)
678 {
679 assert(quality.file == BRW_IMMEDIATE_VALUE);
680 assert(quality.type == BRW_REGISTER_TYPE_D);
681
682 int quality_value = quality.dw1.d;
683
684 if (quality_value == BRW_DERIVATIVE_FINE ||
685 (key->high_quality_derivatives && quality_value != BRW_DERIVATIVE_COARSE)) {
686 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
687 * Region Restrictions):
688 *
689 * In Align16 access mode, SIMD16 is not allowed for DW operations
690 * and SIMD8 is not allowed for DF operations.
691 *
692 * In this context, "DW operations" means "operations acting on 32-bit
693 * values", so it includes operations on floats.
694 *
695 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
696 * (Instruction Compression -> Rules and Restrictions):
697 *
698 * A compressed instruction must be in Align1 access mode. Align16
699 * mode instructions cannot be compressed.
700 *
701 * Similar text exists in the g45 PRM.
702 *
703 * On these platforms, if we're building a SIMD16 shader, we need to
704 * manually unroll to a pair of SIMD8 instructions.
705 */
706 bool unroll_to_simd8 =
707 (dispatch_width == 16 &&
708 (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
709
710 /* produce accurate derivatives */
711 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
712 BRW_REGISTER_TYPE_F,
713 BRW_VERTICAL_STRIDE_4,
714 BRW_WIDTH_4,
715 BRW_HORIZONTAL_STRIDE_1,
716 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
717 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
718 BRW_REGISTER_TYPE_F,
719 BRW_VERTICAL_STRIDE_4,
720 BRW_WIDTH_4,
721 BRW_HORIZONTAL_STRIDE_1,
722 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
723 brw_push_insn_state(p);
724 brw_set_default_access_mode(p, BRW_ALIGN_16);
725 if (unroll_to_simd8)
726 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
727 if (negate_value)
728 brw_ADD(p, dst, src1, negate(src0));
729 else
730 brw_ADD(p, dst, src0, negate(src1));
731 if (unroll_to_simd8) {
732 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
733 src0 = sechalf(src0);
734 src1 = sechalf(src1);
735 dst = sechalf(dst);
736 if (negate_value)
737 brw_ADD(p, dst, src1, negate(src0));
738 else
739 brw_ADD(p, dst, src0, negate(src1));
740 }
741 brw_pop_insn_state(p);
742 } else {
743 /* replicate the derivative at the top-left pixel to other pixels */
744 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
745 BRW_REGISTER_TYPE_F,
746 BRW_VERTICAL_STRIDE_4,
747 BRW_WIDTH_4,
748 BRW_HORIZONTAL_STRIDE_0,
749 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
750 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
751 BRW_REGISTER_TYPE_F,
752 BRW_VERTICAL_STRIDE_4,
753 BRW_WIDTH_4,
754 BRW_HORIZONTAL_STRIDE_0,
755 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
756 if (negate_value)
757 brw_ADD(p, dst, src1, negate(src0));
758 else
759 brw_ADD(p, dst, src0, negate(src1));
760 }
761 }
762
763 void
764 fs_generator::generate_discard_jump(fs_inst *inst)
765 {
766 assert(brw->gen >= 6);
767
768 /* This HALT will be patched up at FB write time to point UIP at the end of
769 * the program, and at brw_uip_jip() JIP will be set to the end of the
770 * current block (or the program).
771 */
772 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
773
774 brw_push_insn_state(p);
775 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
776 gen6_HALT(p);
777 brw_pop_insn_state(p);
778 }
779
780 void
781 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
782 {
783 assert(inst->mlen != 0);
784
785 brw_MOV(p,
786 retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
787 retype(src, BRW_REGISTER_TYPE_UD));
788 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
789 dispatch_width / 8, inst->offset);
790 }
791
792 void
793 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
794 {
795 assert(inst->mlen != 0);
796
797 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
798 dispatch_width / 8, inst->offset);
799 }
800
801 void
802 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
803 {
804 gen7_block_read_scratch(p, dst, dispatch_width / 8, inst->offset);
805 }
806
807 void
808 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
809 struct brw_reg dst,
810 struct brw_reg index,
811 struct brw_reg offset)
812 {
813 assert(inst->mlen != 0);
814
815 assert(index.file == BRW_IMMEDIATE_VALUE &&
816 index.type == BRW_REGISTER_TYPE_UD);
817 uint32_t surf_index = index.dw1.ud;
818
819 assert(offset.file == BRW_IMMEDIATE_VALUE &&
820 offset.type == BRW_REGISTER_TYPE_UD);
821 uint32_t read_offset = offset.dw1.ud;
822
823 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
824 read_offset, surf_index);
825
826 brw_mark_surface_used(&prog_data->base, surf_index);
827 }
828
829 void
830 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
831 struct brw_reg dst,
832 struct brw_reg index,
833 struct brw_reg offset)
834 {
835 assert(inst->mlen == 0);
836 assert(index.type == BRW_REGISTER_TYPE_UD);
837
838 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
839 /* Reference just the dword we need, to avoid angering validate_reg(). */
840 offset = brw_vec1_grf(offset.nr, 0);
841
842 /* We use the SIMD4x2 mode because we want to end up with 4 components in
843 * the destination loaded consecutively from the same offset (which appears
844 * in the first component, and the rest are ignored).
845 */
846 dst.width = BRW_WIDTH_4;
847
848 if (index.file == BRW_IMMEDIATE_VALUE) {
849
850 uint32_t surf_index = index.dw1.ud;
851
852 brw_push_insn_state(p);
853 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
854 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
855 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
856 brw_pop_insn_state(p);
857
858 brw_set_dest(p, send, dst);
859 brw_set_src0(p, send, offset);
860 brw_set_sampler_message(p, send,
861 surf_index,
862 0, /* LD message ignores sampler unit */
863 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
864 1, /* rlen */
865 1, /* mlen */
866 false, /* no header */
867 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
868 0);
869
870 brw_mark_surface_used(&prog_data->base, surf_index);
871
872 } else {
873
874 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
875
876 brw_push_insn_state(p);
877 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
878 brw_set_default_access_mode(p, BRW_ALIGN_1);
879
880 /* a0.0 = surf_index & 0xff */
881 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
882 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
883 brw_set_dest(p, insn_and, addr);
884 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
885 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
886
887
888 /* a0.0 |= <descriptor> */
889 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
890 brw_set_sampler_message(p, insn_or,
891 0 /* surface */,
892 0 /* sampler */,
893 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
894 1 /* rlen */,
895 1 /* mlen */,
896 false /* header */,
897 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
898 0);
899 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
900 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
901 brw_set_src0(p, insn_or, addr);
902 brw_set_dest(p, insn_or, addr);
903
904
905 /* dst = send(offset, a0.0) */
906 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
907 brw_set_dest(p, insn_send, dst);
908 brw_set_src0(p, insn_send, offset);
909 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
910
911 brw_pop_insn_state(p);
912
913 /* visitor knows more than we do about the surface limit required,
914 * so has already done marking.
915 */
916
917 }
918 }
919
920 void
921 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
922 struct brw_reg dst,
923 struct brw_reg index,
924 struct brw_reg offset)
925 {
926 assert(brw->gen < 7); /* Should use the gen7 variant. */
927 assert(inst->header_present);
928 assert(inst->mlen);
929
930 assert(index.file == BRW_IMMEDIATE_VALUE &&
931 index.type == BRW_REGISTER_TYPE_UD);
932 uint32_t surf_index = index.dw1.ud;
933
934 uint32_t simd_mode, rlen, msg_type;
935 if (dispatch_width == 16) {
936 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
937 rlen = 8;
938 } else {
939 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
940 rlen = 4;
941 }
942
943 if (brw->gen >= 5)
944 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
945 else {
946 /* We always use the SIMD16 message so that we only have to load U, and
947 * not V or R.
948 */
949 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
950 assert(inst->mlen == 3);
951 assert(inst->regs_written == 8);
952 rlen = 8;
953 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
954 }
955
956 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
957 BRW_REGISTER_TYPE_D);
958 brw_MOV(p, offset_mrf, offset);
959
960 struct brw_reg header = brw_vec8_grf(0, 0);
961 gen6_resolve_implied_move(p, &header, inst->base_mrf);
962
963 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
964 brw_inst_set_qtr_control(brw, send, BRW_COMPRESSION_NONE);
965 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
966 brw_set_src0(p, send, header);
967 if (brw->gen < 6)
968 brw_inst_set_base_mrf(brw, send, inst->base_mrf);
969
970 /* Our surface is set up as floats, regardless of what actual data is
971 * stored in it.
972 */
973 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
974 brw_set_sampler_message(p, send,
975 surf_index,
976 0, /* sampler (unused) */
977 msg_type,
978 rlen,
979 inst->mlen,
980 inst->header_present,
981 simd_mode,
982 return_format);
983
984 brw_mark_surface_used(&prog_data->base, surf_index);
985 }
986
987 void
988 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
989 struct brw_reg dst,
990 struct brw_reg index,
991 struct brw_reg offset)
992 {
993 assert(brw->gen >= 7);
994 /* Varying-offset pull constant loads are treated as a normal expression on
995 * gen7, so the fact that it's a send message is hidden at the IR level.
996 */
997 assert(!inst->header_present);
998 assert(!inst->mlen);
999 assert(index.type == BRW_REGISTER_TYPE_UD);
1000
1001 uint32_t simd_mode, rlen, mlen;
1002 if (dispatch_width == 16) {
1003 mlen = 2;
1004 rlen = 8;
1005 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1006 } else {
1007 mlen = 1;
1008 rlen = 4;
1009 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1010 }
1011
1012 if (index.file == BRW_IMMEDIATE_VALUE) {
1013
1014 uint32_t surf_index = index.dw1.ud;
1015
1016 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1017 brw_set_dest(p, send, dst);
1018 brw_set_src0(p, send, offset);
1019 brw_set_sampler_message(p, send,
1020 surf_index,
1021 0, /* LD message ignores sampler unit */
1022 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1023 rlen,
1024 mlen,
1025 false, /* no header */
1026 simd_mode,
1027 0);
1028
1029 brw_mark_surface_used(&prog_data->base, surf_index);
1030
1031 } else {
1032
1033 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1034
1035 brw_push_insn_state(p);
1036 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1037 brw_set_default_access_mode(p, BRW_ALIGN_1);
1038
1039 /* a0.0 = surf_index & 0xff */
1040 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1041 brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
1042 brw_set_dest(p, insn_and, addr);
1043 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1044 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1045
1046
1047 /* a0.0 |= <descriptor> */
1048 brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
1049 brw_set_sampler_message(p, insn_or,
1050 0 /* surface */,
1051 0 /* sampler */,
1052 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1053 rlen /* rlen */,
1054 mlen /* mlen */,
1055 false /* header */,
1056 simd_mode,
1057 0);
1058 brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
1059 brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
1060 brw_set_src0(p, insn_or, addr);
1061 brw_set_dest(p, insn_or, addr);
1062
1063
1064 /* dst = send(offset, a0.0) */
1065 brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
1066 brw_set_dest(p, insn_send, dst);
1067 brw_set_src0(p, insn_send, offset);
1068 brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
1069
1070 brw_pop_insn_state(p);
1071
1072 /* visitor knows more than we do about the surface limit required,
1073 * so has already done marking.
1074 */
1075 }
1076 }
1077
1078 /**
1079 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1080 * into the flags register (f0.0).
1081 *
1082 * Used only on Gen6 and above.
1083 */
1084 void
1085 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1086 {
1087 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1088 struct brw_reg dispatch_mask;
1089
1090 if (brw->gen >= 6)
1091 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1092 else
1093 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1094
1095 brw_push_insn_state(p);
1096 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1097 brw_MOV(p, flags, dispatch_mask);
1098 brw_pop_insn_state(p);
1099 }
1100
1101 void
1102 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1103 struct brw_reg dst,
1104 struct brw_reg src,
1105 struct brw_reg msg_data,
1106 unsigned msg_type)
1107 {
1108 assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
1109 msg_data.type == BRW_REGISTER_TYPE_UD);
1110
1111 brw_pixel_interpolator_query(p,
1112 retype(dst, BRW_REGISTER_TYPE_UW),
1113 src,
1114 inst->pi_noperspective,
1115 msg_type,
1116 msg_data.dw1.ud,
1117 inst->mlen,
1118 inst->regs_written);
1119 }
1120
1121
1122 static uint32_t brw_file_from_reg(fs_reg *reg)
1123 {
1124 switch (reg->file) {
1125 case GRF:
1126 return BRW_GENERAL_REGISTER_FILE;
1127 case MRF:
1128 return BRW_MESSAGE_REGISTER_FILE;
1129 case IMM:
1130 return BRW_IMMEDIATE_VALUE;
1131 default:
1132 unreachable("not reached");
1133 }
1134 }
1135
1136 struct brw_reg
1137 brw_reg_from_fs_reg(fs_reg *reg)
1138 {
1139 struct brw_reg brw_reg;
1140
1141 switch (reg->file) {
1142 case GRF:
1143 case MRF:
1144 if (reg->stride == 0) {
1145 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->reg, 0);
1146 } else {
1147 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->reg, 0);
1148 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
1149 }
1150
1151 brw_reg = retype(brw_reg, reg->type);
1152 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
1153 break;
1154 case IMM:
1155 switch (reg->type) {
1156 case BRW_REGISTER_TYPE_F:
1157 brw_reg = brw_imm_f(reg->fixed_hw_reg.dw1.f);
1158 break;
1159 case BRW_REGISTER_TYPE_D:
1160 brw_reg = brw_imm_d(reg->fixed_hw_reg.dw1.d);
1161 break;
1162 case BRW_REGISTER_TYPE_UD:
1163 brw_reg = brw_imm_ud(reg->fixed_hw_reg.dw1.ud);
1164 break;
1165 default:
1166 unreachable("not reached");
1167 }
1168 break;
1169 case HW_REG:
1170 assert(reg->type == reg->fixed_hw_reg.type);
1171 brw_reg = reg->fixed_hw_reg;
1172 break;
1173 case BAD_FILE:
1174 /* Probably unused. */
1175 brw_reg = brw_null_reg();
1176 break;
1177 case UNIFORM:
1178 unreachable("not reached");
1179 default:
1180 unreachable("not reached");
1181 }
1182 if (reg->abs)
1183 brw_reg = brw_abs(brw_reg);
1184 if (reg->negate)
1185 brw_reg = negate(brw_reg);
1186
1187 return brw_reg;
1188 }
1189
1190 /**
1191 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1192 * sampler LD messages.
1193 *
1194 * We don't want to bake it into the send message's code generation because
1195 * that means we don't get a chance to schedule the instructions.
1196 */
1197 void
1198 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1199 struct brw_reg dst,
1200 struct brw_reg value)
1201 {
1202 assert(value.file == BRW_IMMEDIATE_VALUE);
1203
1204 brw_push_insn_state(p);
1205 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1206 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1207 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1208 brw_pop_insn_state(p);
1209 }
1210
1211 /* Sets vstride=16, width=8, hstride=2 or vstride=0, width=1, hstride=0
1212 * (when mask is passed as a uniform) of register mask before moving it
1213 * to register dst.
1214 */
1215 void
1216 fs_generator::generate_set_omask(fs_inst *inst,
1217 struct brw_reg dst,
1218 struct brw_reg mask)
1219 {
1220 bool stride_8_8_1 =
1221 (mask.vstride == BRW_VERTICAL_STRIDE_8 &&
1222 mask.width == BRW_WIDTH_8 &&
1223 mask.hstride == BRW_HORIZONTAL_STRIDE_1);
1224
1225 bool stride_0_1_0 =
1226 (mask.vstride == BRW_VERTICAL_STRIDE_0 &&
1227 mask.width == BRW_WIDTH_1 &&
1228 mask.hstride == BRW_HORIZONTAL_STRIDE_0);
1229
1230 assert(stride_8_8_1 || stride_0_1_0);
1231 assert(dst.type == BRW_REGISTER_TYPE_UW);
1232
1233 if (dispatch_width == 16)
1234 dst = vec16(dst);
1235 brw_push_insn_state(p);
1236 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1237 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1238
1239 if (stride_8_8_1) {
1240 brw_MOV(p, dst, retype(stride(mask, 16, 8, 2), dst.type));
1241 } else if (stride_0_1_0) {
1242 brw_MOV(p, dst, retype(mask, dst.type));
1243 }
1244 brw_pop_insn_state(p);
1245 }
1246
1247 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1248 * the ADD instruction.
1249 */
1250 void
1251 fs_generator::generate_set_sample_id(fs_inst *inst,
1252 struct brw_reg dst,
1253 struct brw_reg src0,
1254 struct brw_reg src1)
1255 {
1256 assert(dst.type == BRW_REGISTER_TYPE_D ||
1257 dst.type == BRW_REGISTER_TYPE_UD);
1258 assert(src0.type == BRW_REGISTER_TYPE_D ||
1259 src0.type == BRW_REGISTER_TYPE_UD);
1260
1261 brw_push_insn_state(p);
1262 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1263 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1264 struct brw_reg reg = retype(stride(src1, 1, 4, 0), BRW_REGISTER_TYPE_UW);
1265 brw_ADD(p, dst, src0, reg);
1266 if (dispatch_width == 16)
1267 brw_ADD(p, offset(dst, 1), offset(src0, 1), suboffset(reg, 2));
1268 brw_pop_insn_state(p);
1269 }
1270
1271 /**
1272 * Change the register's data type from UD to W, doubling the strides in order
1273 * to compensate for halving the data type width.
1274 */
1275 static struct brw_reg
1276 ud_reg_to_w(struct brw_reg r)
1277 {
1278 assert(r.type == BRW_REGISTER_TYPE_UD);
1279 r.type = BRW_REGISTER_TYPE_W;
1280
1281 /* The BRW_*_STRIDE enums are defined so that incrementing the field
1282 * doubles the real stride.
1283 */
1284 if (r.hstride != 0)
1285 ++r.hstride;
1286 if (r.vstride != 0)
1287 ++r.vstride;
1288
1289 return r;
1290 }
1291
1292 void
1293 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1294 struct brw_reg dst,
1295 struct brw_reg x,
1296 struct brw_reg y)
1297 {
1298 assert(brw->gen >= 7);
1299 assert(dst.type == BRW_REGISTER_TYPE_UD);
1300 assert(x.type == BRW_REGISTER_TYPE_F);
1301 assert(y.type == BRW_REGISTER_TYPE_F);
1302
1303 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1304 *
1305 * Because this instruction does not have a 16-bit floating-point type,
1306 * the destination data type must be Word (W).
1307 *
1308 * The destination must be DWord-aligned and specify a horizontal stride
1309 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1310 * each destination channel and the upper word is not modified.
1311 */
1312 struct brw_reg dst_w = ud_reg_to_w(dst);
1313
1314 /* Give each 32-bit channel of dst the form below , where "." means
1315 * unchanged.
1316 * 0x....hhhh
1317 */
1318 brw_F32TO16(p, dst_w, y);
1319
1320 /* Now the form:
1321 * 0xhhhh0000
1322 */
1323 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1324
1325 /* And, finally the form of packHalf2x16's output:
1326 * 0xhhhhllll
1327 */
1328 brw_F32TO16(p, dst_w, x);
1329 }
1330
1331 void
1332 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1333 struct brw_reg dst,
1334 struct brw_reg src)
1335 {
1336 assert(brw->gen >= 7);
1337 assert(dst.type == BRW_REGISTER_TYPE_F);
1338 assert(src.type == BRW_REGISTER_TYPE_UD);
1339
1340 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1341 *
1342 * Because this instruction does not have a 16-bit floating-point type,
1343 * the source data type must be Word (W). The destination type must be
1344 * F (Float).
1345 */
1346 struct brw_reg src_w = ud_reg_to_w(src);
1347
1348 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1349 * For the Y case, we wish to access only the upper word; therefore
1350 * a 16-bit subregister offset is needed.
1351 */
1352 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1353 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1354 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1355 src_w.subnr += 2;
1356
1357 brw_F16TO32(p, dst, src_w);
1358 }
1359
1360 void
1361 fs_generator::generate_shader_time_add(fs_inst *inst,
1362 struct brw_reg payload,
1363 struct brw_reg offset,
1364 struct brw_reg value)
1365 {
1366 assert(brw->gen >= 7);
1367 brw_push_insn_state(p);
1368 brw_set_default_mask_control(p, true);
1369
1370 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1371 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1372 offset.type);
1373 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1374 value.type);
1375
1376 assert(offset.file == BRW_IMMEDIATE_VALUE);
1377 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1378 value.width = BRW_WIDTH_1;
1379 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1380 value.vstride = BRW_VERTICAL_STRIDE_0;
1381 } else {
1382 assert(value.file == BRW_IMMEDIATE_VALUE);
1383 }
1384
1385 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1386 * case, and we don't really care about squeezing every bit of performance
1387 * out of this path, so we just emit the MOVs from here.
1388 */
1389 brw_MOV(p, payload_offset, offset);
1390 brw_MOV(p, payload_value, value);
1391 brw_shader_time_add(p, payload,
1392 prog_data->base.binding_table.shader_time_start);
1393 brw_pop_insn_state(p);
1394
1395 brw_mark_surface_used(&prog_data->base,
1396 prog_data->base.binding_table.shader_time_start);
1397 }
1398
1399 void
1400 fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
1401 struct brw_reg atomic_op,
1402 struct brw_reg surf_index)
1403 {
1404 assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
1405 atomic_op.type == BRW_REGISTER_TYPE_UD &&
1406 surf_index.file == BRW_IMMEDIATE_VALUE &&
1407 surf_index.type == BRW_REGISTER_TYPE_UD);
1408
1409 brw_untyped_atomic(p, dst, brw_message_reg(inst->base_mrf),
1410 atomic_op.dw1.ud, surf_index.dw1.ud,
1411 inst->mlen, dispatch_width / 8);
1412
1413 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1414 }
1415
1416 void
1417 fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
1418 struct brw_reg surf_index)
1419 {
1420 assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
1421 surf_index.type == BRW_REGISTER_TYPE_UD);
1422
1423 brw_untyped_surface_read(p, dst, brw_message_reg(inst->base_mrf),
1424 surf_index.dw1.ud,
1425 inst->mlen, dispatch_width / 8);
1426
1427 brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
1428 }
1429
1430 void
1431 fs_generator::generate_code(exec_list *instructions)
1432 {
1433 int start_offset = p->next_insn_offset;
1434
1435 struct annotation_info annotation;
1436 memset(&annotation, 0, sizeof(annotation));
1437
1438 cfg_t *cfg = NULL;
1439 if (unlikely(debug_flag))
1440 cfg = new(mem_ctx) cfg_t(instructions);
1441
1442 foreach_in_list(fs_inst, inst, instructions) {
1443 struct brw_reg src[3], dst;
1444 unsigned int last_insn_offset = p->next_insn_offset;
1445
1446 if (unlikely(debug_flag))
1447 annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
1448
1449 for (unsigned int i = 0; i < inst->sources; i++) {
1450 src[i] = brw_reg_from_fs_reg(&inst->src[i]);
1451
1452 /* The accumulator result appears to get used for the
1453 * conditional modifier generation. When negating a UD
1454 * value, there is a 33rd bit generated for the sign in the
1455 * accumulator value, so now you can't check, for example,
1456 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1457 */
1458 assert(!inst->conditional_mod ||
1459 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1460 !inst->src[i].negate);
1461 }
1462 dst = brw_reg_from_fs_reg(&inst->dst);
1463
1464 brw_set_default_predicate_control(p, inst->predicate);
1465 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1466 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1467 brw_set_default_saturate(p, inst->saturate);
1468 brw_set_default_mask_control(p, inst->force_writemask_all);
1469 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1470
1471 if (inst->force_uncompressed || dispatch_width == 8) {
1472 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1473 } else if (inst->force_sechalf) {
1474 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1475 } else {
1476 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1477 }
1478
1479 switch (inst->opcode) {
1480 case BRW_OPCODE_MOV:
1481 brw_MOV(p, dst, src[0]);
1482 break;
1483 case BRW_OPCODE_ADD:
1484 brw_ADD(p, dst, src[0], src[1]);
1485 break;
1486 case BRW_OPCODE_MUL:
1487 brw_MUL(p, dst, src[0], src[1]);
1488 break;
1489 case BRW_OPCODE_AVG:
1490 brw_AVG(p, dst, src[0], src[1]);
1491 break;
1492 case BRW_OPCODE_MACH:
1493 brw_MACH(p, dst, src[0], src[1]);
1494 break;
1495
1496 case BRW_OPCODE_MAD:
1497 assert(brw->gen >= 6);
1498 brw_set_default_access_mode(p, BRW_ALIGN_16);
1499 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1500 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1501 brw_MAD(p, dst, src[0], src[1], src[2]);
1502 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1503 brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1504 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1505 } else {
1506 brw_MAD(p, dst, src[0], src[1], src[2]);
1507 }
1508 brw_set_default_access_mode(p, BRW_ALIGN_1);
1509 break;
1510
1511 case BRW_OPCODE_LRP:
1512 assert(brw->gen >= 6);
1513 brw_set_default_access_mode(p, BRW_ALIGN_16);
1514 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1515 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1516 brw_LRP(p, dst, src[0], src[1], src[2]);
1517 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1518 brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1519 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1520 } else {
1521 brw_LRP(p, dst, src[0], src[1], src[2]);
1522 }
1523 brw_set_default_access_mode(p, BRW_ALIGN_1);
1524 break;
1525
1526 case BRW_OPCODE_FRC:
1527 brw_FRC(p, dst, src[0]);
1528 break;
1529 case BRW_OPCODE_RNDD:
1530 brw_RNDD(p, dst, src[0]);
1531 break;
1532 case BRW_OPCODE_RNDE:
1533 brw_RNDE(p, dst, src[0]);
1534 break;
1535 case BRW_OPCODE_RNDZ:
1536 brw_RNDZ(p, dst, src[0]);
1537 break;
1538
1539 case BRW_OPCODE_AND:
1540 brw_AND(p, dst, src[0], src[1]);
1541 break;
1542 case BRW_OPCODE_OR:
1543 brw_OR(p, dst, src[0], src[1]);
1544 break;
1545 case BRW_OPCODE_XOR:
1546 brw_XOR(p, dst, src[0], src[1]);
1547 break;
1548 case BRW_OPCODE_NOT:
1549 brw_NOT(p, dst, src[0]);
1550 break;
1551 case BRW_OPCODE_ASR:
1552 brw_ASR(p, dst, src[0], src[1]);
1553 break;
1554 case BRW_OPCODE_SHR:
1555 brw_SHR(p, dst, src[0], src[1]);
1556 break;
1557 case BRW_OPCODE_SHL:
1558 brw_SHL(p, dst, src[0], src[1]);
1559 break;
1560 case BRW_OPCODE_F32TO16:
1561 assert(brw->gen >= 7);
1562 brw_F32TO16(p, dst, src[0]);
1563 break;
1564 case BRW_OPCODE_F16TO32:
1565 assert(brw->gen >= 7);
1566 brw_F16TO32(p, dst, src[0]);
1567 break;
1568 case BRW_OPCODE_CMP:
1569 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1570 break;
1571 case BRW_OPCODE_SEL:
1572 brw_SEL(p, dst, src[0], src[1]);
1573 break;
1574 case BRW_OPCODE_BFREV:
1575 assert(brw->gen >= 7);
1576 /* BFREV only supports UD type for src and dst. */
1577 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1578 retype(src[0], BRW_REGISTER_TYPE_UD));
1579 break;
1580 case BRW_OPCODE_FBH:
1581 assert(brw->gen >= 7);
1582 /* FBH only supports UD type for dst. */
1583 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1584 break;
1585 case BRW_OPCODE_FBL:
1586 assert(brw->gen >= 7);
1587 /* FBL only supports UD type for dst. */
1588 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1589 break;
1590 case BRW_OPCODE_CBIT:
1591 assert(brw->gen >= 7);
1592 /* CBIT only supports UD type for dst. */
1593 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1594 break;
1595 case BRW_OPCODE_ADDC:
1596 assert(brw->gen >= 7);
1597 brw_ADDC(p, dst, src[0], src[1]);
1598 break;
1599 case BRW_OPCODE_SUBB:
1600 assert(brw->gen >= 7);
1601 brw_SUBB(p, dst, src[0], src[1]);
1602 break;
1603 case BRW_OPCODE_MAC:
1604 brw_MAC(p, dst, src[0], src[1]);
1605 break;
1606
1607 case BRW_OPCODE_BFE:
1608 assert(brw->gen >= 7);
1609 brw_set_default_access_mode(p, BRW_ALIGN_16);
1610 if (dispatch_width == 16 && brw->gen < 8 && !brw->is_haswell) {
1611 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1612 brw_BFE(p, dst, src[0], src[1], src[2]);
1613 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1614 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1615 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1616 } else {
1617 brw_BFE(p, dst, src[0], src[1], src[2]);
1618 }
1619 brw_set_default_access_mode(p, BRW_ALIGN_1);
1620 break;
1621
1622 case BRW_OPCODE_BFI1:
1623 assert(brw->gen >= 7);
1624 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1625 * should
1626 *
1627 * "Force BFI instructions to be executed always in SIMD8."
1628 */
1629 if (dispatch_width == 16 && brw->is_haswell) {
1630 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1631 brw_BFI1(p, dst, src[0], src[1]);
1632 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1633 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1634 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1635 } else {
1636 brw_BFI1(p, dst, src[0], src[1]);
1637 }
1638 break;
1639 case BRW_OPCODE_BFI2:
1640 assert(brw->gen >= 7);
1641 brw_set_default_access_mode(p, BRW_ALIGN_16);
1642 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1643 * should
1644 *
1645 * "Force BFI instructions to be executed always in SIMD8."
1646 *
1647 * Otherwise we would be able to emit compressed instructions like we
1648 * do for the other three-source instructions.
1649 */
1650 if (dispatch_width == 16) {
1651 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1652 brw_BFI2(p, dst, src[0], src[1], src[2]);
1653 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1654 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1655 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1656 } else {
1657 brw_BFI2(p, dst, src[0], src[1], src[2]);
1658 }
1659 brw_set_default_access_mode(p, BRW_ALIGN_1);
1660 break;
1661
1662 case BRW_OPCODE_IF:
1663 if (inst->src[0].file != BAD_FILE) {
1664 /* The instruction has an embedded compare (only allowed on gen6) */
1665 assert(brw->gen == 6);
1666 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1667 } else {
1668 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1669 }
1670 break;
1671
1672 case BRW_OPCODE_ELSE:
1673 brw_ELSE(p);
1674 break;
1675 case BRW_OPCODE_ENDIF:
1676 brw_ENDIF(p);
1677 break;
1678
1679 case BRW_OPCODE_DO:
1680 brw_DO(p, BRW_EXECUTE_8);
1681 break;
1682
1683 case BRW_OPCODE_BREAK:
1684 brw_BREAK(p);
1685 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1686 break;
1687 case BRW_OPCODE_CONTINUE:
1688 brw_CONT(p);
1689 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1690 break;
1691
1692 case BRW_OPCODE_WHILE:
1693 brw_WHILE(p);
1694 break;
1695
1696 case SHADER_OPCODE_RCP:
1697 case SHADER_OPCODE_RSQ:
1698 case SHADER_OPCODE_SQRT:
1699 case SHADER_OPCODE_EXP2:
1700 case SHADER_OPCODE_LOG2:
1701 case SHADER_OPCODE_SIN:
1702 case SHADER_OPCODE_COS:
1703 assert(brw->gen < 6 || inst->mlen == 0);
1704 if (brw->gen >= 7) {
1705 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
1706 brw_null_reg());
1707 } else if (brw->gen == 6) {
1708 generate_math_gen6(inst, dst, src[0], brw_null_reg());
1709 } else if (brw->gen == 5 || brw->is_g4x) {
1710 generate_math_g45(inst, dst, src[0]);
1711 } else {
1712 generate_math_gen4(inst, dst, src[0]);
1713 }
1714 break;
1715 case SHADER_OPCODE_INT_QUOTIENT:
1716 case SHADER_OPCODE_INT_REMAINDER:
1717 case SHADER_OPCODE_POW:
1718 assert(brw->gen < 6 || inst->mlen == 0);
1719 if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
1720 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
1721 } else if (brw->gen >= 6) {
1722 generate_math_gen6(inst, dst, src[0], src[1]);
1723 } else {
1724 generate_math_gen4(inst, dst, src[0]);
1725 }
1726 break;
1727 case FS_OPCODE_PIXEL_X:
1728 generate_pixel_xy(dst, true);
1729 break;
1730 case FS_OPCODE_PIXEL_Y:
1731 generate_pixel_xy(dst, false);
1732 break;
1733 case FS_OPCODE_CINTERP:
1734 brw_MOV(p, dst, src[0]);
1735 break;
1736 case FS_OPCODE_LINTERP:
1737 generate_linterp(inst, dst, src);
1738 break;
1739 case SHADER_OPCODE_TEX:
1740 case FS_OPCODE_TXB:
1741 case SHADER_OPCODE_TXD:
1742 case SHADER_OPCODE_TXF:
1743 case SHADER_OPCODE_TXF_CMS:
1744 case SHADER_OPCODE_TXF_UMS:
1745 case SHADER_OPCODE_TXF_MCS:
1746 case SHADER_OPCODE_TXL:
1747 case SHADER_OPCODE_TXS:
1748 case SHADER_OPCODE_LOD:
1749 case SHADER_OPCODE_TG4:
1750 case SHADER_OPCODE_TG4_OFFSET:
1751 generate_tex(inst, dst, src[0], src[1]);
1752 break;
1753 case FS_OPCODE_DDX:
1754 generate_ddx(inst, dst, src[0], src[1]);
1755 break;
1756 case FS_OPCODE_DDY:
1757 /* Make sure fp->UsesDFdy flag got set (otherwise there's no
1758 * guarantee that key->render_to_fbo is set).
1759 */
1760 assert(fp->UsesDFdy);
1761 generate_ddy(inst, dst, src[0], src[1], key->render_to_fbo);
1762 break;
1763
1764 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
1765 generate_scratch_write(inst, src[0]);
1766 break;
1767
1768 case SHADER_OPCODE_GEN4_SCRATCH_READ:
1769 generate_scratch_read(inst, dst);
1770 break;
1771
1772 case SHADER_OPCODE_GEN7_SCRATCH_READ:
1773 generate_scratch_read_gen7(inst, dst);
1774 break;
1775
1776 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
1777 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
1778 break;
1779
1780 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
1781 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1782 break;
1783
1784 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
1785 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
1786 break;
1787
1788 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
1789 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
1790 break;
1791
1792 case FS_OPCODE_FB_WRITE:
1793 generate_fb_write(inst);
1794 break;
1795
1796 case FS_OPCODE_BLORP_FB_WRITE:
1797 generate_blorp_fb_write(inst);
1798 break;
1799
1800 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
1801 generate_mov_dispatch_to_flags(inst);
1802 break;
1803
1804 case FS_OPCODE_DISCARD_JUMP:
1805 generate_discard_jump(inst);
1806 break;
1807
1808 case SHADER_OPCODE_SHADER_TIME_ADD:
1809 generate_shader_time_add(inst, src[0], src[1], src[2]);
1810 break;
1811
1812 case SHADER_OPCODE_UNTYPED_ATOMIC:
1813 generate_untyped_atomic(inst, dst, src[0], src[1]);
1814 break;
1815
1816 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
1817 generate_untyped_surface_read(inst, dst, src[0]);
1818 break;
1819
1820 case FS_OPCODE_SET_SIMD4X2_OFFSET:
1821 generate_set_simd4x2_offset(inst, dst, src[0]);
1822 break;
1823
1824 case FS_OPCODE_SET_OMASK:
1825 generate_set_omask(inst, dst, src[0]);
1826 break;
1827
1828 case FS_OPCODE_SET_SAMPLE_ID:
1829 generate_set_sample_id(inst, dst, src[0], src[1]);
1830 break;
1831
1832 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
1833 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
1834 break;
1835
1836 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
1837 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
1838 generate_unpack_half_2x16_split(inst, dst, src[0]);
1839 break;
1840
1841 case FS_OPCODE_PLACEHOLDER_HALT:
1842 /* This is the place where the final HALT needs to be inserted if
1843 * we've emitted any discards. If not, this will emit no code.
1844 */
1845 if (!patch_discard_jumps_to_fb_writes()) {
1846 if (unlikely(debug_flag)) {
1847 annotation.ann_count--;
1848 }
1849 }
1850 break;
1851
1852 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
1853 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1854 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
1855 break;
1856
1857 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
1858 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1859 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
1860 break;
1861
1862 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
1863 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1864 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
1865 break;
1866
1867 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
1868 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
1869 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
1870 break;
1871
1872 default:
1873 if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
1874 _mesa_problem(ctx, "Unsupported opcode `%s' in FS",
1875 opcode_descs[inst->opcode].name);
1876 } else {
1877 _mesa_problem(ctx, "Unsupported opcode %d in FS", inst->opcode);
1878 }
1879 abort();
1880
1881 case SHADER_OPCODE_LOAD_PAYLOAD:
1882 unreachable("Should be lowered by lower_load_payload()");
1883 }
1884
1885 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
1886 assert(p->next_insn_offset == last_insn_offset + 16 ||
1887 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
1888 "emitting more than 1 instruction");
1889
1890 brw_inst *last = &p->store[last_insn_offset / 16];
1891
1892 brw_inst_set_cond_modifier(brw, last, inst->conditional_mod);
1893 brw_inst_set_no_dd_clear(brw, last, inst->no_dd_clear);
1894 brw_inst_set_no_dd_check(brw, last, inst->no_dd_check);
1895 }
1896 }
1897
1898 brw_set_uip_jip(p);
1899 annotation_finalize(&annotation, p->next_insn_offset);
1900
1901 int before_size = p->next_insn_offset - start_offset;
1902 brw_compact_instructions(p, start_offset, annotation.ann_count,
1903 annotation.ann);
1904 int after_size = p->next_insn_offset - start_offset;
1905
1906 if (unlikely(debug_flag)) {
1907 if (prog) {
1908 fprintf(stderr,
1909 "Native code for %s fragment shader %d (SIMD%d dispatch):\n",
1910 prog->Label ? prog->Label : "unnamed",
1911 prog->Name, dispatch_width);
1912 } else if (fp) {
1913 fprintf(stderr,
1914 "Native code for fragment program %d (SIMD%d dispatch):\n",
1915 fp->Base.Id, dispatch_width);
1916 } else {
1917 fprintf(stderr, "Native code for blorp program (SIMD%d dispatch):\n",
1918 dispatch_width);
1919 }
1920 fprintf(stderr, "SIMD%d shader: %d instructions. Compacted %d to %d"
1921 " bytes (%.0f%%)\n",
1922 dispatch_width, before_size / 16, before_size, after_size,
1923 100.0f * (before_size - after_size) / before_size);
1924
1925 const struct gl_program *prog = fp ? &fp->Base : NULL;
1926
1927 dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
1928 ralloc_free(annotation.ann);
1929 }
1930 }
1931
1932 const unsigned *
1933 fs_generator::generate_assembly(exec_list *simd8_instructions,
1934 exec_list *simd16_instructions,
1935 unsigned *assembly_size)
1936 {
1937 assert(simd8_instructions || simd16_instructions);
1938
1939 if (simd8_instructions) {
1940 dispatch_width = 8;
1941 generate_code(simd8_instructions);
1942 }
1943
1944 if (simd16_instructions) {
1945 /* align to 64 byte boundary. */
1946 while (p->next_insn_offset % 64) {
1947 brw_NOP(p);
1948 }
1949
1950 /* Save off the start of this SIMD16 program */
1951 prog_data->prog_offset_16 = p->next_insn_offset;
1952
1953 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1954
1955 dispatch_width = 16;
1956 generate_code(simd16_instructions);
1957 }
1958
1959 return brw_get_program(p, assembly_size);
1960 }