projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
i965/fs: Remove handcrafted math SIMD lowering from the generator.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(const struct brw_codegen *p,
58 fs_inst *inst, fs_reg *reg, unsigned gen)
59 {
60 struct brw_reg brw_reg;
61
62 switch (reg->file) {
63 case MRF:
64 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
65 /* Fallthrough */
66 case VGRF:
67 if (reg->stride == 0) {
68 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
69 } else if (!p->compressed &&
70 inst->exec_size * reg->stride * type_sz(reg->type) <= 32) {
71 brw_reg = brw_vecn_reg(inst->exec_size, brw_file_from_reg(reg),
72 reg->nr, 0);
73 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
74 inst->exec_size, reg->stride);
75 } else {
76 /* From the Haswell PRM:
77 *
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
80 * boundaries.
81 *
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
84 */
85 assert(inst->exec_size / 2 * reg->stride * type_sz(reg->type) <= 32);
86 brw_reg = brw_vecn_reg(inst->exec_size / 2, brw_file_from_reg(reg),
87 reg->nr, 0);
88 brw_reg = stride(brw_reg, inst->exec_size / 2 * reg->stride,
89 inst->exec_size / 2, reg->stride);
90 }
91
92 brw_reg = retype(brw_reg, reg->type);
93 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
94 brw_reg.abs = reg->abs;
95 brw_reg.negate = reg->negate;
96 break;
97 case ARF:
98 case FIXED_GRF:
99 case IMM:
100 brw_reg = reg->as_brw_reg();
101 break;
102 case BAD_FILE:
103 /* Probably unused. */
104 brw_reg = brw_null_reg();
105 break;
106 case ATTR:
107 case UNIFORM:
108 unreachable("not reached");
109 }
110
111 return brw_reg;
112 }
113
114 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
115 void *mem_ctx,
116 const void *key,
117 struct brw_stage_prog_data *prog_data,
118 unsigned promoted_constants,
119 bool runtime_check_aads_emit,
120 gl_shader_stage stage)
121
122 : compiler(compiler), log_data(log_data),
123 devinfo(compiler->devinfo), key(key),
124 prog_data(prog_data),
125 promoted_constants(promoted_constants),
126 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
127 stage(stage), mem_ctx(mem_ctx)
128 {
129 p = rzalloc(mem_ctx, struct brw_codegen);
130 brw_init_codegen(devinfo, p, mem_ctx);
131 }
132
133 fs_generator::~fs_generator()
134 {
135 }
136
137 class ip_record : public exec_node {
138 public:
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
140
141 ip_record(int ip)
142 {
143 this->ip = ip;
144 }
145
146 int ip;
147 };
148
149 bool
150 fs_generator::patch_discard_jumps_to_fb_writes()
151 {
152 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
153 return false;
154
155 int scale = brw_jump_scale(p->devinfo);
156
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
163 *
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
166 * tests.
167 */
168 brw_inst *last_halt = gen6_HALT(p);
169 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
170 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
171
172 int ip = p->nr_insn;
173
174 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
175 brw_inst *patch = &p->store[patch_ip->ip];
176
177 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
180 }
181
182 this->discard_halt_patches.make_empty();
183 return true;
184 }
185
186 void
187 fs_generator::fire_fb_write(fs_inst *inst,
188 struct brw_reg payload,
189 struct brw_reg implied_header,
190 GLuint nr)
191 {
192 uint32_t msg_control;
193
194 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
195
196 if (devinfo->gen < 6) {
197 brw_push_insn_state(p);
198 brw_set_default_exec_size(p, BRW_EXECUTE_8);
199 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
200 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
201 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
202 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p);
204 }
205
206 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
207 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
208 else if (prog_data->dual_src_blend) {
209 if (!inst->force_sechalf)
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
211 else
212 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
213 } else if (inst->exec_size == 16)
214 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
215 else
216 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
217
218 uint32_t surf_index =
219 prog_data->binding_table.render_target_start + inst->target;
220
221 bool last_render_target = inst->eot ||
222 (prog_data->dual_src_blend && dispatch_width == 16);
223
224
225 brw_fb_WRITE(p,
226 dispatch_width,
227 payload,
228 implied_header,
229 msg_control,
230 surf_index,
231 nr,
232 0,
233 inst->eot,
234 last_render_target,
235 inst->header_size != 0);
236
237 brw_mark_surface_used(&prog_data->base, surf_index);
238 }
239
240 void
241 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
242 {
243 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
244 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
245 struct brw_reg implied_header;
246
247 if (devinfo->gen < 8 && !devinfo->is_haswell) {
248 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
249 }
250
251 if (inst->base_mrf >= 0)
252 payload = brw_message_reg(inst->base_mrf);
253
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
255 * move, here's g1.
256 */
257 if (inst->header_size != 0) {
258 brw_push_insn_state(p);
259 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
260 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
261 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
262 brw_set_default_flag_reg(p, 0, 0);
263
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
265 * present.
266 */
267 if (prog_data->uses_kill) {
268 struct brw_reg pixel_mask;
269
270 if (devinfo->gen >= 6)
271 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
272 else
273 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
274
275 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
276 }
277
278 if (devinfo->gen >= 6) {
279 brw_push_insn_state(p);
280 brw_set_default_exec_size(p, BRW_EXECUTE_16);
281 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
282 brw_MOV(p,
283 retype(payload, BRW_REGISTER_TYPE_UD),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
285 brw_pop_insn_state(p);
286
287 if (inst->target > 0 && key->replicate_alpha) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
289 * header.
290 */
291 brw_OR(p,
292 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
294 brw_imm_ud(0x1 << 11));
295 }
296
297 if (inst->target > 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
300 BRW_REGISTER_TYPE_UD),
301 brw_imm_ud(inst->target));
302 }
303
304 /* Set computes stencil to render target */
305 if (prog_data->computed_stencil) {
306 brw_OR(p,
307 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
309 brw_imm_ud(0x1 << 14));
310 }
311
312 implied_header = brw_null_reg();
313 } else {
314 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
315 }
316
317 brw_pop_insn_state(p);
318 } else {
319 implied_header = brw_null_reg();
320 }
321
322 if (!runtime_check_aads_emit) {
323 fire_fb_write(inst, payload, implied_header, inst->mlen);
324 } else {
325 /* This can only happen in gen < 6 */
326 assert(devinfo->gen < 6);
327
328 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
329
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
332 brw_AND(p,
333 v1_null_ud,
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
335 brw_imm_ud(1<<26));
336 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
337
338 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
339 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
340 {
341 /* Don't send AA data */
342 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
343 }
344 brw_land_fwd_jump(p, jmp);
345 fire_fb_write(inst, payload, implied_header, inst->mlen);
346 }
347 }
348
349 void
350 fs_generator::generate_mov_indirect(fs_inst *inst,
351 struct brw_reg dst,
352 struct brw_reg reg,
353 struct brw_reg indirect_byte_offset)
354 {
355 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
356 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
357
358 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
359
360 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
361 imm_byte_offset += indirect_byte_offset.ud;
362
363 reg.nr = imm_byte_offset / REG_SIZE;
364 reg.subnr = imm_byte_offset % REG_SIZE;
365 brw_MOV(p, dst, reg);
366 } else {
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst->exec_size == 8 || devinfo->gen >= 8);
369
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr = vec8(brw_address_reg(0));
372
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
377 */
378 indirect_byte_offset =
379 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
380
381 struct brw_reg ind_src;
382 if (devinfo->gen < 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
384 *
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
391 *
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
395 *
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
402 */
403 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
404 ind_src = brw_VxH_indirect(0, 0);
405 } else {
406 brw_MOV(p, addr, indirect_byte_offset);
407 ind_src = brw_VxH_indirect(0, imm_byte_offset);
408 }
409
410 brw_inst *mov = brw_MOV(p, dst, retype(ind_src, dst.type));
411
412 if (devinfo->gen == 6 && dst.file == BRW_MESSAGE_REGISTER_FILE &&
413 !inst->get_next()->is_tail_sentinel() &&
414 ((fs_inst *)inst->get_next())->mlen > 0) {
415 /* From the Sandybridge PRM:
416 *
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
421 */
422 brw_inst_set_thread_control(devinfo, mov, BRW_THREAD_SWITCH);
423 }
424 }
425 }
426
427 void
428 fs_generator::generate_urb_read(fs_inst *inst,
429 struct brw_reg dst,
430 struct brw_reg header)
431 {
432 assert(header.file == BRW_GENERAL_REGISTER_FILE);
433 assert(header.type == BRW_REGISTER_TYPE_UD);
434
435 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
436 brw_set_dest(p, send, dst);
437 brw_set_src0(p, send, header);
438 brw_set_src1(p, send, brw_imm_ud(0u));
439
440 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
441 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
442
443 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
444 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
445
446 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
447 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
448 brw_inst_set_header_present(p->devinfo, send, true);
449 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
450 }
451
452 void
453 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
454 {
455 brw_inst *insn;
456
457 insn = brw_next_insn(p, BRW_OPCODE_SEND);
458
459 brw_set_dest(p, insn, brw_null_reg());
460 brw_set_src0(p, insn, payload);
461 brw_set_src1(p, insn, brw_imm_d(0));
462
463 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
464 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
465
466 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
467 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
468 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
469
470 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
471 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
472 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
473
474 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
475 brw_inst_set_rlen(p->devinfo, insn, 0);
476 brw_inst_set_eot(p->devinfo, insn, inst->eot);
477 brw_inst_set_header_present(p->devinfo, insn, true);
478 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
479 }
480
481 void
482 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
483 {
484 struct brw_inst *insn;
485
486 insn = brw_next_insn(p, BRW_OPCODE_SEND);
487
488 brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
489 brw_set_src0(p, insn, payload);
490 brw_set_src1(p, insn, brw_imm_d(0));
491
492 /* Terminate a compute shader by sending a message to the thread spawner.
493 */
494 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
495 brw_inst_set_mlen(devinfo, insn, 1);
496 brw_inst_set_rlen(devinfo, insn, 0);
497 brw_inst_set_eot(devinfo, insn, inst->eot);
498 brw_inst_set_header_present(devinfo, insn, false);
499
500 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
502
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
506 */
507 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
508
509 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
510 }
511
512 void
513 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
514 struct brw_reg dst,
515 struct brw_reg src)
516 {
517 assert(dispatch_width == 8);
518 assert(devinfo->gen >= 9);
519
520 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
521 * Presumably, in order to save memory bandwidth, the stencil reference
522 * values written from the FS need to be packed into 2 dwords (this makes
523 * sense because the stencil values are limited to 1 byte each and a SIMD8
524 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
525 *
526 * The spec is confusing here because in the payload definition of MDP_RTW_S8
527 * (Message Data Payload for Render Target Writes with Stencil 8b) the
528 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
529 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
530 * packed values specified above and diagrammed below:
531 *
532 * 31 0
533 * --------------------------------
534 * DW | |
535 * 2-7 | IGNORED |
536 * | |
537 * --------------------------------
538 * DW1 | STC | STC | STC | STC |
539 * | slot7 | slot6 | slot5 | slot4|
540 * --------------------------------
541 * DW0 | STC | STC | STC | STC |
542 * | slot3 | slot2 | slot1 | slot0|
543 * --------------------------------
544 */
545
546 src.vstride = BRW_VERTICAL_STRIDE_4;
547 src.width = BRW_WIDTH_1;
548 src.hstride = BRW_HORIZONTAL_STRIDE_0;
549 assert(src.type == BRW_REGISTER_TYPE_UB);
550 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
551 }
552
553 void
554 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
555 {
556 brw_barrier(p, src);
557 brw_WAIT(p);
558 }
559
560 void
561 fs_generator::generate_linterp(fs_inst *inst,
562 struct brw_reg dst, struct brw_reg *src)
563 {
564 /* PLN reads:
565 * / in SIMD16 \
566 * -----------------------------------
567 * | src1+0 | src1+1 | src1+2 | src1+3 |
568 * |-----------------------------------|
569 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
570 * -----------------------------------
571 *
572 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
573 *
574 * -----------------------------------
575 * | src1+0 | src1+1 | src1+2 | src1+3 |
576 * |-----------------------------------|
577 * |(x0, x1)|(y0, y1)| | | in SIMD8
578 * |-----------------------------------|
579 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
580 * -----------------------------------
581 *
582 * See also: emit_interpolation_setup_gen4().
583 */
584 struct brw_reg delta_x = src[0];
585 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
586 struct brw_reg interp = src[1];
587
588 if (devinfo->has_pln &&
589 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
590 brw_PLN(p, dst, interp, delta_x);
591 } else {
592 brw_LINE(p, brw_null_reg(), interp, delta_x);
593 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
594 }
595 }
596
597 void
598 fs_generator::generate_get_buffer_size(fs_inst *inst,
599 struct brw_reg dst,
600 struct brw_reg src,
601 struct brw_reg surf_index)
602 {
603 assert(devinfo->gen >= 7);
604 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
605
606 uint32_t simd_mode;
607 int rlen = 4;
608
609 switch (inst->exec_size) {
610 case 8:
611 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
612 break;
613 case 16:
614 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
615 break;
616 default:
617 unreachable("Invalid width for texture instruction");
618 }
619
620 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
621 rlen = 8;
622 dst = vec16(dst);
623 }
624
625 brw_SAMPLE(p,
626 retype(dst, BRW_REGISTER_TYPE_UW),
627 inst->base_mrf,
628 src,
629 surf_index.ud,
630 0,
631 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
632 rlen, /* response length */
633 inst->mlen,
634 inst->header_size > 0,
635 simd_mode,
636 BRW_SAMPLER_RETURN_FORMAT_SINT32);
637
638 brw_mark_surface_used(prog_data, surf_index.ud);
639 }
640
641 void
642 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
643 struct brw_reg surface_index,
644 struct brw_reg sampler_index)
645 {
646 int msg_type = -1;
647 uint32_t simd_mode;
648 uint32_t return_format;
649 bool is_combined_send = inst->eot;
650
651 switch (dst.type) {
652 case BRW_REGISTER_TYPE_D:
653 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
654 break;
655 case BRW_REGISTER_TYPE_UD:
656 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
657 break;
658 default:
659 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
660 break;
661 }
662
663 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
664 * is set as part of the message descriptor. On gen4, the PRM seems to
665 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
666 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
667 * gone from the message descriptor entirely and you just get UINT32 all
668 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
669 * just stomp it to UINT32 all the time.
670 */
671 if (inst->opcode == SHADER_OPCODE_TXS)
672 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
673
674 switch (inst->exec_size) {
675 case 8:
676 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
677 break;
678 case 16:
679 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
680 break;
681 default:
682 unreachable("Invalid width for texture instruction");
683 }
684
685 if (devinfo->gen >= 5) {
686 switch (inst->opcode) {
687 case SHADER_OPCODE_TEX:
688 if (inst->shadow_compare) {
689 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
690 } else {
691 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
692 }
693 break;
694 case FS_OPCODE_TXB:
695 if (inst->shadow_compare) {
696 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
697 } else {
698 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
699 }
700 break;
701 case SHADER_OPCODE_TXL:
702 if (inst->shadow_compare) {
703 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
704 } else {
705 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
706 }
707 break;
708 case SHADER_OPCODE_TXL_LZ:
709 assert(devinfo->gen >= 9);
710 if (inst->shadow_compare) {
711 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ;
712 } else {
713 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LZ;
714 }
715 break;
716 case SHADER_OPCODE_TXS:
717 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
718 break;
719 case SHADER_OPCODE_TXD:
720 if (inst->shadow_compare) {
721 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
722 assert(devinfo->gen >= 8 || devinfo->is_haswell);
723 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
724 } else {
725 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
726 }
727 break;
728 case SHADER_OPCODE_TXF:
729 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
730 break;
731 case SHADER_OPCODE_TXF_LZ:
732 assert(devinfo->gen >= 9);
733 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ;
734 break;
735 case SHADER_OPCODE_TXF_CMS_W:
736 assert(devinfo->gen >= 9);
737 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
738 break;
739 case SHADER_OPCODE_TXF_CMS:
740 if (devinfo->gen >= 7)
741 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
742 else
743 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
744 break;
745 case SHADER_OPCODE_TXF_UMS:
746 assert(devinfo->gen >= 7);
747 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
748 break;
749 case SHADER_OPCODE_TXF_MCS:
750 assert(devinfo->gen >= 7);
751 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
752 break;
753 case SHADER_OPCODE_LOD:
754 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
755 break;
756 case SHADER_OPCODE_TG4:
757 if (inst->shadow_compare) {
758 assert(devinfo->gen >= 7);
759 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
760 } else {
761 assert(devinfo->gen >= 6);
762 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
763 }
764 break;
765 case SHADER_OPCODE_TG4_OFFSET:
766 assert(devinfo->gen >= 7);
767 if (inst->shadow_compare) {
768 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
769 } else {
770 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
771 }
772 break;
773 case SHADER_OPCODE_SAMPLEINFO:
774 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
775 break;
776 default:
777 unreachable("not reached");
778 }
779 } else {
780 switch (inst->opcode) {
781 case SHADER_OPCODE_TEX:
782 /* Note that G45 and older determines shadow compare and dispatch width
783 * from message length for most messages.
784 */
785 if (inst->exec_size == 8) {
786 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
787 if (inst->shadow_compare) {
788 assert(inst->mlen == 6);
789 } else {
790 assert(inst->mlen <= 4);
791 }
792 } else {
793 if (inst->shadow_compare) {
794 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
795 assert(inst->mlen == 9);
796 } else {
797 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
798 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
799 }
800 }
801 break;
802 case FS_OPCODE_TXB:
803 if (inst->shadow_compare) {
804 assert(inst->exec_size == 8);
805 assert(inst->mlen == 6);
806 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
807 } else {
808 assert(inst->mlen == 9);
809 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
810 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
811 }
812 break;
813 case SHADER_OPCODE_TXL:
814 if (inst->shadow_compare) {
815 assert(inst->exec_size == 8);
816 assert(inst->mlen == 6);
817 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
818 } else {
819 assert(inst->mlen == 9);
820 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
821 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
822 }
823 break;
824 case SHADER_OPCODE_TXD:
825 /* There is no sample_d_c message; comparisons are done manually */
826 assert(inst->exec_size == 8);
827 assert(inst->mlen == 7 || inst->mlen == 10);
828 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
829 break;
830 case SHADER_OPCODE_TXF:
831 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
832 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
833 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
834 break;
835 case SHADER_OPCODE_TXS:
836 assert(inst->mlen == 3);
837 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
838 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
839 break;
840 default:
841 unreachable("not reached");
842 }
843 }
844 assert(msg_type != -1);
845
846 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
847 dst = vec16(dst);
848 }
849
850 assert(devinfo->gen < 7 || inst->header_size == 0 ||
851 src.file == BRW_GENERAL_REGISTER_FILE);
852
853 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
854
855 /* Load the message header if present. If there's a texture offset,
856 * we need to set it up explicitly and load the offset bitfield.
857 * Otherwise, we can use an implied move from g0 to the first message reg.
858 */
859 if (inst->header_size != 0) {
860 if (devinfo->gen < 6 && !inst->offset) {
861 /* Set up an implied move from g0 to the MRF. */
862 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
863 } else {
864 struct brw_reg header_reg;
865
866 if (devinfo->gen >= 7) {
867 header_reg = src;
868 } else {
869 assert(inst->base_mrf != -1);
870 header_reg = brw_message_reg(inst->base_mrf);
871 }
872
873 brw_push_insn_state(p);
874 brw_set_default_exec_size(p, BRW_EXECUTE_8);
875 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
876 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
877 /* Explicitly set up the message header by copying g0 to the MRF. */
878 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
879
880 if (inst->offset) {
881 /* Set the offset bits in DWord 2. */
882 brw_MOV(p, get_element_ud(header_reg, 2),
883 brw_imm_ud(inst->offset));
884 } else if (stage != MESA_SHADER_VERTEX &&
885 stage != MESA_SHADER_FRAGMENT) {
886 /* The vertex and fragment stages have g0.2 set to 0, so
887 * header0.2 is 0 when g0 is copied. Other stages may not, so we
888 * must set it to 0 to avoid setting undesirable bits in the
889 * message.
890 */
891 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
892 }
893
894 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
895 brw_pop_insn_state(p);
896 }
897 }
898
899 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
900 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
901 ? prog_data->binding_table.gather_texture_start
902 : prog_data->binding_table.texture_start;
903
904 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
905 sampler_index.file == BRW_IMMEDIATE_VALUE) {
906 uint32_t surface = surface_index.ud;
907 uint32_t sampler = sampler_index.ud;
908
909 brw_SAMPLE(p,
910 retype(dst, BRW_REGISTER_TYPE_UW),
911 inst->base_mrf,
912 src,
913 surface + base_binding_table_index,
914 sampler % 16,
915 msg_type,
916 inst->regs_written,
917 inst->mlen,
918 inst->header_size != 0,
919 simd_mode,
920 return_format);
921
922 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
923 } else {
924 /* Non-const sampler index */
925
926 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
927 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
928 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
929
930 brw_push_insn_state(p);
931 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
932 brw_set_default_access_mode(p, BRW_ALIGN_1);
933
934 if (brw_regs_equal(&surface_reg, &sampler_reg)) {
935 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
936 } else {
937 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
938 brw_OR(p, addr, addr, surface_reg);
939 }
940 if (base_binding_table_index)
941 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
942 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
943
944 brw_pop_insn_state(p);
945
946 /* dst = send(offset, a0.0 | <descriptor>) */
947 brw_inst *insn = brw_send_indirect_message(
948 p, BRW_SFID_SAMPLER, dst, src, addr);
949 brw_set_sampler_message(p, insn,
950 0 /* surface */,
951 0 /* sampler */,
952 msg_type,
953 inst->regs_written,
954 inst->mlen /* mlen */,
955 inst->header_size != 0 /* header */,
956 simd_mode,
957 return_format);
958
959 /* visitor knows more than we do about the surface limit required,
960 * so has already done marking.
961 */
962 }
963
964 if (is_combined_send) {
965 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
966 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
967 }
968 }
969
970
971 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
972 * looking like:
973 *
974 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
975 *
976 * Ideally, we want to produce:
977 *
978 * DDX DDY
979 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
980 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
981 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
982 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
983 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
984 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
985 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
986 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
987 *
988 * and add another set of two more subspans if in 16-pixel dispatch mode.
989 *
990 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
991 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
992 * pair. But the ideal approximation may impose a huge performance cost on
993 * sample_d. On at least Haswell, sample_d instruction does some
994 * optimizations if the same LOD is used for all pixels in the subspan.
995 *
996 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
997 * appropriate swizzling.
998 */
999 void
1000 fs_generator::generate_ddx(enum opcode opcode,
1001 struct brw_reg dst, struct brw_reg src)
1002 {
1003 unsigned vstride, width;
1004
1005 if (opcode == FS_OPCODE_DDX_FINE) {
1006 /* produce accurate derivatives */
1007 vstride = BRW_VERTICAL_STRIDE_2;
1008 width = BRW_WIDTH_2;
1009 } else {
1010 /* replicate the derivative at the top-left pixel to other pixels */
1011 vstride = BRW_VERTICAL_STRIDE_4;
1012 width = BRW_WIDTH_4;
1013 }
1014
1015 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1016 src.negate, src.abs,
1017 BRW_REGISTER_TYPE_F,
1018 vstride,
1019 width,
1020 BRW_HORIZONTAL_STRIDE_0,
1021 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1022 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1023 src.negate, src.abs,
1024 BRW_REGISTER_TYPE_F,
1025 vstride,
1026 width,
1027 BRW_HORIZONTAL_STRIDE_0,
1028 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1029 brw_ADD(p, dst, src0, negate(src1));
1030 }
1031
1032 /* The negate_value boolean is used to negate the derivative computation for
1033 * FBOs, since they place the origin at the upper left instead of the lower
1034 * left.
1035 */
1036 void
1037 fs_generator::generate_ddy(enum opcode opcode,
1038 struct brw_reg dst, struct brw_reg src)
1039 {
1040 if (opcode == FS_OPCODE_DDY_FINE) {
1041 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1042 * Region Restrictions):
1043 *
1044 * In Align16 access mode, SIMD16 is not allowed for DW operations
1045 * and SIMD8 is not allowed for DF operations.
1046 *
1047 * In this context, "DW operations" means "operations acting on 32-bit
1048 * values", so it includes operations on floats.
1049 *
1050 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1051 * (Instruction Compression -> Rules and Restrictions):
1052 *
1053 * A compressed instruction must be in Align1 access mode. Align16
1054 * mode instructions cannot be compressed.
1055 *
1056 * Similar text exists in the g45 PRM.
1057 *
1058 * Empirically, compressed align16 instructions using odd register
1059 * numbers don't appear to work on Sandybridge either.
1060 *
1061 * On these platforms, if we're building a SIMD16 shader, we need to
1062 * manually unroll to a pair of SIMD8 instructions.
1063 */
1064 bool unroll_to_simd8 =
1065 (dispatch_width == 16 &&
1066 (devinfo->gen == 4 || devinfo->gen == 6 ||
1067 (devinfo->gen == 7 && !devinfo->is_haswell)));
1068
1069 /* produce accurate derivatives */
1070 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1071 src.negate, src.abs,
1072 BRW_REGISTER_TYPE_F,
1073 BRW_VERTICAL_STRIDE_4,
1074 BRW_WIDTH_4,
1075 BRW_HORIZONTAL_STRIDE_1,
1076 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1077 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1078 src.negate, src.abs,
1079 BRW_REGISTER_TYPE_F,
1080 BRW_VERTICAL_STRIDE_4,
1081 BRW_WIDTH_4,
1082 BRW_HORIZONTAL_STRIDE_1,
1083 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1084 brw_push_insn_state(p);
1085 brw_set_default_access_mode(p, BRW_ALIGN_16);
1086 if (unroll_to_simd8) {
1087 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1088 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1089 brw_ADD(p, firsthalf(dst), negate(firsthalf(src0)), firsthalf(src1));
1090 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1091 brw_ADD(p, sechalf(dst), negate(sechalf(src0)), sechalf(src1));
1092 } else {
1093 brw_ADD(p, dst, negate(src0), src1);
1094 }
1095 brw_pop_insn_state(p);
1096 } else {
1097 /* replicate the derivative at the top-left pixel to other pixels */
1098 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1099 src.negate, src.abs,
1100 BRW_REGISTER_TYPE_F,
1101 BRW_VERTICAL_STRIDE_4,
1102 BRW_WIDTH_4,
1103 BRW_HORIZONTAL_STRIDE_0,
1104 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1105 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1106 src.negate, src.abs,
1107 BRW_REGISTER_TYPE_F,
1108 BRW_VERTICAL_STRIDE_4,
1109 BRW_WIDTH_4,
1110 BRW_HORIZONTAL_STRIDE_0,
1111 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1112 brw_ADD(p, dst, negate(src0), src1);
1113 }
1114 }
1115
1116 void
1117 fs_generator::generate_discard_jump(fs_inst *inst)
1118 {
1119 assert(devinfo->gen >= 6);
1120
1121 /* This HALT will be patched up at FB write time to point UIP at the end of
1122 * the program, and at brw_uip_jip() JIP will be set to the end of the
1123 * current block (or the program).
1124 */
1125 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1126
1127 brw_push_insn_state(p);
1128 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1129 gen6_HALT(p);
1130 brw_pop_insn_state(p);
1131 }
1132
1133 void
1134 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1135 {
1136 assert(inst->mlen != 0);
1137
1138 brw_MOV(p,
1139 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1140 retype(src, BRW_REGISTER_TYPE_UD));
1141 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1142 inst->exec_size / 8, inst->offset);
1143 }
1144
1145 void
1146 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1147 {
1148 assert(inst->mlen != 0);
1149
1150 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1151 inst->exec_size / 8, inst->offset);
1152 }
1153
1154 void
1155 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1156 {
1157 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1158 }
1159
1160 void
1161 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1162 struct brw_reg dst,
1163 struct brw_reg index,
1164 struct brw_reg offset)
1165 {
1166 assert(inst->mlen != 0);
1167
1168 assert(index.file == BRW_IMMEDIATE_VALUE &&
1169 index.type == BRW_REGISTER_TYPE_UD);
1170 uint32_t surf_index = index.ud;
1171
1172 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1173 offset.type == BRW_REGISTER_TYPE_UD);
1174 uint32_t read_offset = offset.ud;
1175
1176 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1177 read_offset, surf_index);
1178 }
1179
1180 void
1181 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1182 struct brw_reg dst,
1183 struct brw_reg index,
1184 struct brw_reg offset)
1185 {
1186 assert(index.type == BRW_REGISTER_TYPE_UD);
1187
1188 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1189 /* Reference just the dword we need, to avoid angering validate_reg(). */
1190 offset = brw_vec1_grf(offset.nr, 0);
1191
1192 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1193 * the destination loaded consecutively from the same offset (which appears
1194 * in the first component, and the rest are ignored).
1195 */
1196 dst.width = BRW_WIDTH_4;
1197
1198 struct brw_reg src = offset;
1199 bool header_present = false;
1200
1201 if (devinfo->gen >= 9) {
1202 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1203 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1204 header_present = true;
1205
1206 brw_push_insn_state(p);
1207 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1208 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1209 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1210 brw_set_default_access_mode(p, BRW_ALIGN_1);
1211
1212 brw_MOV(p, get_element_ud(src, 2),
1213 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1214 brw_pop_insn_state(p);
1215 }
1216
1217 if (index.file == BRW_IMMEDIATE_VALUE) {
1218
1219 uint32_t surf_index = index.ud;
1220
1221 brw_push_insn_state(p);
1222 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1223 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1224 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1225 brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
1226 brw_pop_insn_state(p);
1227
1228 brw_set_dest(p, send, dst);
1229 brw_set_src0(p, send, src);
1230 brw_set_sampler_message(p, send,
1231 surf_index,
1232 0, /* LD message ignores sampler unit */
1233 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1234 1, /* rlen */
1235 inst->mlen,
1236 header_present,
1237 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1238 0);
1239 } else {
1240
1241 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1242
1243 brw_push_insn_state(p);
1244 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1245 brw_set_default_access_mode(p, BRW_ALIGN_1);
1246
1247 /* a0.0 = surf_index & 0xff */
1248 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1249 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1250 brw_set_dest(p, insn_and, addr);
1251 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1252 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1253
1254 /* dst = send(payload, a0.0 | <descriptor>) */
1255 brw_inst *insn = brw_send_indirect_message(
1256 p, BRW_SFID_SAMPLER, dst, src, addr);
1257 brw_set_sampler_message(p, insn,
1258 0,
1259 0, /* LD message ignores sampler unit */
1260 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1261 1, /* rlen */
1262 inst->mlen,
1263 header_present,
1264 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1265 0);
1266
1267 brw_pop_insn_state(p);
1268 }
1269 }
1270
1271 void
1272 fs_generator::generate_varying_pull_constant_load_gen4(fs_inst *inst,
1273 struct brw_reg dst,
1274 struct brw_reg index)
1275 {
1276 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1277 assert(inst->header_size != 0);
1278 assert(inst->mlen);
1279
1280 assert(index.file == BRW_IMMEDIATE_VALUE &&
1281 index.type == BRW_REGISTER_TYPE_UD);
1282 uint32_t surf_index = index.ud;
1283
1284 uint32_t simd_mode, rlen, msg_type;
1285 if (dispatch_width == 16) {
1286 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1287 rlen = 8;
1288 } else {
1289 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1290 rlen = 4;
1291 }
1292
1293 if (devinfo->gen >= 5)
1294 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1295 else {
1296 /* We always use the SIMD16 message so that we only have to load U, and
1297 * not V or R.
1298 */
1299 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1300 assert(inst->mlen == 3);
1301 assert(inst->regs_written == 8);
1302 rlen = 8;
1303 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1304 }
1305
1306 struct brw_reg header = brw_vec8_grf(0, 0);
1307 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1308
1309 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1310 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1311 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1312 brw_set_src0(p, send, header);
1313 if (devinfo->gen < 6)
1314 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1315
1316 /* Our surface is set up as floats, regardless of what actual data is
1317 * stored in it.
1318 */
1319 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1320 brw_set_sampler_message(p, send,
1321 surf_index,
1322 0, /* sampler (unused) */
1323 msg_type,
1324 rlen,
1325 inst->mlen,
1326 inst->header_size != 0,
1327 simd_mode,
1328 return_format);
1329 }
1330
1331 void
1332 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1333 struct brw_reg dst,
1334 struct brw_reg index,
1335 struct brw_reg offset)
1336 {
1337 assert(devinfo->gen >= 7);
1338 /* Varying-offset pull constant loads are treated as a normal expression on
1339 * gen7, so the fact that it's a send message is hidden at the IR level.
1340 */
1341 assert(inst->header_size == 0);
1342 assert(!inst->mlen);
1343 assert(index.type == BRW_REGISTER_TYPE_UD);
1344
1345 uint32_t simd_mode, rlen, mlen;
1346 if (dispatch_width == 16) {
1347 mlen = 2;
1348 rlen = 8;
1349 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1350 } else {
1351 mlen = 1;
1352 rlen = 4;
1353 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1354 }
1355
1356 if (index.file == BRW_IMMEDIATE_VALUE) {
1357
1358 uint32_t surf_index = index.ud;
1359
1360 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1361 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1362 brw_set_src0(p, send, offset);
1363 brw_set_sampler_message(p, send,
1364 surf_index,
1365 0, /* LD message ignores sampler unit */
1366 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1367 rlen,
1368 mlen,
1369 false, /* no header */
1370 simd_mode,
1371 0);
1372
1373 } else {
1374
1375 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1376
1377 brw_push_insn_state(p);
1378 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1379 brw_set_default_access_mode(p, BRW_ALIGN_1);
1380
1381 /* a0.0 = surf_index & 0xff */
1382 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1383 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1384 brw_set_dest(p, insn_and, addr);
1385 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1386 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1387
1388 brw_pop_insn_state(p);
1389
1390 /* dst = send(offset, a0.0 | <descriptor>) */
1391 brw_inst *insn = brw_send_indirect_message(
1392 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1393 offset, addr);
1394 brw_set_sampler_message(p, insn,
1395 0 /* surface */,
1396 0 /* sampler */,
1397 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1398 rlen /* rlen */,
1399 mlen /* mlen */,
1400 false /* header */,
1401 simd_mode,
1402 0);
1403 }
1404 }
1405
1406 /**
1407 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1408 * into the flags register (f0.0).
1409 *
1410 * Used only on Gen6 and above.
1411 */
1412 void
1413 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1414 {
1415 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1416 struct brw_reg dispatch_mask;
1417
1418 if (devinfo->gen >= 6)
1419 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1420 else
1421 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1422
1423 brw_push_insn_state(p);
1424 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1425 brw_MOV(p, flags, dispatch_mask);
1426 brw_pop_insn_state(p);
1427 }
1428
1429 void
1430 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1431 struct brw_reg dst,
1432 struct brw_reg src,
1433 struct brw_reg msg_data,
1434 unsigned msg_type)
1435 {
1436 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1437
1438 brw_pixel_interpolator_query(p,
1439 retype(dst, BRW_REGISTER_TYPE_UW),
1440 src,
1441 inst->pi_noperspective,
1442 msg_type,
1443 msg_data,
1444 inst->mlen,
1445 inst->regs_written);
1446 }
1447
1448
1449 /**
1450 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1451 * sampler LD messages.
1452 *
1453 * We don't want to bake it into the send message's code generation because
1454 * that means we don't get a chance to schedule the instructions.
1455 */
1456 void
1457 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1458 struct brw_reg dst,
1459 struct brw_reg value)
1460 {
1461 assert(value.file == BRW_IMMEDIATE_VALUE);
1462
1463 brw_push_insn_state(p);
1464 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1465 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1466 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1467 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1468 brw_pop_insn_state(p);
1469 }
1470
1471 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1472 * the ADD instruction.
1473 */
1474 void
1475 fs_generator::generate_set_sample_id(fs_inst *inst,
1476 struct brw_reg dst,
1477 struct brw_reg src0,
1478 struct brw_reg src1)
1479 {
1480 assert(dst.type == BRW_REGISTER_TYPE_D ||
1481 dst.type == BRW_REGISTER_TYPE_UD);
1482 assert(src0.type == BRW_REGISTER_TYPE_D ||
1483 src0.type == BRW_REGISTER_TYPE_UD);
1484
1485 struct brw_reg reg = stride(src1, 1, 4, 0);
1486 if (devinfo->gen >= 8 || dispatch_width == 8) {
1487 brw_ADD(p, dst, src0, reg);
1488 } else if (dispatch_width == 16) {
1489 brw_push_insn_state(p);
1490 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1491 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1492 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1493 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1494 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1495 brw_pop_insn_state(p);
1496 }
1497 }
1498
1499 void
1500 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1501 struct brw_reg dst,
1502 struct brw_reg x,
1503 struct brw_reg y)
1504 {
1505 assert(devinfo->gen >= 7);
1506 assert(dst.type == BRW_REGISTER_TYPE_UD);
1507 assert(x.type == BRW_REGISTER_TYPE_F);
1508 assert(y.type == BRW_REGISTER_TYPE_F);
1509
1510 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1511 *
1512 * Because this instruction does not have a 16-bit floating-point type,
1513 * the destination data type must be Word (W).
1514 *
1515 * The destination must be DWord-aligned and specify a horizontal stride
1516 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1517 * each destination channel and the upper word is not modified.
1518 */
1519 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1520
1521 /* Give each 32-bit channel of dst the form below, where "." means
1522 * unchanged.
1523 * 0x....hhhh
1524 */
1525 brw_F32TO16(p, dst_w, y);
1526
1527 /* Now the form:
1528 * 0xhhhh0000
1529 */
1530 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1531
1532 /* And, finally the form of packHalf2x16's output:
1533 * 0xhhhhllll
1534 */
1535 brw_F32TO16(p, dst_w, x);
1536 }
1537
1538 void
1539 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1540 struct brw_reg dst,
1541 struct brw_reg src)
1542 {
1543 assert(devinfo->gen >= 7);
1544 assert(dst.type == BRW_REGISTER_TYPE_F);
1545 assert(src.type == BRW_REGISTER_TYPE_UD);
1546
1547 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1548 *
1549 * Because this instruction does not have a 16-bit floating-point type,
1550 * the source data type must be Word (W). The destination type must be
1551 * F (Float).
1552 */
1553 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1554
1555 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1556 * For the Y case, we wish to access only the upper word; therefore
1557 * a 16-bit subregister offset is needed.
1558 */
1559 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1560 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1561 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1562 src_w.subnr += 2;
1563
1564 brw_F16TO32(p, dst, src_w);
1565 }
1566
1567 void
1568 fs_generator::generate_shader_time_add(fs_inst *inst,
1569 struct brw_reg payload,
1570 struct brw_reg offset,
1571 struct brw_reg value)
1572 {
1573 assert(devinfo->gen >= 7);
1574 brw_push_insn_state(p);
1575 brw_set_default_mask_control(p, true);
1576
1577 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1578 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1579 offset.type);
1580 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1581 value.type);
1582
1583 assert(offset.file == BRW_IMMEDIATE_VALUE);
1584 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1585 value.width = BRW_WIDTH_1;
1586 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1587 value.vstride = BRW_VERTICAL_STRIDE_0;
1588 } else {
1589 assert(value.file == BRW_IMMEDIATE_VALUE);
1590 }
1591
1592 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1593 * case, and we don't really care about squeezing every bit of performance
1594 * out of this path, so we just emit the MOVs from here.
1595 */
1596 brw_MOV(p, payload_offset, offset);
1597 brw_MOV(p, payload_value, value);
1598 brw_shader_time_add(p, payload,
1599 prog_data->binding_table.shader_time_start);
1600 brw_pop_insn_state(p);
1601
1602 brw_mark_surface_used(prog_data,
1603 prog_data->binding_table.shader_time_start);
1604 }
1605
1606 void
1607 fs_generator::enable_debug(const char *shader_name)
1608 {
1609 debug_flag = true;
1610 this->shader_name = shader_name;
1611 }
1612
1613 int
1614 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1615 {
1616 /* align to 64 byte boundary. */
1617 while (p->next_insn_offset % 64)
1618 brw_NOP(p);
1619
1620 this->dispatch_width = dispatch_width;
1621 if (dispatch_width == 16)
1622 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1623
1624 int start_offset = p->next_insn_offset;
1625 int spill_count = 0, fill_count = 0;
1626 int loop_count = 0;
1627
1628 struct annotation_info annotation;
1629 memset(&annotation, 0, sizeof(annotation));
1630
1631 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1632 struct brw_reg src[3], dst;
1633 unsigned int last_insn_offset = p->next_insn_offset;
1634 bool multiple_instructions_emitted = false;
1635
1636 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1637 * "Register Region Restrictions" section: for BDW, SKL:
1638 *
1639 * "A POW/FDIV operation must not be followed by an instruction
1640 * that requires two destination registers."
1641 *
1642 * The documentation is often lacking annotations for Atom parts,
1643 * and empirically this affects CHV as well.
1644 */
1645 if (devinfo->gen >= 8 &&
1646 p->nr_insn > 1 &&
1647 brw_inst_opcode(devinfo, brw_last_inst) == BRW_OPCODE_MATH &&
1648 brw_inst_math_function(devinfo, brw_last_inst) == BRW_MATH_FUNCTION_POW &&
1649 inst->dst.component_size(inst->exec_size) > REG_SIZE) {
1650 brw_NOP(p);
1651 last_insn_offset = p->next_insn_offset;
1652 }
1653
1654 if (unlikely(debug_flag))
1655 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1656
1657 switch (inst->exec_size) {
1658 case 1:
1659 case 2:
1660 case 4:
1661 assert(inst->force_writemask_all);
1662 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1663 break;
1664 case 8:
1665 if (inst->force_sechalf) {
1666 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1667 } else {
1668 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1669 }
1670 break;
1671 case 16:
1672 case 32:
1673 /* If the instruction writes to more than one register, it needs to
1674 * be a "compressed" instruction on Gen <= 5.
1675 */
1676 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1677 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1678 else
1679 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1680 break;
1681 default:
1682 unreachable("Invalid instruction width");
1683 }
1684
1685 for (unsigned int i = 0; i < inst->sources; i++) {
1686 src[i] = brw_reg_from_fs_reg(p, inst, &inst->src[i], devinfo->gen);
1687
1688 /* The accumulator result appears to get used for the
1689 * conditional modifier generation. When negating a UD
1690 * value, there is a 33rd bit generated for the sign in the
1691 * accumulator value, so now you can't check, for example,
1692 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1693 */
1694 assert(!inst->conditional_mod ||
1695 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1696 !inst->src[i].negate);
1697 }
1698 dst = brw_reg_from_fs_reg(p, inst, &inst->dst, devinfo->gen);
1699
1700 brw_set_default_predicate_control(p, inst->predicate);
1701 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1702 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1703 brw_set_default_saturate(p, inst->saturate);
1704 brw_set_default_mask_control(p, inst->force_writemask_all);
1705 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1706 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1707
1708 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1709 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1710
1711 switch (inst->opcode) {
1712 case BRW_OPCODE_MOV:
1713 brw_MOV(p, dst, src[0]);
1714 break;
1715 case BRW_OPCODE_ADD:
1716 brw_ADD(p, dst, src[0], src[1]);
1717 break;
1718 case BRW_OPCODE_MUL:
1719 brw_MUL(p, dst, src[0], src[1]);
1720 break;
1721 case BRW_OPCODE_AVG:
1722 brw_AVG(p, dst, src[0], src[1]);
1723 break;
1724 case BRW_OPCODE_MACH:
1725 brw_MACH(p, dst, src[0], src[1]);
1726 break;
1727
1728 case BRW_OPCODE_LINE:
1729 brw_LINE(p, dst, src[0], src[1]);
1730 break;
1731
1732 case BRW_OPCODE_MAD:
1733 assert(devinfo->gen >= 6);
1734 brw_set_default_access_mode(p, BRW_ALIGN_16);
1735 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1736 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1737 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1738 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1739 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1740 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1741 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1742
1743 if (inst->conditional_mod) {
1744 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1745 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1746 multiple_instructions_emitted = true;
1747 }
1748 } else {
1749 brw_MAD(p, dst, src[0], src[1], src[2]);
1750 }
1751 brw_set_default_access_mode(p, BRW_ALIGN_1);
1752 break;
1753
1754 case BRW_OPCODE_LRP:
1755 assert(devinfo->gen >= 6);
1756 brw_set_default_access_mode(p, BRW_ALIGN_16);
1757 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1758 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1759 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1760 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1761 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1762 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1763 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1764
1765 if (inst->conditional_mod) {
1766 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1767 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1768 multiple_instructions_emitted = true;
1769 }
1770 } else {
1771 brw_LRP(p, dst, src[0], src[1], src[2]);
1772 }
1773 brw_set_default_access_mode(p, BRW_ALIGN_1);
1774 break;
1775
1776 case BRW_OPCODE_FRC:
1777 brw_FRC(p, dst, src[0]);
1778 break;
1779 case BRW_OPCODE_RNDD:
1780 brw_RNDD(p, dst, src[0]);
1781 break;
1782 case BRW_OPCODE_RNDE:
1783 brw_RNDE(p, dst, src[0]);
1784 break;
1785 case BRW_OPCODE_RNDZ:
1786 brw_RNDZ(p, dst, src[0]);
1787 break;
1788
1789 case BRW_OPCODE_AND:
1790 brw_AND(p, dst, src[0], src[1]);
1791 break;
1792 case BRW_OPCODE_OR:
1793 brw_OR(p, dst, src[0], src[1]);
1794 break;
1795 case BRW_OPCODE_XOR:
1796 brw_XOR(p, dst, src[0], src[1]);
1797 break;
1798 case BRW_OPCODE_NOT:
1799 brw_NOT(p, dst, src[0]);
1800 break;
1801 case BRW_OPCODE_ASR:
1802 brw_ASR(p, dst, src[0], src[1]);
1803 break;
1804 case BRW_OPCODE_SHR:
1805 brw_SHR(p, dst, src[0], src[1]);
1806 break;
1807 case BRW_OPCODE_SHL:
1808 brw_SHL(p, dst, src[0], src[1]);
1809 break;
1810 case BRW_OPCODE_F32TO16:
1811 assert(devinfo->gen >= 7);
1812 brw_F32TO16(p, dst, src[0]);
1813 break;
1814 case BRW_OPCODE_F16TO32:
1815 assert(devinfo->gen >= 7);
1816 brw_F16TO32(p, dst, src[0]);
1817 break;
1818 case BRW_OPCODE_CMP:
1819 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1820 * that when the destination is a GRF that the dependency-clear bit on
1821 * the flag register is cleared early.
1822 *
1823 * Suggested workarounds are to disable coissuing CMP instructions
1824 * or to split CMP(16) instructions into two CMP(8) instructions.
1825 *
1826 * We choose to split into CMP(8) instructions since disabling
1827 * coissuing would affect CMP instructions not otherwise affected by
1828 * the errata.
1829 */
1830 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1831 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1832 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1833 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1834 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1835 firsthalf(src[0]), firsthalf(src[1]));
1836 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1837 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1838 sechalf(src[0]), sechalf(src[1]));
1839 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1840
1841 multiple_instructions_emitted = true;
1842 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1843 /* For unknown reasons, the aforementioned workaround is not
1844 * sufficient. Overriding the type when the destination is the
1845 * null register is necessary but not sufficient by itself.
1846 */
1847 assert(dst.nr == BRW_ARF_NULL);
1848 dst.type = BRW_REGISTER_TYPE_D;
1849 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1850 } else {
1851 unreachable("not reached");
1852 }
1853 } else {
1854 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1855 }
1856 break;
1857 case BRW_OPCODE_SEL:
1858 brw_SEL(p, dst, src[0], src[1]);
1859 break;
1860 case BRW_OPCODE_BFREV:
1861 assert(devinfo->gen >= 7);
1862 /* BFREV only supports UD type for src and dst. */
1863 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1864 retype(src[0], BRW_REGISTER_TYPE_UD));
1865 break;
1866 case BRW_OPCODE_FBH:
1867 assert(devinfo->gen >= 7);
1868 /* FBH only supports UD type for dst. */
1869 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1870 break;
1871 case BRW_OPCODE_FBL:
1872 assert(devinfo->gen >= 7);
1873 /* FBL only supports UD type for dst. */
1874 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1875 break;
1876 case BRW_OPCODE_CBIT:
1877 assert(devinfo->gen >= 7);
1878 /* CBIT only supports UD type for dst. */
1879 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1880 break;
1881 case BRW_OPCODE_ADDC:
1882 assert(devinfo->gen >= 7);
1883 brw_ADDC(p, dst, src[0], src[1]);
1884 break;
1885 case BRW_OPCODE_SUBB:
1886 assert(devinfo->gen >= 7);
1887 brw_SUBB(p, dst, src[0], src[1]);
1888 break;
1889 case BRW_OPCODE_MAC:
1890 brw_MAC(p, dst, src[0], src[1]);
1891 break;
1892
1893 case BRW_OPCODE_BFE:
1894 assert(devinfo->gen >= 7);
1895 brw_set_default_access_mode(p, BRW_ALIGN_16);
1896 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1897 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1898 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1899 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1900 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1901 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1902 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1903 } else {
1904 brw_BFE(p, dst, src[0], src[1], src[2]);
1905 }
1906 brw_set_default_access_mode(p, BRW_ALIGN_1);
1907 break;
1908
1909 case BRW_OPCODE_BFI1:
1910 assert(devinfo->gen >= 7);
1911 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1912 * should
1913 *
1914 * "Force BFI instructions to be executed always in SIMD8."
1915 */
1916 if (dispatch_width == 16 && devinfo->is_haswell) {
1917 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1918 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1919 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1920 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1921 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1922 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1923 } else {
1924 brw_BFI1(p, dst, src[0], src[1]);
1925 }
1926 break;
1927 case BRW_OPCODE_BFI2:
1928 assert(devinfo->gen >= 7);
1929 brw_set_default_access_mode(p, BRW_ALIGN_16);
1930 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1931 * should
1932 *
1933 * "Force BFI instructions to be executed always in SIMD8."
1934 *
1935 * Otherwise we would be able to emit compressed instructions like we
1936 * do for the other three-source instructions.
1937 */
1938 if (dispatch_width == 16 &&
1939 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1940 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1941 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1942 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1943 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1944 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1945 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1946 } else {
1947 brw_BFI2(p, dst, src[0], src[1], src[2]);
1948 }
1949 brw_set_default_access_mode(p, BRW_ALIGN_1);
1950 break;
1951
1952 case BRW_OPCODE_IF:
1953 if (inst->src[0].file != BAD_FILE) {
1954 /* The instruction has an embedded compare (only allowed on gen6) */
1955 assert(devinfo->gen == 6);
1956 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1957 } else {
1958 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1959 }
1960 break;
1961
1962 case BRW_OPCODE_ELSE:
1963 brw_ELSE(p);
1964 break;
1965 case BRW_OPCODE_ENDIF:
1966 brw_ENDIF(p);
1967 break;
1968
1969 case BRW_OPCODE_DO:
1970 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1971 break;
1972
1973 case BRW_OPCODE_BREAK:
1974 brw_BREAK(p);
1975 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1976 break;
1977 case BRW_OPCODE_CONTINUE:
1978 brw_CONT(p);
1979 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
1980 break;
1981
1982 case BRW_OPCODE_WHILE:
1983 brw_WHILE(p);
1984 loop_count++;
1985 break;
1986
1987 case SHADER_OPCODE_RCP:
1988 case SHADER_OPCODE_RSQ:
1989 case SHADER_OPCODE_SQRT:
1990 case SHADER_OPCODE_EXP2:
1991 case SHADER_OPCODE_LOG2:
1992 case SHADER_OPCODE_SIN:
1993 case SHADER_OPCODE_COS:
1994 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
1995 if (devinfo->gen >= 6) {
1996 assert(inst->mlen == 0);
1997 assert(devinfo->gen >= 7 || inst->exec_size == 8);
1998 gen6_math(p, dst, brw_math_function(inst->opcode),
1999 src[0], brw_null_reg());
2000 } else {
2001 assert(inst->mlen >= 1);
2002 assert(devinfo->gen == 5 || devinfo->is_g4x || inst->exec_size == 8);
2003 gen4_math(p, dst,
2004 brw_math_function(inst->opcode),
2005 inst->base_mrf, src[0],
2006 BRW_MATH_PRECISION_FULL);
2007 }
2008 break;
2009 case SHADER_OPCODE_INT_QUOTIENT:
2010 case SHADER_OPCODE_INT_REMAINDER:
2011 case SHADER_OPCODE_POW:
2012 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2013 if (devinfo->gen >= 6) {
2014 assert(inst->mlen == 0);
2015 assert((devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) ||
2016 inst->exec_size == 8);
2017 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2018 } else {
2019 assert(inst->mlen >= 1);
2020 assert(inst->exec_size == 8);
2021 gen4_math(p, dst, brw_math_function(inst->opcode),
2022 inst->base_mrf, src[0],
2023 BRW_MATH_PRECISION_FULL);
2024 }
2025 break;
2026 case FS_OPCODE_CINTERP:
2027 brw_MOV(p, dst, src[0]);
2028 break;
2029 case FS_OPCODE_LINTERP:
2030 generate_linterp(inst, dst, src);
2031 break;
2032 case FS_OPCODE_PIXEL_X:
2033 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2034 src[0].subnr = 0 * type_sz(src[0].type);
2035 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2036 break;
2037 case FS_OPCODE_PIXEL_Y:
2038 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2039 src[0].subnr = 4 * type_sz(src[0].type);
2040 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2041 break;
2042 case FS_OPCODE_GET_BUFFER_SIZE:
2043 generate_get_buffer_size(inst, dst, src[0], src[1]);
2044 break;
2045 case SHADER_OPCODE_TEX:
2046 case FS_OPCODE_TXB:
2047 case SHADER_OPCODE_TXD:
2048 case SHADER_OPCODE_TXF:
2049 case SHADER_OPCODE_TXF_LZ:
2050 case SHADER_OPCODE_TXF_CMS:
2051 case SHADER_OPCODE_TXF_CMS_W:
2052 case SHADER_OPCODE_TXF_UMS:
2053 case SHADER_OPCODE_TXF_MCS:
2054 case SHADER_OPCODE_TXL:
2055 case SHADER_OPCODE_TXL_LZ:
2056 case SHADER_OPCODE_TXS:
2057 case SHADER_OPCODE_LOD:
2058 case SHADER_OPCODE_TG4:
2059 case SHADER_OPCODE_TG4_OFFSET:
2060 case SHADER_OPCODE_SAMPLEINFO:
2061 generate_tex(inst, dst, src[0], src[1], src[2]);
2062 break;
2063 case FS_OPCODE_DDX_COARSE:
2064 case FS_OPCODE_DDX_FINE:
2065 generate_ddx(inst->opcode, dst, src[0]);
2066 break;
2067 case FS_OPCODE_DDY_COARSE:
2068 case FS_OPCODE_DDY_FINE:
2069 generate_ddy(inst->opcode, dst, src[0]);
2070 break;
2071
2072 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2073 generate_scratch_write(inst, src[0]);
2074 spill_count++;
2075 break;
2076
2077 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2078 generate_scratch_read(inst, dst);
2079 fill_count++;
2080 break;
2081
2082 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2083 generate_scratch_read_gen7(inst, dst);
2084 fill_count++;
2085 break;
2086
2087 case SHADER_OPCODE_MOV_INDIRECT:
2088 generate_mov_indirect(inst, dst, src[0], src[1]);
2089 break;
2090
2091 case SHADER_OPCODE_URB_READ_SIMD8:
2092 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2093 generate_urb_read(inst, dst, src[0]);
2094 break;
2095
2096 case SHADER_OPCODE_URB_WRITE_SIMD8:
2097 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2098 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2099 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2100 generate_urb_write(inst, src[0]);
2101 break;
2102
2103 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2104 assert(inst->force_writemask_all);
2105 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2106 break;
2107
2108 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2109 assert(inst->force_writemask_all);
2110 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2111 break;
2112
2113 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4:
2114 generate_varying_pull_constant_load_gen4(inst, dst, src[0]);
2115 break;
2116
2117 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2118 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2119 break;
2120
2121 case FS_OPCODE_REP_FB_WRITE:
2122 case FS_OPCODE_FB_WRITE:
2123 generate_fb_write(inst, src[0]);
2124 break;
2125
2126 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2127 generate_mov_dispatch_to_flags(inst);
2128 break;
2129
2130 case FS_OPCODE_DISCARD_JUMP:
2131 generate_discard_jump(inst);
2132 break;
2133
2134 case SHADER_OPCODE_SHADER_TIME_ADD:
2135 generate_shader_time_add(inst, src[0], src[1], src[2]);
2136 break;
2137
2138 case SHADER_OPCODE_UNTYPED_ATOMIC:
2139 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2140 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2141 inst->mlen, !inst->dst.is_null());
2142 break;
2143
2144 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2145 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2146 brw_untyped_surface_read(p, dst, src[0], src[1],
2147 inst->mlen, src[2].ud);
2148 break;
2149
2150 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2151 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2152 brw_untyped_surface_write(p, src[0], src[1],
2153 inst->mlen, src[2].ud);
2154 break;
2155
2156 case SHADER_OPCODE_TYPED_ATOMIC:
2157 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2158 brw_typed_atomic(p, dst, src[0], src[1],
2159 src[2].ud, inst->mlen, !inst->dst.is_null());
2160 break;
2161
2162 case SHADER_OPCODE_TYPED_SURFACE_READ:
2163 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2164 brw_typed_surface_read(p, dst, src[0], src[1],
2165 inst->mlen, src[2].ud);
2166 break;
2167
2168 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2169 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2170 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2171 break;
2172
2173 case SHADER_OPCODE_MEMORY_FENCE:
2174 brw_memory_fence(p, dst);
2175 break;
2176
2177 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2178 generate_set_simd4x2_offset(inst, dst, src[0]);
2179 break;
2180
2181 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2182 brw_find_live_channel(p, dst);
2183 break;
2184
2185 case SHADER_OPCODE_BROADCAST:
2186 brw_broadcast(p, dst, src[0], src[1]);
2187 break;
2188
2189 case SHADER_OPCODE_EXTRACT_BYTE: {
2190 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2191 src[0].type == BRW_REGISTER_TYPE_UD);
2192
2193 enum brw_reg_type type =
2194 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
2195 : BRW_REGISTER_TYPE_UB;
2196 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
2197 break;
2198 }
2199
2200 case SHADER_OPCODE_EXTRACT_WORD: {
2201 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2202 src[0].type == BRW_REGISTER_TYPE_UD);
2203
2204 enum brw_reg_type type =
2205 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
2206 : BRW_REGISTER_TYPE_UW;
2207 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
2208 break;
2209 }
2210
2211 case FS_OPCODE_SET_SAMPLE_ID:
2212 generate_set_sample_id(inst, dst, src[0], src[1]);
2213 break;
2214
2215 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2216 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2217 break;
2218
2219 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2220 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2221 generate_unpack_half_2x16_split(inst, dst, src[0]);
2222 break;
2223
2224 case FS_OPCODE_PLACEHOLDER_HALT:
2225 /* This is the place where the final HALT needs to be inserted if
2226 * we've emitted any discards. If not, this will emit no code.
2227 */
2228 if (!patch_discard_jumps_to_fb_writes()) {
2229 if (unlikely(debug_flag)) {
2230 annotation.ann_count--;
2231 }
2232 }
2233 break;
2234
2235 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2236 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2237 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2238 break;
2239
2240 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2241 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2242 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2243 break;
2244
2245 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2246 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2247 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2248 break;
2249
2250 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2251 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2252 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2253 break;
2254
2255 case CS_OPCODE_CS_TERMINATE:
2256 generate_cs_terminate(inst, src[0]);
2257 break;
2258
2259 case SHADER_OPCODE_BARRIER:
2260 generate_barrier(inst, src[0]);
2261 break;
2262
2263 case FS_OPCODE_PACK_STENCIL_REF:
2264 generate_stencil_ref_packing(inst, dst, src[0]);
2265 break;
2266
2267 default:
2268 unreachable("Unsupported opcode");
2269
2270 case SHADER_OPCODE_LOAD_PAYLOAD:
2271 unreachable("Should be lowered by lower_load_payload()");
2272 }
2273
2274 if (multiple_instructions_emitted)
2275 continue;
2276
2277 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2278 assert(p->next_insn_offset == last_insn_offset + 16 ||
2279 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2280 "emitting more than 1 instruction");
2281
2282 brw_inst *last = &p->store[last_insn_offset / 16];
2283
2284 if (inst->conditional_mod)
2285 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2286 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2287 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2288 }
2289 }
2290
2291 brw_set_uip_jip(p);
2292 annotation_finalize(&annotation, p->next_insn_offset);
2293
2294 #ifndef NDEBUG
2295 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2296 #else
2297 if (unlikely(debug_flag))
2298 brw_validate_instructions(p, start_offset, &annotation);
2299 #endif
2300
2301 int before_size = p->next_insn_offset - start_offset;
2302 brw_compact_instructions(p, start_offset, annotation.ann_count,
2303 annotation.ann);
2304 int after_size = p->next_insn_offset - start_offset;
2305
2306 if (unlikely(debug_flag)) {
2307 fprintf(stderr, "Native code for %s\n"
2308 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2309 " bytes (%.0f%%)\n",
2310 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2311 spill_count, fill_count, promoted_constants, before_size, after_size,
2312 100.0f * (before_size - after_size) / before_size);
2313
2314 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2315 p->devinfo);
2316 ralloc_free(annotation.mem_ctx);
2317 }
2318 assert(validated);
2319
2320 compiler->shader_debug_log(log_data,
2321 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2322 "%d:%d spills:fills, Promoted %u constants, "
2323 "compacted %d to %d bytes.",
2324 _mesa_shader_stage_to_abbrev(stage),
2325 dispatch_width, before_size / 16,
2326 loop_count, cfg->cycle_count, spill_count,
2327 fill_count, promoted_constants, before_size,
2328 after_size);
2329
2330 return start_offset;
2331 }
2332
2333 const unsigned *
2334 fs_generator::get_assembly(unsigned int *assembly_size)
2335 {
2336 return brw_get_program(p, assembly_size);
2337 }