projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Merge remote-tracking branch 'jekstrand/wip/i965-uniforms' into vulkan
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else if (inst->exec_size < 8) {
69 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
70 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
71 inst->exec_size, reg->stride);
72 } else {
73 /* From the Haswell PRM:
74 *
75 * VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
77 * boundaries.
78 *
79 * So, for registers with width > 8, we have to use a width of 8
80 * and trust the compression state to sort out the exec size.
81 */
82 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
83 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
84 }
85
86 brw_reg = retype(brw_reg, reg->type);
87 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
88 brw_reg.abs = reg->abs;
89 brw_reg.negate = reg->negate;
90 break;
91 case ARF:
92 case FIXED_GRF:
93 case IMM:
94 brw_reg = reg->as_brw_reg();
95 break;
96 case BAD_FILE:
97 /* Probably unused. */
98 brw_reg = brw_null_reg();
99 break;
100 case ATTR:
101 case UNIFORM:
102 unreachable("not reached");
103 }
104
105 return brw_reg;
106 }
107
108 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
109 void *mem_ctx,
110 const void *key,
111 struct brw_stage_prog_data *prog_data,
112 unsigned promoted_constants,
113 bool runtime_check_aads_emit,
114 gl_shader_stage stage)
115
116 : compiler(compiler), log_data(log_data),
117 devinfo(compiler->devinfo), key(key),
118 prog_data(prog_data),
119 promoted_constants(promoted_constants),
120 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
121 stage(stage), mem_ctx(mem_ctx)
122 {
123 p = rzalloc(mem_ctx, struct brw_codegen);
124 brw_init_codegen(devinfo, p, mem_ctx);
125 }
126
127 fs_generator::~fs_generator()
128 {
129 }
130
131 class ip_record : public exec_node {
132 public:
133 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
134
135 ip_record(int ip)
136 {
137 this->ip = ip;
138 }
139
140 int ip;
141 };
142
143 bool
144 fs_generator::patch_discard_jumps_to_fb_writes()
145 {
146 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
147 return false;
148
149 int scale = brw_jump_scale(p->devinfo);
150
151 /* There is a somewhat strange undocumented requirement of using
152 * HALT, according to the simulator. If some channel has HALTed to
153 * a particular UIP, then by the end of the program, every channel
154 * must have HALTed to that UIP. Furthermore, the tracking is a
155 * stack, so you can't do the final halt of a UIP after starting
156 * halting to a new UIP.
157 *
158 * Symptoms of not emitting this instruction on actual hardware
159 * included GPU hangs and sparkly rendering on the piglit discard
160 * tests.
161 */
162 brw_inst *last_halt = gen6_HALT(p);
163 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
164 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
165
166 int ip = p->nr_insn;
167
168 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
169 brw_inst *patch = &p->store[patch_ip->ip];
170
171 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
172 /* HALT takes a half-instruction distance from the pre-incremented IP. */
173 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
174 }
175
176 this->discard_halt_patches.make_empty();
177 return true;
178 }
179
180 void
181 fs_generator::fire_fb_write(fs_inst *inst,
182 struct brw_reg payload,
183 struct brw_reg implied_header,
184 GLuint nr)
185 {
186 uint32_t msg_control;
187
188 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
189
190 if (devinfo->gen < 6) {
191 brw_push_insn_state(p);
192 brw_set_default_exec_size(p, BRW_EXECUTE_8);
193 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
194 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
195 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
196 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
197 brw_pop_insn_state(p);
198 }
199
200 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
201 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
202 else if (prog_data->dual_src_blend) {
203 if (!inst->force_sechalf)
204 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
205 else
206 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
207 } else if (inst->exec_size == 16)
208 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
209 else
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
211
212 uint32_t surf_index =
213 prog_data->binding_table.render_target_start + inst->target;
214
215 bool last_render_target = inst->eot ||
216 (prog_data->dual_src_blend && dispatch_width == 16);
217
218
219 brw_fb_WRITE(p,
220 dispatch_width,
221 payload,
222 implied_header,
223 msg_control,
224 surf_index,
225 nr,
226 0,
227 inst->eot,
228 last_render_target,
229 inst->header_size != 0);
230
231 brw_mark_surface_used(&prog_data->base, surf_index);
232 }
233
234 void
235 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
236 {
237 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
238 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
239 struct brw_reg implied_header;
240
241 if (devinfo->gen < 8 && !devinfo->is_haswell) {
242 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
243 }
244
245 if (inst->base_mrf >= 0)
246 payload = brw_message_reg(inst->base_mrf);
247
248 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
249 * move, here's g1.
250 */
251 if (inst->header_size != 0) {
252 brw_push_insn_state(p);
253 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
254 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
255 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
256 brw_set_default_flag_reg(p, 0, 0);
257
258 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
259 * present.
260 */
261 if (prog_data->uses_kill) {
262 struct brw_reg pixel_mask;
263
264 if (devinfo->gen >= 6)
265 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
266 else
267 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
268
269 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
270 }
271
272 if (devinfo->gen >= 6) {
273 brw_push_insn_state(p);
274 brw_set_default_exec_size(p, BRW_EXECUTE_16);
275 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
276 brw_MOV(p,
277 retype(payload, BRW_REGISTER_TYPE_UD),
278 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
279 brw_pop_insn_state(p);
280
281 if (inst->target > 0 && key->replicate_alpha) {
282 /* Set "Source0 Alpha Present to RenderTarget" bit in message
283 * header.
284 */
285 brw_OR(p,
286 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
287 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
288 brw_imm_ud(0x1 << 11));
289 }
290
291 if (inst->target > 0) {
292 /* Set the render target index for choosing BLEND_STATE. */
293 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
294 BRW_REGISTER_TYPE_UD),
295 brw_imm_ud(inst->target));
296 }
297
298 /* Set computes stencil to render target */
299 if (prog_data->computed_stencil) {
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 14));
304 }
305
306 implied_header = brw_null_reg();
307 } else {
308 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
309 }
310
311 brw_pop_insn_state(p);
312 } else {
313 implied_header = brw_null_reg();
314 }
315
316 if (!runtime_check_aads_emit) {
317 fire_fb_write(inst, payload, implied_header, inst->mlen);
318 } else {
319 /* This can only happen in gen < 6 */
320 assert(devinfo->gen < 6);
321
322 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
323
324 /* Check runtime bit to detect if we have to send AA data or not */
325 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
326 brw_AND(p,
327 v1_null_ud,
328 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
329 brw_imm_ud(1<<26));
330 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
331
332 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
333 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
334 {
335 /* Don't send AA data */
336 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
337 }
338 brw_land_fwd_jump(p, jmp);
339 fire_fb_write(inst, payload, implied_header, inst->mlen);
340 }
341 }
342
343 void
344 fs_generator::generate_mov_indirect(fs_inst *inst,
345 struct brw_reg dst,
346 struct brw_reg reg,
347 struct brw_reg indirect_byte_offset)
348 {
349 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
350 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
351
352 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
353
354 if (indirect_byte_offset.file == BRW_IMMEDIATE_VALUE) {
355 imm_byte_offset += indirect_byte_offset.ud;
356
357 reg.nr = imm_byte_offset / REG_SIZE;
358 reg.subnr = imm_byte_offset % REG_SIZE;
359 brw_MOV(p, dst, reg);
360 } else {
361 /* Prior to Broadwell, there are only 8 address registers. */
362 assert(inst->exec_size == 8 || devinfo->gen >= 8);
363
364 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
365 struct brw_reg addr = vec8(brw_address_reg(0));
366
367 /* The destination stride of an instruction (in bytes) must be greater
368 * than or equal to the size of the rest of the instruction. Since the
369 * address register is of type UW, we can't use a D-type instruction.
370 * In order to get around this, re re-type to UW and use a stride.
371 */
372 indirect_byte_offset =
373 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
374
375 if (devinfo->gen < 8) {
376 /* Prior to broadwell, we have a restriction that the bottom 5 bits
377 * of the base offset and the bottom 5 bits of the indirect must add
378 * to less than 32. In other words, the hardware needs to be able to
379 * add the bottom five bits of the two to get the subnumber and add
380 * the next 7 bits of each to get the actual register number. Since
381 * the indirect may cause us to cross a register boundary, this makes
382 * it almost useless. We could try and do something clever where we
383 * use a actual base offset if base_offset % 32 == 0 but that would
384 * mean we were generating different code depending on the base
385 * offset. Instead, for the sake of consistency, we'll just do the
386 * add ourselves.
387 */
388 brw_ADD(p, addr, indirect_byte_offset, brw_imm_uw(imm_byte_offset));
389 brw_MOV(p, dst, retype(brw_VxH_indirect(0, 0), dst.type));
390 } else {
391 brw_MOV(p, addr, indirect_byte_offset);
392 brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
393 }
394 }
395 }
396
397 void
398 fs_generator::generate_urb_read(fs_inst *inst,
399 struct brw_reg dst,
400 struct brw_reg header)
401 {
402 assert(header.file == BRW_GENERAL_REGISTER_FILE);
403 assert(header.type == BRW_REGISTER_TYPE_UD);
404
405 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
406 brw_set_dest(p, send, dst);
407 brw_set_src0(p, send, header);
408 brw_set_src1(p, send, brw_imm_ud(0u));
409
410 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
411 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
412
413 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
414 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
415
416 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
417 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
418 brw_inst_set_header_present(p->devinfo, send, true);
419 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
420 }
421
422 void
423 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
424 {
425 brw_inst *insn;
426
427 insn = brw_next_insn(p, BRW_OPCODE_SEND);
428
429 brw_set_dest(p, insn, brw_null_reg());
430 brw_set_src0(p, insn, payload);
431 brw_set_src1(p, insn, brw_imm_d(0));
432
433 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
434 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
435
436 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
437 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
438 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
439
440 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
441 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
442 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
443
444 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
445 brw_inst_set_rlen(p->devinfo, insn, 0);
446 brw_inst_set_eot(p->devinfo, insn, inst->eot);
447 brw_inst_set_header_present(p->devinfo, insn, true);
448 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
449 }
450
451 void
452 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
453 {
454 struct brw_inst *insn;
455
456 insn = brw_next_insn(p, BRW_OPCODE_SEND);
457
458 brw_set_dest(p, insn, brw_null_reg());
459 brw_set_src0(p, insn, payload);
460 brw_set_src1(p, insn, brw_imm_d(0));
461
462 /* Terminate a compute shader by sending a message to the thread spawner.
463 */
464 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
465 brw_inst_set_mlen(devinfo, insn, 1);
466 brw_inst_set_rlen(devinfo, insn, 0);
467 brw_inst_set_eot(devinfo, insn, inst->eot);
468 brw_inst_set_header_present(devinfo, insn, false);
469
470 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
471 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
472
473 /* Note that even though the thread has a URB resource associated with it,
474 * we set the "do not dereference URB" bit, because the URB resource is
475 * managed by the fixed-function unit, so it will free it automatically.
476 */
477 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
478
479 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
480 }
481
482 void
483 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
484 struct brw_reg dst,
485 struct brw_reg src)
486 {
487 assert(dispatch_width == 8);
488 assert(devinfo->gen >= 9);
489
490 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
491 * Presumably, in order to save memory bandwidth, the stencil reference
492 * values written from the FS need to be packed into 2 dwords (this makes
493 * sense because the stencil values are limited to 1 byte each and a SIMD8
494 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
495 *
496 * The spec is confusing here because in the payload definition of MDP_RTW_S8
497 * (Message Data Payload for Render Target Writes with Stencil 8b) the
498 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
499 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
500 * packed values specified above and diagrammed below:
501 *
502 * 31 0
503 * --------------------------------
504 * DW | |
505 * 2-7 | IGNORED |
506 * | |
507 * --------------------------------
508 * DW1 | STC | STC | STC | STC |
509 * | slot7 | slot6 | slot5 | slot4|
510 * --------------------------------
511 * DW0 | STC | STC | STC | STC |
512 * | slot3 | slot2 | slot1 | slot0|
513 * --------------------------------
514 */
515
516 src.vstride = BRW_VERTICAL_STRIDE_4;
517 src.width = BRW_WIDTH_1;
518 src.hstride = BRW_HORIZONTAL_STRIDE_0;
519 assert(src.type == BRW_REGISTER_TYPE_UB);
520 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
521 }
522
523 void
524 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
525 {
526 brw_barrier(p, src);
527 brw_WAIT(p);
528 }
529
530 void
531 fs_generator::generate_blorp_fb_write(fs_inst *inst)
532 {
533 brw_fb_WRITE(p,
534 16 /* dispatch_width */,
535 brw_message_reg(inst->base_mrf),
536 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
537 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
538 inst->target,
539 inst->mlen,
540 0,
541 true,
542 true,
543 inst->header_size != 0);
544 }
545
546 void
547 fs_generator::generate_linterp(fs_inst *inst,
548 struct brw_reg dst, struct brw_reg *src)
549 {
550 /* PLN reads:
551 * / in SIMD16 \
552 * -----------------------------------
553 * | src1+0 | src1+1 | src1+2 | src1+3 |
554 * |-----------------------------------|
555 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
556 * -----------------------------------
557 *
558 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
559 *
560 * -----------------------------------
561 * | src1+0 | src1+1 | src1+2 | src1+3 |
562 * |-----------------------------------|
563 * |(x0, x1)|(y0, y1)| | | in SIMD8
564 * |-----------------------------------|
565 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
566 * -----------------------------------
567 *
568 * See also: emit_interpolation_setup_gen4().
569 */
570 struct brw_reg delta_x = src[0];
571 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
572 struct brw_reg interp = src[1];
573
574 if (devinfo->has_pln &&
575 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
576 brw_PLN(p, dst, interp, delta_x);
577 } else {
578 brw_LINE(p, brw_null_reg(), interp, delta_x);
579 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
580 }
581 }
582
583 void
584 fs_generator::generate_math_gen6(fs_inst *inst,
585 struct brw_reg dst,
586 struct brw_reg src0,
587 struct brw_reg src1)
588 {
589 int op = brw_math_function(inst->opcode);
590 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
591
592 if (dispatch_width == 8) {
593 gen6_math(p, dst, op, src0, src1);
594 } else if (dispatch_width == 16) {
595 brw_push_insn_state(p);
596 brw_set_default_exec_size(p, BRW_EXECUTE_8);
597 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
598 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
599 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
600 gen6_math(p, sechalf(dst), op, sechalf(src0),
601 binop ? sechalf(src1) : brw_null_reg());
602 brw_pop_insn_state(p);
603 }
604 }
605
606 void
607 fs_generator::generate_math_gen4(fs_inst *inst,
608 struct brw_reg dst,
609 struct brw_reg src)
610 {
611 int op = brw_math_function(inst->opcode);
612
613 assert(inst->mlen >= 1);
614
615 if (dispatch_width == 8) {
616 gen4_math(p, dst,
617 op,
618 inst->base_mrf, src,
619 BRW_MATH_PRECISION_FULL);
620 } else if (dispatch_width == 16) {
621 brw_set_default_exec_size(p, BRW_EXECUTE_8);
622 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
623 gen4_math(p, firsthalf(dst),
624 op,
625 inst->base_mrf, firsthalf(src),
626 BRW_MATH_PRECISION_FULL);
627 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
628 gen4_math(p, sechalf(dst),
629 op,
630 inst->base_mrf + 1, sechalf(src),
631 BRW_MATH_PRECISION_FULL);
632
633 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
634 }
635 }
636
637 void
638 fs_generator::generate_math_g45(fs_inst *inst,
639 struct brw_reg dst,
640 struct brw_reg src)
641 {
642 if (inst->opcode == SHADER_OPCODE_POW ||
643 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
644 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
645 generate_math_gen4(inst, dst, src);
646 return;
647 }
648
649 int op = brw_math_function(inst->opcode);
650
651 assert(inst->mlen >= 1);
652
653 gen4_math(p, dst,
654 op,
655 inst->base_mrf, src,
656 BRW_MATH_PRECISION_FULL);
657 }
658
659 void
660 fs_generator::generate_get_buffer_size(fs_inst *inst,
661 struct brw_reg dst,
662 struct brw_reg src,
663 struct brw_reg surf_index)
664 {
665 assert(devinfo->gen >= 7);
666 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
667
668 uint32_t simd_mode;
669 int rlen = 4;
670
671 switch (inst->exec_size) {
672 case 8:
673 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
674 break;
675 case 16:
676 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
677 break;
678 default:
679 unreachable("Invalid width for texture instruction");
680 }
681
682 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
683 rlen = 8;
684 dst = vec16(dst);
685 }
686
687 brw_SAMPLE(p,
688 retype(dst, BRW_REGISTER_TYPE_UW),
689 inst->base_mrf,
690 src,
691 surf_index.ud,
692 0,
693 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
694 rlen, /* response length */
695 inst->mlen,
696 inst->header_size > 0,
697 simd_mode,
698 BRW_SAMPLER_RETURN_FORMAT_SINT32);
699
700 brw_mark_surface_used(prog_data, surf_index.ud);
701 }
702
703 void
704 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
705 struct brw_reg surface_index,
706 struct brw_reg sampler_index)
707 {
708 int msg_type = -1;
709 int rlen = 4;
710 uint32_t simd_mode;
711 uint32_t return_format;
712 bool is_combined_send = inst->eot;
713
714 switch (dst.type) {
715 case BRW_REGISTER_TYPE_D:
716 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
717 break;
718 case BRW_REGISTER_TYPE_UD:
719 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
720 break;
721 default:
722 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
723 break;
724 }
725
726 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
727 * is set as part of the message descriptor. On gen4, the PRM seems to
728 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
729 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
730 * gone from the message descriptor entirely and you just get UINT32 all
731 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
732 * just stomp it to UINT32 all the time.
733 */
734 if (inst->opcode == SHADER_OPCODE_TXS)
735 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
736
737 switch (inst->exec_size) {
738 case 8:
739 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
740 break;
741 case 16:
742 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
743 break;
744 default:
745 unreachable("Invalid width for texture instruction");
746 }
747
748 if (devinfo->gen >= 5) {
749 switch (inst->opcode) {
750 case SHADER_OPCODE_TEX:
751 if (inst->shadow_compare) {
752 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
753 } else {
754 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
755 }
756 break;
757 case FS_OPCODE_TXB:
758 if (inst->shadow_compare) {
759 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
760 } else {
761 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
762 }
763 break;
764 case SHADER_OPCODE_TXL:
765 if (inst->shadow_compare) {
766 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
767 } else {
768 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
769 }
770 break;
771 case SHADER_OPCODE_TXS:
772 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
773 break;
774 case SHADER_OPCODE_TXD:
775 if (inst->shadow_compare) {
776 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
777 assert(devinfo->gen >= 8 || devinfo->is_haswell);
778 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
779 } else {
780 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
781 }
782 break;
783 case SHADER_OPCODE_TXF:
784 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
785 break;
786 case SHADER_OPCODE_TXF_CMS_W:
787 assert(devinfo->gen >= 9);
788 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
789 break;
790 case SHADER_OPCODE_TXF_CMS:
791 if (devinfo->gen >= 7)
792 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
793 else
794 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
795 break;
796 case SHADER_OPCODE_TXF_UMS:
797 assert(devinfo->gen >= 7);
798 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
799 break;
800 case SHADER_OPCODE_TXF_MCS:
801 assert(devinfo->gen >= 7);
802 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
803 break;
804 case SHADER_OPCODE_LOD:
805 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
806 break;
807 case SHADER_OPCODE_TG4:
808 if (inst->shadow_compare) {
809 assert(devinfo->gen >= 7);
810 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
811 } else {
812 assert(devinfo->gen >= 6);
813 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
814 }
815 break;
816 case SHADER_OPCODE_TG4_OFFSET:
817 assert(devinfo->gen >= 7);
818 if (inst->shadow_compare) {
819 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
820 } else {
821 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
822 }
823 break;
824 case SHADER_OPCODE_SAMPLEINFO:
825 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
826 break;
827 default:
828 unreachable("not reached");
829 }
830 } else {
831 switch (inst->opcode) {
832 case SHADER_OPCODE_TEX:
833 /* Note that G45 and older determines shadow compare and dispatch width
834 * from message length for most messages.
835 */
836 if (inst->exec_size == 8) {
837 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
838 if (inst->shadow_compare) {
839 assert(inst->mlen == 6);
840 } else {
841 assert(inst->mlen <= 4);
842 }
843 } else {
844 if (inst->shadow_compare) {
845 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
846 assert(inst->mlen == 9);
847 } else {
848 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
849 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
850 }
851 }
852 break;
853 case FS_OPCODE_TXB:
854 if (inst->shadow_compare) {
855 assert(inst->exec_size == 8);
856 assert(inst->mlen == 6);
857 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
858 } else {
859 assert(inst->mlen == 9);
860 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
861 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
862 }
863 break;
864 case SHADER_OPCODE_TXL:
865 if (inst->shadow_compare) {
866 assert(inst->exec_size == 8);
867 assert(inst->mlen == 6);
868 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
869 } else {
870 assert(inst->mlen == 9);
871 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
872 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
873 }
874 break;
875 case SHADER_OPCODE_TXD:
876 /* There is no sample_d_c message; comparisons are done manually */
877 assert(inst->exec_size == 8);
878 assert(inst->mlen == 7 || inst->mlen == 10);
879 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
880 break;
881 case SHADER_OPCODE_TXF:
882 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
883 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
884 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
885 break;
886 case SHADER_OPCODE_TXS:
887 assert(inst->mlen == 3);
888 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
889 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
890 break;
891 default:
892 unreachable("not reached");
893 }
894 }
895 assert(msg_type != -1);
896
897 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
898 rlen = 8;
899 dst = vec16(dst);
900 }
901
902 if (is_combined_send) {
903 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
904 rlen = 0;
905 }
906
907 assert(devinfo->gen < 7 || inst->header_size == 0 ||
908 src.file == BRW_GENERAL_REGISTER_FILE);
909
910 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
911
912 /* Load the message header if present. If there's a texture offset,
913 * we need to set it up explicitly and load the offset bitfield.
914 * Otherwise, we can use an implied move from g0 to the first message reg.
915 */
916 if (inst->header_size != 0) {
917 if (devinfo->gen < 6 && !inst->offset) {
918 /* Set up an implied move from g0 to the MRF. */
919 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
920 } else {
921 struct brw_reg header_reg;
922
923 if (devinfo->gen >= 7) {
924 header_reg = src;
925 } else {
926 assert(inst->base_mrf != -1);
927 header_reg = brw_message_reg(inst->base_mrf);
928 }
929
930 brw_push_insn_state(p);
931 brw_set_default_exec_size(p, BRW_EXECUTE_8);
932 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
933 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
934 /* Explicitly set up the message header by copying g0 to the MRF. */
935 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
936
937 if (inst->offset) {
938 /* Set the offset bits in DWord 2. */
939 brw_MOV(p, get_element_ud(header_reg, 2),
940 brw_imm_ud(inst->offset));
941 } else if (stage != MESA_SHADER_VERTEX &&
942 stage != MESA_SHADER_FRAGMENT) {
943 /* The vertex and fragment stages have g0.2 set to 0, so
944 * header0.2 is 0 when g0 is copied. Other stages may not, so we
945 * must set it to 0 to avoid setting undesirable bits in the
946 * message.
947 */
948 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
949 }
950
951 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
952 brw_pop_insn_state(p);
953 }
954 }
955
956 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
957 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
958 ? prog_data->binding_table.gather_texture_start
959 : prog_data->binding_table.texture_start;
960
961 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
962 sampler_index.file == BRW_IMMEDIATE_VALUE) {
963 uint32_t surface = surface_index.ud;
964 uint32_t sampler = sampler_index.ud;
965
966 brw_SAMPLE(p,
967 retype(dst, BRW_REGISTER_TYPE_UW),
968 inst->base_mrf,
969 src,
970 surface + base_binding_table_index,
971 sampler % 16,
972 msg_type,
973 rlen,
974 inst->mlen,
975 inst->header_size != 0,
976 simd_mode,
977 return_format);
978
979 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
980 } else {
981 /* Non-const sampler index */
982
983 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
984 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
985 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
986
987 brw_push_insn_state(p);
988 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
989 brw_set_default_access_mode(p, BRW_ALIGN_1);
990
991 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
992 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
993 } else {
994 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
995 brw_OR(p, addr, addr, surface_reg);
996 }
997 if (base_binding_table_index)
998 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
999 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
1000
1001 brw_pop_insn_state(p);
1002
1003 /* dst = send(offset, a0.0 | <descriptor>) */
1004 brw_inst *insn = brw_send_indirect_message(
1005 p, BRW_SFID_SAMPLER, dst, src, addr);
1006 brw_set_sampler_message(p, insn,
1007 0 /* surface */,
1008 0 /* sampler */,
1009 msg_type,
1010 rlen,
1011 inst->mlen /* mlen */,
1012 inst->header_size != 0 /* header */,
1013 simd_mode,
1014 return_format);
1015
1016 /* visitor knows more than we do about the surface limit required,
1017 * so has already done marking.
1018 */
1019 }
1020
1021 if (is_combined_send) {
1022 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
1023 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
1024 }
1025 }
1026
1027
1028 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1029 * looking like:
1030 *
1031 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1032 *
1033 * Ideally, we want to produce:
1034 *
1035 * DDX DDY
1036 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1037 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1038 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1039 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1040 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1041 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1042 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1043 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1044 *
1045 * and add another set of two more subspans if in 16-pixel dispatch mode.
1046 *
1047 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1048 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1049 * pair. But the ideal approximation may impose a huge performance cost on
1050 * sample_d. On at least Haswell, sample_d instruction does some
1051 * optimizations if the same LOD is used for all pixels in the subspan.
1052 *
1053 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1054 * appropriate swizzling.
1055 */
1056 void
1057 fs_generator::generate_ddx(enum opcode opcode,
1058 struct brw_reg dst, struct brw_reg src)
1059 {
1060 unsigned vstride, width;
1061
1062 if (opcode == FS_OPCODE_DDX_FINE) {
1063 /* produce accurate derivatives */
1064 vstride = BRW_VERTICAL_STRIDE_2;
1065 width = BRW_WIDTH_2;
1066 } else {
1067 /* replicate the derivative at the top-left pixel to other pixels */
1068 vstride = BRW_VERTICAL_STRIDE_4;
1069 width = BRW_WIDTH_4;
1070 }
1071
1072 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1073 src.negate, src.abs,
1074 BRW_REGISTER_TYPE_F,
1075 vstride,
1076 width,
1077 BRW_HORIZONTAL_STRIDE_0,
1078 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1079 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1080 src.negate, src.abs,
1081 BRW_REGISTER_TYPE_F,
1082 vstride,
1083 width,
1084 BRW_HORIZONTAL_STRIDE_0,
1085 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1086 brw_ADD(p, dst, src0, negate(src1));
1087 }
1088
1089 /* The negate_value boolean is used to negate the derivative computation for
1090 * FBOs, since they place the origin at the upper left instead of the lower
1091 * left.
1092 */
1093 void
1094 fs_generator::generate_ddy(enum opcode opcode,
1095 struct brw_reg dst, struct brw_reg src,
1096 bool negate_value)
1097 {
1098 if (opcode == FS_OPCODE_DDY_FINE) {
1099 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1100 * Region Restrictions):
1101 *
1102 * In Align16 access mode, SIMD16 is not allowed for DW operations
1103 * and SIMD8 is not allowed for DF operations.
1104 *
1105 * In this context, "DW operations" means "operations acting on 32-bit
1106 * values", so it includes operations on floats.
1107 *
1108 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1109 * (Instruction Compression -> Rules and Restrictions):
1110 *
1111 * A compressed instruction must be in Align1 access mode. Align16
1112 * mode instructions cannot be compressed.
1113 *
1114 * Similar text exists in the g45 PRM.
1115 *
1116 * On these platforms, if we're building a SIMD16 shader, we need to
1117 * manually unroll to a pair of SIMD8 instructions.
1118 */
1119 bool unroll_to_simd8 =
1120 (dispatch_width == 16 &&
1121 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1122
1123 /* produce accurate derivatives */
1124 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1125 src.negate, src.abs,
1126 BRW_REGISTER_TYPE_F,
1127 BRW_VERTICAL_STRIDE_4,
1128 BRW_WIDTH_4,
1129 BRW_HORIZONTAL_STRIDE_1,
1130 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1131 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1132 src.negate, src.abs,
1133 BRW_REGISTER_TYPE_F,
1134 BRW_VERTICAL_STRIDE_4,
1135 BRW_WIDTH_4,
1136 BRW_HORIZONTAL_STRIDE_1,
1137 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1138 brw_push_insn_state(p);
1139 brw_set_default_access_mode(p, BRW_ALIGN_16);
1140 if (unroll_to_simd8) {
1141 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1142 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1143 if (negate_value) {
1144 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1145 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1146 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1147 } else {
1148 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1149 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1150 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1151 }
1152 } else {
1153 if (negate_value)
1154 brw_ADD(p, dst, src1, negate(src0));
1155 else
1156 brw_ADD(p, dst, src0, negate(src1));
1157 }
1158 brw_pop_insn_state(p);
1159 } else {
1160 /* replicate the derivative at the top-left pixel to other pixels */
1161 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1162 src.negate, src.abs,
1163 BRW_REGISTER_TYPE_F,
1164 BRW_VERTICAL_STRIDE_4,
1165 BRW_WIDTH_4,
1166 BRW_HORIZONTAL_STRIDE_0,
1167 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1168 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1169 src.negate, src.abs,
1170 BRW_REGISTER_TYPE_F,
1171 BRW_VERTICAL_STRIDE_4,
1172 BRW_WIDTH_4,
1173 BRW_HORIZONTAL_STRIDE_0,
1174 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1175 if (negate_value)
1176 brw_ADD(p, dst, src1, negate(src0));
1177 else
1178 brw_ADD(p, dst, src0, negate(src1));
1179 }
1180 }
1181
1182 void
1183 fs_generator::generate_discard_jump(fs_inst *inst)
1184 {
1185 assert(devinfo->gen >= 6);
1186
1187 /* This HALT will be patched up at FB write time to point UIP at the end of
1188 * the program, and at brw_uip_jip() JIP will be set to the end of the
1189 * current block (or the program).
1190 */
1191 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1192
1193 brw_push_insn_state(p);
1194 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1195 gen6_HALT(p);
1196 brw_pop_insn_state(p);
1197 }
1198
1199 void
1200 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1201 {
1202 assert(inst->mlen != 0);
1203
1204 brw_MOV(p,
1205 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1206 retype(src, BRW_REGISTER_TYPE_UD));
1207 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1208 inst->exec_size / 8, inst->offset);
1209 }
1210
1211 void
1212 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1213 {
1214 assert(inst->mlen != 0);
1215
1216 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1217 inst->exec_size / 8, inst->offset);
1218 }
1219
1220 void
1221 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1222 {
1223 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1224 }
1225
1226 void
1227 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1228 struct brw_reg dst,
1229 struct brw_reg index,
1230 struct brw_reg offset)
1231 {
1232 assert(inst->mlen != 0);
1233
1234 assert(index.file == BRW_IMMEDIATE_VALUE &&
1235 index.type == BRW_REGISTER_TYPE_UD);
1236 uint32_t surf_index = index.ud;
1237
1238 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1239 offset.type == BRW_REGISTER_TYPE_UD);
1240 uint32_t read_offset = offset.ud;
1241
1242 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1243 read_offset, surf_index);
1244 }
1245
1246 void
1247 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1248 struct brw_reg dst,
1249 struct brw_reg index,
1250 struct brw_reg offset)
1251 {
1252 assert(index.type == BRW_REGISTER_TYPE_UD);
1253
1254 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1255 /* Reference just the dword we need, to avoid angering validate_reg(). */
1256 offset = brw_vec1_grf(offset.nr, 0);
1257
1258 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1259 * the destination loaded consecutively from the same offset (which appears
1260 * in the first component, and the rest are ignored).
1261 */
1262 dst.width = BRW_WIDTH_4;
1263
1264 struct brw_reg src = offset;
1265 bool header_present = false;
1266
1267 if (devinfo->gen >= 9) {
1268 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1269 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1270 header_present = true;
1271
1272 brw_push_insn_state(p);
1273 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1274 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1275 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1276 brw_set_default_access_mode(p, BRW_ALIGN_1);
1277
1278 brw_MOV(p, get_element_ud(src, 2),
1279 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1280 brw_pop_insn_state(p);
1281 }
1282
1283 if (index.file == BRW_IMMEDIATE_VALUE) {
1284
1285 uint32_t surf_index = index.ud;
1286
1287 brw_push_insn_state(p);
1288 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1289 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1290 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1291 brw_pop_insn_state(p);
1292
1293 brw_set_dest(p, send, dst);
1294 brw_set_src0(p, send, src);
1295 brw_set_sampler_message(p, send,
1296 surf_index,
1297 0, /* LD message ignores sampler unit */
1298 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1299 1, /* rlen */
1300 inst->mlen,
1301 header_present,
1302 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1303 0);
1304 } else {
1305
1306 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1307
1308 brw_push_insn_state(p);
1309 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1310 brw_set_default_access_mode(p, BRW_ALIGN_1);
1311
1312 /* a0.0 = surf_index & 0xff */
1313 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1314 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1315 brw_set_dest(p, insn_and, addr);
1316 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1317 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1318
1319 /* dst = send(payload, a0.0 | <descriptor>) */
1320 brw_inst *insn = brw_send_indirect_message(
1321 p, BRW_SFID_SAMPLER, dst, src, addr);
1322 brw_set_sampler_message(p, insn,
1323 0,
1324 0, /* LD message ignores sampler unit */
1325 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1326 1, /* rlen */
1327 inst->mlen,
1328 header_present,
1329 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1330 0);
1331
1332 brw_pop_insn_state(p);
1333 }
1334 }
1335
1336 void
1337 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1338 struct brw_reg dst,
1339 struct brw_reg index,
1340 struct brw_reg offset)
1341 {
1342 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1343 assert(inst->header_size != 0);
1344 assert(inst->mlen);
1345
1346 assert(index.file == BRW_IMMEDIATE_VALUE &&
1347 index.type == BRW_REGISTER_TYPE_UD);
1348 uint32_t surf_index = index.ud;
1349
1350 uint32_t simd_mode, rlen, msg_type;
1351 if (dispatch_width == 16) {
1352 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1353 rlen = 8;
1354 } else {
1355 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1356 rlen = 4;
1357 }
1358
1359 if (devinfo->gen >= 5)
1360 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1361 else {
1362 /* We always use the SIMD16 message so that we only have to load U, and
1363 * not V or R.
1364 */
1365 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1366 assert(inst->mlen == 3);
1367 assert(inst->regs_written == 8);
1368 rlen = 8;
1369 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1370 }
1371
1372 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1373 BRW_REGISTER_TYPE_D);
1374 brw_MOV(p, offset_mrf, offset);
1375
1376 struct brw_reg header = brw_vec8_grf(0, 0);
1377 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1378
1379 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1380 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1381 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1382 brw_set_src0(p, send, header);
1383 if (devinfo->gen < 6)
1384 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1385
1386 /* Our surface is set up as floats, regardless of what actual data is
1387 * stored in it.
1388 */
1389 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1390 brw_set_sampler_message(p, send,
1391 surf_index,
1392 0, /* sampler (unused) */
1393 msg_type,
1394 rlen,
1395 inst->mlen,
1396 inst->header_size != 0,
1397 simd_mode,
1398 return_format);
1399 }
1400
1401 void
1402 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1403 struct brw_reg dst,
1404 struct brw_reg index,
1405 struct brw_reg offset)
1406 {
1407 assert(devinfo->gen >= 7);
1408 /* Varying-offset pull constant loads are treated as a normal expression on
1409 * gen7, so the fact that it's a send message is hidden at the IR level.
1410 */
1411 assert(inst->header_size == 0);
1412 assert(!inst->mlen);
1413 assert(index.type == BRW_REGISTER_TYPE_UD);
1414
1415 uint32_t simd_mode, rlen, mlen;
1416 if (dispatch_width == 16) {
1417 mlen = 2;
1418 rlen = 8;
1419 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1420 } else {
1421 mlen = 1;
1422 rlen = 4;
1423 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1424 }
1425
1426 if (index.file == BRW_IMMEDIATE_VALUE) {
1427
1428 uint32_t surf_index = index.ud;
1429
1430 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1431 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1432 brw_set_src0(p, send, offset);
1433 brw_set_sampler_message(p, send,
1434 surf_index,
1435 0, /* LD message ignores sampler unit */
1436 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1437 rlen,
1438 mlen,
1439 false, /* no header */
1440 simd_mode,
1441 0);
1442
1443 } else {
1444
1445 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1446
1447 brw_push_insn_state(p);
1448 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1449 brw_set_default_access_mode(p, BRW_ALIGN_1);
1450
1451 /* a0.0 = surf_index & 0xff */
1452 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1453 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1454 brw_set_dest(p, insn_and, addr);
1455 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1456 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1457
1458 brw_pop_insn_state(p);
1459
1460 /* dst = send(offset, a0.0 | <descriptor>) */
1461 brw_inst *insn = brw_send_indirect_message(
1462 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1463 offset, addr);
1464 brw_set_sampler_message(p, insn,
1465 0 /* surface */,
1466 0 /* sampler */,
1467 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1468 rlen /* rlen */,
1469 mlen /* mlen */,
1470 false /* header */,
1471 simd_mode,
1472 0);
1473 }
1474 }
1475
1476 /**
1477 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1478 * into the flags register (f0.0).
1479 *
1480 * Used only on Gen6 and above.
1481 */
1482 void
1483 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1484 {
1485 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1486 struct brw_reg dispatch_mask;
1487
1488 if (devinfo->gen >= 6)
1489 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1490 else
1491 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1492
1493 brw_push_insn_state(p);
1494 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1495 brw_MOV(p, flags, dispatch_mask);
1496 brw_pop_insn_state(p);
1497 }
1498
1499 void
1500 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1501 struct brw_reg dst,
1502 struct brw_reg src,
1503 struct brw_reg msg_data,
1504 unsigned msg_type)
1505 {
1506 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1507
1508 brw_pixel_interpolator_query(p,
1509 retype(dst, BRW_REGISTER_TYPE_UW),
1510 src,
1511 inst->pi_noperspective,
1512 msg_type,
1513 msg_data,
1514 inst->mlen,
1515 inst->regs_written);
1516 }
1517
1518
1519 /**
1520 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1521 * sampler LD messages.
1522 *
1523 * We don't want to bake it into the send message's code generation because
1524 * that means we don't get a chance to schedule the instructions.
1525 */
1526 void
1527 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1528 struct brw_reg dst,
1529 struct brw_reg value)
1530 {
1531 assert(value.file == BRW_IMMEDIATE_VALUE);
1532
1533 brw_push_insn_state(p);
1534 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1535 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1536 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1537 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1538 brw_pop_insn_state(p);
1539 }
1540
1541 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1542 * the ADD instruction.
1543 */
1544 void
1545 fs_generator::generate_set_sample_id(fs_inst *inst,
1546 struct brw_reg dst,
1547 struct brw_reg src0,
1548 struct brw_reg src1)
1549 {
1550 assert(dst.type == BRW_REGISTER_TYPE_D ||
1551 dst.type == BRW_REGISTER_TYPE_UD);
1552 assert(src0.type == BRW_REGISTER_TYPE_D ||
1553 src0.type == BRW_REGISTER_TYPE_UD);
1554
1555 struct brw_reg reg = stride(src1, 1, 4, 0);
1556 if (devinfo->gen >= 8 || dispatch_width == 8) {
1557 brw_ADD(p, dst, src0, reg);
1558 } else if (dispatch_width == 16) {
1559 brw_push_insn_state(p);
1560 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1561 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1562 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1563 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1564 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1565 brw_pop_insn_state(p);
1566 }
1567 }
1568
1569 void
1570 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1571 struct brw_reg dst,
1572 struct brw_reg x,
1573 struct brw_reg y)
1574 {
1575 assert(devinfo->gen >= 7);
1576 assert(dst.type == BRW_REGISTER_TYPE_UD);
1577 assert(x.type == BRW_REGISTER_TYPE_F);
1578 assert(y.type == BRW_REGISTER_TYPE_F);
1579
1580 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1581 *
1582 * Because this instruction does not have a 16-bit floating-point type,
1583 * the destination data type must be Word (W).
1584 *
1585 * The destination must be DWord-aligned and specify a horizontal stride
1586 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1587 * each destination channel and the upper word is not modified.
1588 */
1589 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1590
1591 /* Give each 32-bit channel of dst the form below, where "." means
1592 * unchanged.
1593 * 0x....hhhh
1594 */
1595 brw_F32TO16(p, dst_w, y);
1596
1597 /* Now the form:
1598 * 0xhhhh0000
1599 */
1600 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1601
1602 /* And, finally the form of packHalf2x16's output:
1603 * 0xhhhhllll
1604 */
1605 brw_F32TO16(p, dst_w, x);
1606 }
1607
1608 void
1609 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1610 struct brw_reg dst,
1611 struct brw_reg src)
1612 {
1613 assert(devinfo->gen >= 7);
1614 assert(dst.type == BRW_REGISTER_TYPE_F);
1615 assert(src.type == BRW_REGISTER_TYPE_UD);
1616
1617 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1618 *
1619 * Because this instruction does not have a 16-bit floating-point type,
1620 * the source data type must be Word (W). The destination type must be
1621 * F (Float).
1622 */
1623 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1624
1625 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1626 * For the Y case, we wish to access only the upper word; therefore
1627 * a 16-bit subregister offset is needed.
1628 */
1629 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1630 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1631 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1632 src_w.subnr += 2;
1633
1634 brw_F16TO32(p, dst, src_w);
1635 }
1636
1637 void
1638 fs_generator::generate_shader_time_add(fs_inst *inst,
1639 struct brw_reg payload,
1640 struct brw_reg offset,
1641 struct brw_reg value)
1642 {
1643 assert(devinfo->gen >= 7);
1644 brw_push_insn_state(p);
1645 brw_set_default_mask_control(p, true);
1646
1647 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1648 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1649 offset.type);
1650 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1651 value.type);
1652
1653 assert(offset.file == BRW_IMMEDIATE_VALUE);
1654 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1655 value.width = BRW_WIDTH_1;
1656 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1657 value.vstride = BRW_VERTICAL_STRIDE_0;
1658 } else {
1659 assert(value.file == BRW_IMMEDIATE_VALUE);
1660 }
1661
1662 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1663 * case, and we don't really care about squeezing every bit of performance
1664 * out of this path, so we just emit the MOVs from here.
1665 */
1666 brw_MOV(p, payload_offset, offset);
1667 brw_MOV(p, payload_value, value);
1668 brw_shader_time_add(p, payload,
1669 prog_data->binding_table.shader_time_start);
1670 brw_pop_insn_state(p);
1671
1672 brw_mark_surface_used(prog_data,
1673 prog_data->binding_table.shader_time_start);
1674 }
1675
1676 void
1677 fs_generator::enable_debug(const char *shader_name)
1678 {
1679 debug_flag = true;
1680 this->shader_name = shader_name;
1681 }
1682
1683 int
1684 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1685 {
1686 /* align to 64 byte boundary. */
1687 while (p->next_insn_offset % 64)
1688 brw_NOP(p);
1689
1690 this->dispatch_width = dispatch_width;
1691 if (dispatch_width == 16)
1692 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1693
1694 int start_offset = p->next_insn_offset;
1695 int spill_count = 0, fill_count = 0;
1696 int loop_count = 0;
1697
1698 struct annotation_info annotation;
1699 memset(&annotation, 0, sizeof(annotation));
1700
1701 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1702 struct brw_reg src[3], dst;
1703 unsigned int last_insn_offset = p->next_insn_offset;
1704 bool multiple_instructions_emitted = false;
1705
1706 if (unlikely(debug_flag))
1707 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1708
1709 for (unsigned int i = 0; i < inst->sources; i++) {
1710 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1711
1712 /* The accumulator result appears to get used for the
1713 * conditional modifier generation. When negating a UD
1714 * value, there is a 33rd bit generated for the sign in the
1715 * accumulator value, so now you can't check, for example,
1716 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1717 */
1718 assert(!inst->conditional_mod ||
1719 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1720 !inst->src[i].negate);
1721 }
1722 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1723
1724 brw_set_default_predicate_control(p, inst->predicate);
1725 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1726 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1727 brw_set_default_saturate(p, inst->saturate);
1728 brw_set_default_mask_control(p, inst->force_writemask_all);
1729 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1730 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1731
1732 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1733 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1734
1735 switch (inst->exec_size) {
1736 case 1:
1737 case 2:
1738 case 4:
1739 assert(inst->force_writemask_all);
1740 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1741 break;
1742 case 8:
1743 if (inst->force_sechalf) {
1744 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1745 } else {
1746 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1747 }
1748 break;
1749 case 16:
1750 case 32:
1751 /* If the instruction writes to more than one register, it needs to
1752 * be a "compressed" instruction on Gen <= 5.
1753 */
1754 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1755 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1756 else
1757 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1758 break;
1759 default:
1760 unreachable("Invalid instruction width");
1761 }
1762
1763 switch (inst->opcode) {
1764 case BRW_OPCODE_MOV:
1765 brw_MOV(p, dst, src[0]);
1766 break;
1767 case BRW_OPCODE_ADD:
1768 brw_ADD(p, dst, src[0], src[1]);
1769 break;
1770 case BRW_OPCODE_MUL:
1771 brw_MUL(p, dst, src[0], src[1]);
1772 break;
1773 case BRW_OPCODE_AVG:
1774 brw_AVG(p, dst, src[0], src[1]);
1775 break;
1776 case BRW_OPCODE_MACH:
1777 brw_MACH(p, dst, src[0], src[1]);
1778 break;
1779
1780 case BRW_OPCODE_LINE:
1781 brw_LINE(p, dst, src[0], src[1]);
1782 break;
1783
1784 case BRW_OPCODE_MAD:
1785 assert(devinfo->gen >= 6);
1786 brw_set_default_access_mode(p, BRW_ALIGN_16);
1787 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1788 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1789 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1790 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1791 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1792 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1793 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1794
1795 if (inst->conditional_mod) {
1796 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1797 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1798 multiple_instructions_emitted = true;
1799 }
1800 } else {
1801 brw_MAD(p, dst, src[0], src[1], src[2]);
1802 }
1803 brw_set_default_access_mode(p, BRW_ALIGN_1);
1804 break;
1805
1806 case BRW_OPCODE_LRP:
1807 assert(devinfo->gen >= 6);
1808 brw_set_default_access_mode(p, BRW_ALIGN_16);
1809 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1810 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1811 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1812 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1813 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1814 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1815 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1816
1817 if (inst->conditional_mod) {
1818 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1819 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1820 multiple_instructions_emitted = true;
1821 }
1822 } else {
1823 brw_LRP(p, dst, src[0], src[1], src[2]);
1824 }
1825 brw_set_default_access_mode(p, BRW_ALIGN_1);
1826 break;
1827
1828 case BRW_OPCODE_FRC:
1829 brw_FRC(p, dst, src[0]);
1830 break;
1831 case BRW_OPCODE_RNDD:
1832 brw_RNDD(p, dst, src[0]);
1833 break;
1834 case BRW_OPCODE_RNDE:
1835 brw_RNDE(p, dst, src[0]);
1836 break;
1837 case BRW_OPCODE_RNDZ:
1838 brw_RNDZ(p, dst, src[0]);
1839 break;
1840
1841 case BRW_OPCODE_AND:
1842 brw_AND(p, dst, src[0], src[1]);
1843 break;
1844 case BRW_OPCODE_OR:
1845 brw_OR(p, dst, src[0], src[1]);
1846 break;
1847 case BRW_OPCODE_XOR:
1848 brw_XOR(p, dst, src[0], src[1]);
1849 break;
1850 case BRW_OPCODE_NOT:
1851 brw_NOT(p, dst, src[0]);
1852 break;
1853 case BRW_OPCODE_ASR:
1854 brw_ASR(p, dst, src[0], src[1]);
1855 break;
1856 case BRW_OPCODE_SHR:
1857 brw_SHR(p, dst, src[0], src[1]);
1858 break;
1859 case BRW_OPCODE_SHL:
1860 brw_SHL(p, dst, src[0], src[1]);
1861 break;
1862 case BRW_OPCODE_F32TO16:
1863 assert(devinfo->gen >= 7);
1864 brw_F32TO16(p, dst, src[0]);
1865 break;
1866 case BRW_OPCODE_F16TO32:
1867 assert(devinfo->gen >= 7);
1868 brw_F16TO32(p, dst, src[0]);
1869 break;
1870 case BRW_OPCODE_CMP:
1871 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1872 * that when the destination is a GRF that the dependency-clear bit on
1873 * the flag register is cleared early.
1874 *
1875 * Suggested workarounds are to disable coissuing CMP instructions
1876 * or to split CMP(16) instructions into two CMP(8) instructions.
1877 *
1878 * We choose to split into CMP(8) instructions since disabling
1879 * coissuing would affect CMP instructions not otherwise affected by
1880 * the errata.
1881 */
1882 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1883 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1884 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1885 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1886 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1887 firsthalf(src[0]), firsthalf(src[1]));
1888 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1889 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1890 sechalf(src[0]), sechalf(src[1]));
1891 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1892
1893 multiple_instructions_emitted = true;
1894 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1895 /* For unknown reasons, the aforementioned workaround is not
1896 * sufficient. Overriding the type when the destination is the
1897 * null register is necessary but not sufficient by itself.
1898 */
1899 assert(dst.nr == BRW_ARF_NULL);
1900 dst.type = BRW_REGISTER_TYPE_D;
1901 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1902 } else {
1903 unreachable("not reached");
1904 }
1905 } else {
1906 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1907 }
1908 break;
1909 case BRW_OPCODE_SEL:
1910 brw_SEL(p, dst, src[0], src[1]);
1911 break;
1912 case BRW_OPCODE_BFREV:
1913 assert(devinfo->gen >= 7);
1914 /* BFREV only supports UD type for src and dst. */
1915 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1916 retype(src[0], BRW_REGISTER_TYPE_UD));
1917 break;
1918 case BRW_OPCODE_FBH:
1919 assert(devinfo->gen >= 7);
1920 /* FBH only supports UD type for dst. */
1921 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1922 break;
1923 case BRW_OPCODE_FBL:
1924 assert(devinfo->gen >= 7);
1925 /* FBL only supports UD type for dst. */
1926 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1927 break;
1928 case BRW_OPCODE_CBIT:
1929 assert(devinfo->gen >= 7);
1930 /* CBIT only supports UD type for dst. */
1931 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1932 break;
1933 case BRW_OPCODE_ADDC:
1934 assert(devinfo->gen >= 7);
1935 brw_ADDC(p, dst, src[0], src[1]);
1936 break;
1937 case BRW_OPCODE_SUBB:
1938 assert(devinfo->gen >= 7);
1939 brw_SUBB(p, dst, src[0], src[1]);
1940 break;
1941 case BRW_OPCODE_MAC:
1942 brw_MAC(p, dst, src[0], src[1]);
1943 break;
1944
1945 case BRW_OPCODE_BFE:
1946 assert(devinfo->gen >= 7);
1947 brw_set_default_access_mode(p, BRW_ALIGN_16);
1948 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1949 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1950 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1951 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1952 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1953 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1954 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1955 } else {
1956 brw_BFE(p, dst, src[0], src[1], src[2]);
1957 }
1958 brw_set_default_access_mode(p, BRW_ALIGN_1);
1959 break;
1960
1961 case BRW_OPCODE_BFI1:
1962 assert(devinfo->gen >= 7);
1963 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1964 * should
1965 *
1966 * "Force BFI instructions to be executed always in SIMD8."
1967 */
1968 if (dispatch_width == 16 && devinfo->is_haswell) {
1969 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1970 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1971 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1972 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1973 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1974 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1975 } else {
1976 brw_BFI1(p, dst, src[0], src[1]);
1977 }
1978 break;
1979 case BRW_OPCODE_BFI2:
1980 assert(devinfo->gen >= 7);
1981 brw_set_default_access_mode(p, BRW_ALIGN_16);
1982 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1983 * should
1984 *
1985 * "Force BFI instructions to be executed always in SIMD8."
1986 *
1987 * Otherwise we would be able to emit compressed instructions like we
1988 * do for the other three-source instructions.
1989 */
1990 if (dispatch_width == 16 &&
1991 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1992 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1993 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1994 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1995 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1996 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1997 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1998 } else {
1999 brw_BFI2(p, dst, src[0], src[1], src[2]);
2000 }
2001 brw_set_default_access_mode(p, BRW_ALIGN_1);
2002 break;
2003
2004 case BRW_OPCODE_IF:
2005 if (inst->src[0].file != BAD_FILE) {
2006 /* The instruction has an embedded compare (only allowed on gen6) */
2007 assert(devinfo->gen == 6);
2008 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
2009 } else {
2010 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
2011 }
2012 break;
2013
2014 case BRW_OPCODE_ELSE:
2015 brw_ELSE(p);
2016 break;
2017 case BRW_OPCODE_ENDIF:
2018 brw_ENDIF(p);
2019 break;
2020
2021 case BRW_OPCODE_DO:
2022 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
2023 break;
2024
2025 case BRW_OPCODE_BREAK:
2026 brw_BREAK(p);
2027 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2028 break;
2029 case BRW_OPCODE_CONTINUE:
2030 brw_CONT(p);
2031 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2032 break;
2033
2034 case BRW_OPCODE_WHILE:
2035 brw_WHILE(p);
2036 loop_count++;
2037 break;
2038
2039 case SHADER_OPCODE_RCP:
2040 case SHADER_OPCODE_RSQ:
2041 case SHADER_OPCODE_SQRT:
2042 case SHADER_OPCODE_EXP2:
2043 case SHADER_OPCODE_LOG2:
2044 case SHADER_OPCODE_SIN:
2045 case SHADER_OPCODE_COS:
2046 assert(devinfo->gen < 6 || inst->mlen == 0);
2047 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2048 if (devinfo->gen >= 7) {
2049 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2050 brw_null_reg());
2051 } else if (devinfo->gen == 6) {
2052 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2053 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2054 generate_math_g45(inst, dst, src[0]);
2055 } else {
2056 generate_math_gen4(inst, dst, src[0]);
2057 }
2058 break;
2059 case SHADER_OPCODE_INT_QUOTIENT:
2060 case SHADER_OPCODE_INT_REMAINDER:
2061 case SHADER_OPCODE_POW:
2062 assert(devinfo->gen < 6 || inst->mlen == 0);
2063 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2064 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2065 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2066 } else if (devinfo->gen >= 6) {
2067 generate_math_gen6(inst, dst, src[0], src[1]);
2068 } else {
2069 generate_math_gen4(inst, dst, src[0]);
2070 }
2071 break;
2072 case FS_OPCODE_CINTERP:
2073 brw_MOV(p, dst, src[0]);
2074 break;
2075 case FS_OPCODE_LINTERP:
2076 generate_linterp(inst, dst, src);
2077 break;
2078 case FS_OPCODE_PIXEL_X:
2079 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2080 src[0].subnr = 0 * type_sz(src[0].type);
2081 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2082 break;
2083 case FS_OPCODE_PIXEL_Y:
2084 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2085 src[0].subnr = 4 * type_sz(src[0].type);
2086 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2087 break;
2088 case FS_OPCODE_GET_BUFFER_SIZE:
2089 generate_get_buffer_size(inst, dst, src[0], src[1]);
2090 break;
2091 case SHADER_OPCODE_TEX:
2092 case FS_OPCODE_TXB:
2093 case SHADER_OPCODE_TXD:
2094 case SHADER_OPCODE_TXF:
2095 case SHADER_OPCODE_TXF_CMS:
2096 case SHADER_OPCODE_TXF_CMS_W:
2097 case SHADER_OPCODE_TXF_UMS:
2098 case SHADER_OPCODE_TXF_MCS:
2099 case SHADER_OPCODE_TXL:
2100 case SHADER_OPCODE_TXS:
2101 case SHADER_OPCODE_LOD:
2102 case SHADER_OPCODE_TG4:
2103 case SHADER_OPCODE_TG4_OFFSET:
2104 case SHADER_OPCODE_SAMPLEINFO:
2105 generate_tex(inst, dst, src[0], src[1], src[2]);
2106 break;
2107 case FS_OPCODE_DDX_COARSE:
2108 case FS_OPCODE_DDX_FINE:
2109 generate_ddx(inst->opcode, dst, src[0]);
2110 break;
2111 case FS_OPCODE_DDY_COARSE:
2112 case FS_OPCODE_DDY_FINE:
2113 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2114 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2115 break;
2116
2117 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2118 generate_scratch_write(inst, src[0]);
2119 spill_count++;
2120 break;
2121
2122 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2123 generate_scratch_read(inst, dst);
2124 fill_count++;
2125 break;
2126
2127 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2128 generate_scratch_read_gen7(inst, dst);
2129 fill_count++;
2130 break;
2131
2132 case SHADER_OPCODE_MOV_INDIRECT:
2133 generate_mov_indirect(inst, dst, src[0], src[1]);
2134 break;
2135
2136 case SHADER_OPCODE_URB_READ_SIMD8:
2137 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2138 generate_urb_read(inst, dst, src[0]);
2139 break;
2140
2141 case SHADER_OPCODE_URB_WRITE_SIMD8:
2142 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2143 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2144 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2145 generate_urb_write(inst, src[0]);
2146 break;
2147
2148 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2149 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2150 break;
2151
2152 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2153 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2154 break;
2155
2156 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2157 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2158 break;
2159
2160 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2161 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2162 break;
2163
2164 case FS_OPCODE_REP_FB_WRITE:
2165 case FS_OPCODE_FB_WRITE:
2166 generate_fb_write(inst, src[0]);
2167 break;
2168
2169 case FS_OPCODE_BLORP_FB_WRITE:
2170 generate_blorp_fb_write(inst);
2171 break;
2172
2173 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2174 generate_mov_dispatch_to_flags(inst);
2175 break;
2176
2177 case FS_OPCODE_DISCARD_JUMP:
2178 generate_discard_jump(inst);
2179 break;
2180
2181 case SHADER_OPCODE_SHADER_TIME_ADD:
2182 generate_shader_time_add(inst, src[0], src[1], src[2]);
2183 break;
2184
2185 case SHADER_OPCODE_UNTYPED_ATOMIC:
2186 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2187 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2188 inst->mlen, !inst->dst.is_null());
2189 break;
2190
2191 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2192 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2193 brw_untyped_surface_read(p, dst, src[0], src[1],
2194 inst->mlen, src[2].ud);
2195 break;
2196
2197 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2198 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2199 brw_untyped_surface_write(p, src[0], src[1],
2200 inst->mlen, src[2].ud);
2201 break;
2202
2203 case SHADER_OPCODE_TYPED_ATOMIC:
2204 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2205 brw_typed_atomic(p, dst, src[0], src[1],
2206 src[2].ud, inst->mlen, !inst->dst.is_null());
2207 break;
2208
2209 case SHADER_OPCODE_TYPED_SURFACE_READ:
2210 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2211 brw_typed_surface_read(p, dst, src[0], src[1],
2212 inst->mlen, src[2].ud);
2213 break;
2214
2215 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2216 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2217 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2218 break;
2219
2220 case SHADER_OPCODE_MEMORY_FENCE:
2221 brw_memory_fence(p, dst);
2222 break;
2223
2224 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2225 generate_set_simd4x2_offset(inst, dst, src[0]);
2226 break;
2227
2228 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2229 brw_find_live_channel(p, dst);
2230 break;
2231
2232 case SHADER_OPCODE_BROADCAST:
2233 brw_broadcast(p, dst, src[0], src[1]);
2234 break;
2235
2236 case FS_OPCODE_SET_SAMPLE_ID:
2237 generate_set_sample_id(inst, dst, src[0], src[1]);
2238 break;
2239
2240 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2241 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2242 break;
2243
2244 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2245 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2246 generate_unpack_half_2x16_split(inst, dst, src[0]);
2247 break;
2248
2249 case FS_OPCODE_PLACEHOLDER_HALT:
2250 /* This is the place where the final HALT needs to be inserted if
2251 * we've emitted any discards. If not, this will emit no code.
2252 */
2253 if (!patch_discard_jumps_to_fb_writes()) {
2254 if (unlikely(debug_flag)) {
2255 annotation.ann_count--;
2256 }
2257 }
2258 break;
2259
2260 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2261 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2262 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2263 break;
2264
2265 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2266 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2267 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2268 break;
2269
2270 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2271 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2272 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2273 break;
2274
2275 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2276 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2277 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2278 break;
2279
2280 case CS_OPCODE_CS_TERMINATE:
2281 generate_cs_terminate(inst, src[0]);
2282 break;
2283
2284 case SHADER_OPCODE_BARRIER:
2285 generate_barrier(inst, src[0]);
2286 break;
2287
2288 case FS_OPCODE_PACK_STENCIL_REF:
2289 generate_stencil_ref_packing(inst, dst, src[0]);
2290 break;
2291
2292 default:
2293 unreachable("Unsupported opcode");
2294
2295 case SHADER_OPCODE_LOAD_PAYLOAD:
2296 unreachable("Should be lowered by lower_load_payload()");
2297 }
2298
2299 if (multiple_instructions_emitted)
2300 continue;
2301
2302 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2303 assert(p->next_insn_offset == last_insn_offset + 16 ||
2304 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2305 "emitting more than 1 instruction");
2306
2307 brw_inst *last = &p->store[last_insn_offset / 16];
2308
2309 if (inst->conditional_mod)
2310 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2311 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2312 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2313 }
2314 }
2315
2316 brw_set_uip_jip(p);
2317 annotation_finalize(&annotation, p->next_insn_offset);
2318
2319 #ifndef NDEBUG
2320 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2321 #else
2322 if (unlikely(debug_flag))
2323 brw_validate_instructions(p, start_offset, &annotation);
2324 #endif
2325
2326 int before_size = p->next_insn_offset - start_offset;
2327 brw_compact_instructions(p, start_offset, annotation.ann_count,
2328 annotation.ann);
2329 int after_size = p->next_insn_offset - start_offset;
2330
2331 if (unlikely(debug_flag)) {
2332 fprintf(stderr, "Native code for %s\n"
2333 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2334 " bytes (%.0f%%)\n",
2335 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2336 spill_count, fill_count, promoted_constants, before_size, after_size,
2337 100.0f * (before_size - after_size) / before_size);
2338
2339 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2340 p->devinfo);
2341 ralloc_free(annotation.mem_ctx);
2342 }
2343 assert(validated);
2344
2345 compiler->shader_debug_log(log_data,
2346 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2347 "%d:%d spills:fills, Promoted %u constants, "
2348 "compacted %d to %d bytes.",
2349 _mesa_shader_stage_to_abbrev(stage),
2350 dispatch_width, before_size / 16,
2351 loop_count, cfg->cycle_count, spill_count,
2352 fill_count, promoted_constants, before_size,
2353 after_size);
2354
2355 return start_offset;
2356 }
2357
2358 const unsigned *
2359 fs_generator::get_assembly(unsigned int *assembly_size)
2360 {
2361 return brw_get_program(p, assembly_size);
2362 }