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i965/fs: Separate the sampler from the surface in generate_tex
[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_generator.cpp
1 /*
2 * Copyright © 2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 /** @file brw_fs_generator.cpp
25 *
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
28 */
29
30 #include "brw_eu.h"
31 #include "brw_fs.h"
32 #include "brw_cfg.h"
33 #include "brw_program.h"
34
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg *reg)
37 {
38 switch (reg->file) {
39 case ARF:
40 return BRW_ARCHITECTURE_REGISTER_FILE;
41 case FIXED_GRF:
42 case VGRF:
43 return BRW_GENERAL_REGISTER_FILE;
44 case MRF:
45 return BRW_MESSAGE_REGISTER_FILE;
46 case IMM:
47 return BRW_IMMEDIATE_VALUE;
48 case BAD_FILE:
49 case ATTR:
50 case UNIFORM:
51 unreachable("not reached");
52 }
53 return BRW_ARCHITECTURE_REGISTER_FILE;
54 }
55
56 static struct brw_reg
57 brw_reg_from_fs_reg(fs_inst *inst, fs_reg *reg, unsigned gen)
58 {
59 struct brw_reg brw_reg;
60
61 switch (reg->file) {
62 case MRF:
63 assert((reg->nr & ~BRW_MRF_COMPR4) < BRW_MAX_MRF(gen));
64 /* Fallthrough */
65 case VGRF:
66 if (reg->stride == 0) {
67 brw_reg = brw_vec1_reg(brw_file_from_reg(reg), reg->nr, 0);
68 } else if (inst->exec_size < 8) {
69 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
70 brw_reg = stride(brw_reg, inst->exec_size * reg->stride,
71 inst->exec_size, reg->stride);
72 } else {
73 /* From the Haswell PRM:
74 *
75 * VertStride must be used to cross GRF register boundaries. This
76 * rule implies that elements within a 'Width' cannot cross GRF
77 * boundaries.
78 *
79 * So, for registers with width > 8, we have to use a width of 8
80 * and trust the compression state to sort out the exec size.
81 */
82 brw_reg = brw_vec8_reg(brw_file_from_reg(reg), reg->nr, 0);
83 brw_reg = stride(brw_reg, 8 * reg->stride, 8, reg->stride);
84 }
85
86 brw_reg = retype(brw_reg, reg->type);
87 brw_reg = byte_offset(brw_reg, reg->subreg_offset);
88 brw_reg.abs = reg->abs;
89 brw_reg.negate = reg->negate;
90 break;
91 case ARF:
92 case FIXED_GRF:
93 case IMM:
94 brw_reg = reg->as_brw_reg();
95 break;
96 case BAD_FILE:
97 /* Probably unused. */
98 brw_reg = brw_null_reg();
99 break;
100 case ATTR:
101 case UNIFORM:
102 unreachable("not reached");
103 }
104
105 return brw_reg;
106 }
107
108 fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
109 void *mem_ctx,
110 const void *key,
111 struct brw_stage_prog_data *prog_data,
112 unsigned promoted_constants,
113 bool runtime_check_aads_emit,
114 gl_shader_stage stage)
115
116 : compiler(compiler), log_data(log_data),
117 devinfo(compiler->devinfo), key(key),
118 prog_data(prog_data),
119 promoted_constants(promoted_constants),
120 runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
121 stage(stage), mem_ctx(mem_ctx)
122 {
123 p = rzalloc(mem_ctx, struct brw_codegen);
124 brw_init_codegen(devinfo, p, mem_ctx);
125 }
126
127 fs_generator::~fs_generator()
128 {
129 }
130
131 class ip_record : public exec_node {
132 public:
133 DECLARE_RALLOC_CXX_OPERATORS(ip_record)
134
135 ip_record(int ip)
136 {
137 this->ip = ip;
138 }
139
140 int ip;
141 };
142
143 bool
144 fs_generator::patch_discard_jumps_to_fb_writes()
145 {
146 if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
147 return false;
148
149 int scale = brw_jump_scale(p->devinfo);
150
151 /* There is a somewhat strange undocumented requirement of using
152 * HALT, according to the simulator. If some channel has HALTed to
153 * a particular UIP, then by the end of the program, every channel
154 * must have HALTed to that UIP. Furthermore, the tracking is a
155 * stack, so you can't do the final halt of a UIP after starting
156 * halting to a new UIP.
157 *
158 * Symptoms of not emitting this instruction on actual hardware
159 * included GPU hangs and sparkly rendering on the piglit discard
160 * tests.
161 */
162 brw_inst *last_halt = gen6_HALT(p);
163 brw_inst_set_uip(p->devinfo, last_halt, 1 * scale);
164 brw_inst_set_jip(p->devinfo, last_halt, 1 * scale);
165
166 int ip = p->nr_insn;
167
168 foreach_in_list(ip_record, patch_ip, &discard_halt_patches) {
169 brw_inst *patch = &p->store[patch_ip->ip];
170
171 assert(brw_inst_opcode(p->devinfo, patch) == BRW_OPCODE_HALT);
172 /* HALT takes a half-instruction distance from the pre-incremented IP. */
173 brw_inst_set_uip(p->devinfo, patch, (ip - patch_ip->ip) * scale);
174 }
175
176 this->discard_halt_patches.make_empty();
177 return true;
178 }
179
180 void
181 fs_generator::fire_fb_write(fs_inst *inst,
182 struct brw_reg payload,
183 struct brw_reg implied_header,
184 GLuint nr)
185 {
186 uint32_t msg_control;
187
188 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
189
190 if (devinfo->gen < 6) {
191 brw_push_insn_state(p);
192 brw_set_default_exec_size(p, BRW_EXECUTE_8);
193 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
194 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
195 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
196 brw_MOV(p, offset(payload, 1), brw_vec8_grf(1, 0));
197 brw_pop_insn_state(p);
198 }
199
200 if (inst->opcode == FS_OPCODE_REP_FB_WRITE)
201 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED;
202 else if (prog_data->dual_src_blend) {
203 if (!inst->force_sechalf)
204 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01;
205 else
206 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23;
207 } else if (inst->exec_size == 16)
208 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE;
209 else
210 msg_control = BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01;
211
212 uint32_t surf_index =
213 prog_data->binding_table.render_target_start + inst->target;
214
215 bool last_render_target = inst->eot ||
216 (prog_data->dual_src_blend && dispatch_width == 16);
217
218
219 brw_fb_WRITE(p,
220 dispatch_width,
221 payload,
222 implied_header,
223 msg_control,
224 surf_index,
225 nr,
226 0,
227 inst->eot,
228 last_render_target,
229 inst->header_size != 0);
230
231 brw_mark_surface_used(&prog_data->base, surf_index);
232 }
233
234 void
235 fs_generator::generate_fb_write(fs_inst *inst, struct brw_reg payload)
236 {
237 brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
238 const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
239 struct brw_reg implied_header;
240
241 if (devinfo->gen < 8 && !devinfo->is_haswell) {
242 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
243 }
244
245 if (inst->base_mrf >= 0)
246 payload = brw_message_reg(inst->base_mrf);
247
248 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
249 * move, here's g1.
250 */
251 if (inst->header_size != 0) {
252 brw_push_insn_state(p);
253 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
254 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
255 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
256 brw_set_default_flag_reg(p, 0, 0);
257
258 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
259 * present.
260 */
261 if (prog_data->uses_kill) {
262 struct brw_reg pixel_mask;
263
264 if (devinfo->gen >= 6)
265 pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
266 else
267 pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
268
269 brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
270 }
271
272 if (devinfo->gen >= 6) {
273 brw_push_insn_state(p);
274 brw_set_default_exec_size(p, BRW_EXECUTE_16);
275 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
276 brw_MOV(p,
277 retype(payload, BRW_REGISTER_TYPE_UD),
278 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
279 brw_pop_insn_state(p);
280
281 if (inst->target > 0 && key->replicate_alpha) {
282 /* Set "Source0 Alpha Present to RenderTarget" bit in message
283 * header.
284 */
285 brw_OR(p,
286 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
287 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
288 brw_imm_ud(0x1 << 11));
289 }
290
291 if (inst->target > 0) {
292 /* Set the render target index for choosing BLEND_STATE. */
293 brw_MOV(p, retype(vec1(suboffset(payload, 2)),
294 BRW_REGISTER_TYPE_UD),
295 brw_imm_ud(inst->target));
296 }
297
298 /* Set computes stencil to render target */
299 if (prog_data->computed_stencil) {
300 brw_OR(p,
301 vec1(retype(payload, BRW_REGISTER_TYPE_UD)),
302 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
303 brw_imm_ud(0x1 << 14));
304 }
305
306 implied_header = brw_null_reg();
307 } else {
308 implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
309 }
310
311 brw_pop_insn_state(p);
312 } else {
313 implied_header = brw_null_reg();
314 }
315
316 if (!runtime_check_aads_emit) {
317 fire_fb_write(inst, payload, implied_header, inst->mlen);
318 } else {
319 /* This can only happen in gen < 6 */
320 assert(devinfo->gen < 6);
321
322 struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
323
324 /* Check runtime bit to detect if we have to send AA data or not */
325 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
326 brw_AND(p,
327 v1_null_ud,
328 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
329 brw_imm_ud(1<<26));
330 brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, BRW_CONDITIONAL_NZ);
331
332 int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
333 brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
334 {
335 /* Don't send AA data */
336 fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
337 }
338 brw_land_fwd_jump(p, jmp);
339 fire_fb_write(inst, payload, implied_header, inst->mlen);
340 }
341 }
342
343 void
344 fs_generator::generate_mov_indirect(fs_inst *inst,
345 struct brw_reg dst,
346 struct brw_reg reg,
347 struct brw_reg indirect_byte_offset)
348 {
349 assert(indirect_byte_offset.type == BRW_REGISTER_TYPE_UD);
350 assert(indirect_byte_offset.file == BRW_GENERAL_REGISTER_FILE);
351
352 unsigned imm_byte_offset = reg.nr * REG_SIZE + reg.subnr;
353
354 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
355 struct brw_reg addr = vec8(brw_address_reg(0));
356
357 /* The destination stride of an instruction (in bytes) must be greater
358 * than or equal to the size of the rest of the instruction. Since the
359 * address register is of type UW, we can't use a D-type instruction.
360 * In order to get around this, re re-type to UW and use a stride.
361 */
362 indirect_byte_offset =
363 retype(spread(indirect_byte_offset, 2), BRW_REGISTER_TYPE_UW);
364
365 /* Prior to Broadwell, there are only 8 address registers. */
366 assert(inst->exec_size == 8 || devinfo->gen >= 8);
367
368 brw_MOV(p, addr, indirect_byte_offset);
369 brw_inst_set_mask_control(devinfo, brw_last_inst, BRW_MASK_DISABLE);
370 brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
371 }
372
373 void
374 fs_generator::generate_urb_read(fs_inst *inst,
375 struct brw_reg dst,
376 struct brw_reg header)
377 {
378 assert(header.file == BRW_GENERAL_REGISTER_FILE);
379 assert(header.type == BRW_REGISTER_TYPE_UD);
380
381 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
382 brw_set_dest(p, send, dst);
383 brw_set_src0(p, send, header);
384 brw_set_src1(p, send, brw_imm_ud(0u));
385
386 brw_inst_set_sfid(p->devinfo, send, BRW_SFID_URB);
387 brw_inst_set_urb_opcode(p->devinfo, send, GEN8_URB_OPCODE_SIMD8_READ);
388
389 if (inst->opcode == SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT)
390 brw_inst_set_urb_per_slot_offset(p->devinfo, send, true);
391
392 brw_inst_set_mlen(p->devinfo, send, inst->mlen);
393 brw_inst_set_rlen(p->devinfo, send, inst->regs_written);
394 brw_inst_set_header_present(p->devinfo, send, true);
395 brw_inst_set_urb_global_offset(p->devinfo, send, inst->offset);
396 }
397
398 void
399 fs_generator::generate_urb_write(fs_inst *inst, struct brw_reg payload)
400 {
401 brw_inst *insn;
402
403 insn = brw_next_insn(p, BRW_OPCODE_SEND);
404
405 brw_set_dest(p, insn, brw_null_reg());
406 brw_set_src0(p, insn, payload);
407 brw_set_src1(p, insn, brw_imm_d(0));
408
409 brw_inst_set_sfid(p->devinfo, insn, BRW_SFID_URB);
410 brw_inst_set_urb_opcode(p->devinfo, insn, GEN8_URB_OPCODE_SIMD8_WRITE);
411
412 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT ||
413 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
414 brw_inst_set_urb_per_slot_offset(p->devinfo, insn, true);
415
416 if (inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED ||
417 inst->opcode == SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT)
418 brw_inst_set_urb_channel_mask_present(p->devinfo, insn, true);
419
420 brw_inst_set_mlen(p->devinfo, insn, inst->mlen);
421 brw_inst_set_rlen(p->devinfo, insn, 0);
422 brw_inst_set_eot(p->devinfo, insn, inst->eot);
423 brw_inst_set_header_present(p->devinfo, insn, true);
424 brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
425 }
426
427 void
428 fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
429 {
430 struct brw_inst *insn;
431
432 insn = brw_next_insn(p, BRW_OPCODE_SEND);
433
434 brw_set_dest(p, insn, brw_null_reg());
435 brw_set_src0(p, insn, payload);
436 brw_set_src1(p, insn, brw_imm_d(0));
437
438 /* Terminate a compute shader by sending a message to the thread spawner.
439 */
440 brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
441 brw_inst_set_mlen(devinfo, insn, 1);
442 brw_inst_set_rlen(devinfo, insn, 0);
443 brw_inst_set_eot(devinfo, insn, inst->eot);
444 brw_inst_set_header_present(devinfo, insn, false);
445
446 brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
447 brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
448
449 /* Note that even though the thread has a URB resource associated with it,
450 * we set the "do not dereference URB" bit, because the URB resource is
451 * managed by the fixed-function unit, so it will free it automatically.
452 */
453 brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
454
455 brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
456 }
457
458 void
459 fs_generator::generate_stencil_ref_packing(fs_inst *inst,
460 struct brw_reg dst,
461 struct brw_reg src)
462 {
463 assert(dispatch_width == 8);
464 assert(devinfo->gen >= 9);
465
466 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
467 * Presumably, in order to save memory bandwidth, the stencil reference
468 * values written from the FS need to be packed into 2 dwords (this makes
469 * sense because the stencil values are limited to 1 byte each and a SIMD8
470 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
471 *
472 * The spec is confusing here because in the payload definition of MDP_RTW_S8
473 * (Message Data Payload for Render Target Writes with Stencil 8b) the
474 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
475 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
476 * packed values specified above and diagrammed below:
477 *
478 * 31 0
479 * --------------------------------
480 * DW | |
481 * 2-7 | IGNORED |
482 * | |
483 * --------------------------------
484 * DW1 | STC | STC | STC | STC |
485 * | slot7 | slot6 | slot5 | slot4|
486 * --------------------------------
487 * DW0 | STC | STC | STC | STC |
488 * | slot3 | slot2 | slot1 | slot0|
489 * --------------------------------
490 */
491
492 src.vstride = BRW_VERTICAL_STRIDE_4;
493 src.width = BRW_WIDTH_1;
494 src.hstride = BRW_HORIZONTAL_STRIDE_0;
495 assert(src.type == BRW_REGISTER_TYPE_UB);
496 brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_UB), src);
497 }
498
499 void
500 fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
501 {
502 brw_barrier(p, src);
503 brw_WAIT(p);
504 }
505
506 void
507 fs_generator::generate_blorp_fb_write(fs_inst *inst)
508 {
509 brw_fb_WRITE(p,
510 16 /* dispatch_width */,
511 brw_message_reg(inst->base_mrf),
512 brw_reg_from_fs_reg(inst, &inst->src[0], devinfo->gen),
513 BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE,
514 inst->target,
515 inst->mlen,
516 0,
517 true,
518 true,
519 inst->header_size != 0);
520 }
521
522 void
523 fs_generator::generate_linterp(fs_inst *inst,
524 struct brw_reg dst, struct brw_reg *src)
525 {
526 /* PLN reads:
527 * / in SIMD16 \
528 * -----------------------------------
529 * | src1+0 | src1+1 | src1+2 | src1+3 |
530 * |-----------------------------------|
531 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
532 * -----------------------------------
533 *
534 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
535 *
536 * -----------------------------------
537 * | src1+0 | src1+1 | src1+2 | src1+3 |
538 * |-----------------------------------|
539 * |(x0, x1)|(y0, y1)| | | in SIMD8
540 * |-----------------------------------|
541 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
542 * -----------------------------------
543 *
544 * See also: emit_interpolation_setup_gen4().
545 */
546 struct brw_reg delta_x = src[0];
547 struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
548 struct brw_reg interp = src[1];
549
550 if (devinfo->has_pln &&
551 (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
552 brw_PLN(p, dst, interp, delta_x);
553 } else {
554 brw_LINE(p, brw_null_reg(), interp, delta_x);
555 brw_MAC(p, dst, suboffset(interp, 1), delta_y);
556 }
557 }
558
559 void
560 fs_generator::generate_math_gen6(fs_inst *inst,
561 struct brw_reg dst,
562 struct brw_reg src0,
563 struct brw_reg src1)
564 {
565 int op = brw_math_function(inst->opcode);
566 bool binop = src1.file != BRW_ARCHITECTURE_REGISTER_FILE;
567
568 if (dispatch_width == 8) {
569 gen6_math(p, dst, op, src0, src1);
570 } else if (dispatch_width == 16) {
571 brw_push_insn_state(p);
572 brw_set_default_exec_size(p, BRW_EXECUTE_8);
573 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
574 gen6_math(p, firsthalf(dst), op, firsthalf(src0), firsthalf(src1));
575 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
576 gen6_math(p, sechalf(dst), op, sechalf(src0),
577 binop ? sechalf(src1) : brw_null_reg());
578 brw_pop_insn_state(p);
579 }
580 }
581
582 void
583 fs_generator::generate_math_gen4(fs_inst *inst,
584 struct brw_reg dst,
585 struct brw_reg src)
586 {
587 int op = brw_math_function(inst->opcode);
588
589 assert(inst->mlen >= 1);
590
591 if (dispatch_width == 8) {
592 gen4_math(p, dst,
593 op,
594 inst->base_mrf, src,
595 BRW_MATH_PRECISION_FULL);
596 } else if (dispatch_width == 16) {
597 brw_set_default_exec_size(p, BRW_EXECUTE_8);
598 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
599 gen4_math(p, firsthalf(dst),
600 op,
601 inst->base_mrf, firsthalf(src),
602 BRW_MATH_PRECISION_FULL);
603 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
604 gen4_math(p, sechalf(dst),
605 op,
606 inst->base_mrf + 1, sechalf(src),
607 BRW_MATH_PRECISION_FULL);
608
609 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
610 }
611 }
612
613 void
614 fs_generator::generate_math_g45(fs_inst *inst,
615 struct brw_reg dst,
616 struct brw_reg src)
617 {
618 if (inst->opcode == SHADER_OPCODE_POW ||
619 inst->opcode == SHADER_OPCODE_INT_QUOTIENT ||
620 inst->opcode == SHADER_OPCODE_INT_REMAINDER) {
621 generate_math_gen4(inst, dst, src);
622 return;
623 }
624
625 int op = brw_math_function(inst->opcode);
626
627 assert(inst->mlen >= 1);
628
629 gen4_math(p, dst,
630 op,
631 inst->base_mrf, src,
632 BRW_MATH_PRECISION_FULL);
633 }
634
635 void
636 fs_generator::generate_get_buffer_size(fs_inst *inst,
637 struct brw_reg dst,
638 struct brw_reg src,
639 struct brw_reg surf_index)
640 {
641 assert(devinfo->gen >= 7);
642 assert(surf_index.file == BRW_IMMEDIATE_VALUE);
643
644 uint32_t simd_mode;
645 int rlen = 4;
646
647 switch (inst->exec_size) {
648 case 8:
649 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
650 break;
651 case 16:
652 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
653 break;
654 default:
655 unreachable("Invalid width for texture instruction");
656 }
657
658 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
659 rlen = 8;
660 dst = vec16(dst);
661 }
662
663 brw_SAMPLE(p,
664 retype(dst, BRW_REGISTER_TYPE_UW),
665 inst->base_mrf,
666 src,
667 surf_index.ud,
668 0,
669 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO,
670 rlen, /* response length */
671 inst->mlen,
672 inst->header_size > 0,
673 simd_mode,
674 BRW_SAMPLER_RETURN_FORMAT_SINT32);
675
676 brw_mark_surface_used(prog_data, surf_index.ud);
677 }
678
679 void
680 fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
681 struct brw_reg surface_index,
682 struct brw_reg sampler_index)
683 {
684 int msg_type = -1;
685 int rlen = 4;
686 uint32_t simd_mode;
687 uint32_t return_format;
688 bool is_combined_send = inst->eot;
689
690 switch (dst.type) {
691 case BRW_REGISTER_TYPE_D:
692 return_format = BRW_SAMPLER_RETURN_FORMAT_SINT32;
693 break;
694 case BRW_REGISTER_TYPE_UD:
695 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
696 break;
697 default:
698 return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
699 break;
700 }
701
702 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
703 * is set as part of the message descriptor. On gen4, the PRM seems to
704 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
705 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
706 * gone from the message descriptor entirely and you just get UINT32 all
707 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
708 * just stomp it to UINT32 all the time.
709 */
710 if (inst->opcode == SHADER_OPCODE_TXS)
711 return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
712
713 switch (inst->exec_size) {
714 case 8:
715 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
716 break;
717 case 16:
718 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
719 break;
720 default:
721 unreachable("Invalid width for texture instruction");
722 }
723
724 if (devinfo->gen >= 5) {
725 switch (inst->opcode) {
726 case SHADER_OPCODE_TEX:
727 if (inst->shadow_compare) {
728 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE;
729 } else {
730 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE;
731 }
732 break;
733 case FS_OPCODE_TXB:
734 if (inst->shadow_compare) {
735 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE;
736 } else {
737 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS;
738 }
739 break;
740 case SHADER_OPCODE_TXL:
741 if (inst->shadow_compare) {
742 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE;
743 } else {
744 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LOD;
745 }
746 break;
747 case SHADER_OPCODE_TXS:
748 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO;
749 break;
750 case SHADER_OPCODE_TXD:
751 if (inst->shadow_compare) {
752 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
753 assert(devinfo->gen >= 8 || devinfo->is_haswell);
754 msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
755 } else {
756 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
757 }
758 break;
759 case SHADER_OPCODE_TXF:
760 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
761 break;
762 case SHADER_OPCODE_TXF_CMS_W:
763 assert(devinfo->gen >= 9);
764 msg_type = GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W;
765 break;
766 case SHADER_OPCODE_TXF_CMS:
767 if (devinfo->gen >= 7)
768 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
769 else
770 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
771 break;
772 case SHADER_OPCODE_TXF_UMS:
773 assert(devinfo->gen >= 7);
774 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
775 break;
776 case SHADER_OPCODE_TXF_MCS:
777 assert(devinfo->gen >= 7);
778 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
779 break;
780 case SHADER_OPCODE_LOD:
781 msg_type = GEN5_SAMPLER_MESSAGE_LOD;
782 break;
783 case SHADER_OPCODE_TG4:
784 if (inst->shadow_compare) {
785 assert(devinfo->gen >= 7);
786 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
787 } else {
788 assert(devinfo->gen >= 6);
789 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
790 }
791 break;
792 case SHADER_OPCODE_TG4_OFFSET:
793 assert(devinfo->gen >= 7);
794 if (inst->shadow_compare) {
795 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
796 } else {
797 msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO;
798 }
799 break;
800 case SHADER_OPCODE_SAMPLEINFO:
801 msg_type = GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO;
802 break;
803 default:
804 unreachable("not reached");
805 }
806 } else {
807 switch (inst->opcode) {
808 case SHADER_OPCODE_TEX:
809 /* Note that G45 and older determines shadow compare and dispatch width
810 * from message length for most messages.
811 */
812 if (inst->exec_size == 8) {
813 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
814 if (inst->shadow_compare) {
815 assert(inst->mlen == 6);
816 } else {
817 assert(inst->mlen <= 4);
818 }
819 } else {
820 if (inst->shadow_compare) {
821 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE;
822 assert(inst->mlen == 9);
823 } else {
824 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE;
825 assert(inst->mlen <= 7 && inst->mlen % 2 == 1);
826 }
827 }
828 break;
829 case FS_OPCODE_TXB:
830 if (inst->shadow_compare) {
831 assert(inst->exec_size == 8);
832 assert(inst->mlen == 6);
833 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE;
834 } else {
835 assert(inst->mlen == 9);
836 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
837 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
838 }
839 break;
840 case SHADER_OPCODE_TXL:
841 if (inst->shadow_compare) {
842 assert(inst->exec_size == 8);
843 assert(inst->mlen == 6);
844 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE;
845 } else {
846 assert(inst->mlen == 9);
847 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD;
848 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
849 }
850 break;
851 case SHADER_OPCODE_TXD:
852 /* There is no sample_d_c message; comparisons are done manually */
853 assert(inst->exec_size == 8);
854 assert(inst->mlen == 7 || inst->mlen == 10);
855 msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS;
856 break;
857 case SHADER_OPCODE_TXF:
858 assert(inst->mlen <= 9 && inst->mlen % 2 == 1);
859 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
860 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
861 break;
862 case SHADER_OPCODE_TXS:
863 assert(inst->mlen == 3);
864 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_RESINFO;
865 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
866 break;
867 default:
868 unreachable("not reached");
869 }
870 }
871 assert(msg_type != -1);
872
873 if (simd_mode == BRW_SAMPLER_SIMD_MODE_SIMD16) {
874 rlen = 8;
875 dst = vec16(dst);
876 }
877
878 if (is_combined_send) {
879 assert(devinfo->gen >= 9 || devinfo->is_cherryview);
880 rlen = 0;
881 }
882
883 assert(devinfo->gen < 7 || inst->header_size == 0 ||
884 src.file == BRW_GENERAL_REGISTER_FILE);
885
886 assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
887
888 /* Load the message header if present. If there's a texture offset,
889 * we need to set it up explicitly and load the offset bitfield.
890 * Otherwise, we can use an implied move from g0 to the first message reg.
891 */
892 if (inst->header_size != 0) {
893 if (devinfo->gen < 6 && !inst->offset) {
894 /* Set up an implied move from g0 to the MRF. */
895 src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
896 } else {
897 struct brw_reg header_reg;
898
899 if (devinfo->gen >= 7) {
900 header_reg = src;
901 } else {
902 assert(inst->base_mrf != -1);
903 header_reg = brw_message_reg(inst->base_mrf);
904 }
905
906 brw_push_insn_state(p);
907 brw_set_default_exec_size(p, BRW_EXECUTE_8);
908 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
909 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
910 /* Explicitly set up the message header by copying g0 to the MRF. */
911 brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
912
913 if (inst->offset) {
914 /* Set the offset bits in DWord 2. */
915 brw_MOV(p, get_element_ud(header_reg, 2),
916 brw_imm_ud(inst->offset));
917 } else if (stage != MESA_SHADER_VERTEX &&
918 stage != MESA_SHADER_FRAGMENT) {
919 /* The vertex and fragment stages have g0.2 set to 0, so
920 * header0.2 is 0 when g0 is copied. Other stages may not, so we
921 * must set it to 0 to avoid setting undesirable bits in the
922 * message.
923 */
924 brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
925 }
926
927 brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
928 brw_pop_insn_state(p);
929 }
930 }
931
932 uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
933 inst->opcode == SHADER_OPCODE_TG4_OFFSET)
934 ? prog_data->binding_table.gather_texture_start
935 : prog_data->binding_table.texture_start;
936
937 if (surface_index.file == BRW_IMMEDIATE_VALUE &&
938 sampler_index.file == BRW_IMMEDIATE_VALUE) {
939 uint32_t surface = surface_index.ud;
940 uint32_t sampler = sampler_index.ud;
941
942 brw_SAMPLE(p,
943 retype(dst, BRW_REGISTER_TYPE_UW),
944 inst->base_mrf,
945 src,
946 surface + base_binding_table_index,
947 sampler % 16,
948 msg_type,
949 rlen,
950 inst->mlen,
951 inst->header_size != 0,
952 simd_mode,
953 return_format);
954
955 brw_mark_surface_used(prog_data, surface + base_binding_table_index);
956 } else {
957 /* Non-const sampler index */
958
959 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
960 struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
961 struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
962
963 brw_push_insn_state(p);
964 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
965 brw_set_default_access_mode(p, BRW_ALIGN_1);
966
967 if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
968 brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
969 } else {
970 brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
971 brw_OR(p, addr, addr, surface_reg);
972 }
973 if (base_binding_table_index)
974 brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
975 brw_AND(p, addr, addr, brw_imm_ud(0xfff));
976
977 brw_pop_insn_state(p);
978
979 /* dst = send(offset, a0.0 | <descriptor>) */
980 brw_inst *insn = brw_send_indirect_message(
981 p, BRW_SFID_SAMPLER, dst, src, addr);
982 brw_set_sampler_message(p, insn,
983 0 /* surface */,
984 0 /* sampler */,
985 msg_type,
986 rlen,
987 inst->mlen /* mlen */,
988 inst->header_size != 0 /* header */,
989 simd_mode,
990 return_format);
991
992 /* visitor knows more than we do about the surface limit required,
993 * so has already done marking.
994 */
995 }
996
997 if (is_combined_send) {
998 brw_inst_set_eot(p->devinfo, brw_last_inst, true);
999 brw_inst_set_opcode(p->devinfo, brw_last_inst, BRW_OPCODE_SENDC);
1000 }
1001 }
1002
1003
1004 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1005 * looking like:
1006 *
1007 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1008 *
1009 * Ideally, we want to produce:
1010 *
1011 * DDX DDY
1012 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1013 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1014 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1015 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1016 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1017 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1018 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1019 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1020 *
1021 * and add another set of two more subspans if in 16-pixel dispatch mode.
1022 *
1023 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1024 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1025 * pair. But the ideal approximation may impose a huge performance cost on
1026 * sample_d. On at least Haswell, sample_d instruction does some
1027 * optimizations if the same LOD is used for all pixels in the subspan.
1028 *
1029 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1030 * appropriate swizzling.
1031 */
1032 void
1033 fs_generator::generate_ddx(enum opcode opcode,
1034 struct brw_reg dst, struct brw_reg src)
1035 {
1036 unsigned vstride, width;
1037
1038 if (opcode == FS_OPCODE_DDX_FINE) {
1039 /* produce accurate derivatives */
1040 vstride = BRW_VERTICAL_STRIDE_2;
1041 width = BRW_WIDTH_2;
1042 } else {
1043 /* replicate the derivative at the top-left pixel to other pixels */
1044 vstride = BRW_VERTICAL_STRIDE_4;
1045 width = BRW_WIDTH_4;
1046 }
1047
1048 struct brw_reg src0 = brw_reg(src.file, src.nr, 1,
1049 src.negate, src.abs,
1050 BRW_REGISTER_TYPE_F,
1051 vstride,
1052 width,
1053 BRW_HORIZONTAL_STRIDE_0,
1054 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1055 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1056 src.negate, src.abs,
1057 BRW_REGISTER_TYPE_F,
1058 vstride,
1059 width,
1060 BRW_HORIZONTAL_STRIDE_0,
1061 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1062 brw_ADD(p, dst, src0, negate(src1));
1063 }
1064
1065 /* The negate_value boolean is used to negate the derivative computation for
1066 * FBOs, since they place the origin at the upper left instead of the lower
1067 * left.
1068 */
1069 void
1070 fs_generator::generate_ddy(enum opcode opcode,
1071 struct brw_reg dst, struct brw_reg src,
1072 bool negate_value)
1073 {
1074 if (opcode == FS_OPCODE_DDY_FINE) {
1075 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1076 * Region Restrictions):
1077 *
1078 * In Align16 access mode, SIMD16 is not allowed for DW operations
1079 * and SIMD8 is not allowed for DF operations.
1080 *
1081 * In this context, "DW operations" means "operations acting on 32-bit
1082 * values", so it includes operations on floats.
1083 *
1084 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1085 * (Instruction Compression -> Rules and Restrictions):
1086 *
1087 * A compressed instruction must be in Align1 access mode. Align16
1088 * mode instructions cannot be compressed.
1089 *
1090 * Similar text exists in the g45 PRM.
1091 *
1092 * On these platforms, if we're building a SIMD16 shader, we need to
1093 * manually unroll to a pair of SIMD8 instructions.
1094 */
1095 bool unroll_to_simd8 =
1096 (dispatch_width == 16 &&
1097 (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
1098
1099 /* produce accurate derivatives */
1100 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1101 src.negate, src.abs,
1102 BRW_REGISTER_TYPE_F,
1103 BRW_VERTICAL_STRIDE_4,
1104 BRW_WIDTH_4,
1105 BRW_HORIZONTAL_STRIDE_1,
1106 BRW_SWIZZLE_XYXY, WRITEMASK_XYZW);
1107 struct brw_reg src1 = brw_reg(src.file, src.nr, 0,
1108 src.negate, src.abs,
1109 BRW_REGISTER_TYPE_F,
1110 BRW_VERTICAL_STRIDE_4,
1111 BRW_WIDTH_4,
1112 BRW_HORIZONTAL_STRIDE_1,
1113 BRW_SWIZZLE_ZWZW, WRITEMASK_XYZW);
1114 brw_push_insn_state(p);
1115 brw_set_default_access_mode(p, BRW_ALIGN_16);
1116 if (unroll_to_simd8) {
1117 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1118 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1119 if (negate_value) {
1120 brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
1121 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1122 brw_ADD(p, sechalf(dst), sechalf(src1), negate(sechalf(src0)));
1123 } else {
1124 brw_ADD(p, firsthalf(dst), firsthalf(src0), negate(firsthalf(src1)));
1125 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1126 brw_ADD(p, sechalf(dst), sechalf(src0), negate(sechalf(src1)));
1127 }
1128 } else {
1129 if (negate_value)
1130 brw_ADD(p, dst, src1, negate(src0));
1131 else
1132 brw_ADD(p, dst, src0, negate(src1));
1133 }
1134 brw_pop_insn_state(p);
1135 } else {
1136 /* replicate the derivative at the top-left pixel to other pixels */
1137 struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
1138 src.negate, src.abs,
1139 BRW_REGISTER_TYPE_F,
1140 BRW_VERTICAL_STRIDE_4,
1141 BRW_WIDTH_4,
1142 BRW_HORIZONTAL_STRIDE_0,
1143 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1144 struct brw_reg src1 = brw_reg(src.file, src.nr, 2,
1145 src.negate, src.abs,
1146 BRW_REGISTER_TYPE_F,
1147 BRW_VERTICAL_STRIDE_4,
1148 BRW_WIDTH_4,
1149 BRW_HORIZONTAL_STRIDE_0,
1150 BRW_SWIZZLE_XYZW, WRITEMASK_XYZW);
1151 if (negate_value)
1152 brw_ADD(p, dst, src1, negate(src0));
1153 else
1154 brw_ADD(p, dst, src0, negate(src1));
1155 }
1156 }
1157
1158 void
1159 fs_generator::generate_discard_jump(fs_inst *inst)
1160 {
1161 assert(devinfo->gen >= 6);
1162
1163 /* This HALT will be patched up at FB write time to point UIP at the end of
1164 * the program, and at brw_uip_jip() JIP will be set to the end of the
1165 * current block (or the program).
1166 */
1167 this->discard_halt_patches.push_tail(new(mem_ctx) ip_record(p->nr_insn));
1168
1169 brw_push_insn_state(p);
1170 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1171 gen6_HALT(p);
1172 brw_pop_insn_state(p);
1173 }
1174
1175 void
1176 fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
1177 {
1178 assert(inst->mlen != 0);
1179
1180 brw_MOV(p,
1181 brw_uvec_mrf(inst->exec_size, (inst->base_mrf + 1), 0),
1182 retype(src, BRW_REGISTER_TYPE_UD));
1183 brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
1184 inst->exec_size / 8, inst->offset);
1185 }
1186
1187 void
1188 fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
1189 {
1190 assert(inst->mlen != 0);
1191
1192 brw_oword_block_read_scratch(p, dst, brw_message_reg(inst->base_mrf),
1193 inst->exec_size / 8, inst->offset);
1194 }
1195
1196 void
1197 fs_generator::generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst)
1198 {
1199 gen7_block_read_scratch(p, dst, inst->exec_size / 8, inst->offset);
1200 }
1201
1202 void
1203 fs_generator::generate_uniform_pull_constant_load(fs_inst *inst,
1204 struct brw_reg dst,
1205 struct brw_reg index,
1206 struct brw_reg offset)
1207 {
1208 assert(inst->mlen != 0);
1209
1210 assert(index.file == BRW_IMMEDIATE_VALUE &&
1211 index.type == BRW_REGISTER_TYPE_UD);
1212 uint32_t surf_index = index.ud;
1213
1214 assert(offset.file == BRW_IMMEDIATE_VALUE &&
1215 offset.type == BRW_REGISTER_TYPE_UD);
1216 uint32_t read_offset = offset.ud;
1217
1218 brw_oword_block_read(p, dst, brw_message_reg(inst->base_mrf),
1219 read_offset, surf_index);
1220 }
1221
1222 void
1223 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
1224 struct brw_reg dst,
1225 struct brw_reg index,
1226 struct brw_reg offset)
1227 {
1228 assert(index.type == BRW_REGISTER_TYPE_UD);
1229
1230 assert(offset.file == BRW_GENERAL_REGISTER_FILE);
1231 /* Reference just the dword we need, to avoid angering validate_reg(). */
1232 offset = brw_vec1_grf(offset.nr, 0);
1233
1234 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1235 * the destination loaded consecutively from the same offset (which appears
1236 * in the first component, and the rest are ignored).
1237 */
1238 dst.width = BRW_WIDTH_4;
1239
1240 struct brw_reg src = offset;
1241 bool header_present = false;
1242
1243 if (devinfo->gen >= 9) {
1244 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1245 src = retype(brw_vec4_grf(offset.nr, 0), BRW_REGISTER_TYPE_UD);
1246 header_present = true;
1247
1248 brw_push_insn_state(p);
1249 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1250 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1251 brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
1252 brw_set_default_access_mode(p, BRW_ALIGN_1);
1253
1254 brw_MOV(p, get_element_ud(src, 2),
1255 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2));
1256 brw_pop_insn_state(p);
1257 }
1258
1259 if (index.file == BRW_IMMEDIATE_VALUE) {
1260
1261 uint32_t surf_index = index.ud;
1262
1263 brw_push_insn_state(p);
1264 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1265 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1266 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1267 brw_pop_insn_state(p);
1268
1269 brw_set_dest(p, send, dst);
1270 brw_set_src0(p, send, src);
1271 brw_set_sampler_message(p, send,
1272 surf_index,
1273 0, /* LD message ignores sampler unit */
1274 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1275 1, /* rlen */
1276 inst->mlen,
1277 header_present,
1278 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1279 0);
1280 } else {
1281
1282 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1283
1284 brw_push_insn_state(p);
1285 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1286 brw_set_default_access_mode(p, BRW_ALIGN_1);
1287
1288 /* a0.0 = surf_index & 0xff */
1289 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1290 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1291 brw_set_dest(p, insn_and, addr);
1292 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1293 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1294
1295 /* dst = send(payload, a0.0 | <descriptor>) */
1296 brw_inst *insn = brw_send_indirect_message(
1297 p, BRW_SFID_SAMPLER, dst, src, addr);
1298 brw_set_sampler_message(p, insn,
1299 0,
1300 0, /* LD message ignores sampler unit */
1301 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1302 1, /* rlen */
1303 inst->mlen,
1304 header_present,
1305 BRW_SAMPLER_SIMD_MODE_SIMD4X2,
1306 0);
1307
1308 brw_pop_insn_state(p);
1309 }
1310 }
1311
1312 void
1313 fs_generator::generate_varying_pull_constant_load(fs_inst *inst,
1314 struct brw_reg dst,
1315 struct brw_reg index,
1316 struct brw_reg offset)
1317 {
1318 assert(devinfo->gen < 7); /* Should use the gen7 variant. */
1319 assert(inst->header_size != 0);
1320 assert(inst->mlen);
1321
1322 assert(index.file == BRW_IMMEDIATE_VALUE &&
1323 index.type == BRW_REGISTER_TYPE_UD);
1324 uint32_t surf_index = index.ud;
1325
1326 uint32_t simd_mode, rlen, msg_type;
1327 if (dispatch_width == 16) {
1328 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1329 rlen = 8;
1330 } else {
1331 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1332 rlen = 4;
1333 }
1334
1335 if (devinfo->gen >= 5)
1336 msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
1337 else {
1338 /* We always use the SIMD16 message so that we only have to load U, and
1339 * not V or R.
1340 */
1341 msg_type = BRW_SAMPLER_MESSAGE_SIMD16_LD;
1342 assert(inst->mlen == 3);
1343 assert(inst->regs_written == 8);
1344 rlen = 8;
1345 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1346 }
1347
1348 struct brw_reg offset_mrf = retype(brw_message_reg(inst->base_mrf + 1),
1349 BRW_REGISTER_TYPE_D);
1350 brw_MOV(p, offset_mrf, offset);
1351
1352 struct brw_reg header = brw_vec8_grf(0, 0);
1353 gen6_resolve_implied_move(p, &header, inst->base_mrf);
1354
1355 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1356 brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
1357 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1358 brw_set_src0(p, send, header);
1359 if (devinfo->gen < 6)
1360 brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
1361
1362 /* Our surface is set up as floats, regardless of what actual data is
1363 * stored in it.
1364 */
1365 uint32_t return_format = BRW_SAMPLER_RETURN_FORMAT_FLOAT32;
1366 brw_set_sampler_message(p, send,
1367 surf_index,
1368 0, /* sampler (unused) */
1369 msg_type,
1370 rlen,
1371 inst->mlen,
1372 inst->header_size != 0,
1373 simd_mode,
1374 return_format);
1375 }
1376
1377 void
1378 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst *inst,
1379 struct brw_reg dst,
1380 struct brw_reg index,
1381 struct brw_reg offset)
1382 {
1383 assert(devinfo->gen >= 7);
1384 /* Varying-offset pull constant loads are treated as a normal expression on
1385 * gen7, so the fact that it's a send message is hidden at the IR level.
1386 */
1387 assert(inst->header_size == 0);
1388 assert(!inst->mlen);
1389 assert(index.type == BRW_REGISTER_TYPE_UD);
1390
1391 uint32_t simd_mode, rlen, mlen;
1392 if (dispatch_width == 16) {
1393 mlen = 2;
1394 rlen = 8;
1395 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
1396 } else {
1397 mlen = 1;
1398 rlen = 4;
1399 simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
1400 }
1401
1402 if (index.file == BRW_IMMEDIATE_VALUE) {
1403
1404 uint32_t surf_index = index.ud;
1405
1406 brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
1407 brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
1408 brw_set_src0(p, send, offset);
1409 brw_set_sampler_message(p, send,
1410 surf_index,
1411 0, /* LD message ignores sampler unit */
1412 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1413 rlen,
1414 mlen,
1415 false, /* no header */
1416 simd_mode,
1417 0);
1418
1419 } else {
1420
1421 struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
1422
1423 brw_push_insn_state(p);
1424 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1425 brw_set_default_access_mode(p, BRW_ALIGN_1);
1426
1427 /* a0.0 = surf_index & 0xff */
1428 brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
1429 brw_inst_set_exec_size(p->devinfo, insn_and, BRW_EXECUTE_1);
1430 brw_set_dest(p, insn_and, addr);
1431 brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
1432 brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
1433
1434 brw_pop_insn_state(p);
1435
1436 /* dst = send(offset, a0.0 | <descriptor>) */
1437 brw_inst *insn = brw_send_indirect_message(
1438 p, BRW_SFID_SAMPLER, retype(dst, BRW_REGISTER_TYPE_UW),
1439 offset, addr);
1440 brw_set_sampler_message(p, insn,
1441 0 /* surface */,
1442 0 /* sampler */,
1443 GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
1444 rlen /* rlen */,
1445 mlen /* mlen */,
1446 false /* header */,
1447 simd_mode,
1448 0);
1449 }
1450 }
1451
1452 /**
1453 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1454 * into the flags register (f0.0).
1455 *
1456 * Used only on Gen6 and above.
1457 */
1458 void
1459 fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
1460 {
1461 struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
1462 struct brw_reg dispatch_mask;
1463
1464 if (devinfo->gen >= 6)
1465 dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
1466 else
1467 dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
1468
1469 brw_push_insn_state(p);
1470 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1471 brw_MOV(p, flags, dispatch_mask);
1472 brw_pop_insn_state(p);
1473 }
1474
1475 void
1476 fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
1477 struct brw_reg dst,
1478 struct brw_reg src,
1479 struct brw_reg msg_data,
1480 unsigned msg_type)
1481 {
1482 assert(msg_data.type == BRW_REGISTER_TYPE_UD);
1483
1484 brw_pixel_interpolator_query(p,
1485 retype(dst, BRW_REGISTER_TYPE_UW),
1486 src,
1487 inst->pi_noperspective,
1488 msg_type,
1489 msg_data,
1490 inst->mlen,
1491 inst->regs_written);
1492 }
1493
1494
1495 /**
1496 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1497 * sampler LD messages.
1498 *
1499 * We don't want to bake it into the send message's code generation because
1500 * that means we don't get a chance to schedule the instructions.
1501 */
1502 void
1503 fs_generator::generate_set_simd4x2_offset(fs_inst *inst,
1504 struct brw_reg dst,
1505 struct brw_reg value)
1506 {
1507 assert(value.file == BRW_IMMEDIATE_VALUE);
1508
1509 brw_push_insn_state(p);
1510 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1511 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1512 brw_set_default_mask_control(p, BRW_MASK_DISABLE);
1513 brw_MOV(p, retype(brw_vec1_reg(dst.file, dst.nr, 0), value.type), value);
1514 brw_pop_insn_state(p);
1515 }
1516
1517 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1518 * the ADD instruction.
1519 */
1520 void
1521 fs_generator::generate_set_sample_id(fs_inst *inst,
1522 struct brw_reg dst,
1523 struct brw_reg src0,
1524 struct brw_reg src1)
1525 {
1526 assert(dst.type == BRW_REGISTER_TYPE_D ||
1527 dst.type == BRW_REGISTER_TYPE_UD);
1528 assert(src0.type == BRW_REGISTER_TYPE_D ||
1529 src0.type == BRW_REGISTER_TYPE_UD);
1530
1531 struct brw_reg reg = stride(src1, 1, 4, 0);
1532 if (devinfo->gen >= 8 || dispatch_width == 8) {
1533 brw_ADD(p, dst, src0, reg);
1534 } else if (dispatch_width == 16) {
1535 brw_push_insn_state(p);
1536 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1537 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1538 brw_ADD(p, firsthalf(dst), firsthalf(src0), reg);
1539 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1540 brw_ADD(p, sechalf(dst), sechalf(src0), suboffset(reg, 2));
1541 brw_pop_insn_state(p);
1542 }
1543 }
1544
1545 void
1546 fs_generator::generate_pack_half_2x16_split(fs_inst *inst,
1547 struct brw_reg dst,
1548 struct brw_reg x,
1549 struct brw_reg y)
1550 {
1551 assert(devinfo->gen >= 7);
1552 assert(dst.type == BRW_REGISTER_TYPE_UD);
1553 assert(x.type == BRW_REGISTER_TYPE_F);
1554 assert(y.type == BRW_REGISTER_TYPE_F);
1555
1556 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1557 *
1558 * Because this instruction does not have a 16-bit floating-point type,
1559 * the destination data type must be Word (W).
1560 *
1561 * The destination must be DWord-aligned and specify a horizontal stride
1562 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1563 * each destination channel and the upper word is not modified.
1564 */
1565 struct brw_reg dst_w = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
1566
1567 /* Give each 32-bit channel of dst the form below, where "." means
1568 * unchanged.
1569 * 0x....hhhh
1570 */
1571 brw_F32TO16(p, dst_w, y);
1572
1573 /* Now the form:
1574 * 0xhhhh0000
1575 */
1576 brw_SHL(p, dst, dst, brw_imm_ud(16u));
1577
1578 /* And, finally the form of packHalf2x16's output:
1579 * 0xhhhhllll
1580 */
1581 brw_F32TO16(p, dst_w, x);
1582 }
1583
1584 void
1585 fs_generator::generate_unpack_half_2x16_split(fs_inst *inst,
1586 struct brw_reg dst,
1587 struct brw_reg src)
1588 {
1589 assert(devinfo->gen >= 7);
1590 assert(dst.type == BRW_REGISTER_TYPE_F);
1591 assert(src.type == BRW_REGISTER_TYPE_UD);
1592
1593 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1594 *
1595 * Because this instruction does not have a 16-bit floating-point type,
1596 * the source data type must be Word (W). The destination type must be
1597 * F (Float).
1598 */
1599 struct brw_reg src_w = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
1600
1601 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1602 * For the Y case, we wish to access only the upper word; therefore
1603 * a 16-bit subregister offset is needed.
1604 */
1605 assert(inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X ||
1606 inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y);
1607 if (inst->opcode == FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y)
1608 src_w.subnr += 2;
1609
1610 brw_F16TO32(p, dst, src_w);
1611 }
1612
1613 void
1614 fs_generator::generate_shader_time_add(fs_inst *inst,
1615 struct brw_reg payload,
1616 struct brw_reg offset,
1617 struct brw_reg value)
1618 {
1619 assert(devinfo->gen >= 7);
1620 brw_push_insn_state(p);
1621 brw_set_default_mask_control(p, true);
1622
1623 assert(payload.file == BRW_GENERAL_REGISTER_FILE);
1624 struct brw_reg payload_offset = retype(brw_vec1_grf(payload.nr, 0),
1625 offset.type);
1626 struct brw_reg payload_value = retype(brw_vec1_grf(payload.nr + 1, 0),
1627 value.type);
1628
1629 assert(offset.file == BRW_IMMEDIATE_VALUE);
1630 if (value.file == BRW_GENERAL_REGISTER_FILE) {
1631 value.width = BRW_WIDTH_1;
1632 value.hstride = BRW_HORIZONTAL_STRIDE_0;
1633 value.vstride = BRW_VERTICAL_STRIDE_0;
1634 } else {
1635 assert(value.file == BRW_IMMEDIATE_VALUE);
1636 }
1637
1638 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1639 * case, and we don't really care about squeezing every bit of performance
1640 * out of this path, so we just emit the MOVs from here.
1641 */
1642 brw_MOV(p, payload_offset, offset);
1643 brw_MOV(p, payload_value, value);
1644 brw_shader_time_add(p, payload,
1645 prog_data->binding_table.shader_time_start);
1646 brw_pop_insn_state(p);
1647
1648 brw_mark_surface_used(prog_data,
1649 prog_data->binding_table.shader_time_start);
1650 }
1651
1652 void
1653 fs_generator::enable_debug(const char *shader_name)
1654 {
1655 debug_flag = true;
1656 this->shader_name = shader_name;
1657 }
1658
1659 int
1660 fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
1661 {
1662 /* align to 64 byte boundary. */
1663 while (p->next_insn_offset % 64)
1664 brw_NOP(p);
1665
1666 this->dispatch_width = dispatch_width;
1667 if (dispatch_width == 16)
1668 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1669
1670 int start_offset = p->next_insn_offset;
1671 int spill_count = 0, fill_count = 0;
1672 int loop_count = 0;
1673
1674 struct annotation_info annotation;
1675 memset(&annotation, 0, sizeof(annotation));
1676
1677 foreach_block_and_inst (block, fs_inst, inst, cfg) {
1678 struct brw_reg src[3], dst;
1679 unsigned int last_insn_offset = p->next_insn_offset;
1680 bool multiple_instructions_emitted = false;
1681
1682 if (unlikely(debug_flag))
1683 annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
1684
1685 for (unsigned int i = 0; i < inst->sources; i++) {
1686 src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen);
1687
1688 /* The accumulator result appears to get used for the
1689 * conditional modifier generation. When negating a UD
1690 * value, there is a 33rd bit generated for the sign in the
1691 * accumulator value, so now you can't check, for example,
1692 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1693 */
1694 assert(!inst->conditional_mod ||
1695 inst->src[i].type != BRW_REGISTER_TYPE_UD ||
1696 !inst->src[i].negate);
1697 }
1698 dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen);
1699
1700 brw_set_default_predicate_control(p, inst->predicate);
1701 brw_set_default_predicate_inverse(p, inst->predicate_inverse);
1702 brw_set_default_flag_reg(p, 0, inst->flag_subreg);
1703 brw_set_default_saturate(p, inst->saturate);
1704 brw_set_default_mask_control(p, inst->force_writemask_all);
1705 brw_set_default_acc_write_control(p, inst->writes_accumulator);
1706 brw_set_default_exec_size(p, cvt(inst->exec_size) - 1);
1707
1708 assert(inst->base_mrf + inst->mlen <= BRW_MAX_MRF(devinfo->gen));
1709 assert(inst->mlen <= BRW_MAX_MSG_LENGTH);
1710
1711 switch (inst->exec_size) {
1712 case 1:
1713 case 2:
1714 case 4:
1715 assert(inst->force_writemask_all);
1716 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1717 break;
1718 case 8:
1719 if (inst->force_sechalf) {
1720 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1721 } else {
1722 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1723 }
1724 break;
1725 case 16:
1726 case 32:
1727 /* If the instruction writes to more than one register, it needs to
1728 * be a "compressed" instruction on Gen <= 5.
1729 */
1730 if (inst->dst.component_size(inst->exec_size) > REG_SIZE)
1731 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1732 else
1733 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1734 break;
1735 default:
1736 unreachable("Invalid instruction width");
1737 }
1738
1739 switch (inst->opcode) {
1740 case BRW_OPCODE_MOV:
1741 brw_MOV(p, dst, src[0]);
1742 break;
1743 case BRW_OPCODE_ADD:
1744 brw_ADD(p, dst, src[0], src[1]);
1745 break;
1746 case BRW_OPCODE_MUL:
1747 brw_MUL(p, dst, src[0], src[1]);
1748 break;
1749 case BRW_OPCODE_AVG:
1750 brw_AVG(p, dst, src[0], src[1]);
1751 break;
1752 case BRW_OPCODE_MACH:
1753 brw_MACH(p, dst, src[0], src[1]);
1754 break;
1755
1756 case BRW_OPCODE_LINE:
1757 brw_LINE(p, dst, src[0], src[1]);
1758 break;
1759
1760 case BRW_OPCODE_MAD:
1761 assert(devinfo->gen >= 6);
1762 brw_set_default_access_mode(p, BRW_ALIGN_16);
1763 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1764 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1765 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1766 brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1767 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1768 brw_inst *s = brw_MAD(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1769 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1770
1771 if (inst->conditional_mod) {
1772 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1773 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1774 multiple_instructions_emitted = true;
1775 }
1776 } else {
1777 brw_MAD(p, dst, src[0], src[1], src[2]);
1778 }
1779 brw_set_default_access_mode(p, BRW_ALIGN_1);
1780 break;
1781
1782 case BRW_OPCODE_LRP:
1783 assert(devinfo->gen >= 6);
1784 brw_set_default_access_mode(p, BRW_ALIGN_16);
1785 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1786 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1787 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1788 brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1789 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1790 brw_inst *s = brw_LRP(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1791 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1792
1793 if (inst->conditional_mod) {
1794 brw_inst_set_cond_modifier(p->devinfo, f, inst->conditional_mod);
1795 brw_inst_set_cond_modifier(p->devinfo, s, inst->conditional_mod);
1796 multiple_instructions_emitted = true;
1797 }
1798 } else {
1799 brw_LRP(p, dst, src[0], src[1], src[2]);
1800 }
1801 brw_set_default_access_mode(p, BRW_ALIGN_1);
1802 break;
1803
1804 case BRW_OPCODE_FRC:
1805 brw_FRC(p, dst, src[0]);
1806 break;
1807 case BRW_OPCODE_RNDD:
1808 brw_RNDD(p, dst, src[0]);
1809 break;
1810 case BRW_OPCODE_RNDE:
1811 brw_RNDE(p, dst, src[0]);
1812 break;
1813 case BRW_OPCODE_RNDZ:
1814 brw_RNDZ(p, dst, src[0]);
1815 break;
1816
1817 case BRW_OPCODE_AND:
1818 brw_AND(p, dst, src[0], src[1]);
1819 break;
1820 case BRW_OPCODE_OR:
1821 brw_OR(p, dst, src[0], src[1]);
1822 break;
1823 case BRW_OPCODE_XOR:
1824 brw_XOR(p, dst, src[0], src[1]);
1825 break;
1826 case BRW_OPCODE_NOT:
1827 brw_NOT(p, dst, src[0]);
1828 break;
1829 case BRW_OPCODE_ASR:
1830 brw_ASR(p, dst, src[0], src[1]);
1831 break;
1832 case BRW_OPCODE_SHR:
1833 brw_SHR(p, dst, src[0], src[1]);
1834 break;
1835 case BRW_OPCODE_SHL:
1836 brw_SHL(p, dst, src[0], src[1]);
1837 break;
1838 case BRW_OPCODE_F32TO16:
1839 assert(devinfo->gen >= 7);
1840 brw_F32TO16(p, dst, src[0]);
1841 break;
1842 case BRW_OPCODE_F16TO32:
1843 assert(devinfo->gen >= 7);
1844 brw_F16TO32(p, dst, src[0]);
1845 break;
1846 case BRW_OPCODE_CMP:
1847 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1848 * that when the destination is a GRF that the dependency-clear bit on
1849 * the flag register is cleared early.
1850 *
1851 * Suggested workarounds are to disable coissuing CMP instructions
1852 * or to split CMP(16) instructions into two CMP(8) instructions.
1853 *
1854 * We choose to split into CMP(8) instructions since disabling
1855 * coissuing would affect CMP instructions not otherwise affected by
1856 * the errata.
1857 */
1858 if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
1859 if (dst.file == BRW_GENERAL_REGISTER_FILE) {
1860 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1861 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1862 brw_CMP(p, firsthalf(dst), inst->conditional_mod,
1863 firsthalf(src[0]), firsthalf(src[1]));
1864 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1865 brw_CMP(p, sechalf(dst), inst->conditional_mod,
1866 sechalf(src[0]), sechalf(src[1]));
1867 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1868
1869 multiple_instructions_emitted = true;
1870 } else if (dst.file == BRW_ARCHITECTURE_REGISTER_FILE) {
1871 /* For unknown reasons, the aforementioned workaround is not
1872 * sufficient. Overriding the type when the destination is the
1873 * null register is necessary but not sufficient by itself.
1874 */
1875 assert(dst.nr == BRW_ARF_NULL);
1876 dst.type = BRW_REGISTER_TYPE_D;
1877 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1878 } else {
1879 unreachable("not reached");
1880 }
1881 } else {
1882 brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
1883 }
1884 break;
1885 case BRW_OPCODE_SEL:
1886 brw_SEL(p, dst, src[0], src[1]);
1887 break;
1888 case BRW_OPCODE_BFREV:
1889 assert(devinfo->gen >= 7);
1890 /* BFREV only supports UD type for src and dst. */
1891 brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
1892 retype(src[0], BRW_REGISTER_TYPE_UD));
1893 break;
1894 case BRW_OPCODE_FBH:
1895 assert(devinfo->gen >= 7);
1896 /* FBH only supports UD type for dst. */
1897 brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1898 break;
1899 case BRW_OPCODE_FBL:
1900 assert(devinfo->gen >= 7);
1901 /* FBL only supports UD type for dst. */
1902 brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1903 break;
1904 case BRW_OPCODE_CBIT:
1905 assert(devinfo->gen >= 7);
1906 /* CBIT only supports UD type for dst. */
1907 brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
1908 break;
1909 case BRW_OPCODE_ADDC:
1910 assert(devinfo->gen >= 7);
1911 brw_ADDC(p, dst, src[0], src[1]);
1912 break;
1913 case BRW_OPCODE_SUBB:
1914 assert(devinfo->gen >= 7);
1915 brw_SUBB(p, dst, src[0], src[1]);
1916 break;
1917 case BRW_OPCODE_MAC:
1918 brw_MAC(p, dst, src[0], src[1]);
1919 break;
1920
1921 case BRW_OPCODE_BFE:
1922 assert(devinfo->gen >= 7);
1923 brw_set_default_access_mode(p, BRW_ALIGN_16);
1924 if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
1925 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1926 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1927 brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1928 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1929 brw_BFE(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1930 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1931 } else {
1932 brw_BFE(p, dst, src[0], src[1], src[2]);
1933 }
1934 brw_set_default_access_mode(p, BRW_ALIGN_1);
1935 break;
1936
1937 case BRW_OPCODE_BFI1:
1938 assert(devinfo->gen >= 7);
1939 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1940 * should
1941 *
1942 * "Force BFI instructions to be executed always in SIMD8."
1943 */
1944 if (dispatch_width == 16 && devinfo->is_haswell) {
1945 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1946 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1947 brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
1948 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1949 brw_BFI1(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]));
1950 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1951 } else {
1952 brw_BFI1(p, dst, src[0], src[1]);
1953 }
1954 break;
1955 case BRW_OPCODE_BFI2:
1956 assert(devinfo->gen >= 7);
1957 brw_set_default_access_mode(p, BRW_ALIGN_16);
1958 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1959 * should
1960 *
1961 * "Force BFI instructions to be executed always in SIMD8."
1962 *
1963 * Otherwise we would be able to emit compressed instructions like we
1964 * do for the other three-source instructions.
1965 */
1966 if (dispatch_width == 16 &&
1967 (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
1968 brw_set_default_exec_size(p, BRW_EXECUTE_8);
1969 brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
1970 brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
1971 brw_set_default_compression_control(p, BRW_COMPRESSION_2NDHALF);
1972 brw_BFI2(p, sechalf(dst), sechalf(src[0]), sechalf(src[1]), sechalf(src[2]));
1973 brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
1974 } else {
1975 brw_BFI2(p, dst, src[0], src[1], src[2]);
1976 }
1977 brw_set_default_access_mode(p, BRW_ALIGN_1);
1978 break;
1979
1980 case BRW_OPCODE_IF:
1981 if (inst->src[0].file != BAD_FILE) {
1982 /* The instruction has an embedded compare (only allowed on gen6) */
1983 assert(devinfo->gen == 6);
1984 gen6_IF(p, inst->conditional_mod, src[0], src[1]);
1985 } else {
1986 brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1987 }
1988 break;
1989
1990 case BRW_OPCODE_ELSE:
1991 brw_ELSE(p);
1992 break;
1993 case BRW_OPCODE_ENDIF:
1994 brw_ENDIF(p);
1995 break;
1996
1997 case BRW_OPCODE_DO:
1998 brw_DO(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
1999 break;
2000
2001 case BRW_OPCODE_BREAK:
2002 brw_BREAK(p);
2003 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2004 break;
2005 case BRW_OPCODE_CONTINUE:
2006 brw_CONT(p);
2007 brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
2008 break;
2009
2010 case BRW_OPCODE_WHILE:
2011 brw_WHILE(p);
2012 loop_count++;
2013 break;
2014
2015 case SHADER_OPCODE_RCP:
2016 case SHADER_OPCODE_RSQ:
2017 case SHADER_OPCODE_SQRT:
2018 case SHADER_OPCODE_EXP2:
2019 case SHADER_OPCODE_LOG2:
2020 case SHADER_OPCODE_SIN:
2021 case SHADER_OPCODE_COS:
2022 assert(devinfo->gen < 6 || inst->mlen == 0);
2023 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2024 if (devinfo->gen >= 7) {
2025 gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
2026 brw_null_reg());
2027 } else if (devinfo->gen == 6) {
2028 generate_math_gen6(inst, dst, src[0], brw_null_reg());
2029 } else if (devinfo->gen == 5 || devinfo->is_g4x) {
2030 generate_math_g45(inst, dst, src[0]);
2031 } else {
2032 generate_math_gen4(inst, dst, src[0]);
2033 }
2034 break;
2035 case SHADER_OPCODE_INT_QUOTIENT:
2036 case SHADER_OPCODE_INT_REMAINDER:
2037 case SHADER_OPCODE_POW:
2038 assert(devinfo->gen < 6 || inst->mlen == 0);
2039 assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
2040 if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
2041 gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
2042 } else if (devinfo->gen >= 6) {
2043 generate_math_gen6(inst, dst, src[0], src[1]);
2044 } else {
2045 generate_math_gen4(inst, dst, src[0]);
2046 }
2047 break;
2048 case FS_OPCODE_CINTERP:
2049 brw_MOV(p, dst, src[0]);
2050 break;
2051 case FS_OPCODE_LINTERP:
2052 generate_linterp(inst, dst, src);
2053 break;
2054 case FS_OPCODE_PIXEL_X:
2055 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2056 src[0].subnr = 0 * type_sz(src[0].type);
2057 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2058 break;
2059 case FS_OPCODE_PIXEL_Y:
2060 assert(src[0].type == BRW_REGISTER_TYPE_UW);
2061 src[0].subnr = 4 * type_sz(src[0].type);
2062 brw_MOV(p, dst, stride(src[0], 8, 4, 1));
2063 break;
2064 case FS_OPCODE_GET_BUFFER_SIZE:
2065 generate_get_buffer_size(inst, dst, src[0], src[1]);
2066 break;
2067 case SHADER_OPCODE_TEX:
2068 case FS_OPCODE_TXB:
2069 case SHADER_OPCODE_TXD:
2070 case SHADER_OPCODE_TXF:
2071 case SHADER_OPCODE_TXF_CMS:
2072 case SHADER_OPCODE_TXF_CMS_W:
2073 case SHADER_OPCODE_TXF_UMS:
2074 case SHADER_OPCODE_TXF_MCS:
2075 case SHADER_OPCODE_TXL:
2076 case SHADER_OPCODE_TXS:
2077 case SHADER_OPCODE_LOD:
2078 case SHADER_OPCODE_TG4:
2079 case SHADER_OPCODE_TG4_OFFSET:
2080 case SHADER_OPCODE_SAMPLEINFO:
2081 generate_tex(inst, dst, src[0], src[1], src[1]);
2082 break;
2083 case FS_OPCODE_DDX_COARSE:
2084 case FS_OPCODE_DDX_FINE:
2085 generate_ddx(inst->opcode, dst, src[0]);
2086 break;
2087 case FS_OPCODE_DDY_COARSE:
2088 case FS_OPCODE_DDY_FINE:
2089 assert(src[1].file == BRW_IMMEDIATE_VALUE);
2090 generate_ddy(inst->opcode, dst, src[0], src[1].ud);
2091 break;
2092
2093 case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
2094 generate_scratch_write(inst, src[0]);
2095 spill_count++;
2096 break;
2097
2098 case SHADER_OPCODE_GEN4_SCRATCH_READ:
2099 generate_scratch_read(inst, dst);
2100 fill_count++;
2101 break;
2102
2103 case SHADER_OPCODE_GEN7_SCRATCH_READ:
2104 generate_scratch_read_gen7(inst, dst);
2105 fill_count++;
2106 break;
2107
2108 case SHADER_OPCODE_MOV_INDIRECT:
2109 generate_mov_indirect(inst, dst, src[0], src[1]);
2110 break;
2111
2112 case SHADER_OPCODE_URB_READ_SIMD8:
2113 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT:
2114 generate_urb_read(inst, dst, src[0]);
2115 break;
2116
2117 case SHADER_OPCODE_URB_WRITE_SIMD8:
2118 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT:
2119 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED:
2120 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT:
2121 generate_urb_write(inst, src[0]);
2122 break;
2123
2124 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
2125 generate_uniform_pull_constant_load(inst, dst, src[0], src[1]);
2126 break;
2127
2128 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
2129 generate_uniform_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2130 break;
2131
2132 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
2133 generate_varying_pull_constant_load(inst, dst, src[0], src[1]);
2134 break;
2135
2136 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7:
2137 generate_varying_pull_constant_load_gen7(inst, dst, src[0], src[1]);
2138 break;
2139
2140 case FS_OPCODE_REP_FB_WRITE:
2141 case FS_OPCODE_FB_WRITE:
2142 generate_fb_write(inst, src[0]);
2143 break;
2144
2145 case FS_OPCODE_BLORP_FB_WRITE:
2146 generate_blorp_fb_write(inst);
2147 break;
2148
2149 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS:
2150 generate_mov_dispatch_to_flags(inst);
2151 break;
2152
2153 case FS_OPCODE_DISCARD_JUMP:
2154 generate_discard_jump(inst);
2155 break;
2156
2157 case SHADER_OPCODE_SHADER_TIME_ADD:
2158 generate_shader_time_add(inst, src[0], src[1], src[2]);
2159 break;
2160
2161 case SHADER_OPCODE_UNTYPED_ATOMIC:
2162 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2163 brw_untyped_atomic(p, dst, src[0], src[1], src[2].ud,
2164 inst->mlen, !inst->dst.is_null());
2165 break;
2166
2167 case SHADER_OPCODE_UNTYPED_SURFACE_READ:
2168 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2169 brw_untyped_surface_read(p, dst, src[0], src[1],
2170 inst->mlen, src[2].ud);
2171 break;
2172
2173 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
2174 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2175 brw_untyped_surface_write(p, src[0], src[1],
2176 inst->mlen, src[2].ud);
2177 break;
2178
2179 case SHADER_OPCODE_TYPED_ATOMIC:
2180 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2181 brw_typed_atomic(p, dst, src[0], src[1],
2182 src[2].ud, inst->mlen, !inst->dst.is_null());
2183 break;
2184
2185 case SHADER_OPCODE_TYPED_SURFACE_READ:
2186 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2187 brw_typed_surface_read(p, dst, src[0], src[1],
2188 inst->mlen, src[2].ud);
2189 break;
2190
2191 case SHADER_OPCODE_TYPED_SURFACE_WRITE:
2192 assert(src[2].file == BRW_IMMEDIATE_VALUE);
2193 brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].ud);
2194 break;
2195
2196 case SHADER_OPCODE_MEMORY_FENCE:
2197 brw_memory_fence(p, dst);
2198 break;
2199
2200 case FS_OPCODE_SET_SIMD4X2_OFFSET:
2201 generate_set_simd4x2_offset(inst, dst, src[0]);
2202 break;
2203
2204 case SHADER_OPCODE_FIND_LIVE_CHANNEL:
2205 brw_find_live_channel(p, dst);
2206 break;
2207
2208 case SHADER_OPCODE_BROADCAST:
2209 brw_broadcast(p, dst, src[0], src[1]);
2210 break;
2211
2212 case SHADER_OPCODE_EXTRACT_BYTE: {
2213 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2214 src[0].type == BRW_REGISTER_TYPE_UD);
2215
2216 enum brw_reg_type type =
2217 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
2218 : BRW_REGISTER_TYPE_UB;
2219 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
2220 break;
2221 }
2222
2223 case SHADER_OPCODE_EXTRACT_WORD: {
2224 assert(src[0].type == BRW_REGISTER_TYPE_D ||
2225 src[0].type == BRW_REGISTER_TYPE_UD);
2226
2227 enum brw_reg_type type =
2228 src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
2229 : BRW_REGISTER_TYPE_UW;
2230 brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
2231 break;
2232 }
2233
2234 case FS_OPCODE_SET_SAMPLE_ID:
2235 generate_set_sample_id(inst, dst, src[0], src[1]);
2236 break;
2237
2238 case FS_OPCODE_PACK_HALF_2x16_SPLIT:
2239 generate_pack_half_2x16_split(inst, dst, src[0], src[1]);
2240 break;
2241
2242 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X:
2243 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y:
2244 generate_unpack_half_2x16_split(inst, dst, src[0]);
2245 break;
2246
2247 case FS_OPCODE_PLACEHOLDER_HALT:
2248 /* This is the place where the final HALT needs to be inserted if
2249 * we've emitted any discards. If not, this will emit no code.
2250 */
2251 if (!patch_discard_jumps_to_fb_writes()) {
2252 if (unlikely(debug_flag)) {
2253 annotation.ann_count--;
2254 }
2255 }
2256 break;
2257
2258 case FS_OPCODE_INTERPOLATE_AT_CENTROID:
2259 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2260 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID);
2261 break;
2262
2263 case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
2264 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2265 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE);
2266 break;
2267
2268 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
2269 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2270 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET);
2271 break;
2272
2273 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
2274 generate_pixel_interpolator_query(inst, dst, src[0], src[1],
2275 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
2276 break;
2277
2278 case CS_OPCODE_CS_TERMINATE:
2279 generate_cs_terminate(inst, src[0]);
2280 break;
2281
2282 case SHADER_OPCODE_BARRIER:
2283 generate_barrier(inst, src[0]);
2284 break;
2285
2286 case FS_OPCODE_PACK_STENCIL_REF:
2287 generate_stencil_ref_packing(inst, dst, src[0]);
2288 break;
2289
2290 default:
2291 unreachable("Unsupported opcode");
2292
2293 case SHADER_OPCODE_LOAD_PAYLOAD:
2294 unreachable("Should be lowered by lower_load_payload()");
2295 }
2296
2297 if (multiple_instructions_emitted)
2298 continue;
2299
2300 if (inst->no_dd_clear || inst->no_dd_check || inst->conditional_mod) {
2301 assert(p->next_insn_offset == last_insn_offset + 16 ||
2302 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2303 "emitting more than 1 instruction");
2304
2305 brw_inst *last = &p->store[last_insn_offset / 16];
2306
2307 if (inst->conditional_mod)
2308 brw_inst_set_cond_modifier(p->devinfo, last, inst->conditional_mod);
2309 brw_inst_set_no_dd_clear(p->devinfo, last, inst->no_dd_clear);
2310 brw_inst_set_no_dd_check(p->devinfo, last, inst->no_dd_check);
2311 }
2312 }
2313
2314 brw_set_uip_jip(p);
2315 annotation_finalize(&annotation, p->next_insn_offset);
2316
2317 #ifndef NDEBUG
2318 bool validated = brw_validate_instructions(p, start_offset, &annotation);
2319 #else
2320 if (unlikely(debug_flag))
2321 brw_validate_instructions(p, start_offset, &annotation);
2322 #endif
2323
2324 int before_size = p->next_insn_offset - start_offset;
2325 brw_compact_instructions(p, start_offset, annotation.ann_count,
2326 annotation.ann);
2327 int after_size = p->next_insn_offset - start_offset;
2328
2329 if (unlikely(debug_flag)) {
2330 fprintf(stderr, "Native code for %s\n"
2331 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2332 " bytes (%.0f%%)\n",
2333 shader_name, dispatch_width, before_size / 16, loop_count, cfg->cycle_count,
2334 spill_count, fill_count, promoted_constants, before_size, after_size,
2335 100.0f * (before_size - after_size) / before_size);
2336
2337 dump_assembly(p->store, annotation.ann_count, annotation.ann,
2338 p->devinfo);
2339 ralloc_free(annotation.mem_ctx);
2340 }
2341 assert(validated);
2342
2343 compiler->shader_debug_log(log_data,
2344 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2345 "%d:%d spills:fills, Promoted %u constants, "
2346 "compacted %d to %d bytes.",
2347 _mesa_shader_stage_to_abbrev(stage),
2348 dispatch_width, before_size / 16,
2349 loop_count, cfg->cycle_count, spill_count,
2350 fill_count, promoted_constants, before_size,
2351 after_size);
2352
2353 return start_offset;
2354 }
2355
2356 const unsigned *
2357 fs_generator::get_assembly(unsigned int *assembly_size)
2358 {
2359 return brw_get_program(p, assembly_size);
2360 }