2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "brw_program.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct brw_codegen
*p
,
58 fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 } else if (!p
->compressed
&&
70 inst
->exec_size
* reg
->stride
* type_sz(reg
->type
) <= 32) {
71 brw_reg
= brw_vecn_reg(inst
->exec_size
, brw_file_from_reg(reg
),
73 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
74 inst
->exec_size
, reg
->stride
);
76 /* From the Haswell PRM:
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
85 assert(inst
->exec_size
/ 2 * reg
->stride
* type_sz(reg
->type
) <= 32);
86 brw_reg
= brw_vecn_reg(inst
->exec_size
/ 2, brw_file_from_reg(reg
),
88 brw_reg
= stride(brw_reg
, inst
->exec_size
/ 2 * reg
->stride
,
89 inst
->exec_size
/ 2, reg
->stride
);
92 brw_reg
= retype(brw_reg
, reg
->type
);
93 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
94 brw_reg
.abs
= reg
->abs
;
95 brw_reg
.negate
= reg
->negate
;
100 brw_reg
= reg
->as_brw_reg();
103 /* Probably unused. */
104 brw_reg
= brw_null_reg();
108 unreachable("not reached");
114 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
117 struct brw_stage_prog_data
*prog_data
,
118 unsigned promoted_constants
,
119 bool runtime_check_aads_emit
,
120 gl_shader_stage stage
)
122 : compiler(compiler
), log_data(log_data
),
123 devinfo(compiler
->devinfo
), key(key
),
124 prog_data(prog_data
),
125 promoted_constants(promoted_constants
),
126 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
127 stage(stage
), mem_ctx(mem_ctx
)
129 p
= rzalloc(mem_ctx
, struct brw_codegen
);
130 brw_init_codegen(devinfo
, p
, mem_ctx
);
133 fs_generator::~fs_generator()
137 class ip_record
: public exec_node
{
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
150 fs_generator::patch_discard_jumps_to_fb_writes()
152 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
155 int scale
= brw_jump_scale(p
->devinfo
);
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
168 brw_inst
*last_halt
= gen6_HALT(p
);
169 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
170 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
174 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
175 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
177 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
182 this->discard_halt_patches
.make_empty();
187 fs_generator::fire_fb_write(fs_inst
*inst
,
188 struct brw_reg payload
,
189 struct brw_reg implied_header
,
192 uint32_t msg_control
;
194 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
196 if (devinfo
->gen
< 6) {
197 brw_push_insn_state(p
);
198 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
199 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
200 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
201 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
202 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p
);
206 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
207 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
208 else if (prog_data
->dual_src_blend
) {
209 if (!inst
->force_sechalf
)
210 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
212 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
213 } else if (inst
->exec_size
== 16)
214 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
216 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
218 uint32_t surf_index
=
219 prog_data
->binding_table
.render_target_start
+ inst
->target
;
221 bool last_render_target
= inst
->eot
||
222 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
235 inst
->header_size
!= 0);
237 brw_mark_surface_used(&prog_data
->base
, surf_index
);
241 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
243 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
244 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
245 struct brw_reg implied_header
;
247 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
248 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
251 if (inst
->base_mrf
>= 0)
252 payload
= brw_message_reg(inst
->base_mrf
);
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
257 if (inst
->header_size
!= 0) {
258 brw_push_insn_state(p
);
259 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
260 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
262 brw_set_default_flag_reg(p
, 0, 0);
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
267 if (prog_data
->uses_kill
) {
268 struct brw_reg pixel_mask
;
270 if (devinfo
->gen
>= 6)
271 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
273 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
275 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
278 if (devinfo
->gen
>= 6) {
279 brw_push_insn_state(p
);
280 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
281 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
283 retype(payload
, BRW_REGISTER_TYPE_UD
),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
285 brw_pop_insn_state(p
);
287 if (inst
->target
> 0 && key
->replicate_alpha
) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
292 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
294 brw_imm_ud(0x1 << 11));
297 if (inst
->target
> 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
300 BRW_REGISTER_TYPE_UD
),
301 brw_imm_ud(inst
->target
));
304 /* Set computes stencil to render target */
305 if (prog_data
->computed_stencil
) {
307 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
309 brw_imm_ud(0x1 << 14));
312 implied_header
= brw_null_reg();
314 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
317 brw_pop_insn_state(p
);
319 implied_header
= brw_null_reg();
322 if (!runtime_check_aads_emit
) {
323 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
325 /* This can only happen in gen < 6 */
326 assert(devinfo
->gen
< 6);
328 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
336 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
338 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
339 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
341 /* Don't send AA data */
342 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
344 brw_land_fwd_jump(p
, jmp
);
345 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
350 fs_generator::generate_mov_indirect(fs_inst
*inst
,
353 struct brw_reg indirect_byte_offset
)
355 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
356 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
358 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
360 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
361 imm_byte_offset
+= indirect_byte_offset
.ud
;
363 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
364 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
365 brw_MOV(p
, dst
, reg
);
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst
->exec_size
== 8 || devinfo
->gen
>= 8);
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr
= vec8(brw_address_reg(0));
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
378 indirect_byte_offset
=
379 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
381 struct brw_reg ind_src
;
382 if (devinfo
->gen
< 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
403 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
404 ind_src
= brw_VxH_indirect(0, 0);
406 brw_MOV(p
, addr
, indirect_byte_offset
);
407 ind_src
= brw_VxH_indirect(0, imm_byte_offset
);
410 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, dst
.type
));
412 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
413 !inst
->get_next()->is_tail_sentinel() &&
414 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
415 /* From the Sandybridge PRM:
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
422 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
428 fs_generator::generate_urb_read(fs_inst
*inst
,
430 struct brw_reg header
)
432 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
433 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
435 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
436 brw_set_dest(p
, send
, dst
);
437 brw_set_src0(p
, send
, header
);
438 brw_set_src1(p
, send
, brw_imm_ud(0u));
440 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
441 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
443 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
444 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
446 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
447 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
448 brw_inst_set_header_present(p
->devinfo
, send
, true);
449 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
453 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
457 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
459 brw_set_dest(p
, insn
, brw_null_reg());
460 brw_set_src0(p
, insn
, payload
);
461 brw_set_src1(p
, insn
, brw_imm_d(0));
463 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
464 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
466 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
467 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
468 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
470 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
471 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
472 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
474 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
475 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
476 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
477 brw_inst_set_header_present(p
->devinfo
, insn
, true);
478 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
482 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
484 struct brw_inst
*insn
;
486 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
488 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
489 brw_set_src0(p
, insn
, payload
);
490 brw_set_src1(p
, insn
, brw_imm_d(0));
492 /* Terminate a compute shader by sending a message to the thread spawner.
494 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
495 brw_inst_set_mlen(devinfo
, insn
, 1);
496 brw_inst_set_rlen(devinfo
, insn
, 0);
497 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
498 brw_inst_set_header_present(devinfo
, insn
, false);
500 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
507 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
509 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
513 fs_generator::generate_stencil_ref_packing(fs_inst
*inst
,
517 assert(dispatch_width
== 8);
518 assert(devinfo
->gen
>= 9);
520 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
521 * Presumably, in order to save memory bandwidth, the stencil reference
522 * values written from the FS need to be packed into 2 dwords (this makes
523 * sense because the stencil values are limited to 1 byte each and a SIMD8
524 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
526 * The spec is confusing here because in the payload definition of MDP_RTW_S8
527 * (Message Data Payload for Render Target Writes with Stencil 8b) the
528 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
529 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
530 * packed values specified above and diagrammed below:
533 * --------------------------------
537 * --------------------------------
538 * DW1 | STC | STC | STC | STC |
539 * | slot7 | slot6 | slot5 | slot4|
540 * --------------------------------
541 * DW0 | STC | STC | STC | STC |
542 * | slot3 | slot2 | slot1 | slot0|
543 * --------------------------------
546 src
.vstride
= BRW_VERTICAL_STRIDE_4
;
547 src
.width
= BRW_WIDTH_1
;
548 src
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
549 assert(src
.type
== BRW_REGISTER_TYPE_UB
);
550 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UB
), src
);
554 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
561 fs_generator::generate_linterp(fs_inst
*inst
,
562 struct brw_reg dst
, struct brw_reg
*src
)
566 * -----------------------------------
567 * | src1+0 | src1+1 | src1+2 | src1+3 |
568 * |-----------------------------------|
569 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
570 * -----------------------------------
572 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
574 * -----------------------------------
575 * | src1+0 | src1+1 | src1+2 | src1+3 |
576 * |-----------------------------------|
577 * |(x0, x1)|(y0, y1)| | | in SIMD8
578 * |-----------------------------------|
579 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
580 * -----------------------------------
582 * See also: emit_interpolation_setup_gen4().
584 struct brw_reg delta_x
= src
[0];
585 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
586 struct brw_reg interp
= src
[1];
588 if (devinfo
->has_pln
&&
589 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
590 brw_PLN(p
, dst
, interp
, delta_x
);
592 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
593 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
598 fs_generator::generate_math_gen6(fs_inst
*inst
,
603 int op
= brw_math_function(inst
->opcode
);
604 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
606 if (dispatch_width
== 8) {
607 gen6_math(p
, dst
, op
, src0
, src1
);
608 } else if (dispatch_width
== 16) {
609 brw_push_insn_state(p
);
610 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
611 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
612 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
613 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
614 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
615 binop
? sechalf(src1
) : brw_null_reg());
616 brw_pop_insn_state(p
);
621 fs_generator::generate_math_gen4(fs_inst
*inst
,
625 int op
= brw_math_function(inst
->opcode
);
627 assert(inst
->mlen
>= 1);
629 if (dispatch_width
== 8) {
633 BRW_MATH_PRECISION_FULL
);
634 } else if (dispatch_width
== 16) {
635 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
636 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
637 gen4_math(p
, firsthalf(dst
),
639 inst
->base_mrf
, firsthalf(src
),
640 BRW_MATH_PRECISION_FULL
);
641 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
642 gen4_math(p
, sechalf(dst
),
644 inst
->base_mrf
+ 1, sechalf(src
),
645 BRW_MATH_PRECISION_FULL
);
647 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
652 fs_generator::generate_math_g45(fs_inst
*inst
,
656 if (inst
->opcode
== SHADER_OPCODE_POW
||
657 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
658 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
659 generate_math_gen4(inst
, dst
, src
);
663 int op
= brw_math_function(inst
->opcode
);
665 assert(inst
->mlen
>= 1);
670 BRW_MATH_PRECISION_FULL
);
674 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
677 struct brw_reg surf_index
)
679 assert(devinfo
->gen
>= 7);
680 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
685 switch (inst
->exec_size
) {
687 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
690 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
693 unreachable("Invalid width for texture instruction");
696 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
702 retype(dst
, BRW_REGISTER_TYPE_UW
),
707 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
708 rlen
, /* response length */
710 inst
->header_size
> 0,
712 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
714 brw_mark_surface_used(prog_data
, surf_index
.ud
);
718 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
719 struct brw_reg surface_index
,
720 struct brw_reg sampler_index
)
724 uint32_t return_format
;
725 bool is_combined_send
= inst
->eot
;
728 case BRW_REGISTER_TYPE_D
:
729 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
731 case BRW_REGISTER_TYPE_UD
:
732 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
735 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
739 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
740 * is set as part of the message descriptor. On gen4, the PRM seems to
741 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
742 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
743 * gone from the message descriptor entirely and you just get UINT32 all
744 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
745 * just stomp it to UINT32 all the time.
747 if (inst
->opcode
== SHADER_OPCODE_TXS
)
748 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
750 switch (inst
->exec_size
) {
752 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
755 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
758 unreachable("Invalid width for texture instruction");
761 if (devinfo
->gen
>= 5) {
762 switch (inst
->opcode
) {
763 case SHADER_OPCODE_TEX
:
764 if (inst
->shadow_compare
) {
765 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
767 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
771 if (inst
->shadow_compare
) {
772 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
774 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
777 case SHADER_OPCODE_TXL
:
778 if (inst
->shadow_compare
) {
779 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
781 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
784 case SHADER_OPCODE_TXL_LZ
:
785 assert(devinfo
->gen
>= 9);
786 if (inst
->shadow_compare
) {
787 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_C_LZ
;
789 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LZ
;
792 case SHADER_OPCODE_TXS
:
793 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
795 case SHADER_OPCODE_TXD
:
796 if (inst
->shadow_compare
) {
797 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
798 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
799 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
801 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
804 case SHADER_OPCODE_TXF
:
805 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
807 case SHADER_OPCODE_TXF_LZ
:
808 assert(devinfo
->gen
>= 9);
809 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD_LZ
;
811 case SHADER_OPCODE_TXF_CMS_W
:
812 assert(devinfo
->gen
>= 9);
813 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
815 case SHADER_OPCODE_TXF_CMS
:
816 if (devinfo
->gen
>= 7)
817 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
819 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
821 case SHADER_OPCODE_TXF_UMS
:
822 assert(devinfo
->gen
>= 7);
823 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
825 case SHADER_OPCODE_TXF_MCS
:
826 assert(devinfo
->gen
>= 7);
827 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
829 case SHADER_OPCODE_LOD
:
830 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
832 case SHADER_OPCODE_TG4
:
833 if (inst
->shadow_compare
) {
834 assert(devinfo
->gen
>= 7);
835 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
837 assert(devinfo
->gen
>= 6);
838 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
841 case SHADER_OPCODE_TG4_OFFSET
:
842 assert(devinfo
->gen
>= 7);
843 if (inst
->shadow_compare
) {
844 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
846 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
849 case SHADER_OPCODE_SAMPLEINFO
:
850 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
853 unreachable("not reached");
856 switch (inst
->opcode
) {
857 case SHADER_OPCODE_TEX
:
858 /* Note that G45 and older determines shadow compare and dispatch width
859 * from message length for most messages.
861 if (inst
->exec_size
== 8) {
862 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
863 if (inst
->shadow_compare
) {
864 assert(inst
->mlen
== 6);
866 assert(inst
->mlen
<= 4);
869 if (inst
->shadow_compare
) {
870 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
871 assert(inst
->mlen
== 9);
873 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
874 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
879 if (inst
->shadow_compare
) {
880 assert(inst
->exec_size
== 8);
881 assert(inst
->mlen
== 6);
882 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
884 assert(inst
->mlen
== 9);
885 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
886 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
889 case SHADER_OPCODE_TXL
:
890 if (inst
->shadow_compare
) {
891 assert(inst
->exec_size
== 8);
892 assert(inst
->mlen
== 6);
893 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
895 assert(inst
->mlen
== 9);
896 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
897 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
900 case SHADER_OPCODE_TXD
:
901 /* There is no sample_d_c message; comparisons are done manually */
902 assert(inst
->exec_size
== 8);
903 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
904 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
906 case SHADER_OPCODE_TXF
:
907 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
908 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
909 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
911 case SHADER_OPCODE_TXS
:
912 assert(inst
->mlen
== 3);
913 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
914 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
917 unreachable("not reached");
920 assert(msg_type
!= -1);
922 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
926 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
927 src
.file
== BRW_GENERAL_REGISTER_FILE
);
929 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
931 /* Load the message header if present. If there's a texture offset,
932 * we need to set it up explicitly and load the offset bitfield.
933 * Otherwise, we can use an implied move from g0 to the first message reg.
935 if (inst
->header_size
!= 0) {
936 if (devinfo
->gen
< 6 && !inst
->offset
) {
937 /* Set up an implied move from g0 to the MRF. */
938 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
940 struct brw_reg header_reg
;
942 if (devinfo
->gen
>= 7) {
945 assert(inst
->base_mrf
!= -1);
946 header_reg
= brw_message_reg(inst
->base_mrf
);
949 brw_push_insn_state(p
);
950 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
951 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
952 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
953 /* Explicitly set up the message header by copying g0 to the MRF. */
954 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
957 /* Set the offset bits in DWord 2. */
958 brw_MOV(p
, get_element_ud(header_reg
, 2),
959 brw_imm_ud(inst
->offset
));
960 } else if (stage
!= MESA_SHADER_VERTEX
&&
961 stage
!= MESA_SHADER_FRAGMENT
) {
962 /* The vertex and fragment stages have g0.2 set to 0, so
963 * header0.2 is 0 when g0 is copied. Other stages may not, so we
964 * must set it to 0 to avoid setting undesirable bits in the
967 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
970 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
971 brw_pop_insn_state(p
);
975 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
976 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
977 ? prog_data
->binding_table
.gather_texture_start
978 : prog_data
->binding_table
.texture_start
;
980 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
981 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
982 uint32_t surface
= surface_index
.ud
;
983 uint32_t sampler
= sampler_index
.ud
;
986 retype(dst
, BRW_REGISTER_TYPE_UW
),
989 surface
+ base_binding_table_index
,
994 inst
->header_size
!= 0,
998 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
1000 /* Non-const sampler index */
1002 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1003 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
1004 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
1006 brw_push_insn_state(p
);
1007 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1008 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1010 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
1011 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1013 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1014 brw_OR(p
, addr
, addr
, surface_reg
);
1016 if (base_binding_table_index
)
1017 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1018 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1020 brw_pop_insn_state(p
);
1022 /* dst = send(offset, a0.0 | <descriptor>) */
1023 brw_inst
*insn
= brw_send_indirect_message(
1024 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1025 brw_set_sampler_message(p
, insn
,
1030 inst
->mlen
/* mlen */,
1031 inst
->header_size
!= 0 /* header */,
1035 /* visitor knows more than we do about the surface limit required,
1036 * so has already done marking.
1040 if (is_combined_send
) {
1041 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1042 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1047 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1050 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1052 * Ideally, we want to produce:
1055 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1056 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1057 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1058 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1059 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1060 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1061 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1062 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1064 * and add another set of two more subspans if in 16-pixel dispatch mode.
1066 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1067 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1068 * pair. But the ideal approximation may impose a huge performance cost on
1069 * sample_d. On at least Haswell, sample_d instruction does some
1070 * optimizations if the same LOD is used for all pixels in the subspan.
1072 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1073 * appropriate swizzling.
1076 fs_generator::generate_ddx(enum opcode opcode
,
1077 struct brw_reg dst
, struct brw_reg src
)
1079 unsigned vstride
, width
;
1081 if (opcode
== FS_OPCODE_DDX_FINE
) {
1082 /* produce accurate derivatives */
1083 vstride
= BRW_VERTICAL_STRIDE_2
;
1084 width
= BRW_WIDTH_2
;
1086 /* replicate the derivative at the top-left pixel to other pixels */
1087 vstride
= BRW_VERTICAL_STRIDE_4
;
1088 width
= BRW_WIDTH_4
;
1091 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1092 src
.negate
, src
.abs
,
1093 BRW_REGISTER_TYPE_F
,
1096 BRW_HORIZONTAL_STRIDE_0
,
1097 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1098 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1099 src
.negate
, src
.abs
,
1100 BRW_REGISTER_TYPE_F
,
1103 BRW_HORIZONTAL_STRIDE_0
,
1104 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1105 brw_ADD(p
, dst
, src0
, negate(src1
));
1108 /* The negate_value boolean is used to negate the derivative computation for
1109 * FBOs, since they place the origin at the upper left instead of the lower
1113 fs_generator::generate_ddy(enum opcode opcode
,
1114 struct brw_reg dst
, struct brw_reg src
)
1116 if (opcode
== FS_OPCODE_DDY_FINE
) {
1117 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1118 * Region Restrictions):
1120 * In Align16 access mode, SIMD16 is not allowed for DW operations
1121 * and SIMD8 is not allowed for DF operations.
1123 * In this context, "DW operations" means "operations acting on 32-bit
1124 * values", so it includes operations on floats.
1126 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1127 * (Instruction Compression -> Rules and Restrictions):
1129 * A compressed instruction must be in Align1 access mode. Align16
1130 * mode instructions cannot be compressed.
1132 * Similar text exists in the g45 PRM.
1134 * Empirically, compressed align16 instructions using odd register
1135 * numbers don't appear to work on Sandybridge either.
1137 * On these platforms, if we're building a SIMD16 shader, we need to
1138 * manually unroll to a pair of SIMD8 instructions.
1140 bool unroll_to_simd8
=
1141 (dispatch_width
== 16 &&
1142 (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
1143 (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
1145 /* produce accurate derivatives */
1146 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1147 src
.negate
, src
.abs
,
1148 BRW_REGISTER_TYPE_F
,
1149 BRW_VERTICAL_STRIDE_4
,
1151 BRW_HORIZONTAL_STRIDE_1
,
1152 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1153 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1154 src
.negate
, src
.abs
,
1155 BRW_REGISTER_TYPE_F
,
1156 BRW_VERTICAL_STRIDE_4
,
1158 BRW_HORIZONTAL_STRIDE_1
,
1159 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1160 brw_push_insn_state(p
);
1161 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1162 if (unroll_to_simd8
) {
1163 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1164 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1165 brw_ADD(p
, firsthalf(dst
), negate(firsthalf(src0
)), firsthalf(src1
));
1166 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1167 brw_ADD(p
, sechalf(dst
), negate(sechalf(src0
)), sechalf(src1
));
1169 brw_ADD(p
, dst
, negate(src0
), src1
);
1171 brw_pop_insn_state(p
);
1173 /* replicate the derivative at the top-left pixel to other pixels */
1174 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1175 src
.negate
, src
.abs
,
1176 BRW_REGISTER_TYPE_F
,
1177 BRW_VERTICAL_STRIDE_4
,
1179 BRW_HORIZONTAL_STRIDE_0
,
1180 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1181 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1182 src
.negate
, src
.abs
,
1183 BRW_REGISTER_TYPE_F
,
1184 BRW_VERTICAL_STRIDE_4
,
1186 BRW_HORIZONTAL_STRIDE_0
,
1187 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1188 brw_ADD(p
, dst
, negate(src0
), src1
);
1193 fs_generator::generate_discard_jump(fs_inst
*inst
)
1195 assert(devinfo
->gen
>= 6);
1197 /* This HALT will be patched up at FB write time to point UIP at the end of
1198 * the program, and at brw_uip_jip() JIP will be set to the end of the
1199 * current block (or the program).
1201 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1203 brw_push_insn_state(p
);
1204 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1206 brw_pop_insn_state(p
);
1210 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1212 assert(inst
->mlen
!= 0);
1215 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1216 retype(src
, BRW_REGISTER_TYPE_UD
));
1217 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1218 inst
->exec_size
/ 8, inst
->offset
);
1222 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1224 assert(inst
->mlen
!= 0);
1226 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1227 inst
->exec_size
/ 8, inst
->offset
);
1231 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1233 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1237 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1239 struct brw_reg index
,
1240 struct brw_reg offset
)
1242 assert(inst
->mlen
!= 0);
1244 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1245 index
.type
== BRW_REGISTER_TYPE_UD
);
1246 uint32_t surf_index
= index
.ud
;
1248 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1249 offset
.type
== BRW_REGISTER_TYPE_UD
);
1250 uint32_t read_offset
= offset
.ud
;
1252 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1253 read_offset
, surf_index
);
1257 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1259 struct brw_reg index
,
1260 struct brw_reg offset
)
1262 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1264 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1265 /* Reference just the dword we need, to avoid angering validate_reg(). */
1266 offset
= brw_vec1_grf(offset
.nr
, 0);
1268 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1269 * the destination loaded consecutively from the same offset (which appears
1270 * in the first component, and the rest are ignored).
1272 dst
.width
= BRW_WIDTH_4
;
1274 struct brw_reg src
= offset
;
1275 bool header_present
= false;
1277 if (devinfo
->gen
>= 9) {
1278 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1279 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1280 header_present
= true;
1282 brw_push_insn_state(p
);
1283 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1284 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1285 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1286 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1288 brw_MOV(p
, get_element_ud(src
, 2),
1289 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1290 brw_pop_insn_state(p
);
1293 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1295 uint32_t surf_index
= index
.ud
;
1297 brw_push_insn_state(p
);
1298 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1299 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1300 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1301 brw_inst_set_exec_size(devinfo
, send
, BRW_EXECUTE_4
);
1302 brw_pop_insn_state(p
);
1304 brw_set_dest(p
, send
, dst
);
1305 brw_set_src0(p
, send
, src
);
1306 brw_set_sampler_message(p
, send
,
1308 0, /* LD message ignores sampler unit */
1309 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1313 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1317 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1319 brw_push_insn_state(p
);
1320 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1321 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1323 /* a0.0 = surf_index & 0xff */
1324 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1325 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1326 brw_set_dest(p
, insn_and
, addr
);
1327 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1328 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1330 /* dst = send(payload, a0.0 | <descriptor>) */
1331 brw_inst
*insn
= brw_send_indirect_message(
1332 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1333 brw_set_sampler_message(p
, insn
,
1335 0, /* LD message ignores sampler unit */
1336 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1340 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1343 brw_pop_insn_state(p
);
1348 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1350 struct brw_reg index
)
1352 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1353 assert(inst
->header_size
!= 0);
1356 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1357 index
.type
== BRW_REGISTER_TYPE_UD
);
1358 uint32_t surf_index
= index
.ud
;
1360 uint32_t simd_mode
, rlen
, msg_type
;
1361 if (dispatch_width
== 16) {
1362 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1365 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1369 if (devinfo
->gen
>= 5)
1370 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1372 /* We always use the SIMD16 message so that we only have to load U, and
1375 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1376 assert(inst
->mlen
== 3);
1377 assert(inst
->regs_written
== 8);
1379 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1382 struct brw_reg header
= brw_vec8_grf(0, 0);
1383 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1385 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1386 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1387 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1388 brw_set_src0(p
, send
, header
);
1389 if (devinfo
->gen
< 6)
1390 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1392 /* Our surface is set up as floats, regardless of what actual data is
1395 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1396 brw_set_sampler_message(p
, send
,
1398 0, /* sampler (unused) */
1402 inst
->header_size
!= 0,
1408 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1410 struct brw_reg index
,
1411 struct brw_reg offset
)
1413 assert(devinfo
->gen
>= 7);
1414 /* Varying-offset pull constant loads are treated as a normal expression on
1415 * gen7, so the fact that it's a send message is hidden at the IR level.
1417 assert(inst
->header_size
== 0);
1418 assert(!inst
->mlen
);
1419 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1421 uint32_t simd_mode
, rlen
, mlen
;
1422 if (dispatch_width
== 16) {
1425 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1429 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1432 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1434 uint32_t surf_index
= index
.ud
;
1436 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1437 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1438 brw_set_src0(p
, send
, offset
);
1439 brw_set_sampler_message(p
, send
,
1441 0, /* LD message ignores sampler unit */
1442 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1445 false, /* no header */
1451 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1453 brw_push_insn_state(p
);
1454 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1455 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1457 /* a0.0 = surf_index & 0xff */
1458 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1459 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1460 brw_set_dest(p
, insn_and
, addr
);
1461 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1462 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1464 brw_pop_insn_state(p
);
1466 /* dst = send(offset, a0.0 | <descriptor>) */
1467 brw_inst
*insn
= brw_send_indirect_message(
1468 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1470 brw_set_sampler_message(p
, insn
,
1473 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1483 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1484 * into the flags register (f0.0).
1486 * Used only on Gen6 and above.
1489 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1491 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1492 struct brw_reg dispatch_mask
;
1494 if (devinfo
->gen
>= 6)
1495 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1497 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1499 brw_push_insn_state(p
);
1500 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1501 brw_MOV(p
, flags
, dispatch_mask
);
1502 brw_pop_insn_state(p
);
1506 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1509 struct brw_reg msg_data
,
1512 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1514 brw_pixel_interpolator_query(p
,
1515 retype(dst
, BRW_REGISTER_TYPE_UW
),
1517 inst
->pi_noperspective
,
1521 inst
->regs_written
);
1526 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1527 * sampler LD messages.
1529 * We don't want to bake it into the send message's code generation because
1530 * that means we don't get a chance to schedule the instructions.
1533 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1535 struct brw_reg value
)
1537 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1539 brw_push_insn_state(p
);
1540 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1541 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1542 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1543 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1544 brw_pop_insn_state(p
);
1547 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1548 * the ADD instruction.
1551 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1553 struct brw_reg src0
,
1554 struct brw_reg src1
)
1556 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1557 dst
.type
== BRW_REGISTER_TYPE_UD
);
1558 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1559 src0
.type
== BRW_REGISTER_TYPE_UD
);
1561 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1562 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1563 brw_ADD(p
, dst
, src0
, reg
);
1564 } else if (dispatch_width
== 16) {
1565 brw_push_insn_state(p
);
1566 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1567 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1568 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1569 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1570 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1571 brw_pop_insn_state(p
);
1576 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1581 assert(devinfo
->gen
>= 7);
1582 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1583 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1584 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1586 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1588 * Because this instruction does not have a 16-bit floating-point type,
1589 * the destination data type must be Word (W).
1591 * The destination must be DWord-aligned and specify a horizontal stride
1592 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1593 * each destination channel and the upper word is not modified.
1595 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1597 /* Give each 32-bit channel of dst the form below, where "." means
1601 brw_F32TO16(p
, dst_w
, y
);
1606 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1608 /* And, finally the form of packHalf2x16's output:
1611 brw_F32TO16(p
, dst_w
, x
);
1615 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1619 assert(devinfo
->gen
>= 7);
1620 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1621 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1623 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1625 * Because this instruction does not have a 16-bit floating-point type,
1626 * the source data type must be Word (W). The destination type must be
1629 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1631 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1632 * For the Y case, we wish to access only the upper word; therefore
1633 * a 16-bit subregister offset is needed.
1635 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1636 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1637 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1640 brw_F16TO32(p
, dst
, src_w
);
1644 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1645 struct brw_reg payload
,
1646 struct brw_reg offset
,
1647 struct brw_reg value
)
1649 assert(devinfo
->gen
>= 7);
1650 brw_push_insn_state(p
);
1651 brw_set_default_mask_control(p
, true);
1653 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1654 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1656 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1659 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1660 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1661 value
.width
= BRW_WIDTH_1
;
1662 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1663 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1665 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1668 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1669 * case, and we don't really care about squeezing every bit of performance
1670 * out of this path, so we just emit the MOVs from here.
1672 brw_MOV(p
, payload_offset
, offset
);
1673 brw_MOV(p
, payload_value
, value
);
1674 brw_shader_time_add(p
, payload
,
1675 prog_data
->binding_table
.shader_time_start
);
1676 brw_pop_insn_state(p
);
1678 brw_mark_surface_used(prog_data
,
1679 prog_data
->binding_table
.shader_time_start
);
1683 fs_generator::enable_debug(const char *shader_name
)
1686 this->shader_name
= shader_name
;
1690 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1692 /* align to 64 byte boundary. */
1693 while (p
->next_insn_offset
% 64)
1696 this->dispatch_width
= dispatch_width
;
1697 if (dispatch_width
== 16)
1698 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1700 int start_offset
= p
->next_insn_offset
;
1701 int spill_count
= 0, fill_count
= 0;
1704 struct annotation_info annotation
;
1705 memset(&annotation
, 0, sizeof(annotation
));
1707 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1708 struct brw_reg src
[3], dst
;
1709 unsigned int last_insn_offset
= p
->next_insn_offset
;
1710 bool multiple_instructions_emitted
= false;
1712 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1713 * "Register Region Restrictions" section: for BDW, SKL:
1715 * "A POW/FDIV operation must not be followed by an instruction
1716 * that requires two destination registers."
1718 * The documentation is often lacking annotations for Atom parts,
1719 * and empirically this affects CHV as well.
1721 if (devinfo
->gen
>= 8 &&
1723 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1724 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1725 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1727 last_insn_offset
= p
->next_insn_offset
;
1730 if (unlikely(debug_flag
))
1731 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1733 switch (inst
->exec_size
) {
1737 assert(inst
->force_writemask_all
);
1738 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1741 if (inst
->force_sechalf
) {
1742 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1744 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1749 /* If the instruction writes to more than one register, it needs to
1750 * be a "compressed" instruction on Gen <= 5.
1752 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1753 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1755 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1758 unreachable("Invalid instruction width");
1761 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1762 src
[i
] = brw_reg_from_fs_reg(p
, inst
, &inst
->src
[i
], devinfo
->gen
);
1764 /* The accumulator result appears to get used for the
1765 * conditional modifier generation. When negating a UD
1766 * value, there is a 33rd bit generated for the sign in the
1767 * accumulator value, so now you can't check, for example,
1768 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1770 assert(!inst
->conditional_mod
||
1771 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1772 !inst
->src
[i
].negate
);
1774 dst
= brw_reg_from_fs_reg(p
, inst
, &inst
->dst
, devinfo
->gen
);
1776 brw_set_default_predicate_control(p
, inst
->predicate
);
1777 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1778 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1779 brw_set_default_saturate(p
, inst
->saturate
);
1780 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1781 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1782 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1784 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1785 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1787 switch (inst
->opcode
) {
1788 case BRW_OPCODE_MOV
:
1789 brw_MOV(p
, dst
, src
[0]);
1791 case BRW_OPCODE_ADD
:
1792 brw_ADD(p
, dst
, src
[0], src
[1]);
1794 case BRW_OPCODE_MUL
:
1795 brw_MUL(p
, dst
, src
[0], src
[1]);
1797 case BRW_OPCODE_AVG
:
1798 brw_AVG(p
, dst
, src
[0], src
[1]);
1800 case BRW_OPCODE_MACH
:
1801 brw_MACH(p
, dst
, src
[0], src
[1]);
1804 case BRW_OPCODE_LINE
:
1805 brw_LINE(p
, dst
, src
[0], src
[1]);
1808 case BRW_OPCODE_MAD
:
1809 assert(devinfo
->gen
>= 6);
1810 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1811 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1812 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1813 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1814 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1815 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1816 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1817 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1819 if (inst
->conditional_mod
) {
1820 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1821 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1822 multiple_instructions_emitted
= true;
1825 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1827 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1830 case BRW_OPCODE_LRP
:
1831 assert(devinfo
->gen
>= 6);
1832 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1833 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1834 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1835 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1836 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1837 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1838 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1839 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1841 if (inst
->conditional_mod
) {
1842 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1843 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1844 multiple_instructions_emitted
= true;
1847 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1849 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1852 case BRW_OPCODE_FRC
:
1853 brw_FRC(p
, dst
, src
[0]);
1855 case BRW_OPCODE_RNDD
:
1856 brw_RNDD(p
, dst
, src
[0]);
1858 case BRW_OPCODE_RNDE
:
1859 brw_RNDE(p
, dst
, src
[0]);
1861 case BRW_OPCODE_RNDZ
:
1862 brw_RNDZ(p
, dst
, src
[0]);
1865 case BRW_OPCODE_AND
:
1866 brw_AND(p
, dst
, src
[0], src
[1]);
1869 brw_OR(p
, dst
, src
[0], src
[1]);
1871 case BRW_OPCODE_XOR
:
1872 brw_XOR(p
, dst
, src
[0], src
[1]);
1874 case BRW_OPCODE_NOT
:
1875 brw_NOT(p
, dst
, src
[0]);
1877 case BRW_OPCODE_ASR
:
1878 brw_ASR(p
, dst
, src
[0], src
[1]);
1880 case BRW_OPCODE_SHR
:
1881 brw_SHR(p
, dst
, src
[0], src
[1]);
1883 case BRW_OPCODE_SHL
:
1884 brw_SHL(p
, dst
, src
[0], src
[1]);
1886 case BRW_OPCODE_F32TO16
:
1887 assert(devinfo
->gen
>= 7);
1888 brw_F32TO16(p
, dst
, src
[0]);
1890 case BRW_OPCODE_F16TO32
:
1891 assert(devinfo
->gen
>= 7);
1892 brw_F16TO32(p
, dst
, src
[0]);
1894 case BRW_OPCODE_CMP
:
1895 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1896 * that when the destination is a GRF that the dependency-clear bit on
1897 * the flag register is cleared early.
1899 * Suggested workarounds are to disable coissuing CMP instructions
1900 * or to split CMP(16) instructions into two CMP(8) instructions.
1902 * We choose to split into CMP(8) instructions since disabling
1903 * coissuing would affect CMP instructions not otherwise affected by
1906 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1907 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1908 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1909 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1910 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1911 firsthalf(src
[0]), firsthalf(src
[1]));
1912 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1913 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1914 sechalf(src
[0]), sechalf(src
[1]));
1915 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1917 multiple_instructions_emitted
= true;
1918 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1919 /* For unknown reasons, the aforementioned workaround is not
1920 * sufficient. Overriding the type when the destination is the
1921 * null register is necessary but not sufficient by itself.
1923 assert(dst
.nr
== BRW_ARF_NULL
);
1924 dst
.type
= BRW_REGISTER_TYPE_D
;
1925 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1927 unreachable("not reached");
1930 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1933 case BRW_OPCODE_SEL
:
1934 brw_SEL(p
, dst
, src
[0], src
[1]);
1936 case BRW_OPCODE_BFREV
:
1937 assert(devinfo
->gen
>= 7);
1938 /* BFREV only supports UD type for src and dst. */
1939 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1940 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1942 case BRW_OPCODE_FBH
:
1943 assert(devinfo
->gen
>= 7);
1944 /* FBH only supports UD type for dst. */
1945 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1947 case BRW_OPCODE_FBL
:
1948 assert(devinfo
->gen
>= 7);
1949 /* FBL only supports UD type for dst. */
1950 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1952 case BRW_OPCODE_CBIT
:
1953 assert(devinfo
->gen
>= 7);
1954 /* CBIT only supports UD type for dst. */
1955 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1957 case BRW_OPCODE_ADDC
:
1958 assert(devinfo
->gen
>= 7);
1959 brw_ADDC(p
, dst
, src
[0], src
[1]);
1961 case BRW_OPCODE_SUBB
:
1962 assert(devinfo
->gen
>= 7);
1963 brw_SUBB(p
, dst
, src
[0], src
[1]);
1965 case BRW_OPCODE_MAC
:
1966 brw_MAC(p
, dst
, src
[0], src
[1]);
1969 case BRW_OPCODE_BFE
:
1970 assert(devinfo
->gen
>= 7);
1971 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1972 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1973 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1974 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1975 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1976 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1977 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1978 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1980 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1982 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1985 case BRW_OPCODE_BFI1
:
1986 assert(devinfo
->gen
>= 7);
1987 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1990 * "Force BFI instructions to be executed always in SIMD8."
1992 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1993 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1994 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1995 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
1996 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1997 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
1998 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2000 brw_BFI1(p
, dst
, src
[0], src
[1]);
2003 case BRW_OPCODE_BFI2
:
2004 assert(devinfo
->gen
>= 7);
2005 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2006 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
2009 * "Force BFI instructions to be executed always in SIMD8."
2011 * Otherwise we would be able to emit compressed instructions like we
2012 * do for the other three-source instructions.
2014 if (dispatch_width
== 16 &&
2015 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
2016 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2017 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2018 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
2019 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2020 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
2021 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2023 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2025 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2029 if (inst
->src
[0].file
!= BAD_FILE
) {
2030 /* The instruction has an embedded compare (only allowed on gen6) */
2031 assert(devinfo
->gen
== 6);
2032 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2034 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
2038 case BRW_OPCODE_ELSE
:
2041 case BRW_OPCODE_ENDIF
:
2046 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
2049 case BRW_OPCODE_BREAK
:
2051 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2053 case BRW_OPCODE_CONTINUE
:
2055 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2058 case BRW_OPCODE_WHILE
:
2063 case SHADER_OPCODE_RCP
:
2064 case SHADER_OPCODE_RSQ
:
2065 case SHADER_OPCODE_SQRT
:
2066 case SHADER_OPCODE_EXP2
:
2067 case SHADER_OPCODE_LOG2
:
2068 case SHADER_OPCODE_SIN
:
2069 case SHADER_OPCODE_COS
:
2070 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2071 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2072 if (devinfo
->gen
>= 7) {
2073 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
2075 } else if (devinfo
->gen
== 6) {
2076 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
2077 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
2078 generate_math_g45(inst
, dst
, src
[0]);
2080 generate_math_gen4(inst
, dst
, src
[0]);
2083 case SHADER_OPCODE_INT_QUOTIENT
:
2084 case SHADER_OPCODE_INT_REMAINDER
:
2085 case SHADER_OPCODE_POW
:
2086 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2087 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2088 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
2089 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2090 } else if (devinfo
->gen
>= 6) {
2091 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
2093 generate_math_gen4(inst
, dst
, src
[0]);
2096 case FS_OPCODE_CINTERP
:
2097 brw_MOV(p
, dst
, src
[0]);
2099 case FS_OPCODE_LINTERP
:
2100 generate_linterp(inst
, dst
, src
);
2102 case FS_OPCODE_PIXEL_X
:
2103 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2104 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2105 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2107 case FS_OPCODE_PIXEL_Y
:
2108 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2109 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2110 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2112 case FS_OPCODE_GET_BUFFER_SIZE
:
2113 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2115 case SHADER_OPCODE_TEX
:
2117 case SHADER_OPCODE_TXD
:
2118 case SHADER_OPCODE_TXF
:
2119 case SHADER_OPCODE_TXF_LZ
:
2120 case SHADER_OPCODE_TXF_CMS
:
2121 case SHADER_OPCODE_TXF_CMS_W
:
2122 case SHADER_OPCODE_TXF_UMS
:
2123 case SHADER_OPCODE_TXF_MCS
:
2124 case SHADER_OPCODE_TXL
:
2125 case SHADER_OPCODE_TXL_LZ
:
2126 case SHADER_OPCODE_TXS
:
2127 case SHADER_OPCODE_LOD
:
2128 case SHADER_OPCODE_TG4
:
2129 case SHADER_OPCODE_TG4_OFFSET
:
2130 case SHADER_OPCODE_SAMPLEINFO
:
2131 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2133 case FS_OPCODE_DDX_COARSE
:
2134 case FS_OPCODE_DDX_FINE
:
2135 generate_ddx(inst
->opcode
, dst
, src
[0]);
2137 case FS_OPCODE_DDY_COARSE
:
2138 case FS_OPCODE_DDY_FINE
:
2139 generate_ddy(inst
->opcode
, dst
, src
[0]);
2142 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2143 generate_scratch_write(inst
, src
[0]);
2147 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2148 generate_scratch_read(inst
, dst
);
2152 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2153 generate_scratch_read_gen7(inst
, dst
);
2157 case SHADER_OPCODE_MOV_INDIRECT
:
2158 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2161 case SHADER_OPCODE_URB_READ_SIMD8
:
2162 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2163 generate_urb_read(inst
, dst
, src
[0]);
2166 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2167 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2168 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2169 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2170 generate_urb_write(inst
, src
[0]);
2173 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2174 assert(inst
->force_writemask_all
);
2175 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2178 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2179 assert(inst
->force_writemask_all
);
2180 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2183 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
2184 generate_varying_pull_constant_load(inst
, dst
, src
[0]);
2187 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2188 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2191 case FS_OPCODE_REP_FB_WRITE
:
2192 case FS_OPCODE_FB_WRITE
:
2193 generate_fb_write(inst
, src
[0]);
2196 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2197 generate_mov_dispatch_to_flags(inst
);
2200 case FS_OPCODE_DISCARD_JUMP
:
2201 generate_discard_jump(inst
);
2204 case SHADER_OPCODE_SHADER_TIME_ADD
:
2205 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2208 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2209 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2210 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2211 inst
->mlen
, !inst
->dst
.is_null());
2214 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2215 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2216 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2217 inst
->mlen
, src
[2].ud
);
2220 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2221 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2222 brw_untyped_surface_write(p
, src
[0], src
[1],
2223 inst
->mlen
, src
[2].ud
);
2226 case SHADER_OPCODE_TYPED_ATOMIC
:
2227 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2228 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2229 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2232 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2233 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2234 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2235 inst
->mlen
, src
[2].ud
);
2238 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2239 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2240 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2243 case SHADER_OPCODE_MEMORY_FENCE
:
2244 brw_memory_fence(p
, dst
);
2247 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2248 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2251 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2252 brw_find_live_channel(p
, dst
);
2255 case SHADER_OPCODE_BROADCAST
:
2256 brw_broadcast(p
, dst
, src
[0], src
[1]);
2259 case SHADER_OPCODE_EXTRACT_BYTE
: {
2260 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2261 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2263 enum brw_reg_type type
=
2264 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_B
2265 : BRW_REGISTER_TYPE_UB
;
2266 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 4));
2270 case SHADER_OPCODE_EXTRACT_WORD
: {
2271 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2272 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2274 enum brw_reg_type type
=
2275 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_W
2276 : BRW_REGISTER_TYPE_UW
;
2277 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 2));
2281 case FS_OPCODE_SET_SAMPLE_ID
:
2282 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2285 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2286 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2289 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2290 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2291 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2294 case FS_OPCODE_PLACEHOLDER_HALT
:
2295 /* This is the place where the final HALT needs to be inserted if
2296 * we've emitted any discards. If not, this will emit no code.
2298 if (!patch_discard_jumps_to_fb_writes()) {
2299 if (unlikely(debug_flag
)) {
2300 annotation
.ann_count
--;
2305 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2306 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2307 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2310 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2311 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2312 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2315 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2316 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2317 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2320 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2321 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2322 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2325 case CS_OPCODE_CS_TERMINATE
:
2326 generate_cs_terminate(inst
, src
[0]);
2329 case SHADER_OPCODE_BARRIER
:
2330 generate_barrier(inst
, src
[0]);
2333 case FS_OPCODE_PACK_STENCIL_REF
:
2334 generate_stencil_ref_packing(inst
, dst
, src
[0]);
2338 unreachable("Unsupported opcode");
2340 case SHADER_OPCODE_LOAD_PAYLOAD
:
2341 unreachable("Should be lowered by lower_load_payload()");
2344 if (multiple_instructions_emitted
)
2347 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2348 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2349 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2350 "emitting more than 1 instruction");
2352 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2354 if (inst
->conditional_mod
)
2355 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2356 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2357 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2362 annotation_finalize(&annotation
, p
->next_insn_offset
);
2365 bool validated
= brw_validate_instructions(p
, start_offset
, &annotation
);
2367 if (unlikely(debug_flag
))
2368 brw_validate_instructions(p
, start_offset
, &annotation
);
2371 int before_size
= p
->next_insn_offset
- start_offset
;
2372 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2374 int after_size
= p
->next_insn_offset
- start_offset
;
2376 if (unlikely(debug_flag
)) {
2377 fprintf(stderr
, "Native code for %s\n"
2378 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2379 " bytes (%.0f%%)\n",
2380 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2381 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2382 100.0f
* (before_size
- after_size
) / before_size
);
2384 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2386 ralloc_free(annotation
.mem_ctx
);
2390 compiler
->shader_debug_log(log_data
,
2391 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2392 "%d:%d spills:fills, Promoted %u constants, "
2393 "compacted %d to %d bytes.",
2394 _mesa_shader_stage_to_abbrev(stage
),
2395 dispatch_width
, before_size
/ 16,
2396 loop_count
, cfg
->cycle_count
, spill_count
,
2397 fill_count
, promoted_constants
, before_size
,
2400 return start_offset
;
2404 fs_generator::get_assembly(unsigned int *assembly_size
)
2406 return brw_get_program(p
, assembly_size
);