2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 /** @file brw_fs_generator.cpp
26 * This file supports generating code from the FS LIR to the actual
27 * native instructions.
33 #include "brw_program.h"
35 static enum brw_reg_file
36 brw_file_from_reg(fs_reg
*reg
)
40 return BRW_ARCHITECTURE_REGISTER_FILE
;
43 return BRW_GENERAL_REGISTER_FILE
;
45 return BRW_MESSAGE_REGISTER_FILE
;
47 return BRW_IMMEDIATE_VALUE
;
51 unreachable("not reached");
53 return BRW_ARCHITECTURE_REGISTER_FILE
;
57 brw_reg_from_fs_reg(const struct brw_codegen
*p
,
58 fs_inst
*inst
, fs_reg
*reg
, unsigned gen
)
60 struct brw_reg brw_reg
;
64 assert((reg
->nr
& ~BRW_MRF_COMPR4
) < BRW_MAX_MRF(gen
));
67 if (reg
->stride
== 0) {
68 brw_reg
= brw_vec1_reg(brw_file_from_reg(reg
), reg
->nr
, 0);
69 } else if (!p
->compressed
&&
70 inst
->exec_size
* reg
->stride
* type_sz(reg
->type
) <= 32) {
71 brw_reg
= brw_vecn_reg(inst
->exec_size
, brw_file_from_reg(reg
),
73 brw_reg
= stride(brw_reg
, inst
->exec_size
* reg
->stride
,
74 inst
->exec_size
, reg
->stride
);
76 /* From the Haswell PRM:
78 * VertStride must be used to cross GRF register boundaries. This
79 * rule implies that elements within a 'Width' cannot cross GRF
82 * So, for registers that are large enough, we have to split the exec
83 * size in two and trust the compression state to sort it out.
85 assert(inst
->exec_size
/ 2 * reg
->stride
* type_sz(reg
->type
) <= 32);
86 brw_reg
= brw_vecn_reg(inst
->exec_size
/ 2, brw_file_from_reg(reg
),
88 brw_reg
= stride(brw_reg
, inst
->exec_size
/ 2 * reg
->stride
,
89 inst
->exec_size
/ 2, reg
->stride
);
92 brw_reg
= retype(brw_reg
, reg
->type
);
93 brw_reg
= byte_offset(brw_reg
, reg
->subreg_offset
);
94 brw_reg
.abs
= reg
->abs
;
95 brw_reg
.negate
= reg
->negate
;
100 brw_reg
= reg
->as_brw_reg();
103 /* Probably unused. */
104 brw_reg
= brw_null_reg();
108 unreachable("not reached");
114 fs_generator::fs_generator(const struct brw_compiler
*compiler
, void *log_data
,
117 struct brw_stage_prog_data
*prog_data
,
118 unsigned promoted_constants
,
119 bool runtime_check_aads_emit
,
120 gl_shader_stage stage
)
122 : compiler(compiler
), log_data(log_data
),
123 devinfo(compiler
->devinfo
), key(key
),
124 prog_data(prog_data
),
125 promoted_constants(promoted_constants
),
126 runtime_check_aads_emit(runtime_check_aads_emit
), debug_flag(false),
127 stage(stage
), mem_ctx(mem_ctx
)
129 p
= rzalloc(mem_ctx
, struct brw_codegen
);
130 brw_init_codegen(devinfo
, p
, mem_ctx
);
133 fs_generator::~fs_generator()
137 class ip_record
: public exec_node
{
139 DECLARE_RALLOC_CXX_OPERATORS(ip_record
)
150 fs_generator::patch_discard_jumps_to_fb_writes()
152 if (devinfo
->gen
< 6 || this->discard_halt_patches
.is_empty())
155 int scale
= brw_jump_scale(p
->devinfo
);
157 /* There is a somewhat strange undocumented requirement of using
158 * HALT, according to the simulator. If some channel has HALTed to
159 * a particular UIP, then by the end of the program, every channel
160 * must have HALTed to that UIP. Furthermore, the tracking is a
161 * stack, so you can't do the final halt of a UIP after starting
162 * halting to a new UIP.
164 * Symptoms of not emitting this instruction on actual hardware
165 * included GPU hangs and sparkly rendering on the piglit discard
168 brw_inst
*last_halt
= gen6_HALT(p
);
169 brw_inst_set_uip(p
->devinfo
, last_halt
, 1 * scale
);
170 brw_inst_set_jip(p
->devinfo
, last_halt
, 1 * scale
);
174 foreach_in_list(ip_record
, patch_ip
, &discard_halt_patches
) {
175 brw_inst
*patch
= &p
->store
[patch_ip
->ip
];
177 assert(brw_inst_opcode(p
->devinfo
, patch
) == BRW_OPCODE_HALT
);
178 /* HALT takes a half-instruction distance from the pre-incremented IP. */
179 brw_inst_set_uip(p
->devinfo
, patch
, (ip
- patch_ip
->ip
) * scale
);
182 this->discard_halt_patches
.make_empty();
187 fs_generator::fire_fb_write(fs_inst
*inst
,
188 struct brw_reg payload
,
189 struct brw_reg implied_header
,
192 uint32_t msg_control
;
194 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
196 if (devinfo
->gen
< 6) {
197 brw_push_insn_state(p
);
198 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
199 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
200 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
201 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
202 brw_MOV(p
, offset(payload
, 1), brw_vec8_grf(1, 0));
203 brw_pop_insn_state(p
);
206 if (inst
->opcode
== FS_OPCODE_REP_FB_WRITE
)
207 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED
;
208 else if (prog_data
->dual_src_blend
) {
209 if (!inst
->force_sechalf
)
210 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01
;
212 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23
;
213 } else if (inst
->exec_size
== 16)
214 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE
;
216 msg_control
= BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01
;
218 uint32_t surf_index
=
219 prog_data
->binding_table
.render_target_start
+ inst
->target
;
221 bool last_render_target
= inst
->eot
||
222 (prog_data
->dual_src_blend
&& dispatch_width
== 16);
235 inst
->header_size
!= 0);
237 brw_mark_surface_used(&prog_data
->base
, surf_index
);
241 fs_generator::generate_fb_write(fs_inst
*inst
, struct brw_reg payload
)
243 brw_wm_prog_data
*prog_data
= (brw_wm_prog_data
*) this->prog_data
;
244 const brw_wm_prog_key
* const key
= (brw_wm_prog_key
* const) this->key
;
245 struct brw_reg implied_header
;
247 if (devinfo
->gen
< 8 && !devinfo
->is_haswell
) {
248 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
251 if (inst
->base_mrf
>= 0)
252 payload
= brw_message_reg(inst
->base_mrf
);
254 /* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
257 if (inst
->header_size
!= 0) {
258 brw_push_insn_state(p
);
259 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
260 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
261 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
262 brw_set_default_flag_reg(p
, 0, 0);
264 /* On HSW, the GPU will use the predicate on SENDC, unless the header is
267 if (prog_data
->uses_kill
) {
268 struct brw_reg pixel_mask
;
270 if (devinfo
->gen
>= 6)
271 pixel_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
273 pixel_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
275 brw_MOV(p
, pixel_mask
, brw_flag_reg(0, 1));
278 if (devinfo
->gen
>= 6) {
279 brw_push_insn_state(p
);
280 brw_set_default_exec_size(p
, BRW_EXECUTE_16
);
281 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
283 retype(payload
, BRW_REGISTER_TYPE_UD
),
284 retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
285 brw_pop_insn_state(p
);
287 if (inst
->target
> 0 && key
->replicate_alpha
) {
288 /* Set "Source0 Alpha Present to RenderTarget" bit in message
292 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
293 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
294 brw_imm_ud(0x1 << 11));
297 if (inst
->target
> 0) {
298 /* Set the render target index for choosing BLEND_STATE. */
299 brw_MOV(p
, retype(vec1(suboffset(payload
, 2)),
300 BRW_REGISTER_TYPE_UD
),
301 brw_imm_ud(inst
->target
));
304 /* Set computes stencil to render target */
305 if (prog_data
->computed_stencil
) {
307 vec1(retype(payload
, BRW_REGISTER_TYPE_UD
)),
308 vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
)),
309 brw_imm_ud(0x1 << 14));
312 implied_header
= brw_null_reg();
314 implied_header
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
317 brw_pop_insn_state(p
);
319 implied_header
= brw_null_reg();
322 if (!runtime_check_aads_emit
) {
323 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
325 /* This can only happen in gen < 6 */
326 assert(devinfo
->gen
< 6);
328 struct brw_reg v1_null_ud
= vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD
));
330 /* Check runtime bit to detect if we have to send AA data or not */
331 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
334 retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD
),
336 brw_inst_set_cond_modifier(p
->devinfo
, brw_last_inst
, BRW_CONDITIONAL_NZ
);
338 int jmp
= brw_JMPI(p
, brw_imm_ud(0), BRW_PREDICATE_NORMAL
) - p
->store
;
339 brw_inst_set_exec_size(p
->devinfo
, brw_last_inst
, BRW_EXECUTE_1
);
341 /* Don't send AA data */
342 fire_fb_write(inst
, offset(payload
, 1), implied_header
, inst
->mlen
-1);
344 brw_land_fwd_jump(p
, jmp
);
345 fire_fb_write(inst
, payload
, implied_header
, inst
->mlen
);
350 fs_generator::generate_mov_indirect(fs_inst
*inst
,
353 struct brw_reg indirect_byte_offset
)
355 assert(indirect_byte_offset
.type
== BRW_REGISTER_TYPE_UD
);
356 assert(indirect_byte_offset
.file
== BRW_GENERAL_REGISTER_FILE
);
358 unsigned imm_byte_offset
= reg
.nr
* REG_SIZE
+ reg
.subnr
;
360 if (indirect_byte_offset
.file
== BRW_IMMEDIATE_VALUE
) {
361 imm_byte_offset
+= indirect_byte_offset
.ud
;
363 reg
.nr
= imm_byte_offset
/ REG_SIZE
;
364 reg
.subnr
= imm_byte_offset
% REG_SIZE
;
365 brw_MOV(p
, dst
, reg
);
367 /* Prior to Broadwell, there are only 8 address registers. */
368 assert(inst
->exec_size
== 8 || devinfo
->gen
>= 8);
370 /* We use VxH indirect addressing, clobbering a0.0 through a0.7. */
371 struct brw_reg addr
= vec8(brw_address_reg(0));
373 /* The destination stride of an instruction (in bytes) must be greater
374 * than or equal to the size of the rest of the instruction. Since the
375 * address register is of type UW, we can't use a D-type instruction.
376 * In order to get around this, re retype to UW and use a stride.
378 indirect_byte_offset
=
379 retype(spread(indirect_byte_offset
, 2), BRW_REGISTER_TYPE_UW
);
381 struct brw_reg ind_src
;
382 if (devinfo
->gen
< 8) {
383 /* From the Haswell PRM section "Register Region Restrictions":
385 * "The lower bits of the AddressImmediate must not overflow to
386 * change the register address. The lower 5 bits of Address
387 * Immediate when added to lower 5 bits of address register gives
388 * the sub-register offset. The upper bits of Address Immediate
389 * when added to upper bits of address register gives the register
390 * address. Any overflow from sub-register offset is dropped."
392 * This restriction is only listed in the Haswell PRM but emperical
393 * testing indicates that it applies on all older generations and is
394 * lifted on Broadwell.
396 * Since the indirect may cause us to cross a register boundary, this
397 * makes the base offset almost useless. We could try and do
398 * something clever where we use a actual base offset if
399 * base_offset % 32 == 0 but that would mean we were generating
400 * different code depending on the base offset. Instead, for the
401 * sake of consistency, we'll just do the add ourselves.
403 brw_ADD(p
, addr
, indirect_byte_offset
, brw_imm_uw(imm_byte_offset
));
404 ind_src
= brw_VxH_indirect(0, 0);
406 brw_MOV(p
, addr
, indirect_byte_offset
);
407 ind_src
= brw_VxH_indirect(0, imm_byte_offset
);
410 brw_inst
*mov
= brw_MOV(p
, dst
, retype(ind_src
, dst
.type
));
412 if (devinfo
->gen
== 6 && dst
.file
== BRW_MESSAGE_REGISTER_FILE
&&
413 !inst
->get_next()->is_tail_sentinel() &&
414 ((fs_inst
*)inst
->get_next())->mlen
> 0) {
415 /* From the Sandybridge PRM:
417 * "[Errata: DevSNB(SNB)] If MRF register is updated by any
418 * instruction that “indexed/indirect” source AND is followed by a
419 * send, the instruction requires a “Switch”. This is to avoid
420 * race condition where send may dispatch before MRF is updated."
422 brw_inst_set_thread_control(devinfo
, mov
, BRW_THREAD_SWITCH
);
428 fs_generator::generate_urb_read(fs_inst
*inst
,
430 struct brw_reg header
)
432 assert(header
.file
== BRW_GENERAL_REGISTER_FILE
);
433 assert(header
.type
== BRW_REGISTER_TYPE_UD
);
435 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
436 brw_set_dest(p
, send
, dst
);
437 brw_set_src0(p
, send
, header
);
438 brw_set_src1(p
, send
, brw_imm_ud(0u));
440 brw_inst_set_sfid(p
->devinfo
, send
, BRW_SFID_URB
);
441 brw_inst_set_urb_opcode(p
->devinfo
, send
, GEN8_URB_OPCODE_SIMD8_READ
);
443 if (inst
->opcode
== SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
)
444 brw_inst_set_urb_per_slot_offset(p
->devinfo
, send
, true);
446 brw_inst_set_mlen(p
->devinfo
, send
, inst
->mlen
);
447 brw_inst_set_rlen(p
->devinfo
, send
, inst
->regs_written
);
448 brw_inst_set_header_present(p
->devinfo
, send
, true);
449 brw_inst_set_urb_global_offset(p
->devinfo
, send
, inst
->offset
);
453 fs_generator::generate_urb_write(fs_inst
*inst
, struct brw_reg payload
)
457 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
459 brw_set_dest(p
, insn
, brw_null_reg());
460 brw_set_src0(p
, insn
, payload
);
461 brw_set_src1(p
, insn
, brw_imm_d(0));
463 brw_inst_set_sfid(p
->devinfo
, insn
, BRW_SFID_URB
);
464 brw_inst_set_urb_opcode(p
->devinfo
, insn
, GEN8_URB_OPCODE_SIMD8_WRITE
);
466 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
||
467 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
468 brw_inst_set_urb_per_slot_offset(p
->devinfo
, insn
, true);
470 if (inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
||
471 inst
->opcode
== SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
)
472 brw_inst_set_urb_channel_mask_present(p
->devinfo
, insn
, true);
474 brw_inst_set_mlen(p
->devinfo
, insn
, inst
->mlen
);
475 brw_inst_set_rlen(p
->devinfo
, insn
, 0);
476 brw_inst_set_eot(p
->devinfo
, insn
, inst
->eot
);
477 brw_inst_set_header_present(p
->devinfo
, insn
, true);
478 brw_inst_set_urb_global_offset(p
->devinfo
, insn
, inst
->offset
);
482 fs_generator::generate_cs_terminate(fs_inst
*inst
, struct brw_reg payload
)
484 struct brw_inst
*insn
;
486 insn
= brw_next_insn(p
, BRW_OPCODE_SEND
);
488 brw_set_dest(p
, insn
, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW
));
489 brw_set_src0(p
, insn
, payload
);
490 brw_set_src1(p
, insn
, brw_imm_d(0));
492 /* Terminate a compute shader by sending a message to the thread spawner.
494 brw_inst_set_sfid(devinfo
, insn
, BRW_SFID_THREAD_SPAWNER
);
495 brw_inst_set_mlen(devinfo
, insn
, 1);
496 brw_inst_set_rlen(devinfo
, insn
, 0);
497 brw_inst_set_eot(devinfo
, insn
, inst
->eot
);
498 brw_inst_set_header_present(devinfo
, insn
, false);
500 brw_inst_set_ts_opcode(devinfo
, insn
, 0); /* Dereference resource */
501 brw_inst_set_ts_request_type(devinfo
, insn
, 0); /* Root thread */
503 /* Note that even though the thread has a URB resource associated with it,
504 * we set the "do not dereference URB" bit, because the URB resource is
505 * managed by the fixed-function unit, so it will free it automatically.
507 brw_inst_set_ts_resource_select(devinfo
, insn
, 1); /* Do not dereference URB */
509 brw_inst_set_mask_control(devinfo
, insn
, BRW_MASK_DISABLE
);
513 fs_generator::generate_stencil_ref_packing(fs_inst
*inst
,
517 assert(dispatch_width
== 8);
518 assert(devinfo
->gen
>= 9);
520 /* Stencil value updates are provided in 8 slots of 1 byte per slot.
521 * Presumably, in order to save memory bandwidth, the stencil reference
522 * values written from the FS need to be packed into 2 dwords (this makes
523 * sense because the stencil values are limited to 1 byte each and a SIMD8
524 * send, so stencil slots 0-3 in dw0, and 4-7 in dw1.)
526 * The spec is confusing here because in the payload definition of MDP_RTW_S8
527 * (Message Data Payload for Render Target Writes with Stencil 8b) the
528 * stencil value seems to be dw4.0-dw4.7. However, if you look at the type of
529 * dw4 it is type MDPR_STENCIL (Message Data Payload Register) which is the
530 * packed values specified above and diagrammed below:
533 * --------------------------------
537 * --------------------------------
538 * DW1 | STC | STC | STC | STC |
539 * | slot7 | slot6 | slot5 | slot4|
540 * --------------------------------
541 * DW0 | STC | STC | STC | STC |
542 * | slot3 | slot2 | slot1 | slot0|
543 * --------------------------------
546 src
.vstride
= BRW_VERTICAL_STRIDE_4
;
547 src
.width
= BRW_WIDTH_1
;
548 src
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
549 assert(src
.type
== BRW_REGISTER_TYPE_UB
);
550 brw_MOV(p
, retype(dst
, BRW_REGISTER_TYPE_UB
), src
);
554 fs_generator::generate_barrier(fs_inst
*inst
, struct brw_reg src
)
561 fs_generator::generate_linterp(fs_inst
*inst
,
562 struct brw_reg dst
, struct brw_reg
*src
)
566 * -----------------------------------
567 * | src1+0 | src1+1 | src1+2 | src1+3 |
568 * |-----------------------------------|
569 * |(x0, x1)|(y0, y1)|(x2, x3)|(y2, y3)|
570 * -----------------------------------
572 * but for the LINE/MAC pair, the LINE reads Xs and the MAC reads Ys:
574 * -----------------------------------
575 * | src1+0 | src1+1 | src1+2 | src1+3 |
576 * |-----------------------------------|
577 * |(x0, x1)|(y0, y1)| | | in SIMD8
578 * |-----------------------------------|
579 * |(x0, x1)|(x2, x3)|(y0, y1)|(y2, y3)| in SIMD16
580 * -----------------------------------
582 * See also: emit_interpolation_setup_gen4().
584 struct brw_reg delta_x
= src
[0];
585 struct brw_reg delta_y
= offset(src
[0], dispatch_width
/ 8);
586 struct brw_reg interp
= src
[1];
588 if (devinfo
->has_pln
&&
589 (devinfo
->gen
>= 7 || (delta_x
.nr
& 1) == 0)) {
590 brw_PLN(p
, dst
, interp
, delta_x
);
592 brw_LINE(p
, brw_null_reg(), interp
, delta_x
);
593 brw_MAC(p
, dst
, suboffset(interp
, 1), delta_y
);
598 fs_generator::generate_math_gen6(fs_inst
*inst
,
603 int op
= brw_math_function(inst
->opcode
);
604 bool binop
= src1
.file
!= BRW_ARCHITECTURE_REGISTER_FILE
;
606 if (dispatch_width
== 8) {
607 gen6_math(p
, dst
, op
, src0
, src1
);
608 } else if (dispatch_width
== 16) {
609 brw_push_insn_state(p
);
610 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
611 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
612 gen6_math(p
, firsthalf(dst
), op
, firsthalf(src0
), firsthalf(src1
));
613 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
614 gen6_math(p
, sechalf(dst
), op
, sechalf(src0
),
615 binop
? sechalf(src1
) : brw_null_reg());
616 brw_pop_insn_state(p
);
621 fs_generator::generate_math_gen4(fs_inst
*inst
,
625 int op
= brw_math_function(inst
->opcode
);
627 assert(inst
->mlen
>= 1);
629 if (dispatch_width
== 8) {
633 BRW_MATH_PRECISION_FULL
);
634 } else if (dispatch_width
== 16) {
635 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
636 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
637 gen4_math(p
, firsthalf(dst
),
639 inst
->base_mrf
, firsthalf(src
),
640 BRW_MATH_PRECISION_FULL
);
641 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
642 gen4_math(p
, sechalf(dst
),
644 inst
->base_mrf
+ 1, sechalf(src
),
645 BRW_MATH_PRECISION_FULL
);
647 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
652 fs_generator::generate_math_g45(fs_inst
*inst
,
656 if (inst
->opcode
== SHADER_OPCODE_POW
||
657 inst
->opcode
== SHADER_OPCODE_INT_QUOTIENT
||
658 inst
->opcode
== SHADER_OPCODE_INT_REMAINDER
) {
659 generate_math_gen4(inst
, dst
, src
);
663 int op
= brw_math_function(inst
->opcode
);
665 assert(inst
->mlen
>= 1);
670 BRW_MATH_PRECISION_FULL
);
674 fs_generator::generate_get_buffer_size(fs_inst
*inst
,
677 struct brw_reg surf_index
)
679 assert(devinfo
->gen
>= 7);
680 assert(surf_index
.file
== BRW_IMMEDIATE_VALUE
);
685 switch (inst
->exec_size
) {
687 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
690 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
693 unreachable("Invalid width for texture instruction");
696 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
702 retype(dst
, BRW_REGISTER_TYPE_UW
),
707 GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
,
708 rlen
, /* response length */
710 inst
->header_size
> 0,
712 BRW_SAMPLER_RETURN_FORMAT_SINT32
);
714 brw_mark_surface_used(prog_data
, surf_index
.ud
);
718 fs_generator::generate_tex(fs_inst
*inst
, struct brw_reg dst
, struct brw_reg src
,
719 struct brw_reg surface_index
,
720 struct brw_reg sampler_index
)
724 uint32_t return_format
;
725 bool is_combined_send
= inst
->eot
;
728 case BRW_REGISTER_TYPE_D
:
729 return_format
= BRW_SAMPLER_RETURN_FORMAT_SINT32
;
731 case BRW_REGISTER_TYPE_UD
:
732 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
735 return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
739 /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
740 * is set as part of the message descriptor. On gen4, the PRM seems to
741 * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
742 * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
743 * gone from the message descriptor entirely and you just get UINT32 all
744 * the time regasrdless. Since we can really only do non-UINT32 on gen4,
745 * just stomp it to UINT32 all the time.
747 if (inst
->opcode
== SHADER_OPCODE_TXS
)
748 return_format
= BRW_SAMPLER_RETURN_FORMAT_UINT32
;
750 switch (inst
->exec_size
) {
752 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
755 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
758 unreachable("Invalid width for texture instruction");
761 if (devinfo
->gen
>= 5) {
762 switch (inst
->opcode
) {
763 case SHADER_OPCODE_TEX
:
764 if (inst
->shadow_compare
) {
765 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE
;
767 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE
;
771 if (inst
->shadow_compare
) {
772 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE
;
774 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS
;
777 case SHADER_OPCODE_TXL
:
778 if (inst
->shadow_compare
) {
779 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE
;
781 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LOD
;
784 case SHADER_OPCODE_TXS
:
785 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO
;
787 case SHADER_OPCODE_TXD
:
788 if (inst
->shadow_compare
) {
789 /* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
790 assert(devinfo
->gen
>= 8 || devinfo
->is_haswell
);
791 msg_type
= HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE
;
793 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS
;
796 case SHADER_OPCODE_TXF
:
797 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
799 case SHADER_OPCODE_TXF_CMS_W
:
800 assert(devinfo
->gen
>= 9);
801 msg_type
= GEN9_SAMPLER_MESSAGE_SAMPLE_LD2DMS_W
;
803 case SHADER_OPCODE_TXF_CMS
:
804 if (devinfo
->gen
>= 7)
805 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS
;
807 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
809 case SHADER_OPCODE_TXF_UMS
:
810 assert(devinfo
->gen
>= 7);
811 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS
;
813 case SHADER_OPCODE_TXF_MCS
:
814 assert(devinfo
->gen
>= 7);
815 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS
;
817 case SHADER_OPCODE_LOD
:
818 msg_type
= GEN5_SAMPLER_MESSAGE_LOD
;
820 case SHADER_OPCODE_TG4
:
821 if (inst
->shadow_compare
) {
822 assert(devinfo
->gen
>= 7);
823 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C
;
825 assert(devinfo
->gen
>= 6);
826 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4
;
829 case SHADER_OPCODE_TG4_OFFSET
:
830 assert(devinfo
->gen
>= 7);
831 if (inst
->shadow_compare
) {
832 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C
;
834 msg_type
= GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO
;
837 case SHADER_OPCODE_SAMPLEINFO
:
838 msg_type
= GEN6_SAMPLER_MESSAGE_SAMPLE_SAMPLEINFO
;
841 unreachable("not reached");
844 switch (inst
->opcode
) {
845 case SHADER_OPCODE_TEX
:
846 /* Note that G45 and older determines shadow compare and dispatch width
847 * from message length for most messages.
849 if (inst
->exec_size
== 8) {
850 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE
;
851 if (inst
->shadow_compare
) {
852 assert(inst
->mlen
== 6);
854 assert(inst
->mlen
<= 4);
857 if (inst
->shadow_compare
) {
858 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE
;
859 assert(inst
->mlen
== 9);
861 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE
;
862 assert(inst
->mlen
<= 7 && inst
->mlen
% 2 == 1);
867 if (inst
->shadow_compare
) {
868 assert(inst
->exec_size
== 8);
869 assert(inst
->mlen
== 6);
870 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE
;
872 assert(inst
->mlen
== 9);
873 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS
;
874 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
877 case SHADER_OPCODE_TXL
:
878 if (inst
->shadow_compare
) {
879 assert(inst
->exec_size
== 8);
880 assert(inst
->mlen
== 6);
881 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE
;
883 assert(inst
->mlen
== 9);
884 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD
;
885 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
888 case SHADER_OPCODE_TXD
:
889 /* There is no sample_d_c message; comparisons are done manually */
890 assert(inst
->exec_size
== 8);
891 assert(inst
->mlen
== 7 || inst
->mlen
== 10);
892 msg_type
= BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS
;
894 case SHADER_OPCODE_TXF
:
895 assert(inst
->mlen
<= 9 && inst
->mlen
% 2 == 1);
896 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
897 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
899 case SHADER_OPCODE_TXS
:
900 assert(inst
->mlen
== 3);
901 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_RESINFO
;
902 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
905 unreachable("not reached");
908 assert(msg_type
!= -1);
910 if (simd_mode
== BRW_SAMPLER_SIMD_MODE_SIMD16
) {
914 assert(devinfo
->gen
< 7 || inst
->header_size
== 0 ||
915 src
.file
== BRW_GENERAL_REGISTER_FILE
);
917 assert(sampler_index
.type
== BRW_REGISTER_TYPE_UD
);
919 /* Load the message header if present. If there's a texture offset,
920 * we need to set it up explicitly and load the offset bitfield.
921 * Otherwise, we can use an implied move from g0 to the first message reg.
923 if (inst
->header_size
!= 0) {
924 if (devinfo
->gen
< 6 && !inst
->offset
) {
925 /* Set up an implied move from g0 to the MRF. */
926 src
= retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW
);
928 struct brw_reg header_reg
;
930 if (devinfo
->gen
>= 7) {
933 assert(inst
->base_mrf
!= -1);
934 header_reg
= brw_message_reg(inst
->base_mrf
);
937 brw_push_insn_state(p
);
938 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
939 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
940 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
941 /* Explicitly set up the message header by copying g0 to the MRF. */
942 brw_MOV(p
, header_reg
, brw_vec8_grf(0, 0));
945 /* Set the offset bits in DWord 2. */
946 brw_MOV(p
, get_element_ud(header_reg
, 2),
947 brw_imm_ud(inst
->offset
));
948 } else if (stage
!= MESA_SHADER_VERTEX
&&
949 stage
!= MESA_SHADER_FRAGMENT
) {
950 /* The vertex and fragment stages have g0.2 set to 0, so
951 * header0.2 is 0 when g0 is copied. Other stages may not, so we
952 * must set it to 0 to avoid setting undesirable bits in the
955 brw_MOV(p
, get_element_ud(header_reg
, 2), brw_imm_ud(0));
958 brw_adjust_sampler_state_pointer(p
, header_reg
, sampler_index
);
959 brw_pop_insn_state(p
);
963 uint32_t base_binding_table_index
= (inst
->opcode
== SHADER_OPCODE_TG4
||
964 inst
->opcode
== SHADER_OPCODE_TG4_OFFSET
)
965 ? prog_data
->binding_table
.gather_texture_start
966 : prog_data
->binding_table
.texture_start
;
968 if (surface_index
.file
== BRW_IMMEDIATE_VALUE
&&
969 sampler_index
.file
== BRW_IMMEDIATE_VALUE
) {
970 uint32_t surface
= surface_index
.ud
;
971 uint32_t sampler
= sampler_index
.ud
;
974 retype(dst
, BRW_REGISTER_TYPE_UW
),
977 surface
+ base_binding_table_index
,
982 inst
->header_size
!= 0,
986 brw_mark_surface_used(prog_data
, surface
+ base_binding_table_index
);
988 /* Non-const sampler index */
990 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
991 struct brw_reg surface_reg
= vec1(retype(surface_index
, BRW_REGISTER_TYPE_UD
));
992 struct brw_reg sampler_reg
= vec1(retype(sampler_index
, BRW_REGISTER_TYPE_UD
));
994 brw_push_insn_state(p
);
995 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
996 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
998 if (brw_regs_equal(&surface_reg
, &sampler_reg
)) {
999 brw_MUL(p
, addr
, sampler_reg
, brw_imm_uw(0x101));
1001 brw_SHL(p
, addr
, sampler_reg
, brw_imm_ud(8));
1002 brw_OR(p
, addr
, addr
, surface_reg
);
1004 if (base_binding_table_index
)
1005 brw_ADD(p
, addr
, addr
, brw_imm_ud(base_binding_table_index
));
1006 brw_AND(p
, addr
, addr
, brw_imm_ud(0xfff));
1008 brw_pop_insn_state(p
);
1010 /* dst = send(offset, a0.0 | <descriptor>) */
1011 brw_inst
*insn
= brw_send_indirect_message(
1012 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1013 brw_set_sampler_message(p
, insn
,
1018 inst
->mlen
/* mlen */,
1019 inst
->header_size
!= 0 /* header */,
1023 /* visitor knows more than we do about the surface limit required,
1024 * so has already done marking.
1028 if (is_combined_send
) {
1029 brw_inst_set_eot(p
->devinfo
, brw_last_inst
, true);
1030 brw_inst_set_opcode(p
->devinfo
, brw_last_inst
, BRW_OPCODE_SENDC
);
1035 /* For OPCODE_DDX and OPCODE_DDY, per channel of output we've got input
1038 * arg0: ss0.tl ss0.tr ss0.bl ss0.br ss1.tl ss1.tr ss1.bl ss1.br
1040 * Ideally, we want to produce:
1043 * dst: (ss0.tr - ss0.tl) (ss0.tl - ss0.bl)
1044 * (ss0.tr - ss0.tl) (ss0.tr - ss0.br)
1045 * (ss0.br - ss0.bl) (ss0.tl - ss0.bl)
1046 * (ss0.br - ss0.bl) (ss0.tr - ss0.br)
1047 * (ss1.tr - ss1.tl) (ss1.tl - ss1.bl)
1048 * (ss1.tr - ss1.tl) (ss1.tr - ss1.br)
1049 * (ss1.br - ss1.bl) (ss1.tl - ss1.bl)
1050 * (ss1.br - ss1.bl) (ss1.tr - ss1.br)
1052 * and add another set of two more subspans if in 16-pixel dispatch mode.
1054 * For DDX, it ends up being easy: width = 2, horiz=0 gets us the same result
1055 * for each pair, and vertstride = 2 jumps us 2 elements after processing a
1056 * pair. But the ideal approximation may impose a huge performance cost on
1057 * sample_d. On at least Haswell, sample_d instruction does some
1058 * optimizations if the same LOD is used for all pixels in the subspan.
1060 * For DDY, we need to use ALIGN16 mode since it's capable of doing the
1061 * appropriate swizzling.
1064 fs_generator::generate_ddx(enum opcode opcode
,
1065 struct brw_reg dst
, struct brw_reg src
)
1067 unsigned vstride
, width
;
1069 if (opcode
== FS_OPCODE_DDX_FINE
) {
1070 /* produce accurate derivatives */
1071 vstride
= BRW_VERTICAL_STRIDE_2
;
1072 width
= BRW_WIDTH_2
;
1074 /* replicate the derivative at the top-left pixel to other pixels */
1075 vstride
= BRW_VERTICAL_STRIDE_4
;
1076 width
= BRW_WIDTH_4
;
1079 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 1,
1080 src
.negate
, src
.abs
,
1081 BRW_REGISTER_TYPE_F
,
1084 BRW_HORIZONTAL_STRIDE_0
,
1085 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1086 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1087 src
.negate
, src
.abs
,
1088 BRW_REGISTER_TYPE_F
,
1091 BRW_HORIZONTAL_STRIDE_0
,
1092 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1093 brw_ADD(p
, dst
, src0
, negate(src1
));
1096 /* The negate_value boolean is used to negate the derivative computation for
1097 * FBOs, since they place the origin at the upper left instead of the lower
1101 fs_generator::generate_ddy(enum opcode opcode
,
1102 struct brw_reg dst
, struct brw_reg src
,
1105 if (opcode
== FS_OPCODE_DDY_FINE
) {
1106 /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
1107 * Region Restrictions):
1109 * In Align16 access mode, SIMD16 is not allowed for DW operations
1110 * and SIMD8 is not allowed for DF operations.
1112 * In this context, "DW operations" means "operations acting on 32-bit
1113 * values", so it includes operations on floats.
1115 * Gen4 has a similar restriction. From the i965 PRM, section 11.5.3
1116 * (Instruction Compression -> Rules and Restrictions):
1118 * A compressed instruction must be in Align1 access mode. Align16
1119 * mode instructions cannot be compressed.
1121 * Similar text exists in the g45 PRM.
1123 * Empirically, compressed align16 instructions using odd register
1124 * numbers don't appear to work on Sandybridge either.
1126 * On these platforms, if we're building a SIMD16 shader, we need to
1127 * manually unroll to a pair of SIMD8 instructions.
1129 bool unroll_to_simd8
=
1130 (dispatch_width
== 16 &&
1131 (devinfo
->gen
== 4 || devinfo
->gen
== 6 ||
1132 (devinfo
->gen
== 7 && !devinfo
->is_haswell
)));
1134 /* produce accurate derivatives */
1135 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1136 src
.negate
, src
.abs
,
1137 BRW_REGISTER_TYPE_F
,
1138 BRW_VERTICAL_STRIDE_4
,
1140 BRW_HORIZONTAL_STRIDE_1
,
1141 BRW_SWIZZLE_XYXY
, WRITEMASK_XYZW
);
1142 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 0,
1143 src
.negate
, src
.abs
,
1144 BRW_REGISTER_TYPE_F
,
1145 BRW_VERTICAL_STRIDE_4
,
1147 BRW_HORIZONTAL_STRIDE_1
,
1148 BRW_SWIZZLE_ZWZW
, WRITEMASK_XYZW
);
1149 brw_push_insn_state(p
);
1150 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1151 if (unroll_to_simd8
) {
1152 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1153 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1155 brw_ADD(p
, firsthalf(dst
), firsthalf(src1
), negate(firsthalf(src0
)));
1156 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1157 brw_ADD(p
, sechalf(dst
), sechalf(src1
), negate(sechalf(src0
)));
1159 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), negate(firsthalf(src1
)));
1160 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1161 brw_ADD(p
, sechalf(dst
), sechalf(src0
), negate(sechalf(src1
)));
1165 brw_ADD(p
, dst
, src1
, negate(src0
));
1167 brw_ADD(p
, dst
, src0
, negate(src1
));
1169 brw_pop_insn_state(p
);
1171 /* replicate the derivative at the top-left pixel to other pixels */
1172 struct brw_reg src0
= brw_reg(src
.file
, src
.nr
, 0,
1173 src
.negate
, src
.abs
,
1174 BRW_REGISTER_TYPE_F
,
1175 BRW_VERTICAL_STRIDE_4
,
1177 BRW_HORIZONTAL_STRIDE_0
,
1178 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1179 struct brw_reg src1
= brw_reg(src
.file
, src
.nr
, 2,
1180 src
.negate
, src
.abs
,
1181 BRW_REGISTER_TYPE_F
,
1182 BRW_VERTICAL_STRIDE_4
,
1184 BRW_HORIZONTAL_STRIDE_0
,
1185 BRW_SWIZZLE_XYZW
, WRITEMASK_XYZW
);
1187 brw_ADD(p
, dst
, src1
, negate(src0
));
1189 brw_ADD(p
, dst
, src0
, negate(src1
));
1194 fs_generator::generate_discard_jump(fs_inst
*inst
)
1196 assert(devinfo
->gen
>= 6);
1198 /* This HALT will be patched up at FB write time to point UIP at the end of
1199 * the program, and at brw_uip_jip() JIP will be set to the end of the
1200 * current block (or the program).
1202 this->discard_halt_patches
.push_tail(new(mem_ctx
) ip_record(p
->nr_insn
));
1204 brw_push_insn_state(p
);
1205 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1207 brw_pop_insn_state(p
);
1211 fs_generator::generate_scratch_write(fs_inst
*inst
, struct brw_reg src
)
1213 assert(inst
->mlen
!= 0);
1216 brw_uvec_mrf(inst
->exec_size
, (inst
->base_mrf
+ 1), 0),
1217 retype(src
, BRW_REGISTER_TYPE_UD
));
1218 brw_oword_block_write_scratch(p
, brw_message_reg(inst
->base_mrf
),
1219 inst
->exec_size
/ 8, inst
->offset
);
1223 fs_generator::generate_scratch_read(fs_inst
*inst
, struct brw_reg dst
)
1225 assert(inst
->mlen
!= 0);
1227 brw_oword_block_read_scratch(p
, dst
, brw_message_reg(inst
->base_mrf
),
1228 inst
->exec_size
/ 8, inst
->offset
);
1232 fs_generator::generate_scratch_read_gen7(fs_inst
*inst
, struct brw_reg dst
)
1234 gen7_block_read_scratch(p
, dst
, inst
->exec_size
/ 8, inst
->offset
);
1238 fs_generator::generate_uniform_pull_constant_load(fs_inst
*inst
,
1240 struct brw_reg index
,
1241 struct brw_reg offset
)
1243 assert(inst
->mlen
!= 0);
1245 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1246 index
.type
== BRW_REGISTER_TYPE_UD
);
1247 uint32_t surf_index
= index
.ud
;
1249 assert(offset
.file
== BRW_IMMEDIATE_VALUE
&&
1250 offset
.type
== BRW_REGISTER_TYPE_UD
);
1251 uint32_t read_offset
= offset
.ud
;
1253 brw_oword_block_read(p
, dst
, brw_message_reg(inst
->base_mrf
),
1254 read_offset
, surf_index
);
1258 fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst
*inst
,
1260 struct brw_reg index
,
1261 struct brw_reg offset
)
1263 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1265 assert(offset
.file
== BRW_GENERAL_REGISTER_FILE
);
1266 /* Reference just the dword we need, to avoid angering validate_reg(). */
1267 offset
= brw_vec1_grf(offset
.nr
, 0);
1269 /* We use the SIMD4x2 mode because we want to end up with 4 components in
1270 * the destination loaded consecutively from the same offset (which appears
1271 * in the first component, and the rest are ignored).
1273 dst
.width
= BRW_WIDTH_4
;
1275 struct brw_reg src
= offset
;
1276 bool header_present
= false;
1278 if (devinfo
->gen
>= 9) {
1279 /* Skylake requires a message header in order to use SIMD4x2 mode. */
1280 src
= retype(brw_vec4_grf(offset
.nr
, 0), BRW_REGISTER_TYPE_UD
);
1281 header_present
= true;
1283 brw_push_insn_state(p
);
1284 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1285 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1286 brw_MOV(p
, vec8(src
), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD
));
1287 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1289 brw_MOV(p
, get_element_ud(src
, 2),
1290 brw_imm_ud(GEN9_SAMPLER_SIMD_MODE_EXTENSION_SIMD4X2
));
1291 brw_pop_insn_state(p
);
1294 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1296 uint32_t surf_index
= index
.ud
;
1298 brw_push_insn_state(p
);
1299 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1300 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1301 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1302 brw_inst_set_exec_size(devinfo
, send
, BRW_EXECUTE_4
);
1303 brw_pop_insn_state(p
);
1305 brw_set_dest(p
, send
, dst
);
1306 brw_set_src0(p
, send
, src
);
1307 brw_set_sampler_message(p
, send
,
1309 0, /* LD message ignores sampler unit */
1310 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1314 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1318 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1320 brw_push_insn_state(p
);
1321 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1322 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1324 /* a0.0 = surf_index & 0xff */
1325 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1326 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1327 brw_set_dest(p
, insn_and
, addr
);
1328 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1329 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1331 /* dst = send(payload, a0.0 | <descriptor>) */
1332 brw_inst
*insn
= brw_send_indirect_message(
1333 p
, BRW_SFID_SAMPLER
, dst
, src
, addr
);
1334 brw_set_sampler_message(p
, insn
,
1336 0, /* LD message ignores sampler unit */
1337 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1341 BRW_SAMPLER_SIMD_MODE_SIMD4X2
,
1344 brw_pop_insn_state(p
);
1349 fs_generator::generate_varying_pull_constant_load(fs_inst
*inst
,
1351 struct brw_reg index
,
1352 struct brw_reg offset
)
1354 assert(devinfo
->gen
< 7); /* Should use the gen7 variant. */
1355 assert(inst
->header_size
!= 0);
1358 assert(index
.file
== BRW_IMMEDIATE_VALUE
&&
1359 index
.type
== BRW_REGISTER_TYPE_UD
);
1360 uint32_t surf_index
= index
.ud
;
1362 uint32_t simd_mode
, rlen
, msg_type
;
1363 if (dispatch_width
== 16) {
1364 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1367 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1371 if (devinfo
->gen
>= 5)
1372 msg_type
= GEN5_SAMPLER_MESSAGE_SAMPLE_LD
;
1374 /* We always use the SIMD16 message so that we only have to load U, and
1377 msg_type
= BRW_SAMPLER_MESSAGE_SIMD16_LD
;
1378 assert(inst
->mlen
== 3);
1379 assert(inst
->regs_written
== 8);
1381 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1384 struct brw_reg offset_mrf
= retype(brw_message_reg(inst
->base_mrf
+ 1),
1385 BRW_REGISTER_TYPE_D
);
1386 brw_MOV(p
, offset_mrf
, offset
);
1388 struct brw_reg header
= brw_vec8_grf(0, 0);
1389 gen6_resolve_implied_move(p
, &header
, inst
->base_mrf
);
1391 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1392 brw_inst_set_qtr_control(p
->devinfo
, send
, BRW_COMPRESSION_NONE
);
1393 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1394 brw_set_src0(p
, send
, header
);
1395 if (devinfo
->gen
< 6)
1396 brw_inst_set_base_mrf(p
->devinfo
, send
, inst
->base_mrf
);
1398 /* Our surface is set up as floats, regardless of what actual data is
1401 uint32_t return_format
= BRW_SAMPLER_RETURN_FORMAT_FLOAT32
;
1402 brw_set_sampler_message(p
, send
,
1404 0, /* sampler (unused) */
1408 inst
->header_size
!= 0,
1414 fs_generator::generate_varying_pull_constant_load_gen7(fs_inst
*inst
,
1416 struct brw_reg index
,
1417 struct brw_reg offset
)
1419 assert(devinfo
->gen
>= 7);
1420 /* Varying-offset pull constant loads are treated as a normal expression on
1421 * gen7, so the fact that it's a send message is hidden at the IR level.
1423 assert(inst
->header_size
== 0);
1424 assert(!inst
->mlen
);
1425 assert(index
.type
== BRW_REGISTER_TYPE_UD
);
1427 uint32_t simd_mode
, rlen
, mlen
;
1428 if (dispatch_width
== 16) {
1431 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD16
;
1435 simd_mode
= BRW_SAMPLER_SIMD_MODE_SIMD8
;
1438 if (index
.file
== BRW_IMMEDIATE_VALUE
) {
1440 uint32_t surf_index
= index
.ud
;
1442 brw_inst
*send
= brw_next_insn(p
, BRW_OPCODE_SEND
);
1443 brw_set_dest(p
, send
, retype(dst
, BRW_REGISTER_TYPE_UW
));
1444 brw_set_src0(p
, send
, offset
);
1445 brw_set_sampler_message(p
, send
,
1447 0, /* LD message ignores sampler unit */
1448 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1451 false, /* no header */
1457 struct brw_reg addr
= vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD
));
1459 brw_push_insn_state(p
);
1460 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1461 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1463 /* a0.0 = surf_index & 0xff */
1464 brw_inst
*insn_and
= brw_next_insn(p
, BRW_OPCODE_AND
);
1465 brw_inst_set_exec_size(p
->devinfo
, insn_and
, BRW_EXECUTE_1
);
1466 brw_set_dest(p
, insn_and
, addr
);
1467 brw_set_src0(p
, insn_and
, vec1(retype(index
, BRW_REGISTER_TYPE_UD
)));
1468 brw_set_src1(p
, insn_and
, brw_imm_ud(0x0ff));
1470 brw_pop_insn_state(p
);
1472 /* dst = send(offset, a0.0 | <descriptor>) */
1473 brw_inst
*insn
= brw_send_indirect_message(
1474 p
, BRW_SFID_SAMPLER
, retype(dst
, BRW_REGISTER_TYPE_UW
),
1476 brw_set_sampler_message(p
, insn
,
1479 GEN5_SAMPLER_MESSAGE_SAMPLE_LD
,
1489 * Cause the current pixel/sample mask (from R1.7 bits 15:0) to be transferred
1490 * into the flags register (f0.0).
1492 * Used only on Gen6 and above.
1495 fs_generator::generate_mov_dispatch_to_flags(fs_inst
*inst
)
1497 struct brw_reg flags
= brw_flag_reg(0, inst
->flag_subreg
);
1498 struct brw_reg dispatch_mask
;
1500 if (devinfo
->gen
>= 6)
1501 dispatch_mask
= retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW
);
1503 dispatch_mask
= retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW
);
1505 brw_push_insn_state(p
);
1506 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1507 brw_MOV(p
, flags
, dispatch_mask
);
1508 brw_pop_insn_state(p
);
1512 fs_generator::generate_pixel_interpolator_query(fs_inst
*inst
,
1515 struct brw_reg msg_data
,
1518 assert(msg_data
.type
== BRW_REGISTER_TYPE_UD
);
1520 brw_pixel_interpolator_query(p
,
1521 retype(dst
, BRW_REGISTER_TYPE_UW
),
1523 inst
->pi_noperspective
,
1527 inst
->regs_written
);
1532 * Sets the first word of a vgrf for gen7+ simd4x2 uniform pull constant
1533 * sampler LD messages.
1535 * We don't want to bake it into the send message's code generation because
1536 * that means we don't get a chance to schedule the instructions.
1539 fs_generator::generate_set_simd4x2_offset(fs_inst
*inst
,
1541 struct brw_reg value
)
1543 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1545 brw_push_insn_state(p
);
1546 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1547 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1548 brw_set_default_mask_control(p
, BRW_MASK_DISABLE
);
1549 brw_MOV(p
, retype(brw_vec1_reg(dst
.file
, dst
.nr
, 0), value
.type
), value
);
1550 brw_pop_insn_state(p
);
1553 /* Sets vstride=1, width=4, hstride=0 of register src1 during
1554 * the ADD instruction.
1557 fs_generator::generate_set_sample_id(fs_inst
*inst
,
1559 struct brw_reg src0
,
1560 struct brw_reg src1
)
1562 assert(dst
.type
== BRW_REGISTER_TYPE_D
||
1563 dst
.type
== BRW_REGISTER_TYPE_UD
);
1564 assert(src0
.type
== BRW_REGISTER_TYPE_D
||
1565 src0
.type
== BRW_REGISTER_TYPE_UD
);
1567 struct brw_reg reg
= stride(src1
, 1, 4, 0);
1568 if (devinfo
->gen
>= 8 || dispatch_width
== 8) {
1569 brw_ADD(p
, dst
, src0
, reg
);
1570 } else if (dispatch_width
== 16) {
1571 brw_push_insn_state(p
);
1572 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1573 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1574 brw_ADD(p
, firsthalf(dst
), firsthalf(src0
), reg
);
1575 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1576 brw_ADD(p
, sechalf(dst
), sechalf(src0
), suboffset(reg
, 2));
1577 brw_pop_insn_state(p
);
1582 fs_generator::generate_pack_half_2x16_split(fs_inst
*inst
,
1587 assert(devinfo
->gen
>= 7);
1588 assert(dst
.type
== BRW_REGISTER_TYPE_UD
);
1589 assert(x
.type
== BRW_REGISTER_TYPE_F
);
1590 assert(y
.type
== BRW_REGISTER_TYPE_F
);
1592 /* From the Ivybridge PRM, Vol4, Part3, Section 6.27 f32to16:
1594 * Because this instruction does not have a 16-bit floating-point type,
1595 * the destination data type must be Word (W).
1597 * The destination must be DWord-aligned and specify a horizontal stride
1598 * (HorzStride) of 2. The 16-bit result is stored in the lower word of
1599 * each destination channel and the upper word is not modified.
1601 struct brw_reg dst_w
= spread(retype(dst
, BRW_REGISTER_TYPE_W
), 2);
1603 /* Give each 32-bit channel of dst the form below, where "." means
1607 brw_F32TO16(p
, dst_w
, y
);
1612 brw_SHL(p
, dst
, dst
, brw_imm_ud(16u));
1614 /* And, finally the form of packHalf2x16's output:
1617 brw_F32TO16(p
, dst_w
, x
);
1621 fs_generator::generate_unpack_half_2x16_split(fs_inst
*inst
,
1625 assert(devinfo
->gen
>= 7);
1626 assert(dst
.type
== BRW_REGISTER_TYPE_F
);
1627 assert(src
.type
== BRW_REGISTER_TYPE_UD
);
1629 /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
1631 * Because this instruction does not have a 16-bit floating-point type,
1632 * the source data type must be Word (W). The destination type must be
1635 struct brw_reg src_w
= spread(retype(src
, BRW_REGISTER_TYPE_W
), 2);
1637 /* Each channel of src has the form of unpackHalf2x16's input: 0xhhhhllll.
1638 * For the Y case, we wish to access only the upper word; therefore
1639 * a 16-bit subregister offset is needed.
1641 assert(inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
||
1642 inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
);
1643 if (inst
->opcode
== FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
)
1646 brw_F16TO32(p
, dst
, src_w
);
1650 fs_generator::generate_shader_time_add(fs_inst
*inst
,
1651 struct brw_reg payload
,
1652 struct brw_reg offset
,
1653 struct brw_reg value
)
1655 assert(devinfo
->gen
>= 7);
1656 brw_push_insn_state(p
);
1657 brw_set_default_mask_control(p
, true);
1659 assert(payload
.file
== BRW_GENERAL_REGISTER_FILE
);
1660 struct brw_reg payload_offset
= retype(brw_vec1_grf(payload
.nr
, 0),
1662 struct brw_reg payload_value
= retype(brw_vec1_grf(payload
.nr
+ 1, 0),
1665 assert(offset
.file
== BRW_IMMEDIATE_VALUE
);
1666 if (value
.file
== BRW_GENERAL_REGISTER_FILE
) {
1667 value
.width
= BRW_WIDTH_1
;
1668 value
.hstride
= BRW_HORIZONTAL_STRIDE_0
;
1669 value
.vstride
= BRW_VERTICAL_STRIDE_0
;
1671 assert(value
.file
== BRW_IMMEDIATE_VALUE
);
1674 /* Trying to deal with setup of the params from the IR is crazy in the FS8
1675 * case, and we don't really care about squeezing every bit of performance
1676 * out of this path, so we just emit the MOVs from here.
1678 brw_MOV(p
, payload_offset
, offset
);
1679 brw_MOV(p
, payload_value
, value
);
1680 brw_shader_time_add(p
, payload
,
1681 prog_data
->binding_table
.shader_time_start
);
1682 brw_pop_insn_state(p
);
1684 brw_mark_surface_used(prog_data
,
1685 prog_data
->binding_table
.shader_time_start
);
1689 fs_generator::enable_debug(const char *shader_name
)
1692 this->shader_name
= shader_name
;
1696 fs_generator::generate_code(const cfg_t
*cfg
, int dispatch_width
)
1698 /* align to 64 byte boundary. */
1699 while (p
->next_insn_offset
% 64)
1702 this->dispatch_width
= dispatch_width
;
1703 if (dispatch_width
== 16)
1704 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1706 int start_offset
= p
->next_insn_offset
;
1707 int spill_count
= 0, fill_count
= 0;
1710 struct annotation_info annotation
;
1711 memset(&annotation
, 0, sizeof(annotation
));
1713 foreach_block_and_inst (block
, fs_inst
, inst
, cfg
) {
1714 struct brw_reg src
[3], dst
;
1715 unsigned int last_insn_offset
= p
->next_insn_offset
;
1716 bool multiple_instructions_emitted
= false;
1718 /* From the Broadwell PRM, Volume 7, "3D-Media-GPGPU", in the
1719 * "Register Region Restrictions" section: for BDW, SKL:
1721 * "A POW/FDIV operation must not be followed by an instruction
1722 * that requires two destination registers."
1724 * The documentation is often lacking annotations for Atom parts,
1725 * and empirically this affects CHV as well.
1727 if (devinfo
->gen
>= 8 &&
1729 brw_inst_opcode(devinfo
, brw_last_inst
) == BRW_OPCODE_MATH
&&
1730 brw_inst_math_function(devinfo
, brw_last_inst
) == BRW_MATH_FUNCTION_POW
&&
1731 inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
) {
1733 last_insn_offset
= p
->next_insn_offset
;
1736 if (unlikely(debug_flag
))
1737 annotate(p
->devinfo
, &annotation
, cfg
, inst
, p
->next_insn_offset
);
1739 switch (inst
->exec_size
) {
1743 assert(inst
->force_writemask_all
);
1744 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1747 if (inst
->force_sechalf
) {
1748 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1750 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1755 /* If the instruction writes to more than one register, it needs to
1756 * be a "compressed" instruction on Gen <= 5.
1758 if (inst
->dst
.component_size(inst
->exec_size
) > REG_SIZE
)
1759 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1761 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1764 unreachable("Invalid instruction width");
1767 for (unsigned int i
= 0; i
< inst
->sources
; i
++) {
1768 src
[i
] = brw_reg_from_fs_reg(p
, inst
, &inst
->src
[i
], devinfo
->gen
);
1770 /* The accumulator result appears to get used for the
1771 * conditional modifier generation. When negating a UD
1772 * value, there is a 33rd bit generated for the sign in the
1773 * accumulator value, so now you can't check, for example,
1774 * equality with a 32-bit value. See piglit fs-op-neg-uvec4.
1776 assert(!inst
->conditional_mod
||
1777 inst
->src
[i
].type
!= BRW_REGISTER_TYPE_UD
||
1778 !inst
->src
[i
].negate
);
1780 dst
= brw_reg_from_fs_reg(p
, inst
, &inst
->dst
, devinfo
->gen
);
1782 brw_set_default_predicate_control(p
, inst
->predicate
);
1783 brw_set_default_predicate_inverse(p
, inst
->predicate_inverse
);
1784 brw_set_default_flag_reg(p
, 0, inst
->flag_subreg
);
1785 brw_set_default_saturate(p
, inst
->saturate
);
1786 brw_set_default_mask_control(p
, inst
->force_writemask_all
);
1787 brw_set_default_acc_write_control(p
, inst
->writes_accumulator
);
1788 brw_set_default_exec_size(p
, cvt(inst
->exec_size
) - 1);
1790 assert(inst
->base_mrf
+ inst
->mlen
<= BRW_MAX_MRF(devinfo
->gen
));
1791 assert(inst
->mlen
<= BRW_MAX_MSG_LENGTH
);
1793 switch (inst
->opcode
) {
1794 case BRW_OPCODE_MOV
:
1795 brw_MOV(p
, dst
, src
[0]);
1797 case BRW_OPCODE_ADD
:
1798 brw_ADD(p
, dst
, src
[0], src
[1]);
1800 case BRW_OPCODE_MUL
:
1801 brw_MUL(p
, dst
, src
[0], src
[1]);
1803 case BRW_OPCODE_AVG
:
1804 brw_AVG(p
, dst
, src
[0], src
[1]);
1806 case BRW_OPCODE_MACH
:
1807 brw_MACH(p
, dst
, src
[0], src
[1]);
1810 case BRW_OPCODE_LINE
:
1811 brw_LINE(p
, dst
, src
[0], src
[1]);
1814 case BRW_OPCODE_MAD
:
1815 assert(devinfo
->gen
>= 6);
1816 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1817 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1818 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1819 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1820 brw_inst
*f
= brw_MAD(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1821 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1822 brw_inst
*s
= brw_MAD(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1823 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1825 if (inst
->conditional_mod
) {
1826 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1827 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1828 multiple_instructions_emitted
= true;
1831 brw_MAD(p
, dst
, src
[0], src
[1], src
[2]);
1833 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1836 case BRW_OPCODE_LRP
:
1837 assert(devinfo
->gen
>= 6);
1838 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1839 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1840 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1841 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1842 brw_inst
*f
= brw_LRP(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1843 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1844 brw_inst
*s
= brw_LRP(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1845 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1847 if (inst
->conditional_mod
) {
1848 brw_inst_set_cond_modifier(p
->devinfo
, f
, inst
->conditional_mod
);
1849 brw_inst_set_cond_modifier(p
->devinfo
, s
, inst
->conditional_mod
);
1850 multiple_instructions_emitted
= true;
1853 brw_LRP(p
, dst
, src
[0], src
[1], src
[2]);
1855 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1858 case BRW_OPCODE_FRC
:
1859 brw_FRC(p
, dst
, src
[0]);
1861 case BRW_OPCODE_RNDD
:
1862 brw_RNDD(p
, dst
, src
[0]);
1864 case BRW_OPCODE_RNDE
:
1865 brw_RNDE(p
, dst
, src
[0]);
1867 case BRW_OPCODE_RNDZ
:
1868 brw_RNDZ(p
, dst
, src
[0]);
1871 case BRW_OPCODE_AND
:
1872 brw_AND(p
, dst
, src
[0], src
[1]);
1875 brw_OR(p
, dst
, src
[0], src
[1]);
1877 case BRW_OPCODE_XOR
:
1878 brw_XOR(p
, dst
, src
[0], src
[1]);
1880 case BRW_OPCODE_NOT
:
1881 brw_NOT(p
, dst
, src
[0]);
1883 case BRW_OPCODE_ASR
:
1884 brw_ASR(p
, dst
, src
[0], src
[1]);
1886 case BRW_OPCODE_SHR
:
1887 brw_SHR(p
, dst
, src
[0], src
[1]);
1889 case BRW_OPCODE_SHL
:
1890 brw_SHL(p
, dst
, src
[0], src
[1]);
1892 case BRW_OPCODE_F32TO16
:
1893 assert(devinfo
->gen
>= 7);
1894 brw_F32TO16(p
, dst
, src
[0]);
1896 case BRW_OPCODE_F16TO32
:
1897 assert(devinfo
->gen
>= 7);
1898 brw_F16TO32(p
, dst
, src
[0]);
1900 case BRW_OPCODE_CMP
:
1901 /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says
1902 * that when the destination is a GRF that the dependency-clear bit on
1903 * the flag register is cleared early.
1905 * Suggested workarounds are to disable coissuing CMP instructions
1906 * or to split CMP(16) instructions into two CMP(8) instructions.
1908 * We choose to split into CMP(8) instructions since disabling
1909 * coissuing would affect CMP instructions not otherwise affected by
1912 if (dispatch_width
== 16 && devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1913 if (dst
.file
== BRW_GENERAL_REGISTER_FILE
) {
1914 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1915 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1916 brw_CMP(p
, firsthalf(dst
), inst
->conditional_mod
,
1917 firsthalf(src
[0]), firsthalf(src
[1]));
1918 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1919 brw_CMP(p
, sechalf(dst
), inst
->conditional_mod
,
1920 sechalf(src
[0]), sechalf(src
[1]));
1921 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1923 multiple_instructions_emitted
= true;
1924 } else if (dst
.file
== BRW_ARCHITECTURE_REGISTER_FILE
) {
1925 /* For unknown reasons, the aforementioned workaround is not
1926 * sufficient. Overriding the type when the destination is the
1927 * null register is necessary but not sufficient by itself.
1929 assert(dst
.nr
== BRW_ARF_NULL
);
1930 dst
.type
= BRW_REGISTER_TYPE_D
;
1931 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1933 unreachable("not reached");
1936 brw_CMP(p
, dst
, inst
->conditional_mod
, src
[0], src
[1]);
1939 case BRW_OPCODE_SEL
:
1940 brw_SEL(p
, dst
, src
[0], src
[1]);
1942 case BRW_OPCODE_BFREV
:
1943 assert(devinfo
->gen
>= 7);
1944 /* BFREV only supports UD type for src and dst. */
1945 brw_BFREV(p
, retype(dst
, BRW_REGISTER_TYPE_UD
),
1946 retype(src
[0], BRW_REGISTER_TYPE_UD
));
1948 case BRW_OPCODE_FBH
:
1949 assert(devinfo
->gen
>= 7);
1950 /* FBH only supports UD type for dst. */
1951 brw_FBH(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1953 case BRW_OPCODE_FBL
:
1954 assert(devinfo
->gen
>= 7);
1955 /* FBL only supports UD type for dst. */
1956 brw_FBL(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1958 case BRW_OPCODE_CBIT
:
1959 assert(devinfo
->gen
>= 7);
1960 /* CBIT only supports UD type for dst. */
1961 brw_CBIT(p
, retype(dst
, BRW_REGISTER_TYPE_UD
), src
[0]);
1963 case BRW_OPCODE_ADDC
:
1964 assert(devinfo
->gen
>= 7);
1965 brw_ADDC(p
, dst
, src
[0], src
[1]);
1967 case BRW_OPCODE_SUBB
:
1968 assert(devinfo
->gen
>= 7);
1969 brw_SUBB(p
, dst
, src
[0], src
[1]);
1971 case BRW_OPCODE_MAC
:
1972 brw_MAC(p
, dst
, src
[0], src
[1]);
1975 case BRW_OPCODE_BFE
:
1976 assert(devinfo
->gen
>= 7);
1977 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
1978 if (dispatch_width
== 16 && !devinfo
->supports_simd16_3src
) {
1979 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
1980 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
1981 brw_BFE(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
1982 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
1983 brw_BFE(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
1984 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
1986 brw_BFE(p
, dst
, src
[0], src
[1], src
[2]);
1988 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
1991 case BRW_OPCODE_BFI1
:
1992 assert(devinfo
->gen
>= 7);
1993 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
1996 * "Force BFI instructions to be executed always in SIMD8."
1998 if (dispatch_width
== 16 && devinfo
->is_haswell
) {
1999 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2000 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2001 brw_BFI1(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]));
2002 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2003 brw_BFI1(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]));
2004 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2006 brw_BFI1(p
, dst
, src
[0], src
[1]);
2009 case BRW_OPCODE_BFI2
:
2010 assert(devinfo
->gen
>= 7);
2011 brw_set_default_access_mode(p
, BRW_ALIGN_16
);
2012 /* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
2015 * "Force BFI instructions to be executed always in SIMD8."
2017 * Otherwise we would be able to emit compressed instructions like we
2018 * do for the other three-source instructions.
2020 if (dispatch_width
== 16 &&
2021 (devinfo
->is_haswell
|| !devinfo
->supports_simd16_3src
)) {
2022 brw_set_default_exec_size(p
, BRW_EXECUTE_8
);
2023 brw_set_default_compression_control(p
, BRW_COMPRESSION_NONE
);
2024 brw_BFI2(p
, firsthalf(dst
), firsthalf(src
[0]), firsthalf(src
[1]), firsthalf(src
[2]));
2025 brw_set_default_compression_control(p
, BRW_COMPRESSION_2NDHALF
);
2026 brw_BFI2(p
, sechalf(dst
), sechalf(src
[0]), sechalf(src
[1]), sechalf(src
[2]));
2027 brw_set_default_compression_control(p
, BRW_COMPRESSION_COMPRESSED
);
2029 brw_BFI2(p
, dst
, src
[0], src
[1], src
[2]);
2031 brw_set_default_access_mode(p
, BRW_ALIGN_1
);
2035 if (inst
->src
[0].file
!= BAD_FILE
) {
2036 /* The instruction has an embedded compare (only allowed on gen6) */
2037 assert(devinfo
->gen
== 6);
2038 gen6_IF(p
, inst
->conditional_mod
, src
[0], src
[1]);
2040 brw_IF(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
2044 case BRW_OPCODE_ELSE
:
2047 case BRW_OPCODE_ENDIF
:
2052 brw_DO(p
, dispatch_width
== 16 ? BRW_EXECUTE_16
: BRW_EXECUTE_8
);
2055 case BRW_OPCODE_BREAK
:
2057 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2059 case BRW_OPCODE_CONTINUE
:
2061 brw_set_default_predicate_control(p
, BRW_PREDICATE_NONE
);
2064 case BRW_OPCODE_WHILE
:
2069 case SHADER_OPCODE_RCP
:
2070 case SHADER_OPCODE_RSQ
:
2071 case SHADER_OPCODE_SQRT
:
2072 case SHADER_OPCODE_EXP2
:
2073 case SHADER_OPCODE_LOG2
:
2074 case SHADER_OPCODE_SIN
:
2075 case SHADER_OPCODE_COS
:
2076 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2077 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2078 if (devinfo
->gen
>= 7) {
2079 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0],
2081 } else if (devinfo
->gen
== 6) {
2082 generate_math_gen6(inst
, dst
, src
[0], brw_null_reg());
2083 } else if (devinfo
->gen
== 5 || devinfo
->is_g4x
) {
2084 generate_math_g45(inst
, dst
, src
[0]);
2086 generate_math_gen4(inst
, dst
, src
[0]);
2089 case SHADER_OPCODE_INT_QUOTIENT
:
2090 case SHADER_OPCODE_INT_REMAINDER
:
2091 case SHADER_OPCODE_POW
:
2092 assert(devinfo
->gen
< 6 || inst
->mlen
== 0);
2093 assert(inst
->conditional_mod
== BRW_CONDITIONAL_NONE
);
2094 if (devinfo
->gen
>= 7 && inst
->opcode
== SHADER_OPCODE_POW
) {
2095 gen6_math(p
, dst
, brw_math_function(inst
->opcode
), src
[0], src
[1]);
2096 } else if (devinfo
->gen
>= 6) {
2097 generate_math_gen6(inst
, dst
, src
[0], src
[1]);
2099 generate_math_gen4(inst
, dst
, src
[0]);
2102 case FS_OPCODE_CINTERP
:
2103 brw_MOV(p
, dst
, src
[0]);
2105 case FS_OPCODE_LINTERP
:
2106 generate_linterp(inst
, dst
, src
);
2108 case FS_OPCODE_PIXEL_X
:
2109 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2110 src
[0].subnr
= 0 * type_sz(src
[0].type
);
2111 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2113 case FS_OPCODE_PIXEL_Y
:
2114 assert(src
[0].type
== BRW_REGISTER_TYPE_UW
);
2115 src
[0].subnr
= 4 * type_sz(src
[0].type
);
2116 brw_MOV(p
, dst
, stride(src
[0], 8, 4, 1));
2118 case FS_OPCODE_GET_BUFFER_SIZE
:
2119 generate_get_buffer_size(inst
, dst
, src
[0], src
[1]);
2121 case SHADER_OPCODE_TEX
:
2123 case SHADER_OPCODE_TXD
:
2124 case SHADER_OPCODE_TXF
:
2125 case SHADER_OPCODE_TXF_CMS
:
2126 case SHADER_OPCODE_TXF_CMS_W
:
2127 case SHADER_OPCODE_TXF_UMS
:
2128 case SHADER_OPCODE_TXF_MCS
:
2129 case SHADER_OPCODE_TXL
:
2130 case SHADER_OPCODE_TXS
:
2131 case SHADER_OPCODE_LOD
:
2132 case SHADER_OPCODE_TG4
:
2133 case SHADER_OPCODE_TG4_OFFSET
:
2134 case SHADER_OPCODE_SAMPLEINFO
:
2135 generate_tex(inst
, dst
, src
[0], src
[1], src
[2]);
2137 case FS_OPCODE_DDX_COARSE
:
2138 case FS_OPCODE_DDX_FINE
:
2139 generate_ddx(inst
->opcode
, dst
, src
[0]);
2141 case FS_OPCODE_DDY_COARSE
:
2142 case FS_OPCODE_DDY_FINE
:
2143 assert(src
[1].file
== BRW_IMMEDIATE_VALUE
);
2144 generate_ddy(inst
->opcode
, dst
, src
[0], src
[1].ud
);
2147 case SHADER_OPCODE_GEN4_SCRATCH_WRITE
:
2148 generate_scratch_write(inst
, src
[0]);
2152 case SHADER_OPCODE_GEN4_SCRATCH_READ
:
2153 generate_scratch_read(inst
, dst
);
2157 case SHADER_OPCODE_GEN7_SCRATCH_READ
:
2158 generate_scratch_read_gen7(inst
, dst
);
2162 case SHADER_OPCODE_MOV_INDIRECT
:
2163 generate_mov_indirect(inst
, dst
, src
[0], src
[1]);
2166 case SHADER_OPCODE_URB_READ_SIMD8
:
2167 case SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
:
2168 generate_urb_read(inst
, dst
, src
[0]);
2171 case SHADER_OPCODE_URB_WRITE_SIMD8
:
2172 case SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2173 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
:
2174 case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2175 generate_urb_write(inst
, src
[0]);
2178 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
:
2179 generate_uniform_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2182 case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7
:
2183 generate_uniform_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2186 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD
:
2187 generate_varying_pull_constant_load(inst
, dst
, src
[0], src
[1]);
2190 case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7
:
2191 generate_varying_pull_constant_load_gen7(inst
, dst
, src
[0], src
[1]);
2194 case FS_OPCODE_REP_FB_WRITE
:
2195 case FS_OPCODE_FB_WRITE
:
2196 generate_fb_write(inst
, src
[0]);
2199 case FS_OPCODE_MOV_DISPATCH_TO_FLAGS
:
2200 generate_mov_dispatch_to_flags(inst
);
2203 case FS_OPCODE_DISCARD_JUMP
:
2204 generate_discard_jump(inst
);
2207 case SHADER_OPCODE_SHADER_TIME_ADD
:
2208 generate_shader_time_add(inst
, src
[0], src
[1], src
[2]);
2211 case SHADER_OPCODE_UNTYPED_ATOMIC
:
2212 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2213 brw_untyped_atomic(p
, dst
, src
[0], src
[1], src
[2].ud
,
2214 inst
->mlen
, !inst
->dst
.is_null());
2217 case SHADER_OPCODE_UNTYPED_SURFACE_READ
:
2218 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2219 brw_untyped_surface_read(p
, dst
, src
[0], src
[1],
2220 inst
->mlen
, src
[2].ud
);
2223 case SHADER_OPCODE_UNTYPED_SURFACE_WRITE
:
2224 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2225 brw_untyped_surface_write(p
, src
[0], src
[1],
2226 inst
->mlen
, src
[2].ud
);
2229 case SHADER_OPCODE_TYPED_ATOMIC
:
2230 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2231 brw_typed_atomic(p
, dst
, src
[0], src
[1],
2232 src
[2].ud
, inst
->mlen
, !inst
->dst
.is_null());
2235 case SHADER_OPCODE_TYPED_SURFACE_READ
:
2236 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2237 brw_typed_surface_read(p
, dst
, src
[0], src
[1],
2238 inst
->mlen
, src
[2].ud
);
2241 case SHADER_OPCODE_TYPED_SURFACE_WRITE
:
2242 assert(src
[2].file
== BRW_IMMEDIATE_VALUE
);
2243 brw_typed_surface_write(p
, src
[0], src
[1], inst
->mlen
, src
[2].ud
);
2246 case SHADER_OPCODE_MEMORY_FENCE
:
2247 brw_memory_fence(p
, dst
);
2250 case FS_OPCODE_SET_SIMD4X2_OFFSET
:
2251 generate_set_simd4x2_offset(inst
, dst
, src
[0]);
2254 case SHADER_OPCODE_FIND_LIVE_CHANNEL
:
2255 brw_find_live_channel(p
, dst
);
2258 case SHADER_OPCODE_BROADCAST
:
2259 brw_broadcast(p
, dst
, src
[0], src
[1]);
2262 case SHADER_OPCODE_EXTRACT_BYTE
: {
2263 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2264 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2266 enum brw_reg_type type
=
2267 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_B
2268 : BRW_REGISTER_TYPE_UB
;
2269 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 4));
2273 case SHADER_OPCODE_EXTRACT_WORD
: {
2274 assert(src
[0].type
== BRW_REGISTER_TYPE_D
||
2275 src
[0].type
== BRW_REGISTER_TYPE_UD
);
2277 enum brw_reg_type type
=
2278 src
[0].type
== BRW_REGISTER_TYPE_D
? BRW_REGISTER_TYPE_W
2279 : BRW_REGISTER_TYPE_UW
;
2280 brw_MOV(p
, dst
, spread(suboffset(retype(src
[0], type
), src
[1].ud
), 2));
2284 case FS_OPCODE_SET_SAMPLE_ID
:
2285 generate_set_sample_id(inst
, dst
, src
[0], src
[1]);
2288 case FS_OPCODE_PACK_HALF_2x16_SPLIT
:
2289 generate_pack_half_2x16_split(inst
, dst
, src
[0], src
[1]);
2292 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
:
2293 case FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
:
2294 generate_unpack_half_2x16_split(inst
, dst
, src
[0]);
2297 case FS_OPCODE_PLACEHOLDER_HALT
:
2298 /* This is the place where the final HALT needs to be inserted if
2299 * we've emitted any discards. If not, this will emit no code.
2301 if (!patch_discard_jumps_to_fb_writes()) {
2302 if (unlikely(debug_flag
)) {
2303 annotation
.ann_count
--;
2308 case FS_OPCODE_INTERPOLATE_AT_CENTROID
:
2309 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2310 GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID
);
2313 case FS_OPCODE_INTERPOLATE_AT_SAMPLE
:
2314 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2315 GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE
);
2318 case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
:
2319 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2320 GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET
);
2323 case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
:
2324 generate_pixel_interpolator_query(inst
, dst
, src
[0], src
[1],
2325 GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET
);
2328 case CS_OPCODE_CS_TERMINATE
:
2329 generate_cs_terminate(inst
, src
[0]);
2332 case SHADER_OPCODE_BARRIER
:
2333 generate_barrier(inst
, src
[0]);
2336 case FS_OPCODE_PACK_STENCIL_REF
:
2337 generate_stencil_ref_packing(inst
, dst
, src
[0]);
2341 unreachable("Unsupported opcode");
2343 case SHADER_OPCODE_LOAD_PAYLOAD
:
2344 unreachable("Should be lowered by lower_load_payload()");
2347 if (multiple_instructions_emitted
)
2350 if (inst
->no_dd_clear
|| inst
->no_dd_check
|| inst
->conditional_mod
) {
2351 assert(p
->next_insn_offset
== last_insn_offset
+ 16 ||
2352 !"conditional_mod, no_dd_check, or no_dd_clear set for IR "
2353 "emitting more than 1 instruction");
2355 brw_inst
*last
= &p
->store
[last_insn_offset
/ 16];
2357 if (inst
->conditional_mod
)
2358 brw_inst_set_cond_modifier(p
->devinfo
, last
, inst
->conditional_mod
);
2359 brw_inst_set_no_dd_clear(p
->devinfo
, last
, inst
->no_dd_clear
);
2360 brw_inst_set_no_dd_check(p
->devinfo
, last
, inst
->no_dd_check
);
2365 annotation_finalize(&annotation
, p
->next_insn_offset
);
2368 bool validated
= brw_validate_instructions(p
, start_offset
, &annotation
);
2370 if (unlikely(debug_flag
))
2371 brw_validate_instructions(p
, start_offset
, &annotation
);
2374 int before_size
= p
->next_insn_offset
- start_offset
;
2375 brw_compact_instructions(p
, start_offset
, annotation
.ann_count
,
2377 int after_size
= p
->next_insn_offset
- start_offset
;
2379 if (unlikely(debug_flag
)) {
2380 fprintf(stderr
, "Native code for %s\n"
2381 "SIMD%d shader: %d instructions. %d loops. %u cycles. %d:%d spills:fills. Promoted %u constants. Compacted %d to %d"
2382 " bytes (%.0f%%)\n",
2383 shader_name
, dispatch_width
, before_size
/ 16, loop_count
, cfg
->cycle_count
,
2384 spill_count
, fill_count
, promoted_constants
, before_size
, after_size
,
2385 100.0f
* (before_size
- after_size
) / before_size
);
2387 dump_assembly(p
->store
, annotation
.ann_count
, annotation
.ann
,
2389 ralloc_free(annotation
.mem_ctx
);
2393 compiler
->shader_debug_log(log_data
,
2394 "%s SIMD%d shader: %d inst, %d loops, %u cycles, "
2395 "%d:%d spills:fills, Promoted %u constants, "
2396 "compacted %d to %d bytes.",
2397 _mesa_shader_stage_to_abbrev(stage
),
2398 dispatch_width
, before_size
/ 16,
2399 loop_count
, cfg
->cycle_count
, spill_count
,
2400 fill_count
, promoted_constants
, before_size
,
2403 return start_offset
;
2407 fs_generator::get_assembly(unsigned int *assembly_size
)
2409 return brw_get_program(p
, assembly_size
);