2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "glsl/ir_optimization.h"
26 #include "glsl/nir/glsl_to_nir.h"
27 #include "main/shaderimage.h"
28 #include "program/prog_to_nir.h"
30 #include "brw_fs_surface_builder.h"
31 #include "brw_vec4_gs_visitor.h"
35 using namespace brw::surface_access
;
38 fs_visitor::emit_nir_code()
40 /* emit the arrays used for inputs and outputs - load/store intrinsics will
41 * be converted to reads/writes of these arrays
46 nir_emit_system_values();
48 /* get the main function and emit it */
49 nir_foreach_overload(nir
, overload
) {
50 assert(strcmp(overload
->function
->name
, "main") == 0);
51 assert(overload
->impl
);
52 nir_emit_impl(overload
->impl
);
57 fs_visitor::nir_setup_inputs()
59 if (stage
!= MESA_SHADER_FRAGMENT
)
62 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
64 nir_foreach_variable(var
, &nir
->inputs
) {
65 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
68 if (var
->data
.location
== VARYING_SLOT_POS
) {
69 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
70 var
->data
.origin_upper_left
);
71 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
73 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
74 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
75 reg
.type
= BRW_REGISTER_TYPE_D
;
76 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
77 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
78 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
79 reg
.type
= BRW_REGISTER_TYPE_D
;
80 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
82 emit_general_interpolation(input
, var
->name
, var
->type
,
83 (glsl_interp_qualifier
) var
->data
.interpolation
,
84 var
->data
.location
, var
->data
.centroid
,
91 fs_visitor::nir_setup_outputs()
93 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
95 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
97 nir_foreach_variable(var
, &nir
->outputs
) {
98 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
100 int vector_elements
= var
->type
->without_array()->vector_elements
;
103 case MESA_SHADER_VERTEX
:
104 case MESA_SHADER_GEOMETRY
:
105 for (int i
= 0; i
< type_size_vec4(var
->type
); i
++) {
106 int output
= var
->data
.location
+ i
;
107 this->outputs
[output
] = offset(reg
, bld
, 4 * i
);
108 this->output_components
[output
] = vector_elements
;
111 case MESA_SHADER_FRAGMENT
:
112 if (var
->data
.index
> 0) {
113 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
114 assert(var
->data
.index
== 1);
115 this->dual_src_output
= reg
;
116 this->do_dual_src
= true;
117 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
118 /* Writing gl_FragColor outputs to all color regions. */
119 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
120 this->outputs
[i
] = reg
;
121 this->output_components
[i
] = 4;
123 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
124 this->frag_depth
= reg
;
125 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
126 this->frag_stencil
= reg
;
127 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
128 this->sample_mask
= reg
;
130 /* gl_FragData or a user-defined FS output */
131 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
132 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
134 /* General color output. */
135 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
136 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
137 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
138 this->output_components
[output
] = vector_elements
;
143 unreachable("unhandled shader stage");
149 fs_visitor::nir_setup_uniforms()
151 if (dispatch_width
!= 8)
154 uniforms
= nir
->num_uniforms
;
156 nir_foreach_variable(var
, &nir
->uniforms
) {
157 /* UBO's and atomics don't take up space in the uniform file */
158 if (var
->interface_type
!= NULL
|| var
->type
->contains_atomic())
161 if (type_size_scalar(var
->type
) > 0)
162 param_size
[var
->data
.driver_location
] = type_size_scalar(var
->type
);
167 emit_system_values_block(nir_block
*block
, void *void_visitor
)
169 fs_visitor
*v
= (fs_visitor
*)void_visitor
;
172 nir_foreach_instr(block
, instr
) {
173 if (instr
->type
!= nir_instr_type_intrinsic
)
176 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
177 switch (intrin
->intrinsic
) {
178 case nir_intrinsic_load_vertex_id
:
179 unreachable("should be lowered by lower_vertex_id().");
181 case nir_intrinsic_load_vertex_id_zero_base
:
182 assert(v
->stage
== MESA_SHADER_VERTEX
);
183 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
184 if (reg
->file
== BAD_FILE
)
185 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
188 case nir_intrinsic_load_base_vertex
:
189 assert(v
->stage
== MESA_SHADER_VERTEX
);
190 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
191 if (reg
->file
== BAD_FILE
)
192 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
195 case nir_intrinsic_load_instance_id
:
196 assert(v
->stage
== MESA_SHADER_VERTEX
);
197 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
198 if (reg
->file
== BAD_FILE
)
199 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
202 case nir_intrinsic_load_invocation_id
:
203 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
204 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
205 if (reg
->file
== BAD_FILE
) {
206 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
207 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
208 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
209 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
214 case nir_intrinsic_load_sample_pos
:
215 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
216 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
217 if (reg
->file
== BAD_FILE
)
218 *reg
= *v
->emit_samplepos_setup();
221 case nir_intrinsic_load_sample_id
:
222 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
223 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
224 if (reg
->file
== BAD_FILE
)
225 *reg
= *v
->emit_sampleid_setup();
228 case nir_intrinsic_load_sample_mask_in
:
229 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
230 assert(v
->devinfo
->gen
>= 7);
231 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
232 if (reg
->file
== BAD_FILE
)
233 *reg
= fs_reg(retype(brw_vec8_grf(v
->payload
.sample_mask_in_reg
, 0),
234 BRW_REGISTER_TYPE_D
));
237 case nir_intrinsic_load_local_invocation_id
:
238 assert(v
->stage
== MESA_SHADER_COMPUTE
);
239 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
240 if (reg
->file
== BAD_FILE
)
241 *reg
= *v
->emit_cs_local_invocation_id_setup();
244 case nir_intrinsic_load_work_group_id
:
245 assert(v
->stage
== MESA_SHADER_COMPUTE
);
246 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
247 if (reg
->file
== BAD_FILE
)
248 *reg
= *v
->emit_cs_work_group_id_setup();
251 case nir_intrinsic_load_helper_invocation
:
252 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
253 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
254 if (reg
->file
== BAD_FILE
) {
255 const fs_builder abld
=
256 v
->bld
.annotate("gl_HelperInvocation", NULL
);
258 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
259 * pixel mask is in g1.7 of the thread payload.
261 * We move the per-channel pixel enable bit to the low bit of each
262 * channel by shifting the byte containing the pixel mask by the
263 * vector immediate 0x76543210UV.
265 * The region of <1,8,0> reads only 1 byte (the pixel masks for
266 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
267 * masks for 2 and 3) in SIMD16.
269 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
271 stride(byte_offset(retype(brw_vec1_grf(1, 0),
272 BRW_REGISTER_TYPE_UB
), 28),
274 brw_imm_uv(0x76543210));
276 /* A set bit in the pixel mask means the channel is enabled, but
277 * that is the opposite of gl_HelperInvocation so we need to invert
280 * The negate source-modifier bit of logical instructions on Gen8+
281 * performs 1's complement negation, so we can use that instead of
284 fs_reg inverted
= negate(shifted
);
285 if (v
->devinfo
->gen
< 8) {
286 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
287 abld
.NOT(inverted
, shifted
);
290 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
291 * with 1 and negating.
293 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
294 abld
.AND(anded
, inverted
, brw_imm_uw(1));
296 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
297 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
311 fs_visitor::nir_emit_system_values()
313 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
314 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
315 nir_system_values
[i
] = fs_reg();
318 nir_foreach_overload(nir
, overload
) {
319 assert(strcmp(overload
->function
->name
, "main") == 0);
320 assert(overload
->impl
);
321 nir_foreach_block(overload
->impl
, emit_system_values_block
, this);
326 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
328 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
329 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
330 nir_locals
[i
] = fs_reg();
333 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
334 unsigned array_elems
=
335 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
336 unsigned size
= array_elems
* reg
->num_components
;
337 nir_locals
[reg
->index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
340 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
343 nir_emit_cf_list(&impl
->body
);
347 fs_visitor::nir_emit_cf_list(exec_list
*list
)
349 exec_list_validate(list
);
350 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
351 switch (node
->type
) {
353 nir_emit_if(nir_cf_node_as_if(node
));
356 case nir_cf_node_loop
:
357 nir_emit_loop(nir_cf_node_as_loop(node
));
360 case nir_cf_node_block
:
361 nir_emit_block(nir_cf_node_as_block(node
));
365 unreachable("Invalid CFG node block");
371 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
373 /* first, put the condition into f0 */
374 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
375 retype(get_nir_src(if_stmt
->condition
),
376 BRW_REGISTER_TYPE_D
));
377 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
379 bld
.IF(BRW_PREDICATE_NORMAL
);
381 nir_emit_cf_list(&if_stmt
->then_list
);
383 /* note: if the else is empty, dead CF elimination will remove it */
384 bld
.emit(BRW_OPCODE_ELSE
);
386 nir_emit_cf_list(&if_stmt
->else_list
);
388 bld
.emit(BRW_OPCODE_ENDIF
);
392 fs_visitor::nir_emit_loop(nir_loop
*loop
)
394 bld
.emit(BRW_OPCODE_DO
);
396 nir_emit_cf_list(&loop
->body
);
398 bld
.emit(BRW_OPCODE_WHILE
);
402 fs_visitor::nir_emit_block(nir_block
*block
)
404 nir_foreach_instr(block
, instr
) {
405 nir_emit_instr(instr
);
410 fs_visitor::nir_emit_instr(nir_instr
*instr
)
412 const fs_builder abld
= bld
.annotate(NULL
, instr
);
414 switch (instr
->type
) {
415 case nir_instr_type_alu
:
416 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
419 case nir_instr_type_intrinsic
:
421 case MESA_SHADER_VERTEX
:
422 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
424 case MESA_SHADER_GEOMETRY
:
425 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
427 case MESA_SHADER_FRAGMENT
:
428 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
430 case MESA_SHADER_COMPUTE
:
431 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
434 unreachable("unsupported shader stage");
438 case nir_instr_type_tex
:
439 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
442 case nir_instr_type_load_const
:
443 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
446 case nir_instr_type_ssa_undef
:
447 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
450 case nir_instr_type_jump
:
451 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
455 unreachable("unknown instruction type");
460 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
461 const fs_reg
&result
)
463 if (!instr
->src
[0].src
.is_ssa
||
464 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
467 nir_intrinsic_instr
*src0
=
468 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
470 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
473 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
474 if (!value1
|| fabsf(value1
->f
[0]) != 1.0f
)
477 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
478 if (!value2
|| fabsf(value2
->f
[0]) != 1.0f
)
481 fs_reg tmp
= vgrf(glsl_type::int_type
);
483 if (devinfo
->gen
>= 6) {
484 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
485 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
487 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
489 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
490 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
492 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
494 * This negation looks like it's safe in practice, because bits 0:4 will
495 * surely be TRIANGLES
498 if (value1
->f
[0] == -1.0f
) {
502 tmp
.type
= BRW_REGISTER_TYPE_W
;
503 tmp
.subreg_offset
= 2;
506 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
508 tmp
.type
= BRW_REGISTER_TYPE_D
;
509 tmp
.subreg_offset
= 0;
512 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
513 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
515 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
517 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
518 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
520 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
522 * This negation looks like it's safe in practice, because bits 0:4 will
523 * surely be TRIANGLES
526 if (value1
->f
[0] == -1.0f
) {
530 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
532 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
538 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
540 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
543 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
544 result
.type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].output_type
);
547 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
548 op
[i
] = get_nir_src(instr
->src
[i
].src
);
549 op
[i
].type
= brw_type_for_nir_type(nir_op_infos
[instr
->op
].input_types
[i
]);
550 op
[i
].abs
= instr
->src
[i
].abs
;
551 op
[i
].negate
= instr
->src
[i
].negate
;
554 /* We get a bunch of mov's out of the from_ssa pass and they may still
555 * be vectorized. We'll handle them as a special-case. We'll also
556 * handle vecN here because it's basically the same thing.
564 fs_reg temp
= result
;
565 bool need_extra_copy
= false;
566 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
567 if (!instr
->src
[i
].src
.is_ssa
&&
568 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
569 need_extra_copy
= true;
570 temp
= bld
.vgrf(result
.type
, 4);
575 for (unsigned i
= 0; i
< 4; i
++) {
576 if (!(instr
->dest
.write_mask
& (1 << i
)))
579 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
580 inst
= bld
.MOV(offset(temp
, bld
, i
),
581 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
583 inst
= bld
.MOV(offset(temp
, bld
, i
),
584 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
586 inst
->saturate
= instr
->dest
.saturate
;
589 /* In this case the source and destination registers were the same,
590 * so we need to insert an extra set of moves in order to deal with
593 if (need_extra_copy
) {
594 for (unsigned i
= 0; i
< 4; i
++) {
595 if (!(instr
->dest
.write_mask
& (1 << i
)))
598 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
607 /* At this point, we have dealt with any instruction that operates on
608 * more than a single channel. Therefore, we can just adjust the source
609 * and destination registers for that channel and emit the instruction.
611 unsigned channel
= 0;
612 if (nir_op_infos
[instr
->op
].output_size
== 0) {
613 /* Since NIR is doing the scalarizing for us, we should only ever see
614 * vectorized operations with a single channel.
616 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
617 channel
= ffs(instr
->dest
.write_mask
) - 1;
619 result
= offset(result
, bld
, channel
);
622 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
623 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
624 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
630 inst
= bld
.MOV(result
, op
[0]);
631 inst
->saturate
= instr
->dest
.saturate
;
636 bld
.MOV(result
, op
[0]);
640 /* AND(val, 0x80000000) gives the sign bit.
642 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
645 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
647 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
648 op
[0].type
= BRW_REGISTER_TYPE_UD
;
649 result
.type
= BRW_REGISTER_TYPE_UD
;
650 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
652 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
653 inst
->predicate
= BRW_PREDICATE_NORMAL
;
654 if (instr
->dest
.saturate
) {
655 inst
= bld
.MOV(result
, result
);
656 inst
->saturate
= true;
662 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
663 * -> non-negative val generates 0x00000000.
664 * Predicated OR sets 1 if val is positive.
666 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
667 bld
.ASR(result
, op
[0], brw_imm_d(31));
668 inst
= bld
.OR(result
, result
, brw_imm_d(1));
669 inst
->predicate
= BRW_PREDICATE_NORMAL
;
673 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
674 inst
->saturate
= instr
->dest
.saturate
;
678 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
679 inst
->saturate
= instr
->dest
.saturate
;
683 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
684 inst
->saturate
= instr
->dest
.saturate
;
688 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
689 inst
->saturate
= instr
->dest
.saturate
;
693 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
694 inst
->saturate
= instr
->dest
.saturate
;
698 if (fs_key
->high_quality_derivatives
) {
699 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
701 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
703 inst
->saturate
= instr
->dest
.saturate
;
705 case nir_op_fddx_fine
:
706 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
707 inst
->saturate
= instr
->dest
.saturate
;
709 case nir_op_fddx_coarse
:
710 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
711 inst
->saturate
= instr
->dest
.saturate
;
714 if (fs_key
->high_quality_derivatives
) {
715 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
716 brw_imm_d(fs_key
->render_to_fbo
));
718 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
719 brw_imm_d(fs_key
->render_to_fbo
));
721 inst
->saturate
= instr
->dest
.saturate
;
723 case nir_op_fddy_fine
:
724 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
725 brw_imm_d(fs_key
->render_to_fbo
));
726 inst
->saturate
= instr
->dest
.saturate
;
728 case nir_op_fddy_coarse
:
729 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
730 brw_imm_d(fs_key
->render_to_fbo
));
731 inst
->saturate
= instr
->dest
.saturate
;
736 inst
= bld
.ADD(result
, op
[0], op
[1]);
737 inst
->saturate
= instr
->dest
.saturate
;
741 inst
= bld
.MUL(result
, op
[0], op
[1]);
742 inst
->saturate
= instr
->dest
.saturate
;
746 bld
.MUL(result
, op
[0], op
[1]);
749 case nir_op_imul_high
:
750 case nir_op_umul_high
:
751 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
756 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
759 case nir_op_uadd_carry
:
760 unreachable("Should have been lowered by carry_to_arith().");
762 case nir_op_usub_borrow
:
763 unreachable("Should have been lowered by borrow_to_arith().");
766 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
772 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
778 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
783 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
788 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
792 if (devinfo
->gen
>= 8) {
793 op
[0] = resolve_source_modifiers(op
[0]);
795 bld
.NOT(result
, op
[0]);
798 if (devinfo
->gen
>= 8) {
799 op
[0] = resolve_source_modifiers(op
[0]);
800 op
[1] = resolve_source_modifiers(op
[1]);
802 bld
.XOR(result
, op
[0], op
[1]);
805 if (devinfo
->gen
>= 8) {
806 op
[0] = resolve_source_modifiers(op
[0]);
807 op
[1] = resolve_source_modifiers(op
[1]);
809 bld
.OR(result
, op
[0], op
[1]);
812 if (devinfo
->gen
>= 8) {
813 op
[0] = resolve_source_modifiers(op
[0]);
814 op
[1] = resolve_source_modifiers(op
[1]);
816 bld
.AND(result
, op
[0], op
[1]);
828 case nir_op_ball_fequal2
:
829 case nir_op_ball_iequal2
:
830 case nir_op_ball_fequal3
:
831 case nir_op_ball_iequal3
:
832 case nir_op_ball_fequal4
:
833 case nir_op_ball_iequal4
:
834 case nir_op_bany_fnequal2
:
835 case nir_op_bany_inequal2
:
836 case nir_op_bany_fnequal3
:
837 case nir_op_bany_inequal3
:
838 case nir_op_bany_fnequal4
:
839 case nir_op_bany_inequal4
:
840 unreachable("Lowered by nir_lower_alu_reductions");
842 case nir_op_fnoise1_1
:
843 case nir_op_fnoise1_2
:
844 case nir_op_fnoise1_3
:
845 case nir_op_fnoise1_4
:
846 case nir_op_fnoise2_1
:
847 case nir_op_fnoise2_2
:
848 case nir_op_fnoise2_3
:
849 case nir_op_fnoise2_4
:
850 case nir_op_fnoise3_1
:
851 case nir_op_fnoise3_2
:
852 case nir_op_fnoise3_3
:
853 case nir_op_fnoise3_4
:
854 case nir_op_fnoise4_1
:
855 case nir_op_fnoise4_2
:
856 case nir_op_fnoise4_3
:
857 case nir_op_fnoise4_4
:
858 unreachable("not reached: should be handled by lower_noise");
861 unreachable("not reached: should be handled by ldexp_to_arith()");
864 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
865 inst
->saturate
= instr
->dest
.saturate
;
869 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
875 bld
.MOV(result
, negate(op
[0]));
879 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
882 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
886 inst
= bld
.RNDZ(result
, op
[0]);
887 inst
->saturate
= instr
->dest
.saturate
;
891 op
[0].negate
= !op
[0].negate
;
892 fs_reg temp
= vgrf(glsl_type::float_type
);
893 bld
.RNDD(temp
, op
[0]);
895 inst
= bld
.MOV(result
, temp
);
896 inst
->saturate
= instr
->dest
.saturate
;
900 inst
= bld
.RNDD(result
, op
[0]);
901 inst
->saturate
= instr
->dest
.saturate
;
904 inst
= bld
.FRC(result
, op
[0]);
905 inst
->saturate
= instr
->dest
.saturate
;
907 case nir_op_fround_even
:
908 inst
= bld
.RNDE(result
, op
[0]);
909 inst
->saturate
= instr
->dest
.saturate
;
915 if (devinfo
->gen
>= 6) {
916 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
917 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
919 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_L
);
920 inst
= bld
.SEL(result
, op
[0], op
[1]);
921 inst
->predicate
= BRW_PREDICATE_NORMAL
;
923 inst
->saturate
= instr
->dest
.saturate
;
929 if (devinfo
->gen
>= 6) {
930 inst
= bld
.emit(BRW_OPCODE_SEL
, result
, op
[0], op
[1]);
931 inst
->conditional_mod
= BRW_CONDITIONAL_GE
;
933 bld
.CMP(bld
.null_reg_d(), op
[0], op
[1], BRW_CONDITIONAL_GE
);
934 inst
= bld
.SEL(result
, op
[0], op
[1]);
935 inst
->predicate
= BRW_PREDICATE_NORMAL
;
937 inst
->saturate
= instr
->dest
.saturate
;
940 case nir_op_pack_snorm_2x16
:
941 case nir_op_pack_snorm_4x8
:
942 case nir_op_pack_unorm_2x16
:
943 case nir_op_pack_unorm_4x8
:
944 case nir_op_unpack_snorm_2x16
:
945 case nir_op_unpack_snorm_4x8
:
946 case nir_op_unpack_unorm_2x16
:
947 case nir_op_unpack_unorm_4x8
:
948 case nir_op_unpack_half_2x16
:
949 case nir_op_pack_half_2x16
:
950 unreachable("not reached: should be handled by lower_packing_builtins");
952 case nir_op_unpack_half_2x16_split_x
:
953 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
954 inst
->saturate
= instr
->dest
.saturate
;
956 case nir_op_unpack_half_2x16_split_y
:
957 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
958 inst
->saturate
= instr
->dest
.saturate
;
962 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
963 inst
->saturate
= instr
->dest
.saturate
;
966 case nir_op_bitfield_reverse
:
967 bld
.BFREV(result
, op
[0]);
970 case nir_op_bit_count
:
971 bld
.CBIT(result
, op
[0]);
974 case nir_op_ufind_msb
:
975 case nir_op_ifind_msb
: {
976 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
978 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
979 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
980 * subtract the result from 31 to convert the MSB count into an LSB count.
982 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
984 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
985 inst
->predicate
= BRW_PREDICATE_NORMAL
;
986 inst
->src
[0].negate
= true;
990 case nir_op_find_lsb
:
991 bld
.FBL(result
, op
[0]);
994 case nir_op_ubitfield_extract
:
995 case nir_op_ibitfield_extract
:
996 bld
.BFE(result
, op
[2], op
[1], op
[0]);
999 bld
.BFI1(result
, op
[0], op
[1]);
1002 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1005 case nir_op_bitfield_insert
:
1006 unreachable("not reached: should be handled by "
1007 "lower_instructions::bitfield_insert_to_bfm_bfi");
1010 bld
.SHL(result
, op
[0], op
[1]);
1013 bld
.ASR(result
, op
[0], op
[1]);
1016 bld
.SHR(result
, op
[0], op
[1]);
1019 case nir_op_pack_half_2x16_split
:
1020 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1024 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1025 inst
->saturate
= instr
->dest
.saturate
;
1029 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1030 inst
->saturate
= instr
->dest
.saturate
;
1034 if (optimize_frontfacing_ternary(instr
, result
))
1037 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1038 inst
= bld
.SEL(result
, op
[1], op
[2]);
1039 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1043 unreachable("unhandled instruction");
1046 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1047 * to sign extend the low bit to 0/~0
1049 if (devinfo
->gen
<= 5 &&
1050 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1051 fs_reg masked
= vgrf(glsl_type::int_type
);
1052 bld
.AND(masked
, result
, brw_imm_d(1));
1053 masked
.negate
= true;
1054 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1059 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1060 nir_load_const_instr
*instr
)
1062 fs_reg reg
= bld
.vgrf(BRW_REGISTER_TYPE_D
, instr
->def
.num_components
);
1064 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1065 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i
[i
]));
1067 nir_ssa_values
[instr
->def
.index
] = reg
;
1071 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1073 nir_ssa_values
[instr
->def
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_D
,
1074 instr
->def
.num_components
);
1078 fs_reg_for_nir_reg(fs_visitor
*v
, nir_register
*nir_reg
,
1079 unsigned base_offset
, nir_src
*indirect
)
1083 assert(!nir_reg
->is_global
);
1085 reg
= v
->nir_locals
[nir_reg
->index
];
1087 reg
= offset(reg
, v
->bld
, base_offset
* nir_reg
->num_components
);
1089 int multiplier
= nir_reg
->num_components
* (v
->dispatch_width
/ 8);
1091 reg
.reladdr
= new(v
->mem_ctx
) fs_reg(v
->vgrf(glsl_type::int_type
));
1092 v
->bld
.MUL(*reg
.reladdr
, v
->get_nir_src(*indirect
),
1093 brw_imm_d(multiplier
));
1100 fs_visitor::get_nir_src(nir_src src
)
1104 reg
= nir_ssa_values
[src
.ssa
->index
];
1106 reg
= fs_reg_for_nir_reg(this, src
.reg
.reg
, src
.reg
.base_offset
,
1110 /* to avoid floating-point denorm flushing problems, set the type by
1111 * default to D - instructions that need floating point semantics will set
1112 * this to F if they need to
1114 return retype(reg
, BRW_REGISTER_TYPE_D
);
1118 fs_visitor::get_nir_dest(nir_dest dest
)
1121 nir_ssa_values
[dest
.ssa
.index
] = bld
.vgrf(BRW_REGISTER_TYPE_F
,
1122 dest
.ssa
.num_components
);
1123 return nir_ssa_values
[dest
.ssa
.index
];
1126 return fs_reg_for_nir_reg(this, dest
.reg
.reg
, dest
.reg
.base_offset
,
1131 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1133 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
,
1134 BRW_REGISTER_TYPE_UD
);
1136 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1137 tail
= tail
->child
) {
1138 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1139 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1140 const unsigned size
= glsl_get_length(tail
->type
);
1141 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1142 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1143 image
= offset(image
, bld
, base
* element_size
);
1145 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1146 fs_reg tmp
= vgrf(glsl_type::int_type
);
1148 if (devinfo
->gen
== 7 && !devinfo
->is_haswell
) {
1149 /* IVB hangs when trying to access an invalid surface index with
1150 * the dataport. According to the spec "if the index used to
1151 * select an individual element is negative or greater than or
1152 * equal to the size of the array, the results of the operation
1153 * are undefined but may not lead to termination" -- which is one
1154 * of the possible outcomes of the hang. Clamp the index to
1155 * prevent access outside of the array bounds.
1157 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1158 BRW_REGISTER_TYPE_UD
),
1159 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1161 bld
.MOV(tmp
, get_nir_src(deref_array
->indirect
));
1164 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
));
1166 bld
.ADD(*image
.reladdr
, *image
.reladdr
, tmp
);
1168 image
.reladdr
= new(mem_ctx
) fs_reg(tmp
);
1176 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1179 for (unsigned i
= 0; i
< 4; i
++) {
1180 if (!((wr_mask
>> i
) & 1))
1183 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1184 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1185 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1186 if (new_inst
->src
[j
].file
== VGRF
)
1187 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1194 * Get the matching channel register datatype for an image intrinsic of the
1195 * specified GLSL image type.
1198 get_image_base_type(const glsl_type
*type
)
1200 switch ((glsl_base_type
)type
->sampler_type
) {
1201 case GLSL_TYPE_UINT
:
1202 return BRW_REGISTER_TYPE_UD
;
1204 return BRW_REGISTER_TYPE_D
;
1205 case GLSL_TYPE_FLOAT
:
1206 return BRW_REGISTER_TYPE_F
;
1208 unreachable("Not reached.");
1213 * Get the appropriate atomic op for an image atomic intrinsic.
1216 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1219 case nir_intrinsic_image_atomic_add
:
1221 case nir_intrinsic_image_atomic_min
:
1222 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1223 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1224 case nir_intrinsic_image_atomic_max
:
1225 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1226 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1227 case nir_intrinsic_image_atomic_and
:
1229 case nir_intrinsic_image_atomic_or
:
1231 case nir_intrinsic_image_atomic_xor
:
1233 case nir_intrinsic_image_atomic_exchange
:
1235 case nir_intrinsic_image_atomic_comp_swap
:
1236 return BRW_AOP_CMPWR
;
1238 unreachable("Not reachable.");
1243 emit_pixel_interpolater_send(const fs_builder
&bld
,
1248 glsl_interp_qualifier interpolation
)
1254 if (src
.file
== BAD_FILE
) {
1256 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1260 mlen
= 2 * bld
.dispatch_width() / 8;
1263 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1265 /* 2 floats per slot returned */
1266 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1267 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1273 * Computes 1 << x, given a D/UD register containing some value x.
1276 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1278 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1280 fs_reg result
= bld
.vgrf(x
.type
, 1);
1281 fs_reg one
= bld
.vgrf(x
.type
, 1);
1283 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1284 bld
.SHL(result
, one
, x
);
1289 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1291 assert(stage
== MESA_SHADER_GEOMETRY
);
1293 struct brw_gs_prog_data
*gs_prog_data
=
1294 (struct brw_gs_prog_data
*) prog_data
;
1296 /* We can only do EndPrimitive() functionality when the control data
1297 * consists of cut bits. Fortunately, the only time it isn't is when the
1298 * output type is points, in which case EndPrimitive() is a no-op.
1300 if (gs_prog_data
->control_data_format
!=
1301 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1305 /* Cut bits use one bit per vertex. */
1306 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1308 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1309 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1311 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1312 * vertex n, 0 otherwise. So all we need to do here is mark bit
1313 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1314 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1315 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1317 * Note that if EndPrimitive() is called before emitting any vertices, this
1318 * will cause us to set bit 31 of the control_data_bits register to 1.
1319 * That's fine because:
1321 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1322 * output, so the hardware will ignore cut bit 31.
1324 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1325 * last vertex, so setting cut bit 31 has no effect (since the primitive
1326 * is automatically ended when the GS terminates).
1328 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1329 * control_data_bits register to 0 when the first vertex is emitted.
1332 const fs_builder abld
= bld
.annotate("end primitive");
1334 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1335 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1336 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1337 fs_reg mask
= intexp2(abld
, prev_count
);
1338 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1339 * attention to the lower 5 bits of its second source argument, so on this
1340 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1341 * ((vertex_count - 1) % 32).
1343 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1347 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1349 assert(stage
== MESA_SHADER_GEOMETRY
);
1350 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1352 struct brw_gs_prog_data
*gs_prog_data
=
1353 (struct brw_gs_prog_data
*) prog_data
;
1355 const fs_builder abld
= bld
.annotate("emit control data bits");
1356 const fs_builder fwa_bld
= bld
.exec_all();
1358 /* We use a single UD register to accumulate control data bits (32 bits
1359 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1362 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1363 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1364 * use the Channel Mask phase to enable/disable which DWord within that
1365 * group to write. (Remember, different SIMD8 channels may have emitted
1366 * different numbers of vertices, so we may need per-slot offsets.)
1368 * Channel masking presents an annoying problem: we may have to replicate
1369 * the data up to 4 times:
1371 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1373 * To avoid penalizing shaders that emit a small number of vertices, we
1374 * can avoid these sometimes: if the size of the control data header is
1375 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1376 * land in the same 128-bit group, so we can skip per-slot offsets.
1378 * Similarly, if the control data header is <= 32 bits, there is only one
1379 * DWord, so we can skip channel masks.
1381 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1383 fs_reg channel_mask
, per_slot_offset
;
1385 if (gs_compile
->control_data_header_size_bits
> 32) {
1386 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1387 channel_mask
= vgrf(glsl_type::uint_type
);
1390 if (gs_compile
->control_data_header_size_bits
> 128) {
1391 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1392 per_slot_offset
= vgrf(glsl_type::uint_type
);
1395 /* Figure out which DWord we're trying to write to using the formula:
1397 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1399 * Since bits_per_vertex is a power of two, and is known at compile
1400 * time, this can be optimized to:
1402 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1404 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1405 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1406 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1407 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1408 unsigned log2_bits_per_vertex
=
1409 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1410 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1412 if (per_slot_offset
.file
!= BAD_FILE
) {
1413 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1414 * the appropriate OWord within the control data header.
1416 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1419 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1420 * write to the appropriate DWORD within the OWORD.
1422 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1423 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1424 channel_mask
= intexp2(fwa_bld
, channel
);
1425 /* Then the channel masks need to be in bits 23:16. */
1426 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1429 /* Store the control data bits in the message payload and send it. */
1431 if (channel_mask
.file
!= BAD_FILE
)
1432 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1433 if (per_slot_offset
.file
!= BAD_FILE
)
1436 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1437 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1439 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1440 if (per_slot_offset
.file
!= BAD_FILE
)
1441 sources
[i
++] = per_slot_offset
;
1442 if (channel_mask
.file
!= BAD_FILE
)
1443 sources
[i
++] = channel_mask
;
1445 sources
[i
++] = this->control_data_bits
;
1448 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1449 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1451 /* We need to increment Global Offset by 256-bits to make room for
1452 * Broadwell's extra "Vertex Count" payload at the beginning of the
1453 * URB entry. Since this is an OWord message, Global Offset is counted
1454 * in 128-bit units, so we must set it to 2.
1456 if (gs_prog_data
->static_vertex_count
== -1)
1461 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1464 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1466 /* Note: we are calling this *before* increasing vertex_count, so
1467 * this->vertex_count == vertex_count - 1 in the formula above.
1470 /* Stream mode uses 2 bits per vertex */
1471 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1473 /* Must be a valid stream */
1474 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1476 /* Control data bits are initialized to 0 so we don't have to set any
1477 * bits when sending vertices to stream 0.
1482 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1484 /* reg::sid = stream_id */
1485 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1486 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1488 /* reg:shift_count = 2 * (vertex_count - 1) */
1489 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1490 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1492 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1493 * attention to the lower 5 bits of its second source argument, so on this
1494 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1495 * stream_id << ((2 * (vertex_count - 1)) % 32).
1497 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1498 abld
.SHL(mask
, sid
, shift_count
);
1499 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1503 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1506 assert(stage
== MESA_SHADER_GEOMETRY
);
1508 struct brw_gs_prog_data
*gs_prog_data
=
1509 (struct brw_gs_prog_data
*) prog_data
;
1511 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1512 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1514 /* Haswell and later hardware ignores the "Render Stream Select" bits
1515 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1516 * and instead sends all primitives down the pipeline for rasterization.
1517 * If the SOL stage is enabled, "Render Stream Select" is honored and
1518 * primitives bound to non-zero streams are discarded after stream output.
1520 * Since the only purpose of primives sent to non-zero streams is to
1521 * be recorded by transform feedback, we can simply discard all geometry
1522 * bound to these streams when transform feedback is disabled.
1524 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1527 /* If we're outputting 32 control data bits or less, then we can wait
1528 * until the shader is over to output them all. Otherwise we need to
1529 * output them as we go. Now is the time to do it, since we're about to
1530 * output the vertex_count'th vertex, so it's guaranteed that the
1531 * control data bits associated with the (vertex_count - 1)th vertex are
1534 if (gs_compile
->control_data_header_size_bits
> 32) {
1535 const fs_builder abld
=
1536 bld
.annotate("emit vertex: emit control data bits");
1538 /* Only emit control data bits if we've finished accumulating a batch
1539 * of 32 bits. This is the case when:
1541 * (vertex_count * bits_per_vertex) % 32 == 0
1543 * (in other words, when the last 5 bits of vertex_count *
1544 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1545 * integer n (which is always the case, since bits_per_vertex is
1546 * always 1 or 2), this is equivalent to requiring that the last 5-n
1547 * bits of vertex_count are 0:
1549 * vertex_count & (2^(5-n) - 1) == 0
1551 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1554 * vertex_count & (32 / bits_per_vertex - 1) == 0
1556 * TODO: If vertex_count is an immediate, we could do some of this math
1557 * at compile time...
1560 abld
.AND(bld
.null_reg_d(), vertex_count
,
1561 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1562 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1564 abld
.IF(BRW_PREDICATE_NORMAL
);
1565 /* If vertex_count is 0, then no control data bits have been
1566 * accumulated yet, so we can skip emitting them.
1568 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1569 BRW_CONDITIONAL_NEQ
);
1570 abld
.IF(BRW_PREDICATE_NORMAL
);
1571 emit_gs_control_data_bits(vertex_count
);
1572 abld
.emit(BRW_OPCODE_ENDIF
);
1574 /* Reset control_data_bits to 0 so we can start accumulating a new
1577 * Note: in the case where vertex_count == 0, this neutralizes the
1578 * effect of any call to EndPrimitive() that the shader may have
1579 * made before outputting its first vertex.
1581 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1582 inst
->force_writemask_all
= true;
1583 abld
.emit(BRW_OPCODE_ENDIF
);
1586 emit_urb_writes(vertex_count
);
1588 /* In stream mode we have to set control data bits for all vertices
1589 * unless we have disabled control data bits completely (which we do
1590 * do for GL_POINTS outputs that don't use streams).
1592 if (gs_compile
->control_data_header_size_bits
> 0 &&
1593 gs_prog_data
->control_data_format
==
1594 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1595 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1600 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1601 const nir_src
&vertex_src
,
1602 const fs_reg
&indirect_offset
,
1603 unsigned imm_offset
,
1604 unsigned num_components
)
1606 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1608 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1609 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1610 * gl_PointSize is available as a GS input, however, so it must be that.
1612 const bool is_point_size
=
1613 indirect_offset
.file
== BAD_FILE
&& imm_offset
== 0;
1615 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1616 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1618 if (indirect_offset
.file
== BAD_FILE
&& vertex_const
!= NULL
&&
1619 4 * imm_offset
< push_reg_count
) {
1620 imm_offset
= 4 * imm_offset
+ vertex_const
->u
[0] * push_reg_count
;
1621 /* This input was pushed into registers. */
1622 if (is_point_size
) {
1623 /* gl_PointSize comes in .w */
1624 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
1626 for (unsigned i
= 0; i
< num_components
; i
++) {
1627 bld
.MOV(offset(dst
, bld
, i
),
1628 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
1632 /* Resort to the pull model. Ensure the VUE handles are provided. */
1633 gs_prog_data
->base
.include_vue_handles
= true;
1635 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
1639 /* The vertex index is constant; just select the proper URB handle. */
1641 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i
[0], 0),
1642 BRW_REGISTER_TYPE_UD
);
1644 /* The vertex index is non-constant. We need to use indirect
1645 * addressing to fetch the proper URB handle.
1647 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
1648 * indicating that channel <n> should read the handle from
1649 * DWord <n>. We convert that to bytes by multiplying by 4.
1651 * Next, we convert the vertex index to bytes by multiplying
1652 * by 32 (shifting by 5), and add the two together. This is
1653 * the final indirect byte offset.
1655 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
1656 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1657 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1658 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1659 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1661 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
1662 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
1663 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
1664 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
1665 /* Convert vertex_index to bytes (multiply by 32) */
1666 bld
.SHL(vertex_offset_bytes
,
1667 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
1669 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
1671 /* Use first_icp_handle as the base offset. There is one register
1672 * of URB handles per vertex, so inform the register allocator that
1673 * we might read up to nir->info.gs.vertices_in registers.
1675 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
1676 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
1677 fs_reg(icp_offset_bytes
),
1678 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
1682 if (indirect_offset
.file
== BAD_FILE
) {
1683 /* Constant indexing - use global offset. */
1684 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
1685 inst
->offset
= imm_offset
;
1686 inst
->base_mrf
= -1;
1688 inst
->regs_written
= num_components
;
1690 /* Indirect indexing - use per-slot offsets as well. */
1691 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
1692 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
1693 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
1695 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
1696 inst
->offset
= imm_offset
;
1697 inst
->base_mrf
= -1;
1699 inst
->regs_written
= num_components
;
1702 if (is_point_size
) {
1703 /* Read the whole VUE header (because of alignment) and read .w. */
1704 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
1706 inst
->regs_written
= 4;
1707 bld
.MOV(dst
, offset(tmp
, bld
, 3));
1713 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
1714 nir_intrinsic_instr
*instr
)
1716 assert(stage
== MESA_SHADER_VERTEX
);
1719 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1720 dest
= get_nir_dest(instr
->dest
);
1722 switch (instr
->intrinsic
) {
1723 case nir_intrinsic_load_vertex_id
:
1724 unreachable("should be lowered by lower_vertex_id()");
1726 case nir_intrinsic_load_vertex_id_zero_base
:
1727 case nir_intrinsic_load_base_vertex
:
1728 case nir_intrinsic_load_instance_id
: {
1729 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1730 fs_reg val
= nir_system_values
[sv
];
1731 assert(val
.file
!= BAD_FILE
);
1732 dest
.type
= val
.type
;
1738 nir_emit_intrinsic(bld
, instr
);
1744 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
1745 nir_intrinsic_instr
*instr
)
1747 assert(stage
== MESA_SHADER_GEOMETRY
);
1748 fs_reg indirect_offset
;
1751 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1752 dest
= get_nir_dest(instr
->dest
);
1754 switch (instr
->intrinsic
) {
1755 case nir_intrinsic_load_primitive_id
:
1756 assert(stage
== MESA_SHADER_GEOMETRY
);
1757 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
1758 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
1759 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
1762 case nir_intrinsic_load_input_indirect
:
1763 case nir_intrinsic_load_input
:
1764 unreachable("load_input intrinsics are invalid for the GS stage");
1766 case nir_intrinsic_load_per_vertex_input_indirect
:
1767 indirect_offset
= retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_D
);
1769 case nir_intrinsic_load_per_vertex_input
:
1770 emit_gs_input_load(dest
, instr
->src
[0],
1771 indirect_offset
, instr
->const_index
[0],
1772 instr
->num_components
);
1775 case nir_intrinsic_emit_vertex_with_counter
:
1776 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
1779 case nir_intrinsic_end_primitive_with_counter
:
1780 emit_gs_end_primitive(instr
->src
[0]);
1783 case nir_intrinsic_set_vertex_count
:
1784 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
1787 case nir_intrinsic_load_invocation_id
: {
1788 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
1789 assert(val
.file
!= BAD_FILE
);
1790 dest
.type
= val
.type
;
1796 nir_emit_intrinsic(bld
, instr
);
1802 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
1803 nir_intrinsic_instr
*instr
)
1805 assert(stage
== MESA_SHADER_FRAGMENT
);
1806 struct brw_wm_prog_data
*wm_prog_data
=
1807 (struct brw_wm_prog_data
*) prog_data
;
1810 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
1811 dest
= get_nir_dest(instr
->dest
);
1813 switch (instr
->intrinsic
) {
1814 case nir_intrinsic_load_front_face
:
1815 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
1816 *emit_frontfacing_interpolation());
1819 case nir_intrinsic_load_sample_pos
: {
1820 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
1821 assert(sample_pos
.file
!= BAD_FILE
);
1822 dest
.type
= sample_pos
.type
;
1823 bld
.MOV(dest
, sample_pos
);
1824 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
1828 case nir_intrinsic_load_helper_invocation
:
1829 case nir_intrinsic_load_sample_mask_in
:
1830 case nir_intrinsic_load_sample_id
: {
1831 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
1832 fs_reg val
= nir_system_values
[sv
];
1833 assert(val
.file
!= BAD_FILE
);
1834 dest
.type
= val
.type
;
1839 case nir_intrinsic_discard
:
1840 case nir_intrinsic_discard_if
: {
1841 /* We track our discarded pixels in f0.1. By predicating on it, we can
1842 * update just the flag bits that aren't yet discarded. If there's no
1843 * condition, we emit a CMP of g0 != g0, so all currently executing
1844 * channels will get turned off.
1847 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
1848 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
1849 brw_imm_d(0), BRW_CONDITIONAL_Z
);
1851 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
1852 BRW_REGISTER_TYPE_UW
));
1853 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
1855 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
1856 cmp
->flag_subreg
= 1;
1858 if (devinfo
->gen
>= 6) {
1859 emit_discard_jump();
1864 case nir_intrinsic_interp_var_at_centroid
:
1865 case nir_intrinsic_interp_var_at_sample
:
1866 case nir_intrinsic_interp_var_at_offset
: {
1867 /* Handle ARB_gpu_shader5 interpolation intrinsics
1869 * It's worth a quick word of explanation as to why we handle the full
1870 * variable-based interpolation intrinsic rather than a lowered version
1871 * with like we do for other inputs. We have to do that because the way
1872 * we set up inputs doesn't allow us to use the already setup inputs for
1873 * interpolation. At the beginning of the shader, we go through all of
1874 * the input variables and do the initial interpolation and put it in
1875 * the nir_inputs array based on its location as determined in
1876 * nir_lower_io. If the input isn't used, dead code cleans up and
1877 * everything works fine. However, when we get to the ARB_gpu_shader5
1878 * interpolation intrinsics, we need to reinterpolate the input
1879 * differently. If we used an intrinsic that just had an index it would
1880 * only give us the offset into the nir_inputs array. However, this is
1881 * useless because that value is post-interpolation and we need
1882 * pre-interpolation. In order to get the actual location of the bits
1883 * we get from the vertex fetching hardware, we need the variable.
1885 wm_prog_data
->pulls_bary
= true;
1887 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
1888 const glsl_interp_qualifier interpolation
=
1889 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
1891 switch (instr
->intrinsic
) {
1892 case nir_intrinsic_interp_var_at_centroid
:
1893 emit_pixel_interpolater_send(bld
,
1894 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
1901 case nir_intrinsic_interp_var_at_sample
: {
1902 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
1905 unsigned msg_data
= const_sample
->i
[0] << 4;
1907 emit_pixel_interpolater_send(bld
,
1908 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1911 brw_imm_ud(msg_data
),
1914 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
1915 BRW_REGISTER_TYPE_UD
);
1917 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
1918 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1919 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1920 bld
.exec_all().group(1, 0)
1921 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1922 emit_pixel_interpolater_send(bld
,
1923 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1929 /* Make a loop that sends a message to the pixel interpolater
1930 * for the sample number in each live channel. If there are
1931 * multiple channels with the same sample number then these
1932 * will be handled simultaneously with a single interation of
1935 bld
.emit(BRW_OPCODE_DO
);
1937 /* Get the next live sample number into sample_id_reg */
1938 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
1940 /* Set the flag register so that we can perform the send
1941 * message on all channels that have the same sample number
1943 bld
.CMP(bld
.null_reg_ud(),
1944 sample_src
, sample_id
,
1945 BRW_CONDITIONAL_EQ
);
1946 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
1947 bld
.exec_all().group(1, 0)
1948 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
1950 emit_pixel_interpolater_send(bld
,
1951 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
1956 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
1958 /* Continue the loop if there are any live channels left */
1959 set_predicate_inv(BRW_PREDICATE_NORMAL
,
1961 bld
.emit(BRW_OPCODE_WHILE
));
1968 case nir_intrinsic_interp_var_at_offset
: {
1969 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1972 unsigned off_x
= MIN2((int)(const_offset
->f
[0] * 16), 7) & 0xf;
1973 unsigned off_y
= MIN2((int)(const_offset
->f
[1] * 16), 7) & 0xf;
1975 emit_pixel_interpolater_send(bld
,
1976 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
1979 brw_imm_ud(off_x
| (off_y
<< 4)),
1982 fs_reg src
= vgrf(glsl_type::ivec2_type
);
1983 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
1984 BRW_REGISTER_TYPE_F
);
1985 for (int i
= 0; i
< 2; i
++) {
1986 fs_reg temp
= vgrf(glsl_type::float_type
);
1987 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
1988 fs_reg itemp
= vgrf(glsl_type::int_type
);
1989 bld
.MOV(itemp
, temp
); /* float to int */
1991 /* Clamp the upper end of the range to +7/16.
1992 * ARB_gpu_shader5 requires that we support a maximum offset
1993 * of +0.5, which isn't representable in a S0.4 value -- if
1994 * we didn't clamp it, we'd end up with -8/16, which is the
1995 * opposite of what the shader author wanted.
1997 * This is legal due to ARB_gpu_shader5's quantization
2000 * "Not all values of <offset> may be supported; x and y
2001 * offsets may be rounded to fixed-point values with the
2002 * number of fraction bits given by the
2003 * implementation-dependent constant
2004 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
2006 set_condmod(BRW_CONDITIONAL_L
,
2007 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
2010 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
2011 emit_pixel_interpolater_send(bld
,
2022 unreachable("Invalid intrinsic");
2025 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2026 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
2027 src
.type
= dest
.type
;
2029 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
2030 dest
= offset(dest
, bld
, 1);
2035 nir_emit_intrinsic(bld
, instr
);
2041 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
2042 nir_intrinsic_instr
*instr
)
2044 assert(stage
== MESA_SHADER_COMPUTE
);
2045 struct brw_cs_prog_data
*cs_prog_data
=
2046 (struct brw_cs_prog_data
*) prog_data
;
2049 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2050 dest
= get_nir_dest(instr
->dest
);
2052 switch (instr
->intrinsic
) {
2053 case nir_intrinsic_barrier
:
2055 cs_prog_data
->uses_barrier
= true;
2058 case nir_intrinsic_load_local_invocation_id
:
2059 case nir_intrinsic_load_work_group_id
: {
2060 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2061 fs_reg val
= nir_system_values
[sv
];
2062 assert(val
.file
!= BAD_FILE
);
2063 dest
.type
= val
.type
;
2064 for (unsigned i
= 0; i
< 3; i
++)
2065 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
2069 case nir_intrinsic_load_num_work_groups
: {
2070 const unsigned surface
=
2071 cs_prog_data
->binding_table
.work_groups_start
;
2073 cs_prog_data
->uses_num_work_groups
= true;
2075 fs_reg surf_index
= brw_imm_ud(surface
);
2076 brw_mark_surface_used(prog_data
, surface
);
2078 /* Read the 3 GLuint components of gl_NumWorkGroups */
2079 for (unsigned i
= 0; i
< 3; i
++) {
2080 fs_reg read_result
=
2081 emit_untyped_read(bld
, surf_index
,
2083 1 /* dims */, 1 /* size */,
2084 BRW_PREDICATE_NONE
);
2085 read_result
.type
= dest
.type
;
2086 bld
.MOV(dest
, read_result
);
2087 dest
= offset(dest
, bld
, 1);
2093 nir_emit_intrinsic(bld
, instr
);
2099 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
2102 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2103 dest
= get_nir_dest(instr
->dest
);
2105 bool has_indirect
= false;
2107 switch (instr
->intrinsic
) {
2108 case nir_intrinsic_atomic_counter_inc
:
2109 case nir_intrinsic_atomic_counter_dec
:
2110 case nir_intrinsic_atomic_counter_read
: {
2111 using namespace surface_access
;
2113 /* Get the arguments of the atomic intrinsic. */
2114 const fs_reg offset
= get_nir_src(instr
->src
[0]);
2115 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
2116 instr
->const_index
[0]);
2119 /* Emit a surface read or atomic op. */
2120 switch (instr
->intrinsic
) {
2121 case nir_intrinsic_atomic_counter_read
:
2122 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
2125 case nir_intrinsic_atomic_counter_inc
:
2126 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2127 fs_reg(), 1, 1, BRW_AOP_INC
);
2130 case nir_intrinsic_atomic_counter_dec
:
2131 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
2132 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
2136 unreachable("Unreachable");
2139 /* Assign the result. */
2140 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
2142 /* Mark the surface as used. */
2143 brw_mark_surface_used(stage_prog_data
, surface
);
2147 case nir_intrinsic_image_load
:
2148 case nir_intrinsic_image_store
:
2149 case nir_intrinsic_image_atomic_add
:
2150 case nir_intrinsic_image_atomic_min
:
2151 case nir_intrinsic_image_atomic_max
:
2152 case nir_intrinsic_image_atomic_and
:
2153 case nir_intrinsic_image_atomic_or
:
2154 case nir_intrinsic_image_atomic_xor
:
2155 case nir_intrinsic_image_atomic_exchange
:
2156 case nir_intrinsic_image_atomic_comp_swap
: {
2157 using namespace image_access
;
2159 /* Get the referenced image variable and type. */
2160 const nir_variable
*var
= instr
->variables
[0]->var
;
2161 const glsl_type
*type
= var
->type
->without_array();
2162 const brw_reg_type base_type
= get_image_base_type(type
);
2164 /* Get some metadata from the image intrinsic. */
2165 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2166 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
2167 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
2168 const mesa_format format
=
2169 (var
->data
.image
.write_only
? MESA_FORMAT_NONE
:
2170 _mesa_get_shader_image_format(var
->data
.image
.format
));
2172 /* Get the arguments of the image intrinsic. */
2173 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2174 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
2175 BRW_REGISTER_TYPE_UD
);
2176 const fs_reg src0
= (info
->num_srcs
>= 3 ?
2177 retype(get_nir_src(instr
->src
[2]), base_type
) :
2179 const fs_reg src1
= (info
->num_srcs
>= 4 ?
2180 retype(get_nir_src(instr
->src
[3]), base_type
) :
2184 /* Emit an image load, store or atomic op. */
2185 if (instr
->intrinsic
== nir_intrinsic_image_load
)
2186 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
2188 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
2189 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
, format
);
2192 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
2193 surf_dims
, arr_dims
, info
->dest_components
,
2194 get_image_atomic_op(instr
->intrinsic
, type
));
2196 /* Assign the result. */
2197 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
2198 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
2199 offset(tmp
, bld
, c
));
2203 case nir_intrinsic_memory_barrier_atomic_counter
:
2204 case nir_intrinsic_memory_barrier_buffer
:
2205 case nir_intrinsic_memory_barrier_image
:
2206 case nir_intrinsic_memory_barrier
: {
2207 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
2208 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
2213 case nir_intrinsic_group_memory_barrier
:
2214 case nir_intrinsic_memory_barrier_shared
:
2215 /* We treat these workgroup-level barriers as no-ops. This should be
2216 * safe at present and as long as:
2218 * - Memory access instructions are not subsequently reordered by the
2219 * compiler back-end.
2221 * - All threads from a given compute shader workgroup fit within a
2222 * single subslice and therefore talk to the same HDC shared unit
2223 * what supposedly guarantees ordering and coherency between threads
2224 * from the same workgroup. This may change in the future when we
2225 * start splitting workgroups across multiple subslices.
2227 * - The context is not in fault-and-stream mode, which could cause
2228 * memory transactions (including to SLM) prior to the barrier to be
2229 * replayed after the barrier if a pagefault occurs. This shouldn't
2230 * be a problem up to and including SKL because fault-and-stream is
2231 * not usable due to hardware issues, but that's likely to change in
2236 case nir_intrinsic_shader_clock
: {
2237 /* We cannot do anything if there is an event, so ignore it for now */
2238 fs_reg shader_clock
= get_timestamp(bld
);
2239 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
2241 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
2245 case nir_intrinsic_image_size
: {
2246 /* Get the referenced image variable and type. */
2247 const nir_variable
*var
= instr
->variables
[0]->var
;
2248 const glsl_type
*type
= var
->type
->without_array();
2250 /* Get the size of the image. */
2251 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
2252 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
2254 /* For 1DArray image types, the array index is stored in the Z component.
2255 * Fix this by swizzling the Z component to the Y component.
2257 const bool is_1d_array_image
=
2258 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
2259 type
->sampler_array
;
2261 /* For CubeArray images, we should count the number of cubes instead
2262 * of the number of faces. Fix it by dividing the (Z component) by 6.
2264 const bool is_cube_array_image
=
2265 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
2266 type
->sampler_array
;
2268 /* Copy all the components. */
2269 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
2270 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
2271 if ((int)c
>= type
->coordinate_components()) {
2272 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2274 } else if (c
== 1 && is_1d_array_image
) {
2275 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2276 offset(size
, bld
, 2));
2277 } else if (c
== 2 && is_cube_array_image
) {
2278 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
2279 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2280 offset(size
, bld
, c
), brw_imm_d(6));
2282 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
2283 offset(size
, bld
, c
));
2290 case nir_intrinsic_image_samples
:
2291 /* The driver does not support multi-sampled images. */
2292 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
2295 case nir_intrinsic_load_uniform_indirect
:
2296 has_indirect
= true;
2298 case nir_intrinsic_load_uniform
: {
2299 fs_reg
uniform_reg(UNIFORM
, instr
->const_index
[0]);
2300 uniform_reg
.reg_offset
= instr
->const_index
[1];
2302 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2303 fs_reg src
= offset(retype(uniform_reg
, dest
.type
), bld
, j
);
2305 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2308 dest
= offset(dest
, bld
, 1);
2313 case nir_intrinsic_load_ubo_indirect
:
2314 has_indirect
= true;
2316 case nir_intrinsic_load_ubo
: {
2317 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
2321 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
2323 surf_index
= brw_imm_ud(index
);
2324 brw_mark_surface_used(prog_data
, index
);
2326 /* The block index is not a constant. Evaluate the index expression
2327 * per-channel and add the base UBO index; we have to select a value
2328 * from any live channel.
2330 surf_index
= vgrf(glsl_type::uint_type
);
2331 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2332 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
2333 surf_index
= bld
.emit_uniformize(surf_index
);
2335 /* Assume this may touch any UBO. It would be nice to provide
2336 * a tighter bound, but the array information is already lowered away.
2338 brw_mark_surface_used(prog_data
,
2339 stage_prog_data
->binding_table
.ubo_start
+
2340 nir
->info
.num_ubos
- 1);
2344 /* Turn the byte offset into a dword offset. */
2345 fs_reg base_offset
= vgrf(glsl_type::int_type
);
2346 bld
.SHR(base_offset
, retype(get_nir_src(instr
->src
[1]),
2347 BRW_REGISTER_TYPE_D
),
2350 unsigned vec4_offset
= instr
->const_index
[0] / 4;
2351 for (int i
= 0; i
< instr
->num_components
; i
++)
2352 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
2353 base_offset
, vec4_offset
+ i
);
2355 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
2356 packed_consts
.type
= dest
.type
;
2358 struct brw_reg const_offset_reg
= brw_imm_ud(instr
->const_index
[0] & ~15);
2359 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
, packed_consts
,
2360 surf_index
, const_offset_reg
);
2362 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2363 packed_consts
.set_smear(instr
->const_index
[0] % 16 / 4 + i
);
2365 /* The std140 packing rules don't allow vectors to cross 16-byte
2366 * boundaries, and a reg is 32 bytes.
2368 assert(packed_consts
.subreg_offset
< 32);
2370 bld
.MOV(dest
, packed_consts
);
2371 dest
= offset(dest
, bld
, 1);
2377 case nir_intrinsic_load_ssbo_indirect
:
2378 has_indirect
= true;
2380 case nir_intrinsic_load_ssbo
: {
2381 assert(devinfo
->gen
>= 7);
2383 nir_const_value
*const_uniform_block
=
2384 nir_src_as_const_value(instr
->src
[0]);
2387 if (const_uniform_block
) {
2388 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2389 const_uniform_block
->u
[0];
2390 surf_index
= brw_imm_ud(index
);
2391 brw_mark_surface_used(prog_data
, index
);
2393 surf_index
= vgrf(glsl_type::uint_type
);
2394 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
2395 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2397 /* Assume this may touch any UBO. It would be nice to provide
2398 * a tighter bound, but the array information is already lowered away.
2400 brw_mark_surface_used(prog_data
,
2401 stage_prog_data
->binding_table
.ssbo_start
+
2402 nir
->info
.num_ssbos
- 1);
2405 /* Get the offset to read from */
2408 offset_reg
= get_nir_src(instr
->src
[1]);
2410 offset_reg
= brw_imm_ud(instr
->const_index
[0]);
2413 /* Read the vector */
2414 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2416 instr
->num_components
,
2417 BRW_PREDICATE_NONE
);
2418 read_result
.type
= dest
.type
;
2419 for (int i
= 0; i
< instr
->num_components
; i
++)
2420 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2425 case nir_intrinsic_load_input_indirect
:
2426 has_indirect
= true;
2428 case nir_intrinsic_load_input
: {
2430 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2432 if (stage
== MESA_SHADER_VERTEX
) {
2433 src
= offset(fs_reg(ATTR
, instr
->const_index
[0], dest
.type
), bld
, index
);
2435 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
2436 instr
->const_index
[0] + index
);
2439 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[0]));
2443 dest
= offset(dest
, bld
, 1);
2448 case nir_intrinsic_store_ssbo_indirect
:
2449 has_indirect
= true;
2451 case nir_intrinsic_store_ssbo
: {
2452 assert(devinfo
->gen
>= 7);
2456 nir_const_value
*const_uniform_block
=
2457 nir_src_as_const_value(instr
->src
[1]);
2458 if (const_uniform_block
) {
2459 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
2460 const_uniform_block
->u
[0];
2461 surf_index
= brw_imm_ud(index
);
2462 brw_mark_surface_used(prog_data
, index
);
2464 surf_index
= vgrf(glsl_type::uint_type
);
2465 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
2466 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2468 brw_mark_surface_used(prog_data
,
2469 stage_prog_data
->binding_table
.ssbo_start
+
2470 nir
->info
.num_ssbos
- 1);
2474 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
2477 unsigned writemask
= instr
->const_index
[1];
2479 /* Combine groups of consecutive enabled channels in one write
2480 * message. We use ffs to find the first enabled channel and then ffs on
2481 * the bit-inverse, down-shifted writemask to determine the length of
2482 * the block of enabled bits.
2485 unsigned first_component
= ffs(writemask
) - 1;
2486 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
2489 if (!has_indirect
) {
2490 offset_reg
= brw_imm_ud(instr
->const_index
[0] + 4 * first_component
);
2492 offset_reg
= vgrf(glsl_type::uint_type
);
2494 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
2495 brw_imm_ud(4 * first_component
));
2498 emit_untyped_write(bld
, surf_index
, offset_reg
,
2499 offset(val_reg
, bld
, first_component
),
2500 1 /* dims */, length
,
2501 BRW_PREDICATE_NONE
);
2503 /* Clear the bits in the writemask that we just wrote, then try
2504 * again to see if more channels are left.
2506 writemask
&= (15 << (first_component
+ length
));
2511 case nir_intrinsic_store_output_indirect
:
2512 has_indirect
= true;
2514 case nir_intrinsic_store_output
: {
2515 fs_reg src
= get_nir_src(instr
->src
[0]);
2517 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
2518 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
2519 instr
->const_index
[0] + index
);
2521 src
.reladdr
= new(mem_ctx
) fs_reg(get_nir_src(instr
->src
[1]));
2523 bld
.MOV(new_dest
, src
);
2524 src
= offset(src
, bld
, 1);
2529 case nir_intrinsic_ssbo_atomic_add
:
2530 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
2532 case nir_intrinsic_ssbo_atomic_imin
:
2533 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
2535 case nir_intrinsic_ssbo_atomic_umin
:
2536 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
2538 case nir_intrinsic_ssbo_atomic_imax
:
2539 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
2541 case nir_intrinsic_ssbo_atomic_umax
:
2542 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
2544 case nir_intrinsic_ssbo_atomic_and
:
2545 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
2547 case nir_intrinsic_ssbo_atomic_or
:
2548 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
2550 case nir_intrinsic_ssbo_atomic_xor
:
2551 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
2553 case nir_intrinsic_ssbo_atomic_exchange
:
2554 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
2556 case nir_intrinsic_ssbo_atomic_comp_swap
:
2557 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
2560 case nir_intrinsic_get_buffer_size
: {
2561 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
2562 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u
[0] : 0;
2563 int reg_width
= dispatch_width
/ 8;
2566 fs_reg source
= brw_imm_d(0);
2568 int mlen
= 1 * reg_width
;
2570 /* A resinfo's sampler message is used to get the buffer size.
2571 * The SIMD8's writeback message consists of four registers and
2572 * SIMD16's writeback message consists of 8 destination registers
2573 * (two per each component), although we are only interested on the
2574 * first component, where resinfo returns the buffer size for
2577 int regs_written
= 4 * mlen
;
2578 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
2579 BRW_REGISTER_TYPE_UD
);
2580 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
2581 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
2582 BRW_REGISTER_TYPE_UD
);
2583 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
2584 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
2585 src_payload
, brw_imm_ud(index
));
2586 inst
->header_size
= 0;
2588 inst
->regs_written
= regs_written
;
2590 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
2592 brw_mark_surface_used(prog_data
, index
);
2597 unreachable("unknown intrinsic");
2602 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
2603 int op
, nir_intrinsic_instr
*instr
)
2606 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2607 dest
= get_nir_dest(instr
->dest
);
2610 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
2611 if (const_surface
) {
2612 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
2613 const_surface
->u
[0];
2614 surface
= brw_imm_ud(surf_index
);
2615 brw_mark_surface_used(prog_data
, surf_index
);
2617 surface
= vgrf(glsl_type::uint_type
);
2618 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
2619 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
2621 /* Assume this may touch any SSBO. This is the same we do for other
2622 * UBO/SSBO accesses with non-constant surface.
2624 brw_mark_surface_used(prog_data
,
2625 stage_prog_data
->binding_table
.ssbo_start
+
2626 nir
->info
.num_ssbos
- 1);
2629 fs_reg offset
= get_nir_src(instr
->src
[1]);
2630 fs_reg data1
= get_nir_src(instr
->src
[2]);
2632 if (op
== BRW_AOP_CMPWR
)
2633 data2
= get_nir_src(instr
->src
[3]);
2635 /* Emit the actual atomic operation operation */
2637 fs_reg atomic_result
=
2638 surface_access::emit_untyped_atomic(bld
, surface
, offset
,
2640 1 /* dims */, 1 /* rsize */,
2642 BRW_PREDICATE_NONE
);
2643 dest
.type
= atomic_result
.type
;
2644 bld
.MOV(dest
, atomic_result
);
2648 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
2650 unsigned sampler
= instr
->sampler_index
;
2651 fs_reg
sampler_reg(brw_imm_ud(sampler
));
2653 int gather_component
= instr
->component
;
2655 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
2658 int lod_components
= 0;
2659 int UNUSED offset_components
= 0;
2661 fs_reg coordinate
, shadow_comparitor
, lod
, lod2
, sample_index
, mcs
, tex_offset
;
2663 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
2664 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
2665 switch (instr
->src
[i
].src_type
) {
2666 case nir_tex_src_bias
:
2667 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2669 case nir_tex_src_comparitor
:
2670 shadow_comparitor
= retype(src
, BRW_REGISTER_TYPE_F
);
2672 case nir_tex_src_coord
:
2673 switch (instr
->op
) {
2675 case nir_texop_txf_ms
:
2676 case nir_texop_samples_identical
:
2677 coordinate
= retype(src
, BRW_REGISTER_TYPE_D
);
2680 coordinate
= retype(src
, BRW_REGISTER_TYPE_F
);
2684 case nir_tex_src_ddx
:
2685 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2686 lod_components
= nir_tex_instr_src_size(instr
, i
);
2688 case nir_tex_src_ddy
:
2689 lod2
= retype(src
, BRW_REGISTER_TYPE_F
);
2691 case nir_tex_src_lod
:
2692 switch (instr
->op
) {
2694 lod
= retype(src
, BRW_REGISTER_TYPE_UD
);
2697 lod
= retype(src
, BRW_REGISTER_TYPE_D
);
2700 lod
= retype(src
, BRW_REGISTER_TYPE_F
);
2704 case nir_tex_src_ms_index
:
2705 sample_index
= retype(src
, BRW_REGISTER_TYPE_UD
);
2707 case nir_tex_src_offset
:
2708 tex_offset
= retype(src
, BRW_REGISTER_TYPE_D
);
2709 if (instr
->is_array
)
2710 offset_components
= instr
->coord_components
- 1;
2712 offset_components
= instr
->coord_components
;
2714 case nir_tex_src_projector
:
2715 unreachable("should be lowered");
2717 case nir_tex_src_sampler_offset
: {
2718 /* Figure out the highest possible sampler index and mark it as used */
2719 uint32_t max_used
= sampler
+ instr
->sampler_array_size
- 1;
2720 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
2721 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
2723 max_used
+= stage_prog_data
->binding_table
.texture_start
;
2725 brw_mark_surface_used(prog_data
, max_used
);
2727 /* Emit code to evaluate the actual indexing expression */
2728 sampler_reg
= vgrf(glsl_type::uint_type
);
2729 bld
.ADD(sampler_reg
, src
, brw_imm_ud(sampler
));
2730 sampler_reg
= bld
.emit_uniformize(sampler_reg
);
2735 unreachable("unknown texture source");
2739 if (instr
->op
== nir_texop_txf_ms
||
2740 instr
->op
== nir_texop_samples_identical
) {
2741 if (devinfo
->gen
>= 7 &&
2742 key_tex
->compressed_multisample_layout_mask
& (1 << sampler
)) {
2743 mcs
= emit_mcs_fetch(coordinate
, instr
->coord_components
, sampler_reg
);
2745 mcs
= brw_imm_ud(0u);
2749 for (unsigned i
= 0; i
< 3; i
++) {
2750 if (instr
->const_offset
[i
] != 0) {
2751 assert(offset_components
== 0);
2752 tex_offset
= brw_imm_ud(brw_texture_offset(instr
->const_offset
, 3));
2757 enum glsl_base_type dest_base_type
=
2758 brw_glsl_base_type_for_nir_type (instr
->dest_type
);
2760 const glsl_type
*dest_type
=
2761 glsl_type::get_instance(dest_base_type
, nir_tex_instr_dest_size(instr
),
2764 ir_texture_opcode op
;
2765 switch (instr
->op
) {
2766 case nir_texop_lod
: op
= ir_lod
; break;
2767 case nir_texop_query_levels
: op
= ir_query_levels
; break;
2768 case nir_texop_tex
: op
= ir_tex
; break;
2769 case nir_texop_tg4
: op
= ir_tg4
; break;
2770 case nir_texop_txb
: op
= ir_txb
; break;
2771 case nir_texop_txd
: op
= ir_txd
; break;
2772 case nir_texop_txf
: op
= ir_txf
; break;
2773 case nir_texop_txf_ms
: op
= ir_txf_ms
; break;
2774 case nir_texop_txl
: op
= ir_txl
; break;
2775 case nir_texop_txs
: op
= ir_txs
; break;
2776 case nir_texop_texture_samples
: {
2777 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
2778 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, dst
,
2779 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
2782 inst
->header_size
= 1;
2783 inst
->base_mrf
= -1;
2786 case nir_texop_samples_identical
: op
= ir_samples_identical
; break;
2788 unreachable("unknown texture opcode");
2791 emit_texture(op
, dest_type
, coordinate
, instr
->coord_components
,
2792 shadow_comparitor
, lod
, lod2
, lod_components
, sample_index
,
2793 tex_offset
, mcs
, gather_component
,
2794 is_cube_array
, sampler
, sampler_reg
);
2796 fs_reg dest
= get_nir_dest(instr
->dest
);
2797 dest
.type
= this->result
.type
;
2798 unsigned num_components
= nir_tex_instr_dest_size(instr
);
2799 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
2800 dest
, this->result
),
2801 (1 << num_components
) - 1);
2805 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
2807 switch (instr
->type
) {
2808 case nir_jump_break
:
2809 bld
.emit(BRW_OPCODE_BREAK
);
2811 case nir_jump_continue
:
2812 bld
.emit(BRW_OPCODE_CONTINUE
);
2814 case nir_jump_return
:
2816 unreachable("unknown jump");