2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
41 nir_emit_system_values();
43 /* get the main function and emit it */
44 nir_foreach_function(function
, nir
) {
45 assert(strcmp(function
->name
, "main") == 0);
46 assert(function
->impl
);
47 nir_emit_impl(function
->impl
);
52 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
53 const glsl_type
*type
,
56 if (type
->is_array() || type
->is_matrix()) {
57 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
58 const unsigned length
= glsl_get_length(type
);
60 for (unsigned i
= 0; i
< length
; i
++) {
61 nir_setup_single_output_varying(reg
, elem_type
, location
);
63 } else if (type
->is_record()) {
64 for (unsigned i
= 0; i
< type
->length
; i
++) {
65 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
66 nir_setup_single_output_varying(reg
, field_type
, location
);
69 assert(type
->is_scalar() || type
->is_vector());
70 unsigned num_iter
= 1;
71 if (type
->is_dual_slot())
73 for (unsigned count
= 0; count
< num_iter
; count
++) {
74 this->outputs
[*location
] = *reg
;
75 *reg
= offset(*reg
, bld
, 4);
82 fs_visitor::nir_setup_outputs()
84 if (stage
== MESA_SHADER_TESS_CTRL
|| stage
== MESA_SHADER_FRAGMENT
)
87 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
89 nir_foreach_variable(var
, &nir
->outputs
) {
91 case MESA_SHADER_VERTEX
:
92 case MESA_SHADER_TESS_EVAL
:
93 case MESA_SHADER_GEOMETRY
: {
94 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
95 unsigned location
= var
->data
.location
;
96 nir_setup_single_output_varying(®
, var
->type
, &location
);
100 unreachable("unhandled shader stage");
106 fs_visitor::nir_setup_uniforms()
108 if (dispatch_width
!= min_dispatch_width
)
111 uniforms
= nir
->num_uniforms
/ 4;
115 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
119 nir_foreach_instr(instr
, block
) {
120 if (instr
->type
!= nir_instr_type_intrinsic
)
123 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
124 switch (intrin
->intrinsic
) {
125 case nir_intrinsic_load_vertex_id
:
126 unreachable("should be lowered by lower_vertex_id().");
128 case nir_intrinsic_load_vertex_id_zero_base
:
129 assert(v
->stage
== MESA_SHADER_VERTEX
);
130 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
131 if (reg
->file
== BAD_FILE
)
132 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
135 case nir_intrinsic_load_base_vertex
:
136 assert(v
->stage
== MESA_SHADER_VERTEX
);
137 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
138 if (reg
->file
== BAD_FILE
)
139 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
142 case nir_intrinsic_load_instance_id
:
143 assert(v
->stage
== MESA_SHADER_VERTEX
);
144 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
145 if (reg
->file
== BAD_FILE
)
146 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
149 case nir_intrinsic_load_base_instance
:
150 assert(v
->stage
== MESA_SHADER_VERTEX
);
151 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
152 if (reg
->file
== BAD_FILE
)
153 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
156 case nir_intrinsic_load_draw_id
:
157 assert(v
->stage
== MESA_SHADER_VERTEX
);
158 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
159 if (reg
->file
== BAD_FILE
)
160 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
163 case nir_intrinsic_load_invocation_id
:
164 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
166 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
167 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
168 if (reg
->file
== BAD_FILE
) {
169 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
170 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
171 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
172 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
177 case nir_intrinsic_load_sample_pos
:
178 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
179 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
180 if (reg
->file
== BAD_FILE
)
181 *reg
= *v
->emit_samplepos_setup();
184 case nir_intrinsic_load_sample_id
:
185 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
186 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
187 if (reg
->file
== BAD_FILE
)
188 *reg
= *v
->emit_sampleid_setup();
191 case nir_intrinsic_load_sample_mask_in
:
192 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
193 assert(v
->devinfo
->gen
>= 7);
194 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
195 if (reg
->file
== BAD_FILE
)
196 *reg
= *v
->emit_samplemaskin_setup();
199 case nir_intrinsic_load_work_group_id
:
200 assert(v
->stage
== MESA_SHADER_COMPUTE
);
201 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
202 if (reg
->file
== BAD_FILE
)
203 *reg
= *v
->emit_cs_work_group_id_setup();
206 case nir_intrinsic_load_helper_invocation
:
207 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
208 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
209 if (reg
->file
== BAD_FILE
) {
210 const fs_builder abld
=
211 v
->bld
.annotate("gl_HelperInvocation", NULL
);
213 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
214 * pixel mask is in g1.7 of the thread payload.
216 * We move the per-channel pixel enable bit to the low bit of each
217 * channel by shifting the byte containing the pixel mask by the
218 * vector immediate 0x76543210UV.
220 * The region of <1,8,0> reads only 1 byte (the pixel masks for
221 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
222 * masks for 2 and 3) in SIMD16.
224 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
226 stride(byte_offset(retype(brw_vec1_grf(1, 0),
227 BRW_REGISTER_TYPE_UB
), 28),
229 brw_imm_v(0x76543210));
231 /* A set bit in the pixel mask means the channel is enabled, but
232 * that is the opposite of gl_HelperInvocation so we need to invert
235 * The negate source-modifier bit of logical instructions on Gen8+
236 * performs 1's complement negation, so we can use that instead of
239 fs_reg inverted
= negate(shifted
);
240 if (v
->devinfo
->gen
< 8) {
241 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
242 abld
.NOT(inverted
, shifted
);
245 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
246 * with 1 and negating.
248 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
249 abld
.AND(anded
, inverted
, brw_imm_uw(1));
251 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
252 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
266 fs_visitor::nir_emit_system_values()
268 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
269 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
270 nir_system_values
[i
] = fs_reg();
273 nir_foreach_function(function
, nir
) {
274 assert(strcmp(function
->name
, "main") == 0);
275 assert(function
->impl
);
276 nir_foreach_block(block
, function
->impl
) {
277 emit_system_values_block(block
, this);
283 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
285 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
286 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
287 nir_locals
[i
] = fs_reg();
290 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
291 unsigned array_elems
=
292 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
293 unsigned size
= array_elems
* reg
->num_components
;
294 const brw_reg_type reg_type
=
295 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
296 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
299 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
302 nir_emit_cf_list(&impl
->body
);
306 fs_visitor::nir_emit_cf_list(exec_list
*list
)
308 exec_list_validate(list
);
309 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
310 switch (node
->type
) {
312 nir_emit_if(nir_cf_node_as_if(node
));
315 case nir_cf_node_loop
:
316 nir_emit_loop(nir_cf_node_as_loop(node
));
319 case nir_cf_node_block
:
320 nir_emit_block(nir_cf_node_as_block(node
));
324 unreachable("Invalid CFG node block");
330 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
332 /* first, put the condition into f0 */
333 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
334 retype(get_nir_src(if_stmt
->condition
),
335 BRW_REGISTER_TYPE_D
));
336 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
338 bld
.IF(BRW_PREDICATE_NORMAL
);
340 nir_emit_cf_list(&if_stmt
->then_list
);
342 /* note: if the else is empty, dead CF elimination will remove it */
343 bld
.emit(BRW_OPCODE_ELSE
);
345 nir_emit_cf_list(&if_stmt
->else_list
);
347 bld
.emit(BRW_OPCODE_ENDIF
);
351 fs_visitor::nir_emit_loop(nir_loop
*loop
)
353 bld
.emit(BRW_OPCODE_DO
);
355 nir_emit_cf_list(&loop
->body
);
357 bld
.emit(BRW_OPCODE_WHILE
);
361 fs_visitor::nir_emit_block(nir_block
*block
)
363 nir_foreach_instr(instr
, block
) {
364 nir_emit_instr(instr
);
369 fs_visitor::nir_emit_instr(nir_instr
*instr
)
371 const fs_builder abld
= bld
.annotate(NULL
, instr
);
373 switch (instr
->type
) {
374 case nir_instr_type_alu
:
375 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
378 case nir_instr_type_intrinsic
:
380 case MESA_SHADER_VERTEX
:
381 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
383 case MESA_SHADER_TESS_CTRL
:
384 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
386 case MESA_SHADER_TESS_EVAL
:
387 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
389 case MESA_SHADER_GEOMETRY
:
390 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
392 case MESA_SHADER_FRAGMENT
:
393 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
395 case MESA_SHADER_COMPUTE
:
396 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
399 unreachable("unsupported shader stage");
403 case nir_instr_type_tex
:
404 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
407 case nir_instr_type_load_const
:
408 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
411 case nir_instr_type_ssa_undef
:
412 /* We create a new VGRF for undefs on every use (by handling
413 * them in get_nir_src()), rather than for each definition.
414 * This helps register coalescing eliminate MOVs from undef.
418 case nir_instr_type_jump
:
419 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
423 unreachable("unknown instruction type");
428 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
432 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
433 const fs_reg
&result
)
435 if (!instr
->src
[0].src
.is_ssa
||
436 !instr
->src
[0].src
.ssa
->parent_instr
)
439 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
442 nir_alu_instr
*src0
=
443 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
445 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
446 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
449 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
450 assert(element
!= NULL
);
452 /* Element type to extract.*/
453 const brw_reg_type type
= brw_int_type(
454 src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
? 2 : 1,
455 src0
->op
== nir_op_extract_i16
|| src0
->op
== nir_op_extract_i8
);
457 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
458 op0
.type
= brw_type_for_nir_type(
459 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
460 nir_src_bit_size(src0
->src
[0].src
)));
461 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
463 set_saturate(instr
->dest
.saturate
,
464 bld
.MOV(result
, subscript(op0
, type
, element
->u32
[0])));
469 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
470 const fs_reg
&result
)
472 if (!instr
->src
[0].src
.is_ssa
||
473 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
476 nir_intrinsic_instr
*src0
=
477 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
479 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
482 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
483 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
486 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
487 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
490 fs_reg tmp
= vgrf(glsl_type::int_type
);
492 if (devinfo
->gen
>= 6) {
493 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
494 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
496 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
498 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
499 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
501 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
503 * This negation looks like it's safe in practice, because bits 0:4 will
504 * surely be TRIANGLES
507 if (value1
->f32
[0] == -1.0f
) {
511 bld
.OR(subscript(tmp
, BRW_REGISTER_TYPE_W
, 1),
512 g0
, brw_imm_uw(0x3f80));
514 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
515 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
517 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
519 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
520 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
522 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
524 * This negation looks like it's safe in practice, because bits 0:4 will
525 * surely be TRIANGLES
528 if (value1
->f32
[0] == -1.0f
) {
532 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
534 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
540 emit_find_msb_using_lzd(const fs_builder
&bld
,
541 const fs_reg
&result
,
549 /* LZD of an absolute value source almost always does the right
550 * thing. There are two problem values:
552 * * 0x80000000. Since abs(0x80000000) == 0x80000000, LZD returns
553 * 0. However, findMSB(int(0x80000000)) == 30.
555 * * 0xffffffff. Since abs(0xffffffff) == 1, LZD returns
556 * 31. Section 8.8 (Integer Functions) of the GLSL 4.50 spec says:
558 * For a value of zero or negative one, -1 will be returned.
560 * * Negative powers of two. LZD(abs(-(1<<x))) returns x, but
561 * findMSB(-(1<<x)) should return x-1.
563 * For all negative number cases, including 0x80000000 and
564 * 0xffffffff, the correct value is obtained from LZD if instead of
565 * negating the (already negative) value the logical-not is used. A
566 * conditonal logical-not can be achieved in two instructions.
568 temp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
570 bld
.ASR(temp
, src
, brw_imm_d(31));
571 bld
.XOR(temp
, temp
, src
);
574 bld
.LZD(retype(result
, BRW_REGISTER_TYPE_UD
),
575 retype(temp
, BRW_REGISTER_TYPE_UD
));
577 /* LZD counts from the MSB side, while GLSL's findMSB() wants the count
578 * from the LSB side. Subtract the result from 31 to convert the MSB
579 * count into an LSB count. If no bits are set, LZD will return 32.
580 * 31-32 = -1, which is exactly what findMSB() is supposed to return.
582 inst
= bld
.ADD(result
, retype(result
, BRW_REGISTER_TYPE_D
), brw_imm_d(31));
583 inst
->src
[0].negate
= true;
587 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
589 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
592 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
593 result
.type
= brw_type_for_nir_type(
594 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
595 nir_dest_bit_size(instr
->dest
.dest
)));
598 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
599 op
[i
] = get_nir_src(instr
->src
[i
].src
);
600 op
[i
].type
= brw_type_for_nir_type(
601 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
602 nir_src_bit_size(instr
->src
[i
].src
)));
603 op
[i
].abs
= instr
->src
[i
].abs
;
604 op
[i
].negate
= instr
->src
[i
].negate
;
607 /* We get a bunch of mov's out of the from_ssa pass and they may still
608 * be vectorized. We'll handle them as a special-case. We'll also
609 * handle vecN here because it's basically the same thing.
617 fs_reg temp
= result
;
618 bool need_extra_copy
= false;
619 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
620 if (!instr
->src
[i
].src
.is_ssa
&&
621 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
622 need_extra_copy
= true;
623 temp
= bld
.vgrf(result
.type
, 4);
628 for (unsigned i
= 0; i
< 4; i
++) {
629 if (!(instr
->dest
.write_mask
& (1 << i
)))
632 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
633 inst
= bld
.MOV(offset(temp
, bld
, i
),
634 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
636 inst
= bld
.MOV(offset(temp
, bld
, i
),
637 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
639 inst
->saturate
= instr
->dest
.saturate
;
642 /* In this case the source and destination registers were the same,
643 * so we need to insert an extra set of moves in order to deal with
646 if (need_extra_copy
) {
647 for (unsigned i
= 0; i
< 4; i
++) {
648 if (!(instr
->dest
.write_mask
& (1 << i
)))
651 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
660 /* At this point, we have dealt with any instruction that operates on
661 * more than a single channel. Therefore, we can just adjust the source
662 * and destination registers for that channel and emit the instruction.
664 unsigned channel
= 0;
665 if (nir_op_infos
[instr
->op
].output_size
== 0) {
666 /* Since NIR is doing the scalarizing for us, we should only ever see
667 * vectorized operations with a single channel.
669 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
670 channel
= ffs(instr
->dest
.write_mask
) - 1;
672 result
= offset(result
, bld
, channel
);
675 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
676 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
677 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
683 if (optimize_extract_to_float(instr
, result
))
685 inst
= bld
.MOV(result
, op
[0]);
686 inst
->saturate
= instr
->dest
.saturate
;
692 /* CHV PRM, vol07, 3D Media GPGPU Engine, Register Region Restrictions:
694 * "When source or destination is 64b (...), regioning in Align1
695 * must follow these rules:
697 * 1. Source and destination horizontal stride must be aligned to
701 * This means that 32-bit to 64-bit conversions need to have the 32-bit
702 * data elements aligned to 64-bit. This restriction does not apply to
705 if (devinfo
->is_cherryview
|| devinfo
->is_broxton
) {
706 fs_reg tmp
= bld
.vgrf(result
.type
, 1);
707 tmp
= subscript(tmp
, op
[0].type
, 0);
708 inst
= bld
.MOV(tmp
, op
[0]);
709 inst
= bld
.MOV(result
, tmp
);
710 inst
->saturate
= instr
->dest
.saturate
;
717 inst
= bld
.MOV(result
, op
[0]);
718 inst
->saturate
= instr
->dest
.saturate
;
723 bld
.MOV(result
, op
[0]);
727 if (type_sz(op
[0].type
) < 8) {
728 /* AND(val, 0x80000000) gives the sign bit.
730 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
733 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
735 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
736 op
[0].type
= BRW_REGISTER_TYPE_UD
;
737 result
.type
= BRW_REGISTER_TYPE_UD
;
738 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
740 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
741 inst
->predicate
= BRW_PREDICATE_NORMAL
;
742 if (instr
->dest
.saturate
) {
743 inst
= bld
.MOV(result
, result
);
744 inst
->saturate
= true;
747 /* For doubles we do the same but we need to consider:
749 * - 2-src instructions can't operate with 64-bit immediates
750 * - The sign is encoded in the high 32-bit of each DF
751 * - CMP with DF requires special handling in SIMD16
752 * - We need to produce a DF result.
755 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
756 * a register and compare with that.
758 fs_reg tmp
= vgrf(glsl_type::double_type
);
759 bld
.MOV(tmp
, setup_imm_df(bld
, 0.0));
761 /* A direct DF CMP using the flag register (null dst) won't work in
762 * SIMD16 because the CMP will be split in two by lower_simd_width,
763 * resulting in two CMP instructions with the same dst (NULL),
764 * leading to dead code elimination of the first one. In SIMD8,
765 * however, there is no need to split the CMP and we can save some
768 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
769 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
771 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
772 * so we store the result of the comparison in a vgrf instead and
773 * then we generate a UD comparison from that that won't have to
774 * be split by lower_simd_width. This is what NIR does to handle
775 * double comparisons in the general case.
777 if (bld
.dispatch_width() == 16 ) {
778 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
779 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
780 bld
.CMP(bld
.null_reg_ud(),
781 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
784 /* Get the high 32-bit of each double component where the sign is */
785 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
786 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
788 /* Get the sign bit */
789 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
791 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
792 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
793 inst
->predicate
= BRW_PREDICATE_NORMAL
;
795 /* Convert from 32-bit float to 64-bit double */
796 result
.type
= BRW_REGISTER_TYPE_DF
;
797 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
799 if (instr
->dest
.saturate
) {
800 inst
= bld
.MOV(result
, result
);
801 inst
->saturate
= true;
808 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
809 * -> non-negative val generates 0x00000000.
810 * Predicated OR sets 1 if val is positive.
812 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
813 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
814 bld
.ASR(result
, op
[0], brw_imm_d(31));
815 inst
= bld
.OR(result
, result
, brw_imm_d(1));
816 inst
->predicate
= BRW_PREDICATE_NORMAL
;
820 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
821 inst
->saturate
= instr
->dest
.saturate
;
825 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
826 inst
->saturate
= instr
->dest
.saturate
;
830 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
831 inst
->saturate
= instr
->dest
.saturate
;
835 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
836 inst
->saturate
= instr
->dest
.saturate
;
840 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
841 inst
->saturate
= instr
->dest
.saturate
;
845 if (fs_key
->high_quality_derivatives
) {
846 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
848 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
850 inst
->saturate
= instr
->dest
.saturate
;
852 case nir_op_fddx_fine
:
853 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
854 inst
->saturate
= instr
->dest
.saturate
;
856 case nir_op_fddx_coarse
:
857 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
858 inst
->saturate
= instr
->dest
.saturate
;
861 if (fs_key
->high_quality_derivatives
) {
862 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
864 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
866 inst
->saturate
= instr
->dest
.saturate
;
868 case nir_op_fddy_fine
:
869 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
872 case nir_op_fddy_coarse
:
873 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
878 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
880 inst
= bld
.ADD(result
, op
[0], op
[1]);
881 inst
->saturate
= instr
->dest
.saturate
;
885 inst
= bld
.MUL(result
, op
[0], op
[1]);
886 inst
->saturate
= instr
->dest
.saturate
;
890 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
891 bld
.MUL(result
, op
[0], op
[1]);
894 case nir_op_imul_high
:
895 case nir_op_umul_high
:
896 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
897 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
902 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
903 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
906 case nir_op_uadd_carry
:
907 unreachable("Should have been lowered by carry_to_arith().");
909 case nir_op_usub_borrow
:
910 unreachable("Should have been lowered by borrow_to_arith().");
914 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
915 * appears that our hardware just does the right thing for signed
918 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
919 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
923 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
924 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
926 /* Math instructions don't support conditional mod */
927 inst
= bld
.MOV(bld
.null_reg_d(), result
);
928 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
930 /* Now, we need to determine if signs of the sources are different.
931 * When we XOR the sources, the top bit is 0 if they are the same and 1
932 * if they are different. We can then use a conditional modifier to
933 * turn that into a predicate. This leads us to an XOR.l instruction.
935 * Technically, according to the PRM, you're not allowed to use .l on a
936 * XOR instruction. However, emperical experiments and Curro's reading
937 * of the simulator source both indicate that it's safe.
939 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
940 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
941 inst
->predicate
= BRW_PREDICATE_NORMAL
;
942 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
944 /* If the result of the initial remainder operation is non-zero and the
945 * two sources have different signs, add in a copy of op[1] to get the
946 * final integer modulus value.
948 inst
= bld
.ADD(result
, result
, op
[1]);
949 inst
->predicate
= BRW_PREDICATE_NORMAL
;
957 fs_reg dest
= result
;
958 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
959 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
961 brw_conditional_mod cond
;
964 cond
= BRW_CONDITIONAL_L
;
967 cond
= BRW_CONDITIONAL_GE
;
970 cond
= BRW_CONDITIONAL_Z
;
973 cond
= BRW_CONDITIONAL_NZ
;
976 unreachable("bad opcode");
978 bld
.CMP(dest
, op
[0], op
[1], cond
);
979 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
980 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
987 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
988 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
993 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
994 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
998 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
999 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1003 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1004 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1008 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1009 if (devinfo
->gen
>= 8) {
1010 op
[0] = resolve_source_modifiers(op
[0]);
1012 bld
.NOT(result
, op
[0]);
1015 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1016 if (devinfo
->gen
>= 8) {
1017 op
[0] = resolve_source_modifiers(op
[0]);
1018 op
[1] = resolve_source_modifiers(op
[1]);
1020 bld
.XOR(result
, op
[0], op
[1]);
1023 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1024 if (devinfo
->gen
>= 8) {
1025 op
[0] = resolve_source_modifiers(op
[0]);
1026 op
[1] = resolve_source_modifiers(op
[1]);
1028 bld
.OR(result
, op
[0], op
[1]);
1031 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1032 if (devinfo
->gen
>= 8) {
1033 op
[0] = resolve_source_modifiers(op
[0]);
1034 op
[1] = resolve_source_modifiers(op
[1]);
1036 bld
.AND(result
, op
[0], op
[1]);
1042 case nir_op_ball_fequal2
:
1043 case nir_op_ball_iequal2
:
1044 case nir_op_ball_fequal3
:
1045 case nir_op_ball_iequal3
:
1046 case nir_op_ball_fequal4
:
1047 case nir_op_ball_iequal4
:
1048 case nir_op_bany_fnequal2
:
1049 case nir_op_bany_inequal2
:
1050 case nir_op_bany_fnequal3
:
1051 case nir_op_bany_inequal3
:
1052 case nir_op_bany_fnequal4
:
1053 case nir_op_bany_inequal4
:
1054 unreachable("Lowered by nir_lower_alu_reductions");
1056 case nir_op_fnoise1_1
:
1057 case nir_op_fnoise1_2
:
1058 case nir_op_fnoise1_3
:
1059 case nir_op_fnoise1_4
:
1060 case nir_op_fnoise2_1
:
1061 case nir_op_fnoise2_2
:
1062 case nir_op_fnoise2_3
:
1063 case nir_op_fnoise2_4
:
1064 case nir_op_fnoise3_1
:
1065 case nir_op_fnoise3_2
:
1066 case nir_op_fnoise3_3
:
1067 case nir_op_fnoise3_4
:
1068 case nir_op_fnoise4_1
:
1069 case nir_op_fnoise4_2
:
1070 case nir_op_fnoise4_3
:
1071 case nir_op_fnoise4_4
:
1072 unreachable("not reached: should be handled by lower_noise");
1075 unreachable("not reached: should be handled by ldexp_to_arith()");
1078 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1079 inst
->saturate
= instr
->dest
.saturate
;
1083 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1084 inst
->saturate
= instr
->dest
.saturate
;
1089 bld
.MOV(result
, negate(op
[0]));
1093 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1096 /* two-argument instructions can't take 64-bit immediates */
1097 fs_reg zero
= vgrf(glsl_type::double_type
);
1098 bld
.MOV(zero
, setup_imm_df(bld
, 0.0));
1099 /* A SIMD16 execution needs to be split in two instructions, so use
1100 * a vgrf instead of the flag register as dst so instruction splitting
1103 fs_reg tmp
= vgrf(glsl_type::double_type
);
1104 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1105 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1109 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1113 inst
= bld
.RNDZ(result
, op
[0]);
1114 inst
->saturate
= instr
->dest
.saturate
;
1117 case nir_op_fceil
: {
1118 op
[0].negate
= !op
[0].negate
;
1119 fs_reg temp
= vgrf(glsl_type::float_type
);
1120 bld
.RNDD(temp
, op
[0]);
1122 inst
= bld
.MOV(result
, temp
);
1123 inst
->saturate
= instr
->dest
.saturate
;
1127 inst
= bld
.RNDD(result
, op
[0]);
1128 inst
->saturate
= instr
->dest
.saturate
;
1131 inst
= bld
.FRC(result
, op
[0]);
1132 inst
->saturate
= instr
->dest
.saturate
;
1134 case nir_op_fround_even
:
1135 inst
= bld
.RNDE(result
, op
[0]);
1136 inst
->saturate
= instr
->dest
.saturate
;
1139 case nir_op_fquantize2f16
: {
1140 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1141 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1142 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1144 /* The destination stride must be at least as big as the source stride. */
1145 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1148 /* Check for denormal */
1149 fs_reg abs_src0
= op
[0];
1150 abs_src0
.abs
= true;
1151 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1153 /* Get the appropriately signed zero */
1154 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1155 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1156 brw_imm_ud(0x80000000));
1157 /* Do the actual F32 -> F16 -> F32 conversion */
1158 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1159 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1160 /* Select that or zero based on normal status */
1161 inst
= bld
.SEL(result
, zero
, tmp32
);
1162 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1163 inst
->saturate
= instr
->dest
.saturate
;
1169 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1171 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1172 inst
->saturate
= instr
->dest
.saturate
;
1177 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1179 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1180 inst
->saturate
= instr
->dest
.saturate
;
1183 case nir_op_pack_snorm_2x16
:
1184 case nir_op_pack_snorm_4x8
:
1185 case nir_op_pack_unorm_2x16
:
1186 case nir_op_pack_unorm_4x8
:
1187 case nir_op_unpack_snorm_2x16
:
1188 case nir_op_unpack_snorm_4x8
:
1189 case nir_op_unpack_unorm_2x16
:
1190 case nir_op_unpack_unorm_4x8
:
1191 case nir_op_unpack_half_2x16
:
1192 case nir_op_pack_half_2x16
:
1193 unreachable("not reached: should be handled by lower_packing_builtins");
1195 case nir_op_unpack_half_2x16_split_x
:
1196 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1197 inst
->saturate
= instr
->dest
.saturate
;
1199 case nir_op_unpack_half_2x16_split_y
:
1200 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1201 inst
->saturate
= instr
->dest
.saturate
;
1204 case nir_op_pack_double_2x32_split
:
1205 /* Optimize the common case where we are re-packing a double with
1206 * the result of a previous double unpack. In this case we can take the
1207 * 32-bit value to use in the re-pack from the original double and bypass
1208 * the unpack operation.
1210 for (int i
= 0; i
< 2; i
++) {
1211 if (instr
->src
[i
].src
.is_ssa
)
1214 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1215 if (parent_instr
->type
== nir_instr_type_alu
)
1218 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1219 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1220 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1223 if (!alu_parent
->src
[0].src
.is_ssa
)
1226 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1227 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1228 alu_parent
->src
[0].swizzle
[channel
]);
1229 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1230 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1232 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1234 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1237 case nir_op_unpack_double_2x32_split_x
:
1238 case nir_op_unpack_double_2x32_split_y
: {
1239 /* Optimize the common case where we are unpacking from a double we have
1240 * previously packed. In this case we can just bypass the pack operation
1241 * and source directly from its arguments.
1243 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1244 if (instr
->src
[0].src
.is_ssa
) {
1245 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1246 if (parent_instr
->type
== nir_instr_type_alu
) {
1247 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1248 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1249 alu_parent
->src
[index
].src
.is_ssa
) {
1250 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1251 BRW_REGISTER_TYPE_UD
);
1253 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1254 bld
.MOV(result
, op
[0]);
1260 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1261 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1263 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1268 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1269 inst
->saturate
= instr
->dest
.saturate
;
1272 case nir_op_bitfield_reverse
:
1273 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1274 bld
.BFREV(result
, op
[0]);
1277 case nir_op_bit_count
:
1278 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1279 bld
.CBIT(result
, op
[0]);
1282 case nir_op_ufind_msb
: {
1283 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1284 emit_find_msb_using_lzd(bld
, result
, op
[0], false);
1288 case nir_op_ifind_msb
: {
1289 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1291 if (devinfo
->gen
< 7) {
1292 emit_find_msb_using_lzd(bld
, result
, op
[0], true);
1294 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1296 /* FBH counts from the MSB side, while GLSL's findMSB() wants the
1297 * count from the LSB side. If FBH didn't return an error
1298 * (0xFFFFFFFF), then subtract the result from 31 to convert the MSB
1299 * count into an LSB count.
1301 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1303 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1304 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1305 inst
->src
[0].negate
= true;
1310 case nir_op_find_lsb
:
1311 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1313 if (devinfo
->gen
< 7) {
1314 fs_reg temp
= vgrf(glsl_type::int_type
);
1316 /* (x & -x) generates a value that consists of only the LSB of x.
1317 * For all powers of 2, findMSB(y) == findLSB(y).
1319 fs_reg src
= retype(op
[0], BRW_REGISTER_TYPE_D
);
1320 fs_reg negated_src
= src
;
1322 /* One must be negated, and the other must be non-negated. It
1323 * doesn't matter which is which.
1325 negated_src
.negate
= true;
1328 bld
.AND(temp
, src
, negated_src
);
1329 emit_find_msb_using_lzd(bld
, result
, temp
, false);
1331 bld
.FBL(result
, op
[0]);
1335 case nir_op_ubitfield_extract
:
1336 case nir_op_ibitfield_extract
:
1337 unreachable("should have been lowered");
1340 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1341 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1344 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1345 bld
.BFI1(result
, op
[0], op
[1]);
1348 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1349 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1352 case nir_op_bitfield_insert
:
1353 unreachable("not reached: should have been lowered");
1356 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1357 bld
.SHL(result
, op
[0], op
[1]);
1360 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1361 bld
.ASR(result
, op
[0], op
[1]);
1364 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1365 bld
.SHR(result
, op
[0], op
[1]);
1368 case nir_op_pack_half_2x16_split
:
1369 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1373 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1374 inst
->saturate
= instr
->dest
.saturate
;
1378 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1379 inst
->saturate
= instr
->dest
.saturate
;
1383 if (optimize_frontfacing_ternary(instr
, result
))
1386 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1387 inst
= bld
.SEL(result
, op
[1], op
[2]);
1388 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1391 case nir_op_extract_u8
:
1392 case nir_op_extract_i8
: {
1393 const brw_reg_type type
= brw_int_type(1, instr
->op
== nir_op_extract_i8
);
1394 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1395 assert(byte
!= NULL
);
1396 bld
.MOV(result
, subscript(op
[0], type
, byte
->u32
[0]));
1400 case nir_op_extract_u16
:
1401 case nir_op_extract_i16
: {
1402 const brw_reg_type type
= brw_int_type(2, instr
->op
== nir_op_extract_i16
);
1403 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1404 assert(word
!= NULL
);
1405 bld
.MOV(result
, subscript(op
[0], type
, word
->u32
[0]));
1410 unreachable("unhandled instruction");
1413 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1414 * to sign extend the low bit to 0/~0
1416 if (devinfo
->gen
<= 5 &&
1417 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1418 fs_reg masked
= vgrf(glsl_type::int_type
);
1419 bld
.AND(masked
, result
, brw_imm_d(1));
1420 masked
.negate
= true;
1421 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1426 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1427 nir_load_const_instr
*instr
)
1429 const brw_reg_type reg_type
=
1430 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1431 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1433 switch (instr
->def
.bit_size
) {
1435 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1436 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1440 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1441 bld
.MOV(offset(reg
, bld
, i
),
1442 setup_imm_df(bld
, instr
->value
.f64
[i
]));
1446 unreachable("Invalid bit size");
1449 nir_ssa_values
[instr
->def
.index
] = reg
;
1453 fs_visitor::get_nir_src(const nir_src
&src
)
1457 if (src
.ssa
->parent_instr
->type
== nir_instr_type_ssa_undef
) {
1458 const brw_reg_type reg_type
= src
.ssa
->bit_size
== 32 ?
1459 BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1460 reg
= bld
.vgrf(reg_type
, src
.ssa
->num_components
);
1462 reg
= nir_ssa_values
[src
.ssa
->index
];
1465 /* We don't handle indirects on locals */
1466 assert(src
.reg
.indirect
== NULL
);
1467 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1468 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1471 /* to avoid floating-point denorm flushing problems, set the type by
1472 * default to D - instructions that need floating point semantics will set
1473 * this to F if they need to
1475 return retype(reg
, BRW_REGISTER_TYPE_D
);
1479 * Return an IMM for constants; otherwise call get_nir_src() as normal.
1482 fs_visitor::get_nir_src_imm(const nir_src
&src
)
1484 nir_const_value
*val
= nir_src_as_const_value(src
);
1485 return val
? fs_reg(brw_imm_d(val
->i32
[0])) : get_nir_src(src
);
1489 fs_visitor::get_nir_dest(const nir_dest
&dest
)
1492 const brw_reg_type reg_type
=
1493 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1494 nir_ssa_values
[dest
.ssa
.index
] =
1495 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1496 return nir_ssa_values
[dest
.ssa
.index
];
1498 /* We don't handle indirects on locals */
1499 assert(dest
.reg
.indirect
== NULL
);
1500 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1501 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1506 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1508 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1509 BRW_REGISTER_TYPE_UD
);
1511 unsigned indirect_max
= 0;
1513 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1514 tail
= tail
->child
) {
1515 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1516 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1517 const unsigned size
= glsl_get_length(tail
->type
);
1518 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1519 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1520 image
= offset(image
, bld
, base
* element_size
);
1522 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1523 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1525 /* Accessing an invalid surface index with the dataport can result
1526 * in a hang. According to the spec "if the index used to
1527 * select an individual element is negative or greater than or
1528 * equal to the size of the array, the results of the operation
1529 * are undefined but may not lead to termination" -- which is one
1530 * of the possible outcomes of the hang. Clamp the index to
1531 * prevent access outside of the array bounds.
1533 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1534 BRW_REGISTER_TYPE_UD
),
1535 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1537 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1539 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1540 if (indirect
.file
== BAD_FILE
) {
1543 bld
.ADD(indirect
, indirect
, tmp
);
1548 if (indirect
.file
== BAD_FILE
) {
1551 /* Emit a pile of MOVs to load the uniform into a temporary. The
1552 * dead-code elimination pass will get rid of what we don't use.
1554 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1555 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1556 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1557 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1558 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1565 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1568 for (unsigned i
= 0; i
< 4; i
++) {
1569 if (!((wr_mask
>> i
) & 1))
1572 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1573 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1574 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1575 if (new_inst
->src
[j
].file
== VGRF
)
1576 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1583 * Get the matching channel register datatype for an image intrinsic of the
1584 * specified GLSL image type.
1587 get_image_base_type(const glsl_type
*type
)
1589 switch ((glsl_base_type
)type
->sampled_type
) {
1590 case GLSL_TYPE_UINT
:
1591 return BRW_REGISTER_TYPE_UD
;
1593 return BRW_REGISTER_TYPE_D
;
1594 case GLSL_TYPE_FLOAT
:
1595 return BRW_REGISTER_TYPE_F
;
1597 unreachable("Not reached.");
1602 * Get the appropriate atomic op for an image atomic intrinsic.
1605 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1608 case nir_intrinsic_image_atomic_add
:
1610 case nir_intrinsic_image_atomic_min
:
1611 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1612 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1613 case nir_intrinsic_image_atomic_max
:
1614 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1615 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1616 case nir_intrinsic_image_atomic_and
:
1618 case nir_intrinsic_image_atomic_or
:
1620 case nir_intrinsic_image_atomic_xor
:
1622 case nir_intrinsic_image_atomic_exchange
:
1624 case nir_intrinsic_image_atomic_comp_swap
:
1625 return BRW_AOP_CMPWR
;
1627 unreachable("Not reachable.");
1632 emit_pixel_interpolater_send(const fs_builder
&bld
,
1637 glsl_interp_mode interpolation
)
1639 struct brw_wm_prog_data
*wm_prog_data
=
1640 brw_wm_prog_data(bld
.shader
->stage_prog_data
);
1645 if (src
.file
== BAD_FILE
) {
1647 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1651 mlen
= 2 * bld
.dispatch_width() / 8;
1654 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1656 /* 2 floats per slot returned */
1657 inst
->size_written
= 2 * dst
.component_size(inst
->exec_size
);
1658 inst
->pi_noperspective
= interpolation
== INTERP_MODE_NOPERSPECTIVE
;
1660 wm_prog_data
->pulls_bary
= true;
1666 * Computes 1 << x, given a D/UD register containing some value x.
1669 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1671 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1673 fs_reg result
= bld
.vgrf(x
.type
, 1);
1674 fs_reg one
= bld
.vgrf(x
.type
, 1);
1676 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1677 bld
.SHL(result
, one
, x
);
1682 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1684 assert(stage
== MESA_SHADER_GEOMETRY
);
1686 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1688 if (gs_compile
->control_data_header_size_bits
== 0)
1691 /* We can only do EndPrimitive() functionality when the control data
1692 * consists of cut bits. Fortunately, the only time it isn't is when the
1693 * output type is points, in which case EndPrimitive() is a no-op.
1695 if (gs_prog_data
->control_data_format
!=
1696 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1700 /* Cut bits use one bit per vertex. */
1701 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1703 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1704 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1706 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1707 * vertex n, 0 otherwise. So all we need to do here is mark bit
1708 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1709 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1710 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1712 * Note that if EndPrimitive() is called before emitting any vertices, this
1713 * will cause us to set bit 31 of the control_data_bits register to 1.
1714 * That's fine because:
1716 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1717 * output, so the hardware will ignore cut bit 31.
1719 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1720 * last vertex, so setting cut bit 31 has no effect (since the primitive
1721 * is automatically ended when the GS terminates).
1723 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1724 * control_data_bits register to 0 when the first vertex is emitted.
1727 const fs_builder abld
= bld
.annotate("end primitive");
1729 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1730 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1731 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1732 fs_reg mask
= intexp2(abld
, prev_count
);
1733 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1734 * attention to the lower 5 bits of its second source argument, so on this
1735 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1736 * ((vertex_count - 1) % 32).
1738 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1742 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1744 assert(stage
== MESA_SHADER_GEOMETRY
);
1745 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1747 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1749 const fs_builder abld
= bld
.annotate("emit control data bits");
1750 const fs_builder fwa_bld
= bld
.exec_all();
1752 /* We use a single UD register to accumulate control data bits (32 bits
1753 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1756 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1757 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1758 * use the Channel Mask phase to enable/disable which DWord within that
1759 * group to write. (Remember, different SIMD8 channels may have emitted
1760 * different numbers of vertices, so we may need per-slot offsets.)
1762 * Channel masking presents an annoying problem: we may have to replicate
1763 * the data up to 4 times:
1765 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1767 * To avoid penalizing shaders that emit a small number of vertices, we
1768 * can avoid these sometimes: if the size of the control data header is
1769 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1770 * land in the same 128-bit group, so we can skip per-slot offsets.
1772 * Similarly, if the control data header is <= 32 bits, there is only one
1773 * DWord, so we can skip channel masks.
1775 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1777 fs_reg channel_mask
, per_slot_offset
;
1779 if (gs_compile
->control_data_header_size_bits
> 32) {
1780 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1781 channel_mask
= vgrf(glsl_type::uint_type
);
1784 if (gs_compile
->control_data_header_size_bits
> 128) {
1785 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1786 per_slot_offset
= vgrf(glsl_type::uint_type
);
1789 /* Figure out which DWord we're trying to write to using the formula:
1791 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1793 * Since bits_per_vertex is a power of two, and is known at compile
1794 * time, this can be optimized to:
1796 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1798 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1799 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1800 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1801 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1802 unsigned log2_bits_per_vertex
=
1803 util_last_bit(gs_compile
->control_data_bits_per_vertex
);
1804 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1806 if (per_slot_offset
.file
!= BAD_FILE
) {
1807 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1808 * the appropriate OWord within the control data header.
1810 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1813 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1814 * write to the appropriate DWORD within the OWORD.
1816 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1817 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1818 channel_mask
= intexp2(fwa_bld
, channel
);
1819 /* Then the channel masks need to be in bits 23:16. */
1820 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1823 /* Store the control data bits in the message payload and send it. */
1825 if (channel_mask
.file
!= BAD_FILE
)
1826 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1827 if (per_slot_offset
.file
!= BAD_FILE
)
1830 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1831 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1833 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1834 if (per_slot_offset
.file
!= BAD_FILE
)
1835 sources
[i
++] = per_slot_offset
;
1836 if (channel_mask
.file
!= BAD_FILE
)
1837 sources
[i
++] = channel_mask
;
1839 sources
[i
++] = this->control_data_bits
;
1842 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1843 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1845 /* We need to increment Global Offset by 256-bits to make room for
1846 * Broadwell's extra "Vertex Count" payload at the beginning of the
1847 * URB entry. Since this is an OWord message, Global Offset is counted
1848 * in 128-bit units, so we must set it to 2.
1850 if (gs_prog_data
->static_vertex_count
== -1)
1855 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1858 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1860 /* Note: we are calling this *before* increasing vertex_count, so
1861 * this->vertex_count == vertex_count - 1 in the formula above.
1864 /* Stream mode uses 2 bits per vertex */
1865 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1867 /* Must be a valid stream */
1868 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1870 /* Control data bits are initialized to 0 so we don't have to set any
1871 * bits when sending vertices to stream 0.
1876 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1878 /* reg::sid = stream_id */
1879 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1880 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1882 /* reg:shift_count = 2 * (vertex_count - 1) */
1883 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1884 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1886 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1887 * attention to the lower 5 bits of its second source argument, so on this
1888 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1889 * stream_id << ((2 * (vertex_count - 1)) % 32).
1891 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1892 abld
.SHL(mask
, sid
, shift_count
);
1893 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1897 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1900 assert(stage
== MESA_SHADER_GEOMETRY
);
1902 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
1904 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1905 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1907 /* Haswell and later hardware ignores the "Render Stream Select" bits
1908 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1909 * and instead sends all primitives down the pipeline for rasterization.
1910 * If the SOL stage is enabled, "Render Stream Select" is honored and
1911 * primitives bound to non-zero streams are discarded after stream output.
1913 * Since the only purpose of primives sent to non-zero streams is to
1914 * be recorded by transform feedback, we can simply discard all geometry
1915 * bound to these streams when transform feedback is disabled.
1917 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1920 /* If we're outputting 32 control data bits or less, then we can wait
1921 * until the shader is over to output them all. Otherwise we need to
1922 * output them as we go. Now is the time to do it, since we're about to
1923 * output the vertex_count'th vertex, so it's guaranteed that the
1924 * control data bits associated with the (vertex_count - 1)th vertex are
1927 if (gs_compile
->control_data_header_size_bits
> 32) {
1928 const fs_builder abld
=
1929 bld
.annotate("emit vertex: emit control data bits");
1931 /* Only emit control data bits if we've finished accumulating a batch
1932 * of 32 bits. This is the case when:
1934 * (vertex_count * bits_per_vertex) % 32 == 0
1936 * (in other words, when the last 5 bits of vertex_count *
1937 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1938 * integer n (which is always the case, since bits_per_vertex is
1939 * always 1 or 2), this is equivalent to requiring that the last 5-n
1940 * bits of vertex_count are 0:
1942 * vertex_count & (2^(5-n) - 1) == 0
1944 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1947 * vertex_count & (32 / bits_per_vertex - 1) == 0
1949 * TODO: If vertex_count is an immediate, we could do some of this math
1950 * at compile time...
1953 abld
.AND(bld
.null_reg_d(), vertex_count
,
1954 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1955 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1957 abld
.IF(BRW_PREDICATE_NORMAL
);
1958 /* If vertex_count is 0, then no control data bits have been
1959 * accumulated yet, so we can skip emitting them.
1961 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1962 BRW_CONDITIONAL_NEQ
);
1963 abld
.IF(BRW_PREDICATE_NORMAL
);
1964 emit_gs_control_data_bits(vertex_count
);
1965 abld
.emit(BRW_OPCODE_ENDIF
);
1967 /* Reset control_data_bits to 0 so we can start accumulating a new
1970 * Note: in the case where vertex_count == 0, this neutralizes the
1971 * effect of any call to EndPrimitive() that the shader may have
1972 * made before outputting its first vertex.
1974 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1975 inst
->force_writemask_all
= true;
1976 abld
.emit(BRW_OPCODE_ENDIF
);
1979 emit_urb_writes(vertex_count
);
1981 /* In stream mode we have to set control data bits for all vertices
1982 * unless we have disabled control data bits completely (which we do
1983 * do for GL_POINTS outputs that don't use streams).
1985 if (gs_compile
->control_data_header_size_bits
> 0 &&
1986 gs_prog_data
->control_data_format
==
1987 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1988 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1993 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1994 const nir_src
&vertex_src
,
1995 unsigned base_offset
,
1996 const nir_src
&offset_src
,
1997 unsigned num_components
,
1998 unsigned first_component
)
2000 struct brw_gs_prog_data
*gs_prog_data
= brw_gs_prog_data(prog_data
);
2002 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2003 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
2004 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
2006 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
2007 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
2008 * gl_PointSize is available as a GS input, however, so it must be that.
2010 const bool is_point_size
= (base_offset
== 0);
2012 /* TODO: figure out push input layout for invocations == 1 */
2013 if (gs_prog_data
->invocations
== 1 &&
2014 offset_const
!= NULL
&& vertex_const
!= NULL
&&
2015 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
2016 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
2017 vertex_const
->u32
[0] * push_reg_count
;
2018 /* This input was pushed into registers. */
2019 if (is_point_size
) {
2020 /* gl_PointSize comes in .w */
2021 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2023 for (unsigned i
= 0; i
< num_components
; i
++) {
2024 bld
.MOV(offset(dst
, bld
, i
),
2025 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2031 /* Resort to the pull model. Ensure the VUE handles are provided. */
2032 gs_prog_data
->base
.include_vue_handles
= true;
2034 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2035 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2037 if (gs_prog_data
->invocations
== 1) {
2039 /* The vertex index is constant; just select the proper URB handle. */
2041 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2042 BRW_REGISTER_TYPE_UD
);
2044 /* The vertex index is non-constant. We need to use indirect
2045 * addressing to fetch the proper URB handle.
2047 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2048 * indicating that channel <n> should read the handle from
2049 * DWord <n>. We convert that to bytes by multiplying by 4.
2051 * Next, we convert the vertex index to bytes by multiplying
2052 * by 32 (shifting by 5), and add the two together. This is
2053 * the final indirect byte offset.
2055 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2056 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2057 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2058 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2060 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2061 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2062 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2063 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2064 /* Convert vertex_index to bytes (multiply by 32) */
2065 bld
.SHL(vertex_offset_bytes
,
2066 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2068 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2070 /* Use first_icp_handle as the base offset. There is one register
2071 * of URB handles per vertex, so inform the register allocator that
2072 * we might read up to nir->info.gs.vertices_in registers.
2074 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2075 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2076 fs_reg(icp_offset_bytes
),
2077 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2080 assert(gs_prog_data
->invocations
> 1);
2083 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2085 retype(brw_vec1_grf(first_icp_handle
+
2086 vertex_const
->i32
[0] / 8,
2087 vertex_const
->i32
[0] % 8),
2088 BRW_REGISTER_TYPE_UD
));
2090 /* The vertex index is non-constant. We need to use indirect
2091 * addressing to fetch the proper URB handle.
2094 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2096 /* Convert vertex_index to bytes (multiply by 4) */
2097 bld
.SHL(icp_offset_bytes
,
2098 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2101 /* Use first_icp_handle as the base offset. There is one DWord
2102 * of URB handles per vertex, so inform the register allocator that
2103 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2105 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2106 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2107 fs_reg(icp_offset_bytes
),
2108 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2115 fs_reg tmp_dst
= dst
;
2116 fs_reg indirect_offset
= get_nir_src(offset_src
);
2117 unsigned num_iterations
= 1;
2118 unsigned orig_num_components
= num_components
;
2120 if (type_sz(dst
.type
) == 8) {
2121 if (num_components
> 2) {
2125 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2127 first_component
= first_component
/ 2;
2130 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2132 /* Constant indexing - use global offset. */
2133 if (first_component
!= 0) {
2134 unsigned read_components
= num_components
+ first_component
;
2135 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2136 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2137 inst
->size_written
= read_components
*
2138 tmp
.component_size(inst
->exec_size
);
2139 for (unsigned i
= 0; i
< num_components
; i
++) {
2140 bld
.MOV(offset(tmp_dst
, bld
, i
),
2141 offset(tmp
, bld
, i
+ first_component
));
2144 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp_dst
,
2146 inst
->size_written
= num_components
*
2147 tmp_dst
.component_size(inst
->exec_size
);
2149 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2152 /* Indirect indexing - use per-slot offsets as well. */
2153 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2154 unsigned read_components
= num_components
+ first_component
;
2155 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2156 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2157 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2158 if (first_component
!= 0) {
2159 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2161 inst
->size_written
= read_components
*
2162 tmp
.component_size(inst
->exec_size
);
2163 for (unsigned i
= 0; i
< num_components
; i
++) {
2164 bld
.MOV(offset(tmp_dst
, bld
, i
),
2165 offset(tmp
, bld
, i
+ first_component
));
2168 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp_dst
,
2170 inst
->size_written
= num_components
*
2171 tmp_dst
.component_size(inst
->exec_size
);
2173 inst
->offset
= base_offset
;
2177 if (type_sz(dst
.type
) == 8) {
2178 shuffle_32bit_load_result_to_64bit_data(
2179 bld
, tmp_dst
, retype(tmp_dst
, BRW_REGISTER_TYPE_F
), num_components
);
2181 for (unsigned c
= 0; c
< num_components
; c
++)
2182 bld
.MOV(offset(dst
, bld
, iter
* 2 + c
), offset(tmp_dst
, bld
, c
));
2185 if (num_iterations
> 1) {
2186 num_components
= orig_num_components
- 2;
2190 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2191 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2192 indirect_offset
= new_indirect
;
2197 if (is_point_size
) {
2198 /* Read the whole VUE header (because of alignment) and read .w. */
2199 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2201 inst
->size_written
= 4 * REG_SIZE
;
2202 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2207 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2209 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2210 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2213 /* The only constant offset we should find is 0. brw_nir.c's
2214 * add_const_offset_to_base() will fold other constant offsets
2215 * into instr->const_index[0].
2217 assert(const_value
->u32
[0] == 0);
2221 return get_nir_src(*offset_src
);
2225 do_untyped_vector_read(const fs_builder
&bld
,
2227 const fs_reg surf_index
,
2228 const fs_reg offset_reg
,
2229 unsigned num_components
)
2231 if (type_sz(dest
.type
) == 4) {
2232 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2235 BRW_PREDICATE_NONE
);
2236 read_result
.type
= dest
.type
;
2237 for (unsigned i
= 0; i
< num_components
; i
++)
2238 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2239 } else if (type_sz(dest
.type
) == 8) {
2240 /* Reading a dvec, so we need to:
2242 * 1. Multiply num_components by 2, to account for the fact that we
2243 * need to read 64-bit components.
2244 * 2. Shuffle the result of the load to form valid 64-bit elements
2245 * 3. Emit a second load (for components z/w) if needed.
2247 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2248 bld
.MOV(read_offset
, offset_reg
);
2250 int iters
= num_components
<= 2 ? 1 : 2;
2252 /* Load the dvec, the first iteration loads components x/y, the second
2253 * iteration, if needed, loads components z/w
2255 for (int it
= 0; it
< iters
; it
++) {
2256 /* Compute number of components to read in this iteration */
2257 int iter_components
= MIN2(2, num_components
);
2258 num_components
-= iter_components
;
2260 /* Read. Since this message reads 32-bit components, we need to
2261 * read twice as many components.
2263 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2265 iter_components
* 2,
2266 BRW_PREDICATE_NONE
);
2268 /* Shuffle the 32-bit load result into valid 64-bit data */
2269 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2270 shuffle_32bit_load_result_to_64bit_data(
2271 bld
, packed_result
, read_result
, iter_components
);
2273 /* Move each component to its destination */
2274 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2275 for (int c
= 0; c
< iter_components
; c
++) {
2276 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2277 offset(packed_result
, bld
, c
));
2280 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2283 unreachable("Unsupported type");
2288 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2289 nir_intrinsic_instr
*instr
)
2291 assert(stage
== MESA_SHADER_VERTEX
);
2294 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2295 dest
= get_nir_dest(instr
->dest
);
2297 switch (instr
->intrinsic
) {
2298 case nir_intrinsic_load_vertex_id
:
2299 unreachable("should be lowered by lower_vertex_id()");
2301 case nir_intrinsic_load_vertex_id_zero_base
:
2302 case nir_intrinsic_load_base_vertex
:
2303 case nir_intrinsic_load_instance_id
:
2304 case nir_intrinsic_load_base_instance
:
2305 case nir_intrinsic_load_draw_id
: {
2306 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2307 fs_reg val
= nir_system_values
[sv
];
2308 assert(val
.file
!= BAD_FILE
);
2309 dest
.type
= val
.type
;
2314 case nir_intrinsic_load_input
: {
2315 fs_reg src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
2316 unsigned first_component
= nir_intrinsic_component(instr
);
2317 unsigned num_components
= instr
->num_components
;
2318 enum brw_reg_type type
= dest
.type
;
2320 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
2321 assert(const_offset
&& "Indirect input loads not allowed");
2322 src
= offset(src
, bld
, const_offset
->u32
[0]);
2324 for (unsigned j
= 0; j
< num_components
; j
++) {
2325 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
+ first_component
));
2328 if (type
== BRW_REGISTER_TYPE_DF
) {
2329 /* Once the double vector is read, set again its original register
2330 * type to continue with normal execution.
2332 src
= retype(src
, type
);
2333 dest
= retype(dest
, type
);
2336 if (type_sz(src
.type
) == 8) {
2337 shuffle_32bit_load_result_to_64bit_data(bld
,
2339 retype(dest
, BRW_REGISTER_TYPE_F
),
2340 instr
->num_components
);
2346 nir_emit_intrinsic(bld
, instr
);
2352 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2353 nir_intrinsic_instr
*instr
)
2355 assert(stage
== MESA_SHADER_TESS_CTRL
);
2356 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2357 struct brw_tcs_prog_data
*tcs_prog_data
= brw_tcs_prog_data(prog_data
);
2360 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2361 dst
= get_nir_dest(instr
->dest
);
2363 switch (instr
->intrinsic
) {
2364 case nir_intrinsic_load_primitive_id
:
2365 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2367 case nir_intrinsic_load_invocation_id
:
2368 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2370 case nir_intrinsic_load_patch_vertices_in
:
2371 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2372 brw_imm_d(tcs_key
->input_vertices
));
2375 case nir_intrinsic_barrier
: {
2376 if (tcs_prog_data
->instances
== 1)
2379 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2380 fs_reg m0_2
= component(m0
, 2);
2382 const fs_builder chanbld
= bld
.exec_all().group(1, 0);
2384 /* Zero the message header */
2385 bld
.exec_all().MOV(m0
, brw_imm_ud(0u));
2387 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2388 chanbld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2389 brw_imm_ud(INTEL_MASK(16, 13)));
2391 /* Shift it up to bits 27:24. */
2392 chanbld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2394 /* Set the Barrier Count and the enable bit */
2395 chanbld
.OR(m0_2
, m0_2
,
2396 brw_imm_ud(tcs_prog_data
->instances
<< 9 | (1 << 15)));
2398 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2402 case nir_intrinsic_load_input
:
2403 unreachable("nir_lower_io should never give us these.");
2406 case nir_intrinsic_load_per_vertex_input
: {
2407 fs_reg indirect_offset
= get_indirect_offset(instr
);
2408 unsigned imm_offset
= instr
->const_index
[0];
2410 const nir_src
&vertex_src
= instr
->src
[0];
2411 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2418 /* Emit a MOV to resolve <0,1,0> regioning. */
2419 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2421 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2422 vertex_const
->i32
[0] & 7),
2423 BRW_REGISTER_TYPE_UD
));
2424 } else if (tcs_prog_data
->instances
== 1 &&
2425 vertex_src
.is_ssa
&&
2426 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2427 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2428 /* For the common case of only 1 instance, an array index of
2429 * gl_InvocationID means reading g1. Skip all the indirect work.
2431 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2433 /* The vertex index is non-constant. We need to use indirect
2434 * addressing to fetch the proper URB handle.
2436 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2438 /* Each ICP handle is a single DWord (4 bytes) */
2439 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2440 bld
.SHL(vertex_offset_bytes
,
2441 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2444 /* Start at g1. We might read up to 4 registers. */
2445 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2446 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2447 brw_imm_ud(4 * REG_SIZE
));
2450 /* We can only read two double components with each URB read, so
2451 * we send two read messages in that case, each one loading up to
2452 * two double components.
2454 unsigned num_iterations
= 1;
2455 unsigned num_components
= instr
->num_components
;
2456 unsigned first_component
= nir_intrinsic_component(instr
);
2457 fs_reg orig_dst
= dst
;
2458 if (type_sz(dst
.type
) == 8) {
2459 first_component
= first_component
/ 2;
2460 if (instr
->num_components
> 2) {
2465 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2469 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2470 if (indirect_offset
.file
== BAD_FILE
) {
2471 /* Constant indexing - use global offset. */
2472 if (first_component
!= 0) {
2473 unsigned read_components
= num_components
+ first_component
;
2474 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2475 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, icp_handle
);
2476 for (unsigned i
= 0; i
< num_components
; i
++) {
2477 bld
.MOV(offset(dst
, bld
, i
),
2478 offset(tmp
, bld
, i
+ first_component
));
2481 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2483 inst
->offset
= imm_offset
;
2486 /* Indirect indexing - use per-slot offsets as well. */
2487 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2488 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2489 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2490 if (first_component
!= 0) {
2491 unsigned read_components
= num_components
+ first_component
;
2492 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2493 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2495 for (unsigned i
= 0; i
< num_components
; i
++) {
2496 bld
.MOV(offset(dst
, bld
, i
),
2497 offset(tmp
, bld
, i
+ first_component
));
2500 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2503 inst
->offset
= imm_offset
;
2506 inst
->size_written
= (num_components
+ first_component
) *
2507 inst
->dst
.component_size(inst
->exec_size
);
2509 /* If we are reading 64-bit data using 32-bit read messages we need
2510 * build proper 64-bit data elements by shuffling the low and high
2511 * 32-bit components around like we do for other things like UBOs
2514 if (type_sz(dst
.type
) == 8) {
2515 shuffle_32bit_load_result_to_64bit_data(
2516 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2518 for (unsigned c
= 0; c
< num_components
; c
++) {
2519 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2520 offset(dst
, bld
, c
));
2524 /* Copy the temporary to the destination to deal with writemasking.
2526 * Also attempt to deal with gl_PointSize being in the .w component.
2528 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2529 assert(type_sz(dst
.type
) < 8);
2530 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2531 inst
->size_written
= 4 * REG_SIZE
;
2532 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2535 /* If we are loading double data and we need a second read message
2536 * adjust the write offset
2538 if (num_iterations
> 1) {
2539 num_components
= instr
->num_components
- 2;
2546 case nir_intrinsic_load_output
:
2547 case nir_intrinsic_load_per_vertex_output
: {
2548 fs_reg indirect_offset
= get_indirect_offset(instr
);
2549 unsigned imm_offset
= instr
->const_index
[0];
2550 unsigned first_component
= nir_intrinsic_component(instr
);
2553 if (indirect_offset
.file
== BAD_FILE
) {
2554 /* Replicate the patch handle to all enabled channels */
2555 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2556 bld
.MOV(patch_handle
,
2557 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2559 if (imm_offset
== 0) {
2560 /* This is a read of gl_TessLevelInner[], which lives in the
2561 * Patch URB header. The layout depends on the domain.
2563 dst
.type
= BRW_REGISTER_TYPE_F
;
2564 switch (tcs_key
->tes_primitive_mode
) {
2566 /* DWords 3-2 (reversed) */
2567 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2569 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2572 inst
->size_written
= 4 * REG_SIZE
;
2574 /* dst.xy = tmp.wz */
2575 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2576 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2580 /* DWord 4; hardcode offset = 1 and size_written = REG_SIZE */
2581 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2584 inst
->size_written
= REG_SIZE
;
2587 /* All channels are undefined. */
2590 unreachable("Bogus tessellation domain");
2592 } else if (imm_offset
== 1) {
2593 /* This is a read of gl_TessLevelOuter[], which lives in the
2594 * Patch URB header. The layout depends on the domain.
2596 dst
.type
= BRW_REGISTER_TYPE_F
;
2598 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2599 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2602 inst
->size_written
= 4 * REG_SIZE
;
2604 /* Reswizzle: WZYX */
2606 offset(tmp
, bld
, 3),
2607 offset(tmp
, bld
, 2),
2608 offset(tmp
, bld
, 1),
2609 offset(tmp
, bld
, 0),
2612 unsigned num_components
;
2613 switch (tcs_key
->tes_primitive_mode
) {
2621 /* Isolines are not reversed; swizzle .zw -> .xy */
2622 srcs
[0] = offset(tmp
, bld
, 2);
2623 srcs
[1] = offset(tmp
, bld
, 3);
2627 unreachable("Bogus tessellation domain");
2629 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2631 if (first_component
!= 0) {
2632 unsigned read_components
=
2633 instr
->num_components
+ first_component
;
2634 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2635 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2637 inst
->size_written
= read_components
* REG_SIZE
;
2638 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2639 bld
.MOV(offset(dst
, bld
, i
),
2640 offset(tmp
, bld
, i
+ first_component
));
2643 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
,
2645 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2647 inst
->offset
= imm_offset
;
2651 /* Indirect indexing - use per-slot offsets as well. */
2652 const fs_reg srcs
[] = {
2653 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2656 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2657 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2658 if (first_component
!= 0) {
2659 unsigned read_components
=
2660 instr
->num_components
+ first_component
;
2661 fs_reg tmp
= bld
.vgrf(dst
.type
, read_components
);
2662 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
2664 inst
->size_written
= read_components
* REG_SIZE
;
2665 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2666 bld
.MOV(offset(dst
, bld
, i
),
2667 offset(tmp
, bld
, i
+ first_component
));
2670 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
,
2672 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2674 inst
->offset
= imm_offset
;
2680 case nir_intrinsic_store_output
:
2681 case nir_intrinsic_store_per_vertex_output
: {
2682 fs_reg value
= get_nir_src(instr
->src
[0]);
2683 bool is_64bit
= (instr
->src
[0].is_ssa
?
2684 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2685 fs_reg indirect_offset
= get_indirect_offset(instr
);
2686 unsigned imm_offset
= instr
->const_index
[0];
2687 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2688 unsigned mask
= instr
->const_index
[1];
2689 unsigned header_regs
= 0;
2691 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2693 if (indirect_offset
.file
!= BAD_FILE
) {
2694 srcs
[header_regs
++] = indirect_offset
;
2695 } else if (!is_passthrough_shader
) {
2696 if (imm_offset
== 0) {
2697 value
.type
= BRW_REGISTER_TYPE_F
;
2699 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2701 /* This is a write to gl_TessLevelInner[], which lives in the
2702 * Patch URB header. The layout depends on the domain.
2704 switch (tcs_key
->tes_primitive_mode
) {
2706 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2707 * We use an XXYX swizzle to reverse put .xy in the .wz
2708 * channels, and use a .zw writemask.
2710 mask
= writemask_for_backwards_vector(mask
);
2711 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2714 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2715 * writemask to X and bump the URB offset by 1.
2720 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2723 unreachable("Bogus tessellation domain");
2725 } else if (imm_offset
== 1) {
2726 /* This is a write to gl_TessLevelOuter[] which lives in the
2727 * Patch URB Header at DWords 4-7. However, it's reversed, so
2728 * instead of .xyzw we have .wzyx.
2730 value
.type
= BRW_REGISTER_TYPE_F
;
2732 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2734 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2735 /* Isolines .xy should be stored in .zw, in order. */
2736 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2739 /* Other domains are reversed; store .wzyx instead of .xyzw */
2740 swiz
= BRW_SWIZZLE_WZYX
;
2741 mask
= writemask_for_backwards_vector(mask
);
2749 unsigned num_components
= util_last_bit(mask
);
2752 /* We can only pack two 64-bit components in a single message, so send
2753 * 2 messages if we have more components
2755 unsigned num_iterations
= 1;
2756 unsigned iter_components
= num_components
;
2757 unsigned first_component
= nir_intrinsic_component(instr
);
2759 first_component
= first_component
/ 2;
2760 if (instr
->num_components
> 2) {
2762 iter_components
= 2;
2766 /* 64-bit data needs to me shuffled before we can write it to the URB.
2767 * We will use this temporary to shuffle the components in each
2771 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2773 mask
= mask
<< first_component
;
2775 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2776 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2777 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2778 opcode
= indirect_offset
.file
!= BAD_FILE
?
2779 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2780 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2781 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2782 /* Expand the 64-bit mask to 32-bit channels. We only handle
2783 * two channels in each iteration, so we only care about X/Y.
2785 unsigned mask32
= 0;
2786 if (mask
& WRITEMASK_X
)
2787 mask32
|= WRITEMASK_XY
;
2788 if (mask
& WRITEMASK_Y
)
2789 mask32
|= WRITEMASK_ZW
;
2791 /* If the mask does not include any of the channels X or Y there
2792 * is nothing to do in this iteration. Move on to the next couple
2793 * of 64-bit channels.
2801 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2802 opcode
= indirect_offset
.file
!= BAD_FILE
?
2803 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2804 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2806 opcode
= indirect_offset
.file
!= BAD_FILE
?
2807 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2808 SHADER_OPCODE_URB_WRITE_SIMD8
;
2811 for (unsigned i
= 0; i
< iter_components
; i
++) {
2812 if (!(mask
& (1 << (i
+ first_component
))))
2816 srcs
[header_regs
+ i
+ first_component
] =
2817 offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2819 /* We need to shuffle the 64-bit data to match the layout
2820 * expected by our 32-bit URB write messages. We use a temporary
2823 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2824 shuffle_64bit_data_for_32bit_write(bld
,
2825 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2826 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2829 /* Now copy the data to the destination */
2830 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2831 unsigned idx
= 2 * i
;
2832 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2833 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2834 srcs
[header_regs
+ idx
+ first_component
* 2] = dest
;
2835 srcs
[header_regs
+ idx
+ 1 + first_component
* 2] =
2836 offset(dest
, bld
, 1);
2841 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
) +
2842 (is_64bit
? 2 * first_component
: first_component
);
2844 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2845 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2847 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2848 inst
->offset
= imm_offset
;
2851 /* If this is a 64-bit attribute, select the next two 64-bit channels
2852 * to be handled in the next iteration.
2863 nir_emit_intrinsic(bld
, instr
);
2869 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2870 nir_intrinsic_instr
*instr
)
2872 assert(stage
== MESA_SHADER_TESS_EVAL
);
2873 struct brw_tes_prog_data
*tes_prog_data
= brw_tes_prog_data(prog_data
);
2876 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2877 dest
= get_nir_dest(instr
->dest
);
2879 switch (instr
->intrinsic
) {
2880 case nir_intrinsic_load_primitive_id
:
2881 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2883 case nir_intrinsic_load_tess_coord
:
2884 /* gl_TessCoord is part of the payload in g1-3 */
2885 for (unsigned i
= 0; i
< 3; i
++) {
2886 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2890 case nir_intrinsic_load_tess_level_outer
:
2891 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2892 * appears as a push-model input. So, we can simply use the ATTR file
2893 * rather than issuing URB read messages. The data is stored in the
2894 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2897 switch (tes_prog_data
->domain
) {
2898 case BRW_TESS_DOMAIN_QUAD
:
2899 for (unsigned i
= 0; i
< 4; i
++)
2900 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2902 case BRW_TESS_DOMAIN_TRI
:
2903 for (unsigned i
= 0; i
< 3; i
++)
2904 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2906 case BRW_TESS_DOMAIN_ISOLINE
:
2907 for (unsigned i
= 0; i
< 2; i
++)
2908 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 6 + i
));
2913 case nir_intrinsic_load_tess_level_inner
:
2914 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2915 * appears as a push-model input. So, we can simply use the ATTR file
2916 * rather than issuing URB read messages.
2918 switch (tes_prog_data
->domain
) {
2919 case BRW_TESS_DOMAIN_QUAD
:
2920 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2921 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2923 case BRW_TESS_DOMAIN_TRI
:
2924 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2926 case BRW_TESS_DOMAIN_ISOLINE
:
2927 /* ignore - value is undefined */
2932 case nir_intrinsic_load_input
:
2933 case nir_intrinsic_load_per_vertex_input
: {
2934 fs_reg indirect_offset
= get_indirect_offset(instr
);
2935 unsigned imm_offset
= instr
->const_index
[0];
2936 unsigned first_component
= nir_intrinsic_component(instr
);
2938 if (type_sz(dest
.type
) == 8) {
2939 first_component
= first_component
/ 2;
2943 if (indirect_offset
.file
== BAD_FILE
) {
2944 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2945 * which is 16 registers (since each holds 2 vec4 slots).
2947 const unsigned max_push_slots
= 32;
2948 if (imm_offset
< max_push_slots
) {
2949 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2950 for (int i
= 0; i
< instr
->num_components
; i
++) {
2951 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) +
2952 i
+ first_component
;
2953 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2955 tes_prog_data
->base
.urb_read_length
=
2956 MAX2(tes_prog_data
->base
.urb_read_length
,
2957 DIV_ROUND_UP(imm_offset
+ 1, 2));
2959 /* Replicate the patch handle to all enabled channels */
2960 const fs_reg srcs
[] = {
2961 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2963 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2964 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2966 if (first_component
!= 0) {
2967 unsigned read_components
=
2968 instr
->num_components
+ first_component
;
2969 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
2970 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
,
2972 inst
->size_written
= read_components
* REG_SIZE
;
2973 for (unsigned i
= 0; i
< instr
->num_components
; i
++) {
2974 bld
.MOV(offset(dest
, bld
, i
),
2975 offset(tmp
, bld
, i
+ first_component
));
2978 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
,
2980 inst
->size_written
= instr
->num_components
* REG_SIZE
;
2983 inst
->offset
= imm_offset
;
2986 /* Indirect indexing - use per-slot offsets as well. */
2988 /* We can only read two double components with each URB read, so
2989 * we send two read messages in that case, each one loading up to
2990 * two double components.
2992 unsigned num_iterations
= 1;
2993 unsigned num_components
= instr
->num_components
;
2994 fs_reg orig_dest
= dest
;
2995 if (type_sz(dest
.type
) == 8) {
2996 if (instr
->num_components
> 2) {
3000 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dest
.type
);
3004 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
3005 const fs_reg srcs
[] = {
3006 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
3009 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3010 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
3012 if (first_component
!= 0) {
3013 unsigned read_components
=
3014 num_components
+ first_component
;
3015 fs_reg tmp
= bld
.vgrf(dest
.type
, read_components
);
3016 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, tmp
,
3018 for (unsigned i
= 0; i
< num_components
; i
++) {
3019 bld
.MOV(offset(dest
, bld
, i
),
3020 offset(tmp
, bld
, i
+ first_component
));
3023 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
,
3027 inst
->offset
= imm_offset
;
3028 inst
->size_written
= (num_components
+ first_component
) *
3029 inst
->dst
.component_size(inst
->exec_size
);
3031 /* If we are reading 64-bit data using 32-bit read messages we need
3032 * build proper 64-bit data elements by shuffling the low and high
3033 * 32-bit components around like we do for other things like UBOs
3036 if (type_sz(dest
.type
) == 8) {
3037 shuffle_32bit_load_result_to_64bit_data(
3038 bld
, dest
, retype(dest
, BRW_REGISTER_TYPE_F
), num_components
);
3040 for (unsigned c
= 0; c
< num_components
; c
++) {
3041 bld
.MOV(offset(orig_dest
, bld
, iter
* 2 + c
),
3042 offset(dest
, bld
, c
));
3046 /* If we are loading double data and we need a second read message
3049 if (num_iterations
> 1) {
3050 num_components
= instr
->num_components
- 2;
3058 nir_emit_intrinsic(bld
, instr
);
3064 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
3065 nir_intrinsic_instr
*instr
)
3067 assert(stage
== MESA_SHADER_GEOMETRY
);
3068 fs_reg indirect_offset
;
3071 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3072 dest
= get_nir_dest(instr
->dest
);
3074 switch (instr
->intrinsic
) {
3075 case nir_intrinsic_load_primitive_id
:
3076 assert(stage
== MESA_SHADER_GEOMETRY
);
3077 assert(brw_gs_prog_data(prog_data
)->include_primitive_id
);
3078 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
3079 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
3082 case nir_intrinsic_load_input
:
3083 unreachable("load_input intrinsics are invalid for the GS stage");
3085 case nir_intrinsic_load_per_vertex_input
:
3086 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
3087 instr
->src
[1], instr
->num_components
,
3088 nir_intrinsic_component(instr
));
3091 case nir_intrinsic_emit_vertex_with_counter
:
3092 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
3095 case nir_intrinsic_end_primitive_with_counter
:
3096 emit_gs_end_primitive(instr
->src
[0]);
3099 case nir_intrinsic_set_vertex_count
:
3100 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
3103 case nir_intrinsic_load_invocation_id
: {
3104 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
3105 assert(val
.file
!= BAD_FILE
);
3106 dest
.type
= val
.type
;
3112 nir_emit_intrinsic(bld
, instr
);
3118 * Fetch the current render target layer index.
3121 fetch_render_target_array_index(const fs_builder
&bld
)
3123 if (bld
.shader
->devinfo
->gen
>= 6) {
3124 /* The render target array index is provided in the thread payload as
3125 * bits 26:16 of r0.0.
3127 const fs_reg idx
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
3128 bld
.AND(idx
, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE
, 0, 1),
3132 /* Pre-SNB we only ever render into the first layer of the framebuffer
3133 * since layered rendering is not implemented.
3135 return brw_imm_ud(0);
3140 * Fake non-coherent framebuffer read implemented using TXF to fetch from the
3141 * framebuffer at the current fragment coordinates and sample index.
3144 fs_visitor::emit_non_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
,
3147 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
3149 assert(bld
.shader
->stage
== MESA_SHADER_FRAGMENT
);
3150 const brw_wm_prog_key
*wm_key
=
3151 reinterpret_cast<const brw_wm_prog_key
*>(key
);
3152 assert(!wm_key
->coherent_fb_fetch
);
3153 const struct brw_wm_prog_data
*wm_prog_data
=
3154 brw_wm_prog_data(stage_prog_data
);
3156 /* Calculate the surface index relative to the start of the texture binding
3157 * table block, since that's what the texturing messages expect.
3159 const unsigned surface
= target
+
3160 wm_prog_data
->binding_table
.render_target_read_start
-
3161 wm_prog_data
->base
.binding_table
.texture_start
;
3163 brw_mark_surface_used(
3164 bld
.shader
->stage_prog_data
,
3165 wm_prog_data
->binding_table
.render_target_read_start
+ target
);
3167 /* Calculate the fragment coordinates. */
3168 const fs_reg coords
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 3);
3169 bld
.MOV(offset(coords
, bld
, 0), pixel_x
);
3170 bld
.MOV(offset(coords
, bld
, 1), pixel_y
);
3171 bld
.MOV(offset(coords
, bld
, 2), fetch_render_target_array_index(bld
));
3173 /* Calculate the sample index and MCS payload when multisampling. Luckily
3174 * the MCS fetch message behaves deterministically for UMS surfaces, so it
3175 * shouldn't be necessary to recompile based on whether the framebuffer is
3178 if (wm_key
->multisample_fbo
&&
3179 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
].file
== BAD_FILE
)
3180 nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
] = *emit_sampleid_setup();
3182 const fs_reg sample
= nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
3183 const fs_reg mcs
= wm_key
->multisample_fbo
?
3184 emit_mcs_fetch(coords
, 3, brw_imm_ud(surface
)) : fs_reg();
3186 /* Use either a normal or a CMS texel fetch message depending on whether
3187 * the framebuffer is single or multisample. On SKL+ use the wide CMS
3188 * message just in case the framebuffer uses 16x multisampling, it should
3189 * be equivalent to the normal CMS fetch for lower multisampling modes.
3191 const opcode op
= !wm_key
->multisample_fbo
? SHADER_OPCODE_TXF_LOGICAL
:
3192 devinfo
->gen
>= 9 ? SHADER_OPCODE_TXF_CMS_W_LOGICAL
:
3193 SHADER_OPCODE_TXF_CMS_LOGICAL
;
3195 /* Emit the instruction. */
3196 const fs_reg srcs
[] = { coords
, fs_reg(), brw_imm_ud(0), fs_reg(),
3198 brw_imm_ud(surface
), brw_imm_ud(0),
3199 fs_reg(), brw_imm_ud(3), brw_imm_ud(0) };
3200 STATIC_ASSERT(ARRAY_SIZE(srcs
) == TEX_LOGICAL_NUM_SRCS
);
3202 fs_inst
*inst
= bld
.emit(op
, dst
, srcs
, ARRAY_SIZE(srcs
));
3203 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3209 * Actual coherent framebuffer read implemented using the native render target
3210 * read message. Requires SKL+.
3213 emit_coherent_fb_read(const fs_builder
&bld
, const fs_reg
&dst
, unsigned target
)
3215 assert(bld
.shader
->devinfo
->gen
>= 9);
3216 fs_inst
*inst
= bld
.emit(FS_OPCODE_FB_READ_LOGICAL
, dst
);
3217 inst
->target
= target
;
3218 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
3224 alloc_temporary(const fs_builder
&bld
, unsigned size
, fs_reg
*regs
, unsigned n
)
3226 if (n
&& regs
[0].file
!= BAD_FILE
) {
3230 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, size
);
3232 for (unsigned i
= 0; i
< n
; i
++)
3240 alloc_frag_output(fs_visitor
*v
, unsigned location
)
3242 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
3243 const brw_wm_prog_key
*const key
=
3244 reinterpret_cast<const brw_wm_prog_key
*>(v
->key
);
3245 const unsigned l
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_LOCATION
);
3246 const unsigned i
= GET_FIELD(location
, BRW_NIR_FRAG_OUTPUT_INDEX
);
3248 if (i
> 0 || (key
->force_dual_color_blend
&& l
== FRAG_RESULT_DATA1
))
3249 return alloc_temporary(v
->bld
, 4, &v
->dual_src_output
, 1);
3251 else if (l
== FRAG_RESULT_COLOR
)
3252 return alloc_temporary(v
->bld
, 4, v
->outputs
,
3253 MAX2(key
->nr_color_regions
, 1));
3255 else if (l
== FRAG_RESULT_DEPTH
)
3256 return alloc_temporary(v
->bld
, 1, &v
->frag_depth
, 1);
3258 else if (l
== FRAG_RESULT_STENCIL
)
3259 return alloc_temporary(v
->bld
, 1, &v
->frag_stencil
, 1);
3261 else if (l
== FRAG_RESULT_SAMPLE_MASK
)
3262 return alloc_temporary(v
->bld
, 1, &v
->sample_mask
, 1);
3264 else if (l
>= FRAG_RESULT_DATA0
&&
3265 l
< FRAG_RESULT_DATA0
+ BRW_MAX_DRAW_BUFFERS
)
3266 return alloc_temporary(v
->bld
, 4,
3267 &v
->outputs
[l
- FRAG_RESULT_DATA0
], 1);
3270 unreachable("Invalid location");
3274 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
3275 nir_intrinsic_instr
*instr
)
3277 assert(stage
== MESA_SHADER_FRAGMENT
);
3280 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3281 dest
= get_nir_dest(instr
->dest
);
3283 switch (instr
->intrinsic
) {
3284 case nir_intrinsic_load_front_face
:
3285 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
3286 *emit_frontfacing_interpolation());
3289 case nir_intrinsic_load_sample_pos
: {
3290 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
3291 assert(sample_pos
.file
!= BAD_FILE
);
3292 dest
.type
= sample_pos
.type
;
3293 bld
.MOV(dest
, sample_pos
);
3294 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
3298 case nir_intrinsic_load_helper_invocation
:
3299 case nir_intrinsic_load_sample_mask_in
:
3300 case nir_intrinsic_load_sample_id
: {
3301 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3302 fs_reg val
= nir_system_values
[sv
];
3303 assert(val
.file
!= BAD_FILE
);
3304 dest
.type
= val
.type
;
3309 case nir_intrinsic_store_output
: {
3310 const fs_reg src
= get_nir_src(instr
->src
[0]);
3311 const nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3312 assert(const_offset
&& "Indirect output stores not allowed");
3313 const unsigned location
= nir_intrinsic_base(instr
) +
3314 SET_FIELD(const_offset
->u32
[0], BRW_NIR_FRAG_OUTPUT_LOCATION
);
3315 const fs_reg new_dest
= retype(alloc_frag_output(this, location
),
3318 for (unsigned j
= 0; j
< instr
->num_components
; j
++)
3319 bld
.MOV(offset(new_dest
, bld
, nir_intrinsic_component(instr
) + j
),
3320 offset(src
, bld
, j
));
3325 case nir_intrinsic_load_output
: {
3326 const unsigned l
= GET_FIELD(nir_intrinsic_base(instr
),
3327 BRW_NIR_FRAG_OUTPUT_LOCATION
);
3328 assert(l
>= FRAG_RESULT_DATA0
);
3329 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3330 assert(const_offset
&& "Indirect output loads not allowed");
3331 const unsigned target
= l
- FRAG_RESULT_DATA0
+ const_offset
->u32
[0];
3332 const fs_reg tmp
= bld
.vgrf(dest
.type
, 4);
3334 if (reinterpret_cast<const brw_wm_prog_key
*>(key
)->coherent_fb_fetch
)
3335 emit_coherent_fb_read(bld
, tmp
, target
);
3337 emit_non_coherent_fb_read(bld
, tmp
, target
);
3339 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3340 bld
.MOV(offset(dest
, bld
, j
),
3341 offset(tmp
, bld
, nir_intrinsic_component(instr
) + j
));
3347 case nir_intrinsic_discard
:
3348 case nir_intrinsic_discard_if
: {
3349 /* We track our discarded pixels in f0.1. By predicating on it, we can
3350 * update just the flag bits that aren't yet discarded. If there's no
3351 * condition, we emit a CMP of g0 != g0, so all currently executing
3352 * channels will get turned off.
3355 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
3356 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
3357 brw_imm_d(0), BRW_CONDITIONAL_Z
);
3359 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
3360 BRW_REGISTER_TYPE_UW
));
3361 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
3363 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
3364 cmp
->flag_subreg
= 1;
3366 if (devinfo
->gen
>= 6) {
3367 emit_discard_jump();
3372 case nir_intrinsic_load_input
: {
3373 /* load_input is only used for flat inputs */
3374 unsigned base
= nir_intrinsic_base(instr
);
3375 unsigned component
= nir_intrinsic_component(instr
);
3376 unsigned num_components
= instr
->num_components
;
3377 enum brw_reg_type type
= dest
.type
;
3379 /* Special case fields in the VUE header */
3380 if (base
== VARYING_SLOT_LAYER
)
3382 else if (base
== VARYING_SLOT_VIEWPORT
)
3385 if (nir_dest_bit_size(instr
->dest
) == 64) {
3386 /* const_index is in 32-bit type size units that could not be aligned
3387 * with DF. We need to read the double vector as if it was a float
3388 * vector of twice the number of components to fetch the right data.
3390 type
= BRW_REGISTER_TYPE_F
;
3391 num_components
*= 2;
3394 for (unsigned int i
= 0; i
< num_components
; i
++) {
3395 struct brw_reg interp
= interp_reg(base
, component
+ i
);
3396 interp
= suboffset(interp
, 3);
3397 bld
.emit(FS_OPCODE_CINTERP
, offset(retype(dest
, type
), bld
, i
),
3398 retype(fs_reg(interp
), type
));
3401 if (nir_dest_bit_size(instr
->dest
) == 64) {
3402 shuffle_32bit_load_result_to_64bit_data(bld
,
3405 instr
->num_components
);
3410 case nir_intrinsic_load_barycentric_pixel
:
3411 case nir_intrinsic_load_barycentric_centroid
:
3412 case nir_intrinsic_load_barycentric_sample
:
3413 /* Do nothing - load_interpolated_input handling will handle it later. */
3416 case nir_intrinsic_load_barycentric_at_sample
: {
3417 const glsl_interp_mode interpolation
=
3418 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3420 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
3423 unsigned msg_data
= const_sample
->i32
[0] << 4;
3425 emit_pixel_interpolater_send(bld
,
3426 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3429 brw_imm_ud(msg_data
),
3432 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3433 BRW_REGISTER_TYPE_UD
);
3435 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3436 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3437 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3438 bld
.exec_all().group(1, 0)
3439 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3440 emit_pixel_interpolater_send(bld
,
3441 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3447 /* Make a loop that sends a message to the pixel interpolater
3448 * for the sample number in each live channel. If there are
3449 * multiple channels with the same sample number then these
3450 * will be handled simultaneously with a single interation of
3453 bld
.emit(BRW_OPCODE_DO
);
3455 /* Get the next live sample number into sample_id_reg */
3456 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3458 /* Set the flag register so that we can perform the send
3459 * message on all channels that have the same sample number
3461 bld
.CMP(bld
.null_reg_ud(),
3462 sample_src
, sample_id
,
3463 BRW_CONDITIONAL_EQ
);
3464 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3465 bld
.exec_all().group(1, 0)
3466 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3468 emit_pixel_interpolater_send(bld
,
3469 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3474 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3476 /* Continue the loop if there are any live channels left */
3477 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3479 bld
.emit(BRW_OPCODE_WHILE
));
3485 case nir_intrinsic_load_barycentric_at_offset
: {
3486 const glsl_interp_mode interpolation
=
3487 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(instr
);
3489 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3492 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3493 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16), 7) & 0xf;
3495 emit_pixel_interpolater_send(bld
,
3496 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3499 brw_imm_ud(off_x
| (off_y
<< 4)),
3502 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3503 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3504 BRW_REGISTER_TYPE_F
);
3505 for (int i
= 0; i
< 2; i
++) {
3506 fs_reg temp
= vgrf(glsl_type::float_type
);
3507 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3508 fs_reg itemp
= vgrf(glsl_type::int_type
);
3510 bld
.MOV(itemp
, temp
);
3512 /* Clamp the upper end of the range to +7/16.
3513 * ARB_gpu_shader5 requires that we support a maximum offset
3514 * of +0.5, which isn't representable in a S0.4 value -- if
3515 * we didn't clamp it, we'd end up with -8/16, which is the
3516 * opposite of what the shader author wanted.
3518 * This is legal due to ARB_gpu_shader5's quantization
3521 * "Not all values of <offset> may be supported; x and y
3522 * offsets may be rounded to fixed-point values with the
3523 * number of fraction bits given by the
3524 * implementation-dependent constant
3525 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3527 set_condmod(BRW_CONDITIONAL_L
,
3528 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3531 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3532 emit_pixel_interpolater_send(bld
,
3542 case nir_intrinsic_load_interpolated_input
: {
3543 if (nir_intrinsic_base(instr
) == VARYING_SLOT_POS
) {
3544 emit_fragcoord_interpolation(dest
);
3548 assert(instr
->src
[0].ssa
&&
3549 instr
->src
[0].ssa
->parent_instr
->type
== nir_instr_type_intrinsic
);
3550 nir_intrinsic_instr
*bary_intrinsic
=
3551 nir_instr_as_intrinsic(instr
->src
[0].ssa
->parent_instr
);
3552 nir_intrinsic_op bary_intrin
= bary_intrinsic
->intrinsic
;
3553 enum glsl_interp_mode interp_mode
=
3554 (enum glsl_interp_mode
) nir_intrinsic_interp_mode(bary_intrinsic
);
3557 if (bary_intrin
== nir_intrinsic_load_barycentric_at_offset
||
3558 bary_intrin
== nir_intrinsic_load_barycentric_at_sample
) {
3559 /* Use the result of the PI message */
3560 dst_xy
= retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_F
);
3562 /* Use the delta_xy values computed from the payload */
3563 enum brw_barycentric_mode bary
=
3564 brw_barycentric_mode(interp_mode
, bary_intrin
);
3566 dst_xy
= this->delta_xy
[bary
];
3569 for (unsigned int i
= 0; i
< instr
->num_components
; i
++) {
3571 fs_reg(interp_reg(nir_intrinsic_base(instr
),
3572 nir_intrinsic_component(instr
) + i
));
3573 interp
.type
= BRW_REGISTER_TYPE_F
;
3574 dest
.type
= BRW_REGISTER_TYPE_F
;
3576 if (devinfo
->gen
< 6 && interp_mode
== INTERP_MODE_SMOOTH
) {
3577 fs_reg tmp
= vgrf(glsl_type::float_type
);
3578 bld
.emit(FS_OPCODE_LINTERP
, tmp
, dst_xy
, interp
);
3579 bld
.MUL(offset(dest
, bld
, i
), tmp
, this->pixel_w
);
3581 bld
.emit(FS_OPCODE_LINTERP
, offset(dest
, bld
, i
), dst_xy
, interp
);
3588 nir_emit_intrinsic(bld
, instr
);
3594 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3595 nir_intrinsic_instr
*instr
)
3597 assert(stage
== MESA_SHADER_COMPUTE
);
3598 struct brw_cs_prog_data
*cs_prog_data
= brw_cs_prog_data(prog_data
);
3601 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3602 dest
= get_nir_dest(instr
->dest
);
3604 switch (instr
->intrinsic
) {
3605 case nir_intrinsic_barrier
:
3607 cs_prog_data
->uses_barrier
= true;
3610 case nir_intrinsic_load_local_invocation_id
:
3611 case nir_intrinsic_load_work_group_id
: {
3612 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3613 fs_reg val
= nir_system_values
[sv
];
3614 assert(val
.file
!= BAD_FILE
);
3615 dest
.type
= val
.type
;
3616 for (unsigned i
= 0; i
< 3; i
++)
3617 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3621 case nir_intrinsic_load_num_work_groups
: {
3622 const unsigned surface
=
3623 cs_prog_data
->binding_table
.work_groups_start
;
3625 cs_prog_data
->uses_num_work_groups
= true;
3627 fs_reg surf_index
= brw_imm_ud(surface
);
3628 brw_mark_surface_used(prog_data
, surface
);
3630 /* Read the 3 GLuint components of gl_NumWorkGroups */
3631 for (unsigned i
= 0; i
< 3; i
++) {
3632 fs_reg read_result
=
3633 emit_untyped_read(bld
, surf_index
,
3635 1 /* dims */, 1 /* size */,
3636 BRW_PREDICATE_NONE
);
3637 read_result
.type
= dest
.type
;
3638 bld
.MOV(dest
, read_result
);
3639 dest
= offset(dest
, bld
, 1);
3644 case nir_intrinsic_shared_atomic_add
:
3645 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3647 case nir_intrinsic_shared_atomic_imin
:
3648 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3650 case nir_intrinsic_shared_atomic_umin
:
3651 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3653 case nir_intrinsic_shared_atomic_imax
:
3654 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3656 case nir_intrinsic_shared_atomic_umax
:
3657 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3659 case nir_intrinsic_shared_atomic_and
:
3660 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3662 case nir_intrinsic_shared_atomic_or
:
3663 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3665 case nir_intrinsic_shared_atomic_xor
:
3666 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3668 case nir_intrinsic_shared_atomic_exchange
:
3669 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3671 case nir_intrinsic_shared_atomic_comp_swap
:
3672 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3675 case nir_intrinsic_load_shared
: {
3676 assert(devinfo
->gen
>= 7);
3678 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3680 /* Get the offset to read from */
3682 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3684 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3686 offset_reg
= vgrf(glsl_type::uint_type
);
3688 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3689 brw_imm_ud(instr
->const_index
[0]));
3692 /* Read the vector */
3693 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3694 instr
->num_components
);
3698 case nir_intrinsic_store_shared
: {
3699 assert(devinfo
->gen
>= 7);
3702 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3705 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3708 unsigned writemask
= instr
->const_index
[1];
3710 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3711 * since the untyped writes below operate in units of 32-bits, which
3712 * means that we need to write twice as many components each time.
3713 * Also, we have to suffle 64-bit data to be in the appropriate layout
3714 * expected by our 32-bit write messages.
3716 unsigned type_size
= 4;
3717 unsigned bit_size
= instr
->src
[0].is_ssa
?
3718 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3719 if (bit_size
== 64) {
3722 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3723 shuffle_64bit_data_for_32bit_write(
3725 retype(tmp
, BRW_REGISTER_TYPE_F
),
3726 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3727 instr
->num_components
);
3731 unsigned type_slots
= type_size
/ 4;
3733 /* Combine groups of consecutive enabled channels in one write
3734 * message. We use ffs to find the first enabled channel and then ffs on
3735 * the bit-inverse, down-shifted writemask to determine the length of
3736 * the block of enabled bits.
3739 unsigned first_component
= ffs(writemask
) - 1;
3740 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3742 /* We can't write more than 2 64-bit components at once. Limit the
3743 * length of the write to what we can do and let the next iteration
3747 length
= MIN2(2, length
);
3750 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3752 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3753 type_size
* first_component
);
3755 offset_reg
= vgrf(glsl_type::uint_type
);
3757 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3758 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3761 emit_untyped_write(bld
, surf_index
, offset_reg
,
3762 offset(val_reg
, bld
, first_component
* type_slots
),
3763 1 /* dims */, length
* type_slots
,
3764 BRW_PREDICATE_NONE
);
3766 /* Clear the bits in the writemask that we just wrote, then try
3767 * again to see if more channels are left.
3769 writemask
&= (15 << (first_component
+ length
));
3776 nir_emit_intrinsic(bld
, instr
);
3782 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3785 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3786 dest
= get_nir_dest(instr
->dest
);
3788 switch (instr
->intrinsic
) {
3789 case nir_intrinsic_atomic_counter_inc
:
3790 case nir_intrinsic_atomic_counter_dec
:
3791 case nir_intrinsic_atomic_counter_read
:
3792 case nir_intrinsic_atomic_counter_add
:
3793 case nir_intrinsic_atomic_counter_min
:
3794 case nir_intrinsic_atomic_counter_max
:
3795 case nir_intrinsic_atomic_counter_and
:
3796 case nir_intrinsic_atomic_counter_or
:
3797 case nir_intrinsic_atomic_counter_xor
:
3798 case nir_intrinsic_atomic_counter_exchange
:
3799 case nir_intrinsic_atomic_counter_comp_swap
: {
3800 if (stage
== MESA_SHADER_FRAGMENT
&&
3801 instr
->intrinsic
!= nir_intrinsic_atomic_counter_read
)
3802 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3804 /* Get some metadata from the image intrinsic. */
3805 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3807 /* Get the arguments of the atomic intrinsic. */
3808 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3809 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3810 instr
->const_index
[0]);
3811 const fs_reg src0
= (info
->num_srcs
>= 2
3812 ? get_nir_src(instr
->src
[1]) : fs_reg());
3813 const fs_reg src1
= (info
->num_srcs
>= 3
3814 ? get_nir_src(instr
->src
[2]) : fs_reg());
3817 assert(info
->num_srcs
<= 3);
3819 /* Emit a surface read or atomic op. */
3820 if (instr
->intrinsic
== nir_intrinsic_atomic_counter_read
) {
3821 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3823 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, src0
,
3825 get_atomic_counter_op(instr
->intrinsic
));
3828 /* Assign the result. */
3829 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3831 /* Mark the surface as used. */
3832 brw_mark_surface_used(stage_prog_data
, surface
);
3836 case nir_intrinsic_image_load
:
3837 case nir_intrinsic_image_store
:
3838 case nir_intrinsic_image_atomic_add
:
3839 case nir_intrinsic_image_atomic_min
:
3840 case nir_intrinsic_image_atomic_max
:
3841 case nir_intrinsic_image_atomic_and
:
3842 case nir_intrinsic_image_atomic_or
:
3843 case nir_intrinsic_image_atomic_xor
:
3844 case nir_intrinsic_image_atomic_exchange
:
3845 case nir_intrinsic_image_atomic_comp_swap
: {
3846 using namespace image_access
;
3848 if (stage
== MESA_SHADER_FRAGMENT
&&
3849 instr
->intrinsic
!= nir_intrinsic_image_load
)
3850 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
3852 /* Get the referenced image variable and type. */
3853 const nir_variable
*var
= instr
->variables
[0]->var
;
3854 const glsl_type
*type
= var
->type
->without_array();
3855 const brw_reg_type base_type
= get_image_base_type(type
);
3857 /* Get some metadata from the image intrinsic. */
3858 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3859 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3860 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3861 const unsigned format
= var
->data
.image
.format
;
3863 /* Get the arguments of the image intrinsic. */
3864 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3865 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3866 BRW_REGISTER_TYPE_UD
);
3867 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3868 retype(get_nir_src(instr
->src
[2]), base_type
) :
3870 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3871 retype(get_nir_src(instr
->src
[3]), base_type
) :
3875 /* Emit an image load, store or atomic op. */
3876 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3877 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3879 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3880 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3881 var
->data
.image
.write_only
? GL_NONE
: format
);
3884 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3885 surf_dims
, arr_dims
, info
->dest_components
,
3886 get_image_atomic_op(instr
->intrinsic
, type
));
3888 /* Assign the result. */
3889 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3890 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3891 offset(tmp
, bld
, c
));
3895 case nir_intrinsic_memory_barrier_atomic_counter
:
3896 case nir_intrinsic_memory_barrier_buffer
:
3897 case nir_intrinsic_memory_barrier_image
:
3898 case nir_intrinsic_memory_barrier
: {
3899 const fs_builder ubld
= bld
.group(8, 0);
3900 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
3901 ubld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3902 ->size_written
= 2 * REG_SIZE
;
3906 case nir_intrinsic_group_memory_barrier
:
3907 case nir_intrinsic_memory_barrier_shared
:
3908 /* We treat these workgroup-level barriers as no-ops. This should be
3909 * safe at present and as long as:
3911 * - Memory access instructions are not subsequently reordered by the
3912 * compiler back-end.
3914 * - All threads from a given compute shader workgroup fit within a
3915 * single subslice and therefore talk to the same HDC shared unit
3916 * what supposedly guarantees ordering and coherency between threads
3917 * from the same workgroup. This may change in the future when we
3918 * start splitting workgroups across multiple subslices.
3920 * - The context is not in fault-and-stream mode, which could cause
3921 * memory transactions (including to SLM) prior to the barrier to be
3922 * replayed after the barrier if a pagefault occurs. This shouldn't
3923 * be a problem up to and including SKL because fault-and-stream is
3924 * not usable due to hardware issues, but that's likely to change in
3929 case nir_intrinsic_shader_clock
: {
3930 /* We cannot do anything if there is an event, so ignore it for now */
3931 const fs_reg shader_clock
= get_timestamp(bld
);
3932 const fs_reg srcs
[] = { component(shader_clock
, 0),
3933 component(shader_clock
, 1) };
3934 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3938 case nir_intrinsic_image_size
: {
3939 /* Get the referenced image variable and type. */
3940 const nir_variable
*var
= instr
->variables
[0]->var
;
3941 const glsl_type
*type
= var
->type
->without_array();
3943 /* Get the size of the image. */
3944 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3945 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3947 /* For 1DArray image types, the array index is stored in the Z component.
3948 * Fix this by swizzling the Z component to the Y component.
3950 const bool is_1d_array_image
=
3951 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3952 type
->sampler_array
;
3954 /* For CubeArray images, we should count the number of cubes instead
3955 * of the number of faces. Fix it by dividing the (Z component) by 6.
3957 const bool is_cube_array_image
=
3958 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3959 type
->sampler_array
;
3961 /* Copy all the components. */
3962 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3963 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3964 if ((int)c
>= type
->coordinate_components()) {
3965 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3967 } else if (c
== 1 && is_1d_array_image
) {
3968 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3969 offset(size
, bld
, 2));
3970 } else if (c
== 2 && is_cube_array_image
) {
3971 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3972 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3973 offset(size
, bld
, c
), brw_imm_d(6));
3975 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3976 offset(size
, bld
, c
));
3983 case nir_intrinsic_image_samples
:
3984 /* The driver does not support multi-sampled images. */
3985 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3988 case nir_intrinsic_load_uniform
: {
3989 /* Offsets are in bytes but they should always be multiples of 4 */
3990 assert(instr
->const_index
[0] % 4 == 0);
3992 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3994 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3996 /* Offsets are in bytes but they should always be multiples of 4 */
3997 assert(const_offset
->u32
[0] % 4 == 0);
3998 src
.offset
= const_offset
->u32
[0];
4000 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4001 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
4004 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
4005 BRW_REGISTER_TYPE_UD
);
4007 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
4008 * go past the end of the uniform. In order to keep the n'th
4009 * component from running past, we subtract off the size of all but
4010 * one component of the vector.
4012 assert(instr
->const_index
[1] >=
4013 instr
->num_components
* (int) type_sz(dest
.type
));
4014 unsigned read_size
= instr
->const_index
[1] -
4015 (instr
->num_components
- 1) * type_sz(dest
.type
);
4017 fs_reg indirect_chv_high_32bit
;
4018 bool is_chv_bxt_64bit
=
4019 (devinfo
->is_cherryview
|| devinfo
->is_broxton
) &&
4020 type_sz(dest
.type
) == 8;
4021 if (is_chv_bxt_64bit
) {
4022 indirect_chv_high_32bit
= vgrf(glsl_type::uint_type
);
4023 /* Calculate indirect address to read high 32 bits */
4024 bld
.ADD(indirect_chv_high_32bit
, indirect
, brw_imm_ud(4));
4027 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
4028 if (!is_chv_bxt_64bit
) {
4029 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4030 offset(dest
, bld
, j
), offset(src
, bld
, j
),
4031 indirect
, brw_imm_ud(read_size
));
4033 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4034 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 0),
4035 offset(src
, bld
, j
),
4036 indirect
, brw_imm_ud(read_size
));
4038 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
4039 subscript(offset(dest
, bld
, j
), BRW_REGISTER_TYPE_UD
, 1),
4040 offset(src
, bld
, j
),
4041 indirect_chv_high_32bit
, brw_imm_ud(read_size
));
4048 case nir_intrinsic_load_ubo
: {
4049 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
4053 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
4054 const_index
->u32
[0];
4055 surf_index
= brw_imm_ud(index
);
4056 brw_mark_surface_used(prog_data
, index
);
4058 /* The block index is not a constant. Evaluate the index expression
4059 * per-channel and add the base UBO index; we have to select a value
4060 * from any live channel.
4062 surf_index
= vgrf(glsl_type::uint_type
);
4063 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4064 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
4065 surf_index
= bld
.emit_uniformize(surf_index
);
4067 /* Assume this may touch any UBO. It would be nice to provide
4068 * a tighter bound, but the array information is already lowered away.
4070 brw_mark_surface_used(prog_data
,
4071 stage_prog_data
->binding_table
.ubo_start
+
4072 nir
->info
.num_ubos
- 1);
4075 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4076 if (const_offset
== NULL
) {
4077 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
4078 BRW_REGISTER_TYPE_UD
);
4080 for (int i
= 0; i
< instr
->num_components
; i
++)
4081 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
4082 base_offset
, i
* type_sz(dest
.type
));
4084 /* Even if we are loading doubles, a pull constant load will load
4085 * a 32-bit vec4, so should only reserve vgrf space for that. If we
4086 * need to load a full dvec4 we will have to emit 2 loads. This is
4087 * similar to demote_pull_constants(), except that in that case we
4088 * see individual accesses to each component of the vector and then
4089 * we let CSE deal with duplicate loads. Here we see a vector access
4090 * and we have to split it if necessary.
4092 const unsigned type_size
= type_sz(dest
.type
);
4093 const fs_reg packed_consts
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
4094 for (unsigned c
= 0; c
< instr
->num_components
;) {
4095 const unsigned base
= const_offset
->u32
[0] + c
* type_size
;
4097 /* Number of usable components in the next 16B-aligned load */
4098 const unsigned count
= MIN2(instr
->num_components
- c
,
4099 (16 - base
% 16) / type_size
);
4102 .emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
4103 packed_consts
, surf_index
, brw_imm_ud(base
& ~15));
4105 const fs_reg consts
=
4106 retype(byte_offset(packed_consts
, base
& 15), dest
.type
);
4108 for (unsigned d
= 0; d
< count
; d
++)
4109 bld
.MOV(offset(dest
, bld
, c
+ d
), component(consts
, d
));
4117 case nir_intrinsic_load_ssbo
: {
4118 assert(devinfo
->gen
>= 7);
4120 nir_const_value
*const_uniform_block
=
4121 nir_src_as_const_value(instr
->src
[0]);
4124 if (const_uniform_block
) {
4125 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4126 const_uniform_block
->u32
[0];
4127 surf_index
= brw_imm_ud(index
);
4128 brw_mark_surface_used(prog_data
, index
);
4130 surf_index
= vgrf(glsl_type::uint_type
);
4131 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
4132 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4134 /* Assume this may touch any UBO. It would be nice to provide
4135 * a tighter bound, but the array information is already lowered away.
4137 brw_mark_surface_used(prog_data
,
4138 stage_prog_data
->binding_table
.ssbo_start
+
4139 nir
->info
.num_ssbos
- 1);
4143 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4145 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
4147 offset_reg
= get_nir_src(instr
->src
[1]);
4150 /* Read the vector */
4151 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
4152 instr
->num_components
);
4157 case nir_intrinsic_store_ssbo
: {
4158 assert(devinfo
->gen
>= 7);
4160 if (stage
== MESA_SHADER_FRAGMENT
)
4161 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4165 nir_const_value
*const_uniform_block
=
4166 nir_src_as_const_value(instr
->src
[1]);
4167 if (const_uniform_block
) {
4168 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
4169 const_uniform_block
->u32
[0];
4170 surf_index
= brw_imm_ud(index
);
4171 brw_mark_surface_used(prog_data
, index
);
4173 surf_index
= vgrf(glsl_type::uint_type
);
4174 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
4175 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4177 brw_mark_surface_used(prog_data
,
4178 stage_prog_data
->binding_table
.ssbo_start
+
4179 nir
->info
.num_ssbos
- 1);
4183 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
4186 unsigned writemask
= instr
->const_index
[0];
4188 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
4189 * since the untyped writes below operate in units of 32-bits, which
4190 * means that we need to write twice as many components each time.
4191 * Also, we have to suffle 64-bit data to be in the appropriate layout
4192 * expected by our 32-bit write messages.
4194 unsigned type_size
= 4;
4195 unsigned bit_size
= instr
->src
[0].is_ssa
?
4196 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4197 if (bit_size
== 64) {
4200 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
4201 shuffle_64bit_data_for_32bit_write(bld
,
4202 retype(tmp
, BRW_REGISTER_TYPE_F
),
4203 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
4204 instr
->num_components
);
4208 unsigned type_slots
= type_size
/ 4;
4210 /* Combine groups of consecutive enabled channels in one write
4211 * message. We use ffs to find the first enabled channel and then ffs on
4212 * the bit-inverse, down-shifted writemask to determine the length of
4213 * the block of enabled bits.
4216 unsigned first_component
= ffs(writemask
) - 1;
4217 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
4219 /* We can't write more than 2 64-bit components at once. Limit the
4220 * length of the write to what we can do and let the next iteration
4224 length
= MIN2(2, length
);
4227 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
4229 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
4230 type_size
* first_component
);
4232 offset_reg
= vgrf(glsl_type::uint_type
);
4234 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
4235 brw_imm_ud(type_size
* first_component
));
4239 emit_untyped_write(bld
, surf_index
, offset_reg
,
4240 offset(val_reg
, bld
, first_component
* type_slots
),
4241 1 /* dims */, length
* type_slots
,
4242 BRW_PREDICATE_NONE
);
4244 /* Clear the bits in the writemask that we just wrote, then try
4245 * again to see if more channels are left.
4247 writemask
&= (15 << (first_component
+ length
));
4252 case nir_intrinsic_store_output
: {
4253 fs_reg src
= get_nir_src(instr
->src
[0]);
4254 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
4255 instr
->const_index
[0]);
4257 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
4258 assert(const_offset
&& "Indirect output stores not allowed");
4259 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
4261 unsigned num_components
= instr
->num_components
;
4262 unsigned first_component
= nir_intrinsic_component(instr
);
4263 unsigned bit_size
= instr
->src
[0].is_ssa
?
4264 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
4265 if (bit_size
== 64) {
4267 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
4268 BRW_REGISTER_TYPE_F
);
4269 shuffle_64bit_data_for_32bit_write(
4270 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
4271 src
= retype(tmp
, src
.type
);
4272 num_components
*= 2;
4275 for (unsigned j
= 0; j
< num_components
; j
++) {
4276 bld
.MOV(offset(new_dest
, bld
, j
+ first_component
),
4277 offset(src
, bld
, j
));
4282 case nir_intrinsic_ssbo_atomic_add
:
4283 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
4285 case nir_intrinsic_ssbo_atomic_imin
:
4286 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
4288 case nir_intrinsic_ssbo_atomic_umin
:
4289 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
4291 case nir_intrinsic_ssbo_atomic_imax
:
4292 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
4294 case nir_intrinsic_ssbo_atomic_umax
:
4295 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
4297 case nir_intrinsic_ssbo_atomic_and
:
4298 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
4300 case nir_intrinsic_ssbo_atomic_or
:
4301 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
4303 case nir_intrinsic_ssbo_atomic_xor
:
4304 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
4306 case nir_intrinsic_ssbo_atomic_exchange
:
4307 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
4309 case nir_intrinsic_ssbo_atomic_comp_swap
:
4310 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
4313 case nir_intrinsic_get_buffer_size
: {
4314 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
4315 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
4317 /* A resinfo's sampler message is used to get the buffer size. The
4318 * SIMD8's writeback message consists of four registers and SIMD16's
4319 * writeback message consists of 8 destination registers (two per each
4320 * component). Because we are only interested on the first channel of
4321 * the first returned component, where resinfo returns the buffer size
4322 * for SURFTYPE_BUFFER, we can just use the SIMD8 variant regardless of
4323 * the dispatch width.
4325 const fs_builder ubld
= bld
.exec_all().group(8, 0);
4326 fs_reg src_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
);
4327 fs_reg ret_payload
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 4);
4330 ubld
.MOV(src_payload
, brw_imm_d(0));
4332 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
4333 fs_inst
*inst
= ubld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, ret_payload
,
4334 src_payload
, brw_imm_ud(index
));
4335 inst
->header_size
= 0;
4337 inst
->size_written
= 4 * REG_SIZE
;
4339 bld
.MOV(retype(dest
, ret_payload
.type
), component(ret_payload
, 0));
4340 brw_mark_surface_used(prog_data
, index
);
4344 case nir_intrinsic_load_channel_num
: {
4345 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UW
);
4346 dest
= retype(dest
, BRW_REGISTER_TYPE_UD
);
4347 const fs_builder allbld8
= bld
.group(8, 0).exec_all();
4348 allbld8
.MOV(tmp
, brw_imm_v(0x76543210));
4349 if (dispatch_width
> 8)
4350 allbld8
.ADD(byte_offset(tmp
, 16), tmp
, brw_imm_uw(8u));
4351 if (dispatch_width
> 16) {
4352 const fs_builder allbld16
= bld
.group(16, 0).exec_all();
4353 allbld16
.ADD(byte_offset(tmp
, 32), tmp
, brw_imm_uw(16u));
4360 unreachable("unknown intrinsic");
4365 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
4366 int op
, nir_intrinsic_instr
*instr
)
4368 if (stage
== MESA_SHADER_FRAGMENT
)
4369 brw_wm_prog_data(prog_data
)->has_side_effects
= true;
4372 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4373 dest
= get_nir_dest(instr
->dest
);
4376 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
4377 if (const_surface
) {
4378 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
4379 const_surface
->u32
[0];
4380 surface
= brw_imm_ud(surf_index
);
4381 brw_mark_surface_used(prog_data
, surf_index
);
4383 surface
= vgrf(glsl_type::uint_type
);
4384 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
4385 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
4387 /* Assume this may touch any SSBO. This is the same we do for other
4388 * UBO/SSBO accesses with non-constant surface.
4390 brw_mark_surface_used(prog_data
,
4391 stage_prog_data
->binding_table
.ssbo_start
+
4392 nir
->info
.num_ssbos
- 1);
4395 fs_reg offset
= get_nir_src(instr
->src
[1]);
4396 fs_reg data1
= get_nir_src(instr
->src
[2]);
4398 if (op
== BRW_AOP_CMPWR
)
4399 data2
= get_nir_src(instr
->src
[3]);
4401 /* Emit the actual atomic operation */
4403 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4405 1 /* dims */, 1 /* rsize */,
4407 BRW_PREDICATE_NONE
);
4408 dest
.type
= atomic_result
.type
;
4409 bld
.MOV(dest
, atomic_result
);
4413 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
4414 int op
, nir_intrinsic_instr
*instr
)
4417 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
4418 dest
= get_nir_dest(instr
->dest
);
4420 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
4422 fs_reg data1
= get_nir_src(instr
->src
[1]);
4424 if (op
== BRW_AOP_CMPWR
)
4425 data2
= get_nir_src(instr
->src
[2]);
4427 /* Get the offset */
4428 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
4430 offset
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
4432 offset
= vgrf(glsl_type::uint_type
);
4434 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
4435 brw_imm_ud(instr
->const_index
[0]));
4438 /* Emit the actual atomic operation operation */
4440 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
4442 1 /* dims */, 1 /* rsize */,
4444 BRW_PREDICATE_NONE
);
4445 dest
.type
= atomic_result
.type
;
4446 bld
.MOV(dest
, atomic_result
);
4450 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
4452 unsigned texture
= instr
->texture_index
;
4453 unsigned sampler
= instr
->sampler_index
;
4455 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
4457 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
4458 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
4460 int lod_components
= 0;
4462 /* The hardware requires a LOD for buffer textures */
4463 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4464 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4466 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4467 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4468 switch (instr
->src
[i
].src_type
) {
4469 case nir_tex_src_bias
:
4470 srcs
[TEX_LOGICAL_SRC_LOD
] =
4471 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4473 case nir_tex_src_comparitor
:
4474 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4476 case nir_tex_src_coord
:
4477 switch (instr
->op
) {
4479 case nir_texop_txf_ms
:
4480 case nir_texop_txf_ms_mcs
:
4481 case nir_texop_samples_identical
:
4482 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4485 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4489 case nir_tex_src_ddx
:
4490 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4491 lod_components
= nir_tex_instr_src_size(instr
, i
);
4493 case nir_tex_src_ddy
:
4494 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4496 case nir_tex_src_lod
:
4497 switch (instr
->op
) {
4499 srcs
[TEX_LOGICAL_SRC_LOD
] =
4500 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_UD
);
4503 srcs
[TEX_LOGICAL_SRC_LOD
] =
4504 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_D
);
4507 srcs
[TEX_LOGICAL_SRC_LOD
] =
4508 retype(get_nir_src_imm(instr
->src
[i
].src
), BRW_REGISTER_TYPE_F
);
4512 case nir_tex_src_ms_index
:
4513 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4516 case nir_tex_src_offset
: {
4517 nir_const_value
*const_offset
=
4518 nir_src_as_const_value(instr
->src
[i
].src
);
4520 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4521 if (header_bits
!= 0)
4522 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4524 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4525 retype(src
, BRW_REGISTER_TYPE_D
);
4530 case nir_tex_src_projector
:
4531 unreachable("should be lowered");
4533 case nir_tex_src_texture_offset
: {
4534 /* Figure out the highest possible texture index and mark it as used */
4535 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4536 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4537 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4539 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4541 brw_mark_surface_used(prog_data
, max_used
);
4543 /* Emit code to evaluate the actual indexing expression */
4544 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4545 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4546 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4550 case nir_tex_src_sampler_offset
: {
4551 /* Emit code to evaluate the actual indexing expression */
4552 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4553 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4554 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4558 case nir_tex_src_ms_mcs
:
4559 assert(instr
->op
== nir_texop_txf_ms
);
4560 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4563 case nir_tex_src_plane
: {
4564 nir_const_value
*const_plane
=
4565 nir_src_as_const_value(instr
->src
[i
].src
);
4566 const uint32_t plane
= const_plane
->u32
[0];
4567 const uint32_t texture_index
=
4568 instr
->texture_index
+
4569 stage_prog_data
->binding_table
.plane_start
[plane
] -
4570 stage_prog_data
->binding_table
.texture_start
;
4572 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture_index
);
4577 unreachable("unknown texture source");
4581 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4582 (instr
->op
== nir_texop_txf_ms
||
4583 instr
->op
== nir_texop_samples_identical
)) {
4584 if (devinfo
->gen
>= 7 &&
4585 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4586 srcs
[TEX_LOGICAL_SRC_MCS
] =
4587 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4588 instr
->coord_components
,
4589 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4591 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4595 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4596 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4598 if (instr
->op
== nir_texop_query_levels
||
4599 (instr
->op
== nir_texop_tex
&& stage
!= MESA_SHADER_FRAGMENT
)) {
4600 /* textureQueryLevels() and texture() are implemented in terms of TXS
4601 * and TXL respectively, so we need to pass a valid LOD argument.
4603 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4604 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4608 switch (instr
->op
) {
4610 opcode
= (stage
== MESA_SHADER_FRAGMENT
? SHADER_OPCODE_TEX_LOGICAL
:
4611 SHADER_OPCODE_TXL_LOGICAL
);
4614 opcode
= FS_OPCODE_TXB_LOGICAL
;
4617 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4620 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4623 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4625 case nir_texop_txf_ms
:
4626 if ((key_tex
->msaa_16
& (1 << sampler
)))
4627 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4629 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4631 case nir_texop_txf_ms_mcs
:
4632 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4634 case nir_texop_query_levels
:
4636 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4639 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4642 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4643 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4644 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4646 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4648 case nir_texop_texture_samples
:
4649 opcode
= SHADER_OPCODE_SAMPLEINFO_LOGICAL
;
4651 case nir_texop_samples_identical
: {
4652 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4654 /* If mcs is an immediate value, it means there is no MCS. In that case
4655 * just return false.
4657 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4658 bld
.MOV(dst
, brw_imm_ud(0u));
4659 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4660 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4661 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4662 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4663 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4665 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4666 BRW_CONDITIONAL_EQ
);
4671 unreachable("unknown texture opcode");
4674 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4675 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4677 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4678 if (devinfo
->gen
>= 9 &&
4679 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4680 unsigned write_mask
= instr
->dest
.is_ssa
?
4681 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4682 (1 << dest_size
) - 1;
4683 assert(write_mask
!= 0); /* dead code should have been eliminated */
4684 inst
->size_written
= util_last_bit(write_mask
) *
4685 inst
->dst
.component_size(inst
->exec_size
);
4687 inst
->size_written
= 4 * inst
->dst
.component_size(inst
->exec_size
);
4690 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4691 inst
->shadow_compare
= true;
4693 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4694 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4696 if (instr
->op
== nir_texop_tg4
) {
4697 if (instr
->component
== 1 &&
4698 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4699 /* gather4 sampler is broken for green channel on RG32F --
4700 * we must ask for blue instead.
4702 inst
->offset
|= 2 << 16;
4704 inst
->offset
|= instr
->component
<< 16;
4707 if (devinfo
->gen
== 6)
4708 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4712 for (unsigned i
= 0; i
< dest_size
; i
++)
4713 nir_dest
[i
] = offset(dst
, bld
, i
);
4715 if (instr
->op
== nir_texop_query_levels
) {
4716 /* # levels is in .w */
4717 nir_dest
[0] = offset(dst
, bld
, 3);
4718 } else if (instr
->op
== nir_texop_txs
&&
4719 dest_size
>= 3 && devinfo
->gen
< 7) {
4720 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4721 fs_reg depth
= offset(dst
, bld
, 2);
4722 nir_dest
[2] = vgrf(glsl_type::int_type
);
4723 bld
.emit_minmax(nir_dest
[2], depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4726 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4730 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4732 switch (instr
->type
) {
4733 case nir_jump_break
:
4734 bld
.emit(BRW_OPCODE_BREAK
);
4736 case nir_jump_continue
:
4737 bld
.emit(BRW_OPCODE_CONTINUE
);
4739 case nir_jump_return
:
4741 unreachable("unknown jump");
4746 * This helper takes the result of a load operation that reads 32-bit elements
4754 * and shuffles the data to get this:
4761 * Which is exactly what we want if the load is reading 64-bit components
4762 * like doubles, where x represents the low 32-bit of the x double component
4763 * and y represents the high 32-bit of the x double component (likewise with
4764 * z and w for double component y). The parameter @components represents
4765 * the number of 64-bit components present in @src. This would typically be
4766 * 2 at most, since we can only fit 2 double elements in the result of a
4769 * Notice that @dst and @src can be the same register.
4772 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4775 uint32_t components
)
4777 assert(type_sz(src
.type
) == 4);
4778 assert(type_sz(dst
.type
) == 8);
4780 /* A temporary that we will use to shuffle the 32-bit data of each
4781 * component in the vector into valid 64-bit data. We can't write directly
4782 * to dst because dst can be (and would usually be) the same as src
4783 * and in that case the first MOV in the loop below would overwrite the
4784 * data read in the second MOV.
4786 fs_reg tmp
= bld
.vgrf(dst
.type
);
4788 for (unsigned i
= 0; i
< components
; i
++) {
4789 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4791 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4792 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4794 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4799 * This helper does the inverse operation of
4800 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4802 * We need to do this when we are going to use untyped write messsages that
4803 * operate with 32-bit components in order to arrange our 64-bit data to be
4804 * in the expected layout.
4806 * Notice that callers of this function, unlike in the case of the inverse
4807 * operation, would typically need to call this with dst and src being
4808 * different registers, since they would otherwise corrupt the original
4809 * 64-bit data they are about to write. Because of this the function checks
4810 * that the src and dst regions involved in the operation do not overlap.
4813 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4816 uint32_t components
)
4818 assert(type_sz(src
.type
) == 8);
4819 assert(type_sz(dst
.type
) == 4);
4821 assert(!regions_overlap(
4822 dst
, 2 * components
* dst
.component_size(bld
.dispatch_width()),
4823 src
, components
* src
.component_size(bld
.dispatch_width())));
4825 for (unsigned i
= 0; i
< components
; i
++) {
4826 const fs_reg component_i
= offset(src
, bld
, i
);
4827 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4828 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));
4833 setup_imm_df(const fs_builder
&bld
, double v
)
4835 const struct gen_device_info
*devinfo
= bld
.shader
->devinfo
;
4836 assert(devinfo
->gen
>= 7);
4838 if (devinfo
->gen
>= 8)
4839 return brw_imm_df(v
);
4841 /* gen7.5 does not support DF immediates straighforward but the DIM
4842 * instruction allows to set the 64-bit immediate value.
4844 if (devinfo
->is_haswell
) {
4845 const fs_builder ubld
= bld
.exec_all();
4846 fs_reg dst
= ubld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
4847 ubld
.DIM(dst
, brw_imm_df(v
));
4848 return component(dst
, 0);
4851 /* gen7 does not support DF immediates, so we generate a 64-bit constant by
4852 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
4853 * the high 32-bit to suboffset 4 and then applying a stride of 0.
4855 * Alternatively, we could also produce a normal VGRF (without stride 0)
4856 * by writing to all the channels in the VGRF, however, that would hit the
4857 * gen7 bug where we have to split writes that span more than 1 register
4858 * into instructions with a width of 4 (otherwise the write to the second
4859 * register written runs into an execmask hardware bug) which isn't very
4872 const fs_builder ubld
= bld
.exec_all().group(1, 0);
4873 const fs_reg tmp
= ubld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
4874 ubld
.MOV(tmp
, brw_imm_ud(di
.i1
));
4875 ubld
.MOV(horiz_offset(tmp
, 1), brw_imm_ud(di
.i2
));
4877 return component(retype(tmp
, BRW_REGISTER_TYPE_DF
), 0);