2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "compiler/glsl/ir.h"
26 #include "brw_fs_surface_builder.h"
28 #include "brw_program.h"
31 using namespace brw::surface_access
;
34 fs_visitor::emit_nir_code()
36 /* emit the arrays used for inputs and outputs - load/store intrinsics will
37 * be converted to reads/writes of these arrays
42 nir_emit_system_values();
44 /* get the main function and emit it */
45 nir_foreach_function(function
, nir
) {
46 assert(strcmp(function
->name
, "main") == 0);
47 assert(function
->impl
);
48 nir_emit_impl(function
->impl
);
53 fs_visitor::nir_setup_inputs()
55 if (stage
!= MESA_SHADER_FRAGMENT
)
58 nir_inputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_inputs
);
60 nir_foreach_variable(var
, &nir
->inputs
) {
61 fs_reg input
= offset(nir_inputs
, bld
, var
->data
.driver_location
);
64 if (var
->data
.location
== VARYING_SLOT_POS
) {
65 reg
= *emit_fragcoord_interpolation(var
->data
.pixel_center_integer
,
66 var
->data
.origin_upper_left
);
67 emit_percomp(bld
, fs_inst(BRW_OPCODE_MOV
, bld
.dispatch_width(),
69 } else if (var
->data
.location
== VARYING_SLOT_LAYER
) {
70 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_LAYER
, 1), 3);
71 reg
.type
= BRW_REGISTER_TYPE_D
;
72 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
73 } else if (var
->data
.location
== VARYING_SLOT_VIEWPORT
) {
74 struct brw_reg reg
= suboffset(interp_reg(VARYING_SLOT_VIEWPORT
, 2), 3);
75 reg
.type
= BRW_REGISTER_TYPE_D
;
76 bld
.emit(FS_OPCODE_CINTERP
, retype(input
, BRW_REGISTER_TYPE_D
), reg
);
78 int location
= var
->data
.location
;
79 emit_general_interpolation(&input
, var
->name
, var
->type
,
80 (glsl_interp_qualifier
) var
->data
.interpolation
,
81 &location
, var
->data
.centroid
,
88 fs_visitor::nir_setup_single_output_varying(fs_reg
*reg
,
89 const glsl_type
*type
,
92 if (type
->is_array() || type
->is_matrix()) {
93 const struct glsl_type
*elem_type
= glsl_get_array_element(type
);
94 const unsigned length
= glsl_get_length(type
);
96 for (unsigned i
= 0; i
< length
; i
++) {
97 nir_setup_single_output_varying(reg
, elem_type
, location
);
99 } else if (type
->is_record()) {
100 for (unsigned i
= 0; i
< type
->length
; i
++) {
101 const struct glsl_type
*field_type
= type
->fields
.structure
[i
].type
;
102 nir_setup_single_output_varying(reg
, field_type
, location
);
105 assert(type
->is_scalar() || type
->is_vector());
106 unsigned num_elements
= type
->vector_elements
;
107 if (type
->is_double())
109 for (unsigned count
= 0; count
< num_elements
; count
+= 4) {
110 this->outputs
[*location
] = *reg
;
111 this->output_components
[*location
] = MIN2(4, num_elements
- count
);
112 *reg
= offset(*reg
, bld
, 4);
119 fs_visitor::nir_setup_outputs()
121 if (stage
== MESA_SHADER_TESS_CTRL
)
124 brw_wm_prog_key
*key
= (brw_wm_prog_key
*) this->key
;
126 nir_outputs
= bld
.vgrf(BRW_REGISTER_TYPE_F
, nir
->num_outputs
);
128 nir_foreach_variable(var
, &nir
->outputs
) {
129 fs_reg reg
= offset(nir_outputs
, bld
, var
->data
.driver_location
);
132 case MESA_SHADER_VERTEX
:
133 case MESA_SHADER_TESS_EVAL
:
134 case MESA_SHADER_GEOMETRY
: {
135 unsigned location
= var
->data
.location
;
136 nir_setup_single_output_varying(®
, var
->type
, &location
);
139 case MESA_SHADER_FRAGMENT
:
140 if (key
->force_dual_color_blend
&&
141 var
->data
.location
== FRAG_RESULT_DATA1
) {
142 this->dual_src_output
= reg
;
143 this->do_dual_src
= true;
144 } else if (var
->data
.index
> 0) {
145 assert(var
->data
.location
== FRAG_RESULT_DATA0
);
146 assert(var
->data
.index
== 1);
147 this->dual_src_output
= reg
;
148 this->do_dual_src
= true;
149 } else if (var
->data
.location
== FRAG_RESULT_COLOR
) {
150 /* Writing gl_FragColor outputs to all color regions. */
151 for (unsigned int i
= 0; i
< MAX2(key
->nr_color_regions
, 1); i
++) {
152 this->outputs
[i
] = reg
;
153 this->output_components
[i
] = 4;
155 } else if (var
->data
.location
== FRAG_RESULT_DEPTH
) {
156 this->frag_depth
= reg
;
157 } else if (var
->data
.location
== FRAG_RESULT_STENCIL
) {
158 this->frag_stencil
= reg
;
159 } else if (var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
) {
160 this->sample_mask
= reg
;
162 int vector_elements
= var
->type
->without_array()->vector_elements
;
164 /* gl_FragData or a user-defined FS output */
165 assert(var
->data
.location
>= FRAG_RESULT_DATA0
&&
166 var
->data
.location
< FRAG_RESULT_DATA0
+BRW_MAX_DRAW_BUFFERS
);
168 /* General color output. */
169 for (unsigned int i
= 0; i
< MAX2(1, var
->type
->length
); i
++) {
170 int output
= var
->data
.location
- FRAG_RESULT_DATA0
+ i
;
171 this->outputs
[output
] = offset(reg
, bld
, vector_elements
* i
);
172 this->output_components
[output
] = vector_elements
;
177 unreachable("unhandled shader stage");
183 fs_visitor::nir_setup_uniforms()
185 if (dispatch_width
!= 8)
188 uniforms
= nir
->num_uniforms
/ 4;
192 emit_system_values_block(nir_block
*block
, fs_visitor
*v
)
196 nir_foreach_instr(instr
, block
) {
197 if (instr
->type
!= nir_instr_type_intrinsic
)
200 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
201 switch (intrin
->intrinsic
) {
202 case nir_intrinsic_load_vertex_id
:
203 unreachable("should be lowered by lower_vertex_id().");
205 case nir_intrinsic_load_vertex_id_zero_base
:
206 assert(v
->stage
== MESA_SHADER_VERTEX
);
207 reg
= &v
->nir_system_values
[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
];
208 if (reg
->file
== BAD_FILE
)
209 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
212 case nir_intrinsic_load_base_vertex
:
213 assert(v
->stage
== MESA_SHADER_VERTEX
);
214 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_VERTEX
];
215 if (reg
->file
== BAD_FILE
)
216 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX
);
219 case nir_intrinsic_load_instance_id
:
220 assert(v
->stage
== MESA_SHADER_VERTEX
);
221 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INSTANCE_ID
];
222 if (reg
->file
== BAD_FILE
)
223 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID
);
226 case nir_intrinsic_load_base_instance
:
227 assert(v
->stage
== MESA_SHADER_VERTEX
);
228 reg
= &v
->nir_system_values
[SYSTEM_VALUE_BASE_INSTANCE
];
229 if (reg
->file
== BAD_FILE
)
230 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_BASE_INSTANCE
);
233 case nir_intrinsic_load_draw_id
:
234 assert(v
->stage
== MESA_SHADER_VERTEX
);
235 reg
= &v
->nir_system_values
[SYSTEM_VALUE_DRAW_ID
];
236 if (reg
->file
== BAD_FILE
)
237 *reg
= *v
->emit_vs_system_value(SYSTEM_VALUE_DRAW_ID
);
240 case nir_intrinsic_load_invocation_id
:
241 if (v
->stage
== MESA_SHADER_TESS_CTRL
)
243 assert(v
->stage
== MESA_SHADER_GEOMETRY
);
244 reg
= &v
->nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
245 if (reg
->file
== BAD_FILE
) {
246 const fs_builder abld
= v
->bld
.annotate("gl_InvocationID", NULL
);
247 fs_reg
g1(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
248 fs_reg iid
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
249 abld
.SHR(iid
, g1
, brw_imm_ud(27u));
254 case nir_intrinsic_load_sample_pos
:
255 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
256 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
257 if (reg
->file
== BAD_FILE
)
258 *reg
= *v
->emit_samplepos_setup();
261 case nir_intrinsic_load_sample_id
:
262 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
263 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_ID
];
264 if (reg
->file
== BAD_FILE
)
265 *reg
= *v
->emit_sampleid_setup();
268 case nir_intrinsic_load_sample_mask_in
:
269 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
270 assert(v
->devinfo
->gen
>= 7);
271 reg
= &v
->nir_system_values
[SYSTEM_VALUE_SAMPLE_MASK_IN
];
272 if (reg
->file
== BAD_FILE
)
273 *reg
= *v
->emit_samplemaskin_setup();
276 case nir_intrinsic_load_local_invocation_id
:
277 assert(v
->stage
== MESA_SHADER_COMPUTE
);
278 reg
= &v
->nir_system_values
[SYSTEM_VALUE_LOCAL_INVOCATION_ID
];
279 if (reg
->file
== BAD_FILE
)
280 *reg
= *v
->emit_cs_local_invocation_id_setup();
283 case nir_intrinsic_load_work_group_id
:
284 assert(v
->stage
== MESA_SHADER_COMPUTE
);
285 reg
= &v
->nir_system_values
[SYSTEM_VALUE_WORK_GROUP_ID
];
286 if (reg
->file
== BAD_FILE
)
287 *reg
= *v
->emit_cs_work_group_id_setup();
290 case nir_intrinsic_load_helper_invocation
:
291 assert(v
->stage
== MESA_SHADER_FRAGMENT
);
292 reg
= &v
->nir_system_values
[SYSTEM_VALUE_HELPER_INVOCATION
];
293 if (reg
->file
== BAD_FILE
) {
294 const fs_builder abld
=
295 v
->bld
.annotate("gl_HelperInvocation", NULL
);
297 /* On Gen6+ (gl_HelperInvocation is only exposed on Gen7+) the
298 * pixel mask is in g1.7 of the thread payload.
300 * We move the per-channel pixel enable bit to the low bit of each
301 * channel by shifting the byte containing the pixel mask by the
302 * vector immediate 0x76543210UV.
304 * The region of <1,8,0> reads only 1 byte (the pixel masks for
305 * subspans 0 and 1) in SIMD8 and an additional byte (the pixel
306 * masks for 2 and 3) in SIMD16.
308 fs_reg shifted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
, 1);
310 stride(byte_offset(retype(brw_vec1_grf(1, 0),
311 BRW_REGISTER_TYPE_UB
), 28),
313 brw_imm_uv(0x76543210));
315 /* A set bit in the pixel mask means the channel is enabled, but
316 * that is the opposite of gl_HelperInvocation so we need to invert
319 * The negate source-modifier bit of logical instructions on Gen8+
320 * performs 1's complement negation, so we can use that instead of
323 fs_reg inverted
= negate(shifted
);
324 if (v
->devinfo
->gen
< 8) {
325 inverted
= abld
.vgrf(BRW_REGISTER_TYPE_UW
);
326 abld
.NOT(inverted
, shifted
);
329 /* We then resolve the 0/1 result to 0/~0 boolean values by ANDing
330 * with 1 and negating.
332 fs_reg anded
= abld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
333 abld
.AND(anded
, inverted
, brw_imm_uw(1));
335 fs_reg dst
= abld
.vgrf(BRW_REGISTER_TYPE_D
, 1);
336 abld
.MOV(dst
, negate(retype(anded
, BRW_REGISTER_TYPE_D
)));
350 fs_visitor::nir_emit_system_values()
352 nir_system_values
= ralloc_array(mem_ctx
, fs_reg
, SYSTEM_VALUE_MAX
);
353 for (unsigned i
= 0; i
< SYSTEM_VALUE_MAX
; i
++) {
354 nir_system_values
[i
] = fs_reg();
357 nir_foreach_function(function
, nir
) {
358 assert(strcmp(function
->name
, "main") == 0);
359 assert(function
->impl
);
360 nir_foreach_block(block
, function
->impl
) {
361 emit_system_values_block(block
, this);
367 fs_visitor::nir_emit_impl(nir_function_impl
*impl
)
369 nir_locals
= ralloc_array(mem_ctx
, fs_reg
, impl
->reg_alloc
);
370 for (unsigned i
= 0; i
< impl
->reg_alloc
; i
++) {
371 nir_locals
[i
] = fs_reg();
374 foreach_list_typed(nir_register
, reg
, node
, &impl
->registers
) {
375 unsigned array_elems
=
376 reg
->num_array_elems
== 0 ? 1 : reg
->num_array_elems
;
377 unsigned size
= array_elems
* reg
->num_components
;
378 const brw_reg_type reg_type
=
379 reg
->bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
380 nir_locals
[reg
->index
] = bld
.vgrf(reg_type
, size
);
383 nir_ssa_values
= reralloc(mem_ctx
, nir_ssa_values
, fs_reg
,
386 nir_emit_cf_list(&impl
->body
);
390 fs_visitor::nir_emit_cf_list(exec_list
*list
)
392 exec_list_validate(list
);
393 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
394 switch (node
->type
) {
396 nir_emit_if(nir_cf_node_as_if(node
));
399 case nir_cf_node_loop
:
400 nir_emit_loop(nir_cf_node_as_loop(node
));
403 case nir_cf_node_block
:
404 nir_emit_block(nir_cf_node_as_block(node
));
408 unreachable("Invalid CFG node block");
414 fs_visitor::nir_emit_if(nir_if
*if_stmt
)
416 /* first, put the condition into f0 */
417 fs_inst
*inst
= bld
.MOV(bld
.null_reg_d(),
418 retype(get_nir_src(if_stmt
->condition
),
419 BRW_REGISTER_TYPE_D
));
420 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
422 bld
.IF(BRW_PREDICATE_NORMAL
);
424 nir_emit_cf_list(&if_stmt
->then_list
);
426 /* note: if the else is empty, dead CF elimination will remove it */
427 bld
.emit(BRW_OPCODE_ELSE
);
429 nir_emit_cf_list(&if_stmt
->else_list
);
431 bld
.emit(BRW_OPCODE_ENDIF
);
435 fs_visitor::nir_emit_loop(nir_loop
*loop
)
437 bld
.emit(BRW_OPCODE_DO
);
439 nir_emit_cf_list(&loop
->body
);
441 bld
.emit(BRW_OPCODE_WHILE
);
445 fs_visitor::nir_emit_block(nir_block
*block
)
447 nir_foreach_instr(instr
, block
) {
448 nir_emit_instr(instr
);
453 fs_visitor::nir_emit_instr(nir_instr
*instr
)
455 const fs_builder abld
= bld
.annotate(NULL
, instr
);
457 switch (instr
->type
) {
458 case nir_instr_type_alu
:
459 nir_emit_alu(abld
, nir_instr_as_alu(instr
));
462 case nir_instr_type_intrinsic
:
464 case MESA_SHADER_VERTEX
:
465 nir_emit_vs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
467 case MESA_SHADER_TESS_CTRL
:
468 nir_emit_tcs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
470 case MESA_SHADER_TESS_EVAL
:
471 nir_emit_tes_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
473 case MESA_SHADER_GEOMETRY
:
474 nir_emit_gs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
476 case MESA_SHADER_FRAGMENT
:
477 nir_emit_fs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
479 case MESA_SHADER_COMPUTE
:
480 nir_emit_cs_intrinsic(abld
, nir_instr_as_intrinsic(instr
));
483 unreachable("unsupported shader stage");
487 case nir_instr_type_tex
:
488 nir_emit_texture(abld
, nir_instr_as_tex(instr
));
491 case nir_instr_type_load_const
:
492 nir_emit_load_const(abld
, nir_instr_as_load_const(instr
));
495 case nir_instr_type_ssa_undef
:
496 nir_emit_undef(abld
, nir_instr_as_ssa_undef(instr
));
499 case nir_instr_type_jump
:
500 nir_emit_jump(abld
, nir_instr_as_jump(instr
));
504 unreachable("unknown instruction type");
509 * Recognizes a parent instruction of nir_op_extract_* and changes the type to
513 fs_visitor::optimize_extract_to_float(nir_alu_instr
*instr
,
514 const fs_reg
&result
)
516 if (!instr
->src
[0].src
.is_ssa
||
517 !instr
->src
[0].src
.ssa
->parent_instr
)
520 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
523 nir_alu_instr
*src0
=
524 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
526 if (src0
->op
!= nir_op_extract_u8
&& src0
->op
!= nir_op_extract_u16
&&
527 src0
->op
!= nir_op_extract_i8
&& src0
->op
!= nir_op_extract_i16
)
530 nir_const_value
*element
= nir_src_as_const_value(src0
->src
[1].src
);
531 assert(element
!= NULL
);
533 enum opcode extract_op
;
534 if (src0
->op
== nir_op_extract_u16
|| src0
->op
== nir_op_extract_i16
) {
535 assert(element
->u32
[0] <= 1);
536 extract_op
= SHADER_OPCODE_EXTRACT_WORD
;
538 assert(element
->u32
[0] <= 3);
539 extract_op
= SHADER_OPCODE_EXTRACT_BYTE
;
542 fs_reg op0
= get_nir_src(src0
->src
[0].src
);
543 op0
.type
= brw_type_for_nir_type(
544 (nir_alu_type
)(nir_op_infos
[src0
->op
].input_types
[0] |
545 nir_src_bit_size(src0
->src
[0].src
)));
546 op0
= offset(op0
, bld
, src0
->src
[0].swizzle
[0]);
548 set_saturate(instr
->dest
.saturate
,
549 bld
.emit(extract_op
, result
, op0
, brw_imm_ud(element
->u32
[0])));
554 fs_visitor::optimize_frontfacing_ternary(nir_alu_instr
*instr
,
555 const fs_reg
&result
)
557 if (!instr
->src
[0].src
.is_ssa
||
558 instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_intrinsic
)
561 nir_intrinsic_instr
*src0
=
562 nir_instr_as_intrinsic(instr
->src
[0].src
.ssa
->parent_instr
);
564 if (src0
->intrinsic
!= nir_intrinsic_load_front_face
)
567 nir_const_value
*value1
= nir_src_as_const_value(instr
->src
[1].src
);
568 if (!value1
|| fabsf(value1
->f32
[0]) != 1.0f
)
571 nir_const_value
*value2
= nir_src_as_const_value(instr
->src
[2].src
);
572 if (!value2
|| fabsf(value2
->f32
[0]) != 1.0f
)
575 fs_reg tmp
= vgrf(glsl_type::int_type
);
577 if (devinfo
->gen
>= 6) {
578 /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
579 fs_reg g0
= fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W
));
581 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
583 * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
584 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
586 * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
588 * This negation looks like it's safe in practice, because bits 0:4 will
589 * surely be TRIANGLES
592 if (value1
->f32
[0] == -1.0f
) {
596 tmp
.type
= BRW_REGISTER_TYPE_W
;
597 tmp
.subreg_offset
= 2;
600 bld
.OR(tmp
, g0
, brw_imm_uw(0x3f80));
602 tmp
.type
= BRW_REGISTER_TYPE_D
;
603 tmp
.subreg_offset
= 0;
606 /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
607 fs_reg g1_6
= fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D
));
609 /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
611 * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
612 * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
614 * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
616 * This negation looks like it's safe in practice, because bits 0:4 will
617 * surely be TRIANGLES
620 if (value1
->f32
[0] == -1.0f
) {
624 bld
.OR(tmp
, g1_6
, brw_imm_d(0x3f800000));
626 bld
.AND(retype(result
, BRW_REGISTER_TYPE_D
), tmp
, brw_imm_d(0xbf800000));
632 fs_visitor::nir_emit_alu(const fs_builder
&bld
, nir_alu_instr
*instr
)
634 struct brw_wm_prog_key
*fs_key
= (struct brw_wm_prog_key
*) this->key
;
637 fs_reg result
= get_nir_dest(instr
->dest
.dest
);
638 result
.type
= brw_type_for_nir_type(
639 (nir_alu_type
)(nir_op_infos
[instr
->op
].output_type
|
640 nir_dest_bit_size(instr
->dest
.dest
)));
643 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
644 op
[i
] = get_nir_src(instr
->src
[i
].src
);
645 op
[i
].type
= brw_type_for_nir_type(
646 (nir_alu_type
)(nir_op_infos
[instr
->op
].input_types
[i
] |
647 nir_src_bit_size(instr
->src
[i
].src
)));
648 op
[i
].abs
= instr
->src
[i
].abs
;
649 op
[i
].negate
= instr
->src
[i
].negate
;
652 /* We get a bunch of mov's out of the from_ssa pass and they may still
653 * be vectorized. We'll handle them as a special-case. We'll also
654 * handle vecN here because it's basically the same thing.
662 fs_reg temp
= result
;
663 bool need_extra_copy
= false;
664 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
665 if (!instr
->src
[i
].src
.is_ssa
&&
666 instr
->dest
.dest
.reg
.reg
== instr
->src
[i
].src
.reg
.reg
) {
667 need_extra_copy
= true;
668 temp
= bld
.vgrf(result
.type
, 4);
673 for (unsigned i
= 0; i
< 4; i
++) {
674 if (!(instr
->dest
.write_mask
& (1 << i
)))
677 if (instr
->op
== nir_op_imov
|| instr
->op
== nir_op_fmov
) {
678 inst
= bld
.MOV(offset(temp
, bld
, i
),
679 offset(op
[0], bld
, instr
->src
[0].swizzle
[i
]));
681 inst
= bld
.MOV(offset(temp
, bld
, i
),
682 offset(op
[i
], bld
, instr
->src
[i
].swizzle
[0]));
684 inst
->saturate
= instr
->dest
.saturate
;
687 /* In this case the source and destination registers were the same,
688 * so we need to insert an extra set of moves in order to deal with
691 if (need_extra_copy
) {
692 for (unsigned i
= 0; i
< 4; i
++) {
693 if (!(instr
->dest
.write_mask
& (1 << i
)))
696 bld
.MOV(offset(result
, bld
, i
), offset(temp
, bld
, i
));
705 /* At this point, we have dealt with any instruction that operates on
706 * more than a single channel. Therefore, we can just adjust the source
707 * and destination registers for that channel and emit the instruction.
709 unsigned channel
= 0;
710 if (nir_op_infos
[instr
->op
].output_size
== 0) {
711 /* Since NIR is doing the scalarizing for us, we should only ever see
712 * vectorized operations with a single channel.
714 assert(_mesa_bitcount(instr
->dest
.write_mask
) == 1);
715 channel
= ffs(instr
->dest
.write_mask
) - 1;
717 result
= offset(result
, bld
, channel
);
720 for (unsigned i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
721 assert(nir_op_infos
[instr
->op
].input_sizes
[i
] < 2);
722 op
[i
] = offset(op
[i
], bld
, instr
->src
[i
].swizzle
[channel
]);
728 if (optimize_extract_to_float(instr
, result
))
737 inst
= bld
.MOV(result
, op
[0]);
738 inst
->saturate
= instr
->dest
.saturate
;
743 bld
.MOV(result
, op
[0]);
747 if (type_sz(op
[0].type
) < 8) {
748 /* AND(val, 0x80000000) gives the sign bit.
750 * Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
753 bld
.CMP(bld
.null_reg_f(), op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
755 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
756 op
[0].type
= BRW_REGISTER_TYPE_UD
;
757 result
.type
= BRW_REGISTER_TYPE_UD
;
758 bld
.AND(result_int
, op
[0], brw_imm_ud(0x80000000u
));
760 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
761 inst
->predicate
= BRW_PREDICATE_NORMAL
;
762 if (instr
->dest
.saturate
) {
763 inst
= bld
.MOV(result
, result
);
764 inst
->saturate
= true;
767 /* For doubles we do the same but we need to consider:
769 * - 2-src instructions can't operate with 64-bit immediates
770 * - The sign is encoded in the high 32-bit of each DF
771 * - CMP with DF requires special handling in SIMD16
772 * - We need to produce a DF result.
775 /* 2-src instructions can't have 64-bit immediates, so put 0.0 in
776 * a register and compare with that.
778 fs_reg tmp
= vgrf(glsl_type::double_type
);
779 bld
.MOV(tmp
, brw_imm_df(0.0));
781 /* A direct DF CMP using the flag register (null dst) won't work in
782 * SIMD16 because the CMP will be split in two by lower_simd_width,
783 * resulting in two CMP instructions with the same dst (NULL),
784 * leading to dead code elimination of the first one. In SIMD8,
785 * however, there is no need to split the CMP and we can save some
788 fs_reg dst_tmp
= vgrf(glsl_type::double_type
);
789 bld
.CMP(dst_tmp
, op
[0], tmp
, BRW_CONDITIONAL_NZ
);
791 /* In SIMD16 we want to avoid using a NULL dst register with DF CMP,
792 * so we store the result of the comparison in a vgrf instead and
793 * then we generate a UD comparison from that that won't have to
794 * be split by lower_simd_width. This is what NIR does to handle
795 * double comparisons in the general case.
797 if (bld
.dispatch_width() == 16 ) {
798 fs_reg dst_tmp_ud
= retype(dst_tmp
, BRW_REGISTER_TYPE_UD
);
799 bld
.MOV(dst_tmp_ud
, subscript(dst_tmp
, BRW_REGISTER_TYPE_UD
, 0));
800 bld
.CMP(bld
.null_reg_ud(),
801 dst_tmp_ud
, brw_imm_ud(0), BRW_CONDITIONAL_NZ
);
804 /* Get the high 32-bit of each double component where the sign is */
805 fs_reg result_int
= retype(result
, BRW_REGISTER_TYPE_UD
);
806 bld
.MOV(result_int
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
808 /* Get the sign bit */
809 bld
.AND(result_int
, result_int
, brw_imm_ud(0x80000000u
));
811 /* Add 1.0 to the sign, predicated to skip the case of op[0] == 0.0 */
812 inst
= bld
.OR(result_int
, result_int
, brw_imm_ud(0x3f800000u
));
813 inst
->predicate
= BRW_PREDICATE_NORMAL
;
815 /* Convert from 32-bit float to 64-bit double */
816 result
.type
= BRW_REGISTER_TYPE_DF
;
817 inst
= bld
.MOV(result
, retype(result_int
, BRW_REGISTER_TYPE_F
));
819 if (instr
->dest
.saturate
) {
820 inst
= bld
.MOV(result
, result
);
821 inst
->saturate
= true;
828 /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
829 * -> non-negative val generates 0x00000000.
830 * Predicated OR sets 1 if val is positive.
832 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
833 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_G
);
834 bld
.ASR(result
, op
[0], brw_imm_d(31));
835 inst
= bld
.OR(result
, result
, brw_imm_d(1));
836 inst
->predicate
= BRW_PREDICATE_NORMAL
;
840 inst
= bld
.emit(SHADER_OPCODE_RCP
, result
, op
[0]);
841 inst
->saturate
= instr
->dest
.saturate
;
845 inst
= bld
.emit(SHADER_OPCODE_EXP2
, result
, op
[0]);
846 inst
->saturate
= instr
->dest
.saturate
;
850 inst
= bld
.emit(SHADER_OPCODE_LOG2
, result
, op
[0]);
851 inst
->saturate
= instr
->dest
.saturate
;
855 inst
= bld
.emit(SHADER_OPCODE_SIN
, result
, op
[0]);
856 inst
->saturate
= instr
->dest
.saturate
;
860 inst
= bld
.emit(SHADER_OPCODE_COS
, result
, op
[0]);
861 inst
->saturate
= instr
->dest
.saturate
;
865 if (fs_key
->high_quality_derivatives
) {
866 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
868 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
870 inst
->saturate
= instr
->dest
.saturate
;
872 case nir_op_fddx_fine
:
873 inst
= bld
.emit(FS_OPCODE_DDX_FINE
, result
, op
[0]);
874 inst
->saturate
= instr
->dest
.saturate
;
876 case nir_op_fddx_coarse
:
877 inst
= bld
.emit(FS_OPCODE_DDX_COARSE
, result
, op
[0]);
878 inst
->saturate
= instr
->dest
.saturate
;
881 if (fs_key
->high_quality_derivatives
) {
882 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
883 brw_imm_d(fs_key
->render_to_fbo
));
885 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
886 brw_imm_d(fs_key
->render_to_fbo
));
888 inst
->saturate
= instr
->dest
.saturate
;
890 case nir_op_fddy_fine
:
891 inst
= bld
.emit(FS_OPCODE_DDY_FINE
, result
, op
[0],
892 brw_imm_d(fs_key
->render_to_fbo
));
893 inst
->saturate
= instr
->dest
.saturate
;
895 case nir_op_fddy_coarse
:
896 inst
= bld
.emit(FS_OPCODE_DDY_COARSE
, result
, op
[0],
897 brw_imm_d(fs_key
->render_to_fbo
));
898 inst
->saturate
= instr
->dest
.saturate
;
902 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
904 inst
= bld
.ADD(result
, op
[0], op
[1]);
905 inst
->saturate
= instr
->dest
.saturate
;
909 inst
= bld
.MUL(result
, op
[0], op
[1]);
910 inst
->saturate
= instr
->dest
.saturate
;
914 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
915 bld
.MUL(result
, op
[0], op
[1]);
918 case nir_op_imul_high
:
919 case nir_op_umul_high
:
920 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
921 bld
.emit(SHADER_OPCODE_MULH
, result
, op
[0], op
[1]);
926 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
927 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, result
, op
[0], op
[1]);
930 case nir_op_uadd_carry
:
931 unreachable("Should have been lowered by carry_to_arith().");
933 case nir_op_usub_borrow
:
934 unreachable("Should have been lowered by borrow_to_arith().");
938 /* According to the sign table for INT DIV in the Ivy Bridge PRM, it
939 * appears that our hardware just does the right thing for signed
942 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
943 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
947 /* Get a regular C-style remainder. If a % b == 0, set the predicate. */
948 bld
.emit(SHADER_OPCODE_INT_REMAINDER
, result
, op
[0], op
[1]);
950 /* Math instructions don't support conditional mod */
951 inst
= bld
.MOV(bld
.null_reg_d(), result
);
952 inst
->conditional_mod
= BRW_CONDITIONAL_NZ
;
954 /* Now, we need to determine if signs of the sources are different.
955 * When we XOR the sources, the top bit is 0 if they are the same and 1
956 * if they are different. We can then use a conditional modifier to
957 * turn that into a predicate. This leads us to an XOR.l instruction.
959 * Technically, according to the PRM, you're not allowed to use .l on a
960 * XOR instruction. However, emperical experiments and Curro's reading
961 * of the simulator source both indicate that it's safe.
963 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
964 inst
= bld
.XOR(tmp
, op
[0], op
[1]);
965 inst
->predicate
= BRW_PREDICATE_NORMAL
;
966 inst
->conditional_mod
= BRW_CONDITIONAL_L
;
968 /* If the result of the initial remainder operation is non-zero and the
969 * two sources have different signs, add in a copy of op[1] to get the
970 * final integer modulus value.
972 inst
= bld
.ADD(result
, result
, op
[1]);
973 inst
->predicate
= BRW_PREDICATE_NORMAL
;
981 fs_reg dest
= result
;
982 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
983 dest
= bld
.vgrf(BRW_REGISTER_TYPE_DF
, 1);
985 brw_conditional_mod cond
;
988 cond
= BRW_CONDITIONAL_L
;
991 cond
= BRW_CONDITIONAL_GE
;
994 cond
= BRW_CONDITIONAL_Z
;
997 cond
= BRW_CONDITIONAL_NZ
;
1000 unreachable("bad opcode");
1002 bld
.CMP(dest
, op
[0], op
[1], cond
);
1003 if (nir_src_bit_size(instr
->src
[0].src
) > 32) {
1004 bld
.MOV(result
, subscript(dest
, BRW_REGISTER_TYPE_UD
, 0));
1011 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1012 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1017 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1018 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1022 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1023 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_Z
);
1027 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1028 bld
.CMP(result
, op
[0], op
[1], BRW_CONDITIONAL_NZ
);
1032 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1033 if (devinfo
->gen
>= 8) {
1034 op
[0] = resolve_source_modifiers(op
[0]);
1036 bld
.NOT(result
, op
[0]);
1039 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1040 if (devinfo
->gen
>= 8) {
1041 op
[0] = resolve_source_modifiers(op
[0]);
1042 op
[1] = resolve_source_modifiers(op
[1]);
1044 bld
.XOR(result
, op
[0], op
[1]);
1047 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1048 if (devinfo
->gen
>= 8) {
1049 op
[0] = resolve_source_modifiers(op
[0]);
1050 op
[1] = resolve_source_modifiers(op
[1]);
1052 bld
.OR(result
, op
[0], op
[1]);
1055 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1056 if (devinfo
->gen
>= 8) {
1057 op
[0] = resolve_source_modifiers(op
[0]);
1058 op
[1] = resolve_source_modifiers(op
[1]);
1060 bld
.AND(result
, op
[0], op
[1]);
1066 case nir_op_ball_fequal2
:
1067 case nir_op_ball_iequal2
:
1068 case nir_op_ball_fequal3
:
1069 case nir_op_ball_iequal3
:
1070 case nir_op_ball_fequal4
:
1071 case nir_op_ball_iequal4
:
1072 case nir_op_bany_fnequal2
:
1073 case nir_op_bany_inequal2
:
1074 case nir_op_bany_fnequal3
:
1075 case nir_op_bany_inequal3
:
1076 case nir_op_bany_fnequal4
:
1077 case nir_op_bany_inequal4
:
1078 unreachable("Lowered by nir_lower_alu_reductions");
1080 case nir_op_fnoise1_1
:
1081 case nir_op_fnoise1_2
:
1082 case nir_op_fnoise1_3
:
1083 case nir_op_fnoise1_4
:
1084 case nir_op_fnoise2_1
:
1085 case nir_op_fnoise2_2
:
1086 case nir_op_fnoise2_3
:
1087 case nir_op_fnoise2_4
:
1088 case nir_op_fnoise3_1
:
1089 case nir_op_fnoise3_2
:
1090 case nir_op_fnoise3_3
:
1091 case nir_op_fnoise3_4
:
1092 case nir_op_fnoise4_1
:
1093 case nir_op_fnoise4_2
:
1094 case nir_op_fnoise4_3
:
1095 case nir_op_fnoise4_4
:
1096 unreachable("not reached: should be handled by lower_noise");
1099 unreachable("not reached: should be handled by ldexp_to_arith()");
1102 inst
= bld
.emit(SHADER_OPCODE_SQRT
, result
, op
[0]);
1103 inst
->saturate
= instr
->dest
.saturate
;
1107 inst
= bld
.emit(SHADER_OPCODE_RSQ
, result
, op
[0]);
1108 inst
->saturate
= instr
->dest
.saturate
;
1113 bld
.MOV(result
, negate(op
[0]));
1117 bld
.CMP(result
, op
[0], brw_imm_f(0.0f
), BRW_CONDITIONAL_NZ
);
1120 /* two-argument instructions can't take 64-bit immediates */
1121 fs_reg zero
= vgrf(glsl_type::double_type
);
1122 bld
.MOV(zero
, brw_imm_df(0.0));
1123 /* A SIMD16 execution needs to be split in two instructions, so use
1124 * a vgrf instead of the flag register as dst so instruction splitting
1127 fs_reg tmp
= vgrf(glsl_type::double_type
);
1128 bld
.CMP(tmp
, op
[0], zero
, BRW_CONDITIONAL_NZ
);
1129 bld
.MOV(result
, subscript(tmp
, BRW_REGISTER_TYPE_UD
, 0));
1133 bld
.CMP(result
, op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1137 inst
= bld
.RNDZ(result
, op
[0]);
1138 inst
->saturate
= instr
->dest
.saturate
;
1141 case nir_op_fceil
: {
1142 op
[0].negate
= !op
[0].negate
;
1143 fs_reg temp
= vgrf(glsl_type::float_type
);
1144 bld
.RNDD(temp
, op
[0]);
1146 inst
= bld
.MOV(result
, temp
);
1147 inst
->saturate
= instr
->dest
.saturate
;
1151 inst
= bld
.RNDD(result
, op
[0]);
1152 inst
->saturate
= instr
->dest
.saturate
;
1155 inst
= bld
.FRC(result
, op
[0]);
1156 inst
->saturate
= instr
->dest
.saturate
;
1158 case nir_op_fround_even
:
1159 inst
= bld
.RNDE(result
, op
[0]);
1160 inst
->saturate
= instr
->dest
.saturate
;
1163 case nir_op_fquantize2f16
: {
1164 fs_reg tmp16
= bld
.vgrf(BRW_REGISTER_TYPE_D
);
1165 fs_reg tmp32
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1166 fs_reg zero
= bld
.vgrf(BRW_REGISTER_TYPE_F
);
1168 /* The destination stride must be at least as big as the source stride. */
1169 tmp16
.type
= BRW_REGISTER_TYPE_W
;
1172 /* Check for denormal */
1173 fs_reg abs_src0
= op
[0];
1174 abs_src0
.abs
= true;
1175 bld
.CMP(bld
.null_reg_f(), abs_src0
, brw_imm_f(ldexpf(1.0, -14)),
1177 /* Get the appropriately signed zero */
1178 bld
.AND(retype(zero
, BRW_REGISTER_TYPE_UD
),
1179 retype(op
[0], BRW_REGISTER_TYPE_UD
),
1180 brw_imm_ud(0x80000000));
1181 /* Do the actual F32 -> F16 -> F32 conversion */
1182 bld
.emit(BRW_OPCODE_F32TO16
, tmp16
, op
[0]);
1183 bld
.emit(BRW_OPCODE_F16TO32
, tmp32
, tmp16
);
1184 /* Select that or zero based on normal status */
1185 inst
= bld
.SEL(result
, zero
, tmp32
);
1186 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1187 inst
->saturate
= instr
->dest
.saturate
;
1193 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1195 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_L
);
1196 inst
->saturate
= instr
->dest
.saturate
;
1201 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1203 inst
= bld
.emit_minmax(result
, op
[0], op
[1], BRW_CONDITIONAL_GE
);
1204 inst
->saturate
= instr
->dest
.saturate
;
1207 case nir_op_pack_snorm_2x16
:
1208 case nir_op_pack_snorm_4x8
:
1209 case nir_op_pack_unorm_2x16
:
1210 case nir_op_pack_unorm_4x8
:
1211 case nir_op_unpack_snorm_2x16
:
1212 case nir_op_unpack_snorm_4x8
:
1213 case nir_op_unpack_unorm_2x16
:
1214 case nir_op_unpack_unorm_4x8
:
1215 case nir_op_unpack_half_2x16
:
1216 case nir_op_pack_half_2x16
:
1217 unreachable("not reached: should be handled by lower_packing_builtins");
1219 case nir_op_unpack_half_2x16_split_x
:
1220 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X
, result
, op
[0]);
1221 inst
->saturate
= instr
->dest
.saturate
;
1223 case nir_op_unpack_half_2x16_split_y
:
1224 inst
= bld
.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y
, result
, op
[0]);
1225 inst
->saturate
= instr
->dest
.saturate
;
1228 case nir_op_pack_double_2x32_split
:
1229 /* Optimize the common case where we are re-packing a double with
1230 * the result of a previous double unpack. In this case we can take the
1231 * 32-bit value to use in the re-pack from the original double and bypass
1232 * the unpack operation.
1234 for (int i
= 0; i
< 2; i
++) {
1235 if (instr
->src
[i
].src
.is_ssa
)
1238 const nir_instr
*parent_instr
= instr
->src
[i
].src
.ssa
->parent_instr
;
1239 if (parent_instr
->type
== nir_instr_type_alu
)
1242 const nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1243 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_x
||
1244 alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1247 if (!alu_parent
->src
[0].src
.is_ssa
)
1250 op
[i
] = get_nir_src(alu_parent
->src
[0].src
);
1251 op
[i
] = offset(retype(op
[i
], BRW_REGISTER_TYPE_DF
), bld
,
1252 alu_parent
->src
[0].swizzle
[channel
]);
1253 if (alu_parent
->op
== nir_op_unpack_double_2x32_split_y
)
1254 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 1);
1256 op
[i
] = subscript(op
[i
], BRW_REGISTER_TYPE_UD
, 0);
1258 bld
.emit(FS_OPCODE_PACK
, result
, op
[0], op
[1]);
1261 case nir_op_unpack_double_2x32_split_x
:
1262 case nir_op_unpack_double_2x32_split_y
: {
1263 /* Optimize the common case where we are unpacking from a double we have
1264 * previously packed. In this case we can just bypass the pack operation
1265 * and source directly from its arguments.
1267 unsigned index
= (instr
->op
== nir_op_unpack_double_2x32_split_x
) ? 0 : 1;
1268 if (instr
->src
[0].src
.is_ssa
) {
1269 nir_instr
*parent_instr
= instr
->src
[0].src
.ssa
->parent_instr
;
1270 if (parent_instr
->type
== nir_instr_type_alu
) {
1271 nir_alu_instr
*alu_parent
= nir_instr_as_alu(parent_instr
);
1272 if (alu_parent
->op
== nir_op_pack_double_2x32_split
&&
1273 alu_parent
->src
[index
].src
.is_ssa
) {
1274 op
[0] = retype(get_nir_src(alu_parent
->src
[index
].src
),
1275 BRW_REGISTER_TYPE_UD
);
1277 offset(op
[0], bld
, alu_parent
->src
[index
].swizzle
[channel
]);
1278 bld
.MOV(result
, op
[0]);
1284 if (instr
->op
== nir_op_unpack_double_2x32_split_x
)
1285 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 0));
1287 bld
.MOV(result
, subscript(op
[0], BRW_REGISTER_TYPE_UD
, 1));
1292 inst
= bld
.emit(SHADER_OPCODE_POW
, result
, op
[0], op
[1]);
1293 inst
->saturate
= instr
->dest
.saturate
;
1296 case nir_op_bitfield_reverse
:
1297 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1298 bld
.BFREV(result
, op
[0]);
1301 case nir_op_bit_count
:
1302 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1303 bld
.CBIT(result
, op
[0]);
1306 case nir_op_ufind_msb
:
1307 case nir_op_ifind_msb
: {
1308 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1309 bld
.FBH(retype(result
, BRW_REGISTER_TYPE_UD
), op
[0]);
1311 /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
1312 * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
1313 * subtract the result from 31 to convert the MSB count into an LSB count.
1315 bld
.CMP(bld
.null_reg_d(), result
, brw_imm_d(-1), BRW_CONDITIONAL_NZ
);
1317 inst
= bld
.ADD(result
, result
, brw_imm_d(31));
1318 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1319 inst
->src
[0].negate
= true;
1323 case nir_op_find_lsb
:
1324 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1325 bld
.FBL(result
, op
[0]);
1328 case nir_op_ubitfield_extract
:
1329 case nir_op_ibitfield_extract
:
1330 unreachable("should have been lowered");
1333 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1334 bld
.BFE(result
, op
[2], op
[1], op
[0]);
1337 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1338 bld
.BFI1(result
, op
[0], op
[1]);
1341 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1342 bld
.BFI2(result
, op
[0], op
[1], op
[2]);
1345 case nir_op_bitfield_insert
:
1346 unreachable("not reached: should have been lowered");
1349 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1350 bld
.SHL(result
, op
[0], op
[1]);
1353 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1354 bld
.ASR(result
, op
[0], op
[1]);
1357 assert(nir_dest_bit_size(instr
->dest
.dest
) < 64);
1358 bld
.SHR(result
, op
[0], op
[1]);
1361 case nir_op_pack_half_2x16_split
:
1362 bld
.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT
, result
, op
[0], op
[1]);
1366 inst
= bld
.MAD(result
, op
[2], op
[1], op
[0]);
1367 inst
->saturate
= instr
->dest
.saturate
;
1371 inst
= bld
.LRP(result
, op
[0], op
[1], op
[2]);
1372 inst
->saturate
= instr
->dest
.saturate
;
1376 if (optimize_frontfacing_ternary(instr
, result
))
1379 bld
.CMP(bld
.null_reg_d(), op
[0], brw_imm_d(0), BRW_CONDITIONAL_NZ
);
1380 inst
= bld
.SEL(result
, op
[1], op
[2]);
1381 inst
->predicate
= BRW_PREDICATE_NORMAL
;
1384 case nir_op_extract_u8
:
1385 case nir_op_extract_i8
: {
1386 nir_const_value
*byte
= nir_src_as_const_value(instr
->src
[1].src
);
1387 bld
.emit(SHADER_OPCODE_EXTRACT_BYTE
,
1388 result
, op
[0], brw_imm_ud(byte
->u32
[0]));
1392 case nir_op_extract_u16
:
1393 case nir_op_extract_i16
: {
1394 nir_const_value
*word
= nir_src_as_const_value(instr
->src
[1].src
);
1395 bld
.emit(SHADER_OPCODE_EXTRACT_WORD
,
1396 result
, op
[0], brw_imm_ud(word
->u32
[0]));
1401 unreachable("unhandled instruction");
1404 /* If we need to do a boolean resolve, replace the result with -(x & 1)
1405 * to sign extend the low bit to 0/~0
1407 if (devinfo
->gen
<= 5 &&
1408 (instr
->instr
.pass_flags
& BRW_NIR_BOOLEAN_MASK
) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE
) {
1409 fs_reg masked
= vgrf(glsl_type::int_type
);
1410 bld
.AND(masked
, result
, brw_imm_d(1));
1411 masked
.negate
= true;
1412 bld
.MOV(retype(result
, BRW_REGISTER_TYPE_D
), masked
);
1417 fs_visitor::nir_emit_load_const(const fs_builder
&bld
,
1418 nir_load_const_instr
*instr
)
1420 const brw_reg_type reg_type
=
1421 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1422 fs_reg reg
= bld
.vgrf(reg_type
, instr
->def
.num_components
);
1424 switch (instr
->def
.bit_size
) {
1426 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1427 bld
.MOV(offset(reg
, bld
, i
), brw_imm_d(instr
->value
.i32
[i
]));
1431 for (unsigned i
= 0; i
< instr
->def
.num_components
; i
++)
1432 bld
.MOV(offset(reg
, bld
, i
), brw_imm_df(instr
->value
.f64
[i
]));
1436 unreachable("Invalid bit size");
1439 nir_ssa_values
[instr
->def
.index
] = reg
;
1443 fs_visitor::nir_emit_undef(const fs_builder
&bld
, nir_ssa_undef_instr
*instr
)
1445 const brw_reg_type reg_type
=
1446 instr
->def
.bit_size
== 32 ? BRW_REGISTER_TYPE_D
: BRW_REGISTER_TYPE_DF
;
1447 nir_ssa_values
[instr
->def
.index
] =
1448 bld
.vgrf(reg_type
, instr
->def
.num_components
);
1452 fs_visitor::get_nir_src(nir_src src
)
1456 reg
= nir_ssa_values
[src
.ssa
->index
];
1458 /* We don't handle indirects on locals */
1459 assert(src
.reg
.indirect
== NULL
);
1460 reg
= offset(nir_locals
[src
.reg
.reg
->index
], bld
,
1461 src
.reg
.base_offset
* src
.reg
.reg
->num_components
);
1464 /* to avoid floating-point denorm flushing problems, set the type by
1465 * default to D - instructions that need floating point semantics will set
1466 * this to F if they need to
1468 return retype(reg
, BRW_REGISTER_TYPE_D
);
1472 fs_visitor::get_nir_dest(nir_dest dest
)
1475 const brw_reg_type reg_type
=
1476 dest
.ssa
.bit_size
== 32 ? BRW_REGISTER_TYPE_F
: BRW_REGISTER_TYPE_DF
;
1477 nir_ssa_values
[dest
.ssa
.index
] =
1478 bld
.vgrf(reg_type
, dest
.ssa
.num_components
);
1479 return nir_ssa_values
[dest
.ssa
.index
];
1481 /* We don't handle indirects on locals */
1482 assert(dest
.reg
.indirect
== NULL
);
1483 return offset(nir_locals
[dest
.reg
.reg
->index
], bld
,
1484 dest
.reg
.base_offset
* dest
.reg
.reg
->num_components
);
1489 fs_visitor::get_nir_image_deref(const nir_deref_var
*deref
)
1491 fs_reg
image(UNIFORM
, deref
->var
->data
.driver_location
/ 4,
1492 BRW_REGISTER_TYPE_UD
);
1494 unsigned indirect_max
= 0;
1496 for (const nir_deref
*tail
= &deref
->deref
; tail
->child
;
1497 tail
= tail
->child
) {
1498 const nir_deref_array
*deref_array
= nir_deref_as_array(tail
->child
);
1499 assert(tail
->child
->deref_type
== nir_deref_type_array
);
1500 const unsigned size
= glsl_get_length(tail
->type
);
1501 const unsigned element_size
= type_size_scalar(deref_array
->deref
.type
);
1502 const unsigned base
= MIN2(deref_array
->base_offset
, size
- 1);
1503 image
= offset(image
, bld
, base
* element_size
);
1505 if (deref_array
->deref_array_type
== nir_deref_array_type_indirect
) {
1506 fs_reg tmp
= vgrf(glsl_type::uint_type
);
1508 /* Accessing an invalid surface index with the dataport can result
1509 * in a hang. According to the spec "if the index used to
1510 * select an individual element is negative or greater than or
1511 * equal to the size of the array, the results of the operation
1512 * are undefined but may not lead to termination" -- which is one
1513 * of the possible outcomes of the hang. Clamp the index to
1514 * prevent access outside of the array bounds.
1516 bld
.emit_minmax(tmp
, retype(get_nir_src(deref_array
->indirect
),
1517 BRW_REGISTER_TYPE_UD
),
1518 brw_imm_ud(size
- base
- 1), BRW_CONDITIONAL_L
);
1520 indirect_max
+= element_size
* (tail
->type
->length
- 1);
1522 bld
.MUL(tmp
, tmp
, brw_imm_ud(element_size
* 4));
1523 if (indirect
.file
== BAD_FILE
) {
1526 bld
.ADD(indirect
, indirect
, tmp
);
1531 if (indirect
.file
== BAD_FILE
) {
1534 /* Emit a pile of MOVs to load the uniform into a temporary. The
1535 * dead-code elimination pass will get rid of what we don't use.
1537 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, BRW_IMAGE_PARAM_SIZE
);
1538 for (unsigned j
= 0; j
< BRW_IMAGE_PARAM_SIZE
; j
++) {
1539 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
1540 offset(tmp
, bld
, j
), offset(image
, bld
, j
),
1541 indirect
, brw_imm_ud((indirect_max
+ 1) * 4));
1548 fs_visitor::emit_percomp(const fs_builder
&bld
, const fs_inst
&inst
,
1551 for (unsigned i
= 0; i
< 4; i
++) {
1552 if (!((wr_mask
>> i
) & 1))
1555 fs_inst
*new_inst
= new(mem_ctx
) fs_inst(inst
);
1556 new_inst
->dst
= offset(new_inst
->dst
, bld
, i
);
1557 for (unsigned j
= 0; j
< new_inst
->sources
; j
++)
1558 if (new_inst
->src
[j
].file
== VGRF
)
1559 new_inst
->src
[j
] = offset(new_inst
->src
[j
], bld
, i
);
1566 * Get the matching channel register datatype for an image intrinsic of the
1567 * specified GLSL image type.
1570 get_image_base_type(const glsl_type
*type
)
1572 switch ((glsl_base_type
)type
->sampled_type
) {
1573 case GLSL_TYPE_UINT
:
1574 return BRW_REGISTER_TYPE_UD
;
1576 return BRW_REGISTER_TYPE_D
;
1577 case GLSL_TYPE_FLOAT
:
1578 return BRW_REGISTER_TYPE_F
;
1580 unreachable("Not reached.");
1585 * Get the appropriate atomic op for an image atomic intrinsic.
1588 get_image_atomic_op(nir_intrinsic_op op
, const glsl_type
*type
)
1591 case nir_intrinsic_image_atomic_add
:
1593 case nir_intrinsic_image_atomic_min
:
1594 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1595 BRW_AOP_IMIN
: BRW_AOP_UMIN
);
1596 case nir_intrinsic_image_atomic_max
:
1597 return (get_image_base_type(type
) == BRW_REGISTER_TYPE_D
?
1598 BRW_AOP_IMAX
: BRW_AOP_UMAX
);
1599 case nir_intrinsic_image_atomic_and
:
1601 case nir_intrinsic_image_atomic_or
:
1603 case nir_intrinsic_image_atomic_xor
:
1605 case nir_intrinsic_image_atomic_exchange
:
1607 case nir_intrinsic_image_atomic_comp_swap
:
1608 return BRW_AOP_CMPWR
;
1610 unreachable("Not reachable.");
1615 emit_pixel_interpolater_send(const fs_builder
&bld
,
1620 glsl_interp_qualifier interpolation
)
1626 if (src
.file
== BAD_FILE
) {
1628 payload
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 1);
1632 mlen
= 2 * bld
.dispatch_width() / 8;
1635 inst
= bld
.emit(opcode
, dst
, payload
, desc
);
1637 /* 2 floats per slot returned */
1638 inst
->regs_written
= 2 * bld
.dispatch_width() / 8;
1639 inst
->pi_noperspective
= interpolation
== INTERP_QUALIFIER_NOPERSPECTIVE
;
1645 * Computes 1 << x, given a D/UD register containing some value x.
1648 intexp2(const fs_builder
&bld
, const fs_reg
&x
)
1650 assert(x
.type
== BRW_REGISTER_TYPE_UD
|| x
.type
== BRW_REGISTER_TYPE_D
);
1652 fs_reg result
= bld
.vgrf(x
.type
, 1);
1653 fs_reg one
= bld
.vgrf(x
.type
, 1);
1655 bld
.MOV(one
, retype(brw_imm_d(1), one
.type
));
1656 bld
.SHL(result
, one
, x
);
1661 fs_visitor::emit_gs_end_primitive(const nir_src
&vertex_count_nir_src
)
1663 assert(stage
== MESA_SHADER_GEOMETRY
);
1665 struct brw_gs_prog_data
*gs_prog_data
=
1666 (struct brw_gs_prog_data
*) prog_data
;
1668 /* We can only do EndPrimitive() functionality when the control data
1669 * consists of cut bits. Fortunately, the only time it isn't is when the
1670 * output type is points, in which case EndPrimitive() is a no-op.
1672 if (gs_prog_data
->control_data_format
!=
1673 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT
) {
1677 /* Cut bits use one bit per vertex. */
1678 assert(gs_compile
->control_data_bits_per_vertex
== 1);
1680 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1681 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1683 /* Cut bit n should be set to 1 if EndPrimitive() was called after emitting
1684 * vertex n, 0 otherwise. So all we need to do here is mark bit
1685 * (vertex_count - 1) % 32 in the cut_bits register to indicate that
1686 * EndPrimitive() was called after emitting vertex (vertex_count - 1);
1687 * vec4_gs_visitor::emit_control_data_bits() will take care of the rest.
1689 * Note that if EndPrimitive() is called before emitting any vertices, this
1690 * will cause us to set bit 31 of the control_data_bits register to 1.
1691 * That's fine because:
1693 * - If max_vertices < 32, then vertex number 31 (zero-based) will never be
1694 * output, so the hardware will ignore cut bit 31.
1696 * - If max_vertices == 32, then vertex number 31 is guaranteed to be the
1697 * last vertex, so setting cut bit 31 has no effect (since the primitive
1698 * is automatically ended when the GS terminates).
1700 * - If max_vertices > 32, then the ir_emit_vertex visitor will reset the
1701 * control_data_bits register to 0 when the first vertex is emitted.
1704 const fs_builder abld
= bld
.annotate("end primitive");
1706 /* control_data_bits |= 1 << ((vertex_count - 1) % 32) */
1707 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1708 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1709 fs_reg mask
= intexp2(abld
, prev_count
);
1710 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1711 * attention to the lower 5 bits of its second source argument, so on this
1712 * architecture, 1 << (vertex_count - 1) is equivalent to 1 <<
1713 * ((vertex_count - 1) % 32).
1715 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1719 fs_visitor::emit_gs_control_data_bits(const fs_reg
&vertex_count
)
1721 assert(stage
== MESA_SHADER_GEOMETRY
);
1722 assert(gs_compile
->control_data_bits_per_vertex
!= 0);
1724 struct brw_gs_prog_data
*gs_prog_data
=
1725 (struct brw_gs_prog_data
*) prog_data
;
1727 const fs_builder abld
= bld
.annotate("emit control data bits");
1728 const fs_builder fwa_bld
= bld
.exec_all();
1730 /* We use a single UD register to accumulate control data bits (32 bits
1731 * for each of the SIMD8 channels). So we need to write a DWord (32 bits)
1734 * Unfortunately, the URB_WRITE_SIMD8 message uses 128-bit (OWord) offsets.
1735 * We have select a 128-bit group via the Global and Per-Slot Offsets, then
1736 * use the Channel Mask phase to enable/disable which DWord within that
1737 * group to write. (Remember, different SIMD8 channels may have emitted
1738 * different numbers of vertices, so we may need per-slot offsets.)
1740 * Channel masking presents an annoying problem: we may have to replicate
1741 * the data up to 4 times:
1743 * Msg = Handles, Per-Slot Offsets, Channel Masks, Data, Data, Data, Data.
1745 * To avoid penalizing shaders that emit a small number of vertices, we
1746 * can avoid these sometimes: if the size of the control data header is
1747 * <= 128 bits, then there is only 1 OWord. All SIMD8 channels will land
1748 * land in the same 128-bit group, so we can skip per-slot offsets.
1750 * Similarly, if the control data header is <= 32 bits, there is only one
1751 * DWord, so we can skip channel masks.
1753 enum opcode opcode
= SHADER_OPCODE_URB_WRITE_SIMD8
;
1755 fs_reg channel_mask
, per_slot_offset
;
1757 if (gs_compile
->control_data_header_size_bits
> 32) {
1758 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
1759 channel_mask
= vgrf(glsl_type::uint_type
);
1762 if (gs_compile
->control_data_header_size_bits
> 128) {
1763 opcode
= SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
;
1764 per_slot_offset
= vgrf(glsl_type::uint_type
);
1767 /* Figure out which DWord we're trying to write to using the formula:
1769 * dword_index = (vertex_count - 1) * bits_per_vertex / 32
1771 * Since bits_per_vertex is a power of two, and is known at compile
1772 * time, this can be optimized to:
1774 * dword_index = (vertex_count - 1) >> (6 - log2(bits_per_vertex))
1776 if (opcode
!= SHADER_OPCODE_URB_WRITE_SIMD8
) {
1777 fs_reg dword_index
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1778 fs_reg prev_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1779 abld
.ADD(prev_count
, vertex_count
, brw_imm_ud(0xffffffffu
));
1780 unsigned log2_bits_per_vertex
=
1781 _mesa_fls(gs_compile
->control_data_bits_per_vertex
);
1782 abld
.SHR(dword_index
, prev_count
, brw_imm_ud(6u - log2_bits_per_vertex
));
1784 if (per_slot_offset
.file
!= BAD_FILE
) {
1785 /* Set the per-slot offset to dword_index / 4, so that we'll write to
1786 * the appropriate OWord within the control data header.
1788 abld
.SHR(per_slot_offset
, dword_index
, brw_imm_ud(2u));
1791 /* Set the channel masks to 1 << (dword_index % 4), so that we'll
1792 * write to the appropriate DWORD within the OWORD.
1794 fs_reg channel
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1795 fwa_bld
.AND(channel
, dword_index
, brw_imm_ud(3u));
1796 channel_mask
= intexp2(fwa_bld
, channel
);
1797 /* Then the channel masks need to be in bits 23:16. */
1798 fwa_bld
.SHL(channel_mask
, channel_mask
, brw_imm_ud(16u));
1801 /* Store the control data bits in the message payload and send it. */
1803 if (channel_mask
.file
!= BAD_FILE
)
1804 mlen
+= 4; /* channel masks, plus 3 extra copies of the data */
1805 if (per_slot_offset
.file
!= BAD_FILE
)
1808 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
1809 fs_reg
*sources
= ralloc_array(mem_ctx
, fs_reg
, mlen
);
1811 sources
[i
++] = fs_reg(retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
));
1812 if (per_slot_offset
.file
!= BAD_FILE
)
1813 sources
[i
++] = per_slot_offset
;
1814 if (channel_mask
.file
!= BAD_FILE
)
1815 sources
[i
++] = channel_mask
;
1817 sources
[i
++] = this->control_data_bits
;
1820 abld
.LOAD_PAYLOAD(payload
, sources
, mlen
, mlen
);
1821 fs_inst
*inst
= abld
.emit(opcode
, reg_undef
, payload
);
1823 /* We need to increment Global Offset by 256-bits to make room for
1824 * Broadwell's extra "Vertex Count" payload at the beginning of the
1825 * URB entry. Since this is an OWord message, Global Offset is counted
1826 * in 128-bit units, so we must set it to 2.
1828 if (gs_prog_data
->static_vertex_count
== -1)
1833 fs_visitor::set_gs_stream_control_data_bits(const fs_reg
&vertex_count
,
1836 /* control_data_bits |= stream_id << ((2 * (vertex_count - 1)) % 32) */
1838 /* Note: we are calling this *before* increasing vertex_count, so
1839 * this->vertex_count == vertex_count - 1 in the formula above.
1842 /* Stream mode uses 2 bits per vertex */
1843 assert(gs_compile
->control_data_bits_per_vertex
== 2);
1845 /* Must be a valid stream */
1846 assert(stream_id
>= 0 && stream_id
< MAX_VERTEX_STREAMS
);
1848 /* Control data bits are initialized to 0 so we don't have to set any
1849 * bits when sending vertices to stream 0.
1854 const fs_builder abld
= bld
.annotate("set stream control data bits", NULL
);
1856 /* reg::sid = stream_id */
1857 fs_reg sid
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1858 abld
.MOV(sid
, brw_imm_ud(stream_id
));
1860 /* reg:shift_count = 2 * (vertex_count - 1) */
1861 fs_reg shift_count
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1862 abld
.SHL(shift_count
, vertex_count
, brw_imm_ud(1u));
1864 /* Note: we're relying on the fact that the GEN SHL instruction only pays
1865 * attention to the lower 5 bits of its second source argument, so on this
1866 * architecture, stream_id << 2 * (vertex_count - 1) is equivalent to
1867 * stream_id << ((2 * (vertex_count - 1)) % 32).
1869 fs_reg mask
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
1870 abld
.SHL(mask
, sid
, shift_count
);
1871 abld
.OR(this->control_data_bits
, this->control_data_bits
, mask
);
1875 fs_visitor::emit_gs_vertex(const nir_src
&vertex_count_nir_src
,
1878 assert(stage
== MESA_SHADER_GEOMETRY
);
1880 struct brw_gs_prog_data
*gs_prog_data
=
1881 (struct brw_gs_prog_data
*) prog_data
;
1883 fs_reg vertex_count
= get_nir_src(vertex_count_nir_src
);
1884 vertex_count
.type
= BRW_REGISTER_TYPE_UD
;
1886 /* Haswell and later hardware ignores the "Render Stream Select" bits
1887 * from the 3DSTATE_STREAMOUT packet when the SOL stage is disabled,
1888 * and instead sends all primitives down the pipeline for rasterization.
1889 * If the SOL stage is enabled, "Render Stream Select" is honored and
1890 * primitives bound to non-zero streams are discarded after stream output.
1892 * Since the only purpose of primives sent to non-zero streams is to
1893 * be recorded by transform feedback, we can simply discard all geometry
1894 * bound to these streams when transform feedback is disabled.
1896 if (stream_id
> 0 && !nir
->info
.has_transform_feedback_varyings
)
1899 /* If we're outputting 32 control data bits or less, then we can wait
1900 * until the shader is over to output them all. Otherwise we need to
1901 * output them as we go. Now is the time to do it, since we're about to
1902 * output the vertex_count'th vertex, so it's guaranteed that the
1903 * control data bits associated with the (vertex_count - 1)th vertex are
1906 if (gs_compile
->control_data_header_size_bits
> 32) {
1907 const fs_builder abld
=
1908 bld
.annotate("emit vertex: emit control data bits");
1910 /* Only emit control data bits if we've finished accumulating a batch
1911 * of 32 bits. This is the case when:
1913 * (vertex_count * bits_per_vertex) % 32 == 0
1915 * (in other words, when the last 5 bits of vertex_count *
1916 * bits_per_vertex are 0). Assuming bits_per_vertex == 2^n for some
1917 * integer n (which is always the case, since bits_per_vertex is
1918 * always 1 or 2), this is equivalent to requiring that the last 5-n
1919 * bits of vertex_count are 0:
1921 * vertex_count & (2^(5-n) - 1) == 0
1923 * 2^(5-n) == 2^5 / 2^n == 32 / bits_per_vertex, so this is
1926 * vertex_count & (32 / bits_per_vertex - 1) == 0
1928 * TODO: If vertex_count is an immediate, we could do some of this math
1929 * at compile time...
1932 abld
.AND(bld
.null_reg_d(), vertex_count
,
1933 brw_imm_ud(32u / gs_compile
->control_data_bits_per_vertex
- 1u));
1934 inst
->conditional_mod
= BRW_CONDITIONAL_Z
;
1936 abld
.IF(BRW_PREDICATE_NORMAL
);
1937 /* If vertex_count is 0, then no control data bits have been
1938 * accumulated yet, so we can skip emitting them.
1940 abld
.CMP(bld
.null_reg_d(), vertex_count
, brw_imm_ud(0u),
1941 BRW_CONDITIONAL_NEQ
);
1942 abld
.IF(BRW_PREDICATE_NORMAL
);
1943 emit_gs_control_data_bits(vertex_count
);
1944 abld
.emit(BRW_OPCODE_ENDIF
);
1946 /* Reset control_data_bits to 0 so we can start accumulating a new
1949 * Note: in the case where vertex_count == 0, this neutralizes the
1950 * effect of any call to EndPrimitive() that the shader may have
1951 * made before outputting its first vertex.
1953 inst
= abld
.MOV(this->control_data_bits
, brw_imm_ud(0u));
1954 inst
->force_writemask_all
= true;
1955 abld
.emit(BRW_OPCODE_ENDIF
);
1958 emit_urb_writes(vertex_count
);
1960 /* In stream mode we have to set control data bits for all vertices
1961 * unless we have disabled control data bits completely (which we do
1962 * do for GL_POINTS outputs that don't use streams).
1964 if (gs_compile
->control_data_header_size_bits
> 0 &&
1965 gs_prog_data
->control_data_format
==
1966 GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
) {
1967 set_gs_stream_control_data_bits(vertex_count
, stream_id
);
1972 fs_visitor::emit_gs_input_load(const fs_reg
&dst
,
1973 const nir_src
&vertex_src
,
1974 unsigned base_offset
,
1975 const nir_src
&offset_src
,
1976 unsigned num_components
)
1978 struct brw_gs_prog_data
*gs_prog_data
= (struct brw_gs_prog_data
*) prog_data
;
1980 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
1981 nir_const_value
*offset_const
= nir_src_as_const_value(offset_src
);
1982 const unsigned push_reg_count
= gs_prog_data
->base
.urb_read_length
* 8;
1984 /* Offset 0 is the VUE header, which contains VARYING_SLOT_LAYER [.y],
1985 * VARYING_SLOT_VIEWPORT [.z], and VARYING_SLOT_PSIZ [.w]. Only
1986 * gl_PointSize is available as a GS input, however, so it must be that.
1988 const bool is_point_size
= (base_offset
== 0);
1990 /* TODO: figure out push input layout for invocations == 1 */
1991 if (gs_prog_data
->invocations
== 1 &&
1992 offset_const
!= NULL
&& vertex_const
!= NULL
&&
1993 4 * (base_offset
+ offset_const
->u32
[0]) < push_reg_count
) {
1994 int imm_offset
= (base_offset
+ offset_const
->u32
[0]) * 4 +
1995 vertex_const
->u32
[0] * push_reg_count
;
1996 /* This input was pushed into registers. */
1997 if (is_point_size
) {
1998 /* gl_PointSize comes in .w */
1999 bld
.MOV(dst
, fs_reg(ATTR
, imm_offset
+ 3, dst
.type
));
2001 for (unsigned i
= 0; i
< num_components
; i
++) {
2002 bld
.MOV(offset(dst
, bld
, i
),
2003 fs_reg(ATTR
, imm_offset
+ i
, dst
.type
));
2009 /* Resort to the pull model. Ensure the VUE handles are provided. */
2010 gs_prog_data
->base
.include_vue_handles
= true;
2012 unsigned first_icp_handle
= gs_prog_data
->include_primitive_id
? 3 : 2;
2013 fs_reg icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2015 if (gs_prog_data
->invocations
== 1) {
2017 /* The vertex index is constant; just select the proper URB handle. */
2019 retype(brw_vec8_grf(first_icp_handle
+ vertex_const
->i32
[0], 0),
2020 BRW_REGISTER_TYPE_UD
);
2022 /* The vertex index is non-constant. We need to use indirect
2023 * addressing to fetch the proper URB handle.
2025 * First, we start with the sequence <7, 6, 5, 4, 3, 2, 1, 0>
2026 * indicating that channel <n> should read the handle from
2027 * DWord <n>. We convert that to bytes by multiplying by 4.
2029 * Next, we convert the vertex index to bytes by multiplying
2030 * by 32 (shifting by 5), and add the two together. This is
2031 * the final indirect byte offset.
2033 fs_reg sequence
= bld
.vgrf(BRW_REGISTER_TYPE_W
, 1);
2034 fs_reg channel_offsets
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2035 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2036 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2038 /* sequence = <7, 6, 5, 4, 3, 2, 1, 0> */
2039 bld
.MOV(sequence
, fs_reg(brw_imm_v(0x76543210)));
2040 /* channel_offsets = 4 * sequence = <28, 24, 20, 16, 12, 8, 4, 0> */
2041 bld
.SHL(channel_offsets
, sequence
, brw_imm_ud(2u));
2042 /* Convert vertex_index to bytes (multiply by 32) */
2043 bld
.SHL(vertex_offset_bytes
,
2044 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2046 bld
.ADD(icp_offset_bytes
, vertex_offset_bytes
, channel_offsets
);
2048 /* Use first_icp_handle as the base offset. There is one register
2049 * of URB handles per vertex, so inform the register allocator that
2050 * we might read up to nir->info.gs.vertices_in registers.
2052 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2053 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2054 fs_reg(icp_offset_bytes
),
2055 brw_imm_ud(nir
->info
.gs
.vertices_in
* REG_SIZE
));
2058 assert(gs_prog_data
->invocations
> 1);
2061 assert(devinfo
->gen
>= 9 || vertex_const
->i32
[0] <= 5);
2063 retype(brw_vec1_grf(first_icp_handle
+
2064 vertex_const
->i32
[0] / 8,
2065 vertex_const
->i32
[0] % 8),
2066 BRW_REGISTER_TYPE_UD
));
2068 /* The vertex index is non-constant. We need to use indirect
2069 * addressing to fetch the proper URB handle.
2072 fs_reg icp_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2074 /* Convert vertex_index to bytes (multiply by 4) */
2075 bld
.SHL(icp_offset_bytes
,
2076 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2079 /* Use first_icp_handle as the base offset. There is one DWord
2080 * of URB handles per vertex, so inform the register allocator that
2081 * we might read up to ceil(nir->info.gs.vertices_in / 8) registers.
2083 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2084 fs_reg(brw_vec8_grf(first_icp_handle
, 0)),
2085 fs_reg(icp_offset_bytes
),
2086 brw_imm_ud(DIV_ROUND_UP(nir
->info
.gs
.vertices_in
, 8) *
2093 /* Constant indexing - use global offset. */
2094 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2095 inst
->offset
= base_offset
+ offset_const
->u32
[0];
2096 inst
->base_mrf
= -1;
2098 inst
->regs_written
= num_components
;
2100 /* Indirect indexing - use per-slot offsets as well. */
2101 const fs_reg srcs
[] = { icp_handle
, get_nir_src(offset_src
) };
2102 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2103 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2105 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2106 inst
->offset
= base_offset
;
2107 inst
->base_mrf
= -1;
2109 inst
->regs_written
= num_components
;
2112 if (is_point_size
) {
2113 /* Read the whole VUE header (because of alignment) and read .w. */
2114 fs_reg tmp
= bld
.vgrf(dst
.type
, 4);
2116 inst
->regs_written
= 4;
2117 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2122 fs_visitor::get_indirect_offset(nir_intrinsic_instr
*instr
)
2124 nir_src
*offset_src
= nir_get_io_offset_src(instr
);
2125 nir_const_value
*const_value
= nir_src_as_const_value(*offset_src
);
2128 /* The only constant offset we should find is 0. brw_nir.c's
2129 * add_const_offset_to_base() will fold other constant offsets
2130 * into instr->const_index[0].
2132 assert(const_value
->u32
[0] == 0);
2136 return get_nir_src(*offset_src
);
2140 do_untyped_vector_read(const fs_builder
&bld
,
2142 const fs_reg surf_index
,
2143 const fs_reg offset_reg
,
2144 unsigned num_components
)
2146 if (type_sz(dest
.type
) == 4) {
2147 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, offset_reg
,
2150 BRW_PREDICATE_NONE
);
2151 read_result
.type
= dest
.type
;
2152 for (unsigned i
= 0; i
< num_components
; i
++)
2153 bld
.MOV(offset(dest
, bld
, i
), offset(read_result
, bld
, i
));
2154 } else if (type_sz(dest
.type
) == 8) {
2155 /* Reading a dvec, so we need to:
2157 * 1. Multiply num_components by 2, to account for the fact that we
2158 * need to read 64-bit components.
2159 * 2. Shuffle the result of the load to form valid 64-bit elements
2160 * 3. Emit a second load (for components z/w) if needed.
2162 fs_reg read_offset
= bld
.vgrf(BRW_REGISTER_TYPE_UD
);
2163 bld
.MOV(read_offset
, offset_reg
);
2165 int iters
= num_components
<= 2 ? 1 : 2;
2167 /* Load the dvec, the first iteration loads components x/y, the second
2168 * iteration, if needed, loads components z/w
2170 for (int it
= 0; it
< iters
; it
++) {
2171 /* Compute number of components to read in this iteration */
2172 int iter_components
= MIN2(2, num_components
);
2173 num_components
-= iter_components
;
2175 /* Read. Since this message reads 32-bit components, we need to
2176 * read twice as many components.
2178 fs_reg read_result
= emit_untyped_read(bld
, surf_index
, read_offset
,
2180 iter_components
* 2,
2181 BRW_PREDICATE_NONE
);
2183 /* Shuffle the 32-bit load result into valid 64-bit data */
2184 const fs_reg packed_result
= bld
.vgrf(dest
.type
, iter_components
);
2185 shuffle_32bit_load_result_to_64bit_data(
2186 bld
, packed_result
, read_result
, iter_components
);
2188 /* Move each component to its destination */
2189 read_result
= retype(read_result
, BRW_REGISTER_TYPE_DF
);
2190 for (int c
= 0; c
< iter_components
; c
++) {
2191 bld
.MOV(offset(dest
, bld
, it
* 2 + c
),
2192 offset(packed_result
, bld
, c
));
2195 bld
.ADD(read_offset
, read_offset
, brw_imm_ud(16));
2198 unreachable("Unsupported type");
2203 fs_visitor::nir_emit_vs_intrinsic(const fs_builder
&bld
,
2204 nir_intrinsic_instr
*instr
)
2206 assert(stage
== MESA_SHADER_VERTEX
);
2209 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2210 dest
= get_nir_dest(instr
->dest
);
2212 switch (instr
->intrinsic
) {
2213 case nir_intrinsic_load_vertex_id
:
2214 unreachable("should be lowered by lower_vertex_id()");
2216 case nir_intrinsic_load_vertex_id_zero_base
:
2217 case nir_intrinsic_load_base_vertex
:
2218 case nir_intrinsic_load_instance_id
:
2219 case nir_intrinsic_load_base_instance
:
2220 case nir_intrinsic_load_draw_id
: {
2221 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2222 fs_reg val
= nir_system_values
[sv
];
2223 assert(val
.file
!= BAD_FILE
);
2224 dest
.type
= val
.type
;
2230 nir_emit_intrinsic(bld
, instr
);
2236 fs_visitor::nir_emit_tcs_intrinsic(const fs_builder
&bld
,
2237 nir_intrinsic_instr
*instr
)
2239 assert(stage
== MESA_SHADER_TESS_CTRL
);
2240 struct brw_tcs_prog_key
*tcs_key
= (struct brw_tcs_prog_key
*) key
;
2241 struct brw_tcs_prog_data
*tcs_prog_data
=
2242 (struct brw_tcs_prog_data
*) prog_data
;
2245 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2246 dst
= get_nir_dest(instr
->dest
);
2248 switch (instr
->intrinsic
) {
2249 case nir_intrinsic_load_primitive_id
:
2250 bld
.MOV(dst
, fs_reg(brw_vec1_grf(0, 1)));
2252 case nir_intrinsic_load_invocation_id
:
2253 bld
.MOV(retype(dst
, invocation_id
.type
), invocation_id
);
2255 case nir_intrinsic_load_patch_vertices_in
:
2256 bld
.MOV(retype(dst
, BRW_REGISTER_TYPE_D
),
2257 brw_imm_d(tcs_key
->input_vertices
));
2260 case nir_intrinsic_barrier
: {
2261 if (tcs_prog_data
->instances
== 1)
2264 fs_reg m0
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2265 fs_reg m0_2
= byte_offset(m0
, 2 * sizeof(uint32_t));
2267 const fs_builder fwa_bld
= bld
.exec_all();
2269 /* Zero the message header */
2270 fwa_bld
.MOV(m0
, brw_imm_ud(0u));
2272 /* Copy "Barrier ID" from r0.2, bits 16:13 */
2273 fwa_bld
.AND(m0_2
, retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD
),
2274 brw_imm_ud(INTEL_MASK(16, 13)));
2276 /* Shift it up to bits 27:24. */
2277 fwa_bld
.SHL(m0_2
, m0_2
, brw_imm_ud(11));
2279 /* Set the Barrier Count and the enable bit */
2280 fwa_bld
.OR(m0_2
, m0_2
,
2281 brw_imm_ud(tcs_prog_data
->instances
<< 8 | (1 << 15)));
2283 bld
.emit(SHADER_OPCODE_BARRIER
, bld
.null_reg_ud(), m0
);
2287 case nir_intrinsic_load_input
:
2288 unreachable("nir_lower_io should never give us these.");
2291 case nir_intrinsic_load_per_vertex_input
: {
2292 fs_reg indirect_offset
= get_indirect_offset(instr
);
2293 unsigned imm_offset
= instr
->const_index
[0];
2295 const nir_src
&vertex_src
= instr
->src
[0];
2296 nir_const_value
*vertex_const
= nir_src_as_const_value(vertex_src
);
2303 /* Emit a MOV to resolve <0,1,0> regioning. */
2304 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2306 retype(brw_vec1_grf(1 + (vertex_const
->i32
[0] >> 3),
2307 vertex_const
->i32
[0] & 7),
2308 BRW_REGISTER_TYPE_UD
));
2309 } else if (tcs_prog_data
->instances
== 1 &&
2310 vertex_src
.is_ssa
&&
2311 vertex_src
.ssa
->parent_instr
->type
== nir_instr_type_intrinsic
&&
2312 nir_instr_as_intrinsic(vertex_src
.ssa
->parent_instr
)->intrinsic
== nir_intrinsic_load_invocation_id
) {
2313 /* For the common case of only 1 instance, an array index of
2314 * gl_InvocationID means reading g1. Skip all the indirect work.
2316 icp_handle
= retype(brw_vec8_grf(1, 0), BRW_REGISTER_TYPE_UD
);
2318 /* The vertex index is non-constant. We need to use indirect
2319 * addressing to fetch the proper URB handle.
2321 icp_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2323 /* Each ICP handle is a single DWord (4 bytes) */
2324 fs_reg vertex_offset_bytes
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2325 bld
.SHL(vertex_offset_bytes
,
2326 retype(get_nir_src(vertex_src
), BRW_REGISTER_TYPE_UD
),
2329 /* Start at g1. We might read up to 4 registers. */
2330 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
, icp_handle
,
2331 fs_reg(brw_vec8_grf(1, 0)), vertex_offset_bytes
,
2332 brw_imm_ud(4 * REG_SIZE
));
2335 /* We can only read two double components with each URB read, so
2336 * we send two read messages in that case, each one loading up to
2337 * two double components.
2339 unsigned num_iterations
= 1;
2340 unsigned num_components
= instr
->num_components
;
2341 fs_reg orig_dst
= dst
;
2342 if (type_sz(dst
.type
) == 8) {
2343 if (instr
->num_components
> 2) {
2348 fs_reg tmp
= fs_reg(VGRF
, alloc
.allocate(4), dst
.type
);
2352 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2353 if (indirect_offset
.file
== BAD_FILE
) {
2354 /* Constant indexing - use global offset. */
2355 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, icp_handle
);
2356 inst
->offset
= imm_offset
;
2358 inst
->base_mrf
= -1;
2360 /* Indirect indexing - use per-slot offsets as well. */
2361 const fs_reg srcs
[] = { icp_handle
, indirect_offset
};
2362 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2363 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2365 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2366 inst
->offset
= imm_offset
;
2367 inst
->base_mrf
= -1;
2370 inst
->regs_written
= num_components
* type_sz(dst
.type
) / 4;
2372 /* If we are reading 64-bit data using 32-bit read messages we need
2373 * build proper 64-bit data elements by shuffling the low and high
2374 * 32-bit components around like we do for other things like UBOs
2377 if (type_sz(dst
.type
) == 8) {
2378 shuffle_32bit_load_result_to_64bit_data(
2379 bld
, dst
, retype(dst
, BRW_REGISTER_TYPE_F
), num_components
);
2381 for (unsigned c
= 0; c
< num_components
; c
++) {
2382 bld
.MOV(offset(orig_dst
, bld
, iter
* 2 + c
),
2383 offset(dst
, bld
, c
));
2387 /* Copy the temporary to the destination to deal with writemasking.
2389 * Also attempt to deal with gl_PointSize being in the .w component.
2391 if (inst
->offset
== 0 && indirect_offset
.file
== BAD_FILE
) {
2392 assert(type_sz(dst
.type
) < 8);
2393 inst
->dst
= bld
.vgrf(dst
.type
, 4);
2394 inst
->regs_written
= 4;
2395 bld
.MOV(dst
, offset(inst
->dst
, bld
, 3));
2398 /* If we are loading double data and we need a second read message
2399 * adjust the write offset
2401 if (num_iterations
> 1) {
2402 num_components
= instr
->num_components
- 2;
2403 if (indirect_offset
.file
== BAD_FILE
) {
2406 fs_reg new_indirect
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2407 bld
.ADD(new_indirect
, indirect_offset
, brw_imm_ud(1u));
2408 indirect_offset
= new_indirect
;
2415 case nir_intrinsic_load_output
:
2416 case nir_intrinsic_load_per_vertex_output
: {
2417 fs_reg indirect_offset
= get_indirect_offset(instr
);
2418 unsigned imm_offset
= instr
->const_index
[0];
2421 if (indirect_offset
.file
== BAD_FILE
) {
2422 /* Replicate the patch handle to all enabled channels */
2423 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2424 bld
.MOV(patch_handle
,
2425 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
));
2427 if (imm_offset
== 0) {
2428 /* This is a read of gl_TessLevelInner[], which lives in the
2429 * Patch URB header. The layout depends on the domain.
2431 dst
.type
= BRW_REGISTER_TYPE_F
;
2432 switch (tcs_key
->tes_primitive_mode
) {
2434 /* DWords 3-2 (reversed) */
2435 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2437 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2440 inst
->base_mrf
= -1;
2441 inst
->regs_written
= 4;
2443 /* dst.xy = tmp.wz */
2444 bld
.MOV(dst
, offset(tmp
, bld
, 3));
2445 bld
.MOV(offset(dst
, bld
, 1), offset(tmp
, bld
, 2));
2449 /* DWord 4; hardcode offset = 1 and regs_written = 1 */
2450 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2453 inst
->base_mrf
= -1;
2454 inst
->regs_written
= 1;
2457 /* All channels are undefined. */
2460 unreachable("Bogus tessellation domain");
2462 } else if (imm_offset
== 1) {
2463 /* This is a read of gl_TessLevelOuter[], which lives in the
2464 * Patch URB header. The layout depends on the domain.
2466 dst
.type
= BRW_REGISTER_TYPE_F
;
2468 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 4);
2469 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, tmp
, patch_handle
);
2472 inst
->base_mrf
= -1;
2473 inst
->regs_written
= 4;
2475 /* Reswizzle: WZYX */
2477 offset(tmp
, bld
, 3),
2478 offset(tmp
, bld
, 2),
2479 offset(tmp
, bld
, 1),
2480 offset(tmp
, bld
, 0),
2483 unsigned num_components
;
2484 switch (tcs_key
->tes_primitive_mode
) {
2492 /* Isolines are not reversed; swizzle .zw -> .xy */
2493 srcs
[0] = offset(tmp
, bld
, 2);
2494 srcs
[1] = offset(tmp
, bld
, 3);
2498 unreachable("Bogus tessellation domain");
2500 bld
.LOAD_PAYLOAD(dst
, srcs
, num_components
, 0);
2502 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dst
, patch_handle
);
2503 inst
->offset
= imm_offset
;
2505 inst
->base_mrf
= -1;
2506 inst
->regs_written
= instr
->num_components
;
2509 /* Indirect indexing - use per-slot offsets as well. */
2510 const fs_reg srcs
[] = {
2511 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2514 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2515 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2517 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dst
, payload
);
2518 inst
->offset
= imm_offset
;
2520 inst
->base_mrf
= -1;
2521 inst
->regs_written
= instr
->num_components
;
2526 case nir_intrinsic_store_output
:
2527 case nir_intrinsic_store_per_vertex_output
: {
2528 fs_reg value
= get_nir_src(instr
->src
[0]);
2529 bool is_64bit
= (instr
->src
[0].is_ssa
?
2530 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
) == 64;
2531 fs_reg indirect_offset
= get_indirect_offset(instr
);
2532 unsigned imm_offset
= instr
->const_index
[0];
2533 unsigned swiz
= BRW_SWIZZLE_XYZW
;
2534 unsigned mask
= instr
->const_index
[1];
2535 unsigned header_regs
= 0;
2537 srcs
[header_regs
++] = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
);
2539 if (indirect_offset
.file
!= BAD_FILE
) {
2540 srcs
[header_regs
++] = indirect_offset
;
2541 } else if (!is_passthrough_shader
) {
2542 if (imm_offset
== 0) {
2543 value
.type
= BRW_REGISTER_TYPE_F
;
2545 mask
&= (1 << tesslevel_inner_components(tcs_key
->tes_primitive_mode
)) - 1;
2547 /* This is a write to gl_TessLevelInner[], which lives in the
2548 * Patch URB header. The layout depends on the domain.
2550 switch (tcs_key
->tes_primitive_mode
) {
2552 /* gl_TessLevelInner[].xy lives at DWords 3-2 (reversed).
2553 * We use an XXYX swizzle to reverse put .xy in the .wz
2554 * channels, and use a .zw writemask.
2556 mask
= writemask_for_backwards_vector(mask
);
2557 swiz
= BRW_SWIZZLE4(0, 0, 1, 0);
2560 /* gl_TessLevelInner[].x lives at DWord 4, so we set the
2561 * writemask to X and bump the URB offset by 1.
2566 /* Skip; gl_TessLevelInner[] doesn't exist for isolines. */
2569 unreachable("Bogus tessellation domain");
2571 } else if (imm_offset
== 1) {
2572 /* This is a write to gl_TessLevelOuter[] which lives in the
2573 * Patch URB Header at DWords 4-7. However, it's reversed, so
2574 * instead of .xyzw we have .wzyx.
2576 value
.type
= BRW_REGISTER_TYPE_F
;
2578 mask
&= (1 << tesslevel_outer_components(tcs_key
->tes_primitive_mode
)) - 1;
2580 if (tcs_key
->tes_primitive_mode
== GL_ISOLINES
) {
2581 /* Isolines .xy should be stored in .zw, in order. */
2582 swiz
= BRW_SWIZZLE4(0, 0, 0, 1);
2585 /* Other domains are reversed; store .wzyx instead of .xyzw */
2586 swiz
= BRW_SWIZZLE_WZYX
;
2587 mask
= writemask_for_backwards_vector(mask
);
2595 unsigned num_components
= _mesa_fls(mask
);
2598 /* We can only pack two 64-bit components in a single message, so send
2599 * 2 messages if we have more components
2601 unsigned num_iterations
= 1;
2602 unsigned iter_components
= num_components
;
2603 if (is_64bit
&& instr
->num_components
> 2) {
2605 iter_components
= 2;
2608 /* 64-bit data needs to me shuffled before we can write it to the URB.
2609 * We will use this temporary to shuffle the components in each
2613 fs_reg(VGRF
, alloc
.allocate(2 * iter_components
), value
.type
);
2615 for (unsigned iter
= 0; iter
< num_iterations
; iter
++) {
2616 if (!is_64bit
&& mask
!= WRITEMASK_XYZW
) {
2617 srcs
[header_regs
++] = brw_imm_ud(mask
<< 16);
2618 opcode
= indirect_offset
.file
!= BAD_FILE
?
2619 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2620 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2621 } else if (is_64bit
&& ((mask
& WRITEMASK_XY
) != WRITEMASK_XY
)) {
2622 /* Expand the 64-bit mask to 32-bit channels. We only handle
2623 * two channels in each iteration, so we only care about X/Y.
2625 unsigned mask32
= 0;
2626 if (mask
& WRITEMASK_X
)
2627 mask32
|= WRITEMASK_XY
;
2628 if (mask
& WRITEMASK_Y
)
2629 mask32
|= WRITEMASK_ZW
;
2631 /* If the mask does not include any of the channels X or Y there
2632 * is nothing to do in this iteration. Move on to the next couple
2633 * of 64-bit channels.
2641 srcs
[header_regs
++] = brw_imm_ud(mask32
<< 16);
2642 opcode
= indirect_offset
.file
!= BAD_FILE
?
2643 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT
:
2644 SHADER_OPCODE_URB_WRITE_SIMD8_MASKED
;
2646 opcode
= indirect_offset
.file
!= BAD_FILE
?
2647 SHADER_OPCODE_URB_WRITE_SIMD8_PER_SLOT
:
2648 SHADER_OPCODE_URB_WRITE_SIMD8
;
2651 for (unsigned i
= 0; i
< iter_components
; i
++) {
2652 if (!(mask
& (1 << i
)))
2656 srcs
[header_regs
+ i
] = offset(value
, bld
, BRW_GET_SWZ(swiz
, i
));
2658 /* We need to shuffle the 64-bit data to match the layout
2659 * expected by our 32-bit URB write messages. We use a temporary
2662 unsigned channel
= BRW_GET_SWZ(swiz
, iter
* 2 + i
);
2663 shuffle_64bit_data_for_32bit_write(bld
,
2664 retype(offset(tmp
, bld
, 2 * i
), BRW_REGISTER_TYPE_F
),
2665 retype(offset(value
, bld
, 2 * channel
), BRW_REGISTER_TYPE_DF
),
2668 /* Now copy the data to the destination */
2669 fs_reg dest
= fs_reg(VGRF
, alloc
.allocate(2), value
.type
);
2670 unsigned idx
= 2 * i
;
2671 bld
.MOV(dest
, offset(tmp
, bld
, idx
));
2672 bld
.MOV(offset(dest
, bld
, 1), offset(tmp
, bld
, idx
+ 1));
2673 srcs
[header_regs
+ idx
] = dest
;
2674 srcs
[header_regs
+ idx
+ 1] = offset(dest
, bld
, 1);
2679 header_regs
+ (is_64bit
? 2 * iter_components
: iter_components
);
2681 bld
.vgrf(BRW_REGISTER_TYPE_UD
, mlen
);
2682 bld
.LOAD_PAYLOAD(payload
, srcs
, mlen
, header_regs
);
2684 fs_inst
*inst
= bld
.emit(opcode
, bld
.null_reg_ud(), payload
);
2685 inst
->offset
= imm_offset
;
2687 inst
->base_mrf
= -1;
2689 /* If this is a 64-bit attribute, select the next two 64-bit channels
2690 * to be handled in the next iteration.
2701 nir_emit_intrinsic(bld
, instr
);
2707 fs_visitor::nir_emit_tes_intrinsic(const fs_builder
&bld
,
2708 nir_intrinsic_instr
*instr
)
2710 assert(stage
== MESA_SHADER_TESS_EVAL
);
2711 struct brw_tes_prog_data
*tes_prog_data
= (struct brw_tes_prog_data
*) prog_data
;
2714 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2715 dest
= get_nir_dest(instr
->dest
);
2717 switch (instr
->intrinsic
) {
2718 case nir_intrinsic_load_primitive_id
:
2719 bld
.MOV(dest
, fs_reg(brw_vec1_grf(0, 1)));
2721 case nir_intrinsic_load_tess_coord
:
2722 /* gl_TessCoord is part of the payload in g1-3 */
2723 for (unsigned i
= 0; i
< 3; i
++) {
2724 bld
.MOV(offset(dest
, bld
, i
), fs_reg(brw_vec8_grf(1 + i
, 0)));
2728 case nir_intrinsic_load_tess_level_outer
:
2729 /* When the TES reads gl_TessLevelOuter, we ensure that the patch header
2730 * appears as a push-model input. So, we can simply use the ATTR file
2731 * rather than issuing URB read messages. The data is stored in the
2732 * high DWords in reverse order - DWord 7 contains .x, DWord 6 contains
2735 switch (tes_prog_data
->domain
) {
2736 case BRW_TESS_DOMAIN_QUAD
:
2737 for (unsigned i
= 0; i
< 4; i
++)
2738 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2740 case BRW_TESS_DOMAIN_TRI
:
2741 for (unsigned i
= 0; i
< 3; i
++)
2742 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2744 case BRW_TESS_DOMAIN_ISOLINE
:
2745 for (unsigned i
= 0; i
< 2; i
++)
2746 bld
.MOV(offset(dest
, bld
, i
), component(fs_reg(ATTR
, 0), 7 - i
));
2751 case nir_intrinsic_load_tess_level_inner
:
2752 /* When the TES reads gl_TessLevelInner, we ensure that the patch header
2753 * appears as a push-model input. So, we can simply use the ATTR file
2754 * rather than issuing URB read messages.
2756 switch (tes_prog_data
->domain
) {
2757 case BRW_TESS_DOMAIN_QUAD
:
2758 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 3));
2759 bld
.MOV(offset(dest
, bld
, 1), component(fs_reg(ATTR
, 0), 2));
2761 case BRW_TESS_DOMAIN_TRI
:
2762 bld
.MOV(dest
, component(fs_reg(ATTR
, 0), 4));
2764 case BRW_TESS_DOMAIN_ISOLINE
:
2765 /* ignore - value is undefined */
2770 case nir_intrinsic_load_input
:
2771 case nir_intrinsic_load_per_vertex_input
: {
2772 fs_reg indirect_offset
= get_indirect_offset(instr
);
2773 unsigned imm_offset
= instr
->const_index
[0];
2776 if (indirect_offset
.file
== BAD_FILE
) {
2777 /* Arbitrarily only push up to 32 vec4 slots worth of data,
2778 * which is 16 registers (since each holds 2 vec4 slots).
2780 const unsigned max_push_slots
= 32;
2781 if (imm_offset
< max_push_slots
) {
2782 fs_reg src
= fs_reg(ATTR
, imm_offset
/ 2, dest
.type
);
2783 for (int i
= 0; i
< instr
->num_components
; i
++) {
2784 unsigned comp
= 16 / type_sz(dest
.type
) * (imm_offset
% 2) + i
;
2785 bld
.MOV(offset(dest
, bld
, i
), component(src
, comp
));
2787 tes_prog_data
->base
.urb_read_length
=
2788 MAX2(tes_prog_data
->base
.urb_read_length
,
2789 DIV_ROUND_UP(imm_offset
+ 1, 2));
2791 /* Replicate the patch handle to all enabled channels */
2792 const fs_reg srcs
[] = {
2793 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
)
2795 fs_reg patch_handle
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 1);
2796 bld
.LOAD_PAYLOAD(patch_handle
, srcs
, ARRAY_SIZE(srcs
), 0);
2798 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8
, dest
, patch_handle
);
2800 inst
->offset
= imm_offset
;
2801 inst
->base_mrf
= -1;
2802 inst
->regs_written
= instr
->num_components
;
2805 /* Indirect indexing - use per-slot offsets as well. */
2806 const fs_reg srcs
[] = {
2807 retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD
),
2810 fs_reg payload
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 2);
2811 bld
.LOAD_PAYLOAD(payload
, srcs
, ARRAY_SIZE(srcs
), 0);
2813 inst
= bld
.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT
, dest
, payload
);
2815 inst
->offset
= imm_offset
;
2816 inst
->base_mrf
= -1;
2817 inst
->regs_written
= instr
->num_components
;
2822 nir_emit_intrinsic(bld
, instr
);
2828 fs_visitor::nir_emit_gs_intrinsic(const fs_builder
&bld
,
2829 nir_intrinsic_instr
*instr
)
2831 assert(stage
== MESA_SHADER_GEOMETRY
);
2832 fs_reg indirect_offset
;
2835 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2836 dest
= get_nir_dest(instr
->dest
);
2838 switch (instr
->intrinsic
) {
2839 case nir_intrinsic_load_primitive_id
:
2840 assert(stage
== MESA_SHADER_GEOMETRY
);
2841 assert(((struct brw_gs_prog_data
*)prog_data
)->include_primitive_id
);
2842 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
),
2843 retype(fs_reg(brw_vec8_grf(2, 0)), BRW_REGISTER_TYPE_UD
));
2846 case nir_intrinsic_load_input
:
2847 unreachable("load_input intrinsics are invalid for the GS stage");
2849 case nir_intrinsic_load_per_vertex_input
:
2850 emit_gs_input_load(dest
, instr
->src
[0], instr
->const_index
[0],
2851 instr
->src
[1], instr
->num_components
);
2854 case nir_intrinsic_emit_vertex_with_counter
:
2855 emit_gs_vertex(instr
->src
[0], instr
->const_index
[0]);
2858 case nir_intrinsic_end_primitive_with_counter
:
2859 emit_gs_end_primitive(instr
->src
[0]);
2862 case nir_intrinsic_set_vertex_count
:
2863 bld
.MOV(this->final_gs_vertex_count
, get_nir_src(instr
->src
[0]));
2866 case nir_intrinsic_load_invocation_id
: {
2867 fs_reg val
= nir_system_values
[SYSTEM_VALUE_INVOCATION_ID
];
2868 assert(val
.file
!= BAD_FILE
);
2869 dest
.type
= val
.type
;
2875 nir_emit_intrinsic(bld
, instr
);
2881 fs_visitor::nir_emit_fs_intrinsic(const fs_builder
&bld
,
2882 nir_intrinsic_instr
*instr
)
2884 assert(stage
== MESA_SHADER_FRAGMENT
);
2885 struct brw_wm_prog_data
*wm_prog_data
=
2886 (struct brw_wm_prog_data
*) prog_data
;
2887 const struct brw_wm_prog_key
*wm_key
= (const struct brw_wm_prog_key
*) key
;
2890 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
2891 dest
= get_nir_dest(instr
->dest
);
2893 switch (instr
->intrinsic
) {
2894 case nir_intrinsic_load_front_face
:
2895 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
),
2896 *emit_frontfacing_interpolation());
2899 case nir_intrinsic_load_sample_pos
: {
2900 fs_reg sample_pos
= nir_system_values
[SYSTEM_VALUE_SAMPLE_POS
];
2901 assert(sample_pos
.file
!= BAD_FILE
);
2902 dest
.type
= sample_pos
.type
;
2903 bld
.MOV(dest
, sample_pos
);
2904 bld
.MOV(offset(dest
, bld
, 1), offset(sample_pos
, bld
, 1));
2908 case nir_intrinsic_load_helper_invocation
:
2909 case nir_intrinsic_load_sample_mask_in
:
2910 case nir_intrinsic_load_sample_id
: {
2911 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
2912 fs_reg val
= nir_system_values
[sv
];
2913 assert(val
.file
!= BAD_FILE
);
2914 dest
.type
= val
.type
;
2919 case nir_intrinsic_discard
:
2920 case nir_intrinsic_discard_if
: {
2921 /* We track our discarded pixels in f0.1. By predicating on it, we can
2922 * update just the flag bits that aren't yet discarded. If there's no
2923 * condition, we emit a CMP of g0 != g0, so all currently executing
2924 * channels will get turned off.
2927 if (instr
->intrinsic
== nir_intrinsic_discard_if
) {
2928 cmp
= bld
.CMP(bld
.null_reg_f(), get_nir_src(instr
->src
[0]),
2929 brw_imm_d(0), BRW_CONDITIONAL_Z
);
2931 fs_reg some_reg
= fs_reg(retype(brw_vec8_grf(0, 0),
2932 BRW_REGISTER_TYPE_UW
));
2933 cmp
= bld
.CMP(bld
.null_reg_f(), some_reg
, some_reg
, BRW_CONDITIONAL_NZ
);
2935 cmp
->predicate
= BRW_PREDICATE_NORMAL
;
2936 cmp
->flag_subreg
= 1;
2938 if (devinfo
->gen
>= 6) {
2939 emit_discard_jump();
2944 case nir_intrinsic_interp_var_at_centroid
:
2945 case nir_intrinsic_interp_var_at_sample
:
2946 case nir_intrinsic_interp_var_at_offset
: {
2947 /* Handle ARB_gpu_shader5 interpolation intrinsics
2949 * It's worth a quick word of explanation as to why we handle the full
2950 * variable-based interpolation intrinsic rather than a lowered version
2951 * with like we do for other inputs. We have to do that because the way
2952 * we set up inputs doesn't allow us to use the already setup inputs for
2953 * interpolation. At the beginning of the shader, we go through all of
2954 * the input variables and do the initial interpolation and put it in
2955 * the nir_inputs array based on its location as determined in
2956 * nir_lower_io. If the input isn't used, dead code cleans up and
2957 * everything works fine. However, when we get to the ARB_gpu_shader5
2958 * interpolation intrinsics, we need to reinterpolate the input
2959 * differently. If we used an intrinsic that just had an index it would
2960 * only give us the offset into the nir_inputs array. However, this is
2961 * useless because that value is post-interpolation and we need
2962 * pre-interpolation. In order to get the actual location of the bits
2963 * we get from the vertex fetching hardware, we need the variable.
2965 wm_prog_data
->pulls_bary
= true;
2967 fs_reg dst_xy
= bld
.vgrf(BRW_REGISTER_TYPE_F
, 2);
2968 const glsl_interp_qualifier interpolation
=
2969 (glsl_interp_qualifier
) instr
->variables
[0]->var
->data
.interpolation
;
2971 switch (instr
->intrinsic
) {
2972 case nir_intrinsic_interp_var_at_centroid
:
2973 emit_pixel_interpolater_send(bld
,
2974 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2981 case nir_intrinsic_interp_var_at_sample
: {
2982 if (!wm_key
->multisample_fbo
) {
2983 /* From the ARB_gpu_shader5 specification:
2984 * "If multisample buffers are not available, the input varying
2985 * will be evaluated at the center of the pixel."
2987 emit_pixel_interpolater_send(bld
,
2988 FS_OPCODE_INTERPOLATE_AT_CENTROID
,
2996 nir_const_value
*const_sample
= nir_src_as_const_value(instr
->src
[0]);
2999 unsigned msg_data
= const_sample
->i32
[0] << 4;
3001 emit_pixel_interpolater_send(bld
,
3002 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3005 brw_imm_ud(msg_data
),
3008 const fs_reg sample_src
= retype(get_nir_src(instr
->src
[0]),
3009 BRW_REGISTER_TYPE_UD
);
3011 if (nir_src_is_dynamically_uniform(instr
->src
[0])) {
3012 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3013 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3014 bld
.exec_all().group(1, 0)
3015 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3016 emit_pixel_interpolater_send(bld
,
3017 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3023 /* Make a loop that sends a message to the pixel interpolater
3024 * for the sample number in each live channel. If there are
3025 * multiple channels with the same sample number then these
3026 * will be handled simultaneously with a single interation of
3029 bld
.emit(BRW_OPCODE_DO
);
3031 /* Get the next live sample number into sample_id_reg */
3032 const fs_reg sample_id
= bld
.emit_uniformize(sample_src
);
3034 /* Set the flag register so that we can perform the send
3035 * message on all channels that have the same sample number
3037 bld
.CMP(bld
.null_reg_ud(),
3038 sample_src
, sample_id
,
3039 BRW_CONDITIONAL_EQ
);
3040 const fs_reg msg_data
= vgrf(glsl_type::uint_type
);
3041 bld
.exec_all().group(1, 0)
3042 .SHL(msg_data
, sample_id
, brw_imm_ud(4u));
3044 emit_pixel_interpolater_send(bld
,
3045 FS_OPCODE_INTERPOLATE_AT_SAMPLE
,
3050 set_predicate(BRW_PREDICATE_NORMAL
, inst
);
3052 /* Continue the loop if there are any live channels left */
3053 set_predicate_inv(BRW_PREDICATE_NORMAL
,
3055 bld
.emit(BRW_OPCODE_WHILE
));
3062 case nir_intrinsic_interp_var_at_offset
: {
3063 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3065 const bool flip
= !wm_key
->render_to_fbo
;
3068 unsigned off_x
= MIN2((int)(const_offset
->f32
[0] * 16), 7) & 0xf;
3069 unsigned off_y
= MIN2((int)(const_offset
->f32
[1] * 16 *
3070 (flip
? -1 : 1)), 7) & 0xf;
3072 emit_pixel_interpolater_send(bld
,
3073 FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET
,
3076 brw_imm_ud(off_x
| (off_y
<< 4)),
3079 fs_reg src
= vgrf(glsl_type::ivec2_type
);
3080 fs_reg offset_src
= retype(get_nir_src(instr
->src
[0]),
3081 BRW_REGISTER_TYPE_F
);
3082 for (int i
= 0; i
< 2; i
++) {
3083 fs_reg temp
= vgrf(glsl_type::float_type
);
3084 bld
.MUL(temp
, offset(offset_src
, bld
, i
), brw_imm_f(16.0f
));
3085 fs_reg itemp
= vgrf(glsl_type::int_type
);
3087 bld
.MOV(itemp
, (i
== 1 && flip
) ? negate(temp
) : temp
);
3089 /* Clamp the upper end of the range to +7/16.
3090 * ARB_gpu_shader5 requires that we support a maximum offset
3091 * of +0.5, which isn't representable in a S0.4 value -- if
3092 * we didn't clamp it, we'd end up with -8/16, which is the
3093 * opposite of what the shader author wanted.
3095 * This is legal due to ARB_gpu_shader5's quantization
3098 * "Not all values of <offset> may be supported; x and y
3099 * offsets may be rounded to fixed-point values with the
3100 * number of fraction bits given by the
3101 * implementation-dependent constant
3102 * FRAGMENT_INTERPOLATION_OFFSET_BITS"
3104 set_condmod(BRW_CONDITIONAL_L
,
3105 bld
.SEL(offset(src
, bld
, i
), itemp
, brw_imm_d(7)));
3108 const enum opcode opcode
= FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET
;
3109 emit_pixel_interpolater_send(bld
,
3120 unreachable("Invalid intrinsic");
3123 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3124 fs_reg src
= interp_reg(instr
->variables
[0]->var
->data
.location
, j
);
3125 src
.type
= dest
.type
;
3127 bld
.emit(FS_OPCODE_LINTERP
, dest
, dst_xy
, src
);
3128 dest
= offset(dest
, bld
, 1);
3133 nir_emit_intrinsic(bld
, instr
);
3139 fs_visitor::nir_emit_cs_intrinsic(const fs_builder
&bld
,
3140 nir_intrinsic_instr
*instr
)
3142 assert(stage
== MESA_SHADER_COMPUTE
);
3143 struct brw_cs_prog_data
*cs_prog_data
=
3144 (struct brw_cs_prog_data
*) prog_data
;
3147 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3148 dest
= get_nir_dest(instr
->dest
);
3150 switch (instr
->intrinsic
) {
3151 case nir_intrinsic_barrier
:
3153 cs_prog_data
->uses_barrier
= true;
3156 case nir_intrinsic_load_local_invocation_id
:
3157 case nir_intrinsic_load_work_group_id
: {
3158 gl_system_value sv
= nir_system_value_from_intrinsic(instr
->intrinsic
);
3159 fs_reg val
= nir_system_values
[sv
];
3160 assert(val
.file
!= BAD_FILE
);
3161 dest
.type
= val
.type
;
3162 for (unsigned i
= 0; i
< 3; i
++)
3163 bld
.MOV(offset(dest
, bld
, i
), offset(val
, bld
, i
));
3167 case nir_intrinsic_load_num_work_groups
: {
3168 const unsigned surface
=
3169 cs_prog_data
->binding_table
.work_groups_start
;
3171 cs_prog_data
->uses_num_work_groups
= true;
3173 fs_reg surf_index
= brw_imm_ud(surface
);
3174 brw_mark_surface_used(prog_data
, surface
);
3176 /* Read the 3 GLuint components of gl_NumWorkGroups */
3177 for (unsigned i
= 0; i
< 3; i
++) {
3178 fs_reg read_result
=
3179 emit_untyped_read(bld
, surf_index
,
3181 1 /* dims */, 1 /* size */,
3182 BRW_PREDICATE_NONE
);
3183 read_result
.type
= dest
.type
;
3184 bld
.MOV(dest
, read_result
);
3185 dest
= offset(dest
, bld
, 1);
3190 case nir_intrinsic_shared_atomic_add
:
3191 nir_emit_shared_atomic(bld
, BRW_AOP_ADD
, instr
);
3193 case nir_intrinsic_shared_atomic_imin
:
3194 nir_emit_shared_atomic(bld
, BRW_AOP_IMIN
, instr
);
3196 case nir_intrinsic_shared_atomic_umin
:
3197 nir_emit_shared_atomic(bld
, BRW_AOP_UMIN
, instr
);
3199 case nir_intrinsic_shared_atomic_imax
:
3200 nir_emit_shared_atomic(bld
, BRW_AOP_IMAX
, instr
);
3202 case nir_intrinsic_shared_atomic_umax
:
3203 nir_emit_shared_atomic(bld
, BRW_AOP_UMAX
, instr
);
3205 case nir_intrinsic_shared_atomic_and
:
3206 nir_emit_shared_atomic(bld
, BRW_AOP_AND
, instr
);
3208 case nir_intrinsic_shared_atomic_or
:
3209 nir_emit_shared_atomic(bld
, BRW_AOP_OR
, instr
);
3211 case nir_intrinsic_shared_atomic_xor
:
3212 nir_emit_shared_atomic(bld
, BRW_AOP_XOR
, instr
);
3214 case nir_intrinsic_shared_atomic_exchange
:
3215 nir_emit_shared_atomic(bld
, BRW_AOP_MOV
, instr
);
3217 case nir_intrinsic_shared_atomic_comp_swap
:
3218 nir_emit_shared_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3221 case nir_intrinsic_load_shared
: {
3222 assert(devinfo
->gen
>= 7);
3224 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3226 /* Get the offset to read from */
3228 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3230 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0]);
3232 offset_reg
= vgrf(glsl_type::uint_type
);
3234 retype(get_nir_src(instr
->src
[0]), BRW_REGISTER_TYPE_UD
),
3235 brw_imm_ud(instr
->const_index
[0]));
3238 /* Read the vector */
3239 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3240 instr
->num_components
);
3244 case nir_intrinsic_store_shared
: {
3245 assert(devinfo
->gen
>= 7);
3248 fs_reg surf_index
= brw_imm_ud(GEN7_BTI_SLM
);
3251 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3254 unsigned writemask
= instr
->const_index
[1];
3256 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3257 * since the untyped writes below operate in units of 32-bits, which
3258 * means that we need to write twice as many components each time.
3259 * Also, we have to suffle 64-bit data to be in the appropriate layout
3260 * expected by our 32-bit write messages.
3262 unsigned type_size
= 4;
3263 unsigned bit_size
= instr
->src
[0].is_ssa
?
3264 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3265 if (bit_size
== 64) {
3268 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3269 shuffle_64bit_data_for_32bit_write(
3271 retype(tmp
, BRW_REGISTER_TYPE_F
),
3272 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3273 instr
->num_components
);
3277 unsigned type_slots
= type_size
/ 4;
3279 /* Combine groups of consecutive enabled channels in one write
3280 * message. We use ffs to find the first enabled channel and then ffs on
3281 * the bit-inverse, down-shifted writemask to determine the length of
3282 * the block of enabled bits.
3285 unsigned first_component
= ffs(writemask
) - 1;
3286 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3288 /* We can't write more than 2 64-bit components at once. Limit the
3289 * length of the write to what we can do and let the next iteration
3293 length
= MIN2(2, length
);
3296 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3298 offset_reg
= brw_imm_ud(instr
->const_index
[0] + const_offset
->u32
[0] +
3299 type_size
* first_component
);
3301 offset_reg
= vgrf(glsl_type::uint_type
);
3303 retype(get_nir_src(instr
->src
[1]), BRW_REGISTER_TYPE_UD
),
3304 brw_imm_ud(instr
->const_index
[0] + type_size
* first_component
));
3307 emit_untyped_write(bld
, surf_index
, offset_reg
,
3308 offset(val_reg
, bld
, first_component
* type_slots
),
3309 1 /* dims */, length
* type_slots
,
3310 BRW_PREDICATE_NONE
);
3312 /* Clear the bits in the writemask that we just wrote, then try
3313 * again to see if more channels are left.
3315 writemask
&= (15 << (first_component
+ length
));
3322 nir_emit_intrinsic(bld
, instr
);
3328 fs_visitor::nir_emit_intrinsic(const fs_builder
&bld
, nir_intrinsic_instr
*instr
)
3331 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3332 dest
= get_nir_dest(instr
->dest
);
3334 switch (instr
->intrinsic
) {
3335 case nir_intrinsic_atomic_counter_inc
:
3336 case nir_intrinsic_atomic_counter_dec
:
3337 case nir_intrinsic_atomic_counter_read
: {
3338 /* Get the arguments of the atomic intrinsic. */
3339 const fs_reg offset
= get_nir_src(instr
->src
[0]);
3340 const unsigned surface
= (stage_prog_data
->binding_table
.abo_start
+
3341 instr
->const_index
[0]);
3344 /* Emit a surface read or atomic op. */
3345 switch (instr
->intrinsic
) {
3346 case nir_intrinsic_atomic_counter_read
:
3347 tmp
= emit_untyped_read(bld
, brw_imm_ud(surface
), offset
, 1, 1);
3350 case nir_intrinsic_atomic_counter_inc
:
3351 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3352 fs_reg(), 1, 1, BRW_AOP_INC
);
3355 case nir_intrinsic_atomic_counter_dec
:
3356 tmp
= emit_untyped_atomic(bld
, brw_imm_ud(surface
), offset
, fs_reg(),
3357 fs_reg(), 1, 1, BRW_AOP_PREDEC
);
3361 unreachable("Unreachable");
3364 /* Assign the result. */
3365 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_UD
), tmp
);
3367 /* Mark the surface as used. */
3368 brw_mark_surface_used(stage_prog_data
, surface
);
3372 case nir_intrinsic_image_load
:
3373 case nir_intrinsic_image_store
:
3374 case nir_intrinsic_image_atomic_add
:
3375 case nir_intrinsic_image_atomic_min
:
3376 case nir_intrinsic_image_atomic_max
:
3377 case nir_intrinsic_image_atomic_and
:
3378 case nir_intrinsic_image_atomic_or
:
3379 case nir_intrinsic_image_atomic_xor
:
3380 case nir_intrinsic_image_atomic_exchange
:
3381 case nir_intrinsic_image_atomic_comp_swap
: {
3382 using namespace image_access
;
3384 /* Get the referenced image variable and type. */
3385 const nir_variable
*var
= instr
->variables
[0]->var
;
3386 const glsl_type
*type
= var
->type
->without_array();
3387 const brw_reg_type base_type
= get_image_base_type(type
);
3389 /* Get some metadata from the image intrinsic. */
3390 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3391 const unsigned arr_dims
= type
->sampler_array
? 1 : 0;
3392 const unsigned surf_dims
= type
->coordinate_components() - arr_dims
;
3393 const unsigned format
= var
->data
.image
.format
;
3395 /* Get the arguments of the image intrinsic. */
3396 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3397 const fs_reg addr
= retype(get_nir_src(instr
->src
[0]),
3398 BRW_REGISTER_TYPE_UD
);
3399 const fs_reg src0
= (info
->num_srcs
>= 3 ?
3400 retype(get_nir_src(instr
->src
[2]), base_type
) :
3402 const fs_reg src1
= (info
->num_srcs
>= 4 ?
3403 retype(get_nir_src(instr
->src
[3]), base_type
) :
3407 /* Emit an image load, store or atomic op. */
3408 if (instr
->intrinsic
== nir_intrinsic_image_load
)
3409 tmp
= emit_image_load(bld
, image
, addr
, surf_dims
, arr_dims
, format
);
3411 else if (instr
->intrinsic
== nir_intrinsic_image_store
)
3412 emit_image_store(bld
, image
, addr
, src0
, surf_dims
, arr_dims
,
3413 var
->data
.image
.write_only
? GL_NONE
: format
);
3416 tmp
= emit_image_atomic(bld
, image
, addr
, src0
, src1
,
3417 surf_dims
, arr_dims
, info
->dest_components
,
3418 get_image_atomic_op(instr
->intrinsic
, type
));
3420 /* Assign the result. */
3421 for (unsigned c
= 0; c
< info
->dest_components
; ++c
)
3422 bld
.MOV(offset(retype(dest
, base_type
), bld
, c
),
3423 offset(tmp
, bld
, c
));
3427 case nir_intrinsic_memory_barrier_atomic_counter
:
3428 case nir_intrinsic_memory_barrier_buffer
:
3429 case nir_intrinsic_memory_barrier_image
:
3430 case nir_intrinsic_memory_barrier
: {
3431 const fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_UD
, 16 / dispatch_width
);
3432 bld
.emit(SHADER_OPCODE_MEMORY_FENCE
, tmp
)
3437 case nir_intrinsic_group_memory_barrier
:
3438 case nir_intrinsic_memory_barrier_shared
:
3439 /* We treat these workgroup-level barriers as no-ops. This should be
3440 * safe at present and as long as:
3442 * - Memory access instructions are not subsequently reordered by the
3443 * compiler back-end.
3445 * - All threads from a given compute shader workgroup fit within a
3446 * single subslice and therefore talk to the same HDC shared unit
3447 * what supposedly guarantees ordering and coherency between threads
3448 * from the same workgroup. This may change in the future when we
3449 * start splitting workgroups across multiple subslices.
3451 * - The context is not in fault-and-stream mode, which could cause
3452 * memory transactions (including to SLM) prior to the barrier to be
3453 * replayed after the barrier if a pagefault occurs. This shouldn't
3454 * be a problem up to and including SKL because fault-and-stream is
3455 * not usable due to hardware issues, but that's likely to change in
3460 case nir_intrinsic_shader_clock
: {
3461 /* We cannot do anything if there is an event, so ignore it for now */
3462 fs_reg shader_clock
= get_timestamp(bld
);
3463 const fs_reg srcs
[] = { shader_clock
.set_smear(0), shader_clock
.set_smear(1) };
3465 bld
.LOAD_PAYLOAD(dest
, srcs
, ARRAY_SIZE(srcs
), 0);
3469 case nir_intrinsic_image_size
: {
3470 /* Get the referenced image variable and type. */
3471 const nir_variable
*var
= instr
->variables
[0]->var
;
3472 const glsl_type
*type
= var
->type
->without_array();
3474 /* Get the size of the image. */
3475 const fs_reg image
= get_nir_image_deref(instr
->variables
[0]);
3476 const fs_reg size
= offset(image
, bld
, BRW_IMAGE_PARAM_SIZE_OFFSET
);
3478 /* For 1DArray image types, the array index is stored in the Z component.
3479 * Fix this by swizzling the Z component to the Y component.
3481 const bool is_1d_array_image
=
3482 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_1D
&&
3483 type
->sampler_array
;
3485 /* For CubeArray images, we should count the number of cubes instead
3486 * of the number of faces. Fix it by dividing the (Z component) by 6.
3488 const bool is_cube_array_image
=
3489 type
->sampler_dimensionality
== GLSL_SAMPLER_DIM_CUBE
&&
3490 type
->sampler_array
;
3492 /* Copy all the components. */
3493 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[instr
->intrinsic
];
3494 for (unsigned c
= 0; c
< info
->dest_components
; ++c
) {
3495 if ((int)c
>= type
->coordinate_components()) {
3496 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3498 } else if (c
== 1 && is_1d_array_image
) {
3499 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3500 offset(size
, bld
, 2));
3501 } else if (c
== 2 && is_cube_array_image
) {
3502 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
,
3503 offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3504 offset(size
, bld
, c
), brw_imm_d(6));
3506 bld
.MOV(offset(retype(dest
, BRW_REGISTER_TYPE_D
), bld
, c
),
3507 offset(size
, bld
, c
));
3514 case nir_intrinsic_image_samples
:
3515 /* The driver does not support multi-sampled images. */
3516 bld
.MOV(retype(dest
, BRW_REGISTER_TYPE_D
), brw_imm_d(1));
3519 case nir_intrinsic_load_uniform
: {
3520 /* Offsets are in bytes but they should always be multiples of 4 */
3521 assert(instr
->const_index
[0] % 4 == 0);
3523 fs_reg
src(UNIFORM
, instr
->const_index
[0] / 4, dest
.type
);
3525 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3527 /* Offsets are in bytes but they should always be multiples of 4 */
3528 assert(const_offset
->u32
[0] % 4 == 0);
3529 src
.reg_offset
= const_offset
->u32
[0] / 4;
3531 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3532 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3535 fs_reg indirect
= retype(get_nir_src(instr
->src
[0]),
3536 BRW_REGISTER_TYPE_UD
);
3538 /* We need to pass a size to the MOV_INDIRECT but we don't want it to
3539 * go past the end of the uniform. In order to keep the n'th
3540 * component from running past, we subtract off the size of all but
3541 * one component of the vector.
3543 assert(instr
->const_index
[1] >=
3544 instr
->num_components
* (int) type_sz(dest
.type
));
3545 unsigned read_size
= instr
->const_index
[1] -
3546 (instr
->num_components
- 1) * type_sz(dest
.type
);
3548 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3549 bld
.emit(SHADER_OPCODE_MOV_INDIRECT
,
3550 offset(dest
, bld
, j
), offset(src
, bld
, j
),
3551 indirect
, brw_imm_ud(read_size
));
3557 case nir_intrinsic_load_ubo
: {
3558 nir_const_value
*const_index
= nir_src_as_const_value(instr
->src
[0]);
3562 const unsigned index
= stage_prog_data
->binding_table
.ubo_start
+
3563 const_index
->u32
[0];
3564 surf_index
= brw_imm_ud(index
);
3565 brw_mark_surface_used(prog_data
, index
);
3567 /* The block index is not a constant. Evaluate the index expression
3568 * per-channel and add the base UBO index; we have to select a value
3569 * from any live channel.
3571 surf_index
= vgrf(glsl_type::uint_type
);
3572 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3573 brw_imm_ud(stage_prog_data
->binding_table
.ubo_start
));
3574 surf_index
= bld
.emit_uniformize(surf_index
);
3576 /* Assume this may touch any UBO. It would be nice to provide
3577 * a tighter bound, but the array information is already lowered away.
3579 brw_mark_surface_used(prog_data
,
3580 stage_prog_data
->binding_table
.ubo_start
+
3581 nir
->info
.num_ubos
- 1);
3584 /* Number of 32-bit slots in the type */
3585 unsigned type_slots
= MAX2(1, type_sz(dest
.type
) / 4);
3587 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3588 if (const_offset
== NULL
) {
3589 fs_reg base_offset
= retype(get_nir_src(instr
->src
[1]),
3590 BRW_REGISTER_TYPE_UD
);
3592 for (int i
= 0; i
< instr
->num_components
; i
++)
3593 VARYING_PULL_CONSTANT_LOAD(bld
, offset(dest
, bld
, i
), surf_index
,
3594 base_offset
, i
* type_sz(dest
.type
));
3596 /* Even if we are loading doubles, a pull constant load will load
3597 * a 32-bit vec4, so should only reserve vgrf space for that. If we
3598 * need to load a full dvec4 we will have to emit 2 loads. This is
3599 * similar to demote_pull_constants(), except that in that case we
3600 * see individual accesses to each component of the vector and then
3601 * we let CSE deal with duplicate loads. Here we see a vector access
3602 * and we have to split it if necessary.
3604 fs_reg packed_consts
= vgrf(glsl_type::float_type
);
3605 packed_consts
.type
= dest
.type
;
3607 unsigned const_offset_aligned
= const_offset
->u32
[0] & ~15;
3609 /* A vec4 only contains half of a dvec4, if we need more than 2
3610 * components of a dvec4 we will have to issue another load for
3611 * components z and w.
3614 if (type_slots
== 1)
3615 num_components
= instr
->num_components
;
3617 num_components
= MIN2(2, instr
->num_components
);
3619 /* The computation of num_components doesn't take into account
3620 * misalignment, which should be okay according to std140 vector
3623 assert(const_offset
->u32
[0] % 16 +
3624 type_sz(dest
.type
) * num_components
<= 16);
3626 int remaining_components
= instr
->num_components
;
3627 while (remaining_components
> 0) {
3628 /* Read the vec4 from a 16-byte aligned offset */
3629 struct brw_reg const_offset_reg
= brw_imm_ud(const_offset_aligned
);
3630 bld
.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD
,
3631 retype(packed_consts
, BRW_REGISTER_TYPE_F
),
3632 surf_index
, const_offset_reg
);
3634 const fs_reg consts
= byte_offset(packed_consts
, (const_offset
->u32
[0] % 16));
3635 unsigned dest_offset
= instr
->num_components
- remaining_components
;
3637 /* XXX: This doesn't update the sub-16B offset across iterations of
3638 * the loop, which should work for std140 vector alignment rules.
3640 assert(dest_offset
== 0 || const_offset
->u32
[0] % 16 == 0);
3642 for (int i
= 0; i
< num_components
; i
++)
3643 bld
.MOV(offset(dest
, bld
, i
+ dest_offset
), component(consts
, i
));
3645 /* If this is a large enough 64-bit load, we will need to emit
3648 remaining_components
-= num_components
;
3649 assert(remaining_components
== 0 ||
3650 (remaining_components
<= 2 && type_slots
== 2));
3651 num_components
= remaining_components
;
3652 const_offset_aligned
+= 16;
3658 case nir_intrinsic_load_ssbo
: {
3659 assert(devinfo
->gen
>= 7);
3661 nir_const_value
*const_uniform_block
=
3662 nir_src_as_const_value(instr
->src
[0]);
3665 if (const_uniform_block
) {
3666 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3667 const_uniform_block
->u32
[0];
3668 surf_index
= brw_imm_ud(index
);
3669 brw_mark_surface_used(prog_data
, index
);
3671 surf_index
= vgrf(glsl_type::uint_type
);
3672 bld
.ADD(surf_index
, get_nir_src(instr
->src
[0]),
3673 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3675 /* Assume this may touch any UBO. It would be nice to provide
3676 * a tighter bound, but the array information is already lowered away.
3678 brw_mark_surface_used(prog_data
,
3679 stage_prog_data
->binding_table
.ssbo_start
+
3680 nir
->info
.num_ssbos
- 1);
3684 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3686 offset_reg
= brw_imm_ud(const_offset
->u32
[0]);
3688 offset_reg
= get_nir_src(instr
->src
[1]);
3691 /* Read the vector */
3692 do_untyped_vector_read(bld
, dest
, surf_index
, offset_reg
,
3693 instr
->num_components
);
3698 case nir_intrinsic_load_input
: {
3700 if (stage
== MESA_SHADER_VERTEX
) {
3701 src
= fs_reg(ATTR
, instr
->const_index
[0], dest
.type
);
3703 src
= offset(retype(nir_inputs
, dest
.type
), bld
,
3704 instr
->const_index
[0]);
3707 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
3708 assert(const_offset
&& "Indirect input loads not allowed");
3709 src
= offset(src
, bld
, const_offset
->u32
[0]);
3711 for (unsigned j
= 0; j
< instr
->num_components
; j
++) {
3712 bld
.MOV(offset(dest
, bld
, j
), offset(src
, bld
, j
));
3715 if (type_sz(src
.type
) == 8) {
3716 shuffle_32bit_load_result_to_64bit_data(bld
,
3718 retype(dest
, BRW_REGISTER_TYPE_F
),
3719 instr
->num_components
);
3725 case nir_intrinsic_store_ssbo
: {
3726 assert(devinfo
->gen
>= 7);
3730 nir_const_value
*const_uniform_block
=
3731 nir_src_as_const_value(instr
->src
[1]);
3732 if (const_uniform_block
) {
3733 unsigned index
= stage_prog_data
->binding_table
.ssbo_start
+
3734 const_uniform_block
->u32
[0];
3735 surf_index
= brw_imm_ud(index
);
3736 brw_mark_surface_used(prog_data
, index
);
3738 surf_index
= vgrf(glsl_type::uint_type
);
3739 bld
.ADD(surf_index
, get_nir_src(instr
->src
[1]),
3740 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3742 brw_mark_surface_used(prog_data
,
3743 stage_prog_data
->binding_table
.ssbo_start
+
3744 nir
->info
.num_ssbos
- 1);
3748 fs_reg val_reg
= get_nir_src(instr
->src
[0]);
3751 unsigned writemask
= instr
->const_index
[0];
3753 /* get_nir_src() retypes to integer. Be wary of 64-bit types though
3754 * since the untyped writes below operate in units of 32-bits, which
3755 * means that we need to write twice as many components each time.
3756 * Also, we have to suffle 64-bit data to be in the appropriate layout
3757 * expected by our 32-bit write messages.
3759 unsigned type_size
= 4;
3760 unsigned bit_size
= instr
->src
[0].is_ssa
?
3761 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3762 if (bit_size
== 64) {
3765 fs_reg(VGRF
, alloc
.allocate(alloc
.sizes
[val_reg
.nr
]), val_reg
.type
);
3766 shuffle_64bit_data_for_32bit_write(bld
,
3767 retype(tmp
, BRW_REGISTER_TYPE_F
),
3768 retype(val_reg
, BRW_REGISTER_TYPE_DF
),
3769 instr
->num_components
);
3773 unsigned type_slots
= type_size
/ 4;
3775 /* Combine groups of consecutive enabled channels in one write
3776 * message. We use ffs to find the first enabled channel and then ffs on
3777 * the bit-inverse, down-shifted writemask to determine the length of
3778 * the block of enabled bits.
3781 unsigned first_component
= ffs(writemask
) - 1;
3782 unsigned length
= ffs(~(writemask
>> first_component
)) - 1;
3784 /* We can't write more than 2 64-bit components at once. Limit the
3785 * length of the write to what we can do and let the next iteration
3789 length
= MIN2(2, length
);
3792 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[2]);
3794 offset_reg
= brw_imm_ud(const_offset
->u32
[0] +
3795 type_size
* first_component
);
3797 offset_reg
= vgrf(glsl_type::uint_type
);
3799 retype(get_nir_src(instr
->src
[2]), BRW_REGISTER_TYPE_UD
),
3800 brw_imm_ud(type_size
* first_component
));
3804 emit_untyped_write(bld
, surf_index
, offset_reg
,
3805 offset(val_reg
, bld
, first_component
* type_slots
),
3806 1 /* dims */, length
* type_slots
,
3807 BRW_PREDICATE_NONE
);
3809 /* Clear the bits in the writemask that we just wrote, then try
3810 * again to see if more channels are left.
3812 writemask
&= (15 << (first_component
+ length
));
3817 case nir_intrinsic_store_output
: {
3818 fs_reg src
= get_nir_src(instr
->src
[0]);
3819 fs_reg new_dest
= offset(retype(nir_outputs
, src
.type
), bld
,
3820 instr
->const_index
[0]);
3822 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[1]);
3823 assert(const_offset
&& "Indirect output stores not allowed");
3824 new_dest
= offset(new_dest
, bld
, const_offset
->u32
[0]);
3826 unsigned num_components
= instr
->num_components
;
3827 unsigned bit_size
= instr
->src
[0].is_ssa
?
3828 instr
->src
[0].ssa
->bit_size
: instr
->src
[0].reg
.reg
->bit_size
;
3829 if (bit_size
== 64) {
3831 fs_reg(VGRF
, alloc
.allocate(2 * num_components
),
3832 BRW_REGISTER_TYPE_F
);
3833 shuffle_64bit_data_for_32bit_write(
3834 bld
, tmp
, retype(src
, BRW_REGISTER_TYPE_DF
), num_components
);
3835 src
= retype(tmp
, src
.type
);
3836 num_components
*= 2;
3839 for (unsigned j
= 0; j
< num_components
; j
++) {
3840 bld
.MOV(offset(new_dest
, bld
, j
), offset(src
, bld
, j
));
3845 case nir_intrinsic_ssbo_atomic_add
:
3846 nir_emit_ssbo_atomic(bld
, BRW_AOP_ADD
, instr
);
3848 case nir_intrinsic_ssbo_atomic_imin
:
3849 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMIN
, instr
);
3851 case nir_intrinsic_ssbo_atomic_umin
:
3852 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMIN
, instr
);
3854 case nir_intrinsic_ssbo_atomic_imax
:
3855 nir_emit_ssbo_atomic(bld
, BRW_AOP_IMAX
, instr
);
3857 case nir_intrinsic_ssbo_atomic_umax
:
3858 nir_emit_ssbo_atomic(bld
, BRW_AOP_UMAX
, instr
);
3860 case nir_intrinsic_ssbo_atomic_and
:
3861 nir_emit_ssbo_atomic(bld
, BRW_AOP_AND
, instr
);
3863 case nir_intrinsic_ssbo_atomic_or
:
3864 nir_emit_ssbo_atomic(bld
, BRW_AOP_OR
, instr
);
3866 case nir_intrinsic_ssbo_atomic_xor
:
3867 nir_emit_ssbo_atomic(bld
, BRW_AOP_XOR
, instr
);
3869 case nir_intrinsic_ssbo_atomic_exchange
:
3870 nir_emit_ssbo_atomic(bld
, BRW_AOP_MOV
, instr
);
3872 case nir_intrinsic_ssbo_atomic_comp_swap
:
3873 nir_emit_ssbo_atomic(bld
, BRW_AOP_CMPWR
, instr
);
3876 case nir_intrinsic_get_buffer_size
: {
3877 nir_const_value
*const_uniform_block
= nir_src_as_const_value(instr
->src
[0]);
3878 unsigned ssbo_index
= const_uniform_block
? const_uniform_block
->u32
[0] : 0;
3879 int reg_width
= dispatch_width
/ 8;
3882 fs_reg source
= brw_imm_d(0);
3884 int mlen
= 1 * reg_width
;
3886 /* A resinfo's sampler message is used to get the buffer size.
3887 * The SIMD8's writeback message consists of four registers and
3888 * SIMD16's writeback message consists of 8 destination registers
3889 * (two per each component), although we are only interested on the
3890 * first component, where resinfo returns the buffer size for
3893 int regs_written
= 4 * mlen
;
3894 fs_reg src_payload
= fs_reg(VGRF
, alloc
.allocate(mlen
),
3895 BRW_REGISTER_TYPE_UD
);
3896 bld
.LOAD_PAYLOAD(src_payload
, &source
, 1, 0);
3897 fs_reg buffer_size
= fs_reg(VGRF
, alloc
.allocate(regs_written
),
3898 BRW_REGISTER_TYPE_UD
);
3899 const unsigned index
= prog_data
->binding_table
.ssbo_start
+ ssbo_index
;
3900 fs_inst
*inst
= bld
.emit(FS_OPCODE_GET_BUFFER_SIZE
, buffer_size
,
3901 src_payload
, brw_imm_ud(index
));
3902 inst
->header_size
= 0;
3904 inst
->regs_written
= regs_written
;
3906 bld
.MOV(retype(dest
, buffer_size
.type
), buffer_size
);
3908 brw_mark_surface_used(prog_data
, index
);
3913 unreachable("unknown intrinsic");
3918 fs_visitor::nir_emit_ssbo_atomic(const fs_builder
&bld
,
3919 int op
, nir_intrinsic_instr
*instr
)
3922 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3923 dest
= get_nir_dest(instr
->dest
);
3926 nir_const_value
*const_surface
= nir_src_as_const_value(instr
->src
[0]);
3927 if (const_surface
) {
3928 unsigned surf_index
= stage_prog_data
->binding_table
.ssbo_start
+
3929 const_surface
->u32
[0];
3930 surface
= brw_imm_ud(surf_index
);
3931 brw_mark_surface_used(prog_data
, surf_index
);
3933 surface
= vgrf(glsl_type::uint_type
);
3934 bld
.ADD(surface
, get_nir_src(instr
->src
[0]),
3935 brw_imm_ud(stage_prog_data
->binding_table
.ssbo_start
));
3937 /* Assume this may touch any SSBO. This is the same we do for other
3938 * UBO/SSBO accesses with non-constant surface.
3940 brw_mark_surface_used(prog_data
,
3941 stage_prog_data
->binding_table
.ssbo_start
+
3942 nir
->info
.num_ssbos
- 1);
3945 fs_reg offset
= get_nir_src(instr
->src
[1]);
3946 fs_reg data1
= get_nir_src(instr
->src
[2]);
3948 if (op
== BRW_AOP_CMPWR
)
3949 data2
= get_nir_src(instr
->src
[3]);
3951 /* Emit the actual atomic operation operation */
3953 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3955 1 /* dims */, 1 /* rsize */,
3957 BRW_PREDICATE_NONE
);
3958 dest
.type
= atomic_result
.type
;
3959 bld
.MOV(dest
, atomic_result
);
3963 fs_visitor::nir_emit_shared_atomic(const fs_builder
&bld
,
3964 int op
, nir_intrinsic_instr
*instr
)
3967 if (nir_intrinsic_infos
[instr
->intrinsic
].has_dest
)
3968 dest
= get_nir_dest(instr
->dest
);
3970 fs_reg surface
= brw_imm_ud(GEN7_BTI_SLM
);
3971 fs_reg offset
= get_nir_src(instr
->src
[0]);
3972 fs_reg data1
= get_nir_src(instr
->src
[1]);
3974 if (op
== BRW_AOP_CMPWR
)
3975 data2
= get_nir_src(instr
->src
[2]);
3977 /* Emit the actual atomic operation operation */
3979 fs_reg atomic_result
= emit_untyped_atomic(bld
, surface
, offset
,
3981 1 /* dims */, 1 /* rsize */,
3983 BRW_PREDICATE_NONE
);
3984 dest
.type
= atomic_result
.type
;
3985 bld
.MOV(dest
, atomic_result
);
3989 fs_visitor::nir_emit_texture(const fs_builder
&bld
, nir_tex_instr
*instr
)
3991 unsigned texture
= instr
->texture_index
;
3992 unsigned sampler
= instr
->sampler_index
;
3994 fs_reg srcs
[TEX_LOGICAL_NUM_SRCS
];
3996 srcs
[TEX_LOGICAL_SRC_SURFACE
] = brw_imm_ud(texture
);
3997 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = brw_imm_ud(sampler
);
3999 int lod_components
= 0;
4001 /* The hardware requires a LOD for buffer textures */
4002 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_BUF
)
4003 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_d(0);
4005 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
4006 fs_reg src
= get_nir_src(instr
->src
[i
].src
);
4007 switch (instr
->src
[i
].src_type
) {
4008 case nir_tex_src_bias
:
4009 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4011 case nir_tex_src_comparitor
:
4012 srcs
[TEX_LOGICAL_SRC_SHADOW_C
] = retype(src
, BRW_REGISTER_TYPE_F
);
4014 case nir_tex_src_coord
:
4015 switch (instr
->op
) {
4017 case nir_texop_txf_ms
:
4018 case nir_texop_txf_ms_mcs
:
4019 case nir_texop_samples_identical
:
4020 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_D
);
4023 srcs
[TEX_LOGICAL_SRC_COORDINATE
] = retype(src
, BRW_REGISTER_TYPE_F
);
4027 case nir_tex_src_ddx
:
4028 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4029 lod_components
= nir_tex_instr_src_size(instr
, i
);
4031 case nir_tex_src_ddy
:
4032 srcs
[TEX_LOGICAL_SRC_LOD2
] = retype(src
, BRW_REGISTER_TYPE_F
);
4034 case nir_tex_src_lod
:
4035 switch (instr
->op
) {
4037 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4040 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_D
);
4043 srcs
[TEX_LOGICAL_SRC_LOD
] = retype(src
, BRW_REGISTER_TYPE_F
);
4047 case nir_tex_src_ms_index
:
4048 srcs
[TEX_LOGICAL_SRC_SAMPLE_INDEX
] = retype(src
, BRW_REGISTER_TYPE_UD
);
4051 case nir_tex_src_offset
: {
4052 nir_const_value
*const_offset
=
4053 nir_src_as_const_value(instr
->src
[i
].src
);
4055 unsigned header_bits
= brw_texture_offset(const_offset
->i32
, 3);
4056 if (header_bits
!= 0)
4057 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] = brw_imm_ud(header_bits
);
4059 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
] =
4060 retype(src
, BRW_REGISTER_TYPE_D
);
4065 case nir_tex_src_projector
:
4066 unreachable("should be lowered");
4068 case nir_tex_src_texture_offset
: {
4069 /* Figure out the highest possible texture index and mark it as used */
4070 uint32_t max_used
= texture
+ instr
->texture_array_size
- 1;
4071 if (instr
->op
== nir_texop_tg4
&& devinfo
->gen
< 8) {
4072 max_used
+= stage_prog_data
->binding_table
.gather_texture_start
;
4074 max_used
+= stage_prog_data
->binding_table
.texture_start
;
4076 brw_mark_surface_used(prog_data
, max_used
);
4078 /* Emit code to evaluate the actual indexing expression */
4079 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4080 bld
.ADD(tmp
, src
, brw_imm_ud(texture
));
4081 srcs
[TEX_LOGICAL_SRC_SURFACE
] = bld
.emit_uniformize(tmp
);
4085 case nir_tex_src_sampler_offset
: {
4086 /* Emit code to evaluate the actual indexing expression */
4087 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4088 bld
.ADD(tmp
, src
, brw_imm_ud(sampler
));
4089 srcs
[TEX_LOGICAL_SRC_SAMPLER
] = bld
.emit_uniformize(tmp
);
4093 case nir_tex_src_ms_mcs
:
4094 assert(instr
->op
== nir_texop_txf_ms
);
4095 srcs
[TEX_LOGICAL_SRC_MCS
] = retype(src
, BRW_REGISTER_TYPE_D
);
4099 unreachable("unknown texture source");
4103 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BAD_FILE
&&
4104 (instr
->op
== nir_texop_txf_ms
||
4105 instr
->op
== nir_texop_samples_identical
)) {
4106 if (devinfo
->gen
>= 7 &&
4107 key_tex
->compressed_multisample_layout_mask
& (1 << texture
)) {
4108 srcs
[TEX_LOGICAL_SRC_MCS
] =
4109 emit_mcs_fetch(srcs
[TEX_LOGICAL_SRC_COORDINATE
],
4110 instr
->coord_components
,
4111 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4113 srcs
[TEX_LOGICAL_SRC_MCS
] = brw_imm_ud(0u);
4117 srcs
[TEX_LOGICAL_SRC_COORD_COMPONENTS
] = brw_imm_d(instr
->coord_components
);
4118 srcs
[TEX_LOGICAL_SRC_GRAD_COMPONENTS
] = brw_imm_d(lod_components
);
4120 if (instr
->op
== nir_texop_query_levels
) {
4121 /* textureQueryLevels() is implemented in terms of TXS so we need to
4122 * pass a valid LOD argument.
4124 assert(srcs
[TEX_LOGICAL_SRC_LOD
].file
== BAD_FILE
);
4125 srcs
[TEX_LOGICAL_SRC_LOD
] = brw_imm_ud(0u);
4129 switch (instr
->op
) {
4131 opcode
= SHADER_OPCODE_TEX_LOGICAL
;
4134 opcode
= FS_OPCODE_TXB_LOGICAL
;
4137 opcode
= SHADER_OPCODE_TXL_LOGICAL
;
4140 opcode
= SHADER_OPCODE_TXD_LOGICAL
;
4143 opcode
= SHADER_OPCODE_TXF_LOGICAL
;
4145 case nir_texop_txf_ms
:
4146 if ((key_tex
->msaa_16
& (1 << sampler
)))
4147 opcode
= SHADER_OPCODE_TXF_CMS_W_LOGICAL
;
4149 opcode
= SHADER_OPCODE_TXF_CMS_LOGICAL
;
4151 case nir_texop_txf_ms_mcs
:
4152 opcode
= SHADER_OPCODE_TXF_MCS_LOGICAL
;
4154 case nir_texop_query_levels
:
4156 opcode
= SHADER_OPCODE_TXS_LOGICAL
;
4159 opcode
= SHADER_OPCODE_LOD_LOGICAL
;
4162 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= BAD_FILE
&&
4163 srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
!= IMM
)
4164 opcode
= SHADER_OPCODE_TG4_OFFSET_LOGICAL
;
4166 opcode
= SHADER_OPCODE_TG4_LOGICAL
;
4168 case nir_texop_texture_samples
: {
4169 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4171 fs_reg tmp
= bld
.vgrf(BRW_REGISTER_TYPE_D
, 4);
4172 fs_inst
*inst
= bld
.emit(SHADER_OPCODE_SAMPLEINFO
, tmp
,
4173 bld
.vgrf(BRW_REGISTER_TYPE_D
, 1),
4174 srcs
[TEX_LOGICAL_SRC_SURFACE
],
4175 srcs
[TEX_LOGICAL_SRC_SURFACE
]);
4177 inst
->header_size
= 1;
4178 inst
->base_mrf
= -1;
4179 inst
->regs_written
= 4 * (dispatch_width
/ 8);
4181 /* Pick off the one component we care about */
4185 case nir_texop_samples_identical
: {
4186 fs_reg dst
= retype(get_nir_dest(instr
->dest
), BRW_REGISTER_TYPE_D
);
4188 /* If mcs is an immediate value, it means there is no MCS. In that case
4189 * just return false.
4191 if (srcs
[TEX_LOGICAL_SRC_MCS
].file
== BRW_IMMEDIATE_VALUE
) {
4192 bld
.MOV(dst
, brw_imm_ud(0u));
4193 } else if ((key_tex
->msaa_16
& (1 << sampler
))) {
4194 fs_reg tmp
= vgrf(glsl_type::uint_type
);
4195 bld
.OR(tmp
, srcs
[TEX_LOGICAL_SRC_MCS
],
4196 offset(srcs
[TEX_LOGICAL_SRC_MCS
], bld
, 1));
4197 bld
.CMP(dst
, tmp
, brw_imm_ud(0u), BRW_CONDITIONAL_EQ
);
4199 bld
.CMP(dst
, srcs
[TEX_LOGICAL_SRC_MCS
], brw_imm_ud(0u),
4200 BRW_CONDITIONAL_EQ
);
4205 unreachable("unknown texture opcode");
4208 fs_reg dst
= bld
.vgrf(brw_type_for_nir_type(instr
->dest_type
), 4);
4209 fs_inst
*inst
= bld
.emit(opcode
, dst
, srcs
, ARRAY_SIZE(srcs
));
4211 const unsigned dest_size
= nir_tex_instr_dest_size(instr
);
4212 if (devinfo
->gen
>= 9 &&
4213 instr
->op
!= nir_texop_tg4
&& instr
->op
!= nir_texop_query_levels
) {
4214 unsigned write_mask
= instr
->dest
.is_ssa
?
4215 nir_ssa_def_components_read(&instr
->dest
.ssa
):
4216 (1 << dest_size
) - 1;
4217 assert(write_mask
!= 0); /* dead code should have been eliminated */
4218 inst
->regs_written
= _mesa_fls(write_mask
) * dispatch_width
/ 8;
4220 inst
->regs_written
= 4 * dispatch_width
/ 8;
4223 if (srcs
[TEX_LOGICAL_SRC_SHADOW_C
].file
!= BAD_FILE
)
4224 inst
->shadow_compare
= true;
4226 if (srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].file
== IMM
)
4227 inst
->offset
= srcs
[TEX_LOGICAL_SRC_OFFSET_VALUE
].ud
;
4229 if (instr
->op
== nir_texop_tg4
) {
4230 if (instr
->component
== 1 &&
4231 key_tex
->gather_channel_quirk_mask
& (1 << texture
)) {
4232 /* gather4 sampler is broken for green channel on RG32F --
4233 * we must ask for blue instead.
4235 inst
->offset
|= 2 << 16;
4237 inst
->offset
|= instr
->component
<< 16;
4240 if (devinfo
->gen
== 6)
4241 emit_gen6_gather_wa(key_tex
->gen6_gather_wa
[texture
], dst
);
4245 for (unsigned i
= 0; i
< dest_size
; i
++)
4246 nir_dest
[i
] = offset(dst
, bld
, i
);
4248 bool is_cube_array
= instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
&&
4251 if (instr
->op
== nir_texop_query_levels
) {
4252 /* # levels is in .w */
4253 nir_dest
[0] = offset(dst
, bld
, 3);
4254 } else if (instr
->op
== nir_texop_txs
&& dest_size
>= 3 &&
4255 (devinfo
->gen
< 7 || is_cube_array
)) {
4256 fs_reg depth
= offset(dst
, bld
, 2);
4257 fs_reg fixed_depth
= vgrf(glsl_type::int_type
);
4259 if (is_cube_array
) {
4260 /* fixup #layers for cube map arrays */
4261 bld
.emit(SHADER_OPCODE_INT_QUOTIENT
, fixed_depth
, depth
, brw_imm_d(6));
4262 } else if (devinfo
->gen
< 7) {
4263 /* Gen4-6 return 0 instead of 1 for single layer surfaces. */
4264 bld
.emit_minmax(fixed_depth
, depth
, brw_imm_d(1), BRW_CONDITIONAL_GE
);
4267 nir_dest
[2] = fixed_depth
;
4270 bld
.LOAD_PAYLOAD(get_nir_dest(instr
->dest
), nir_dest
, dest_size
, 0);
4274 fs_visitor::nir_emit_jump(const fs_builder
&bld
, nir_jump_instr
*instr
)
4276 switch (instr
->type
) {
4277 case nir_jump_break
:
4278 bld
.emit(BRW_OPCODE_BREAK
);
4280 case nir_jump_continue
:
4281 bld
.emit(BRW_OPCODE_CONTINUE
);
4283 case nir_jump_return
:
4285 unreachable("unknown jump");
4290 * This helper takes the result of a load operation that reads 32-bit elements
4298 * and shuffles the data to get this:
4305 * Which is exactly what we want if the load is reading 64-bit components
4306 * like doubles, where x represents the low 32-bit of the x double component
4307 * and y represents the high 32-bit of the x double component (likewise with
4308 * z and w for double component y). The parameter @components represents
4309 * the number of 64-bit components present in @src. This would typically be
4310 * 2 at most, since we can only fit 2 double elements in the result of a
4313 * Notice that @dst and @src can be the same register.
4316 shuffle_32bit_load_result_to_64bit_data(const fs_builder
&bld
,
4319 uint32_t components
)
4321 assert(type_sz(src
.type
) == 4);
4322 assert(type_sz(dst
.type
) == 8);
4324 /* A temporary that we will use to shuffle the 32-bit data of each
4325 * component in the vector into valid 64-bit data. We can't write directly
4326 * to dst because dst can be (and would usually be) the same as src
4327 * and in that case the first MOV in the loop below would overwrite the
4328 * data read in the second MOV.
4330 fs_reg tmp
= bld
.vgrf(dst
.type
);
4332 for (unsigned i
= 0; i
< components
; i
++) {
4333 const fs_reg component_i
= offset(src
, bld
, 2 * i
);
4335 bld
.MOV(subscript(tmp
, src
.type
, 0), component_i
);
4336 bld
.MOV(subscript(tmp
, src
.type
, 1), offset(component_i
, bld
, 1));
4338 bld
.MOV(offset(dst
, bld
, i
), tmp
);
4343 * This helper does the inverse operation of
4344 * SHUFFLE_32BIT_LOAD_RESULT_TO_64BIT_DATA.
4346 * We need to do this when we are going to use untyped write messsages that
4347 * operate with 32-bit components in order to arrange our 64-bit data to be
4348 * in the expected layout.
4350 * Notice that callers of this function, unlike in the case of the inverse
4351 * operation, would typically need to call this with dst and src being
4352 * different registers, since they would otherwise corrupt the original
4353 * 64-bit data they are about to write. Because of this the function checks
4354 * that the src and dst regions involved in the operation do not overlap.
4357 shuffle_64bit_data_for_32bit_write(const fs_builder
&bld
,
4360 uint32_t components
)
4362 assert(type_sz(src
.type
) == 8);
4363 assert(type_sz(dst
.type
) == 4);
4365 assert(!src
.in_range(dst
, 2 * components
* bld
.dispatch_width() / 8));
4367 for (unsigned i
= 0; i
< components
; i
++) {
4368 const fs_reg component_i
= offset(src
, bld
, i
);
4369 bld
.MOV(offset(dst
, bld
, 2 * i
), subscript(component_i
, dst
.type
, 0));
4370 bld
.MOV(offset(dst
, bld
, 2 * i
+ 1), subscript(component_i
, dst
.type
, 1));